Reset PCI pass through devices via PCI-e FLR during VM start and end.
Add routines to trigger a function level reset (FLR) of a PCI-express device via the PCI-express device control register. This also includes support routines to wait for pending transactions to complete as well as calculating the maximum completion timeout permitted by a device. Change the ppt(4) driver to reset pass through devices before attaching to a VM during startup and before detaching from a VM during shutdown. Reviewed by: imp, wblock (earlier version) MFC after: 1 month Sponsored by: Chelsio Communications Differential Revision: https://reviews.freebsd.org/D7751
This commit is contained in:
John Baldwin
parent
b90d9a3752
commit
da0fc9250c
@ -1354,7 +1354,10 @@ MLINKS+=pci.9 pci_alloc_msi.9 \
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pci.9 pci_set_max_read_req.9 \
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pci.9 pci_write_config.9 \
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pci.9 pcie_adjust_config.9 \
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pci.9 pcie_flr.9 \
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pci.9 pcie_max_completion_timeout.9 \
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pci.9 pcie_read_config.9 \
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pci.9 pcie_wait_for_pending_transactions.9 \
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pci.9 pcie_write_config.9
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MLINKS+=pci_iov_schema.9 pci_iov_schema_alloc_node.9 \
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pci_iov_schema.9 pci_iov_schema_add_bool.9 \
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@ -66,7 +66,10 @@
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.Nm pci_set_powerstate ,
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.Nm pci_write_config ,
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.Nm pcie_adjust_config ,
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.Nm pcie_flr ,
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.Nm pcie_get_max_completion_timeout ,
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.Nm pcie_read_config ,
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.Nm pcie_wait_for_pending_transactions ,
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.Nm pcie_write_config
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.Nd PCI bus interface
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.Sh SYNOPSIS
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@ -145,8 +148,14 @@
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.Fa "uint32_t val"
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.Fa "int width"
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.Fc
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.Ft bool
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.Fn pcie_flr "device_t dev" "u_int max_delay" "bool force"
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.Ft int
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.Fn pcie_get_max_completion_timeout "device_t dev"
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.Ft uint32_t
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.Fn pcie_read_config "device_t dev" "int reg" "int width"
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.Ft bool
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.Fn pcie_wait_for_pending_transactions "device_t dev" "u_int max_delay"
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.Ft void
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.Fn pcie_write_config "device_t dev" "int reg" "uint32_t val" "int width"
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.Ft void
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@ -431,6 +440,51 @@ keyword,
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then
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.Fn pci_get_vpd_readonly
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returns an error.
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.Pp
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The
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.Fn pcie_get_max_completion_timeout
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function returns the maximum completion timeout configured for the device
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.Fa dev
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in microseconds.
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If the
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.Fa dev
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device is not a PCI-express device,
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.Fn pcie_get_max_completion_timeout
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returns zero.
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When completion timeouts are disabled for
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.Fa dev ,
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this function returns the maxmimum timeout that would be used if timeouts
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were enabled.
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.Pp
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The
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.Fn pcie_wait_for_pending_transactions
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function waits for any pending transactions initiated by the
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.Fa dev
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device to complete.
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The function checks for pending transactions by polling the transactions
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pending flag in the PCI-express device status register.
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It returns
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.Dv true
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once the transaction pending flag is clear.
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If transactions are still pending after
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.Fa max_delay
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milliseconds,
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.Fn pcie_wait_for_pending_transactions
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returns
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.Dv false .
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If
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.Fa max_delay
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is set to zero,
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.Fn pcie_wait_for_pending_transactions
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performs a single check;
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otherwise,
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this function may sleep while polling the transactions pending flag.
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.Nm pcie_wait_for_pending_transactions
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returns
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.Dv true
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if
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.Fa dev
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is not a PCI-express device.
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.Ss Device Configuration
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The
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.Fn pci_enable_busmaster
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@ -662,6 +716,51 @@ is invoked,
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then the device will be transitioned to
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.Dv PCI_POWERSTATE_D0
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before any config registers are restored.
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.Pp
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The
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.Fn pcie_flr
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function requests a Function Level Reset
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.Pq FLR
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of
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.Fa dev .
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If
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.Fa dev
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is not a PCI-express device or does not support Function Level Resets via
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the PCI-express device control register,
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.Dv false
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is returned.
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Pending transactions are drained by disabling busmastering and calling
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.Fn pcie_wait_for_pending_transactions
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before resetting the device.
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The
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.Fa max_delay
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argument specifies the maximum timeout to wait for pending transactions as
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described for
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.Fn pcie_wait_for_pending_transactions .
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If
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.Fn pcie_wait_for_pending_transactions
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fails with a timeout and
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.Fa force
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is
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.Dv false ,
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busmastering is re-enabled and
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.Dv false
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is returned.
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If
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.Fn pcie_wait_for_pending_transactions
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fails with a timeout and
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.Fa force
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is
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.Dv true ,
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the device is reset despite the timeout.
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After the reset has been requested,
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.Nm pcie_flr
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sleeps for at least 100 milliseconds before returning
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.Dv true .
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Note that
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.Nm pcie_flr
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does not save and restore any state around the reset.
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The caller should save and restore state as needed.
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.Ss Message Signaled Interrupts
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Message Signaled Interrupts
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.Pq MSI
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@ -362,6 +362,11 @@ ppt_assign_device(struct vm *vm, int bus, int slot, int func)
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if (ppt->vm != NULL && ppt->vm != vm)
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return (EBUSY);
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pci_save_state(ppt->dev);
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pcie_flr(ppt->dev,
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max(pcie_get_max_completion_timeout(ppt->dev) / 1000, 10),
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true);
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pci_restore_state(ppt->dev);
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ppt->vm = vm;
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iommu_remove_device(iommu_host_domain(), pci_get_rid(ppt->dev));
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iommu_add_device(vm_iommu_domain(vm), pci_get_rid(ppt->dev));
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@ -382,6 +387,12 @@ ppt_unassign_device(struct vm *vm, int bus, int slot, int func)
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*/
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if (ppt->vm != vm)
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return (EBUSY);
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pci_save_state(ppt->dev);
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pcie_flr(ppt->dev,
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max(pcie_get_max_completion_timeout(ppt->dev) / 1000, 10),
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true);
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pci_restore_state(ppt->dev);
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ppt_unmap_mmio(vm, ppt);
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ppt_teardown_msi(ppt);
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ppt_teardown_msix(ppt);
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@ -5892,3 +5892,165 @@ pci_find_pcie_root_port(device_t dev)
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dev = pcib;
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}
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}
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/*
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* Wait for pending transactions to complete on a PCI-express function.
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*
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* The maximum delay is specified in milliseconds in max_delay. Note
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* that this function may sleep.
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*
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* Returns true if the function is idle and false if the timeout is
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* exceeded. If dev is not a PCI-express function, this returns true.
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*/
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bool
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pcie_wait_for_pending_transactions(device_t dev, u_int max_delay)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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uint16_t sta;
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int cap;
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cap = dinfo->cfg.pcie.pcie_location;
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if (cap == 0)
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return (true);
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sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2);
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while (sta & PCIEM_STA_TRANSACTION_PND) {
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if (max_delay == 0)
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return (false);
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/* Poll once every 100 milliseconds up to the timeout. */
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if (max_delay > 100) {
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pause_sbt("pcietp", 100 * SBT_1MS, 0, C_HARDCLOCK);
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max_delay -= 100;
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} else {
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pause_sbt("pcietp", max_delay * SBT_1MS, 0,
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C_HARDCLOCK);
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max_delay = 0;
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}
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sta = pci_read_config(dev, cap + PCIER_DEVICE_STA, 2);
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}
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return (true);
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}
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/*
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* Determine the maximum Completion Timeout in microseconds.
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*
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* For non-PCI-express functions this returns 0.
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*/
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int
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pcie_get_max_completion_timeout(device_t dev)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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int cap;
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cap = dinfo->cfg.pcie.pcie_location;
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if (cap == 0)
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return (0);
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/*
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* Functions using the 1.x spec use the default timeout range of
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* 50 microseconds to 50 milliseconds. Functions that do not
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* support programmable timeouts also use this range.
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*/
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if ((dinfo->cfg.pcie.pcie_flags & PCIEM_FLAGS_VERSION) < 2 ||
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(pci_read_config(dev, cap + PCIER_DEVICE_CAP2, 4) &
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PCIEM_CAP2_COMP_TIMO_RANGES) == 0)
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return (50 * 1000);
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switch (pci_read_config(dev, cap + PCIER_DEVICE_CTL2, 2) &
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PCIEM_CTL2_COMP_TIMO_VAL) {
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case PCIEM_CTL2_COMP_TIMO_100US:
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return (100);
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case PCIEM_CTL2_COMP_TIMO_10MS:
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return (10 * 1000);
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case PCIEM_CTL2_COMP_TIMO_55MS:
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return (55 * 1000);
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case PCIEM_CTL2_COMP_TIMO_210MS:
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return (210 * 1000);
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case PCIEM_CTL2_COMP_TIMO_900MS:
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return (900 * 1000);
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case PCIEM_CTL2_COMP_TIMO_3500MS:
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return (3500 * 1000);
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case PCIEM_CTL2_COMP_TIMO_13S:
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return (13 * 1000 * 1000);
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case PCIEM_CTL2_COMP_TIMO_64S:
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return (64 * 1000 * 1000);
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default:
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return (50 * 1000);
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}
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}
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/*
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* Perform a Function Level Reset (FLR) on a device.
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*
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* This function first waits for any pending transactions to complete
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* within the timeout specified by max_delay. If transactions are
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* still pending, the function will return false without attempting a
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* reset.
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*
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* If dev is not a PCI-express function or does not support FLR, this
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* function returns false.
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*
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* Note that no registers are saved or restored. The caller is
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* responsible for saving and restoring any registers including
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* PCI-standard registers via pci_save_state() and
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* pci_restore_state().
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*/
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bool
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pcie_flr(device_t dev, u_int max_delay, bool force)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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uint16_t cmd, ctl;
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int compl_delay;
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int cap;
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cap = dinfo->cfg.pcie.pcie_location;
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if (cap == 0)
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return (false);
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if (!(pci_read_config(dev, cap + PCIER_DEVICE_CAP, 4) & PCIEM_CAP_FLR))
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return (false);
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/*
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* Disable busmastering to prevent generation of new
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* transactions while waiting for the device to go idle. If
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* the idle timeout fails, the command register is restored
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* which will re-enable busmastering.
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*/
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cmd = pci_read_config(dev, PCIR_COMMAND, 2);
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pci_write_config(dev, PCIR_COMMAND, cmd & ~(PCIM_CMD_BUSMASTEREN), 2);
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if (!pcie_wait_for_pending_transactions(dev, max_delay)) {
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if (!force) {
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pci_write_config(dev, PCIR_COMMAND, cmd, 2);
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return (false);
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}
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pci_printf(&dinfo->cfg,
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"Resetting with transactions pending after %d ms\n",
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max_delay);
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/*
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* Extend the post-FLR delay to cover the maximum
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* Completion Timeout delay of anything in flight
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* during the FLR delay. Enforce a minimum delay of
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* at least 10ms.
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*/
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compl_delay = pcie_get_max_completion_timeout(dev) / 1000;
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if (compl_delay < 10)
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compl_delay = 10;
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} else
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compl_delay = 0;
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/* Initiate the reset. */
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ctl = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2);
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pci_write_config(dev, cap + PCIER_DEVICE_CTL, ctl |
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PCIEM_CTL_INITIATE_FLR, 2);
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/* Wait for 100ms. */
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pause_sbt("pcieflr", (100 + compl_delay) * SBT_1MS, 0, C_HARDCLOCK);
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if (pci_read_config(dev, cap + PCIER_DEVICE_STA, 2) &
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PCIEM_STA_TRANSACTION_PND)
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pci_printf(&dinfo->cfg, "Transactions pending after FLR!\n");
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return (true);
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}
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@ -885,10 +885,25 @@
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#define PCIEM_ROOT_STA_PME_STATUS 0x00010000
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#define PCIEM_ROOT_STA_PME_PEND 0x00020000
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#define PCIER_DEVICE_CAP2 0x24
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#define PCIEM_CAP2_ARI 0x20
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#define PCIEM_CAP2_COMP_TIMO_RANGES 0x0000000f
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#define PCIEM_CAP2_COMP_TIMO_RANGE_A 0x00000001
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#define PCIEM_CAP2_COMP_TIMO_RANGE_B 0x00000002
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#define PCIEM_CAP2_COMP_TIMO_RANGE_C 0x00000004
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#define PCIEM_CAP2_COMP_TIMO_RANGE_D 0x00000008
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#define PCIEM_CAP2_COMP_TIMO_DISABLE 0x00000010
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#define PCIEM_CAP2_ARI 0x00000020
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#define PCIER_DEVICE_CTL2 0x28
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#define PCIEM_CTL2_COMP_TIMEOUT_VAL 0x000f
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#define PCIEM_CTL2_COMP_TIMEOUT_DIS 0x0010
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#define PCIEM_CTL2_COMP_TIMO_VAL 0x000f
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#define PCIEM_CTL2_COMP_TIMO_50MS 0x0000
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#define PCIEM_CTL2_COMP_TIMO_100US 0x0001
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#define PCIEM_CTL2_COMP_TIMO_10MS 0x0002
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#define PCIEM_CTL2_COMP_TIMO_55MS 0x0005
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#define PCIEM_CTL2_COMP_TIMO_210MS 0x0006
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#define PCIEM_CTL2_COMP_TIMO_900MS 0x0009
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#define PCIEM_CTL2_COMP_TIMO_3500MS 0x000a
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#define PCIEM_CTL2_COMP_TIMO_13S 0x000d
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#define PCIEM_CTL2_COMP_TIMO_64S 0x000e
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#define PCIEM_CTL2_COMP_TIMO_DISABLE 0x0010
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#define PCIEM_CTL2_ARI 0x0020
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#define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040
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#define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080
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@ -595,7 +595,9 @@ uint32_t pcie_read_config(device_t dev, int reg, int width);
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void pcie_write_config(device_t dev, int reg, uint32_t value, int width);
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uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask,
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uint32_t value, int width);
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bool pcie_flr(device_t dev, u_int max_delay, bool force);
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int pcie_get_max_completion_timeout(device_t dev);
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bool pcie_wait_for_pending_transactions(device_t dev, u_int max_delay);
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#ifdef BUS_SPACE_MAXADDR
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#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
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