Fix hwpmc sampling for MPC74xxx (G4) processors.
With this, hwpmc sampling now works correctly on these processors. MFC after: 3 weeks Relnotes: yes
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244d05e746
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@ -578,9 +578,9 @@ mpc7xxx_pcpu_init(struct pmc_mdep *md, int cpu)
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}
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/* Clear the MMCRs, and set FC, to disable all PMCs. */
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/* Clear the MMCRs, and set FC, to disable all PMCs. */
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mtspr(SPR_MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE | SPR_MMCR0_PMC1CE | SPR_MMCR0_PMCNCE);
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mtspr(SPR_MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE |
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SPR_MMCR0_FCECE | SPR_MMCR0_PMC1CE | SPR_MMCR0_PMCNCE);
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mtspr(SPR_MMCR1, 0);
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mtspr(SPR_MMCR1, 0);
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mtmsr(mfmsr() | PSL_PMM);
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return 0;
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return 0;
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}
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}
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@ -667,7 +667,6 @@ mpc7xxx_intr(int cpu, struct trapframe *tf)
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uint32_t config;
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uint32_t config;
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struct pmc *pm;
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struct pmc *pm;
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struct powerpc_cpu *pac;
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struct powerpc_cpu *pac;
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pmc_value_t v;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[powerpc,%d] out of range CPU %d", __LINE__, cpu));
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("[powerpc,%d] out of range CPU %d", __LINE__, cpu));
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@ -679,8 +678,7 @@ mpc7xxx_intr(int cpu, struct trapframe *tf)
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pac = powerpc_pcpu[cpu];
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pac = powerpc_pcpu[cpu];
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config = mfspr(SPR_MMCR0);
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config = mfspr(SPR_MMCR0) & ~SPR_MMCR0_FC;
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mtspr(SPR_MMCR0, config | SPR_MMCR0_FC);
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/*
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/*
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* look for all PMCs that have interrupted:
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* look for all PMCs that have interrupted:
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@ -704,22 +702,22 @@ mpc7xxx_intr(int cpu, struct trapframe *tf)
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if (pm->pm_state != PMC_STATE_RUNNING)
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if (pm->pm_state != PMC_STATE_RUNNING)
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continue;
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continue;
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/* Stop the PMC, reload count. */
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/* Stop the counter if logging fails. */
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v = pm->pm_sc.pm_reloadcount;
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mpc7xxx_pmcn_write(i, v);
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/* Restart the counter if logging succeeded. */
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error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
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error = pmc_process_interrupt(cpu, PMC_HR, pm, tf,
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TRAPF_USERMODE(tf));
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TRAPF_USERMODE(tf));
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if (error != 0)
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if (error != 0)
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mpc7xxx_stop_pmc(cpu, i);
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mpc7xxx_stop_pmc(cpu, i);
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atomic_add_int(retval ? &pmc_stats.pm_intr_processed :
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&pmc_stats.pm_intr_ignored, 1);
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/* reload count. */
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mpc7xxx_write_pmc(cpu, i, pm->pm_sc.pm_reloadcount);
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}
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}
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atomic_add_int(retval ? &pmc_stats.pm_intr_processed :
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&pmc_stats.pm_intr_ignored, 1);
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/* Re-enable PERF exceptions. */
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/* Re-enable PERF exceptions. */
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mtspr(SPR_MMCR0, config | SPR_MMCR0_PMXE);
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if (retval)
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mtspr(SPR_MMCR0, config | SPR_MMCR0_PMXE);
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return (retval);
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return (retval);
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}
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}
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