Connect Xilinx AXI drivers and Cadence Ethernet MAC to the RISC-V build.

Sponsored by:	DARPA, AFRL
This commit is contained in:
br 2019-05-08 16:06:54 +00:00
parent 256e8d266d
commit da99db36d7
2 changed files with 13 additions and 0 deletions

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@ -5,10 +5,13 @@ cddl/dev/dtrace/riscv/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}"
cddl/dev/fbt/riscv/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}"
crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support
crypto/des/des_enc.c optional crypto | ipsec | ipsec_support | netsmb
dev/cadence/if_cgem.c optional cgem
dev/ofw/ofw_cpu.c optional fdt
dev/uart/uart_cpu_fdt.c optional uart fdt
dev/uart/uart_dev_lowrisc.c optional uart_lowrisc
dev/xilinx/axi_quad_spi.c optional xilinx_spi
dev/xilinx/axidma.c optional axidma xdma
dev/xilinx/if_xae.c optional xae
kern/kern_clocksource.c standard
kern/msi_if.m standard
kern/pic_if.m standard

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@ -102,6 +102,16 @@ device uart # Generic UART driver
device uart_lowrisc # lowRISC UART driver
device uart_ns8250 # ns8250-type UART driver
# Ethernet drivers
device miibus # MII bus support
device cgem # Cadence Gigabit Ethernet MAC
device xae # Xilinx AXI Ethernet MAC
# DMA support
device xdma # DMA interface
device axidma # Xilinx AXI DMA Controller
# Uncomment for memory disk
# options MD_ROOT
# options MD_ROOT_SIZE=32768 # 32MB ram disk