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Add some more paranoia to setting HID registers, and update the AIM

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clock routines to work better with SMP. This makes SMP work fully and
stably on an Xserve G5.

Obtained from:	Book-E (clock bits)
This commit is contained in:
Nathan Whitehorn 2009-10-23 21:36:33 +00:00
parent 27acd6ea1f
commit dab90f68ed
3 changed files with 27 additions and 12 deletions
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17
sys/powerpc/aim/clock.c
View File

@ -95,8 +95,7 @@ static struct timecounter decr_timecounter = {
void
decr_intr(struct trapframe *frame)
{
long tick;
int nticks;
int32_t tick, nticks;
/*
* Check whether we are initialized.
@ -112,13 +111,17 @@ decr_intr(struct trapframe *frame)
for (nticks = 0; tick < 0; nticks++)
tick += ticks_per_intr;
mtdec(tick);
if (nticks > 5) printf("BIG NTICKS on CPU %d: %x\n",PCPU_GET(cpuid),nticks);
if (PCPU_GET(cpuid) == 0) {
while (nticks-- > 0)
while (nticks-- > 0) {
if (PCPU_GET(cpuid) == 0)
hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
} else {
while (nticks-- > 0)
else
hardclock_cpu(TRAPF_USERMODE(frame));
statclock(TRAPF_USERMODE(frame));
if (profprocs != 0)
profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
}
}
@ -145,6 +148,8 @@ decr_init(void)
ticks_per_intr = ticks_per_sec / hz;
mtdec(ticks_per_intr);
set_cputicker(mftb, ticks_per_sec, 0);
mtmsr(msr);
}

2
sys/powerpc/aim/machdep.c
View File

@ -885,6 +885,8 @@ cpu_initclocks(void)
{
decr_tc_init();
stathz = hz;
profhz = hz;
}
/*

20
sys/powerpc/aim/mp_cpudep.c
View File

@ -50,7 +50,7 @@ __FBSDID("$FreeBSD$");
void *ap_pcpu;
static register_t bsp_state[8];
static register_t bsp_state[8] __aligned(8);
static void cpudep_save_config(void *dummy);
SYSINIT(cpu_save_config, SI_SUB_CPU, SI_ORDER_ANY, cpudep_save_config, NULL);
@ -184,6 +184,8 @@ cpudep_save_config(void *dummy)
__asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
: "=r" (bsp_state[6]),"=r" (bsp_state[7]) : "K" (SPR_HID5));
powerpc_sync();
break;
case MPC7450:
case MPC7455:
@ -224,17 +226,23 @@ cpudep_ap_setup()
* See Table 2-3, 970MP manual
*/
__asm __volatile("mtasr %0; sync" :: "r"(0));
__asm __volatile(" \
ld %0,0(%2); \
sync; isync; \
mtspr %1, %0; \
mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
mfspr %0, %1; mfspr %0, %1; mfspr %0, %1;"
mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
sync; isync"
: "=r"(reg) : "K"(SPR_HID0), "r"(bsp_state));
__asm __volatile("ld %0, 8(%2); mtspr %1, %0; mtspr %1, %0; \
isync" : "=r"(reg) : "K"(SPR_HID1), "r"(bsp_state));
__asm __volatile("ld %0, 16(%2); sync; mtspr %1, %0; isync;"
__asm __volatile("ld %0, 8(%2); sync; isync; \
mtspr %1, %0; mtspr %1, %0; sync; isync"
: "=r"(reg) : "K"(SPR_HID1), "r"(bsp_state));
__asm __volatile("ld %0, 16(%2); sync; isync; \
mtspr %1, %0; sync; isync;"
: "=r"(reg) : "K"(SPR_HID4), "r"(bsp_state));
__asm __volatile("ld %0, 24(%2); sync; mtspr %1, %0; isync;"
__asm __volatile("ld %0, 24(%2); sync; isync; \
mtspr %1, %0; sync; isync;"
: "=r"(reg) : "K"(SPR_HID5), "r"(bsp_state));
powerpc_sync();