d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support

Browse Source 
Socket 8 to 370 converters.  When (1) CPU_PPRO2CELERON option is
defined, (2) Intel CPU is found and (3) CPU ID is 0x66?, L2 cache is
enabled through MSR 0x11e.  The L2 cache latency value can be
specified by CPU_L2_LATENCY option.  Default value of L2 cache latency
is 5.

These options are useful if you use Socket 8 to Socket 370 converter
(e.g. Power Leap's PL-Pro/II.)  Most PentiumPro BIOSs don't enable L2
cache of Mendocino Celeron CPUs because they don't know Celeron CPUs.
These options are needles if you use a Coppermine (FCPGA) Celeron or
PentiumIII, becuase the L2 cache enable bit is hard wired and L2 cache
is always enabled.
This commit is contained in:
kato 2000-06-13 09:10:37 +00:00
parent 5eb5ab57a6
commit dba64e78dc
7 changed files with 138 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
sys/amd64/amd64/initcpu.c
View File

@ -60,6 +60,7 @@ static void init_6x86(void);
#ifdef I686_CPU
static void init_6x86MX(void);
static void init_ppro(void);
static void init_mendocino(void);
#endif
#ifdef I486_CPU
@ -450,6 +451,47 @@ init_ppro(void)
wrmsr(0x1b, apicbase);
#endif
}
/*
* Initialize BBL_CR_CTL3 (Control register 3: used to configure the
* L2 cache).
*/
void
init_mendocino(void)
{
#ifdef CPU_PPRO2CELERON
u_long eflags;
u_int64_t bbl_cr_ctl3;
eflags = read_eflags();
disable_intr();
load_cr0(rcr0() | CR0_CD | CR0_NW);
wbinvd();
bbl_cr_ctl3 = rdmsr(0x11e);
/* If the L2 cache is configured, do nothing. */
if (!(bbl_cr_ctl3 & 1)) {
bbl_cr_ctl3 = 0x134052bLL;
/* Set L2 Cache Latency (Default: 5). */
#ifdef CPU_CELERON_L2_LATENCY
#if CPU_L2_LATENCY > 15
#error invalid CPU_L2_LATENCY.
#endif
bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
#else
bbl_cr_ctl3 |= 5 << 1;
#endif
wrmsr(0x11e, bbl_cr_ctl3);
}
load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
write_eflags(eflags);
#endif /* CPU_PPRO2CELERON */
}
#endif /* I686_CPU */
void
@ -484,9 +526,16 @@ initializecpu(void)
init_6x86MX();
break;
case CPU_686:
if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
(cpu_id & 0xff0) == 0x610)
init_ppro();
if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
switch (cpu_id & 0xff0) {
case 0x610:
init_ppro();
break;
case 0x660:
init_mendocino();
break;
}
}
break;
#endif
default:

10
sys/conf/NOTES
View File

@ -181,10 +181,18 @@ cpu I686_CPU # aka Pentium Pro(tm)
# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
# (no clock delay).
#
# CPU_L2_LATENCY specifed the L2 cache latency value. This option is used
# only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected.
# The default value is 5.
#
# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination
# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE
# 1).
#
# CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs. This option
# is useful when you use Socket 8 to Socket 370 converter, because most Pentium
# Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs.
#
# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).
#
# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU
@ -228,7 +236,9 @@ options CPU_DISABLE_5X86_LSSER
options CPU_FASTER_5X86_FPU
options CPU_I486_ON_386
options CPU_IORT
options CPU_L2_LATENCY=5
options CPU_LOOP_EN
options CPU_PPRO2CELERON
options CPU_RSTK_EN
options CPU_SUSP_HLT
options CPU_WT_ALLOC

2
sys/conf/options.i386
View File

@ -51,7 +51,9 @@ CPU_DISABLE_5X86_LSSER opt_cpu.h
CPU_FASTER_5X86_FPU opt_cpu.h
CPU_I486_ON_386 opt_cpu.h
CPU_IORT opt_cpu.h
CPU_L2_LATENCY opt_cpu.h
CPU_LOOP_EN opt_cpu.h
CPU_PPRO2CELERON opt_cpu.h
CPU_RSTK_EN opt_cpu.h
CPU_SUSP_HLT opt_cpu.h
CPU_UPGRADE_HW_CACHE opt_cpu.h

2
sys/conf/options.pc98
View File

@ -50,7 +50,9 @@ CPU_DISABLE_5X86_LSSER opt_cpu.h
CPU_FASTER_5X86_FPU opt_cpu.h
CPU_I486_ON_386 opt_cpu.h
CPU_IORT opt_cpu.h
CPU_L2_LATENCY opt_cpu.h
CPU_LOOP_EN opt_cpu.h
CPU_PPRO2CELERON opt_cpu.h
CPU_RSTK_EN opt_cpu.h
CPU_SUSP_HLT opt_cpu.h
CPU_UPGRADE_HW_CACHE opt_cpu.h

10
sys/i386/conf/LINT
View File

@ -181,10 +181,18 @@ cpu I686_CPU # aka Pentium Pro(tm)
# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
# (no clock delay).
#
# CPU_L2_LATENCY specifed the L2 cache latency value. This option is used
# only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected.
# The default value is 5.
#
# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination
# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE
# 1).
#
# CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs. This option
# is useful when you use Socket 8 to Socket 370 converter, because most Pentium
# Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs.
#
# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).
#
# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU
@ -228,7 +236,9 @@ options CPU_DISABLE_5X86_LSSER
options CPU_FASTER_5X86_FPU
options CPU_I486_ON_386
options CPU_IORT
options CPU_L2_LATENCY=5
options CPU_LOOP_EN
options CPU_PPRO2CELERON
options CPU_RSTK_EN
options CPU_SUSP_HLT
options CPU_WT_ALLOC

10
sys/i386/conf/NOTES
View File

@ -181,10 +181,18 @@ cpu I686_CPU # aka Pentium Pro(tm)
# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
# (no clock delay).
#
# CPU_L2_LATENCY specifed the L2 cache latency value. This option is used
# only when CPU_PPRO2CELERON is defined and Mendocino Celeron is detected.
# The default value is 5.
#
# CPU_LOOP_EN prevents flushing the prefetch buffer if the destination
# of a jump is already present in the prefetch buffer on Cyrix 5x86(NOTE
# 1).
#
# CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs. This option
# is useful when you use Socket 8 to Socket 370 converter, because most Pentium
# Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs.
#
# CPU_RSTK_EN enables return stack on Cyrix 5x86 (NOTE 1).
#
# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU
@ -228,7 +236,9 @@ options CPU_DISABLE_5X86_LSSER
options CPU_FASTER_5X86_FPU
options CPU_I486_ON_386
options CPU_IORT
options CPU_L2_LATENCY=5
options CPU_LOOP_EN
options CPU_PPRO2CELERON
options CPU_RSTK_EN
options CPU_SUSP_HLT
options CPU_WT_ALLOC

55
sys/i386/i386/initcpu.c
View File

@ -60,6 +60,7 @@ static void init_6x86(void);
#ifdef I686_CPU
static void init_6x86MX(void);
static void init_ppro(void);
static void init_mendocino(void);
#endif
#ifdef I486_CPU
@ -450,6 +451,47 @@ init_ppro(void)
wrmsr(0x1b, apicbase);
#endif
}
/*
* Initialize BBL_CR_CTL3 (Control register 3: used to configure the
* L2 cache).
*/
void
init_mendocino(void)
{
#ifdef CPU_PPRO2CELERON
u_long eflags;
u_int64_t bbl_cr_ctl3;
eflags = read_eflags();
disable_intr();
load_cr0(rcr0() | CR0_CD | CR0_NW);
wbinvd();
bbl_cr_ctl3 = rdmsr(0x11e);
/* If the L2 cache is configured, do nothing. */
if (!(bbl_cr_ctl3 & 1)) {
bbl_cr_ctl3 = 0x134052bLL;
/* Set L2 Cache Latency (Default: 5). */
#ifdef CPU_CELERON_L2_LATENCY
#if CPU_L2_LATENCY > 15
#error invalid CPU_L2_LATENCY.
#endif
bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
#else
bbl_cr_ctl3 |= 5 << 1;
#endif
wrmsr(0x11e, bbl_cr_ctl3);
}
load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
write_eflags(eflags);
#endif /* CPU_PPRO2CELERON */
}
#endif /* I686_CPU */
void
@ -484,9 +526,16 @@ initializecpu(void)
init_6x86MX();
break;
case CPU_686:
if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
(cpu_id & 0xff0) == 0x610)
init_ppro();
if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
switch (cpu_id & 0xff0) {
case 0x610:
init_ppro();
break;
case 0x660:
init_mendocino();
break;
}
}
break;
#endif
default: