Merge some style and minor changes from NetBSD:
- ncr53c9x.c: 1.108: Remove unreachable break after return and goto statements. 1.109: avoid strong words; use 'screw' instead 1.110: Fix some typos. From Tom Cosgrove via jmc@openbsd. 1.114: nuke trailing whitespace 1.107 was already merged, 1.112 and 1.113 are not relevant for FreeBSD. 1.111 is a functional change and will be merged later. - ncr53c9xreg.h: 1.12: DMA, not dma nor Dma. 1.13: Fix some typos. From Tom Cosgrove via jmc@openbsd. 1.14: nuke trailing whitespace - ncr53c9xvar.h: 1.43: Fix some typos. From Tom Cosgrove via jmc@openbsd. 1.44: Constify. 1.42 and 1.46 were already merged, 1.45 is not relevant for FreeBSD.
This commit is contained in:
marius
parent
44c82d73e2
commit
dc4a70aca9
@ -25,7 +25,7 @@
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*
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*/
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/* $NetBSD: ncr53c9x.c,v 1.106 2003/04/16 18:53:50 petrov Exp $ */
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/* $NetBSD: ncr53c9x.c,v 1.110 2003/11/02 11:07:45 wiz Exp $ */
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/*-
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* Copyright (c) 1998, 2002 The NetBSD Foundation, Inc.
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@ -185,7 +185,7 @@ static __inline void ncr53c9x_setsync(struct ncr53c9x_softc *,
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#endif
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/*
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* Names for the NCR53c9x variants, correspnding to the variant tags
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* Names for the NCR53c9x variants, corresponding to the variant tags
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* in ncr53c9xvar.h.
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*/
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static const char *ncr53c9x_variant_names[] = {
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@ -334,7 +334,7 @@ ncr53c9x_attach(struct ncr53c9x_softc *sc)
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TAILQ_INIT(&sc->free_list);
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if ((sc->ecb_array = malloc(sizeof(struct ncr53c9x_ecb) * NCR_TAG_DEPTH,
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M_DEVBUF, M_NOWAIT|M_ZERO)) == NULL) {
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device_printf(sc->sc_dev, "Cannot allocate ecb array!\n");
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device_printf(sc->sc_dev, "cannot allocate ECB array\n");
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return (ENOMEM);
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}
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for (i = 0; i < NCR_TAG_DEPTH; i++) {
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@ -558,7 +558,7 @@ ncr53c9x_readregs(struct ncr53c9x_softc *sc)
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/* Only the stepo bits are of interest */
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sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK;
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if (sc->sc_rev == NCR_VARIANT_FAS366)
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if (sc->sc_rev == NCR_VARIANT_FAS366)
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sc->sc_espstat2 = NCR_READ_REG(sc, NCR_STAT2);
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sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR);
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@ -1064,7 +1064,7 @@ ncr53c9x_poll(struct cam_sim *sim)
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/*
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* Schedule a scsi operation. This has now been pulled out of the interrupt
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* handler so that we may call it from ncr53c9x_scsipi_request and
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* ncr53c9x_done. This may save us an unecessary interrupt just to get
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* ncr53c9x_done. This may save us an unnecessary interrupt just to get
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* things going. Should only be called when state == NCR_IDLE and at bio pl.
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*/
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static void
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@ -1849,7 +1849,7 @@ ncr53c9x_msgin(struct ncr53c9x_softc *sc)
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case NCR_IDENTIFIED:
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/*
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* IDENTIFY message was received and queue tag is expected now
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*/
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*/
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if ((sc->sc_imess[0] != MSG_SIMPLE_Q_TAG) ||
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(sc->sc_msgify == 0)) {
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device_printf(sc->sc_dev, "TAG reselect without "
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@ -2031,15 +2031,15 @@ ncr53c9x_msgout(struct ncr53c9x_softc *sc)
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#ifdef DEBUG
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if (ncr53c9x_debug & NCR_SHOWMSGS) {
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int i;
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NCR_MSGS(("<msgout:"));
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for (i = 0; i < sc->sc_omlen; i++)
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for (i = 0; i < sc->sc_omlen; i++)
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NCR_MSGS((" %02x", sc->sc_omess[i]));
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NCR_MSGS(("> "));
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}
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#endif
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if (sc->sc_rev == NCR_VARIANT_FAS366) {
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/*
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/*
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* XXX fifo size
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*/
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ncr53c9x_flushfifo(sc);
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@ -2369,7 +2369,7 @@ ncr53c9x_intr(void *arg)
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if (sc->sc_phase != MESSAGE_IN_PHASE) {
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int i = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF);
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/*
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* Things are seriously fucked up.
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* Things are seriously screwed up.
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* Pull the brakes, i.e. reset
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*/
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device_printf(sc->sc_dev, "target didn't send tag: %d "
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@ -2383,8 +2383,6 @@ ncr53c9x_intr(void *arg)
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} else
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goto msgin;
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break;
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case NCR_IDLE:
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case NCR_SELECTING:
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ecb = sc->sc_nexus;
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@ -2408,7 +2406,7 @@ ncr53c9x_intr(void *arg)
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sc->sc_state = NCR_RESELECTED;
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if (sc->sc_phase != MESSAGE_IN_PHASE) {
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/*
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* Things are seriously fucked up.
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* Things are seriously screwed up.
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* Pull the brakes, i.e. reset
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*/
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device_printf(sc->sc_dev, "target didn't "
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@ -2682,7 +2680,7 @@ ncr53c9x_intr(void *arg)
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}
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sc->sc_flags &= ~NCR_WAITI;
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ncr53c9x_rdfifo(sc,
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(sc->sc_prevphase == sc->sc_phase) ?
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(sc->sc_prevphase == sc->sc_phase) ?
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NCR_RDFIFO_CONTINUE : NCR_RDFIFO_START);
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ncr53c9x_msgin(sc);
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} else {
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@ -2692,7 +2690,6 @@ ncr53c9x_intr(void *arg)
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}
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sc->sc_prevphase = MESSAGE_IN_PHASE;
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goto shortcut; /* i.e. expect data to be ready */
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break;
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case COMMAND_PHASE:
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/*
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@ -2775,7 +2772,6 @@ ncr53c9x_intr(void *arg)
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NCRCMD(sc, NCRCMD_ICCS);
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sc->sc_prevphase = STATUS_PHASE;
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goto shortcut; /* i.e. expect status results soon */
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break;
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case INVALID_PHASE:
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break;
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@ -1,4 +1,4 @@
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/* $NetBSD: ncr53c9xreg.h,v 1.11 2003/02/21 17:14:05 tsutsui Exp $ */
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/* $NetBSD: ncr53c9xreg.h,v 1.14 2005/02/27 00:27:02 perry Exp $ */
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/*-
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* Copyright (c) 1994 Peter Galbavy. All rights reserved.
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@ -42,7 +42,7 @@
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#define NCR_FIFO 0x02 /* RW - FIFO data */
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#define NCR_CMD 0x03 /* RW - Command (2 deep) */
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#define NCR_CMD 0x03 /* RW - Command (2 deep) */
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#define NCRCMD_DMA 0x80 /* DMA Bit */
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#define NCRCMD_NOP 0x00 /* No Operation */
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#define NCRCMD_FLUSH 0x01 /* Flush FIFO */
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@ -75,7 +75,7 @@
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#define NCRCMD_SETATN 0x1a /* Set ATN */
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#define NCRCMD_RSTATN 0x1b /* Reset ATN */
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#define NCR_STAT 0x04 /* RO - Status */
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#define NCR_STAT 0x04 /* RO - Status */
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#define NCRSTAT_INT 0x80 /* Interrupt */
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#define NCRSTAT_GE 0x40 /* Gross Error */
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#define NCRSTAT_PE 0x20 /* Parity Error */
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@ -83,11 +83,11 @@
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#define NCRSTAT_VGC 0x08 /* Valid Group Code */
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#define NCRSTAT_PHASE 0x07 /* Phase bits */
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#define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */
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#define NCR_SELID 0x04 /* WO - Select/Reselect Bus ID */
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#define NCR_BUSID_HME 0x10 /* XXX HME reselect ID */
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#define NCR_BUSID_HME32 0x40 /* XXX HME to select more than 16 */
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#define NCR_INTR 0x05 /* RO - Interrupt */
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#define NCR_INTR 0x05 /* RO - Interrupt */
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#define NCRINTR_SBR 0x80 /* SCSI Bus Reset */
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#define NCRINTR_ILL 0x40 /* Illegal Command */
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#define NCRINTR_DIS 0x20 /* Disconnect */
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@ -97,16 +97,16 @@
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#define NCRINTR_SELATN 0x02 /* Select with ATN */
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#define NCRINTR_SEL 0x01 /* Selected */
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#define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */
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#define NCR_TIMEOUT 0x05 /* WO - Select/Reselect Timeout */
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#define NCR_STEP 0x06 /* RO - Sequence Step */
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#define NCR_STEP 0x06 /* RO - Sequence Step */
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#define NCRSTEP_MASK 0x07 /* the last 3 bits */
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#define NCRSTEP_DONE 0x04 /* command went out */
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#define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */
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#define NCR_SYNCTP 0x06 /* WO - Synch Transfer Period */
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/* Default 5 (53C9X) */
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#define NCR_FFLAG 0x07 /* RO - FIFO Flags */
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#define NCR_FFLAG 0x07 /* RO - FIFO Flags */
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#define NCRFIFO_SS 0xe0 /* Sequence Step (Dup) */
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#define NCRFIFO_FF 0x1f /* Bytes in FIFO */
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@ -114,7 +114,7 @@
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/* 0 = ASYNC */
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/* 1 - 15 = SYNC bytes */
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#define NCR_CFG1 0x08 /* RW - Configuration #1 */
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#define NCR_CFG1 0x08 /* RW - Configuration #1 */
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#define NCRCFG1_SLOW 0x80 /* Slow Cable Mode */
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#define NCRCFG1_SRR 0x40 /* SCSI Reset Rep Int Dis */
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#define NCRCFG1_PTEST 0x20 /* Parity Test Mod */
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@ -122,7 +122,7 @@
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#define NCRCFG1_CTEST 0x08 /* Enable Chip Test */
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#define NCRCFG1_BUSID 0x07 /* Bus ID */
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#define NCR_CCF 0x09 /* WO - Clock Conversion Factor */
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#define NCR_CCF 0x09 /* WO - Clock Conversion Factor */
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/* 0 = 35.01 - 40MHz */
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/* NEVER SET TO 1 */
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/* 2 = 10MHz */
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@ -132,9 +132,9 @@
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/* 6 = 25.01 - 30MHz */
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/* 7 = 30.01 - 35MHz */
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#define NCR_TEST 0x0a /* WO - Test (Chip Test Only) */
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#define NCR_TEST 0x0a /* WO - Test (Chip Test Only) */
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#define NCR_CFG2 0x0b /* RW - Configuration #2 */
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#define NCR_CFG2 0x0b /* RW - Configuration #2 */
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#define NCRCFG2_RSVD 0xa0 /* reserved */
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#define NCRCFG2_FE 0x40 /* Features Enable */
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#define NCRCFG2_DREQ 0x10 /* DREQ High Impedance */
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@ -147,7 +147,7 @@
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#define NCRCFG2_HME32 0x80 /* HME 32 extended */
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/* Config #3 only on 53C9X */
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#define NCR_CFG3 0x0c /* RW - Configuration #3 */
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#define NCR_CFG3 0x0c /* RW - Configuration #3 */
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#define NCRCFG3_RSVD 0xe0 /* reserved */
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#define NCRCFG3_IDM 0x10 /* ID Message Res Check */
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#define NCRCFG3_QTE 0x08 /* Queue Tag Enable */
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@ -163,7 +163,7 @@
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*/
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/* Config #3 different on ESP406/FAS408 */
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#define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */
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#define NCR_ESPCFG3 0x0c /* RW - Configuration #3 */
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#define NCRESPCFG3_IDM 0x80 /* ID Message Res Check */
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#define NCRESPCFG3_QTE 0x40 /* Queue Tag Enable */
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#define NCRESPCFG3_CDB 0x20 /* CDB 10-bytes OK */
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@ -174,7 +174,7 @@
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#define NCRESPCFG3_T8M 0x01 /* Threshold 8 Mode */
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/* Config #3 also different on NCR53CF9x/FAS216 */
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#define NCR_F9XCFG3 0x0c /* RW - Configuration #3 */
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#define NCR_F9XCFG3 0x0c /* RW - Configuration #3 */
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#define NCRF9XCFG3_IDM 0x80 /* ID Message Res Check */
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#define NCRF9XCFG3_QTE 0x40 /* Queue Tag Enable */
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#define NCRF9XCFG3_CDB 0x20 /* CDB 10-bytes OK */
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@ -195,7 +195,7 @@
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#define NCRFASCFG3_FASTCLK 0x01 /* fast clock mode */
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/* Config #4 only on ESP406/FAS408 */
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#define NCR_CFG4 0x0d /* RW - Configuration #4 */
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#define NCR_CFG4 0x0d /* RW - Configuration #4 */
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#define NCRCFG4_CRS1 0x80 /* Select register set #1 */
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#define NCRCFG4_RSVD 0x7b /* reserved */
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#define NCRCFG4_ACTNEG 0x04 /* Active negation */
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@ -203,11 +203,11 @@
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/*
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The following registers are only on the ESP406/FAS408. The
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documentation refers to them as "Control Register Set #1".
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These are the registers that are visible when bit 7 of
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These are the registers that are visible when bit 7 of
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register 0x0d is set. This bit is common to both register sets.
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*/
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#define NCR_JMP 0x00 /* RO - Jumper Sense Register */
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#define NCR_JMP 0x00 /* RO - Jumper Sense Register */
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#define NCRJMP_RSVD 0xc0 /* reserved */
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#define NCRJMP_ROMSZ 0x20 /* ROM Size 1=16K, 0=32K */
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#define NCRJMP_J4 0x10 /* Jumper #4 */
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@ -216,9 +216,9 @@
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#define NCRJMP_J1 0x02 /* Jumper #1 */
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#define NCRJMP_J0 0x01 /* Jumper #0 */
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#define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */
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#define NCR_PIOFIFO 0x04 /* WO - PIO FIFO, 4 bytes deep */
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#define NCR_PSTAT 0x08 /* RW - PIO Status Register */
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#define NCR_PSTAT 0x08 /* RW - PIO Status Register */
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#define NCRPSTAT_PERR 0x80 /* PIO Error */
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#define NCRPSTAT_SIRQ 0x40 /* Active High of SCSI IRQ */
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#define NCRPSTAT_ATAI 0x20 /* ATA IRQ */
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@ -228,7 +228,7 @@
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#define NCRPSTAT_FFULL 0x02 /* PIO FIFO Full */
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#define NCRPSTAT_PIOM 0x01 /* PIO/DMA Mode */
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#define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */
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#define NCR_PIOI 0x0b /* RW - PIO Interrupt Enable */
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#define NCRPIOI_RSVD 0xe0 /* reserved */
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#define NCRPIOI_EMPTY 0x10 /* IRQ When Empty */
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#define NCRPIOI_13 0x08 /* IRQ When 1/3 */
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@ -236,20 +236,20 @@
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#define NCRPIOI_FULL 0x02 /* IRQ When Full */
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#define NCRPIOI_FINV 0x01 /* Flag Invert */
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#define NCR_CFG5 0x0d /* RW - Configuration #5 */
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#define NCR_CFG5 0x0d /* RW - Configuration #5 */
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#define NCRCFG5_CRS1 0x80 /* Select Register Set #1 */
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#define NCRCFG5_SRAM 0x40 /* SRAM Memory Map */
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#define NCRCFG5_AADDR 0x20 /* Auto Address */
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#define NCRCFG5_PTRINC 0x10 /* Pointer Increment */
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#define NCRCFG5_LOWPWR 0x08 /* Low Power Mode */
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#define NCRCFG5_SINT 0x04 /* SCSI Interupt Enable */
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#define NCRCFG5_SINT 0x04 /* SCSI Interrupt Enable */
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#define NCRCFG5_INTP 0x02 /* INT Polarity */
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#define NCRCFG5_AINT 0x01 /* ATA Interupt Enable */
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#define NCRCFG5_AINT 0x01 /* ATA Interrupt Enable */
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#define NCR_SIGNTR 0x0e /* RO - Signature */
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#define NCR_SIGNTR 0x0e /* RO - Signature */
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/* Am53c974 Config #3 */
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#define NCR_AMDCFG3 0x0c /* RW - Configuration #3 */
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#define NCR_AMDCFG3 0x0c /* RW - Configuration #3 */
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#define NCRAMDCFG3_IDM 0x80 /* ID Message Res Check */
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#define NCRAMDCFG3_QTE 0x40 /* Queue Tag Enable */
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#define NCRAMDCFG3_CDB 0x20 /* CDB 10-bytes OK */
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@ -258,7 +258,7 @@
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#define NCRAMDCFG3_RSVD 0x07 /* Reserved */
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/* Am53c974 Config #4 */
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#define NCR_AMDCFG4 0x0d /* RW - Configuration #4 */
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#define NCR_AMDCFG4 0x0d /* RW - Configuration #4 */
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#define NCRAMDCFG4_GE 0xc0 /* Glitch Eater */
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#define NCRAMDCFG4_GE12NS 0x00 /* Signal window 12ns */
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#define NCRAMDCFG4_GE25NS 0x80 /* Signal window 25ns */
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@ -271,20 +271,20 @@
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/*
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* FAS366
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*/
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#define NCR_RCL NCR_TCH /* Recommand counter low */
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#define NCR_RCH 0xf /* Recommand counter high */
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#define NCR_UID NCR_RCL /* fas366 part-uniq id */
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*/
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#define NCR_RCL NCR_TCH /* Recommand counter low */
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#define NCR_RCH 0xf /* Recommand counter high */
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#define NCR_UID NCR_RCL /* fas366 part-uniq id */
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/* status register #2 definitions (read only) */
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#define NCR_STAT2 NCR_CCF
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#define NCRFAS_STAT2_SEQCNT 0x01 /* Sequence counter bit 7-3 enabled */
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#define NCRFAS_STAT2_FLATCHED 0x02 /* FIFO flags register latched */
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#define NCRFAS_STAT2_CLATCHED 0x04 /* Xfer cntr & recommand ctr latched */
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#define NCRFAS_STAT2_CACTIVE 0x08 /* Command register is active */
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#define NCRFAS_STAT2_SCSI16 0x10 /* SCSI interface is wide */
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#define NCRFAS_STAT2_ISHUTTLE 0x20 /* FIFO Top register contains 1 byte */
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#define NCRFAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */
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#define NCRFAS_STAT2_EMPTY 0x80 /* FIFO is empty */
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#define NCR_STAT2 NCR_CCF
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#define NCRFAS_STAT2_SEQCNT 0x01 /* Sequence counter bit 7-3 enabled */
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#define NCRFAS_STAT2_FLATCHED 0x02 /* FIFO flags register latched */
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#define NCRFAS_STAT2_CLATCHED 0x04 /* Xfer cntr & recommand ctr latched */
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#define NCRFAS_STAT2_CACTIVE 0x08 /* Command register is active */
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#define NCRFAS_STAT2_SCSI16 0x10 /* SCSI interface is wide */
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#define NCRFAS_STAT2_ISHUTTLE 0x20 /* FIFO Top register contains 1 byte */
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#define NCRFAS_STAT2_OSHUTTLE 0x40 /* next byte from FIFO is MSB */
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#define NCRFAS_STAT2_EMPTY 0x80 /* FIFO is empty */
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@ -1,4 +1,4 @@
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/* $NetBSD: ncr53c9xvar.h,v 1.41 2003/02/04 20:05:11 pk Exp $ */
|
||||
/* $NetBSD: ncr53c9xvar.h,v 1.46 2005/02/04 02:10:36 perry Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 The NetBSD Foundation, Inc.
|
||||
@ -285,7 +285,7 @@ struct ncr53c9x_softc {
|
||||
struct cam_path *sc_path; /* our scsi channel */
|
||||
struct callout sc_watchdog; /* periodic timer */
|
||||
|
||||
struct ncr53c9x_glue *sc_glue; /* glue to MD code */
|
||||
const struct ncr53c9x_glue *sc_glue; /* glue to MD code */
|
||||
|
||||
int sc_cfflags; /* Copy of config flags */
|
||||
|
||||
@ -453,7 +453,7 @@ struct ncr53c9x_softc {
|
||||
|
||||
/*
|
||||
* Macro to convert the chip register Clock Per Byte value to
|
||||
* Sunchronous Transfer Period.
|
||||
* Synchronous Transfer Period.
|
||||
*/
|
||||
#define ncr53c9x_cpb2stp(sc, cpb) \
|
||||
((250 * (cpb)) / (sc)->sc_freq)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user