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Use the bus_*() routines rather than bus_space_*() for register operations.

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This commit is contained in:
John Baldwin 2009-11-17 18:22:14 +00:00
parent 77e6010f24
commit dc8ecaacd4
9 changed files with 27 additions and 60 deletions
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2
sys/dev/sn/if_sn.c
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@ -1220,8 +1220,6 @@ sn_activate(device_t dev)
sn_deactivate(dev);
return ENOMEM;
}
sc->bst = rman_get_bustag(sc->port_res);
sc->bsh = rman_get_bushandle(sc->port_res);
return (0);
}

2
sys/dev/sn/if_sn_pccard.c
View File

@ -271,8 +271,6 @@ sn_pccard_megahertz_activate(device_t dev)
sn_deactivate(dev);
return ENOMEM;
}
sc->bst = rman_get_bustag(sc->port_res);
sc->bsh = rman_get_bushandle(sc->port_res);
return 0;
}

18
sys/dev/sn/if_snvar.h
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@ -32,8 +32,6 @@
struct sn_softc {
struct ifnet *ifp;
bus_space_tag_t bst;
bus_space_handle_t bsh;
struct mtx sc_mtx;
int pages_wanted; /* Size of outstanding MMU ALLOC */
int intr_mask; /* Most recently set interrupt mask */
@ -55,20 +53,20 @@ void sn_intr(void *);
int sn_activate(device_t);
void sn_deactivate(device_t);
#define CSR_READ_1(sc, off) (bus_space_read_1((sc)->bst, (sc)->bsh, off))
#define CSR_READ_2(sc, off) (bus_space_read_2((sc)->bst, (sc)->bsh, off))
#define CSR_READ_1(sc, off) (bus_read_1((sc)->port_res, off))
#define CSR_READ_2(sc, off) (bus_read_2((sc)->port_res, off))
#define CSR_WRITE_1(sc, off, val) \
bus_space_write_1(sc->bst, sc->bsh, off, val)
bus_write_1((sc)->port_res, off, val)
#define CSR_WRITE_2(sc, off, val) \
bus_space_write_2(sc->bst, sc->bsh, off, val)
bus_write_2((sc)->port_res, off, val)
#define CSR_WRITE_MULTI_1(sc, off, addr, count) \
bus_space_write_multi_1(sc->bst, sc->bsh, off, addr, count)
bus_write_multi_1((sc)->port_res, off, addr, count)
#define CSR_WRITE_MULTI_2(sc, off, addr, count) \
bus_space_write_multi_2(sc->bst, sc->bsh, off, addr, count)
bus_write_multi_2((sc)->port_res, off, addr, count)
#define CSR_READ_MULTI_1(sc, off, addr, count) \
bus_space_read_multi_1(sc->bst, sc->bsh, off, addr, count)
bus_read_multi_1((sc)->port_res, off, addr, count)
#define CSR_READ_MULTI_2(sc, off, addr, count) \
bus_space_read_multi_2(sc->bst, sc->bsh, off, addr, count)
bus_read_multi_2((sc)->port_res, off, addr, count)
#define SN_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
#define SN_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)

3
sys/dev/tl/if_tl.c
View File

@ -1170,9 +1170,6 @@ tl_attach(dev)
goto fail;
}
sc->tl_btag = rman_get_bustag(sc->tl_res);
sc->tl_bhandle = rman_get_bushandle(sc->tl_res);
#ifdef notdef
/*
* The ThunderLAN manual suggests jacking the PCI latency

20
sys/dev/tl/if_tlreg.h
View File

@ -112,8 +112,6 @@ struct tl_softc {
struct ifnet *tl_ifp;
device_t tl_dev;
struct ifmedia ifmedia; /* media info */
bus_space_handle_t tl_bhandle;
bus_space_tag_t tl_btag;
void *tl_intrhand;
struct resource *tl_irq;
struct resource *tl_res;
@ -493,19 +491,13 @@ struct tl_stats {
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val)
#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->tl_res, reg, val)
#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->tl_res, reg, val)
#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->tl_res, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->tl_btag, sc->tl_bhandle, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->tl_btag, sc->tl_bhandle, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->tl_btag, sc->tl_bhandle, reg)
#define CSR_READ_4(sc, reg) bus_read_4(sc->tl_res, reg)
#define CSR_READ_2(sc, reg) bus_read_2(sc->tl_res, reg)
#define CSR_READ_1(sc, reg) bus_read_1(sc->tl_res, reg)
#define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x)
#define CMD_SET(sc, x) \

3
sys/dev/vge/if_vge.c
View File

@ -945,9 +945,6 @@ vge_attach(dev)
goto fail;
}
sc->vge_btag = rman_get_bustag(sc->vge_res);
sc->vge_bhandle = rman_get_bushandle(sc->vge_res);
/* Allocate interrupt */
rid = 0;
sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,

16
sys/dev/vge/if_vgevar.h
View File

@ -100,8 +100,6 @@ struct vge_list_data {
struct vge_softc {
struct ifnet *vge_ifp; /* interface info */
device_t vge_dev;
bus_space_handle_t vge_bhandle; /* bus space handle */
bus_space_tag_t vge_btag; /* bus space tag */
struct resource *vge_res;
struct resource *vge_irq;
void *vge_intrhand;
@ -134,20 +132,20 @@ struct vge_softc {
* register space access macros
*/
#define CSR_WRITE_STREAM_4(sc, reg, val) \
bus_space_write_stream_4(sc->vge_btag, sc->vge_bhandle, reg, val)
bus_write_stream_4(sc->vge_res, reg, val)
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->vge_btag, sc->vge_bhandle, reg, val)
bus_write_4(sc->vge_res, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->vge_btag, sc->vge_bhandle, reg, val)
bus_write_2(sc->vge_res, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->vge_btag, sc->vge_bhandle, reg, val)
bus_write_1(sc->vge_res, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->vge_btag, sc->vge_bhandle, reg)
bus_read_4(sc->vge_res, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->vge_btag, sc->vge_bhandle, reg)
bus_read_2(sc->vge_res, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->vge_btag, sc->vge_bhandle, reg)
bus_read_1(sc->vge_res, reg)
#define CSR_SETBIT_1(sc, reg, x) \
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))

3
sys/dev/wb/if_wb.c
View File

@ -804,9 +804,6 @@ wb_attach(dev)
goto fail;
}
sc->wb_btag = rman_get_bustag(sc->wb_res);
sc->wb_bhandle = rman_get_bushandle(sc->wb_res);
/* Allocate interrupt */
rid = 0;
sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,

20
sys/dev/wb/if_wbreg.h
View File

@ -365,8 +365,6 @@ struct wb_softc {
struct ifnet *wb_ifp; /* interface info */
device_t wb_dev;
device_t wb_miibus;
bus_space_handle_t wb_bhandle;
bus_space_tag_t wb_btag;
struct resource *wb_res;
struct resource *wb_irq;
void *wb_intrhand;
@ -388,19 +386,13 @@ struct wb_softc {
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->wb_btag, sc->wb_bhandle, reg, val)
#define CSR_WRITE_2(sc, reg, val) \
bus_space_write_2(sc->wb_btag, sc->wb_bhandle, reg, val)
#define CSR_WRITE_1(sc, reg, val) \
bus_space_write_1(sc->wb_btag, sc->wb_bhandle, reg, val)
#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->wb_res, reg, val)
#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->wb_res, reg, val)
#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->wb_res, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->wb_btag, sc->wb_bhandle, reg)
#define CSR_READ_2(sc, reg) \
bus_space_read_2(sc->wb_btag, sc->wb_bhandle, reg)
#define CSR_READ_1(sc, reg) \
bus_space_read_1(sc->wb_btag, sc->wb_bhandle, reg)
#define CSR_READ_4(sc, reg) bus_read_4(sc->wb_res, reg)
#define CSR_READ_2(sc, reg) bus_read_2(sc->wb_res, reg)
#define CSR_READ_1(sc, reg) bus_read_1(sc->wb_res, reg)
#define WB_TIMEOUT 1000