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Enumerate and print Intel CPU features for Speculative Execution Side

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Channel Mitigations.

The definitions are taken from the document 336996-001.

Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
This commit is contained in:
kib 2018-01-14 12:36:23 +00:00
parent 1d4c150060
commit dcd37bb111
3 changed files with 50 additions and 2 deletions
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21
sys/x86/include/specialreg.h
View File

@ -422,6 +422,17 @@
#define CPUID_STDEXT2_RDPID 0x00400000
#define CPUID_STDEXT2_SGXLC 0x40000000
/*
* CPUID instruction 7 Structured Extended Features, leaf 0 edx info
*/
#define CPUID_STDEXT3_IBPB 0x04000000
#define CPUID_STDEXT3_STIBP 0x08000000
#define CPUID_STDEXT3_ARCH_CAP 0x20000000
/* MSR IA32_ARCH_CAP(ABILITIES) bits */
#define IA32_ARCH_CAP_RDCL_NO 0x00000001
#define IA32_ARCH_CAP_IBRS_ALL 0x00000002
/*
* CPUID manufacturers identifiers
*/
@ -450,6 +461,8 @@
#define MSR_EBL_CR_POWERON 0x02a
#define MSR_TEST_CTL 0x033
#define MSR_IA32_FEATURE_CONTROL 0x03a
#define MSR_IA32_SPEC_CTRL 0x048
#define MSR_IA32_PRED_CMD 0x049
#define MSR_BIOS_UPDT_TRIG 0x079
#define MSR_BBL_CR_D0 0x088
#define MSR_BBL_CR_D1 0x089
@ -462,6 +475,7 @@
#define MSR_APERF 0x0e8
#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
#define MSR_MTRRcap 0x0fe
#define MSR_IA32_ARCH_CAP 0x10a
#define MSR_BBL_CR_ADDR 0x116
#define MSR_BBL_CR_DECC 0x118
#define MSR_BBL_CR_CTL 0x119
@ -683,6 +697,13 @@
#define IA32_MISC_EN_xTPRD 0x0000000000800000ULL
#define IA32_MISC_EN_XDD 0x0000000400000000ULL
/* MSR IA32_SPEC_CTRL */
#define IA32_SPEC_CTRL_IBRS 0x0000000000000001ULL
#define IA32_SPEC_CTRL_STIBP 0x0000000000000002ULL
/* MSR IA32_PRED_CMD */
#define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
/*
* PAT modes.
*/

2
sys/x86/include/x86_var.h
View File

@ -52,6 +52,8 @@ extern u_int via_feature_xcrypt;
extern u_int cpu_clflush_line_size;
extern u_int cpu_stdext_feature;
extern u_int cpu_stdext_feature2;
extern u_int cpu_stdext_feature3;
extern uint64_t cpu_ia32_arch_caps;
extern u_int cpu_fxsr;
extern u_int cpu_high;
extern u_int cpu_id;

29
sys/x86/x86/identcpu.c
View File

@ -106,8 +106,10 @@ u_int cpu_vendor_id; /* CPU vendor ID */
u_int cpu_fxsr; /* SSE enabled */
u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */
u_int cpu_clflush_line_size = 32;
u_int cpu_stdext_feature;
u_int cpu_stdext_feature2;
u_int cpu_stdext_feature; /* %ebx */
u_int cpu_stdext_feature2; /* %ecx */
u_int cpu_stdext_feature3; /* %edx */
uint64_t cpu_ia32_arch_caps;
u_int cpu_max_ext_state_size;
u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */
u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */
@ -981,6 +983,16 @@ printcpuinfo(void)
);
}
if (cpu_stdext_feature3 != 0) {
printf("\n Structured Extended Features3=0x%b",
cpu_stdext_feature3,
"\020"
"\033IBPB"
"\034STIBP"
"\036ARCH_CAP"
);
}
if ((cpu_feature2 & CPUID2_XSAVE) != 0) {
cpuid_count(0xd, 0x1, regs);
if (regs[0] != 0) {
@ -994,6 +1006,15 @@ printcpuinfo(void)
}
}
if (cpu_ia32_arch_caps != 0) {
printf("\n IA32_ARCH_CAPS=0x%b",
(u_int)cpu_ia32_arch_caps,
"\020"
"\001RDCL_NO"
"\002IBRS_ALL"
);
}
if (amd_extended_feature_extensions != 0) {
printf("\n "
"AMD Extended Feature Extensions ID EBX="
@ -1424,6 +1445,10 @@ identify_cpu2(void)
cpu_stdext_feature &= ~cpu_stdext_disable;
cpu_stdext_feature2 = regs[2];
cpu_stdext_feature3 = regs[3];
if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0)
cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP);
}
}