Import from rebasing repo at b78b6b80
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@ -19,6 +19,9 @@ to deliver its interrupts via SPIs.
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- clock-frequency : The frequency of the main counter, in Hz. Optional.
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- always-on : a boolean property. If present, the timer is powered through an
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always-on power domain, therefore it never loses context.
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Example:
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timer {
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@ -86,3 +86,9 @@ Interrupt controllers:
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compatible = "arm,versatile-sic";
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interrupt-controller;
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#interrupt-cells = <1>;
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Required nodes:
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- core-module: the root node to the Versatile platforms must have
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a core-module with regs and the compatible strings
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"arm,core-module-versatile", "syscon"
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@ -1,20 +1,21 @@
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Power Management Service Unit(PMSU)
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-----------------------------------
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Available on Marvell SOCs: Armada 370 and Armada XP
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Available on Marvell SOCs: Armada 370, Armada 38x and Armada XP
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Required properties:
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- compatible: "marvell,armada-370-xp-pmsu"
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- compatible: should be one of:
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- "marvell,armada-370-pmsu" for Armada 370 or Armada XP
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- "marvell,armada-380-pmsu" for Armada 38x
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- "marvell,armada-370-xp-pmsu" was used for Armada 370/XP but is now
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deprecated and will be removed
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- reg: Should contain PMSU registers location and length. First pair
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for the per-CPU SW Reset Control registers, second pair for the
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Power Management Service Unit.
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- reg: Should contain PMSU registers location and length.
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Example:
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armada-370-xp-pmsu@d0022000 {
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compatible = "marvell,armada-370-xp-pmsu";
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reg = <0xd0022100 0x430>,
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<0xd0020800 0x20>;
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armada-370-xp-pmsu@22000 {
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compatible = "marvell,armada-370-pmsu";
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reg = <0x22000 0x1000>;
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};
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@ -1,7 +1,10 @@
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* Power Management Controller (PMC)
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Required properties:
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- compatible: Should be "atmel,at91rm9200-pmc"
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- compatible: Should be "atmel,<chip>-pmc".
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<chip> can be: at91rm9200, at91sam9260, at91sam9g45, at91sam9n12,
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at91sam9x5, sama5d3
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- reg: Should contain PMC registers location and length
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Examples:
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@ -1,16 +1,33 @@
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Coherency fabric
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----------------
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Available on Marvell SOCs: Armada 370 and Armada XP
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Available on Marvell SOCs: Armada 370, Armada 375, Armada 38x and Armada XP
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Required properties:
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- compatible: "marvell,coherency-fabric"
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- compatible: the possible values are:
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* "marvell,coherency-fabric", to be used for the coherency fabric of
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the Armada 370 and Armada XP.
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* "marvell,armada-375-coherency-fabric", for the Armada 375 coherency
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fabric.
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* "marvell,armada-380-coherency-fabric", for the Armada 38x coherency
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fabric.
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- reg: Should contain coherency fabric registers location and
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length. First pair for the coherency fabric registers, second pair
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for the per-CPU fabric registers registers.
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length.
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Example:
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* For "marvell,coherency-fabric", the first pair for the coherency
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fabric registers, second pair for the per-CPU fabric registers.
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* For "marvell,armada-375-coherency-fabric", only one pair is needed
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for the per-CPU fabric registers.
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* For "marvell,armada-380-coherency-fabric", only one pair is needed
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for the per-CPU fabric registers.
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Examples:
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coherency-fabric@d0020200 {
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compatible = "marvell,coherency-fabric";
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@ -19,3 +36,8 @@ coherency-fabric@d0020200 {
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};
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coherency-fabric@21810 {
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compatible = "marvell,armada-375-coherency-fabric";
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reg = <0x21810 0x1c>;
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};
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@ -152,7 +152,9 @@ nodes to be present and contain the properties described below.
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"arm,cortex-a7"
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"arm,cortex-a8"
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"arm,cortex-a9"
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"arm,cortex-a12"
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"arm,cortex-a15"
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"arm,cortex-a17"
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"arm,cortex-a53"
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"arm,cortex-a57"
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"arm,cortex-m0"
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@ -163,6 +165,7 @@ nodes to be present and contain the properties described below.
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"arm,cortex-r4"
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"arm,cortex-r5"
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"arm,cortex-r7"
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"brcm,brahma-b15"
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"faraday,fa526"
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"intel,sa110"
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"intel,sa1100"
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@ -178,9 +181,20 @@ nodes to be present and contain the properties described below.
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Usage and definition depend on ARM architecture version.
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# On ARM v8 64-bit this property is required and must
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be one of:
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"spin-table"
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"psci"
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# On ARM 32-bit systems this property is optional.
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"spin-table"
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# On ARM 32-bit systems this property is optional and
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can be one of:
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"allwinner,sun6i-a31"
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"arm,psci"
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"brcm,brahma-b15"
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"marvell,armada-375-smp"
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"marvell,armada-380-smp"
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"marvell,armada-xp-smp"
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"qcom,gcc-msm8660"
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"qcom,kpss-acc-v1"
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"qcom,kpss-acc-v2"
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"rockchip,rk3066-smp"
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- cpu-release-addr
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Usage: required for systems that have an "enable-method"
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@ -191,6 +205,21 @@ nodes to be present and contain the properties described below.
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property identifying a 64-bit zero-initialised
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memory location.
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- qcom,saw
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Usage: required for systems that have an "enable-method"
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property value of "qcom,kpss-acc-v1" or
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"qcom,kpss-acc-v2"
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Value type: <phandle>
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Definition: Specifies the SAW[1] node associated with this CPU.
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- qcom,acc
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Usage: required for systems that have an "enable-method"
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property value of "qcom,kpss-acc-v1" or
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"qcom,kpss-acc-v2"
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Value type: <phandle>
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Definition: Specifies the ACC[2] node associated with this CPU.
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Example 1 (dual-cluster big.LITTLE system 32-bit):
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cpus {
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@ -382,3 +411,7 @@ cpus {
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cpu-release-addr = <0 0x20000000>;
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};
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};
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--
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[1] arm/msm/qcom,saw2.txt
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[2] arm/msm/qcom,kpss-acc.txt
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@ -9,6 +9,18 @@ Required Properties:
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- reg: physical base address of the controller and length of memory mapped
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region.
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Optional Properties:
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- clocks: List of clock handles. The parent clocks of the input clocks to the
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devices in this power domain are set to oscclk before power gating
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and restored back after powering on a domain. This is required for
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all domains which are powered on and off and not required for unused
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domains.
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- clock-names: The following clocks can be specified:
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- oscclk: Oscillator clock.
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- pclkN, clkN: Pairs of parent of input clock and input clock to the
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devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
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are supported currently.
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Node of a device using power domains must have a samsung,power-domain property
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defined with a phandle to respective power domain.
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@ -19,6 +31,14 @@ Example:
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reg = <0x10023C00 0x10>;
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};
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mfc_pd: power-domain@10044060 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044060 0x20>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
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<&clock CLK_MOUT_USER_ACLK333>;
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clock-names = "oscclk", "pclk0", "clk0";
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};
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Example of the node using power domain:
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node {
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@ -16,6 +16,7 @@ Main node required properties:
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"arm,cortex-a9-gic"
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"arm,cortex-a7-gic"
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"arm,arm11mp-gic"
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"brcm,brahma-b15-gic"
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The type shall be a <u32> and the value shall be 3.
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@ -50,6 +51,11 @@ Optional
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regions, used when the GIC doesn't have banked registers. The offset is
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cpu-offset * cpu-nr.
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- arm,routable-irqs : Total number of gic irq inputs which are not directly
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connected from the peripherals, but are routed dynamically
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by a crossbar/multiplexer preceding the GIC. The GIC irq
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input line is assigned dynamically when the corresponding
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peripheral's crossbar line is mapped.
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Example:
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intc: interrupt-controller@fff11000 {
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@ -57,6 +63,7 @@ Example:
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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arm,routable-irqs = <160>;
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reg = <0xfff11000 0x1000>,
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<0xfff10100 0x100>;
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};
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@ -4,8 +4,11 @@
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** Timer node required properties:
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- compatible : Should be "arm,cortex-a9-global-timer"
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Driver supports versions r2p0 and above.
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- compatible : should contain
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* "arm,cortex-a5-global-timer" for Cortex-A5 global timers.
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* "arm,cortex-a9-global-timer" for Cortex-A9 global
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timers or any compatible implementation. Note: driver
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supports versions r2p0 and above.
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- interrupts : One interrupt to each core
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@ -30,3 +30,28 @@ Example:
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resume-offset = <0x308>;
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reboot-offset = <0x4>;
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};
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-----------------------------------------------------------------------
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Hisilicon CPU controller
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Required properties:
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- compatible : "hisilicon,cpuctrl"
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- reg : Register address and size
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The clock registers and power registers of secondary cores are defined
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in CPU controller, especially in HIX5HD2 SoC.
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-----------------------------------------------------------------------
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PCTRL: Peripheral misc control register
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Required Properties:
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- compatible: "hisilicon,pctrl"
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- reg: Address and size of pctrl.
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Example:
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/* for Hi3620 */
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pctrl: pctrl@fca09000 {
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compatible = "hisilicon,pctrl";
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reg = <0xfca09000 0x1000>;
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};
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@ -8,3 +8,13 @@ Required properties:
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- compatible: All TI specific devices present in Keystone SOC should be in
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the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
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type UART should use the specified compatible for those devices.
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Boards:
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- Keystone 2 Hawking/Kepler EVM
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compatible = "ti,k2hk-evm","ti,keystone"
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- Keystone 2 Lamarr EVM
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compatible = "ti,k2l-evm","ti,keystone"
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- Keystone 2 Edison EVM
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compatible = "ti,k2e-evm","ti,keystone"
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@ -40,6 +40,9 @@ Optional properties:
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- arm,filter-ranges : <start length> Starting address and length of window to
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filter. Addresses in the filter window are directed to the M1 port. Other
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addresses will go to the M0 port.
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- arm,io-coherent : indicates that the system is operating in an hardware
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I/O coherent mode. Valid only when the arm,pl310-cache compatible
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string is used.
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- interrupts : 1 combined interrupt.
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- cache-id-part: cache id part number to be used if it is not present
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on hardware
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@ -12,6 +12,7 @@ SoC and board used. Currently known SoC compatibles are:
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"marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
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"marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
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"marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
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"marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
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"marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
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* Example:
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@ -22,3 +23,120 @@ SoC and board used. Currently known SoC compatibles are:
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...
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}
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* Marvell Berlin CPU control bindings
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CPU control register allows various operations on CPUs, like resetting them
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independently.
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Required properties:
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- compatible: should be "marvell,berlin-cpu-ctrl"
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- reg: address and length of the register set
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Example:
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cpu-ctrl@f7dd0000 {
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compatible = "marvell,berlin-cpu-ctrl";
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reg = <0xf7dd0000 0x10000>;
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};
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* Marvell Berlin2 chip control binding
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Marvell Berlin SoCs have a chip control register set providing several
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individual registers dealing with pinmux, padmux, clock, reset, and secondary
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CPU boot address. Unfortunately, the individual registers are spread among the
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chip control registers, so there should be a single DT node only providing the
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different functions which are described below.
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Required properties:
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- compatible: shall be one of
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"marvell,berlin2-chip-ctrl" for BG2
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"marvell,berlin2cd-chip-ctrl" for BG2CD
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"marvell,berlin2q-chip-ctrl" for BG2Q
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- reg: address and length of following register sets for
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BG2/BG2CD: chip control register set
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BG2Q: chip control register set and cpu pll registers
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* Marvell Berlin2 system control binding
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Marvell Berlin SoCs have a system control register set providing several
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individual registers dealing with pinmux, padmux, and reset.
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Required properties:
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- compatible: should be one of
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"marvell,berlin2-system-ctrl" for BG2
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"marvell,berlin2cd-system-ctrl" for BG2CD
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"marvell,berlin2q-system-ctrl" for BG2Q
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- reg: address and length of the system control register set
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* Clock provider binding
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As clock related registers are spread among the chip control registers, the
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chip control node also provides the clocks. Marvell Berlin2 (BG2, BG2CD, BG2Q)
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SoCs share the same IP for PLLs and clocks, with some minor differences in
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features and register layout.
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Required properties:
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- #clock-cells: shall be set to 1
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- clocks: clock specifiers referencing the core clock input clocks
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- clock-names: array of strings describing the input clock specifiers above.
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Allowed clock-names for the reference clocks are
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"refclk" for the SoCs osciallator input on all SoCs,
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and SoC-specific input clocks for
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BG2/BG2CD: "video_ext0" for the external video clock input
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Clocks provided by core clocks shall be referenced by a clock specifier
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indexing one of the provided clocks. Refer to dt-bindings/clock/berlin<soc>.h
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for the corresponding index mapping.
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* Pin controller binding
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Pin control registers are part of both register sets, chip control and system
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control. The pins controlled are organized in groups, so no actual pin
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information is needed.
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A pin-controller node should contain subnodes representing the pin group
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configurations, one per function. Each subnode has the group name and the muxing
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function used.
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Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is called
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a 'function' in the pin-controller subsystem.
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Required subnode-properties:
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- groups: a list of strings describing the group names.
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- function: a string describing the function used to mux the groups.
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Example:
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chip: chip-control@ea0000 {
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compatible = "marvell,berlin2-chip-ctrl";
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#clock-cells = <1>;
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reg = <0xea0000 0x400>;
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clocks = <&refclk>, <&externaldev 0>;
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clock-names = "refclk", "video_ext0";
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spi1_pmux: spi1-pmux {
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groups = "G0";
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function = "spi1";
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};
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};
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sysctrl: system-controller@d000 {
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compatible = "marvell,berlin2-system-ctrl";
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reg = <0xd000 0x100>;
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uart0_pmux: uart0-pmux {
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groups = "GSM4";
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function = "uart0";
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};
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uart1_pmux: uart1-pmux {
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groups = "GSM5";
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function = "uart1";
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};
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uart2_pmux: uart2-pmux {
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groups = "GSM3";
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function = "uart2";
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};
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};
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@ -1,12 +1,13 @@
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MVEBU System Controller
|
||||
-----------------------
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MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x)
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MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x)
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Required properties:
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- compatible: one of:
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- "marvell,orion-system-controller"
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- "marvell,armada-370-xp-system-controller"
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- "marvell,armada-375-system-controller"
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- reg: Should contain system controller registers location and length.
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||||
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Example:
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@ -6,6 +6,8 @@ provided by Arteris.
|
||||
Required properties:
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||||
- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
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Should be "ti,omap4-l3-noc" for OMAP4 family
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Should be "ti,dra7-l3-noc" for DRA7 family
|
||||
Should be "ti,am4372-l3-noc" for AM43 family
|
||||
- reg: Contains L3 register address range for each noc domain.
|
||||
- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
|
||||
|
||||
|
||||
@ -80,7 +80,10 @@ SoCs:
|
||||
compatible = "ti,omap5432", "ti,omap5"
|
||||
|
||||
- DRA742
|
||||
compatible = "ti,dra7xx", "ti,dra7"
|
||||
compatible = "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- DRA722
|
||||
compatible = "ti,dra722", "ti,dra72", "ti,dra7"
|
||||
|
||||
- AM4372
|
||||
compatible = "ti,am4372", "ti,am43"
|
||||
@ -99,6 +102,15 @@ Boards:
|
||||
- OMAP4 PandaBoard : Low cost community board
|
||||
compatible = "ti,omap4-panda", "ti,omap4430"
|
||||
|
||||
- OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board
|
||||
compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
|
||||
|
||||
- OMAP4 VAR-STK-OM44 : Commercial dev kit with VAR-OM44CustomBoard and VAR-SOM-OM44 w/WLAN
|
||||
compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
|
||||
|
||||
- OMAP4 VAR-DVK-OM44 : Commercial dev kit with VAR-OM44CustomBoard, VAR-SOM-OM44 w/WLAN and LCD touchscreen
|
||||
compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
|
||||
|
||||
- OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x
|
||||
compatible = "ti,omap3-evm", "ti,omap3"
|
||||
|
||||
@ -114,5 +126,14 @@ Boards:
|
||||
- AM43x EPOS EVM
|
||||
compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
|
||||
|
||||
- DRA7 EVM: Software Developement Board for DRA7XX
|
||||
compatible = "ti,dra7-evm", "ti,dra7"
|
||||
- AM437x GP EVM
|
||||
compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
|
||||
|
||||
- AM437x SK EVM: AM437x StarterKit Evaluation Module
|
||||
compatible = "ti,am437x-sk-evm", "ti,am4372", "ti,am43"
|
||||
|
||||
- DRA742 EVM: Software Development Board for DRA742
|
||||
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- DRA722 EVM: Software Development Board for DRA722
|
||||
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"
|
||||
|
||||
@ -8,7 +8,9 @@ Required properties:
|
||||
|
||||
- compatible : should be one of
|
||||
"arm,armv8-pmuv3"
|
||||
"arm,cortex-a17-pmu"
|
||||
"arm,cortex-a15-pmu"
|
||||
"arm,cortex-a12-pmu"
|
||||
"arm,cortex-a9-pmu"
|
||||
"arm,cortex-a8-pmu"
|
||||
"arm,cortex-a7-pmu"
|
||||
@ -16,7 +18,14 @@ Required properties:
|
||||
"arm,arm11mpcore-pmu"
|
||||
"arm,arm1176-pmu"
|
||||
"arm,arm1136-pmu"
|
||||
- interrupts : 1 combined interrupt or 1 per core.
|
||||
"qcom,krait-pmu"
|
||||
- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
|
||||
interrupt (PPI) then 1 interrupt should be specified.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
|
||||
events.
|
||||
|
||||
Example:
|
||||
|
||||
|
||||
@ -21,7 +21,15 @@ to #0.
|
||||
|
||||
Main node required properties:
|
||||
|
||||
- compatible : Must be "arm,psci"
|
||||
- compatible : should contain at least one of:
|
||||
|
||||
* "arm,psci" : for implementations complying to PSCI versions prior to
|
||||
0.2. For these cases function IDs must be provided.
|
||||
|
||||
* "arm,psci-0.2" : for implementations complying to PSCI 0.2. Function
|
||||
IDs are not required and should be ignored by an OS with PSCI 0.2
|
||||
support, but are permitted to be present for compatibility with
|
||||
existing software when "arm,psci" is later in the compatible list.
|
||||
|
||||
- method : The method of calling the PSCI firmware. Permitted
|
||||
values are:
|
||||
@ -45,6 +53,8 @@ Main node optional properties:
|
||||
|
||||
Example:
|
||||
|
||||
Case 1: PSCI v0.1 only.
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci";
|
||||
method = "smc";
|
||||
@ -53,3 +63,28 @@ Example:
|
||||
cpu_on = <0x95c10002>;
|
||||
migrate = <0x95c10003>;
|
||||
};
|
||||
|
||||
|
||||
Case 2: PSCI v0.2 only
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
Case 3: PSCI v0.2 and PSCI v0.1.
|
||||
|
||||
A DTB may provide IDs for use by kernels without PSCI 0.2 support,
|
||||
enabling firmware and hypervisors to support existing and new kernels.
|
||||
These IDs will be ignored by kernels with PSCI 0.2 support, which will
|
||||
use the standard PSCI 0.2 IDs exclusively.
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2", "arm,psci";
|
||||
method = "hvc";
|
||||
|
||||
cpu_on = < arbitrary value >;
|
||||
cpu_off = < arbitrary value >;
|
||||
|
||||
...
|
||||
};
|
||||
|
||||
@ -14,14 +14,21 @@ Required properties:
|
||||
for exynos4412/5250 controllers.
|
||||
Must be "samsung,exynos-adc-v2" for
|
||||
future controllers.
|
||||
Must be "samsung,exynos3250-adc" for
|
||||
controllers compatible with ADC of Exynos3250.
|
||||
- reg: Contains ADC register address range (base address and
|
||||
length) and the address of the phy enable register.
|
||||
- interrupts: Contains the interrupt information for the timer. The
|
||||
format is being dependent on which interrupt controller
|
||||
the Samsung device uses.
|
||||
- #io-channel-cells = <1>; As ADC has multiple outputs
|
||||
- clocks From common clock binding: handle to adc clock.
|
||||
- clock-names From common clock binding: Shall be "adc".
|
||||
- clocks From common clock bindings: handles to clocks specified
|
||||
in "clock-names" property, in the same order.
|
||||
- clock-names From common clock bindings: list of clock input names
|
||||
used by ADC block:
|
||||
- "adc" : ADC bus clock
|
||||
- "sclk" : ADC special clock (only for Exynos3250 and
|
||||
compatible ADC block)
|
||||
- vdd-supply VDD input supply.
|
||||
|
||||
Note: child nodes can be added for auto probing from device tree.
|
||||
@ -41,6 +48,20 @@ adc: adc@12D10000 {
|
||||
vdd-supply = <&buck5_reg>;
|
||||
};
|
||||
|
||||
Example: adding device info in dtsi file for Exynos3250 with additional sclk
|
||||
|
||||
adc: adc@126C0000 {
|
||||
compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
|
||||
reg = <0x126C0000 0x100>, <0x10020718 0x4>;
|
||||
interrupts = <0 137 0>;
|
||||
#io-channel-cells = <1>;
|
||||
io-channel-ranges;
|
||||
|
||||
clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
|
||||
clock-names = "adc", "sclk";
|
||||
|
||||
vdd-supply = <&buck5_reg>;
|
||||
};
|
||||
|
||||
Example: Adding child nodes in dts file
|
||||
|
||||
@ -48,7 +69,7 @@ adc@12D10000 {
|
||||
|
||||
/* NTC thermistor is a hwmon device */
|
||||
ncp15wb473@0 {
|
||||
compatible = "ntc,ncp15wb473";
|
||||
compatible = "murata,ncp15wb473";
|
||||
pullup-uv = <1800000>;
|
||||
pullup-ohm = <47000>;
|
||||
pulldown-ohm = <0>;
|
||||
|
||||
@ -1,8 +1,10 @@
|
||||
SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
|
||||
|
||||
Properties:
|
||||
- compatible : should contain "samsung,<chip name>-sysreg", "syscon";
|
||||
For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon";
|
||||
- compatible : should contain two values. First value must be one from following list:
|
||||
- "samsung,exynos4-sysreg" - for Exynos4 based SoCs,
|
||||
- "samsung,exynos5-sysreg" - for Exynos5 based SoCs.
|
||||
second value must be always "syscon".
|
||||
- reg : offset and length of the register set.
|
||||
|
||||
Example:
|
||||
@ -10,3 +12,8 @@ Example:
|
||||
compatible = "samsung,exynos4-sysreg", "syscon";
|
||||
reg = <0x10010000 0x400>;
|
||||
};
|
||||
|
||||
syscon@10050000 {
|
||||
compatible = "samsung,exynos5-sysreg", "syscon";
|
||||
reg = <0x10050000 0x5000>;
|
||||
};
|
||||
|
||||
@ -30,6 +30,8 @@ board-specific compatible values:
|
||||
nvidia,seaboard
|
||||
nvidia,ventana
|
||||
nvidia,whistler
|
||||
toradex,apalis_t30
|
||||
toradex,apalis_t30-eval
|
||||
toradex,colibri_t20-512
|
||||
toradex,iris
|
||||
|
||||
|
||||
@ -75,9 +75,10 @@ The cpu-map node can only contain three types of child nodes:
|
||||
|
||||
whose bindings are described in paragraph 3.
|
||||
|
||||
The nodes describing the CPU topology (cluster/core/thread) can only be
|
||||
defined within the cpu-map node.
|
||||
Any other configuration is consider invalid and therefore must be ignored.
|
||||
The nodes describing the CPU topology (cluster/core/thread) can only
|
||||
be defined within the cpu-map node and every core/thread in the system
|
||||
must be defined within the topology. Any other configuration is
|
||||
invalid and therefore must be ignored.
|
||||
|
||||
===========================================
|
||||
2.1 - cpu-map child nodes naming convention
|
||||
|
||||
@ -8,6 +8,8 @@ interrupt generation, MMC and NOR Flash control etc.
|
||||
Required node properties:
|
||||
- compatible value : = "arm,vexpress,sysreg";
|
||||
- reg : physical base address and the size of the registers window
|
||||
|
||||
Deprecated properties, replaced by GPIO subnodes (see below):
|
||||
- gpio-controller : specifies that the node is a GPIO controller
|
||||
- #gpio-cells : size of the GPIO specifier, should be 2:
|
||||
- first cell is the pseudo-GPIO line number:
|
||||
@ -16,35 +18,86 @@ Required node properties:
|
||||
2 - NOR FLASH WPn
|
||||
- second cell can take standard GPIO flags (currently ignored).
|
||||
|
||||
Control registers providing pseudo-GPIO lines must be represented
|
||||
by subnodes, each of them requiring the following properties:
|
||||
- compatible value : one of
|
||||
"arm,vexpress-sysreg,sys_led"
|
||||
"arm,vexpress-sysreg,sys_mci"
|
||||
"arm,vexpress-sysreg,sys_flash"
|
||||
- gpio-controller : makes the node a GPIO controller
|
||||
- #gpio-cells : size of the GPIO specifier, must be 2:
|
||||
- first cell is the function number:
|
||||
- for sys_led : 0..7 = LED 0..7
|
||||
- for sys_mci : 0 = MMC CARDIN, 1 = MMC WPROT
|
||||
- for sys_flash : 0 = NOR FLASH WPn
|
||||
- second cell can take standard GPIO flags (currently ignored).
|
||||
|
||||
Example:
|
||||
v2m_sysreg: sysreg@10000000 {
|
||||
compatible = "arm,vexpress-sysreg";
|
||||
reg = <0x10000000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
v2m_led_gpios: sys_led@08 {
|
||||
compatible = "arm,vexpress-sysreg,sys_led";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
v2m_mmc_gpios: sys_mci@48 {
|
||||
compatible = "arm,vexpress-sysreg,sys_mci";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
v2m_flash_gpios: sys_flash@4c {
|
||||
compatible = "arm,vexpress-sysreg,sys_flash";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
This block also can also act a bridge to the platform's configuration
|
||||
bus via "system control" interface, addressing devices with site number,
|
||||
position in the board stack, config controller, function and device
|
||||
numbers - see motherboard's TRM for more details.
|
||||
|
||||
The node describing a config device must refer to the sysreg node via
|
||||
"arm,vexpress,config-bridge" phandle (can be also defined in the node's
|
||||
parent) and relies on the board topology properties - see main vexpress
|
||||
node documentation for more details. It must also define the following
|
||||
property:
|
||||
- arm,vexpress-sysreg,func : must contain two cells:
|
||||
- first cell defines function number (eg. 1 for clock generator,
|
||||
2 for voltage regulators etc.)
|
||||
- device number (eg. osc 0, osc 1 etc.)
|
||||
numbers - see motherboard's TRM for more details. All configuration
|
||||
controller accessible via this interface must reference the sysreg
|
||||
node via "arm,vexpress,config-bridge" phandle and define appropriate
|
||||
topology properties - see main vexpress node documentation for more
|
||||
details. Each child of such node describes one function and must
|
||||
define the following properties:
|
||||
- compatible value : must be one of (corresponding to the TRM):
|
||||
"arm,vexpress-amp"
|
||||
"arm,vexpress-dvimode"
|
||||
"arm,vexpress-energy"
|
||||
"arm,vexpress-muxfpga"
|
||||
"arm,vexpress-osc"
|
||||
"arm,vexpress-power"
|
||||
"arm,vexpress-reboot"
|
||||
"arm,vexpress-reset"
|
||||
"arm,vexpress-scc"
|
||||
"arm,vexpress-shutdown"
|
||||
"arm,vexpress-temp"
|
||||
"arm,vexpress-volt"
|
||||
- arm,vexpress-sysreg,func : must contain a set of two cells long groups:
|
||||
- first cell of each group defines the function number
|
||||
(eg. 1 for clock generator, 2 for voltage regulators etc.)
|
||||
- second cell of each group defines device number (eg. osc 0,
|
||||
osc 1 etc.)
|
||||
- some functions (eg. energy meter, with its 64 bit long counter)
|
||||
are using more than one function/device number pair
|
||||
|
||||
Example:
|
||||
mcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
osc@0 {
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 0>;
|
||||
};
|
||||
|
||||
energy@0 {
|
||||
compatible = "arm,vexpress-energy";
|
||||
arm,vexpress-sysreg,func = <13 0>, <13 1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -80,12 +80,17 @@ but also control clock generators, voltage regulators, gather
|
||||
environmental data like temperature, power consumption etc. Even
|
||||
the video output switch (FPGA) is controlled that way.
|
||||
|
||||
Nodes describing devices controlled by this infrastructure should
|
||||
point at the bridge device node:
|
||||
The controllers are not mapped into normal memory address space
|
||||
and must be accessed through bridges - other devices capable
|
||||
of generating transactions on the configuration bus.
|
||||
|
||||
The nodes describing configuration controllers must define
|
||||
the following properties:
|
||||
- compatible value:
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
- bridge phandle:
|
||||
arm,vexpress,config-bridge = <phandle>;
|
||||
This property can be also defined in a parent node (eg. for a DCC)
|
||||
and is effective for all children.
|
||||
and children describing available functions.
|
||||
|
||||
|
||||
Platform topology
|
||||
@ -197,7 +202,7 @@ Example of a VE tile description (simplified)
|
||||
};
|
||||
|
||||
dcc {
|
||||
compatible = "simple-bus";
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
osc@0 {
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
Xilinx Zynq EP107 Emulation Platform board
|
||||
Xilinx Zynq Platforms Device Tree Bindings
|
||||
|
||||
This board is an emulation platform for the Zynq product which is
|
||||
based on an ARM Cortex A9 processor.
|
||||
Boards with Zynq-7000 SOC based on an ARM Cortex A9 processor
|
||||
shall have the following properties.
|
||||
|
||||
Required root node properties:
|
||||
- compatible = "xlnx,zynq-ep107";
|
||||
- compatible = "xlnx,zynq-7000";
|
||||
|
||||
@ -3,18 +3,75 @@
|
||||
SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA controller should have its own node.
|
||||
|
||||
It is possible, but not required, to represent each port as a sub-node.
|
||||
It allows to enable each port independently when dealing with multiple
|
||||
PHYs.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, contains "snps,spear-ahci"
|
||||
- compatible : compatible string, one of:
|
||||
- "allwinner,sun4i-a10-ahci"
|
||||
- "hisilicon,hisi-ahci"
|
||||
- "ibm,476gtr-ahci"
|
||||
- "marvell,armada-380-ahci"
|
||||
- "snps,dwc-ahci"
|
||||
- "snps,exynos5440-ahci"
|
||||
- "snps,spear-ahci"
|
||||
- "generic-ahci"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- reg : <registers mapping>
|
||||
|
||||
Please note that when using "generic-ahci" you must also specify a SoC specific
|
||||
compatible:
|
||||
compatible = "manufacturer,soc-model-ahci", "generic-ahci";
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent : Present if dma operations are coherent
|
||||
- clocks : a list of phandle + clock specifier pairs
|
||||
- target-supply : regulator for SATA target power
|
||||
- phys : reference to the SATA PHY node
|
||||
- phy-names : must be "sata-phy"
|
||||
|
||||
Example:
|
||||
Required properties when using sub-nodes:
|
||||
- #address-cells : number of cells to encode an address
|
||||
- #size-cells : number of cells representing the size of an address
|
||||
|
||||
|
||||
Sub-nodes required properties:
|
||||
- reg : the port number
|
||||
- phys : reference to the SATA PHY node
|
||||
|
||||
|
||||
Examples:
|
||||
sata@ffe08000 {
|
||||
compatible = "snps,spear-ahci";
|
||||
reg = <0xffe08000 0x1000>;
|
||||
interrupts = <115>;
|
||||
|
||||
};
|
||||
|
||||
ahci: sata@01c18000 {
|
||||
compatible = "allwinner,sun4i-a10-ahci";
|
||||
reg = <0x01c18000 0x1000>;
|
||||
interrupts = <56>;
|
||||
clocks = <&pll6 0>, <&ahb_gates 25>;
|
||||
target-supply = <®_ahci_5v>;
|
||||
};
|
||||
|
||||
With sub-nodes:
|
||||
sata@f7e90000 {
|
||||
compatible = "marvell,berlin2q-achi", "generic-ahci";
|
||||
reg = <0xe90000 0x1000>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&chip CLKID_SATA>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata0: sata-port@0 {
|
||||
reg = <0>;
|
||||
phys = <&sata_phy 0>;
|
||||
};
|
||||
|
||||
sata1: sata-port@1 {
|
||||
reg = <1>;
|
||||
phys = <&sata_phy 1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -4,14 +4,27 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
|
||||
Each SATA controller should have its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : compatible list, contains "samsung,exynos5-sata"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- reg : <registers mapping>
|
||||
- samsung,sata-freq : <frequency in MHz>
|
||||
- compatible : compatible list, contains "samsung,exynos5-sata"
|
||||
- interrupts : <interrupt mapping for SATA IRQ>
|
||||
- reg : <registers mapping>
|
||||
- samsung,sata-freq : <frequency in MHz>
|
||||
- phys : Must contain exactly one entry as specified
|
||||
in phy-bindings.txt
|
||||
- phy-names : Must be "sata-phy"
|
||||
|
||||
Optional properties:
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
- clock-names : Shall be "sata" for the external SATA bus clock,
|
||||
and "sclk_sata" for the internal controller clock.
|
||||
|
||||
Example:
|
||||
sata@ffe08000 {
|
||||
compatible = "samsung,exynos5-sata";
|
||||
reg = <0xffe08000 0x1000>;
|
||||
interrupts = <115>;
|
||||
};
|
||||
sata@122f0000 {
|
||||
compatible = "snps,dwc-ahci";
|
||||
samsung,sata-freq = <66>;
|
||||
reg = <0x122f0000 0x1ff>;
|
||||
interrupts = <0 115 0>;
|
||||
clocks = <&clock 277>, <&clock 143>;
|
||||
clock-names = "sata", "sclk_sata";
|
||||
phys = <&sata_phy>;
|
||||
phy-names = "sata-phy";
|
||||
};
|
||||
|
||||
@ -8,7 +8,12 @@ The actual devices are instantiated from the child nodes of a WEIM node.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be set to "fsl,<soc>-weim"
|
||||
- compatible: Should contain one of the following:
|
||||
"fsl,imx1-weim"
|
||||
"fsl,imx27-weim"
|
||||
"fsl,imx51-weim"
|
||||
"fsl,imx50-weim"
|
||||
"fsl,imx6q-weim"
|
||||
- reg: A resource specifier for the register space
|
||||
(see the example below)
|
||||
- clocks: the clock, see the example below.
|
||||
@ -19,6 +24,26 @@ Required properties:
|
||||
|
||||
<cs-number> 0 <physical address of mapping> <size>
|
||||
|
||||
Optional properties:
|
||||
|
||||
- fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
|
||||
devices, it should be the phandle to the system General
|
||||
Purpose Register controller that contains WEIM CS GPR
|
||||
register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
|
||||
should be set up as one of the following 4 possible
|
||||
values depending on the CS space configuration.
|
||||
|
||||
IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
|
||||
---------------------------------------------
|
||||
05 128M 0M 0M 0M
|
||||
033 64M 64M 0M 0M
|
||||
0113 64M 32M 32M 0M
|
||||
01111 32M 32M 32M 32M
|
||||
|
||||
In case that the property is absent, the reset value or
|
||||
what bootloader sets up in IOMUXC_GPR1[11:0] will be
|
||||
used.
|
||||
|
||||
Timing property for child nodes. It is mandatory, not optional.
|
||||
|
||||
- fsl,weim-cs-timing: The timing array, contains timing values for the
|
||||
@ -43,6 +68,7 @@ Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x08000000 0x08000000>;
|
||||
fsl,weim-cs-gpr = <&gpr>;
|
||||
|
||||
nor@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
|
||||
@ -197,7 +197,7 @@ to be set by the operating system and that are guaranteed to be free of overlaps
|
||||
with one another or with the system memory ranges.
|
||||
|
||||
Each entry in the property refers to exactly one window. If the operating system
|
||||
choses to use a different set of mbus windows, it must ensure that any address
|
||||
chooses to use a different set of mbus windows, it must ensure that any address
|
||||
translations performed from downstream devices are adapted accordingly.
|
||||
|
||||
The operating system may insert additional mbus windows that do not conflict
|
||||
|
||||
@ -21,5 +21,10 @@ Optional properties:
|
||||
- fixed-divider : If clocks have a fixed divider value, use this property.
|
||||
- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
|
||||
and the bit index.
|
||||
- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
|
||||
and width.
|
||||
- div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
|
||||
the divider register, bit shift, and width.
|
||||
- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
|
||||
the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
|
||||
value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
|
||||
hold/delay times that is needed for the SD/MMC CIU clock. The values of both
|
||||
can be 0-315 degrees, in 45 degree increments.
|
||||
|
||||
@ -6,6 +6,16 @@ This binding uses the common clock binding[1].
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"atmel,at91sam9x5-sckc":
|
||||
at91 SCKC (Slow Clock Controller)
|
||||
This node contains the slow clock definitions.
|
||||
|
||||
"atmel,at91sam9x5-clk-slow-osc":
|
||||
at91 slow oscillator
|
||||
|
||||
"atmel,at91sam9x5-clk-slow-rc-osc":
|
||||
at91 internal slow RC oscillator
|
||||
|
||||
"atmel,at91rm9200-pmc" or
|
||||
"atmel,at91sam9g45-pmc" or
|
||||
"atmel,at91sam9n12-pmc" or
|
||||
@ -15,8 +25,18 @@ Required properties:
|
||||
All at91 specific clocks (clocks defined below) must be child
|
||||
node of the PMC node.
|
||||
|
||||
"atmel,at91sam9x5-clk-slow" (under sckc node)
|
||||
or
|
||||
"atmel,at91sam9260-clk-slow" (under pmc node):
|
||||
at91 slow clk
|
||||
|
||||
"atmel,at91rm9200-clk-main-osc"
|
||||
"atmel,at91sam9x5-clk-main-rc-osc"
|
||||
at91 main clk sources
|
||||
|
||||
"atmel,at91sam9x5-clk-main"
|
||||
"atmel,at91rm9200-clk-main":
|
||||
at91 main oscillator
|
||||
at91 main clock
|
||||
|
||||
"atmel,at91rm9200-clk-master" or
|
||||
"atmel,at91sam9x5-clk-master":
|
||||
@ -54,6 +74,63 @@ Required properties:
|
||||
"atmel,at91sam9x5-clk-utmi":
|
||||
at91 utmi clock
|
||||
|
||||
Required properties for SCKC node:
|
||||
- reg : defines the IO memory reserved for the SCKC.
|
||||
- #size-cells : shall be 0 (reg is used to encode clk id).
|
||||
- #address-cells : shall be 1 (reg is used to encode clk id).
|
||||
|
||||
|
||||
For example:
|
||||
sckc: sckc@fffffe50 {
|
||||
compatible = "atmel,sama5d3-pmc";
|
||||
reg = <0xfffffe50 0x4>
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
/* put at91 slow clocks here */
|
||||
};
|
||||
|
||||
|
||||
Required properties for internal slow RC oscillator:
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clock-frequency : define the internal RC oscillator frequency.
|
||||
|
||||
Optional properties:
|
||||
- clock-accuracy : define the internal RC oscillator accuracy.
|
||||
|
||||
For example:
|
||||
slow_rc_osc: slow_rc_osc {
|
||||
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
|
||||
clock-frequency = <32768>;
|
||||
clock-accuracy = <50000000>;
|
||||
};
|
||||
|
||||
Required properties for slow oscillator:
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : shall encode the main osc source clk sources (see atmel datasheet).
|
||||
|
||||
Optional properties:
|
||||
- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
|
||||
provided on XIN.
|
||||
|
||||
For example:
|
||||
slow_osc: slow_osc {
|
||||
compatible = "atmel,at91rm9200-clk-slow-osc";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&slow_xtal>;
|
||||
};
|
||||
|
||||
Required properties for slow clock:
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : shall encode the slow clk sources (see atmel datasheet).
|
||||
|
||||
For example:
|
||||
clk32k: slck {
|
||||
compatible = "atmel,at91sam9x5-clk-slow";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&slow_rc_osc &slow_osc>;
|
||||
};
|
||||
|
||||
Required properties for PMC node:
|
||||
- reg : defines the IO memory reserved for the PMC.
|
||||
- #size-cells : shall be 0 (reg is used to encode clk id).
|
||||
@ -62,7 +139,7 @@ Required properties for PMC node:
|
||||
- interrupt-controller : tell that the PMC is an interrupt controller.
|
||||
- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,
|
||||
and reflect the bit position in the PMC_ER/DR/SR registers.
|
||||
You can use the dt macros defined in dt-bindings/clk/at91.h.
|
||||
You can use the dt macros defined in dt-bindings/clock/at91.h.
|
||||
0 (AT91_PMC_MOSCS) -> main oscillator ready
|
||||
1 (AT91_PMC_LOCKA) -> PLL A ready
|
||||
2 (AT91_PMC_LOCKB) -> PLL B ready
|
||||
@ -85,24 +162,57 @@ For example:
|
||||
/* put at91 clocks here */
|
||||
};
|
||||
|
||||
Required properties for main clock internal RC oscillator:
|
||||
- interrupt-parent : must reference the PMC node.
|
||||
- interrupts : shall be set to "<0>".
|
||||
- clock-frequency : define the internal RC oscillator frequency.
|
||||
|
||||
Optional properties:
|
||||
- clock-accuracy : define the internal RC oscillator accuracy.
|
||||
|
||||
For example:
|
||||
main_rc_osc: main_rc_osc {
|
||||
compatible = "atmel,at91sam9x5-clk-main-rc-osc";
|
||||
interrupt-parent = <&pmc>;
|
||||
interrupts = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
clock-accuracy = <50000000>;
|
||||
};
|
||||
|
||||
Required properties for main clock oscillator:
|
||||
- interrupt-parent : must reference the PMC node.
|
||||
- interrupts : shall be set to "<0>".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : shall encode the main osc source clk sources (see atmel datasheet).
|
||||
|
||||
Optional properties:
|
||||
- atmel,osc-bypass : boolean property. Specified if a clock signal is provided
|
||||
on XIN.
|
||||
|
||||
clock signal is directly provided on XIN pin.
|
||||
|
||||
For example:
|
||||
main_osc: main_osc {
|
||||
compatible = "atmel,at91rm9200-clk-main-osc";
|
||||
interrupt-parent = <&pmc>;
|
||||
interrupts = <0>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&main_xtal>;
|
||||
};
|
||||
|
||||
Required properties for main clock:
|
||||
- interrupt-parent : must reference the PMC node.
|
||||
- interrupts : shall be set to "<0>".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks (optional if clock-frequency is provided) : shall be the slow clock
|
||||
phandle. This clock is used to calculate the main clock rate if
|
||||
"clock-frequency" is not provided.
|
||||
- clock-frequency : the main oscillator frequency.Prefer the use of
|
||||
"clock-frequency" over automatic clock rate calculation.
|
||||
- clocks : shall encode the main clk sources (see atmel datasheet).
|
||||
|
||||
For example:
|
||||
main: mainck {
|
||||
compatible = "atmel,at91rm9200-clk-main";
|
||||
compatible = "atmel,at91sam9x5-clk-main";
|
||||
interrupt-parent = <&pmc>;
|
||||
interrupts = <0>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&ck32k>;
|
||||
clock-frequency = <18432000>;
|
||||
clocks = <&main_rc_osc &main_osc>;
|
||||
};
|
||||
|
||||
Required properties for master clock:
|
||||
|
||||
@ -5,7 +5,7 @@ This binding uses the common clock binding[1].
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "adi,axi-clkgen".
|
||||
- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
|
||||
- #clock-cells : from common clock binding; Should always be set to 0.
|
||||
- reg : Address and length of the axi-clkgen register set.
|
||||
- clocks : Phandle and clock specifier for the parent clock.
|
||||
|
||||
@ -10,12 +10,12 @@ This binding uses the common clock binding:
|
||||
|
||||
Required properties:
|
||||
- compatible
|
||||
Shall have one of the following values:
|
||||
- "brcm,bcm11351-root-ccu"
|
||||
- "brcm,bcm11351-aon-ccu"
|
||||
- "brcm,bcm11351-hub-ccu"
|
||||
- "brcm,bcm11351-master-ccu"
|
||||
- "brcm,bcm11351-slave-ccu"
|
||||
Shall have a value of the form "brcm,<model>-<which>-ccu",
|
||||
where <model> is a Broadcom SoC model number and <which> is
|
||||
the name of a defined CCU. For example:
|
||||
"brcm,bcm11351-root-ccu"
|
||||
The compatible strings used for each supported SoC family
|
||||
are defined below.
|
||||
- reg
|
||||
Shall define the base and range of the address space
|
||||
containing clock control registers
|
||||
@ -26,12 +26,48 @@ Required properties:
|
||||
Shall be an ordered list of strings defining the names of
|
||||
the clocks provided by the CCU.
|
||||
|
||||
Device tree example:
|
||||
|
||||
BCM281XX family SoCs use Kona CCUs. The following table defines
|
||||
the set of CCUs and clock specifiers for BCM281XX clocks. When
|
||||
a clock consumer references a clocks, its symbolic specifier
|
||||
(rather than its numeric index value) should be used. These
|
||||
specifiers are defined in "include/dt-bindings/clock/bcm281xx.h".
|
||||
slave_ccu: slave_ccu {
|
||||
compatible = "brcm,bcm11351-slave-ccu";
|
||||
reg = <0x3e011000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "uartb",
|
||||
"uartb2",
|
||||
"uartb3",
|
||||
"uartb4";
|
||||
};
|
||||
|
||||
ref_crystal_clk: ref_crystal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
uart@3e002000 {
|
||||
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e002000 0x1000>;
|
||||
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
BCM281XX family
|
||||
---------------
|
||||
CCU compatible string values for SoCs in the BCM281XX family are:
|
||||
"brcm,bcm11351-root-ccu"
|
||||
"brcm,bcm11351-aon-ccu"
|
||||
"brcm,bcm11351-hub-ccu"
|
||||
"brcm,bcm11351-master-ccu"
|
||||
"brcm,bcm11351-slave-ccu"
|
||||
|
||||
The following table defines the set of CCUs and clock specifiers for
|
||||
BCM281XX family clocks. When a clock consumer references a clocks,
|
||||
its symbolic specifier (rather than its numeric index value) should
|
||||
be used. These specifiers are defined in:
|
||||
"include/dt-bindings/clock/bcm281xx.h"
|
||||
|
||||
CCU Clock Type Index Specifier
|
||||
--- ----- ---- ----- ---------
|
||||
@ -64,30 +100,40 @@ specifiers are defined in "include/dt-bindings/clock/bcm281xx.h".
|
||||
slave pwm peri 9 BCM281XX_SLAVE_CCU_PWM
|
||||
|
||||
|
||||
Device tree example:
|
||||
BCM21664 family
|
||||
---------------
|
||||
CCU compatible string values for SoCs in the BCM21664 family are:
|
||||
"brcm,bcm21664-root-ccu"
|
||||
"brcm,bcm21664-aon-ccu"
|
||||
"brcm,bcm21664-master-ccu"
|
||||
"brcm,bcm21664-slave-ccu"
|
||||
|
||||
slave_ccu: slave_ccu {
|
||||
compatible = "brcm,bcm11351-slave-ccu";
|
||||
reg = <0x3e011000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "uartb",
|
||||
"uartb2",
|
||||
"uartb3",
|
||||
"uartb4";
|
||||
};
|
||||
The following table defines the set of CCUs and clock specifiers for
|
||||
BCM21664 family clocks. When a clock consumer references a clocks,
|
||||
its symbolic specifier (rather than its numeric index value) should
|
||||
be used. These specifiers are defined in:
|
||||
"include/dt-bindings/clock/bcm21664.h"
|
||||
|
||||
ref_crystal_clk: ref_crystal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
CCU Clock Type Index Specifier
|
||||
--- ----- ---- ----- ---------
|
||||
root frac_1m peri 0 BCM21664_ROOT_CCU_FRAC_1M
|
||||
|
||||
uart@3e002000 {
|
||||
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e002000 0x1000>;
|
||||
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
aon hub_timer peri 0 BCM21664_AON_CCU_HUB_TIMER
|
||||
|
||||
master sdio1 peri 0 BCM21664_MASTER_CCU_SDIO1
|
||||
master sdio2 peri 1 BCM21664_MASTER_CCU_SDIO2
|
||||
master sdio3 peri 2 BCM21664_MASTER_CCU_SDIO3
|
||||
master sdio4 peri 3 BCM21664_MASTER_CCU_SDIO4
|
||||
master sdio1_sleep peri 4 BCM21664_MASTER_CCU_SDIO1_SLEEP
|
||||
master sdio2_sleep peri 5 BCM21664_MASTER_CCU_SDIO2_SLEEP
|
||||
master sdio3_sleep peri 6 BCM21664_MASTER_CCU_SDIO3_SLEEP
|
||||
master sdio4_sleep peri 7 BCM21664_MASTER_CCU_SDIO4_SLEEP
|
||||
|
||||
slave uartb peri 0 BCM21664_SLAVE_CCU_UARTB
|
||||
slave uartb2 peri 1 BCM21664_SLAVE_CCU_UARTB2
|
||||
slave uartb3 peri 2 BCM21664_SLAVE_CCU_UARTB3
|
||||
slave uartb4 peri 3 BCM21664_SLAVE_CCU_UARTB4
|
||||
slave bsc1 peri 4 BCM21664_SLAVE_CCU_BSC1
|
||||
slave bsc2 peri 5 BCM21664_SLAVE_CCU_BSC2
|
||||
slave bsc3 peri 6 BCM21664_SLAVE_CCU_BSC3
|
||||
slave bsc4 peri 7 BCM21664_SLAVE_CCU_BSC4
|
||||
|
||||
@ -44,6 +44,22 @@ For example:
|
||||
clocks by index. The names should reflect the clock output signal
|
||||
names for the device.
|
||||
|
||||
clock-indices: If the identifying number for the clocks in the node
|
||||
is not linear from zero, then this allows the mapping of
|
||||
identifiers into the clock-output-names array.
|
||||
|
||||
For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
|
||||
|
||||
oscillator {
|
||||
compatible = "myclocktype";
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <1>, <3>;
|
||||
clock-output-names = "clka", "clkb";
|
||||
}
|
||||
|
||||
This ensures we do not have any empty strings in clock-output-names
|
||||
|
||||
|
||||
==Clock consumers==
|
||||
|
||||
Required properties:
|
||||
@ -115,3 +131,39 @@ clock signal, and a UART.
|
||||
("pll" and "pll-switched").
|
||||
* The UART has its baud clock connected the external oscillator and its
|
||||
register clock connected to the PLL clock (the "pll-switched" signal)
|
||||
|
||||
==Assigned clock parents and rates==
|
||||
|
||||
Some platforms may require initial configuration of default parent clocks
|
||||
and clock frequencies. Such a configuration can be specified in a device tree
|
||||
node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
|
||||
properties. The assigned-clock-parents property should contain a list of parent
|
||||
clocks in form of phandle and clock specifier pairs, the assigned-clock-parents
|
||||
property the list of assigned clock frequency values - corresponding to clocks
|
||||
listed in the assigned-clocks property.
|
||||
|
||||
To skip setting parent or rate of a clock its corresponding entry should be
|
||||
set to 0, or can be omitted if it is not followed by any non-zero entry.
|
||||
|
||||
uart@a000 {
|
||||
compatible = "fsl,imx-uart";
|
||||
reg = <0xa000 0x1000>;
|
||||
...
|
||||
clocks = <&osc 0>, <&pll 1>;
|
||||
clock-names = "baud", "register";
|
||||
|
||||
assigned-clocks = <&clkcon 0>, <&pll 2>;
|
||||
assigned-clock-parents = <&pll 2>;
|
||||
assigned-clock-rates = <0>, <460800>;
|
||||
};
|
||||
|
||||
In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
|
||||
the <&pll 2> clock is assigned a frequency value of 460800 Hz.
|
||||
|
||||
Configuring a clock's parent and rate through the device node that consumes
|
||||
the clock can be done only for clocks that have a single user. Specifying
|
||||
conflicting parent or rate configuration in multiple consumer nodes for
|
||||
a shared clock is forbidden.
|
||||
|
||||
Configuration of common clocks, which affect multiple consumer devices can
|
||||
be similarly specified in the clock provider node.
|
||||
|
||||
@ -15,259 +15,12 @@ Required Properties:
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume. Some of the clocks are available only on a particular
|
||||
Exynos4 SoC and this is specified where applicable.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
xxti 1
|
||||
xusbxti 2
|
||||
fin_pll 3
|
||||
fout_apll 4
|
||||
fout_mpll 5
|
||||
fout_epll 6
|
||||
fout_vpll 7
|
||||
sclk_apll 8
|
||||
sclk_mpll 9
|
||||
sclk_epll 10
|
||||
sclk_vpll 11
|
||||
arm_clk 12
|
||||
aclk200 13
|
||||
aclk100 14
|
||||
aclk160 15
|
||||
aclk133 16
|
||||
mout_mpll_user_t 17 Exynos4x12
|
||||
mout_mpll_user_c 18 Exynos4x12
|
||||
mout_core 19
|
||||
mout_apll 20
|
||||
|
||||
|
||||
[Clock Gate for Special Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
sclk_fimc0 128
|
||||
sclk_fimc1 129
|
||||
sclk_fimc2 130
|
||||
sclk_fimc3 131
|
||||
sclk_cam0 132
|
||||
sclk_cam1 133
|
||||
sclk_csis0 134
|
||||
sclk_csis1 135
|
||||
sclk_hdmi 136
|
||||
sclk_mixer 137
|
||||
sclk_dac 138
|
||||
sclk_pixel 139
|
||||
sclk_fimd0 140
|
||||
sclk_mdnie0 141 Exynos4412
|
||||
sclk_mdnie_pwm0 12 142 Exynos4412
|
||||
sclk_mipi0 143
|
||||
sclk_audio0 144
|
||||
sclk_mmc0 145
|
||||
sclk_mmc1 146
|
||||
sclk_mmc2 147
|
||||
sclk_mmc3 148
|
||||
sclk_mmc4 149
|
||||
sclk_sata 150 Exynos4210
|
||||
sclk_uart0 151
|
||||
sclk_uart1 152
|
||||
sclk_uart2 153
|
||||
sclk_uart3 154
|
||||
sclk_uart4 155
|
||||
sclk_audio1 156
|
||||
sclk_audio2 157
|
||||
sclk_spdif 158
|
||||
sclk_spi0 159
|
||||
sclk_spi1 160
|
||||
sclk_spi2 161
|
||||
sclk_slimbus 162
|
||||
sclk_fimd1 163 Exynos4210
|
||||
sclk_mipi1 164 Exynos4210
|
||||
sclk_pcm1 165
|
||||
sclk_pcm2 166
|
||||
sclk_i2s1 167
|
||||
sclk_i2s2 168
|
||||
sclk_mipihsi 169 Exynos4412
|
||||
sclk_mfc 170
|
||||
sclk_pcm0 171
|
||||
sclk_g3d 172
|
||||
sclk_pwm_isp 173 Exynos4x12
|
||||
sclk_spi0_isp 174 Exynos4x12
|
||||
sclk_spi1_isp 175 Exynos4x12
|
||||
sclk_uart_isp 176 Exynos4x12
|
||||
sclk_fimg2d 177
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
fimc0 256
|
||||
fimc1 257
|
||||
fimc2 258
|
||||
fimc3 259
|
||||
csis0 260
|
||||
csis1 261
|
||||
jpeg 262
|
||||
smmu_fimc0 263
|
||||
smmu_fimc1 264
|
||||
smmu_fimc2 265
|
||||
smmu_fimc3 266
|
||||
smmu_jpeg 267
|
||||
vp 268
|
||||
mixer 269
|
||||
tvenc 270 Exynos4210
|
||||
hdmi 271
|
||||
smmu_tv 272
|
||||
mfc 273
|
||||
smmu_mfcl 274
|
||||
smmu_mfcr 275
|
||||
g3d 276
|
||||
g2d 277
|
||||
rotator 278 Exynos4210
|
||||
mdma 279 Exynos4210
|
||||
smmu_g2d 280 Exynos4210
|
||||
smmu_rotator 281 Exynos4210
|
||||
smmu_mdma 282 Exynos4210
|
||||
fimd0 283
|
||||
mie0 284
|
||||
mdnie0 285 Exynos4412
|
||||
dsim0 286
|
||||
smmu_fimd0 287
|
||||
fimd1 288 Exynos4210
|
||||
mie1 289 Exynos4210
|
||||
dsim1 290 Exynos4210
|
||||
smmu_fimd1 291 Exynos4210
|
||||
pdma0 292
|
||||
pdma1 293
|
||||
pcie_phy 294
|
||||
sata_phy 295 Exynos4210
|
||||
tsi 296
|
||||
sdmmc0 297
|
||||
sdmmc1 298
|
||||
sdmmc2 299
|
||||
sdmmc3 300
|
||||
sdmmc4 301
|
||||
sata 302 Exynos4210
|
||||
sromc 303
|
||||
usb_host 304
|
||||
usb_device 305
|
||||
pcie 306
|
||||
onenand 307
|
||||
nfcon 308
|
||||
smmu_pcie 309
|
||||
gps 310
|
||||
smmu_gps 311
|
||||
uart0 312
|
||||
uart1 313
|
||||
uart2 314
|
||||
uart3 315
|
||||
uart4 316
|
||||
i2c0 317
|
||||
i2c1 318
|
||||
i2c2 319
|
||||
i2c3 320
|
||||
i2c4 321
|
||||
i2c5 322
|
||||
i2c6 323
|
||||
i2c7 324
|
||||
i2c_hdmi 325
|
||||
tsadc 326
|
||||
spi0 327
|
||||
spi1 328
|
||||
spi2 329
|
||||
i2s1 330
|
||||
i2s2 331
|
||||
pcm0 332
|
||||
i2s0 333
|
||||
pcm1 334
|
||||
pcm2 335
|
||||
pwm 336
|
||||
slimbus 337
|
||||
spdif 338
|
||||
ac97 339
|
||||
modemif 340
|
||||
chipid 341
|
||||
sysreg 342
|
||||
hdmi_cec 343
|
||||
mct 344
|
||||
wdt 345
|
||||
rtc 346
|
||||
keyif 347
|
||||
audss 348
|
||||
mipi_hsi 349 Exynos4210
|
||||
mdma2 350 Exynos4210
|
||||
pixelasyncm0 351
|
||||
pixelasyncm1 352
|
||||
fimc_lite0 353 Exynos4x12
|
||||
fimc_lite1 354 Exynos4x12
|
||||
ppmuispx 355 Exynos4x12
|
||||
ppmuispmx 356 Exynos4x12
|
||||
fimc_isp 357 Exynos4x12
|
||||
fimc_drc 358 Exynos4x12
|
||||
fimc_fd 359 Exynos4x12
|
||||
mcuisp 360 Exynos4x12
|
||||
gicisp 361 Exynos4x12
|
||||
smmu_isp 362 Exynos4x12
|
||||
smmu_drc 363 Exynos4x12
|
||||
smmu_fd 364 Exynos4x12
|
||||
smmu_lite0 365 Exynos4x12
|
||||
smmu_lite1 366 Exynos4x12
|
||||
mcuctl_isp 367 Exynos4x12
|
||||
mpwm_isp 368 Exynos4x12
|
||||
i2c0_isp 369 Exynos4x12
|
||||
i2c1_isp 370 Exynos4x12
|
||||
mtcadc_isp 371 Exynos4x12
|
||||
pwm_isp 372 Exynos4x12
|
||||
wdt_isp 373 Exynos4x12
|
||||
uart_isp 374 Exynos4x12
|
||||
asyncaxim 375 Exynos4x12
|
||||
smmu_ispcx 376 Exynos4x12
|
||||
spi0_isp 377 Exynos4x12
|
||||
spi1_isp 378 Exynos4x12
|
||||
pwm_isp_sclk 379 Exynos4x12
|
||||
spi0_isp_sclk 380 Exynos4x12
|
||||
spi1_isp_sclk 381 Exynos4x12
|
||||
uart_isp_sclk 382 Exynos4x12
|
||||
tmu_apbif 383
|
||||
|
||||
[Mux Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
mout_fimc0 384
|
||||
mout_fimc1 385
|
||||
mout_fimc2 386
|
||||
mout_fimc3 387
|
||||
mout_cam0 388
|
||||
mout_cam1 389
|
||||
mout_csis0 390
|
||||
mout_csis1 391
|
||||
mout_g3d0 392
|
||||
mout_g3d1 393
|
||||
mout_g3d 394
|
||||
aclk400_mcuisp 395 Exynos4x12
|
||||
|
||||
[Div Clocks]
|
||||
|
||||
Clock ID SoC (if specific)
|
||||
-----------------------------------------------
|
||||
|
||||
div_isp0 450 Exynos4x12
|
||||
div_isp1 451 Exynos4x12
|
||||
div_mcuisp0 452 Exynos4x12
|
||||
div_mcuisp1 453 Exynos4x12
|
||||
div_aclk200 454 Exynos4x12
|
||||
div_aclk400_mcuisp 455 Exynos4x12
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos4.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
@ -285,6 +38,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
@ -13,163 +13,12 @@ Required Properties:
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
fin_pll 1
|
||||
|
||||
[Clock Gate for Special Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
sclk_cam_bayer 128
|
||||
sclk_cam0 129
|
||||
sclk_cam1 130
|
||||
sclk_gscl_wa 131
|
||||
sclk_gscl_wb 132
|
||||
sclk_fimd1 133
|
||||
sclk_mipi1 134
|
||||
sclk_dp 135
|
||||
sclk_hdmi 136
|
||||
sclk_pixel 137
|
||||
sclk_audio0 138
|
||||
sclk_mmc0 139
|
||||
sclk_mmc1 140
|
||||
sclk_mmc2 141
|
||||
sclk_mmc3 142
|
||||
sclk_sata 143
|
||||
sclk_usb3 144
|
||||
sclk_jpeg 145
|
||||
sclk_uart0 146
|
||||
sclk_uart1 147
|
||||
sclk_uart2 148
|
||||
sclk_uart3 149
|
||||
sclk_pwm 150
|
||||
sclk_audio1 151
|
||||
sclk_audio2 152
|
||||
sclk_spdif 153
|
||||
sclk_spi0 154
|
||||
sclk_spi1 155
|
||||
sclk_spi2 156
|
||||
div_i2s1 157
|
||||
div_i2s2 158
|
||||
sclk_hdmiphy 159
|
||||
div_pcm0 160
|
||||
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
gscl0 256
|
||||
gscl1 257
|
||||
gscl2 258
|
||||
gscl3 259
|
||||
gscl_wa 260
|
||||
gscl_wb 261
|
||||
smmu_gscl0 262
|
||||
smmu_gscl1 263
|
||||
smmu_gscl2 264
|
||||
smmu_gscl3 265
|
||||
mfc 266
|
||||
smmu_mfcl 267
|
||||
smmu_mfcr 268
|
||||
rotator 269
|
||||
jpeg 270
|
||||
mdma1 271
|
||||
smmu_rotator 272
|
||||
smmu_jpeg 273
|
||||
smmu_mdma1 274
|
||||
pdma0 275
|
||||
pdma1 276
|
||||
sata 277
|
||||
usbotg 278
|
||||
mipi_hsi 279
|
||||
sdmmc0 280
|
||||
sdmmc1 281
|
||||
sdmmc2 282
|
||||
sdmmc3 283
|
||||
sromc 284
|
||||
usb2 285
|
||||
usb3 286
|
||||
sata_phyctrl 287
|
||||
sata_phyi2c 288
|
||||
uart0 289
|
||||
uart1 290
|
||||
uart2 291
|
||||
uart3 292
|
||||
uart4 293
|
||||
i2c0 294
|
||||
i2c1 295
|
||||
i2c2 296
|
||||
i2c3 297
|
||||
i2c4 298
|
||||
i2c5 299
|
||||
i2c6 300
|
||||
i2c7 301
|
||||
i2c_hdmi 302
|
||||
adc 303
|
||||
spi0 304
|
||||
spi1 305
|
||||
spi2 306
|
||||
i2s1 307
|
||||
i2s2 308
|
||||
pcm1 309
|
||||
pcm2 310
|
||||
pwm 311
|
||||
spdif 312
|
||||
ac97 313
|
||||
hsi2c0 314
|
||||
hsi2c1 315
|
||||
hs12c2 316
|
||||
hs12c3 317
|
||||
chipid 318
|
||||
sysreg 319
|
||||
pmu 320
|
||||
cmu_top 321
|
||||
cmu_core 322
|
||||
cmu_mem 323
|
||||
tzpc0 324
|
||||
tzpc1 325
|
||||
tzpc2 326
|
||||
tzpc3 327
|
||||
tzpc4 328
|
||||
tzpc5 329
|
||||
tzpc6 330
|
||||
tzpc7 331
|
||||
tzpc8 332
|
||||
tzpc9 333
|
||||
hdmi_cec 334
|
||||
mct 335
|
||||
wdt 336
|
||||
rtc 337
|
||||
tmu 338
|
||||
fimd1 339
|
||||
mie1 340
|
||||
dsim0 341
|
||||
dp 342
|
||||
mixer 343
|
||||
hdmi 344
|
||||
g2d 345
|
||||
mdma0 346
|
||||
smmu_mdma0 347
|
||||
|
||||
|
||||
[Clock Muxes]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
mout_hdmi 1024
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5250.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
@ -187,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 314>, <&clock 153>;
|
||||
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
@ -1,196 +1,25 @@
|
||||
* Samsung Exynos5420 Clock Controller
|
||||
|
||||
The Exynos5420 clock controller generates and supplies clock to various
|
||||
controllers within the Exynos5420 SoC.
|
||||
controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
|
||||
- "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
fin_pll 1
|
||||
|
||||
[Clock Gate for Special Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
sclk_uart0 128
|
||||
sclk_uart1 129
|
||||
sclk_uart2 130
|
||||
sclk_uart3 131
|
||||
sclk_mmc0 132
|
||||
sclk_mmc1 133
|
||||
sclk_mmc2 134
|
||||
sclk_spi0 135
|
||||
sclk_spi1 136
|
||||
sclk_spi2 137
|
||||
sclk_i2s1 138
|
||||
sclk_i2s2 139
|
||||
sclk_pcm1 140
|
||||
sclk_pcm2 141
|
||||
sclk_spdif 142
|
||||
sclk_hdmi 143
|
||||
sclk_pixel 144
|
||||
sclk_dp1 145
|
||||
sclk_mipi1 146
|
||||
sclk_fimd1 147
|
||||
sclk_maudio0 148
|
||||
sclk_maupcm0 149
|
||||
sclk_usbd300 150
|
||||
sclk_usbd301 151
|
||||
sclk_usbphy300 152
|
||||
sclk_usbphy301 153
|
||||
sclk_unipro 154
|
||||
sclk_pwm 155
|
||||
sclk_gscl_wa 156
|
||||
sclk_gscl_wb 157
|
||||
sclk_hdmiphy 158
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
aclk66_peric 256
|
||||
uart0 257
|
||||
uart1 258
|
||||
uart2 259
|
||||
uart3 260
|
||||
i2c0 261
|
||||
i2c1 262
|
||||
i2c2 263
|
||||
i2c3 264
|
||||
i2c4 265
|
||||
i2c5 266
|
||||
i2c6 267
|
||||
i2c7 268
|
||||
i2c_hdmi 269
|
||||
tsadc 270
|
||||
spi0 271
|
||||
spi1 272
|
||||
spi2 273
|
||||
keyif 274
|
||||
i2s1 275
|
||||
i2s2 276
|
||||
pcm1 277
|
||||
pcm2 278
|
||||
pwm 279
|
||||
spdif 280
|
||||
i2c8 281
|
||||
i2c9 282
|
||||
i2c10 283
|
||||
aclk66_psgen 300
|
||||
chipid 301
|
||||
sysreg 302
|
||||
tzpc0 303
|
||||
tzpc1 304
|
||||
tzpc2 305
|
||||
tzpc3 306
|
||||
tzpc4 307
|
||||
tzpc5 308
|
||||
tzpc6 309
|
||||
tzpc7 310
|
||||
tzpc8 311
|
||||
tzpc9 312
|
||||
hdmi_cec 313
|
||||
seckey 314
|
||||
mct 315
|
||||
wdt 316
|
||||
rtc 317
|
||||
tmu 318
|
||||
tmu_gpu 319
|
||||
pclk66_gpio 330
|
||||
aclk200_fsys2 350
|
||||
mmc0 351
|
||||
mmc1 352
|
||||
mmc2 353
|
||||
sromc 354
|
||||
ufs 355
|
||||
aclk200_fsys 360
|
||||
tsi 361
|
||||
pdma0 362
|
||||
pdma1 363
|
||||
rtic 364
|
||||
usbh20 365
|
||||
usbd300 366
|
||||
usbd301 377
|
||||
aclk400_mscl 380
|
||||
mscl0 381
|
||||
mscl1 382
|
||||
mscl2 383
|
||||
smmu_mscl0 384
|
||||
smmu_mscl1 385
|
||||
smmu_mscl2 386
|
||||
aclk333 400
|
||||
mfc 401
|
||||
smmu_mfcl 402
|
||||
smmu_mfcr 403
|
||||
aclk200_disp1 410
|
||||
dsim1 411
|
||||
dp1 412
|
||||
hdmi 413
|
||||
aclk300_disp1 420
|
||||
fimd1 421
|
||||
smmu_fimd1 422
|
||||
aclk166 430
|
||||
mixer 431
|
||||
aclk266 440
|
||||
rotator 441
|
||||
mdma1 442
|
||||
smmu_rotator 443
|
||||
smmu_mdma1 444
|
||||
aclk300_jpeg 450
|
||||
jpeg 451
|
||||
jpeg2 452
|
||||
smmu_jpeg 453
|
||||
aclk300_gscl 460
|
||||
smmu_gscl0 461
|
||||
smmu_gscl1 462
|
||||
gscl_wa 463
|
||||
gscl_wb 464
|
||||
gscl0 465
|
||||
gscl1 466
|
||||
clk_3aa 467
|
||||
aclk266_g2d 470
|
||||
sss 471
|
||||
slim_sss 472
|
||||
mdma0 473
|
||||
aclk333_g2d 480
|
||||
g2d 481
|
||||
aclk333_432_gscl 490
|
||||
smmu_3aa 491
|
||||
smmu_fimcl0 492
|
||||
smmu_fimcl1 493
|
||||
smmu_fimcl3 494
|
||||
fimc_lite3 495
|
||||
aclk_g3d 500
|
||||
g3d 501
|
||||
smmu_mixer 502
|
||||
|
||||
Mux ID
|
||||
----------------------------
|
||||
|
||||
mout_hdmi 640
|
||||
|
||||
Divider ID
|
||||
----------------------------
|
||||
|
||||
dout_pixel 768
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5420.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example 1: An example of a clock controller node is listed below.
|
||||
|
||||
@ -208,6 +37,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
|
||||
compatible = "samsung,exynos4210-uart";
|
||||
reg = <0x13820000 0x100>;
|
||||
interrupts = <0 54 0>;
|
||||
clocks = <&clock 259>, <&clock 130>;
|
||||
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
};
|
||||
|
||||
@ -12,45 +12,12 @@ Required Properties:
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
The following is the list of clocks generated by the controller. Each clock is
|
||||
assigned an identifier and client nodes use this identifier to specify the
|
||||
clock which they consume.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
|
||||
[Core Clocks]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
xtal 1
|
||||
arm_clk 2
|
||||
|
||||
[Peripheral Clock Gates]
|
||||
|
||||
Clock ID
|
||||
----------------------------
|
||||
|
||||
spi_baud 16
|
||||
pb0_250 17
|
||||
pr0_250 18
|
||||
pr1_250 19
|
||||
b_250 20
|
||||
b_125 21
|
||||
b_200 22
|
||||
sata 23
|
||||
usb 24
|
||||
gmac0 25
|
||||
cs250 26
|
||||
pb0_250_o 27
|
||||
pr0_250_o 28
|
||||
pr1_250_o 29
|
||||
b_250_o 30
|
||||
b_125_o 31
|
||||
b_200_o 32
|
||||
sata_o 33
|
||||
usb_o 34
|
||||
gmac0_o 35
|
||||
cs250_o 36
|
||||
All available clocks are defined as preprocessor macros in
|
||||
dt-bindings/clock/exynos5440.h header and can be used in device
|
||||
tree sources.
|
||||
|
||||
Example: An example of a clock controller node is listed below.
|
||||
|
||||
|
||||
@ -12,7 +12,6 @@ Required properties:
|
||||
Optional properties:
|
||||
- clock-accuracy : accuracy of clock in ppb (parts per billion).
|
||||
Should be a single cell.
|
||||
- gpios : From common gpio binding; gpio connection to clock enable pin.
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Example:
|
||||
|
||||
@ -7,6 +7,7 @@ Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
|
||||
- "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
@ -139,6 +139,9 @@ clocks and IDs.
|
||||
uart5_ipg 124
|
||||
reserved 125
|
||||
wdt_ipg 126
|
||||
cko_div 127
|
||||
cko_sel 128
|
||||
cko 129
|
||||
|
||||
Examples:
|
||||
|
||||
|
||||
@ -7,112 +7,22 @@ Required properties:
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX27
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
-----------------------
|
||||
dummy 0
|
||||
ckih 1
|
||||
ckil 2
|
||||
mpll 3
|
||||
spll 4
|
||||
mpll_main2 5
|
||||
ahb 6
|
||||
ipg 7
|
||||
nfc_div 8
|
||||
per1_div 9
|
||||
per2_div 10
|
||||
per3_div 11
|
||||
per4_div 12
|
||||
vpu_sel 13
|
||||
vpu_div 14
|
||||
usb_div 15
|
||||
cpu_sel 16
|
||||
clko_sel 17
|
||||
cpu_div 18
|
||||
clko_div 19
|
||||
ssi1_sel 20
|
||||
ssi2_sel 21
|
||||
ssi1_div 22
|
||||
ssi2_div 23
|
||||
clko_en 24
|
||||
ssi2_ipg_gate 25
|
||||
ssi1_ipg_gate 26
|
||||
slcdc_ipg_gate 27
|
||||
sdhc3_ipg_gate 28
|
||||
sdhc2_ipg_gate 29
|
||||
sdhc1_ipg_gate 30
|
||||
scc_ipg_gate 31
|
||||
sahara_ipg_gate 32
|
||||
rtc_ipg_gate 33
|
||||
pwm_ipg_gate 34
|
||||
owire_ipg_gate 35
|
||||
lcdc_ipg_gate 36
|
||||
kpp_ipg_gate 37
|
||||
iim_ipg_gate 38
|
||||
i2c2_ipg_gate 39
|
||||
i2c1_ipg_gate 40
|
||||
gpt6_ipg_gate 41
|
||||
gpt5_ipg_gate 42
|
||||
gpt4_ipg_gate 43
|
||||
gpt3_ipg_gate 44
|
||||
gpt2_ipg_gate 45
|
||||
gpt1_ipg_gate 46
|
||||
gpio_ipg_gate 47
|
||||
fec_ipg_gate 48
|
||||
emma_ipg_gate 49
|
||||
dma_ipg_gate 50
|
||||
cspi3_ipg_gate 51
|
||||
cspi2_ipg_gate 52
|
||||
cspi1_ipg_gate 53
|
||||
nfc_baud_gate 54
|
||||
ssi2_baud_gate 55
|
||||
ssi1_baud_gate 56
|
||||
vpu_baud_gate 57
|
||||
per4_gate 58
|
||||
per3_gate 59
|
||||
per2_gate 60
|
||||
per1_gate 61
|
||||
usb_ahb_gate 62
|
||||
slcdc_ahb_gate 63
|
||||
sahara_ahb_gate 64
|
||||
lcdc_ahb_gate 65
|
||||
vpu_ahb_gate 66
|
||||
fec_ahb_gate 67
|
||||
emma_ahb_gate 68
|
||||
emi_ahb_gate 69
|
||||
dma_ahb_gate 70
|
||||
csi_ahb_gate 71
|
||||
brom_ahb_gate 72
|
||||
ata_ahb_gate 73
|
||||
wdog_ipg_gate 74
|
||||
usb_ipg_gate 75
|
||||
uart6_ipg_gate 76
|
||||
uart5_ipg_gate 77
|
||||
uart4_ipg_gate 78
|
||||
uart3_ipg_gate 79
|
||||
uart2_ipg_gate 80
|
||||
uart1_ipg_gate 81
|
||||
ckih_div1p5 82
|
||||
fpm 83
|
||||
mpll_osc_sel 84
|
||||
mpll_sel 85
|
||||
spll_gate 86
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h
|
||||
for the full list of i.MX27 clock IDs.
|
||||
|
||||
Examples:
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks 81>, <&clks 61>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
interrupts = <20>;
|
||||
clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
|
||||
<&clks IMX27_CLK_PER1_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -7,222 +7,13 @@ Required properties:
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
---------------------------
|
||||
dummy 0
|
||||
ckil 1
|
||||
ckih 2
|
||||
osc 3
|
||||
pll2_pfd0_352m 4
|
||||
pll2_pfd1_594m 5
|
||||
pll2_pfd2_396m 6
|
||||
pll3_pfd0_720m 7
|
||||
pll3_pfd1_540m 8
|
||||
pll3_pfd2_508m 9
|
||||
pll3_pfd3_454m 10
|
||||
pll2_198m 11
|
||||
pll3_120m 12
|
||||
pll3_80m 13
|
||||
pll3_60m 14
|
||||
twd 15
|
||||
step 16
|
||||
pll1_sw 17
|
||||
periph_pre 18
|
||||
periph2_pre 19
|
||||
periph_clk2_sel 20
|
||||
periph2_clk2_sel 21
|
||||
axi_sel 22
|
||||
esai_sel 23
|
||||
asrc_sel 24
|
||||
spdif_sel 25
|
||||
gpu2d_axi 26
|
||||
gpu3d_axi 27
|
||||
gpu2d_core_sel 28
|
||||
gpu3d_core_sel 29
|
||||
gpu3d_shader_sel 30
|
||||
ipu1_sel 31
|
||||
ipu2_sel 32
|
||||
ldb_di0_sel 33
|
||||
ldb_di1_sel 34
|
||||
ipu1_di0_pre_sel 35
|
||||
ipu1_di1_pre_sel 36
|
||||
ipu2_di0_pre_sel 37
|
||||
ipu2_di1_pre_sel 38
|
||||
ipu1_di0_sel 39
|
||||
ipu1_di1_sel 40
|
||||
ipu2_di0_sel 41
|
||||
ipu2_di1_sel 42
|
||||
hsi_tx_sel 43
|
||||
pcie_axi_sel 44
|
||||
ssi1_sel 45
|
||||
ssi2_sel 46
|
||||
ssi3_sel 47
|
||||
usdhc1_sel 48
|
||||
usdhc2_sel 49
|
||||
usdhc3_sel 50
|
||||
usdhc4_sel 51
|
||||
enfc_sel 52
|
||||
emi_sel 53
|
||||
emi_slow_sel 54
|
||||
vdo_axi_sel 55
|
||||
vpu_axi_sel 56
|
||||
cko1_sel 57
|
||||
periph 58
|
||||
periph2 59
|
||||
periph_clk2 60
|
||||
periph2_clk2 61
|
||||
ipg 62
|
||||
ipg_per 63
|
||||
esai_pred 64
|
||||
esai_podf 65
|
||||
asrc_pred 66
|
||||
asrc_podf 67
|
||||
spdif_pred 68
|
||||
spdif_podf 69
|
||||
can_root 70
|
||||
ecspi_root 71
|
||||
gpu2d_core_podf 72
|
||||
gpu3d_core_podf 73
|
||||
gpu3d_shader 74
|
||||
ipu1_podf 75
|
||||
ipu2_podf 76
|
||||
ldb_di0_podf 77
|
||||
ldb_di1_podf 78
|
||||
ipu1_di0_pre 79
|
||||
ipu1_di1_pre 80
|
||||
ipu2_di0_pre 81
|
||||
ipu2_di1_pre 82
|
||||
hsi_tx_podf 83
|
||||
ssi1_pred 84
|
||||
ssi1_podf 85
|
||||
ssi2_pred 86
|
||||
ssi2_podf 87
|
||||
ssi3_pred 88
|
||||
ssi3_podf 89
|
||||
uart_serial_podf 90
|
||||
usdhc1_podf 91
|
||||
usdhc2_podf 92
|
||||
usdhc3_podf 93
|
||||
usdhc4_podf 94
|
||||
enfc_pred 95
|
||||
enfc_podf 96
|
||||
emi_podf 97
|
||||
emi_slow_podf 98
|
||||
vpu_axi_podf 99
|
||||
cko1_podf 100
|
||||
axi 101
|
||||
mmdc_ch0_axi_podf 102
|
||||
mmdc_ch1_axi_podf 103
|
||||
arm 104
|
||||
ahb 105
|
||||
apbh_dma 106
|
||||
asrc 107
|
||||
can1_ipg 108
|
||||
can1_serial 109
|
||||
can2_ipg 110
|
||||
can2_serial 111
|
||||
ecspi1 112
|
||||
ecspi2 113
|
||||
ecspi3 114
|
||||
ecspi4 115
|
||||
ecspi5 116
|
||||
enet 117
|
||||
esai 118
|
||||
gpt_ipg 119
|
||||
gpt_ipg_per 120
|
||||
gpu2d_core 121
|
||||
gpu3d_core 122
|
||||
hdmi_iahb 123
|
||||
hdmi_isfr 124
|
||||
i2c1 125
|
||||
i2c2 126
|
||||
i2c3 127
|
||||
iim 128
|
||||
enfc 129
|
||||
ipu1 130
|
||||
ipu1_di0 131
|
||||
ipu1_di1 132
|
||||
ipu2 133
|
||||
ipu2_di0 134
|
||||
ldb_di0 135
|
||||
ldb_di1 136
|
||||
ipu2_di1 137
|
||||
hsi_tx 138
|
||||
mlb 139
|
||||
mmdc_ch0_axi 140
|
||||
mmdc_ch1_axi 141
|
||||
ocram 142
|
||||
openvg_axi 143
|
||||
pcie_axi 144
|
||||
pwm1 145
|
||||
pwm2 146
|
||||
pwm3 147
|
||||
pwm4 148
|
||||
per1_bch 149
|
||||
gpmi_bch_apb 150
|
||||
gpmi_bch 151
|
||||
gpmi_io 152
|
||||
gpmi_apb 153
|
||||
sata 154
|
||||
sdma 155
|
||||
spba 156
|
||||
ssi1 157
|
||||
ssi2 158
|
||||
ssi3 159
|
||||
uart_ipg 160
|
||||
uart_serial 161
|
||||
usboh3 162
|
||||
usdhc1 163
|
||||
usdhc2 164
|
||||
usdhc3 165
|
||||
usdhc4 166
|
||||
vdo_axi 167
|
||||
vpu_axi 168
|
||||
cko1 169
|
||||
pll1_sys 170
|
||||
pll2_bus 171
|
||||
pll3_usb_otg 172
|
||||
pll4_audio 173
|
||||
pll5_video 174
|
||||
pll8_mlb 175
|
||||
pll7_usb_host 176
|
||||
pll6_enet 177
|
||||
ssi1_ipg 178
|
||||
ssi2_ipg 179
|
||||
ssi3_ipg 180
|
||||
rom 181
|
||||
usbphy1 182
|
||||
usbphy2 183
|
||||
ldb_di0_div_3_5 184
|
||||
ldb_di1_div_3_5 185
|
||||
sata_ref 186
|
||||
sata_ref_100m 187
|
||||
pcie_ref 188
|
||||
pcie_ref_125m 189
|
||||
enet_ref 190
|
||||
usbphy1_gate 191
|
||||
usbphy2_gate 192
|
||||
pll4_post_div 193
|
||||
pll5_post_div 194
|
||||
pll5_video_div 195
|
||||
eim_slow 196
|
||||
spdif 197
|
||||
cko2_sel 198
|
||||
cko2_podf 199
|
||||
cko2 200
|
||||
cko 201
|
||||
vdoa 202
|
||||
pll4_audio_div 203
|
||||
lvds1_sel 204
|
||||
lvds2_sel 205
|
||||
lvds1_gate 206
|
||||
lvds2_gate 207
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
|
||||
for the full list of i.MX6 Quad and DualLite clock IDs.
|
||||
|
||||
Examples:
|
||||
|
||||
#include <dt-bindings/clock/imx6qdl-clock.h>
|
||||
|
||||
clks: ccm@020c4000 {
|
||||
compatible = "fsl,imx6q-ccm";
|
||||
reg = <0x020c4000 0x4000>;
|
||||
@ -234,7 +25,7 @@ uart1: serial@02020000 {
|
||||
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -11,19 +11,41 @@ The following is a list of provided IDs and clock names on Armada 370/XP:
|
||||
3 = hclk (DRAM control clock)
|
||||
4 = dramclk (DDR clock)
|
||||
|
||||
The following is a list of provided IDs and clock names on Armada 375:
|
||||
0 = tclk (Internal Bus clock)
|
||||
1 = cpuclk (CPU clock)
|
||||
2 = l2clk (L2 Cache clock)
|
||||
3 = ddrclk (DDR clock)
|
||||
|
||||
The following is a list of provided IDs and clock names on Armada 380/385:
|
||||
0 = tclk (Internal Bus clock)
|
||||
1 = cpuclk (CPU clock)
|
||||
2 = l2clk (L2 Cache clock)
|
||||
3 = ddrclk (DDR clock)
|
||||
|
||||
The following is a list of provided IDs and clock names on Kirkwood and Dove:
|
||||
0 = tclk (Internal Bus clock)
|
||||
1 = cpuclk (CPU0 clock)
|
||||
2 = l2clk (L2 Cache clock derived from CPU0 clock)
|
||||
3 = ddrclk (DDR controller clock derived from CPU0 clock)
|
||||
|
||||
The following is a list of provided IDs and clock names on Orion5x:
|
||||
0 = tclk (Internal Bus clock)
|
||||
1 = cpuclk (CPU0 clock)
|
||||
2 = ddrclk (DDR controller clock derived from CPU0 clock)
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
|
||||
"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
|
||||
"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
|
||||
"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
|
||||
"marvell,dove-core-clock" - for Dove SoC core clocks
|
||||
"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
|
||||
"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
|
||||
"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
|
||||
"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
|
||||
"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
|
||||
- reg : shall be the register address of the Sample-At-Reset (SAR) register
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
|
||||
|
||||
@ -4,7 +4,10 @@ The following is a list of provided IDs and clock names on Armada 370/XP:
|
||||
0 = nand (NAND clock)
|
||||
|
||||
Required properties:
|
||||
- compatible : must be "marvell,armada-370-corediv-clock"
|
||||
- compatible : must be "marvell,armada-370-corediv-clock",
|
||||
"marvell,armada-375-corediv-clock",
|
||||
"marvell,armada-380-corediv-clock",
|
||||
|
||||
- reg : must be the register address of Core Divider control register
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
- clocks : must be set to the parent's phandle
|
||||
|
||||
@ -3,14 +3,15 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
|
||||
- reg : Address and length of the clock complex register set
|
||||
- reg : Address and length of the clock complex register set, followed
|
||||
by address and length of the PMU DFS registers
|
||||
- #clock-cells : should be set to 1.
|
||||
- clocks : shall be the input parent clock phandle for the clock.
|
||||
|
||||
cpuclk: clock-complex@d0018700 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "marvell,armada-xp-cpu-clock";
|
||||
reg = <0xd0018700 0xA0>;
|
||||
reg = <0xd0018700 0xA0>, <0x1c054 0x10>;
|
||||
clocks = <&coreclk 1>;
|
||||
}
|
||||
|
||||
|
||||
@ -1,9 +1,10 @@
|
||||
* Gated Clock bindings for Marvell EBU SoCs
|
||||
|
||||
Marvell Armada 370/XP, Dove and Kirkwood allow some peripheral clocks to be
|
||||
gated to save some power. The clock consumer should specify the desired clock
|
||||
by having the clock ID in its "clocks" phandle cell. The clock ID is directly
|
||||
mapped to the corresponding clock gating control bit in HW to ease manual clock
|
||||
Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some
|
||||
peripheral clocks to be gated to save some power. The clock consumer
|
||||
should specify the desired clock by having the clock ID in its
|
||||
"clocks" phandle cell. The clock ID is directly mapped to the
|
||||
corresponding clock gating control bit in HW to ease manual clock
|
||||
lookup in datasheet.
|
||||
|
||||
The following is a list of provided IDs for Armada 370:
|
||||
@ -22,6 +23,60 @@ ID Clock Peripheral
|
||||
28 ddr DDR Cntrl
|
||||
30 sata1 SATA Host 0
|
||||
|
||||
The following is a list of provided IDs for Armada 375:
|
||||
ID Clock Peripheral
|
||||
-----------------------------------
|
||||
2 mu Management Unit
|
||||
3 pp Packet Processor
|
||||
4 ptp PTP
|
||||
5 pex0 PCIe 0 Clock out
|
||||
6 pex1 PCIe 1 Clock out
|
||||
8 audio Audio Cntrl
|
||||
11 nd_clk Nand Flash Cntrl
|
||||
14 sata0_link SATA 0 Link
|
||||
15 sata0_core SATA 0 Core
|
||||
16 usb3 USB3 Host
|
||||
17 sdio SDHCI Host
|
||||
18 usb USB Host
|
||||
19 gop Gigabit Ethernet MAC
|
||||
20 sata1_link SATA 1 Link
|
||||
21 sata1_core SATA 1 Core
|
||||
22 xor0 XOR DMA 0
|
||||
23 xor1 XOR DMA 0
|
||||
24 copro Coprocessor
|
||||
25 tdm Time Division Mplx
|
||||
28 crypto0_enc Cryptographic Unit Port 0 Encryption
|
||||
29 crypto0_core Cryptographic Unit Port 0 Core
|
||||
30 crypto1_enc Cryptographic Unit Port 1 Encryption
|
||||
31 crypto1_core Cryptographic Unit Port 1 Core
|
||||
|
||||
The following is a list of provided IDs for Armada 380/385:
|
||||
ID Clock Peripheral
|
||||
-----------------------------------
|
||||
0 audio Audio
|
||||
2 ge2 Gigabit Ethernet 2
|
||||
3 ge1 Gigabit Ethernet 1
|
||||
4 ge0 Gigabit Ethernet 0
|
||||
5 pex1 PCIe 1
|
||||
6 pex2 PCIe 2
|
||||
7 pex3 PCIe 3
|
||||
8 pex0 PCIe 0
|
||||
9 usb3h0 USB3 Host 0
|
||||
10 usb3h1 USB3 Host 1
|
||||
11 usb3d USB3 Device
|
||||
13 bm Buffer Management
|
||||
14 crypto0z Cryptographic 0 Z
|
||||
15 sata0 SATA 0
|
||||
16 crypto1z Cryptographic 1 Z
|
||||
17 sdio SDIO
|
||||
18 usb2 USB 2
|
||||
21 crypto1 Cryptographic 1
|
||||
22 xor0 XOR 0
|
||||
23 crypto0 Cryptographic 0
|
||||
25 tdm Time Division Multiplexing
|
||||
28 xor1 XOR 1
|
||||
30 sata1 SATA 1
|
||||
|
||||
The following is a list of provided IDs for Armada XP:
|
||||
ID Clock Peripheral
|
||||
-----------------------------------
|
||||
@ -95,6 +150,8 @@ ID Clock Peripheral
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
|
||||
"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
|
||||
"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
|
||||
"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
|
||||
"marvell,dove-gating-clock" - for Dove SoC clock gating
|
||||
"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
|
||||
|
||||
@ -4,9 +4,14 @@ Qualcomm Global Clock & Reset Controller Binding
|
||||
Required properties :
|
||||
- compatible : shall contain only one of the following:
|
||||
|
||||
"qcom,gcc-apq8064"
|
||||
"qcom,gcc-apq8084"
|
||||
"qcom,gcc-ipq8064"
|
||||
"qcom,gcc-msm8660"
|
||||
"qcom,gcc-msm8960"
|
||||
"qcom,gcc-msm8974"
|
||||
"qcom,gcc-msm8974pro"
|
||||
"qcom,gcc-msm8974pro-ac"
|
||||
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : shall contain 1
|
||||
|
||||
@ -4,6 +4,8 @@ Qualcomm Multimedia Clock & Reset Controller Binding
|
||||
Required properties :
|
||||
- compatible : shall contain only one of the following:
|
||||
|
||||
"qcom,mmcc-apq8064"
|
||||
"qcom,mmcc-apq8084"
|
||||
"qcom,mmcc-msm8660"
|
||||
"qcom,mmcc-msm8960"
|
||||
"qcom,mmcc-msm8974"
|
||||
|
||||
@ -10,6 +10,8 @@ index in the group, from 0 to 31.
|
||||
Required Properties:
|
||||
|
||||
- compatible: Must be one of the following
|
||||
- "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
|
||||
- "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
|
||||
- "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
|
||||
- "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
|
||||
- "renesas,cpg-mstp-clock" for generic MSTP gate clocks
|
||||
@ -21,9 +23,9 @@ Required Properties:
|
||||
must appear in the same order as the output clocks.
|
||||
- #clock-cells: Must be 1
|
||||
- clock-output-names: The name of the clocks as free-form strings
|
||||
- renesas,indices: Indices of the gate clocks into the group (0 to 31)
|
||||
- renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
|
||||
|
||||
The clocks, clock-output-names and renesas,indices properties contain one
|
||||
The clocks, clock-output-names and renesas,clock-indices properties contain one
|
||||
entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
|
||||
gate clocks must not be declared.
|
||||
|
||||
@ -43,7 +45,7 @@ Example
|
||||
clock-output-names =
|
||||
"tpu0", "mmcif1", "sdhi3", "sdhi2",
|
||||
"sdhi1", "sdhi0", "mmcif0";
|
||||
renesas,clock-indices = <
|
||||
clock-indices = <
|
||||
R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
|
||||
R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
|
||||
R8A7790_CLK_MMCIF0
|
||||
|
||||
@ -6,6 +6,9 @@ This binding uses the common clock binding[1].
|
||||
|
||||
== Gate clocks ==
|
||||
|
||||
These bindings are deprecated!
|
||||
Please use the soc specific CRU bindings instead.
|
||||
|
||||
The gate registers form a continuos block which makes the dt node
|
||||
structure a matter of taste, as either all gates can be put into
|
||||
one gate clock spanning all registers or they can be divided into
|
||||
|
||||
@ -6,37 +6,52 @@ This binding uses the common clock binding[1].
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of the following:
|
||||
"allwinner,sun4i-osc-clk" - for a gatable oscillator
|
||||
"allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
|
||||
"allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
|
||||
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
|
||||
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
|
||||
"allwinner,sun4i-pll5-clk" - for the PLL5 clock
|
||||
"allwinner,sun4i-pll6-clk" - for the PLL6 clock
|
||||
"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
|
||||
"allwinner,sun4i-axi-clk" - for the AXI clock
|
||||
"allwinner,sun4i-axi-gates-clk" - for the AXI gates
|
||||
"allwinner,sun4i-ahb-clk" - for the AHB clock
|
||||
"allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
|
||||
"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
|
||||
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
|
||||
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
|
||||
"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
|
||||
"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
|
||||
"allwinner,sun4i-a10-axi-clk" - for the AXI clock
|
||||
"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
|
||||
"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
|
||||
"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
|
||||
"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
|
||||
"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
|
||||
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
|
||||
"allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
|
||||
"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
|
||||
"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
|
||||
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
|
||||
"allwinner,sun4i-apb0-clk" - for the APB0 clock
|
||||
"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
|
||||
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
|
||||
"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
|
||||
"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
|
||||
"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
|
||||
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
|
||||
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
|
||||
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
|
||||
"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
|
||||
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
|
||||
"allwinner,sun4i-apb1-clk" - for the APB1 clock
|
||||
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
|
||||
"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
|
||||
"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
|
||||
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
|
||||
"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
|
||||
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
|
||||
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
|
||||
"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
|
||||
"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
|
||||
"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
|
||||
"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
|
||||
"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
|
||||
"allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
|
||||
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
|
||||
"allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
|
||||
"allwinner,sun7i-a20-out-clk" - for the external output clocks
|
||||
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
|
||||
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
|
||||
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
|
||||
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
|
||||
|
||||
Required properties for all clocks:
|
||||
- reg : shall be the control register address for the clock.
|
||||
@ -44,10 +59,17 @@ Required properties for all clocks:
|
||||
multiplexed clocks, the list order must match the hardware
|
||||
programming order.
|
||||
- #clock-cells : from common clock binding; shall be set to 0 except for
|
||||
"allwinner,*-gates-clk" where it shall be set to 1
|
||||
"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
|
||||
"allwinner,sun4i-pll6-clk" where it shall be set to 1
|
||||
- clock-output-names : shall be the corresponding names of the outputs.
|
||||
If the clock module only has one output, the name shall be the
|
||||
module name.
|
||||
|
||||
Additionally, "allwinner,*-gates-clk" clocks require:
|
||||
- clock-output-names : the corresponding gate names that the clock controls
|
||||
And "allwinner,*-usb-clk" clocks also require:
|
||||
- reset-cells : shall be set to 1
|
||||
|
||||
For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
|
||||
dummy clocks at 25 MHz and 125 MHz, respectively. See example.
|
||||
|
||||
Clock consumers should specify the desired clocks they use with a
|
||||
"clocks" phandle cell. Consumers that are using a gated clock should
|
||||
@ -56,23 +78,68 @@ offset of the bit controlling this particular gate in the register.
|
||||
|
||||
For example:
|
||||
|
||||
osc24M: osc24M@01c20050 {
|
||||
osc24M: clk@01c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-osc-clk";
|
||||
compatible = "allwinner,sun4i-a10-osc-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
clocks = <&osc24M_fixed>;
|
||||
clock-output-names = "osc24M";
|
||||
};
|
||||
|
||||
pll1: pll1@01c20000 {
|
||||
pll1: clk@01c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-pll1-clk";
|
||||
compatible = "allwinner,sun4i-a10-pll1-clk";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll1";
|
||||
};
|
||||
|
||||
pll5: clk@01c20020 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-pll5-clk";
|
||||
reg = <0x01c20020 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
clock-output-names = "pll5_ddr", "pll5_other";
|
||||
};
|
||||
|
||||
cpu: cpu@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-cpu-clk";
|
||||
compatible = "allwinner,sun4i-a10-cpu-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>;
|
||||
clock-output-names = "cpu";
|
||||
};
|
||||
|
||||
mmc0_clk: clk@01c20088 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-mod0-clk";
|
||||
reg = <0x01c20088 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc0";
|
||||
};
|
||||
|
||||
mii_phy_tx_clk: clk@2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "mii_phy_tx";
|
||||
};
|
||||
|
||||
gmac_int_tx_clk: clk@3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "gmac_int_tx";
|
||||
};
|
||||
|
||||
gmac_clk: clk@01c20164 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun7i-a20-gmac-clk";
|
||||
reg = <0x01c20164 0x4>;
|
||||
/*
|
||||
* The first clock must be fixed at 25MHz;
|
||||
* the second clock must be fixed at 125MHz
|
||||
*/
|
||||
clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
|
||||
clock-output-names = "gmac";
|
||||
};
|
||||
|
||||
@ -14,18 +14,32 @@ a subtype of a DPLL [2], although a simplified one at that.
|
||||
[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,dra7-apll-clock"
|
||||
- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
|
||||
- reg : address and length of the register set for controlling the APLL.
|
||||
It contains the information of registers in the following order:
|
||||
"control" - contains the control register base address
|
||||
"idlest" - contains the idlest register base address
|
||||
"control" - contains the control register offset
|
||||
"idlest" - contains the idlest register offset
|
||||
"autoidle" - contains the autoidle register offset (OMAP2 only)
|
||||
- ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
|
||||
- ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)
|
||||
- ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)
|
||||
|
||||
Examples:
|
||||
apll_pcie_ck: apll_pcie_ck@4a008200 {
|
||||
apll_pcie_ck: apll_pcie_ck {
|
||||
#clock-cells = <0>;
|
||||
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
|
||||
reg = <0x4a00821c 0x4>, <0x4a008220 0x4>;
|
||||
reg = <0x021c>, <0x0220>;
|
||||
compatible = "ti,dra7-apll-clock";
|
||||
};
|
||||
|
||||
apll96_ck: apll96_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap2-apll-clock";
|
||||
clocks = <&sys_ck>;
|
||||
ti,bit-shift = <2>;
|
||||
ti,idlest-shift = <8>;
|
||||
ti,clock-frequency = <96000000>;
|
||||
reg = <0x0500>, <0x0530>, <0x0520>;
|
||||
};
|
||||
|
||||
@ -24,12 +24,14 @@ Required properties:
|
||||
"ti,omap4-dpll-core-clock",
|
||||
"ti,omap4-dpll-m4xen-clock",
|
||||
"ti,omap4-dpll-j-type-clock",
|
||||
"ti,omap5-mpu-dpll-clock",
|
||||
"ti,am3-dpll-no-gate-clock",
|
||||
"ti,am3-dpll-j-type-clock",
|
||||
"ti,am3-dpll-no-gate-j-type-clock",
|
||||
"ti,am3-dpll-clock",
|
||||
"ti,am3-dpll-core-clock",
|
||||
"ti,am3-dpll-x2-clock",
|
||||
"ti,omap2-dpll-core-clock",
|
||||
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles of parent clocks, first entry lists reference clock
|
||||
@ -41,6 +43,7 @@ Required properties:
|
||||
"mult-div1" - contains the multiplier / divider register base address
|
||||
"autoidle" - contains the autoidle register base address (optional)
|
||||
ti,am3-* dpll types do not have autoidle register
|
||||
ti,omap2-* dpll type does not support idlest / autoidle registers
|
||||
|
||||
Optional properties:
|
||||
- DPLL mode setting - defining any one or more of the following overrides
|
||||
@ -73,3 +76,10 @@ Examples:
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x90>, <0x5c>, <0x68>;
|
||||
};
|
||||
|
||||
dpll_ck: dpll_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap2-dpll-core-clock";
|
||||
clocks = <&sys_ck>, <&sys_ck>;
|
||||
reg = <0x0500>, <0x0540>;
|
||||
};
|
||||
|
||||
@ -25,6 +25,11 @@ Required properties:
|
||||
to map clockdomains properly
|
||||
"ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
|
||||
required for a hardware errata
|
||||
"ti,composite-gate-clock" - composite gate clock, to be part of composite
|
||||
clock
|
||||
"ti,composite-no-wait-gate-clock" - composite gate clock that does not wait
|
||||
for clock to be active before returning
|
||||
from clk_enable()
|
||||
- #clock-cells : from common clock binding; shall be set to 0
|
||||
- clocks : link to phandle of parent clock
|
||||
- reg : offset for register controlling adjustable gate, not needed for
|
||||
@ -41,7 +46,7 @@ Examples:
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&core_96m_fck>;
|
||||
reg = <0x48004a00 0x4>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <25>;
|
||||
};
|
||||
|
||||
@ -57,7 +62,7 @@ Examples:
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,dss-gate-clock";
|
||||
clocks = <&dpll4_m4x2_ck>;
|
||||
reg = <0x48004e00 0x4>;
|
||||
reg = <0x0e00>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
@ -65,7 +70,7 @@ Examples:
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-gate-clock";
|
||||
clocks = <&ipss_ick>;
|
||||
reg = <0x4800259c 0x4>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
@ -80,6 +85,22 @@ Examples:
|
||||
compatible = "ti,hsdiv-gate-clock";
|
||||
clocks = <&dpll4_m2x2_mul_ck>;
|
||||
ti,bit-shift = <0x1b>;
|
||||
reg = <0x48004d00 0x4>;
|
||||
reg = <0x0d00>;
|
||||
ti,set-bit-to-disable;
|
||||
};
|
||||
|
||||
vlynq_gate_fck: vlynq_gate_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-gate-clock";
|
||||
clocks = <&core_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
reg = <0x0200>;
|
||||
};
|
||||
|
||||
sys_clkout2_src_gate: sys_clkout2_src_gate {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-no-wait-gate-clock";
|
||||
clocks = <&core_ck>;
|
||||
ti,bit-shift = <15>;
|
||||
reg = <0x0070>;
|
||||
};
|
||||
|
||||
@ -21,6 +21,8 @@ Required properties:
|
||||
"ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
|
||||
"ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
|
||||
"ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
|
||||
"ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW
|
||||
handling
|
||||
- #clock-cells : from common clock binding; shall be set to 0
|
||||
- clocks : link to phandle of parent clock
|
||||
- reg : base address for the control register
|
||||
|
||||
@ -14,6 +14,7 @@ for all clock consumers of PS clocks.
|
||||
Required properties:
|
||||
- #clock-cells : Must be 1
|
||||
- compatible : "xlnx,ps7-clkc"
|
||||
- reg : SLCR offset and size taken via syscon < 0x100 0x100 >
|
||||
- ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
|
||||
(usually 33 MHz oscillators are used for Zynq platforms)
|
||||
- clock-output-names : List of strings used to name the clock outputs. Shall be
|
||||
@ -87,10 +88,11 @@ Clock outputs:
|
||||
47: dbg_apb
|
||||
|
||||
Example:
|
||||
clkc: clkc {
|
||||
clkc: clkc@100 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "xlnx,ps7-clkc";
|
||||
ps-clk-frequency = <33333333>;
|
||||
reg = <0x100 0x100>;
|
||||
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
|
||||
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
|
||||
"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
|
||||
|
||||
@ -8,10 +8,12 @@ Both required and optional properties listed below must be defined
|
||||
under node /cpus/cpu@0.
|
||||
|
||||
Required properties:
|
||||
- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt
|
||||
for details
|
||||
- None
|
||||
|
||||
Optional properties:
|
||||
- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt for
|
||||
details. OPPs *must* be supplied either via DT, i.e. this property, or
|
||||
populated at runtime.
|
||||
- clock-latency: Specify the possible maximum transition latency for clock,
|
||||
in unit of nanoseconds.
|
||||
- voltage-tolerance: Specify the CPU voltage tolerance in percentage.
|
||||
|
||||
@ -14,7 +14,7 @@ Required property:
|
||||
|
||||
Optional properties:
|
||||
- dma-channels: Number of DMA channels supported by the controller.
|
||||
- dma-requests: Number of DMA requests signals supported by the
|
||||
- dma-requests: Number of DMA request signals supported by the
|
||||
controller.
|
||||
|
||||
Example:
|
||||
@ -44,7 +44,7 @@ Required property:
|
||||
#dma-cells property in the node referenced by phandle
|
||||
containing DMA controller specific information. This
|
||||
typically contains a DMA request line number or a
|
||||
channel number, but can contain any data that is used
|
||||
channel number, but can contain any data that is
|
||||
required for configuring a channel.
|
||||
- dma-names: Contains one identifier string for each DMA specifier in
|
||||
the dmas property. The specific strings that can be used
|
||||
|
||||
@ -1,12 +1,16 @@
|
||||
* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,imx31-sdma", "fsl,imx31-to1-sdma",
|
||||
"fsl,imx31-to2-sdma", "fsl,imx35-sdma", "fsl,imx35-to1-sdma",
|
||||
"fsl,imx35-to2-sdma", "fsl,imx51-sdma", "fsl,imx53-sdma" or
|
||||
"fsl,imx6q-sdma". The -to variants should be preferred since they
|
||||
allow to determnine the correct ROM script addresses needed for
|
||||
the driver to work without additional firmware.
|
||||
- compatible : Should be one of
|
||||
"fsl,imx25-sdma"
|
||||
"fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
|
||||
"fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
|
||||
"fsl,imx51-sdma"
|
||||
"fsl,imx53-sdma"
|
||||
"fsl,imx6q-sdma"
|
||||
The -to variants should be preferred since they allow to determine the
|
||||
correct ROM script addresses needed for the driver to work without additional
|
||||
firmware.
|
||||
- reg : Should contain SDMA registers location and length
|
||||
- interrupts : Should contain SDMA interrupt
|
||||
- #dma-cells : Must be <3>.
|
||||
@ -43,6 +47,7 @@ The full ID of peripheral types can be found below.
|
||||
20 ASRC
|
||||
21 ESAI
|
||||
22 SSI Dual FIFO (needs firmware ver >= 2)
|
||||
23 Shared ASRC
|
||||
|
||||
The third cell specifies the transfer priority as below.
|
||||
|
||||
|
||||
@ -1,17 +1,20 @@
|
||||
* MARVELL MMP DMA controller
|
||||
|
||||
Marvell Peripheral DMA Controller
|
||||
Used platfroms: pxa688, pxa910, pxa3xx, etc
|
||||
Used platforms: pxa688, pxa910, pxa3xx, etc
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "marvell,pdma-1.0"
|
||||
- reg: Should contain DMA registers location and length.
|
||||
- interrupts: Either contain all of the per-channel DMA interrupts
|
||||
or one irq for pdma device
|
||||
- #dma-channels: Number of DMA channels supported by the controller.
|
||||
|
||||
Optional properties:
|
||||
- #dma-channels: Number of DMA channels supported by the controller (defaults
|
||||
to 32 when not specified)
|
||||
|
||||
"marvell,pdma-1.0"
|
||||
Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
|
||||
Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
|
||||
|
||||
Examples:
|
||||
|
||||
@ -45,7 +48,7 @@ pdma: dma-controller@d4000000 {
|
||||
|
||||
|
||||
Marvell Two Channel DMA Controller used specifically for audio
|
||||
Used platfroms: pxa688, pxa910
|
||||
Used platforms: pxa688, pxa910
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"
|
||||
|
||||
@ -35,9 +35,11 @@ Required properties:
|
||||
|
||||
Each dmas request consists of 4 cells:
|
||||
1. A phandle pointing to the DMA controller
|
||||
2. Device Type
|
||||
2. Device signal number, the signal line for single and burst requests
|
||||
connected from the device to the DMA40 engine
|
||||
3. The DMA request line number (only when 'use fixed channel' is set)
|
||||
4. A 32bit mask specifying; mode, direction and endianness [NB: This list will grow]
|
||||
4. A 32bit mask specifying; mode, direction and endianness
|
||||
[NB: This list will grow]
|
||||
0x00000001: Mode:
|
||||
Logical channel when unset
|
||||
Physical channel when set
|
||||
@ -54,6 +56,74 @@ Each dmas request consists of 4 cells:
|
||||
Normal priority when unset
|
||||
High priority when set
|
||||
|
||||
Existing signal numbers for the DB8500 ASIC. Unless specified, the signals are
|
||||
bidirectional, i.e. the same for RX and TX operations:
|
||||
|
||||
0: SPI controller 0
|
||||
1: SD/MMC controller 0 (unused)
|
||||
2: SD/MMC controller 1 (unused)
|
||||
3: SD/MMC controller 2 (unused)
|
||||
4: I2C port 1
|
||||
5: I2C port 3
|
||||
6: I2C port 2
|
||||
7: I2C port 4
|
||||
8: Synchronous Serial Port SSP0
|
||||
9: Synchronous Serial Port SSP1
|
||||
10: Multi-Channel Display Engine MCDE RX
|
||||
11: UART port 2
|
||||
12: UART port 1
|
||||
13: UART port 0
|
||||
14: Multirate Serial Port MSP2
|
||||
15: I2C port 0
|
||||
16: USB OTG in/out endpoints 7 & 15
|
||||
17: USB OTG in/out endpoints 6 & 14
|
||||
18: USB OTG in/out endpoints 5 & 13
|
||||
19: USB OTG in/out endpoints 4 & 12
|
||||
20: SLIMbus or HSI channel 0
|
||||
21: SLIMbus or HSI channel 1
|
||||
22: SLIMbus or HSI channel 2
|
||||
23: SLIMbus or HSI channel 3
|
||||
24: Multimedia DSP SXA0
|
||||
25: Multimedia DSP SXA1
|
||||
26: Multimedia DSP SXA2
|
||||
27: Multimedia DSP SXA3
|
||||
28: SD/MM controller 2
|
||||
29: SD/MM controller 0
|
||||
30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2
|
||||
31: MSP port 0 or SLIMbus channel 0
|
||||
32: SD/MM controller 1
|
||||
33: SPI controller 2
|
||||
34: i2c3 RX2 TX2
|
||||
35: SPI controller 1
|
||||
36: USB OTG in/out endpoints 3 & 11
|
||||
37: USB OTG in/out endpoints 2 & 10
|
||||
38: USB OTG in/out endpoints 1 & 9
|
||||
39: USB OTG in/out endpoints 8
|
||||
40: SPI controller 3
|
||||
41: SD/MM controller 3
|
||||
42: SD/MM controller 4
|
||||
43: SD/MM controller 5
|
||||
44: Multimedia DSP SXA4
|
||||
45: Multimedia DSP SXA5
|
||||
46: SLIMbus channel 8 or Multimedia DSP SXA6
|
||||
47: SLIMbus channel 9 or Multimedia DSP SXA7
|
||||
48: Crypto Accelerator 1
|
||||
49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
|
||||
50: Hash Accelerator 1 TX
|
||||
51: memcpy TX (to be used by the DMA driver for memcpy operations)
|
||||
52: SLIMbus or HSI channel 4
|
||||
53: SLIMbus or HSI channel 5
|
||||
54: SLIMbus or HSI channel 6
|
||||
55: SLIMbus or HSI channel 7
|
||||
56: memcpy (to be used by the DMA driver for memcpy operations)
|
||||
57: memcpy (to be used by the DMA driver for memcpy operations)
|
||||
58: memcpy (to be used by the DMA driver for memcpy operations)
|
||||
59: memcpy (to be used by the DMA driver for memcpy operations)
|
||||
60: memcpy (to be used by the DMA driver for memcpy operations)
|
||||
61: Crypto Accelerator 0
|
||||
62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
|
||||
63: Hash Accelerator 0 TX
|
||||
|
||||
Example:
|
||||
|
||||
uart@80120000 {
|
||||
|
||||
@ -2,11 +2,8 @@ TI EDMA
|
||||
|
||||
Required properties:
|
||||
- compatible : "ti,edma3"
|
||||
- ti,edma-regions: Number of regions
|
||||
- ti,edma-slots: Number of slots
|
||||
- #dma-cells: Should be set to <1>
|
||||
Clients should use a single channel number per DMA request.
|
||||
- dma-channels: Specify total DMA channels per CC
|
||||
- reg: Memory map for accessing module
|
||||
- interrupt-parent: Interrupt controller the interrupt is routed through
|
||||
- interrupts: Exactly 3 interrupts need to be specified in the order:
|
||||
@ -17,6 +14,13 @@ Optional properties:
|
||||
- ti,hwmods: Name of the hwmods associated to the EDMA
|
||||
- ti,edma-xbar-event-map: Crossbar event to channel map
|
||||
|
||||
Deprecated properties:
|
||||
Listed here in case one wants to boot an old kernel with new DTB. These
|
||||
properties might need to be added to the new DTS files.
|
||||
- ti,edma-regions: Number of regions
|
||||
- ti,edma-slots: Number of slots
|
||||
- dma-channels: Specify total DMA channels per CC
|
||||
|
||||
Example:
|
||||
|
||||
edma: edma@49000000 {
|
||||
@ -26,9 +30,6 @@ edma: edma@49000000 {
|
||||
compatible = "ti,edma3";
|
||||
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <64>;
|
||||
ti,edma-regions = <4>;
|
||||
ti,edma-slots = <256>;
|
||||
ti,edma-xbar-event-map = <1 12
|
||||
2 13>;
|
||||
ti,edma-xbar-event-map = /bits/ 16 <1 12
|
||||
2 13>;
|
||||
};
|
||||
|
||||
@ -1,13 +1,17 @@
|
||||
Davinci GPIO controller bindings
|
||||
Davinci/Keystone GPIO controller bindings
|
||||
|
||||
Required Properties:
|
||||
- compatible: should be "ti,dm6441-gpio"
|
||||
- compatible: should be "ti,dm6441-gpio", "ti,keystone-gpio"
|
||||
|
||||
- reg: Physical base address of the controller and the size of memory mapped
|
||||
registers.
|
||||
|
||||
- gpio-controller : Marks the device node as a gpio controller.
|
||||
|
||||
- #gpio-cells : Should be two.
|
||||
- first cell is the pin number
|
||||
- second cell is used to specify optional parameters (unused)
|
||||
|
||||
- interrupt-parent: phandle of the parent interrupt controller.
|
||||
|
||||
- interrupts: Array of GPIO interrupt number. Only banked or unbanked IRQs are
|
||||
@ -27,6 +31,7 @@ Example:
|
||||
gpio: gpio@1e26000 {
|
||||
compatible = "ti,dm6441-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x226000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <42 IRQ_TYPE_EDGE_BOTH 43 IRQ_TYPE_EDGE_BOTH
|
||||
@ -39,3 +44,19 @@ gpio: gpio@1e26000 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led1 {
|
||||
label = "davinci:green:usr1";
|
||||
gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
|
||||
...
|
||||
};
|
||||
|
||||
led2 {
|
||||
label = "davinci:red:debug1";
|
||||
gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
|
||||
...
|
||||
};
|
||||
};
|
||||
|
||||
@ -54,7 +54,7 @@ Optional device specific properties:
|
||||
IO 8-15 are bank 2. These chips have two different interrupt outputs:
|
||||
One for bank 1 and another for bank 2. If irq-mirror is set, both
|
||||
interrupts are generated regardless of the bank that an input change
|
||||
occured on. If it is not set, the interrupt are only generated for the
|
||||
occurred on. If it is not set, the interrupt are only generated for the
|
||||
bank they belong to.
|
||||
On devices with only one interrupt output this property is useless.
|
||||
|
||||
|
||||
@ -13,11 +13,11 @@ properties, each containing a 'gpio-list':
|
||||
gpio-specifier : Array of #gpio-cells specifying specific gpio
|
||||
(controller specific)
|
||||
|
||||
GPIO properties should be named "[<name>-]gpios". Exact
|
||||
GPIO properties should be named "[<name>-]gpios". The exact
|
||||
meaning of each gpios property must be documented in the device tree
|
||||
binding for each device.
|
||||
|
||||
For example, the following could be used to describe gpios pins to use
|
||||
For example, the following could be used to describe GPIO pins used
|
||||
as chip select lines; with chip selects 0, 1 and 3 populated, and chip
|
||||
select 2 left empty:
|
||||
|
||||
@ -44,35 +44,79 @@ whether pin is open-drain and whether pin is logically inverted.
|
||||
Exact meaning of each specifier cell is controller specific, and must
|
||||
be documented in the device tree binding for the device.
|
||||
|
||||
Example of the node using GPIOs:
|
||||
Example of a node using GPIOs:
|
||||
|
||||
node {
|
||||
gpios = <&qe_pio_e 18 0>;
|
||||
};
|
||||
|
||||
In this example gpio-specifier is "18 0" and encodes GPIO pin number,
|
||||
and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
|
||||
and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
|
||||
|
||||
1.1) GPIO specifier best practices
|
||||
----------------------------------
|
||||
|
||||
A gpio-specifier should contain a flag indicating the GPIO polarity; active-
|
||||
high or active-low. If it does, the follow best practices should be followed:
|
||||
|
||||
The gpio-specifier's polarity flag should represent the physical level at the
|
||||
GPIO controller that achieves (or represents, for inputs) a logically asserted
|
||||
value at the device. The exact definition of logically asserted should be
|
||||
defined by the binding for the device. If the board inverts the signal between
|
||||
the GPIO controller and the device, then the gpio-specifier will represent the
|
||||
opposite physical level than the signal at the device's pin.
|
||||
|
||||
When the device's signal polarity is configurable, the binding for the
|
||||
device must either:
|
||||
|
||||
a) Define a single static polarity for the signal, with the expectation that
|
||||
any software using that binding would statically program the device to use
|
||||
that signal polarity.
|
||||
|
||||
The static choice of polarity may be either:
|
||||
|
||||
a1) (Preferred) Dictated by a binding-specific DT property.
|
||||
|
||||
or:
|
||||
|
||||
a2) Defined statically by the DT binding itself.
|
||||
|
||||
In particular, the polarity cannot be derived from the gpio-specifier, since
|
||||
that would prevent the DT from separately representing the two orthogonal
|
||||
concepts of configurable signal polarity in the device, and possible board-
|
||||
level signal inversion.
|
||||
|
||||
or:
|
||||
|
||||
b) Pick a single option for device signal polarity, and document this choice
|
||||
in the binding. The gpio-specifier should represent the polarity of the signal
|
||||
(at the GPIO controller) assuming that the device is configured for this
|
||||
particular signal polarity choice. If software chooses to program the device
|
||||
to generate or receive a signal of the opposite polarity, software will be
|
||||
responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
|
||||
controller.
|
||||
|
||||
2) gpio-controller nodes
|
||||
------------------------
|
||||
|
||||
Every GPIO controller node must both an empty "gpio-controller"
|
||||
property, and have #gpio-cells contain the size of the gpio-specifier.
|
||||
Every GPIO controller node must contain both an empty "gpio-controller"
|
||||
property, and a #gpio-cells integer property, which indicates the number of
|
||||
cells in a gpio-specifier.
|
||||
|
||||
Example of two SOC GPIO banks defined as gpio-controller nodes:
|
||||
|
||||
qe_pio_a: gpio-controller@1400 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
|
||||
reg = <0x1400 0x18>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
qe_pio_e: gpio-controller@1460 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
|
||||
reg = <0x1460 0x18>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
2.1) gpio- and pin-controller interaction
|
||||
|
||||
@ -21,6 +21,12 @@ Required Properties:
|
||||
GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
|
||||
- gpio-ranges: Range of pins managed by the GPIO controller.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- clocks: Must contain a reference to the functional clock. The property is
|
||||
mandatory if the hardware implements a controllable functional clock for
|
||||
the GPIO instance.
|
||||
|
||||
Please refer to gpio.txt in this directory for details of gpio-ranges property
|
||||
and the common GPIO bindings used by client devices.
|
||||
|
||||
|
||||
@ -136,6 +136,7 @@ of the following host1x client modules:
|
||||
- compatible: "nvidia,tegra<chip>-hdmi"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- hdmi-supply: supply for the +5V HDMI connector pin
|
||||
- vdd-supply: regulator for supply voltage
|
||||
- pll-supply: regulator for PLL
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
@ -180,6 +181,7 @@ of the following host1x client modules:
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- dsi
|
||||
- avdd-dsi-supply: phandle of a supply that powers the DSI controller
|
||||
- nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
|
||||
which pads are used by this DSI output and need to be calibrated. See also
|
||||
../mipi/nvidia,tegra114-mipi.txt.
|
||||
@ -190,6 +192,48 @@ of the following host1x client modules:
|
||||
- nvidia,edid: supplies a binary EDID blob
|
||||
- nvidia,panel: phandle of a display panel
|
||||
|
||||
- sor: serial output resource
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra124-sor"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- sor: clock input for the SOR hardware
|
||||
- parent: input for the pixel clock
|
||||
- dp: reference clock for the SOR clock
|
||||
- safe: safe reference for the SOR clock during power up
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- sor
|
||||
|
||||
Optional properties:
|
||||
- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
||||
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
|
||||
- nvidia,edid: supplies a binary EDID blob
|
||||
- nvidia,panel: phandle of a display panel
|
||||
|
||||
Optional properties when driving an eDP output:
|
||||
- nvidia,dpaux: phandle to a DispayPort AUX interface
|
||||
|
||||
- dpaux: DisplayPort AUX interface
|
||||
- compatible: "nvidia,tegra124-dpaux"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The interrupt outputs from the controller.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- dpaux: clock input for the DPAUX hardware
|
||||
- parent: reference clock
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- dpaux
|
||||
- vdd-supply: phandle of a supply that powers the DisplayPort link
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
|
||||
@ -3,11 +3,20 @@ NTC Thermistor hwmon sensors
|
||||
|
||||
Requires node properties:
|
||||
- "compatible" value : one of
|
||||
"ntc,ncp15wb473"
|
||||
"ntc,ncp18wb473"
|
||||
"ntc,ncp21wb473"
|
||||
"ntc,ncp03wb473"
|
||||
"ntc,ncp15wl333"
|
||||
"epcos,b57330v2103"
|
||||
"murata,ncp15wb473"
|
||||
"murata,ncp18wb473"
|
||||
"murata,ncp21wb473"
|
||||
"murata,ncp03wb473"
|
||||
"murata,ncp15wl333"
|
||||
|
||||
/* Usage of vendor name "ntc" is deprecated */
|
||||
<DEPRECATED> "ntc,ncp15wb473"
|
||||
<DEPRECATED> "ntc,ncp18wb473"
|
||||
<DEPRECATED> "ntc,ncp21wb473"
|
||||
<DEPRECATED> "ntc,ncp03wb473"
|
||||
<DEPRECATED> "ntc,ncp15wl333"
|
||||
|
||||
- "pullup-uv" Pull up voltage in micro volts
|
||||
- "pullup-ohm" Pull up resistor value in ohms
|
||||
- "pulldown-ohm" Pull down resistor value in ohms
|
||||
@ -21,7 +30,7 @@ Read more about iio bindings at
|
||||
|
||||
Example:
|
||||
ncp15wb473@0 {
|
||||
compatible = "ntc,ncp15wb473";
|
||||
compatible = "murata,ncp15wb473";
|
||||
pullup-uv = <1800000>;
|
||||
pullup-ohm = <47000>;
|
||||
pulldown-ohm = <0>;
|
||||
|
||||
@ -8,6 +8,12 @@ the standard I2C multi-master rules. Using GPIOs is generally useful in
|
||||
the case where there is a device on the bus that has errata and/or bugs
|
||||
that makes standard multimaster mode not feasible.
|
||||
|
||||
Note that this scheme works well enough but has some downsides:
|
||||
* It is nonstandard (not using standard I2C multimaster)
|
||||
* Having two masters on a bus in general makes it relatively hard to debug
|
||||
problems (hard to tell if i2c issues were caused by one master, another, or
|
||||
some device on the bus).
|
||||
|
||||
|
||||
Algorithm:
|
||||
|
||||
|
||||
@ -12,6 +12,7 @@ Required properties :
|
||||
- clocks: phandles to input clocks.
|
||||
|
||||
Optional properties:
|
||||
- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
|
||||
- Child nodes conforming to i2c bus binding
|
||||
|
||||
Examples :
|
||||
@ -23,6 +24,7 @@ i2c0: i2c@fff84000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&twi0_clk>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
24c512@50 {
|
||||
compatible = "24c512";
|
||||
|
||||
@ -14,6 +14,12 @@ Optional properties :
|
||||
- i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds.
|
||||
This option is only supported in hardware blocks version 1.11a or newer.
|
||||
|
||||
- i2c-scl-falling-time : should contain the SCL falling time in nanoseconds.
|
||||
This value which is by default 300ns is used to compute the tLOW period.
|
||||
|
||||
- i2c-sda-falling-time : should contain the SDA falling time in nanoseconds.
|
||||
This value which is by default 300ns is used to compute the tHIGH period.
|
||||
|
||||
Example :
|
||||
|
||||
i2c@f0000 {
|
||||
@ -34,4 +40,6 @@ Example :
|
||||
interrupts = <12 1>;
|
||||
clock-frequency = <400000>;
|
||||
i2c-sda-hold-time-ns = <300>;
|
||||
i2c-sda-falling-time-ns = <300>;
|
||||
i2c-scl-falling-time-ns = <300>;
|
||||
};
|
||||
|
||||
@ -5,7 +5,14 @@ at various speeds ranging from 100khz to 3.4Mhz.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be.
|
||||
-> "samsung,exynos5-hsi2c", for i2c compatible with exynos5 hsi2c.
|
||||
-> "samsung,exynos5-hsi2c", (DEPRECATED)
|
||||
for i2c compatible with HSI2C available
|
||||
on Exynos5250 and Exynos5420 SoCs.
|
||||
-> "samsung,exynos5250-hsi2c", for i2c compatible with HSI2C available
|
||||
on Exynos5250 and Exynos5420 SoCs.
|
||||
-> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available
|
||||
on Exynos5260 SoCs.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
@ -26,7 +33,7 @@ Optional properties:
|
||||
Example:
|
||||
|
||||
hsi2c@12ca0000 {
|
||||
compatible = "samsung,exynos5-hsi2c";
|
||||
compatible = "samsung,exynos5250-hsi2c";
|
||||
reg = <0x12ca0000 0x100>;
|
||||
interrupts = <56>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
@ -4,12 +4,16 @@
|
||||
Required properties :
|
||||
|
||||
- reg : Offset and length of the register set for the device
|
||||
- compatible : Should be "marvell,mv64xxx-i2c" or "allwinner,sun4i-i2c"
|
||||
or "marvell,mv78230-i2c" or "marvell,mv78230-a0-i2c"
|
||||
Note: Only use "marvell,mv78230-a0-i2c" for a very rare,
|
||||
initial version of the SoC which had broken offload
|
||||
support. Linux auto-detects this and sets it
|
||||
appropriately.
|
||||
- compatible : Should be either:
|
||||
- "allwinner,sun4i-a10-i2c"
|
||||
- "allwinner,sun6i-a31-i2c"
|
||||
- "marvell,mv64xxx-i2c"
|
||||
- "marvell,mv78230-i2c"
|
||||
- "marvell,mv78230-a0-i2c"
|
||||
* Note: Only use "marvell,mv78230-a0-i2c" for a
|
||||
very rare, initial version of the SoC which
|
||||
had broken offload support. Linux
|
||||
auto-detects this and sets it appropriately.
|
||||
- interrupts : The interrupt number
|
||||
|
||||
Optional properties :
|
||||
@ -17,6 +21,10 @@ Optional properties :
|
||||
- clock-frequency : Desired I2C bus clock frequency in Hz. If not set the
|
||||
default frequency is 100kHz
|
||||
|
||||
- resets : phandle to the parent reset controller. Mandatory
|
||||
whenever you're using the "allwinner,sun6i-a31-i2c"
|
||||
compatible.
|
||||
|
||||
Examples:
|
||||
|
||||
i2c@11000 {
|
||||
|
||||
@ -6,6 +6,10 @@ Required properties:
|
||||
"renesas,i2c-r8a7778"
|
||||
"renesas,i2c-r8a7779"
|
||||
"renesas,i2c-r8a7790"
|
||||
"renesas,i2c-r8a7791"
|
||||
"renesas,i2c-r8a7792"
|
||||
"renesas,i2c-r8a7793"
|
||||
"renesas,i2c-r8a7794"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt specifier.
|
||||
@ -13,11 +17,16 @@ Required properties:
|
||||
Optional properties:
|
||||
- clock-frequency: desired I2C bus clock frequency in Hz. The absence of this
|
||||
propoerty indicates the default frequency 100 kHz.
|
||||
- clocks: clock specifier.
|
||||
|
||||
Examples :
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
compatible = "renesas,i2c-rcar-h2";
|
||||
reg = <0 0xe6500000 0 0x428>;
|
||||
interrupts = <0 174 0x4>;
|
||||
i2c0: i2c@e6508000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "renesas,i2c-r8a7791";
|
||||
reg = <0 0xe6508000 0 0x40>;
|
||||
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
@ -13,11 +13,26 @@ ad,ad7414 SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert an
|
||||
ad,adm9240 ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
|
||||
adi,adt7461 +/-1C TDM Extended Temp Range I.C
|
||||
adt7461 +/-1C TDM Extended Temp Range I.C
|
||||
adi,adt7473 +/-1C TDM Extended Temp Range I.C
|
||||
adi,adt7475 +/-1C TDM Extended Temp Range I.C
|
||||
adi,adt7476 +/-1C TDM Extended Temp Range I.C
|
||||
adi,adt7490 +/-1C TDM Extended Temp Range I.C
|
||||
at,24c08 i2c serial eeprom (24cxx)
|
||||
atmel,24c00 i2c serial eeprom (24cxx)
|
||||
atmel,24c01 i2c serial eeprom (24cxx)
|
||||
atmel,24c02 i2c serial eeprom (24cxx)
|
||||
atmel,24c04 i2c serial eeprom (24cxx)
|
||||
atmel,24c16 i2c serial eeprom (24cxx)
|
||||
atmel,24c32 i2c serial eeprom (24cxx)
|
||||
atmel,24c64 i2c serial eeprom (24cxx)
|
||||
atmel,24c128 i2c serial eeprom (24cxx)
|
||||
atmel,24c256 i2c serial eeprom (24cxx)
|
||||
atmel,24c512 i2c serial eeprom (24cxx)
|
||||
atmel,24c1024 i2c serial eeprom (24cxx)
|
||||
atmel,at97sc3204t i2c trusted platform module (TPM)
|
||||
capella,cm32181 CM32181: Ambient Light Sensor
|
||||
catalyst,24c32 i2c serial eeprom
|
||||
cirrus,cs42l51 Cirrus Logic CS42L51 audio codec
|
||||
dallas,ds1307 64 x 8, Serial, I2C Real-Time Clock
|
||||
dallas,ds1338 I2C RTC with 56-Byte NV RAM
|
||||
dallas,ds1339 I2C Serial Real-Time Clock
|
||||
@ -35,6 +50,7 @@ epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
|
||||
fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
|
||||
fsl,mc13892 MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51
|
||||
fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer
|
||||
fsl,mma8452 MMA8452Q: 3-axis 12-bit / 8-bit Digital Accelerometer
|
||||
fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller
|
||||
fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec
|
||||
gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface
|
||||
@ -45,19 +61,23 @@ maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator
|
||||
maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
|
||||
maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
|
||||
mc,rv3029c2 Real Time Clock Module with I2C-Bus
|
||||
national,lm63 Temperature sensor with integrated fan control
|
||||
national,lm75 I2C TEMP SENSOR
|
||||
national,lm80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
|
||||
national,lm85 Temperature sensor with integrated fan control
|
||||
national,lm92 ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface
|
||||
nuvoton,npct501 i2c trusted platform module (TPM)
|
||||
nxp,pca9556 Octal SMBus and I2C registered interface
|
||||
nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
|
||||
nxp,pcf8563 Real-time clock/calendar
|
||||
nxp,pcf85063 Tiny Real-Time Clock
|
||||
ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
|
||||
pericom,pt7c4338 Real-time Clock Module
|
||||
plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
|
||||
ramtron,24c64 i2c serial eeprom (24cxx)
|
||||
ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
|
||||
samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
|
||||
sii,s35390a 2-wire CMOS real-time clock
|
||||
st-micro,24c256 i2c serial eeprom (24cxx)
|
||||
stm,m41t00 Serial Access TIMEKEEPER
|
||||
stm,m41t62 Serial real-time clock (RTC) with alarm
|
||||
@ -65,5 +85,6 @@ stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
|
||||
taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface
|
||||
ti,tsc2003 I2C Touch-Screen Controller
|
||||
ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
|
||||
ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
|
||||
ti,tmp275 Digital Temperature Sensor
|
||||
winbond,wpct301 i2c trusted platform module (TPM)
|
||||
|
||||
@ -3,6 +3,10 @@
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "honeywell,hmc5843"
|
||||
Other models which are supported with driver are:
|
||||
"honeywell,hmc5883"
|
||||
"honeywell,hmc5883l"
|
||||
"honeywell,hmc5983"
|
||||
- reg : the I2C address of the magnetometer - typically 0x1e
|
||||
|
||||
Optional properties:
|
||||
|
||||
@ -2,7 +2,7 @@ Allwinner Sunxi Interrupt Controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sun4i-ic"
|
||||
- compatible : should be "allwinner,sun4i-a10-ic"
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupt-controller : Identifies the node as an interrupt controller
|
||||
- #interrupt-cells : Specifies the number of cells needed to encode an
|
||||
@ -11,7 +11,7 @@ Required properties:
|
||||
Example:
|
||||
|
||||
intc: interrupt-controller {
|
||||
compatible = "allwinner,sun4i-ic";
|
||||
compatible = "allwinner,sun4i-a10-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
@ -4,11 +4,13 @@ Specifying interrupt information for devices
|
||||
1) Interrupt client nodes
|
||||
-------------------------
|
||||
|
||||
Nodes that describe devices which generate interrupts must contain an either an
|
||||
"interrupts" property or an "interrupts-extended" property. These properties
|
||||
contain a list of interrupt specifiers, one per output interrupt. The format of
|
||||
the interrupt specifier is determined by the interrupt controller to which the
|
||||
interrupts are routed; see section 2 below for details.
|
||||
Nodes that describe devices which generate interrupts must contain an
|
||||
"interrupts" property, an "interrupts-extended" property, or both. If both are
|
||||
present, the latter should take precedence; the former may be provided simply
|
||||
for compatibility with software that does not recognize the latter. These
|
||||
properties contain a list of interrupt specifiers, one per output interrupt. The
|
||||
format of the interrupt specifier is determined by the interrupt controller to
|
||||
which the interrupts are routed; see section 2 below for details.
|
||||
|
||||
Example:
|
||||
interrupt-parent = <&intc1>;
|
||||
|
||||
@ -42,11 +42,11 @@ conditions.
|
||||
|
||||
** System MMU optional properties:
|
||||
|
||||
- smmu-parent : When multiple SMMUs are chained together, this
|
||||
property can be used to provide a phandle to the
|
||||
parent SMMU (that is the next SMMU on the path going
|
||||
from the mmu-masters towards memory) node for this
|
||||
SMMU.
|
||||
- calxeda,smmu-secure-config-access : Enable proper handling of buggy
|
||||
implementations that always use secure access to
|
||||
SMMU configuration registers. In this case non-secure
|
||||
aliases of secure registers have to be used during
|
||||
SMMU configuration.
|
||||
|
||||
Example:
|
||||
|
||||
|
||||
@ -21,6 +21,8 @@ LED sub-node properties:
|
||||
on). The "keep" setting will keep the LED at whatever its current
|
||||
state is, without producing a glitch. The default is off if this
|
||||
property is not present.
|
||||
- retain-state-suspended: (optional) The suspend state can be retained.Such
|
||||
as charge-led gpio.
|
||||
|
||||
Examples:
|
||||
|
||||
@ -50,3 +52,13 @@ run-control {
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
charger-led {
|
||||
gpios = <&gpio1 2 0>;
|
||||
linux,default-trigger = "max8903-charger-charging";
|
||||
retain-state-suspended;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,7 +1,13 @@
|
||||
Binding for TI/National Semiconductor LP55xx Led Drivers
|
||||
|
||||
Required properties:
|
||||
- compatible: "national,lp5521" or "national,lp5523" or "ti,lp5562" or "ti,lp8501"
|
||||
- compatible: one of
|
||||
national,lp5521
|
||||
national,lp5523
|
||||
ti,lp55231
|
||||
ti,lp5562
|
||||
ti,lp8501
|
||||
|
||||
- reg: I2C slave address
|
||||
- clock-mode: Input clock mode, (0: automode, 1: internal, 2: external)
|
||||
|
||||
|
||||
@ -13,6 +13,8 @@ LED sub-node properties:
|
||||
For the pwms and pwm-names property please refer to:
|
||||
Documentation/devicetree/bindings/pwm/pwm.txt
|
||||
- max-brightness : Maximum brightness possible for the LED
|
||||
- active-low : (optional) For PWMs where the LED is wired to supply
|
||||
rather than ground.
|
||||
- label : (optional)
|
||||
see Documentation/devicetree/bindings/leds/common.txt
|
||||
- linux,default-trigger : (optional)
|
||||
|
||||
@ -1,18 +1,19 @@
|
||||
LEDs connected to pca9632, pca9633 or pca9634
|
||||
|
||||
Required properties:
|
||||
- compatible : should be : "nxp,pca9632", "nxp,pca9633" or "nxp,pca9634"
|
||||
- compatible : should be : "nxp,pca9632", "nxp,pca9633", "nxp,pca9634" or "nxp,pca9635"
|
||||
|
||||
Optional properties:
|
||||
- nxp,totem-pole : use totem pole (push-pull) instead of default open-drain
|
||||
- nxp,totem-pole : use totem pole (push-pull) instead of open-drain (pca9632 defaults
|
||||
to open-drain, newer chips to totem pole)
|
||||
- nxp,hw-blink : use hardware blinking instead of software blinking
|
||||
|
||||
Each led is represented as a sub-node of the nxp,pca963x device.
|
||||
|
||||
LED sub-node properties:
|
||||
- label : (optional) see Documentation/devicetree/bindings/leds/common.txt
|
||||
- reg : number of LED line (could be from 0 to 3 in pca9632 or pca9633
|
||||
or 0 to 7 in pca9634)
|
||||
- reg : number of LED line (could be from 0 to 3 in pca9632 or pca9633,
|
||||
0 to 7 in pca9634, or 0 to 15 in pca9635)
|
||||
- linux,default-trigger : (optional)
|
||||
see Documentation/devicetree/bindings/leds/common.txt
|
||||
|
||||
|
||||
@ -8,7 +8,7 @@ Required properties:
|
||||
|
||||
Optional properties:
|
||||
- gpio-controller: allows lines to be used as output-only GPIOs.
|
||||
- #gpio-cells: if present, must be 0.
|
||||
- #gpio-cells: if present, must not be 0.
|
||||
|
||||
Each led is represented as a sub-node of the ti,tca6507 device.
|
||||
|
||||
|
||||
@ -3,9 +3,13 @@ Samsung S5P/EXYNOS SoC series JPEG codec
|
||||
Required properties:
|
||||
|
||||
- compatible : should be one of:
|
||||
"samsung,s5pv210-jpeg", "samsung,exynos4210-jpeg";
|
||||
"samsung,s5pv210-jpeg", "samsung,exynos4210-jpeg",
|
||||
"samsung,exynos3250-jpeg";
|
||||
- reg : address and length of the JPEG codec IP register set;
|
||||
- interrupts : specifies the JPEG codec IP interrupt;
|
||||
- clocks : should contain the JPEG codec IP gate clock specifier, from the
|
||||
common clock bindings;
|
||||
- clock-names : should contain "jpeg" entry.
|
||||
- clock-names : should contain:
|
||||
- "jpeg" for the core gate clock,
|
||||
- "sclk" for the special clock (optional).
|
||||
- clocks : should contain the clock specifier and clock ID list
|
||||
matching entries in the clock-names property; from
|
||||
the common clock bindings.
|
||||
|
||||
@ -10,7 +10,8 @@ Required properties:
|
||||
- compatible : value should be either one among the following
|
||||
(a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
|
||||
(b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
|
||||
(b) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
|
||||
(c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
|
||||
(d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
|
||||
|
||||
- reg : Physical base address of the IP registers and length of memory
|
||||
mapped region.
|
||||
|
||||
@ -15,11 +15,21 @@ Common 'camera' node
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : must be "samsung,fimc", "simple-bus"
|
||||
- clocks : list of clock specifiers, corresponding to entries in
|
||||
the clock-names property;
|
||||
- clock-names : must contain "sclk_cam0", "sclk_cam1", "pxl_async0",
|
||||
"pxl_async1" entries, matching entries in the clocks property.
|
||||
- compatible: must be "samsung,fimc", "simple-bus"
|
||||
- clocks: list of clock specifiers, corresponding to entries in
|
||||
the clock-names property;
|
||||
- clock-names : must contain "sclk_cam0", "sclk_cam1", "pxl_async0",
|
||||
"pxl_async1" entries, matching entries in the clocks property.
|
||||
|
||||
- #clock-cells: from the common clock bindings (../clock/clock-bindings.txt),
|
||||
must be 1. A clock provider is associated with the 'camera' node and it should
|
||||
be referenced by external sensors that use clocks provided by the SoC on
|
||||
CAM_*_CLKOUT pins. The clock specifier cell stores an index of a clock.
|
||||
The indices are 0, 1 for CAM_A_CLKOUT, CAM_B_CLKOUT clocks respectively.
|
||||
|
||||
- clock-output-names: from the common clock bindings, should contain names of
|
||||
clocks registered by the camera subsystem corresponding to CAM_A_CLKOUT,
|
||||
CAM_B_CLKOUT output clocks respectively.
|
||||
|
||||
The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used
|
||||
to define a required pinctrl state named "default" and optional pinctrl states:
|
||||
@ -32,6 +42,7 @@ way around.
|
||||
|
||||
The 'camera' node must include at least one 'fimc' child node.
|
||||
|
||||
|
||||
'fimc' device nodes
|
||||
-------------------
|
||||
|
||||
@ -88,8 +99,8 @@ port nodes specifies data input - 0, 1 indicates input A, B respectively.
|
||||
|
||||
Optional properties
|
||||
|
||||
- samsung,camclk-out : specifies clock output for remote sensor,
|
||||
0 - CAM_A_CLKOUT, 1 - CAM_B_CLKOUT;
|
||||
- samsung,camclk-out (deprecated) : specifies clock output for remote sensor,
|
||||
0 - CAM_A_CLKOUT, 1 - CAM_B_CLKOUT;
|
||||
|
||||
Image sensor nodes
|
||||
------------------
|
||||
@ -97,8 +108,6 @@ Image sensor nodes
|
||||
The sensor device nodes should be added to their control bus controller (e.g.
|
||||
I2C0) nodes and linked to a port node in the csis or the parallel-ports node,
|
||||
using the common video interfaces bindings, defined in video-interfaces.txt.
|
||||
The implementation of this bindings requires clock-frequency property to be
|
||||
present in the sensor device nodes.
|
||||
|
||||
Example:
|
||||
|
||||
@ -114,7 +123,7 @@ Example:
|
||||
vddio-supply = <...>;
|
||||
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <...>;
|
||||
clocks = <&camera 1>;
|
||||
clock-names = "mclk";
|
||||
|
||||
port {
|
||||
@ -135,7 +144,7 @@ Example:
|
||||
vddio-supply = <...>;
|
||||
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <...>;
|
||||
clocks = <&camera 0>;
|
||||
clock-names = "mclk";
|
||||
|
||||
port {
|
||||
@ -149,12 +158,17 @@ Example:
|
||||
|
||||
camera {
|
||||
compatible = "samsung,fimc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "okay";
|
||||
|
||||
clocks = <&clock 132>, <&clock 133>, <&clock 351>,
|
||||
<&clock 352>;
|
||||
clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0",
|
||||
"pxl_async1";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "cam_a_clkout", "cam_b_clkout";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cam_port_a_clk_active>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* parallel camera ports */
|
||||
parallel-ports {
|
||||
|
||||
@ -6,10 +6,11 @@ The actual devices are instantiated from the child nodes of a Device Bus node.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Currently only Armada 370/XP SoC are supported,
|
||||
with this compatible string:
|
||||
- compatible: Armada 370/XP SoC are supported using the
|
||||
"marvell,mvebu-devbus" compatible string.
|
||||
|
||||
marvell,mvebu-devbus
|
||||
Orion5x SoC are supported using the
|
||||
"marvell,orion-devbus" compatible string.
|
||||
|
||||
- reg: A resource specifier for the register space.
|
||||
This is the base address of a chip select within
|
||||
@ -22,7 +23,14 @@ Required properties:
|
||||
integer values for each chip-select line in use:
|
||||
0 <physical address of mapping> <size>
|
||||
|
||||
Mandatory timing properties for child nodes:
|
||||
Optional properties:
|
||||
|
||||
- devbus,keep-config This property can optionally be used to keep
|
||||
using the timing parameters set by the
|
||||
bootloader. It makes all the timing properties
|
||||
described below unused.
|
||||
|
||||
Timing properties for child nodes:
|
||||
|
||||
Read parameters:
|
||||
|
||||
@ -30,21 +38,26 @@ Read parameters:
|
||||
drive the AD bus after the completion of a device read.
|
||||
This prevents contentions on the Device Bus after a read
|
||||
cycle from a slow device.
|
||||
Mandatory, except if devbus,keep-config is used.
|
||||
|
||||
- devbus,bus-width: Defines the bus width (e.g. <16>)
|
||||
- devbus,bus-width: Defines the bus width, in bits (e.g. <16>).
|
||||
Mandatory, except if devbus,keep-config is used.
|
||||
|
||||
- devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
|
||||
to read data sample. This parameter is useful for
|
||||
synchronous pipelined devices, where the address
|
||||
precedes the read data by one or two cycles.
|
||||
Mandatory, except if devbus,keep-config is used.
|
||||
|
||||
- devbus,acc-first-ps: Defines the time delay from the negation of
|
||||
ALE[0] to the cycle that the first read data is sampled
|
||||
by the controller.
|
||||
Mandatory, except if devbus,keep-config is used.
|
||||
|
||||
- devbus,acc-next-ps: Defines the time delay between the cycle that
|
||||
samples data N and the cycle that samples data N+1
|
||||
(in burst accesses).
|
||||
Mandatory, except if devbus,keep-config is used.
|
||||
|
||||
- devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to
|
||||
DEV_OEn assertion. If set to 0 (default),
|
||||
@ -52,6 +65,8 @@ Read parameters:
|
||||
This parameter has no affect on <acc-first-ps> parameter
|
||||
(no affect on first data sample). Set <rd-setup-ps>
|
||||
to a value smaller than <acc-first-ps>.
|
||||
Mandatory for "marvell,mvebu-devbus" compatible string,
|
||||
except if devbus,keep-config is used.
|
||||
|
||||
- devbus,rd-hold-ps: Defines the time between the last data sample to the
|
||||
de-assertion of DEV_CSn. If set to 0 (default),
|
||||
@ -62,16 +77,20 @@ Read parameters:
|
||||
last data sampled. Also this parameter has no
|
||||
affect on <turn-off-ps> parameter.
|
||||
Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
|
||||
Mandatory for "marvell,mvebu-devbus" compatible string,
|
||||
except if devbus,keep-config is used.
|
||||
|
||||
Write parameters:
|
||||
|
||||
- devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
|
||||
to the DEV_WEn assertion.
|
||||
Mandatory.
|
||||
|
||||
- devbus,wr-low-ps: Defines the time during which DEV_WEn is active.
|
||||
A[2:0] and Data are kept valid as long as DEV_WEn
|
||||
is active. This parameter defines the setup time of
|
||||
address and data to DEV_WEn rise.
|
||||
Mandatory.
|
||||
|
||||
- devbus,wr-high-ps: Defines the time during which DEV_WEn is kept
|
||||
inactive (high) between data beats of a burst write.
|
||||
@ -79,10 +98,13 @@ Write parameters:
|
||||
<wr-high-ps> - <tick> ps.
|
||||
This parameter defines the hold time of address and
|
||||
data after DEV_WEn rise.
|
||||
Mandatory.
|
||||
|
||||
- devbus,sync-enable: Synchronous device enable.
|
||||
1: True
|
||||
0: False
|
||||
Mandatory for "marvell,mvebu-devbus" compatible string,
|
||||
except if devbus,keep-config is used.
|
||||
|
||||
An example for an Armada XP GP board, with a 16 MiB NOR device as child
|
||||
is showed below. Note that the Device Bus driver is in charge of allocating
|
||||
|
||||
@ -5,9 +5,10 @@ of analogue I/O.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : one of the following chip-specific strings:
|
||||
"wlf,wm5102"
|
||||
"wlf,wm5110"
|
||||
- compatible : One of the following chip-specific strings:
|
||||
"wlf,wm5102"
|
||||
"wlf,wm5110"
|
||||
"wlf,wm8997"
|
||||
- reg : I2C slave address when connected using I2C, chip select number when
|
||||
using SPI.
|
||||
|
||||
@ -25,8 +26,9 @@ Required properties:
|
||||
- #gpio-cells : Must be 2. The first cell is the pin number and the
|
||||
second cell is used to specify optional parameters (currently unused).
|
||||
|
||||
- AVDD1-supply, DBVDD1-supply, DBVDD2-supply, DBVDD3-supply, CPVDD-supply,
|
||||
SPKVDDL-supply, SPKVDDR-supply : power supplies for the device, as covered
|
||||
- AVDD-supply, DBVDD1-supply, DBVDD2-supply, DBVDD3-supply (wm5102, wm5110),
|
||||
CPVDD-supply, SPKVDDL-supply (wm5102, wm5110), SPKVDDR-supply (wm5102,
|
||||
wm5110), SPKVDD-supply (wm8997) : Power supplies for the device, as covered
|
||||
in Documentation/devicetree/bindings/regulator/regulator.txt
|
||||
|
||||
Optional properties:
|
||||
@ -40,12 +42,23 @@ Optional properties:
|
||||
the chip default will be used. If present exactly five values must
|
||||
be specified.
|
||||
|
||||
- DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if
|
||||
they are being externally supplied. As covered in
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt
|
||||
|
||||
Optional subnodes:
|
||||
- ldo1 : Initial data for the LDO1 regulator, as covered in
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt
|
||||
- micvdd : Initial data for the MICVDD regulator, as covered in
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt
|
||||
|
||||
Example:
|
||||
|
||||
codec: wm5102@1a {
|
||||
compatible = "wlf,wm5102";
|
||||
reg = <0x1a>;
|
||||
interrupts = <347>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
@ -53,10 +66,10 @@ codec: wm5102@1a {
|
||||
#gpio-cells = <2>;
|
||||
|
||||
wlf,gpio-defaults = <
|
||||
0x00000000, /* AIF1TXLRCLK */
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0xffffffff,
|
||||
0x00000000 /* AIF1TXLRCLK */
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
0xffffffff
|
||||
>;
|
||||
};
|
||||
|
||||
@ -13,6 +13,14 @@ Required properties:
|
||||
The second cell is the flags, encoded as the trigger masks from binding document
|
||||
interrupts.txt, using dt-bindings/irq.
|
||||
|
||||
Optional properties:
|
||||
--------------------
|
||||
- ams,enable-internal-int-pullup: Boolean property, to enable internal pullup on
|
||||
interrupt pin. Missing this will disable internal pullup on INT pin.
|
||||
- ams,enable-internal-i2c-pullup: Boolean property, to enable internal pullup on
|
||||
i2c scl/sda pins. Missing this will disable internal pullup on i2c
|
||||
scl/sda lines.
|
||||
|
||||
Optional submodule and their properties:
|
||||
=======================================
|
||||
|
||||
|
||||
@ -10,9 +10,47 @@ Optional properties:
|
||||
- fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
|
||||
|
||||
Sub-nodes:
|
||||
- codec: Contain the Audio Codec node.
|
||||
- adc-port: Contain PMIC SSI port number used for ADC.
|
||||
- dac-port: Contain PMIC SSI port number used for DAC.
|
||||
- leds : Contain the led nodes and initial register values in property
|
||||
"led-control". Number of register depends of used IC, for MC13783 is 6,
|
||||
for MC13892 is 4, for MC34708 is 1. See datasheet for bits definitions of
|
||||
these registers.
|
||||
- #address-cells: Must be 1.
|
||||
- #size-cells: Must be 0.
|
||||
Each led node should contain "reg", which used as LED ID (described below).
|
||||
Optional properties "label" and "linux,default-trigger" is described in
|
||||
Documentation/devicetree/bindings/leds/common.txt.
|
||||
- regulators : Contain the regulator nodes. The regulators are bound using
|
||||
their names as listed below with their registers and bits for enabling.
|
||||
|
||||
MC13783 LED IDs:
|
||||
0 : Main display
|
||||
1 : AUX display
|
||||
2 : Keypad
|
||||
3 : Red 1
|
||||
4 : Green 1
|
||||
5 : Blue 1
|
||||
6 : Red 2
|
||||
7 : Green 2
|
||||
8 : Blue 2
|
||||
9 : Red 3
|
||||
10 : Green 3
|
||||
11 : Blue 3
|
||||
|
||||
MC13892 LED IDs:
|
||||
0 : Main display
|
||||
1 : AUX display
|
||||
2 : Keypad
|
||||
3 : Red
|
||||
4 : Green
|
||||
5 : Blue
|
||||
|
||||
MC34708 LED IDs:
|
||||
0 : Charger Red
|
||||
1 : Charger Green
|
||||
|
||||
MC13783 regulators:
|
||||
sw1a : regulator SW1A (register 24, bit 0)
|
||||
sw1b : regulator SW1B (register 25, bit 0)
|
||||
@ -89,6 +127,18 @@ ecspi@70010000 { /* ECSPI1 */
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <8>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
led-control = <0x000 0x000 0x0e0 0x000>;
|
||||
|
||||
sysled {
|
||||
reg = <3>;
|
||||
label = "system:red:live";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
sw1_reg: mc13892__sw1 {
|
||||
regulator-min-microvolt = <600000>;
|
||||
|
||||
@ -32,6 +32,29 @@ Optional properties:
|
||||
- single-ulpi-bypass: Must be present if the controller contains a single
|
||||
ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1
|
||||
|
||||
- clocks: a list of phandles and clock-specifier pairs, one for each entry in
|
||||
clock-names.
|
||||
|
||||
- clock-names: should include:
|
||||
For OMAP3
|
||||
* "usbhost_120m_fck" - 120MHz Functional clock.
|
||||
|
||||
For OMAP4+
|
||||
* "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
|
||||
* "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
|
||||
* "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
|
||||
* "utmi_p1_gfclk" - Port 1 UTMI clock mux.
|
||||
* "utmi_p2_gfclk" - Port 2 UTMI clock mux.
|
||||
* "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
|
||||
* "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
|
||||
* "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
|
||||
* "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
|
||||
* "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
|
||||
* "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
|
||||
* "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
|
||||
* "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
|
||||
* "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
|
||||
|
||||
Required properties if child node exists:
|
||||
|
||||
- #address-cells: Must be 1
|
||||
|
||||
@ -7,6 +7,16 @@ Required properties:
|
||||
- interrupts : should contain the TLL module's interrupt
|
||||
- ti,hwmod : must contain "usb_tll_hs"
|
||||
|
||||
Optional properties:
|
||||
|
||||
- clocks: a list of phandles and clock-specifier pairs, one for each entry in
|
||||
clock-names.
|
||||
|
||||
- clock-names: should include:
|
||||
* "usb_tll_hs_usb_ch0_clk" - USB TLL channel 0 clock
|
||||
* "usb_tll_hs_usb_ch1_clk" - USB TLL channel 1 clock
|
||||
* "usb_tll_hs_usb_ch2_clk" - USB TLL channel 2 clock
|
||||
|
||||
Example:
|
||||
|
||||
usbhstll: usbhstll@4a062000 {
|
||||
|
||||
@ -6,6 +6,7 @@ twl6037 (palmas)
|
||||
tps65913 (palmas)
|
||||
tps65914 (palmas)
|
||||
tps659038
|
||||
tps65917
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be from the list
|
||||
@ -16,6 +17,7 @@ Required properties:
|
||||
ti,tps65914
|
||||
ti,tps80036
|
||||
ti,tps659038
|
||||
ti,tps65917
|
||||
and also the generic series names
|
||||
ti,palmas
|
||||
- interrupt-controller : palmas has its own internal IRQs
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
|
||||
* Samsung S2MPS11 Voltage and Current Regulator
|
||||
* Samsung S2MPS11, S2MPS14 and S2MPU02 Voltage and Current Regulator
|
||||
|
||||
The Samsung S2MPS11 is a multi-function device which includes voltage and
|
||||
current regulators, RTC, charger controller and other sub-blocks. It is
|
||||
@ -7,7 +7,8 @@ interfaced to the host controller using an I2C interface. Each sub-block is
|
||||
addressed by the host system using different I2C slave addresses.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "samsung,s2mps11-pmic".
|
||||
- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps14-pmic"
|
||||
or "samsung,s2mpu02-pmic".
|
||||
- reg: Specifies the I2C slave address of the pmic block. It should be 0x66.
|
||||
|
||||
Optional properties:
|
||||
@ -16,20 +17,25 @@ Optional properties:
|
||||
- interrupts: Interrupt specifiers for interrupt sources.
|
||||
|
||||
Optional nodes:
|
||||
- clocks: s2mps11 provides three(AP/CP/BT) buffered 32.768 KHz outputs, so to
|
||||
register these as clocks with common clock framework instantiate a sub-node
|
||||
named "clocks". It uses the common clock binding documented in :
|
||||
- clocks: s2mps11 and s5m8767 provide three(AP/CP/BT) buffered 32.768 KHz
|
||||
outputs, so to register these as clocks with common clock framework
|
||||
instantiate a sub-node named "clocks". It uses the common clock binding
|
||||
documented in :
|
||||
[Documentation/devicetree/bindings/clock/clock-bindings.txt]
|
||||
The s2mps14 provides two (AP/BT) buffered 32.768 KHz outputs.
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
- The following is the list of clocks generated by the controller. Each clock
|
||||
is assigned an identifier and client nodes use this identifier to specify
|
||||
the clock which they consume.
|
||||
Clock ID
|
||||
----------------------
|
||||
32KhzAP 0
|
||||
32KhzCP 1
|
||||
32KhzBT 2
|
||||
Clock ID Devices
|
||||
----------------------------------------------------------
|
||||
32KhzAP 0 S2MPS11, S2MPS14, S5M8767
|
||||
32KhzCP 1 S2MPS11, S5M8767
|
||||
32KhzBT 2 S2MPS11, S2MPS14, S5M8767
|
||||
|
||||
- compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps14-clk",
|
||||
"samsung,s5m8767-clk"
|
||||
|
||||
- regulators: The regulators of s2mps11 that have to be instantiated should be
|
||||
included in a sub-node named 'regulators'. Regulator nodes included in this
|
||||
@ -51,6 +57,20 @@ for a particular group of BUCKs. So provide same regulator-ramp-delay<value>.
|
||||
Grouping of BUCKs sharing ramp rate setting is as follow : BUCK[1, 6],
|
||||
BUCK[3, 4], and BUCK[7, 8, 10]
|
||||
|
||||
On S2MPS14 the LDO10, LDO11 and LDO12 can be configured to external control
|
||||
over GPIO. To turn this feature on this property must be added to the regulator
|
||||
sub-node:
|
||||
- samsung,ext-control-gpios: GPIO specifier for one GPIO
|
||||
controlling this regulator (enable/disable);
|
||||
Example:
|
||||
LDO12 {
|
||||
regulator-name = "V_EMMC_2.8V";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
samsung,ext-control-gpios = <&gpk0 2 0>;
|
||||
};
|
||||
|
||||
|
||||
The regulator constraints inside the regulator nodes use the standard regulator
|
||||
bindings which are documented elsewhere.
|
||||
|
||||
@ -59,10 +79,16 @@ supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number
|
||||
as per the datasheet of s2mps11.
|
||||
|
||||
- LDOn
|
||||
- valid values for n are 1 to 38
|
||||
- Example: LDO1, LD02, LDO28
|
||||
- valid values for n are:
|
||||
- S2MPS11: 1 to 38
|
||||
- S2MPS14: 1 to 25
|
||||
- S2MPU02: 1 to 28
|
||||
- Example: LDO1, LDO2, LDO28
|
||||
- BUCKn
|
||||
- valid values for n are 1 to 10.
|
||||
- valid values for n are:
|
||||
- S2MPS11: 1 to 10
|
||||
- S2MPS14: 1 to 5
|
||||
- S2MPU02: 1 to 7
|
||||
- Example: BUCK1, BUCK2, BUCK9
|
||||
|
||||
Example:
|
||||
@ -71,8 +97,9 @@ Example:
|
||||
compatible = "samsung,s2mps11-pmic";
|
||||
reg = <0x66>;
|
||||
|
||||
s2m_osc: clocks{
|
||||
#clock-cells = 1;
|
||||
s2m_osc: clocks {
|
||||
compatible = "samsung,s2mps11-clk";
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "xx", "yy", "zz";
|
||||
};
|
||||
|
||||
|
||||
@ -11,7 +11,7 @@ Required properties:
|
||||
- #interrupt-cells: the number of cells to describe an IRQ, this should be 2.
|
||||
The first cell is the IRQ number.
|
||||
The second cell is the flags, encoded as the trigger masks from
|
||||
Documentation/devicetree/bindings/interrupts.txt
|
||||
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
|
||||
- regulators: This is the list of child nodes that specify the regulator
|
||||
initialization data for defined regulators. Not all regulators for the given
|
||||
device need to be present. The definition for each of these nodes is defined
|
||||
|
||||
@ -5,7 +5,22 @@ to control the power resources, including power scripts. For now, the
|
||||
binding only supports the complete shutdown of the system after poweroff.
|
||||
|
||||
Required properties:
|
||||
- compatible : must be "ti,twl4030-power"
|
||||
- compatible : must be one of the following
|
||||
"ti,twl4030-power"
|
||||
"ti,twl4030-power-reset"
|
||||
"ti,twl4030-power-idle"
|
||||
"ti,twl4030-power-idle-osc-off"
|
||||
|
||||
The use of ti,twl4030-power-reset is recommended at least on
|
||||
3530 that needs a special configuration for warm reset to work.
|
||||
|
||||
When using ti,twl4030-power-idle, the TI recommended configuration
|
||||
for idle modes is loaded to the tlw4030 PMIC.
|
||||
|
||||
When using ti,twl4030-power-idle-osc-off, the TI recommended
|
||||
configuration is used with the external oscillator being shut
|
||||
down during off-idle. Note that this does not work on all boards
|
||||
depending on how the external oscillator is wired.
|
||||
|
||||
Optional properties:
|
||||
- ti,use_poweroff: With this flag, the chip will initiates an ACTIVE-to-OFF or
|
||||
|
||||
@ -19,6 +19,8 @@ Required properties:
|
||||
|
||||
Optional properties, nodes:
|
||||
- enable-active-high: To power on the twl6040 during boot.
|
||||
- clocks: phandle to the clk32k clock provider
|
||||
- clock-names: Must be "clk32k"
|
||||
|
||||
Vibra functionality
|
||||
Required properties:
|
||||
|
||||
@ -1,12 +1,12 @@
|
||||
Allwinner sunxi-sid
|
||||
|
||||
Required properties:
|
||||
- compatible: "allwinner,sun4i-sid" or "allwinner,sun7i-a20-sid".
|
||||
- compatible: "allwinner,sun4i-a10-sid" or "allwinner,sun7i-a20-sid"
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
Example for sun4i:
|
||||
sid@01c23800 {
|
||||
compatible = "allwinner,sun4i-sid";
|
||||
compatible = "allwinner,sun4i-a10-sid";
|
||||
reg = <0x01c23800 0x10>
|
||||
};
|
||||
|
||||
|
||||
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Reference in New Issue
Block a user