Moved some definitions of initialized data nearer to the start of
the file so that this compiles without forward declarations of that data. (It is impossible to forward-declare static data in Gnu C. Declaring it as static is correct, but causes bogus warnings from gcc -Wredundant-decls. Declaring it as extern works, but causes correct warnings from gcc -pedantic and is undefined in ANSI C. We usually declare it as extern. Here it was once really extern, but botched staticization left it as static here and apparently- extern in a header file.) ---------------------------------------------------------------------- another system, such as NetBSD, CVS: then name the system in this line, otherwise delete it. CVS: Reviewed by: CVS: Before committing changes please have someone check your work and CVS: include their name here. If the change is trivial and you have not else; i.e., CVS: they sent us a patch or a new module, then include their name/email CVS: address here. If this is your work then delete this line. CVS: ---------------------------------------------------------------------- ----------------------------------------------------------------------
This commit is contained in:
Bruce Evans
parent
9aa783b382
commit
dd1df1935f
@ -65,6 +65,163 @@ static int cx_univ_mode = M_ASYNC; /* univ. chan. mode: async or sync */
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static int cx_sync_mode = M_HDLC; /* sync. chan. mode: HDLC, Bisync or X.21 */
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static int cx_iftype = 0; /* univ. chan. interface: upper/lower */
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static cx_chan_opt_t chan_opt_dflt = { /* mode-independent options */
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{ /* cor4 */
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7, /* FIFO threshold, odd is better */
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0,
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0, /* don't detect 1 to 0 on CTS */
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1, /* detect 1 to 0 on CD */
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0, /* detect 1 to 0 on DSR */
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},
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{ /* cor5 */
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0, /* receive flow control FIFO threshold */
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0,
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0, /* don't detect 0 to 1 on CTS */
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1, /* detect 0 to 1 on CD */
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0, /* detect 0 to 1 on DSR */
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},
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{ /* rcor */
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0, /* dummy clock source */
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ENCOD_NRZ, /* NRZ mode */
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0, /* disable DPLL */
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0,
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0, /* transmit line value */
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},
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{ /* tcor */
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0,
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0, /* local loopback mode */
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0,
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1, /* external 1x clock mode */
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0,
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0, /* dummy transmit clock source */
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},
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};
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static cx_opt_async_t opt_async_dflt = { /* default async options */
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{ /* cor1 */
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8-1, /* 8-bit char length */
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0, /* don't ignore parity */
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PARM_NOPAR, /* no parity */
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PAR_EVEN, /* even parity */
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},
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{ /* cor2 */
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0, /* disable automatic DSR */
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1, /* enable automatic CTS */
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0, /* disable automatic RTS */
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0, /* no remote loopback */
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0,
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0, /* disable embedded cmds */
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0, /* disable XON/XOFF */
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0, /* disable XANY */
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},
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{ /* cor3 */
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STOPB_1, /* 1 stop bit */
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0,
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0, /* disable special char detection */
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FLOWCC_PASS, /* pass flow ctl chars to the host */
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0, /* range detect disable */
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0, /* disable extended spec. char detect */
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},
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{ /* cor6 */
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PERR_INTR, /* generate exception on parity errors */
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BRK_INTR, /* generate exception on break condition */
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0, /* don't translate NL to CR on input */
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0, /* don't translate CR to NL on input */
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0, /* don't discard CR on input */
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},
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{ /* cor7 */
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0, /* don't translate CR to NL on output */
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0, /* don't translate NL to CR on output */
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0,
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0, /* don't process flow ctl err chars */
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0, /* disable LNext option */
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0, /* don't strip 8 bit on input */
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},
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0, 0, 0, 0, 0, 0, 0, /* clear schr1-4, scrl, scrh, lnxt */
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};
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static cx_opt_hdlc_t opt_hdlc_dflt = { /* default hdlc options */
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{ /* cor1 */
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2, /* 2 inter-frame flags */
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0, /* no-address mode */
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CLRDET_DISABLE, /* disable clear detect */
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AFLO_1OCT, /* 1-byte address field length */
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},
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{ /* cor2 */
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0, /* disable automatic DSR */
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0, /* disable automatic CTS */
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0, /* disable automatic RTS */
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0,
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CRC_INVERT, /* use CRC V.41 */
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0,
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FCS_NOTPASS, /* don't pass received CRC to the host */
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0,
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},
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{ /* cor3 */
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0, /* 0 pad characters sent */
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IDLE_FLAG, /* idle in flag */
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0, /* enable FCS */
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FCSP_ONES, /* FCS preset to all ones (V.41) */
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SYNC_AA, /* use AAh as sync char */
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0, /* disable pad characters */
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},
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0, 0, 0, 0, /* clear rfar1-4 */
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POLY_V41, /* use V.41 CRC polynomial */
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};
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static cx_opt_bisync_t opt_bisync_dflt = { /* default bisync options */
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{ /* cor1 */
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8-1, /* 8-bit char length */
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0, /* don't ignore parity */
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PARM_NOPAR, /* no parity */
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PAR_EVEN, /* even parity */
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},
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{ /* cor2 */
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3-2, /* send three SYN chars */
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CRC_DONT_INVERT,/* don't invert CRC (CRC-16) */
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0, /* use ASCII, not EBCDIC */
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0, /* disable bcc append */
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BCC_CRC16, /* user CRC16, not LRC */
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},
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{ /* cor3 */
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0, /* send 0 pad chars */
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IDLE_FLAG, /* idle in SYN */
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0, /* enable FCS */
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FCSP_ZEROS, /* FCS preset to all zeros (CRC-16) */
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PAD_AA, /* use AAh as pad char */
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0, /* disable pad characters */
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},
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{ /* cor6 */
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10, /* DLE - disable special termination char */
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},
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POLY_16, /* use CRC-16 polynomial */
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};
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static cx_opt_x21_t opt_x21_dflt = { /* default x21 options */
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{ /* cor1 */
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8-1, /* 8-bit char length */
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0, /* don't ignore parity */
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PARM_NOPAR, /* no parity */
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PAR_EVEN, /* even parity */
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},
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{ /* cor2 */
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0,
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0, /* disable embedded transmitter cmds */
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0,
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},
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{ /* cor3 */
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0,
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0, /* disable special character detect */
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0, /* don't treat SYN as special condition */
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0, /* disable steady state detect */
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X21SYN_2, /* 2 SYN chars on receive are required */
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},
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{ /* cor6 */
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16, /* SYN - standard SYN character */
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},
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0, 0, 0, /* clear schr1-3 */
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};
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static int cx_probe_chip (int base);
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static void cx_setup_chip (cx_chip_t *c);
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static void cx_init_board (cx_board_t *b, int num, int port, int irq, int dma,
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@ -870,160 +1027,3 @@ void cx_clock (long hz, long ba, int *clk, int *div)
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*clk = 0;
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*div = 255;
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}
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static cx_chan_opt_t chan_opt_dflt = { /* mode-independent options */
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{ /* cor4 */
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7, /* FIFO threshold, odd is better */
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0,
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0, /* don't detect 1 to 0 on CTS */
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1, /* detect 1 to 0 on CD */
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0, /* detect 1 to 0 on DSR */
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},
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{ /* cor5 */
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0, /* receive flow control FIFO threshold */
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0,
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0, /* don't detect 0 to 1 on CTS */
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1, /* detect 0 to 1 on CD */
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0, /* detect 0 to 1 on DSR */
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},
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{ /* rcor */
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0, /* dummy clock source */
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ENCOD_NRZ, /* NRZ mode */
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0, /* disable DPLL */
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0,
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0, /* transmit line value */
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},
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{ /* tcor */
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0,
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0, /* local loopback mode */
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0,
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1, /* external 1x clock mode */
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0,
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0, /* dummy transmit clock source */
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},
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};
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static cx_opt_async_t opt_async_dflt = { /* default async options */
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{ /* cor1 */
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8-1, /* 8-bit char length */
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0, /* don't ignore parity */
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PARM_NOPAR, /* no parity */
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PAR_EVEN, /* even parity */
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},
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{ /* cor2 */
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0, /* disable automatic DSR */
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1, /* enable automatic CTS */
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0, /* disable automatic RTS */
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0, /* no remote loopback */
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0,
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0, /* disable embedded cmds */
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0, /* disable XON/XOFF */
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0, /* disable XANY */
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},
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{ /* cor3 */
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STOPB_1, /* 1 stop bit */
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0,
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0, /* disable special char detection */
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FLOWCC_PASS, /* pass flow ctl chars to the host */
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0, /* range detect disable */
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0, /* disable extended spec. char detect */
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},
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{ /* cor6 */
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PERR_INTR, /* generate exception on parity errors */
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BRK_INTR, /* generate exception on break condition */
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0, /* don't translate NL to CR on input */
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0, /* don't translate CR to NL on input */
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0, /* don't discard CR on input */
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},
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{ /* cor7 */
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0, /* don't translate CR to NL on output */
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0, /* don't translate NL to CR on output */
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0,
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0, /* don't process flow ctl err chars */
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0, /* disable LNext option */
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0, /* don't strip 8 bit on input */
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},
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0, 0, 0, 0, 0, 0, 0, /* clear schr1-4, scrl, scrh, lnxt */
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};
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static cx_opt_hdlc_t opt_hdlc_dflt = { /* default hdlc options */
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{ /* cor1 */
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2, /* 2 inter-frame flags */
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0, /* no-address mode */
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CLRDET_DISABLE, /* disable clear detect */
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AFLO_1OCT, /* 1-byte address field length */
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},
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{ /* cor2 */
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0, /* disable automatic DSR */
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0, /* disable automatic CTS */
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0, /* disable automatic RTS */
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0,
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CRC_INVERT, /* use CRC V.41 */
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0,
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FCS_NOTPASS, /* don't pass received CRC to the host */
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0,
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},
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{ /* cor3 */
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0, /* 0 pad characters sent */
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IDLE_FLAG, /* idle in flag */
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0, /* enable FCS */
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FCSP_ONES, /* FCS preset to all ones (V.41) */
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SYNC_AA, /* use AAh as sync char */
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0, /* disable pad characters */
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},
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0, 0, 0, 0, /* clear rfar1-4 */
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POLY_V41, /* use V.41 CRC polynomial */
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};
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static cx_opt_bisync_t opt_bisync_dflt = { /* default bisync options */
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{ /* cor1 */
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8-1, /* 8-bit char length */
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0, /* don't ignore parity */
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PARM_NOPAR, /* no parity */
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PAR_EVEN, /* even parity */
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},
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{ /* cor2 */
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3-2, /* send three SYN chars */
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CRC_DONT_INVERT,/* don't invert CRC (CRC-16) */
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0, /* use ASCII, not EBCDIC */
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0, /* disable bcc append */
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BCC_CRC16, /* user CRC16, not LRC */
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},
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{ /* cor3 */
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0, /* send 0 pad chars */
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IDLE_FLAG, /* idle in SYN */
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0, /* enable FCS */
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FCSP_ZEROS, /* FCS preset to all zeros (CRC-16) */
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PAD_AA, /* use AAh as pad char */
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0, /* disable pad characters */
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},
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{ /* cor6 */
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10, /* DLE - disable special termination char */
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},
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POLY_16, /* use CRC-16 polynomial */
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};
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static cx_opt_x21_t opt_x21_dflt = { /* default x21 options */
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{ /* cor1 */
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8-1, /* 8-bit char length */
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0, /* don't ignore parity */
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PARM_NOPAR, /* no parity */
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PAR_EVEN, /* even parity */
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},
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{ /* cor2 */
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0,
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0, /* disable embedded transmitter cmds */
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0,
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},
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{ /* cor3 */
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0,
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0, /* disable special character detect */
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0, /* don't treat SYN as special condition */
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0, /* disable steady state detect */
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X21SYN_2, /* 2 SYN chars on receive are required */
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},
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{ /* cor6 */
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16, /* SYN - standard SYN character */
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},
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0, 0, 0, /* clear schr1-3 */
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};
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