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Make pmap_copy_page() L2-cache friendly by doing the copy through the

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cacheable window on physical memory (KSEG0). On the Sibyte processor
going through the uncacheable window (KSEG1) bypasses both L1 and L2
caches so we may end up with stale contents in the L2 cache.

This also makes it consistent with the rest of the function that
uses cacheable mappings to copy pages.

Approved by: imp (mentor)
This commit is contained in:
neel 2009-11-13 09:24:09 +00:00
parent de58e642f4
commit de1449747c
1 changed files with 4 additions and 3 deletions
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7
sys/mips/mips/pmap.c
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@ -2415,7 +2415,7 @@ pmap_copy_page(vm_page_t src, vm_page_t dst)
#endif
{
if ((phy_src < MIPS_KSEG0_LARGEST_PHYS) && (phy_dst < MIPS_KSEG0_LARGEST_PHYS)) {
/* easy case, all can be accessed via KSEG1 */
/* easy case, all can be accessed via KSEG0 */
/*
* Flush all caches for VA that are mapped to this page
* to make sure that data in SDRAM is up to date
@ -2423,9 +2423,10 @@ pmap_copy_page(vm_page_t src, vm_page_t dst)
pmap_flush_pvcache(src);
mips_dcache_wbinv_range_index(
MIPS_PHYS_TO_CACHED(phy_dst), NBPG);
va_src = MIPS_PHYS_TO_UNCACHED(phy_src);
va_dst = MIPS_PHYS_TO_UNCACHED(phy_dst);
va_src = MIPS_PHYS_TO_CACHED(phy_src);
va_dst = MIPS_PHYS_TO_CACHED(phy_dst);
bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE);
mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
} else {
int cpu;
struct local_sysmaps *sysm;