Remove ubsec(4).
This driver was previously marked for deprecation in r360710. Approved by: csprng (cem, gordon, delphij) Relnotes: yes Sponsored by: Chelsio Communications Differential Revision: https://reviews.freebsd.org/D24766
This commit is contained in:
jhb
parent
0209fe3398
commit
df4d227547
@ -36,6 +36,9 @@
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# xargs -n1 | sort | uniq -d;
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# done
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# 2020xxxx: Remove ubsec(4)
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OLD_FILES+=usr/share/man/man4/ubsec.4.gz
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# 20200506: GNU objdump 2.17.50 retired
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OLD_FILES+=usr/bin/objdump
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OLD_FILES+=usr/share/man/man1/objdump.1.gz
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@ -966,7 +966,6 @@ MAN+= \
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uart.4 \
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uath.4 \
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ubsa.4 \
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ubsec.4 \
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ubser.4 \
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ubtbcmfw.4 \
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uchcom.4 \
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@ -60,7 +60,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd March 27, 2020
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.Dd May 11, 2020
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.Dt CRYPTO 4
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.Os
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.Sh NAME
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@ -424,7 +424,6 @@ The semantics of these arguments are currently undocumented.
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.Xr ipsec 4 ,
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.Xr padlock 4 ,
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.Xr safe 4 ,
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.Xr ubsec 4 ,
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.Xr crypto 7 ,
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.Xr geli 8 ,
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.Xr crypto 9
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@ -25,7 +25,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd March 11, 2003
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.Dd May 11, 2020
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.Dt RNDTEST 4
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.Os
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.Sh NAME
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@ -54,7 +54,6 @@ Failures are optionally reported on the console.
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.Xr hifn 4 ,
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.Xr random 4 ,
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.Xr safe 4 ,
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.Xr ubsec 4 ,
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.Xr crypto 9
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.Sh HISTORY
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The idea for this and the original code came from
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@ -1,132 +0,0 @@
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.\" $OpenBSD: ubsec.4,v 1.25 2003/08/12 19:42:46 jason Exp $
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.\"
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.\" Copyright (c) 2000 Jason L. Wright (jason@thought.net)
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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.\" WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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.\" DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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.\" INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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.\" (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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.\" SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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.\" STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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.\" ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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.\" POSSIBILITY OF SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd May 16, 2009
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.Dt UBSEC 4
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.Os
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.Sh NAME
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.Nm ubsec
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.Nd Broadcom and BlueSteel uBsec 5x0x crypto accelerator
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.Sh SYNOPSIS
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To compile this driver into the kernel,
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place the following lines in your
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kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device crypto"
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.Cd "device cryptodev"
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.Cd "device ubsec"
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.Ed
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.Pp
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Alternatively, to load the driver as a
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module at boot time, place the following line in
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.Xr loader.conf 5 :
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.Bd -literal -offset indent
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ubsec_load="YES"
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.Ed
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.Sh DEPRECATION NOTICE
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The
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.Nm
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driver is not present in
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.Fx 13.0
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and later.
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The majority of crypto algorithms supported by this driver are no longer
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used by the kernel in
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.Fx 13.0 .
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.Sh DESCRIPTION
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The
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.Nm
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driver supports cards containing Broadcom and BlueSteel uBsec 5x0x
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crypto accelerator chips.
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.Pp
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The
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.Nm
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driver registers itself to accelerate DES, Triple-DES, MD5-HMAC,
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and SHA1-HMAC operations for
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.Xr ipsec 4
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and
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.Xr crypto 4 .
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.Pp
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On those models which contain a public key engine (almost all of the
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more recent ones), this feature is registered with the
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.Xr crypto 4
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subsystem.
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.Pp
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On all models except the Bluesteel 5501 and Broadcom 5801, the driver
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registers itself to provide random data to the
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.Xr random 4
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subsystem.
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.Sh HARDWARE
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The
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.Nm
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driver supports cards containing any of the following chips:
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.Bl -tag -width "Broadcom BCM5822" -offset indent
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.It Bluesteel 5501
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The original chipset, no longer made.
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This extremely rare unit
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was not very fast, lacked an RNG, and had a number of other bugs.
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.It Bluesteel 5601
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A faster and fixed version of the original, with a random number
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unit and large number engine added.
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.It Broadcom BCM5801
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A BCM5805 without public key engine or random number generator.
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.It Broadcom BCM5802
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A slower version of the BCM5805.
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.It Broadcom BCM5805
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Faster version of Bluesteel 5601.
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.It Broadcom BCM5820
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64 bit version of the chip, and significantly more advanced.
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.It Broadcom BCM5821
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Faster version of the BCM5820.
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This is the chip found on the Sun Crypto Accelerator 1000.
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.It Broadcom BCM5822
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Faster version of the BCM5820.
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.It Broadcom BCM5823
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A BCM5822 with AES capability.
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.It Broadcom BCM5825
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Faster version of the BCM5823.
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.El
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.Sh SEE ALSO
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.Xr crypt 3 ,
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.Xr crypto 4 ,
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.Xr intro 4 ,
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.Xr ipsec 4 ,
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.Xr random 4 ,
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.Xr crypto 9
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.Sh HISTORY
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The
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.Nm
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device driver appeared in
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.Ox 2.8 .
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The
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.Nm
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device driver was imported to
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.Fx 5.0 .
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.Sh BUGS
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The BCM5801 and BCM5802 have not actually been tested.
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The AES capability of the BCM5823 is not yet supported; it is awaiting
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public disclosure of programming information from Broadcom.
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@ -2630,10 +2630,6 @@ device hifn # Hifn 7951, 7781, etc.
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options HIFN_DEBUG # enable debugging support: hw.hifn.debug
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options HIFN_RNDTEST # enable rndtest support
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device ubsec # Broadcom 5501, 5601, 58xx
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options UBSEC_DEBUG # enable debugging support: hw.ubsec.debug
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options UBSEC_RNDTEST # enable rndtest support
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#####################################################################
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@ -3182,7 +3182,6 @@ dev/uart/uart_dev_z8530.c optional uart uart_z8530 | uart scc
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dev/uart/uart_if.m optional uart
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dev/uart/uart_subr.c optional uart
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dev/uart/uart_tty.c optional uart
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dev/ubsec/ubsec.c optional ubsec
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#
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# USB controller drivers
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#
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@ -734,11 +734,6 @@ BCE_NVRAM_WRITE_SUPPORT opt_bce.h
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SOCKBUF_DEBUG opt_global.h
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# options for ubsec driver
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UBSEC_DEBUG opt_ubsec.h
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UBSEC_RNDTEST opt_ubsec.h
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UBSEC_NO_RNG opt_ubsec.h
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# options for hifn driver
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HIFN_DEBUG opt_hifn.h
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HIFN_RNDTEST opt_hifn.h
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@ -347,7 +347,6 @@ static const char *random_source_descr[ENTROPYSOURCE] = {
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[RANDOM_PURE_OCTEON] = "PURE_OCTEON", /* PURE_START */
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[RANDOM_PURE_SAFE] = "PURE_SAFE",
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[RANDOM_PURE_GLXSB] = "PURE_GLXSB",
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[RANDOM_PURE_UBSEC] = "PURE_UBSEC",
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[RANDOM_PURE_HIFN] = "PURE_HIFN",
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[RANDOM_PURE_RDRAND] = "PURE_RDRAND",
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[RANDOM_PURE_NEHEMIAH] = "PURE_NEHEMIAH",
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File diff suppressed because it is too large
Load Diff
@ -1,222 +0,0 @@
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/* $FreeBSD$ */
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/* $OpenBSD: ubsecreg.h,v 1.27 2002/09/11 22:40:31 jason Exp $ */
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/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2000 Theo de Raadt
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* Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Effort sponsored in part by the Defense Advanced Research Projects
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* Agency (DARPA) and Air Force Research Laboratory, Air Force
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* Materiel Command, USAF, under agreement number F30602-01-2-0537.
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*
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*/
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/*
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* Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband
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* Security "uBSec" chip. Definitions from revision 2.8 of the product
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* datasheet.
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*/
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#define BS_BAR 0x10 /* DMA base address register */
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#define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */
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#define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */
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#define PCI_VENDOR_BROADCOM 0x14e4 /* Broadcom */
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#define PCI_VENDOR_BLUESTEEL 0x15ab /* Bluesteel Networks */
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#define PCI_VENDOR_SUN 0x108e /* Sun Microsystems */
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/* Bluesteel Networks */
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#define PCI_PRODUCT_BLUESTEEL_5501 0x0000 /* 5501 */
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#define PCI_PRODUCT_BLUESTEEL_5601 0x5601 /* 5601 */
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/* Broadcom */
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#define PCI_PRODUCT_BROADCOM_BCM5700 0x1644 /* BCM5700 */
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#define PCI_PRODUCT_BROADCOM_BCM5701 0x1645 /* BCM5701 */
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#define PCI_PRODUCT_BROADCOM_5801 0x5801 /* 5801 */
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#define PCI_PRODUCT_BROADCOM_5802 0x5802 /* 5802 */
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#define PCI_PRODUCT_BROADCOM_5805 0x5805 /* 5805 */
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#define PCI_PRODUCT_BROADCOM_5820 0x5820 /* 5820 */
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#define PCI_PRODUCT_BROADCOM_5821 0x5821 /* 5821 */
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#define PCI_PRODUCT_BROADCOM_5822 0x5822 /* 5822 */
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#define PCI_PRODUCT_BROADCOM_5823 0x5823 /* 5823 */
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#define PCI_PRODUCT_BROADCOM_5825 0x5825 /* 5825 */
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/* Sun Microsystems */
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#define PCI_PRODUCT_SUN_5821 0x5454 /* Crypto 5821 */
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#define PCI_PRODUCT_SUN_SCA1K 0x5455 /* Crypto 1K */
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#define UBS_PCI_RTY_SHIFT 8
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#define UBS_PCI_RTY_MASK 0xff
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#define UBS_PCI_RTY(misc) \
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(((misc) >> UBS_PCI_RTY_SHIFT) & UBS_PCI_RTY_MASK)
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#define UBS_PCI_TOUT_SHIFT 0
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#define UBS_PCI_TOUT_MASK 0xff
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#define UBS_PCI_TOUT(misc) \
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(((misc) >> PCI_TOUT_SHIFT) & PCI_TOUT_MASK)
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/*
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* DMA Control & Status Registers (offset from BS_BAR)
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*/
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#define BS_MCR1 0x00 /* DMA Master Command Record 1 */
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#define BS_CTRL 0x04 /* DMA Control */
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#define BS_STAT 0x08 /* DMA Status */
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#define BS_ERR 0x0c /* DMA Error Address */
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#define BS_MCR2 0x10 /* DMA Master Command Record 2 */
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/* BS_CTRL - DMA Control */
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#define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */
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#define BS_CTRL_MCR2INT 0x40000000 /* enable intr MCR for MCR2 */
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#define BS_CTRL_MCR1INT 0x20000000 /* enable intr MCR for MCR1 */
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#define BS_CTRL_OFM 0x10000000 /* Output fragment mode */
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#define BS_CTRL_BE32 0x08000000 /* big-endian, 32bit bytes */
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#define BS_CTRL_BE64 0x04000000 /* big-endian, 64bit bytes */
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#define BS_CTRL_DMAERR 0x02000000 /* enable intr DMA error */
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#define BS_CTRL_RNG_M 0x01800000 /* RNG mode */
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#define BS_CTRL_RNG_1 0x00000000 /* 1bit rn/one slow clock */
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#define BS_CTRL_RNG_4 0x00800000 /* 1bit rn/four slow clocks */
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#define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */
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#define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */
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#define BS_CTRL_SWNORM 0x00400000 /* 582[01], sw normalization */
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#define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */
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#define BS_CTRL_LITTLE_ENDIAN (BS_CTRL_BE32 | BS_CTRL_BE64)
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/* BS_STAT - DMA Status */
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#define BS_STAT_MCR1_BUSY 0x80000000 /* MCR1 is busy */
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#define BS_STAT_MCR1_FULL 0x40000000 /* MCR1 is full */
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#define BS_STAT_MCR1_DONE 0x20000000 /* MCR1 is done */
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#define BS_STAT_DMAERR 0x10000000 /* DMA error */
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#define BS_STAT_MCR2_FULL 0x08000000 /* MCR2 is full */
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#define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */
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#define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* 5821, MCR1 is empty */
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#define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* 5821, MCR2 is empty */
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/* BS_ERR - DMA Error Address */
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#define BS_ERR_ADDR 0xfffffffc /* error address mask */
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#define BS_ERR_READ 0x00000002 /* fault was on read */
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struct ubsec_pktctx {
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u_int32_t pc_deskey[6]; /* 3DES key */
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u_int32_t pc_hminner[5]; /* hmac inner state */
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u_int32_t pc_hmouter[5]; /* hmac outer state */
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u_int32_t pc_iv[2]; /* [3]DES iv */
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u_int16_t pc_flags; /* flags, below */
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u_int16_t pc_offset; /* crypto offset */
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};
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#define UBS_PKTCTX_ENC_3DES 0x8000 /* use 3des */
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#define UBS_PKTCTX_ENC_NONE 0x0000 /* no encryption */
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#define UBS_PKTCTX_INBOUND 0x4000 /* inbound packet */
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#define UBS_PKTCTX_AUTH 0x3000 /* authentication mask */
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#define UBS_PKTCTX_AUTH_NONE 0x0000 /* no authentication */
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#define UBS_PKTCTX_AUTH_MD5 0x1000 /* use hmac-md5 */
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#define UBS_PKTCTX_AUTH_SHA1 0x2000 /* use hmac-sha1 */
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struct ubsec_pktctx_long {
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volatile u_int16_t pc_len; /* length of ctx struct */
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volatile u_int16_t pc_type; /* context type, 0 */
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volatile u_int16_t pc_flags; /* flags, same as above */
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volatile u_int16_t pc_offset; /* crypto/auth offset */
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volatile u_int32_t pc_deskey[6]; /* 3DES key */
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volatile u_int32_t pc_iv[2]; /* [3]DES iv */
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volatile u_int32_t pc_hminner[5]; /* hmac inner state */
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volatile u_int32_t pc_hmouter[5]; /* hmac outer state */
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};
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#define UBS_PKTCTX_TYPE_IPSEC 0x0000
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struct ubsec_pktbuf {
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volatile u_int32_t pb_addr; /* address of buffer start */
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volatile u_int32_t pb_next; /* pointer to next pktbuf */
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volatile u_int32_t pb_len; /* packet length */
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};
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#define UBS_PKTBUF_LEN 0x0000ffff /* length mask */
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struct ubsec_mcr {
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volatile u_int16_t mcr_pkts; /* #pkts in this mcr */
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volatile u_int16_t mcr_flags; /* mcr flags (below) */
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volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */
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struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */
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volatile u_int16_t mcr_reserved;
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volatile u_int16_t mcr_pktlen;
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struct ubsec_pktbuf mcr_opktbuf; /* output chain header */
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};
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struct ubsec_mcr_add {
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volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */
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struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */
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volatile u_int16_t mcr_reserved;
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volatile u_int16_t mcr_pktlen;
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struct ubsec_pktbuf mcr_opktbuf; /* output chain header */
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};
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#define UBS_MCR_DONE 0x0001 /* mcr has been processed */
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#define UBS_MCR_ERROR 0x0002 /* error in processing */
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#define UBS_MCR_ERRORCODE 0xff00 /* error type */
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struct ubsec_ctx_keyop {
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volatile u_int16_t ctx_len; /* command length */
|
||||
volatile u_int16_t ctx_op; /* operation code */
|
||||
volatile u_int8_t ctx_pad[60]; /* padding */
|
||||
};
|
||||
#define UBS_CTXOP_DHPKGEN 0x01 /* dh public key generation */
|
||||
#define UBS_CTXOP_DHSSGEN 0x02 /* dh shared secret gen. */
|
||||
#define UBS_CTXOP_RSAPUB 0x03 /* rsa public key op */
|
||||
#define UBS_CTXOP_RSAPRIV 0x04 /* rsa private key op */
|
||||
#define UBS_CTXOP_DSASIGN 0x05 /* dsa signing op */
|
||||
#define UBS_CTXOP_DSAVRFY 0x06 /* dsa verification */
|
||||
#define UBS_CTXOP_RNGBYPASS 0x41 /* rng direct test mode */
|
||||
#define UBS_CTXOP_RNGSHA1 0x42 /* rng sha1 test mode */
|
||||
#define UBS_CTXOP_MODADD 0x43 /* modular addition */
|
||||
#define UBS_CTXOP_MODSUB 0x44 /* modular subtraction */
|
||||
#define UBS_CTXOP_MODMUL 0x45 /* modular multiplication */
|
||||
#define UBS_CTXOP_MODRED 0x46 /* modular reduction */
|
||||
#define UBS_CTXOP_MODEXP 0x47 /* modular exponentiation */
|
||||
#define UBS_CTXOP_MODINV 0x48 /* modular inverse */
|
||||
|
||||
struct ubsec_ctx_rngbypass {
|
||||
volatile u_int16_t rbp_len; /* command length, 64 */
|
||||
volatile u_int16_t rbp_op; /* rng bypass, 0x41 */
|
||||
volatile u_int8_t rbp_pad[60]; /* padding */
|
||||
};
|
||||
|
||||
/* modexp: C = (M ^ E) mod N */
|
||||
struct ubsec_ctx_modexp {
|
||||
volatile u_int16_t me_len; /* command length */
|
||||
volatile u_int16_t me_op; /* modexp, 0x47 */
|
||||
volatile u_int16_t me_E_len; /* E (bits) */
|
||||
volatile u_int16_t me_N_len; /* N (bits) */
|
||||
u_int8_t me_N[2048/8]; /* N */
|
||||
};
|
||||
|
||||
struct ubsec_ctx_rsapriv {
|
||||
volatile u_int16_t rpr_len; /* command length */
|
||||
volatile u_int16_t rpr_op; /* rsaprivate, 0x04 */
|
||||
volatile u_int16_t rpr_q_len; /* q (bits) */
|
||||
volatile u_int16_t rpr_p_len; /* p (bits) */
|
||||
u_int8_t rpr_buf[5 * 1024 / 8]; /* parameters: */
|
||||
/* p, q, dp, dq, pinv */
|
||||
};
|
||||
@ -1,246 +0,0 @@
|
||||
/* $FreeBSD$ */
|
||||
/* $OpenBSD: ubsecvar.h,v 1.35 2002/09/24 18:33:26 jason Exp $ */
|
||||
|
||||
/*-
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 2000 Theo de Raadt
|
||||
* Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Effort sponsored in part by the Defense Advanced Research Projects
|
||||
* Agency (DARPA) and Air Force Research Laboratory, Air Force
|
||||
* Materiel Command, USAF, under agreement number F30602-01-2-0537.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Maximum queue length */
|
||||
#ifndef UBS_MAX_NQUEUE
|
||||
#define UBS_MAX_NQUEUE 60
|
||||
#endif
|
||||
|
||||
#define UBS_MAX_SCATTER 64 /* Maximum scatter/gather depth */
|
||||
|
||||
#ifndef UBS_MAX_AGGR
|
||||
#define UBS_MAX_AGGR 5 /* Maximum aggregation count */
|
||||
#endif
|
||||
|
||||
#define UBS_DEF_RTY 0xff /* PCI Retry Timeout */
|
||||
#define UBS_DEF_TOUT 0xff /* PCI TRDY Timeout */
|
||||
#define UBS_DEF_CACHELINE 0x01 /* Cache Line setting */
|
||||
|
||||
#ifdef _KERNEL
|
||||
|
||||
struct ubsec_dma_alloc {
|
||||
u_int32_t dma_paddr;
|
||||
caddr_t dma_vaddr;
|
||||
bus_dma_tag_t dma_tag;
|
||||
bus_dmamap_t dma_map;
|
||||
bus_dma_segment_t dma_seg;
|
||||
bus_size_t dma_size;
|
||||
int dma_nseg;
|
||||
};
|
||||
|
||||
struct ubsec_q2 {
|
||||
SIMPLEQ_ENTRY(ubsec_q2) q_next;
|
||||
struct ubsec_dma_alloc q_mcr;
|
||||
struct ubsec_dma_alloc q_ctx;
|
||||
u_int q_type;
|
||||
};
|
||||
|
||||
struct ubsec_q2_rng {
|
||||
struct ubsec_q2 rng_q;
|
||||
struct ubsec_dma_alloc rng_buf;
|
||||
int rng_used;
|
||||
};
|
||||
|
||||
/* C = (M ^ E) mod N */
|
||||
#define UBS_MODEXP_PAR_M 0
|
||||
#define UBS_MODEXP_PAR_E 1
|
||||
#define UBS_MODEXP_PAR_N 2
|
||||
#define UBS_MODEXP_PAR_C 3
|
||||
struct ubsec_q2_modexp {
|
||||
struct ubsec_q2 me_q;
|
||||
struct cryptkop * me_krp;
|
||||
struct ubsec_dma_alloc me_M;
|
||||
struct ubsec_dma_alloc me_E;
|
||||
struct ubsec_dma_alloc me_C;
|
||||
struct ubsec_dma_alloc me_epb;
|
||||
int me_modbits;
|
||||
int me_shiftbits;
|
||||
int me_normbits;
|
||||
};
|
||||
|
||||
#define UBS_RSAPRIV_PAR_P 0
|
||||
#define UBS_RSAPRIV_PAR_Q 1
|
||||
#define UBS_RSAPRIV_PAR_DP 2
|
||||
#define UBS_RSAPRIV_PAR_DQ 3
|
||||
#define UBS_RSAPRIV_PAR_PINV 4
|
||||
#define UBS_RSAPRIV_PAR_MSGIN 5
|
||||
#define UBS_RSAPRIV_PAR_MSGOUT 6
|
||||
struct ubsec_q2_rsapriv {
|
||||
struct ubsec_q2 rpr_q;
|
||||
struct cryptkop * rpr_krp;
|
||||
struct ubsec_dma_alloc rpr_msgin;
|
||||
struct ubsec_dma_alloc rpr_msgout;
|
||||
};
|
||||
|
||||
#define UBSEC_RNG_BUFSIZ 16 /* measured in 32bit words */
|
||||
|
||||
struct ubsec_dmachunk {
|
||||
struct ubsec_mcr d_mcr;
|
||||
struct ubsec_mcr_add d_mcradd[UBS_MAX_AGGR-1];
|
||||
struct ubsec_pktbuf d_sbuf[UBS_MAX_SCATTER-1];
|
||||
struct ubsec_pktbuf d_dbuf[UBS_MAX_SCATTER-1];
|
||||
u_int32_t d_macbuf[5];
|
||||
union {
|
||||
struct ubsec_pktctx_long ctxl;
|
||||
struct ubsec_pktctx ctx;
|
||||
} d_ctx;
|
||||
};
|
||||
|
||||
struct ubsec_dma {
|
||||
SIMPLEQ_ENTRY(ubsec_dma) d_next;
|
||||
struct ubsec_dmachunk *d_dma;
|
||||
struct ubsec_dma_alloc d_alloc;
|
||||
};
|
||||
|
||||
#define UBS_FLAGS_KEY 0x01 /* has key accelerator */
|
||||
#define UBS_FLAGS_LONGCTX 0x02 /* uses long ipsec ctx */
|
||||
#define UBS_FLAGS_BIGKEY 0x04 /* 2048bit keys */
|
||||
#define UBS_FLAGS_HWNORM 0x08 /* hardware normalization */
|
||||
#define UBS_FLAGS_RNG 0x10 /* hardware rng */
|
||||
|
||||
struct ubsec_operand {
|
||||
bus_dmamap_t map;
|
||||
bus_size_t mapsize;
|
||||
int nsegs;
|
||||
bus_dma_segment_t segs[UBS_MAX_SCATTER];
|
||||
};
|
||||
|
||||
struct ubsec_q {
|
||||
SIMPLEQ_ENTRY(ubsec_q) q_next;
|
||||
int q_nstacked_mcrs;
|
||||
struct ubsec_q *q_stacked_mcr[UBS_MAX_AGGR-1];
|
||||
struct cryptop *q_crp;
|
||||
struct ubsec_dma *q_dma;
|
||||
|
||||
struct ubsec_operand q_src;
|
||||
struct ubsec_operand q_dst;
|
||||
struct mbuf *q_dst_m;
|
||||
|
||||
int q_flags;
|
||||
};
|
||||
|
||||
#define q_src_map q_src.map
|
||||
#define q_src_nsegs q_src.nsegs
|
||||
#define q_src_segs q_src.segs
|
||||
#define q_src_mapsize q_src.mapsize
|
||||
|
||||
#define q_dst_map q_dst.map
|
||||
#define q_dst_nsegs q_dst.nsegs
|
||||
#define q_dst_segs q_dst.segs
|
||||
#define q_dst_mapsize q_dst.mapsize
|
||||
|
||||
struct rndstate_test;
|
||||
|
||||
struct ubsec_softc {
|
||||
device_t sc_dev; /* device backpointer */
|
||||
struct resource *sc_irq;
|
||||
void *sc_ih; /* interrupt handler cookie */
|
||||
bus_space_handle_t sc_sh; /* memory handle */
|
||||
bus_space_tag_t sc_st; /* memory tag */
|
||||
struct resource *sc_sr; /* memory resource */
|
||||
bus_dma_tag_t sc_dmat; /* dma tag */
|
||||
int sc_flags; /* device specific flags */
|
||||
int sc_suspended;
|
||||
int sc_needwakeup; /* notify crypto layer */
|
||||
u_int32_t sc_statmask; /* interrupt status mask */
|
||||
int32_t sc_cid; /* crypto tag */
|
||||
struct mtx sc_mcr1lock; /* mcr1 operation lock */
|
||||
SIMPLEQ_HEAD(,ubsec_q) sc_queue; /* packet queue, mcr1 */
|
||||
int sc_nqueue; /* count enqueued, mcr1 */
|
||||
SIMPLEQ_HEAD(,ubsec_q) sc_qchip; /* on chip, mcr1 */
|
||||
int sc_nqchip; /* count on chip, mcr1 */
|
||||
struct mtx sc_freeqlock; /* freequeue lock */
|
||||
SIMPLEQ_HEAD(,ubsec_q) sc_freequeue; /* list of free queue elements */
|
||||
struct mtx sc_mcr2lock; /* mcr2 operation lock */
|
||||
SIMPLEQ_HEAD(,ubsec_q2) sc_queue2; /* packet queue, mcr2 */
|
||||
int sc_nqueue2; /* count enqueued, mcr2 */
|
||||
SIMPLEQ_HEAD(,ubsec_q2) sc_qchip2; /* on chip, mcr2 */
|
||||
struct callout sc_rngto; /* rng timeout */
|
||||
int sc_rnghz; /* rng poll time */
|
||||
struct ubsec_q2_rng sc_rng;
|
||||
struct rndtest_state *sc_rndtest; /* RNG test state */
|
||||
void (*sc_harvest)(struct rndtest_state *,
|
||||
void *, u_int);
|
||||
struct ubsec_dma sc_dmaa[UBS_MAX_NQUEUE];
|
||||
struct ubsec_q *sc_queuea[UBS_MAX_NQUEUE];
|
||||
SIMPLEQ_HEAD(,ubsec_q2) sc_q2free; /* free list */
|
||||
};
|
||||
|
||||
#define UBSEC_QFLAGS_COPYOUTIV 0x1
|
||||
|
||||
struct ubsec_session {
|
||||
u_int32_t ses_deskey[6]; /* 3DES key */
|
||||
u_int32_t ses_mlen; /* hmac length */
|
||||
u_int32_t ses_hminner[5]; /* hmac inner state */
|
||||
u_int32_t ses_hmouter[5]; /* hmac outer state */
|
||||
};
|
||||
#endif /* _KERNEL */
|
||||
|
||||
struct ubsec_stats {
|
||||
u_int64_t hst_ibytes;
|
||||
u_int64_t hst_obytes;
|
||||
u_int32_t hst_ipackets;
|
||||
u_int32_t hst_opackets;
|
||||
u_int32_t hst_invalid; /* invalid argument */
|
||||
u_int32_t hst_badsession; /* invalid session id */
|
||||
u_int32_t hst_badflags; /* flags indicate !(mbuf | uio) */
|
||||
u_int32_t hst_nodesc; /* op submitted w/o descriptors */
|
||||
u_int32_t hst_badalg; /* unsupported algorithm */
|
||||
u_int32_t hst_nomem;
|
||||
u_int32_t hst_queuefull;
|
||||
u_int32_t hst_dmaerr;
|
||||
u_int32_t hst_mcrerr;
|
||||
u_int32_t hst_nodmafree;
|
||||
u_int32_t hst_lenmismatch; /* enc/auth lengths different */
|
||||
u_int32_t hst_skipmismatch; /* enc part begins before auth part */
|
||||
u_int32_t hst_iovmisaligned; /* iov op not aligned */
|
||||
u_int32_t hst_noirq; /* IRQ for no reason */
|
||||
u_int32_t hst_unaligned; /* unaligned src caused copy */
|
||||
u_int32_t hst_nomap; /* bus_dmamap_create failed */
|
||||
u_int32_t hst_noload; /* bus_dmamap_load_* failed */
|
||||
u_int32_t hst_nombuf; /* MGET* failed */
|
||||
u_int32_t hst_nomcl; /* MCLGET* failed */
|
||||
u_int32_t hst_totbatch; /* ops submitted w/o interrupt */
|
||||
u_int32_t hst_maxbatch; /* max ops submitted together */
|
||||
u_int32_t hst_maxqueue; /* max ops queued for submission */
|
||||
u_int32_t hst_maxqchip; /* max mcr1 ops out for processing */
|
||||
u_int32_t hst_mcr1full; /* MCR1 too busy to take ops */
|
||||
u_int32_t hst_rng; /* RNG requests */
|
||||
u_int32_t hst_modexp; /* MOD EXP requests */
|
||||
u_int32_t hst_modexpcrt; /* MOD EXP CRT requests */
|
||||
};
|
||||
@ -354,7 +354,6 @@ SUBDIR= \
|
||||
twe \
|
||||
tws \
|
||||
uart \
|
||||
ubsec \
|
||||
udf \
|
||||
udf_iconv \
|
||||
ufs \
|
||||
|
||||
@ -1,14 +0,0 @@
|
||||
# $FreeBSD$
|
||||
|
||||
.PATH: ${SRCTOP}/sys/dev/ubsec
|
||||
KMOD = ubsec
|
||||
SRCS = ubsec.c opt_ubsec.h
|
||||
SRCS += device_if.h bus_if.h pci_if.h
|
||||
SRCS += opt_bus.h cryptodev_if.h
|
||||
|
||||
.if !defined(KERNBUILDDIR)
|
||||
opt_ubsec.h:
|
||||
echo "#define UBSEC_DEBUG 1" > ${.TARGET}
|
||||
.endif
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
@ -92,7 +92,6 @@ enum random_entropy_source {
|
||||
RANDOM_PURE_OCTEON = RANDOM_PURE_START,
|
||||
RANDOM_PURE_SAFE,
|
||||
RANDOM_PURE_GLXSB,
|
||||
RANDOM_PURE_UBSEC,
|
||||
RANDOM_PURE_HIFN,
|
||||
RANDOM_PURE_RDRAND,
|
||||
RANDOM_PURE_NEHEMIAH,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user