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Make IPI_WAIT use a bit mask of the cpus that a pmap is active on and only

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wait for those cpus, instead of all of them by using a count.  Oops.
Make the pointer to the mask that the primary cpu spins on volatile, so
gcc doesn't optimize out an important load.  Oops again.
Activate tlb shootdown ipi synchronization now that it works.  We have
all involved cpus wait until all the others are done.  This may not be
necessary, it is mostly for sanity.
Make the trigger level interrupt ipi handler work.

Submitted by:	tmm
This commit is contained in:
jake 2002-03-13 03:43:00 +00:00
parent 6ee80641df
commit df6db29bae
4 changed files with 50 additions and 43 deletions
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30
sys/sparc64/include/smp.h
View File

@ -57,13 +57,8 @@ struct cpu_start_args {
struct tte csa_ttes[PCPU_PAGES];
};
struct ipi_level_args {
u_int ila_count;
u_int ila_level;
};
struct ipi_tlb_args {
u_int ita_count;
u_int ita_mask;
u_long ita_tlb;
struct pmap *ita_pmap;
u_long ita_start;
@ -74,6 +69,7 @@ struct ipi_tlb_args {
struct pcpu;
void cpu_mp_bootstrap(struct pcpu *pc);
void cpu_mp_shutdown(void);
void cpu_ipi_selected(u_int cpus, u_long d0, u_long d1, u_long d2);
void cpu_ipi_send(u_int mid, u_long d0, u_long d1, u_long d2);
@ -116,11 +112,11 @@ ipi_tlb_context_demap(struct pmap *pm)
if ((cpus = (pm->pm_active & PCPU_GET(other_cpus))) == 0)
return (NULL);
ita = &ipi_tlb_args;
ita->ita_count = smp_cpus;
ita->ita_mask = cpus | PCPU_GET(cpumask);
ita->ita_pmap = pm;
cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_context_demap,
(u_long)ita);
return (&ita->ita_count);
return (&ita->ita_mask);
}
static __inline void *
@ -134,12 +130,12 @@ ipi_tlb_page_demap(u_int tlb, struct pmap *pm, vm_offset_t va)
if ((cpus = (pm->pm_active & PCPU_GET(other_cpus))) == 0)
return (NULL);
ita = &ipi_tlb_args;
ita->ita_count = smp_cpus;
ita->ita_mask = cpus | PCPU_GET(cpumask);
ita->ita_tlb = tlb;
ita->ita_pmap = pm;
ita->ita_va = va;
cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_page_demap, (u_long)ita);
return (&ita->ita_count);
return (&ita->ita_mask);
}
static __inline void *
@ -153,26 +149,24 @@ ipi_tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end)
if ((cpus = (pm->pm_active & PCPU_GET(other_cpus))) == 0)
return (NULL);
ita = &ipi_tlb_args;
ita->ita_count = smp_cpus;
ita->ita_mask = cpus | PCPU_GET(cpumask);
ita->ita_pmap = pm;
ita->ita_start = start;
ita->ita_end = end;
cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_range_demap, (u_long)ita);
return (&ita->ita_count);
return (&ita->ita_mask);
}
static __inline void
ipi_wait(void *cookie)
{
#if 0
u_int *count;
u_int *volatile mask;
if ((count = cookie) != NULL) {
atomic_subtract_int(count, 1);
while (*count != 0)
if ((mask = cookie) != NULL) {
atomic_clear_int(mask, PCPU_GET(cpumask));
while (*mask != 0)
;
}
#endif
}
#endif

7
sys/sparc64/sparc64/genassym.c
View File

@ -134,6 +134,7 @@ ASSYM(KTR_CT8, KTR_CT8);
ASSYM(KTR_SIZEOF, sizeof(struct ktr_entry));
ASSYM(KTR_DESC, offsetof(struct ktr_entry, ktr_desc));
ASSYM(KTR_CPU, offsetof(struct ktr_entry, ktr_cpu));
ASSYM(KTR_PARM1, offsetof(struct ktr_entry, ktr_parm1));
ASSYM(KTR_PARM2, offsetof(struct ktr_entry, ktr_parm2));
ASSYM(KTR_PARM3, offsetof(struct ktr_entry, ktr_parm3));
@ -178,8 +179,7 @@ ASSYM(IQE_VEC, offsetof(struct iqe, iqe_vec));
ASSYM(IQE_FUNC, offsetof(struct iqe, iqe_func));
ASSYM(IQE_ARG, offsetof(struct iqe, iqe_arg));
ASSYM(ILA_LEVEL, offsetof(struct ipi_level_args, ila_level));
ASSYM(ITA_MASK, offsetof(struct ipi_tlb_args, ita_mask));
ASSYM(ITA_TLB, offsetof(struct ipi_tlb_args, ita_tlb));
ASSYM(ITA_PMAP, offsetof(struct ipi_tlb_args, ita_pmap));
ASSYM(ITA_START, offsetof(struct ipi_tlb_args, ita_start));
@ -278,7 +278,4 @@ ASSYM(TF_PIL, offsetof(struct trapframe, tf_pil));
ASSYM(TF_WSTATE, offsetof(struct trapframe, tf_wstate));
ASSYM(TF_SIZEOF, sizeof(struct trapframe));
ASSYM(UPA_CR_MID_SHIFT, UPA_CR_MID_SHIFT);
ASSYM(UPA_CR_MID_SIZE, UPA_CR_MID_SIZE);
ASSYM(UT_MAX, UT_MAX);

28
sys/sparc64/sparc64/mp_exception.S
View File

@ -36,9 +36,9 @@
.register %g2, #ignore
.register %g3, #ignore
#if 0
#define IPI_WAIT(r1, r2, r3) \
ATOMIC_DEC_INT(r1, r2, r3) ; \
#define IPI_WAIT(r1, r2, r3, r4) \
lduw [PCPU(CPUMASK)], r4 ; \
ATOMIC_CLEAR_INT(r1, r2, r3, r4) ; \
9: lduw [r1], r2 ; \
brnz,a,pn r2, 9b ; \
nop
@ -50,13 +50,21 @@
* Trigger a softint at the desired level.
*/
ENTRY(tl_ipi_level)
lduw [%g5 + ILA_LEVEL], %g2
#if KTR_COMPILE & KTR_SMP
CATR(KTR_SMP, "tl_ipi_level: cpuid=%d mid=%d d1=%#lx d2=%#lx"
, %g1, %g2, %g3, 7, 8, 9)
lduw [PCPU(CPUID)], %g2
stx %g2, [%g1 + KTR_PARM1]
lduw [PCPU(MID)], %g2
stx %g2, [%g1 + KTR_PARM2]
stx %g4, [%g1 + KTR_PARM3]
stx %g5, [%g1 + KTR_PARM4]
9:
#endif
mov 1, %g1
sllx %g1, %g2, %g1
sllx %g1, %g5, %g1
wr %g1, 0, %asr20
IPI_WAIT(%g5, %g1, %g2)
retry
END(tl_ipi_level)
@ -113,7 +121,7 @@ ENTRY(tl_ipi_tlb_page_demap)
stxa %g0, [%g2] ASI_IMMU_DEMAP
membar #Sync
2: IPI_WAIT(%g5, %g1, %g2)
2: IPI_WAIT(%g5, %g1, %g2, %g3)
retry
END(tl_ipi_tlb_page_demap)
@ -156,7 +164,7 @@ ENTRY(tl_ipi_tlb_range_demap)
blt,a,pt %xcc, 1b
nop
IPI_WAIT(%g5, %g1, %g2)
IPI_WAIT(%g5, %g1, %g2, %g3)
retry
END(tl_ipi_tlb_range_demap)
@ -179,6 +187,6 @@ ENTRY(tl_ipi_tlb_context_demap)
stxa %g0, [%g1] ASI_IMMU_DEMAP
membar #Sync
IPI_WAIT(%g5, %g1, %g2)
IPI_WAIT(%g5, %g1, %g2, %g3)
retry
END(tl_ipi_tlb_context_demap)

28
sys/sparc64/sparc64/mp_exception.s
View File

@ -36,9 +36,9 @@
.register %g2, #ignore
.register %g3, #ignore
#if 0
#define IPI_WAIT(r1, r2, r3) \
ATOMIC_DEC_INT(r1, r2, r3) ; \
#define IPI_WAIT(r1, r2, r3, r4) \
lduw [PCPU(CPUMASK)], r4 ; \
ATOMIC_CLEAR_INT(r1, r2, r3, r4) ; \
9: lduw [r1], r2 ; \
brnz,a,pn r2, 9b ; \
nop
@ -50,13 +50,21 @@
* Trigger a softint at the desired level.
*/
ENTRY(tl_ipi_level)
lduw [%g5 + ILA_LEVEL], %g2
#if KTR_COMPILE & KTR_SMP
CATR(KTR_SMP, "tl_ipi_level: cpuid=%d mid=%d d1=%#lx d2=%#lx"
, %g1, %g2, %g3, 7, 8, 9)
lduw [PCPU(CPUID)], %g2
stx %g2, [%g1 + KTR_PARM1]
lduw [PCPU(MID)], %g2
stx %g2, [%g1 + KTR_PARM2]
stx %g4, [%g1 + KTR_PARM3]
stx %g5, [%g1 + KTR_PARM4]
9:
#endif
mov 1, %g1
sllx %g1, %g2, %g1
sllx %g1, %g5, %g1
wr %g1, 0, %asr20
IPI_WAIT(%g5, %g1, %g2)
retry
END(tl_ipi_level)
@ -113,7 +121,7 @@ ENTRY(tl_ipi_tlb_page_demap)
stxa %g0, [%g2] ASI_IMMU_DEMAP
membar #Sync
2: IPI_WAIT(%g5, %g1, %g2)
2: IPI_WAIT(%g5, %g1, %g2, %g3)
retry
END(tl_ipi_tlb_page_demap)
@ -156,7 +164,7 @@ ENTRY(tl_ipi_tlb_range_demap)
blt,a,pt %xcc, 1b
nop
IPI_WAIT(%g5, %g1, %g2)
IPI_WAIT(%g5, %g1, %g2, %g3)
retry
END(tl_ipi_tlb_range_demap)
@ -179,6 +187,6 @@ ENTRY(tl_ipi_tlb_context_demap)
stxa %g0, [%g1] ASI_IMMU_DEMAP
membar #Sync
IPI_WAIT(%g5, %g1, %g2)
IPI_WAIT(%g5, %g1, %g2, %g3)
retry
END(tl_ipi_tlb_context_demap)