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When doing busdma sync ops for BUSDMA_COHERENT memory, there is no need

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for cache maintenance operations, but ensure that all prior writes have
reached memory when doing a PREWRITE sync.

Submitted by:	Michal Meloun <meloun@miracle.cz>
This commit is contained in:
Ian Lepore 2014-11-15 03:39:58 +00:00
parent cf902afcac
commit df826e78d4
1 changed files with 11 additions and 1 deletions
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12
sys/arm/arm/busdma_machdep-v6.c
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@ -1385,8 +1385,18 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op)
dmat->bounce_zone->total_bounced++;
}
}
if (map->flags & DMAMAP_COHERENT)
/*
* For COHERENT memory no cache maintenance is necessary, but ensure all
* writes have reached memory for the PREWRITE case.
*/
if (map->flags & DMAMAP_COHERENT) {
if (op & BUS_DMASYNC_PREWRITE) {
dsb();
cpu_l2cache_drain_writebuf();
}
return;
}
if (map->sync_count != 0) {
if (!pmap_dmap_iscurrent(map->pmap))