Sync BERI kernel configs with P4:
Switch the majority of device configuration to FDT from hints. Add BERI_*_BASE configs to reduce duplication in the MDROOT and SDROOT kernels. Add NFS and GSSAPI support by default. MFC after: 3 days Sponsored by: DARPA/AFRL
This commit is contained in:
brooks
parent
6a1ac1b4fa
commit
e0414fcda4
144
sys/boot/fdt/dts/beri-sim.dts
Normal file
144
sys/boot/fdt/dts/beri-sim.dts
Normal file
@ -0,0 +1,144 @@
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/*-
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* Copyright (c) 2012-2013 Robert N. M. Watson
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* Copyright (c) 2013 SRI International
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/dts-v1/;
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/*
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* Device names here have been largely made up on the spot, especially for the
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* "compatible" strings, and might want to be revised.
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*
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* For now, use 32-bit addressing as our Avalon bus is 32-bit. However, in
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* the future, we should likely change to 64-bit.
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*/
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/ {
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model = "SRI/Cambridge BERI simulation";
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compatible = "sri-cambridge,beri-sim";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* Secondary CPUs all start disabled and use the
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* spin-table enable method. cpu-release-addr must be
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* specified for each cpu other than cpu@0. Values of
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* cpu-release-addr grow down from 0x100000 (kernel).
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*/
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status = "disabled";
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enable-method = "spin-table";
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cpu@0 {
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device-type = "cpu";
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compatible = "sri-cambridge,beri";
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reg = <0>;
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status = "okay";
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};
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/*
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cpu@1 {
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device-type = "cpu";
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compatible = "sri-cambridge,beri";
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reg = <1>;
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// XXX: should we need cached prefix?
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cpu-release-addr = <0xffffffff 0x800fffe0>;
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};
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*/
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <1>;
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/*
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* Declare mips,mips4k since BERI doesn't (yet) have a PIC, so
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* we use mips4k coprocessor 0 interrupt management directly.
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*/
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compatible = "simple-bus", "mips,mips4k";
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ranges = <>;
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memory {
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device_type = "memory";
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reg = <0x0 0x4000000>; // 64M at 0x0
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};
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beripic: beripic@7f804000 {
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compatible = "sri-cambridge,beri-pic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x7f804000 0x400
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0x7f806000 0x10
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0x7f806080 0x10
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0x7f806100 0x10>;
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interrupts = <0 1 2 3 4>;
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hard-interrupt-sources = <64>;
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soft-interrupt-sources = <64>;
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};
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serial@7f000000 {
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compatible = "altera,jtag_uart-11_0";
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reg = <0x7f000000 0x40>;
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interrupts = <0>;
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interrupt-parent = <&beripic>;
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};
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serial@7f001000 {
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compatible = "altera,jtag_uart-11_0";
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reg = <0x7f001000 0x40>;
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};
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serial@7f002000 {
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compatible = "altera,jtag_uart-11_0";
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reg = <0x7f002000 0x40>;
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};
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sdcard@7f008000 {
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compatible = "altera,sdcard_11_2011";
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reg = <0x7f008000 0x400>;
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};
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avgen@0x7f00a000 {
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compatible = "sri-cambridge,avgen";
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reg = <0x7f00a000 0x14>;
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sri-cambridge,width = <4>;
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sri-cambridge,fileio = "rw";
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sri-cambridge,devname = "berirom";
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};
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};
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};
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266
sys/boot/fdt/dts/beripad-de4.dts
Normal file
266
sys/boot/fdt/dts/beripad-de4.dts
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@ -0,0 +1,266 @@
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/*-
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* Copyright (c) 2012-2013 Robert N. M. Watson
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* Copyright (c) 2013 SRI International
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/dts-v1/;
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/*
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* Device names here have been largely made up on the spot, especially for the
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* "compatible" strings, and might want to be revised.
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*
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* For now, use 32-bit addressing as our Avalon bus is 32-bit. However, in
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* the future, we should likely change to 64-bit.
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*/
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/ {
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model = "SRI/Cambridge BeriPad (DE4)";
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compatible = "sri-cambridge,beripad-de4";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* Secondary CPUs all start disabled and use the
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* spin-table enable method. cpu-release-addr must be
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* specified for each cpu other than cpu@0. Values of
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* cpu-release-addr grow down from 0x100000 (kernel).
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*/
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status = "disabled";
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enable-method = "spin-table";
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cpu@0 {
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device-type = "cpu";
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compatible = "sri-cambridge,beri";
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reg = <0>;
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status = "okay";
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};
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/*
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cpu@1 {
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device-type = "cpu";
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compatible = "sri-cambridge,beri";
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reg = <1>;
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// XXX: should we need cached prefix?
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cpu-release-addr = <0xffffffff 0x800fffe0>;
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};
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*/
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <1>;
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/*
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* Declare mips,mips4k since BERI doesn't (yet) have a PIC, so
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* we use mips4k coprocessor 0 interrupt management directly.
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*/
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compatible = "simple-bus", "mips,mips4k";
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ranges = <>;
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memory {
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device_type = "memory";
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reg = <0x0 0x40000000>; // 1G at 0x0
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};
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beripic: beripic@7f804000 {
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compatible = "sri-cambridge,beri-pic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x7f804000 0x400
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0x7f806000 0x10
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0x7f806080 0x10
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0x7f806100 0x10>;
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interrupts = <0 1 2 3 4>;
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hard-interrupt-sources = <64>;
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soft-interrupt-sources = <64>;
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};
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serial@7f002100 {
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compatible = "ns16550";
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reg = <0x7f002100 0x20>;
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reg-shift = <2>;
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clock-frequency = <50000000>;
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interrupts = <6>;
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interrupt-parent = <&beripic>;
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};
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serial@7f000000 {
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compatible = "altera,jtag_uart-11_0";
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reg = <0x7f000000 0x40>;
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interrupts = <0>;
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interrupt-parent = <&beripic>;
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};
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serial@7f001000 {
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compatible = "altera,jtag_uart-11_0";
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reg = <0x7f001000 0x40>;
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};
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serial@7f002000 {
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compatible = "altera,jtag_uart-11_0";
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reg = <0x7f002000 0x40>;
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};
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sdcard@7f008000 {
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compatible = "altera,sdcard_11_2011";
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reg = <0x7f008000 0x400>;
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};
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led@7f006000 {
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compatible = "sri-cambridge,de4led";
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reg = <0x7f006000 0x1>;
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};
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/*
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* XXX-BZ keep flash before ethernet so that atse can read the
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* Ethernet addresses for now.
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*/
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flash@74000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x74000000 0x4000000>;
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/* Board configuration */
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partition@0 {
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reg = <0x0 0x20000>;
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label = "config";
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};
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/* Power up FPGA image */
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partition@20000 {
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reg = <0x20000 0xc00000>;
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label = "fpga0";
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};
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/* Secondary FPGA image (on RE_CONFIGn button) */
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partition@C20000 {
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reg = <0xc20000 0xc00000>;
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label = "fpga1";
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};
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/* Space for operating system use */
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partition@1820000 {
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reg = <0x1820000 0x027c0000>;
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label = "os";
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};
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/* Second stage bootloader */
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parition@3fe0000 {
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reg = <0x3fe0000 0x20000>;
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label = "boot";
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};
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};
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ethernet@7f007000 {
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compatible = "altera,atse";
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// MAC, RX+RXC, TX+TXC.
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reg = <0x7f007000 0x400
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0x7f007500 0x8
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0x7f007520 0x20
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0x7f007400 0x8
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0x7f007420 0x20>;
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// RX, TX
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interrupts = <1 2>;
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interrupt-parent = <&beripic>;
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};
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ethernet@7f005000 {
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compatible = "altera,atse";
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// MAC, RX+RXC, TX+TXC.
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reg = <0x7f005000 0x400
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0x7f005500 0x8
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0x7f005520 0x20
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0x7f005400 0x8
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0x7f005420 0x20>;
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// RX, TX
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interrupts = <11 12>;
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interrupt-parent = <&beripic>;
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};
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touchscreen@70400000 {
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compatible = "sri-cambridge,mtl";
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reg = <0x70400000 0x1000
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0x70000000 0x177000
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0x70177000 0x2000>;
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};
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usb@0x7f100000 {
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compatible = "philips,isp1761";
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reg = <0x7f100000 0x40000
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0x7f140000 0x4>;
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// IRQ 4 is DC, IRQ 5 is HC.
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interrupts = <4 5>;
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interrupt-parent = <&beripic>;
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};
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avgen@0x7f009000 {
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compatible = "sri-cambridge,avgen";
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reg = <0x7f009000 0x2>;
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sri-cambridge,width = <1>;
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sri-cambridge,fileio = "r";
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sri-cambridge,devname = "de4bsw";
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};
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avgen@0x7f00a000 {
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compatible = "sri-cambridge,avgen";
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reg = <0x7f00a000 0x14>;
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sri-cambridge,width = <4>;
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sri-cambridge,fileio = "rw";
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sri-cambridge,devname = "berirom";
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};
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avgen@0x7f00c000 {
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compatible = "sri-cambridge,avgen";
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reg = <0x7f00c000 0x8>;
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sri-cambridge,width = <4>;
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sri-cambridge,fileio = "rw";
|
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sri-cambridge,devname = "de4tempfan";
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};
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avgen@0x7f100000 {
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compatible = "sri-cambridge,avgen";
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reg = <0x7f100000 0x40000>;
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sri-cambridge,width = <4>;
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sri-cambridge,fileio = "r";
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sri-cambridge,devname = "usbmem";
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};
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||||
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||||
};
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};
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@ -1,75 +1,26 @@
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# $FreeBSD$
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#
|
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# Altera JTAG UARTs configured for console, debugging, and data putput on the
|
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# Terasic DE-4.
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#
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hint.altera_jtag_uart.0.at="nexus0"
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hint.altera_jtag_uart.0.maddr=0x7f000000
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hint.altera_jtag_uart.0.msize=0x40
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hint.altera_jtag_uart.0.irq=0
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# Hardwired location of bitfile
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hint.map.0.at="cfid0s.fpga0"
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hint.map.0.start=0x00000000
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hint.map.0.end=0x00c00000
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hint.map.0.name="fpga"
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hint.altera_jtag_uart.1.at="nexus0"
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hint.altera_jtag_uart.1.maddr=0x7f001000
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hint.altera_jtag_uart.1.msize=0x40
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# Kernel on the second chip
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hint.map.1.at="cfid0s.os"
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hint.map.1.start=0x007e0000
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hint.map.1.end=0x01fe0000
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hint.map.1.name="kernel"
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hint.altera_jtag_uart.2.at="nexus0"
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hint.altera_jtag_uart.2.maddr=0x7f002000
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hint.altera_jtag_uart.2.msize=0x40
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# Altera Triple-Speed Ethernet Mac, present in tPad and DE-4 configurations
|
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# configured from fdt(4) but PHYs are still described in here.
|
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# Currently configured for individual tse_mac cores.
|
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hint.e1000phy.0.at="miibus0"
|
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hint.e1000phy.0.phyno=0
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hint.e1000phy.1.at="miibus0"
|
||||
hint.e1000phy.1.phyno=0
|
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hint.e1000phy.2.at="miibus0"
|
||||
hint.e1000phy.2.phyno=0
|
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hint.e1000phy.3.at="miibus0"
|
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hint.e1000phy.3.phyno=0
|
||||
|
||||
#
|
||||
# On-board DE4 and tPad SD Card IP core
|
||||
#
|
||||
hint.altera_sdcardc.0.at="nexus0"
|
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hint.altera_sdcardc.0.maddr=0x7f008000
|
||||
hint.altera_sdcardc.0.msize=0x400
|
||||
|
||||
#
|
||||
# On-board DE4 8-element LED
|
||||
#
|
||||
hint.terasic_de4led.0.at="nexus0"
|
||||
hint.terasic_de4led.0.maddr=0x7f006000
|
||||
hint.terasic_de4led.0.msize=1
|
||||
hint.terasic_de4led.0.de4led_0_cmd="f9"
|
||||
|
||||
#
|
||||
# Terasic Multi-touch LCD (MTL), an optional feature in DE-4 configurations.
|
||||
#
|
||||
hint.terasic_mtl.0.at="nexus0"
|
||||
hint.terasic_mtl.0.reg_maddr=0x70400000
|
||||
hint.terasic_mtl.0.reg_msize=0x1000
|
||||
hint.terasic_mtl.0.pixel_maddr=0x70000000
|
||||
hint.terasic_mtl.0.pixel_msize=0x177000
|
||||
hint.terasic_mtl.0.text_maddr=0x70177000
|
||||
hint.terasic_mtl.0.text_msize=0x2000
|
||||
|
||||
#
|
||||
# BERI Hardware Version ROM
|
||||
#
|
||||
hint.altera_avgen.0.at="nexus0"
|
||||
hint.altera_avgen.0.maddr=0x7F00A000
|
||||
hint.altera_avgen.0.msize=20
|
||||
hint.altera_avgen.0.width=4
|
||||
hint.altera_avgen.0.fileio="rw"
|
||||
hint.altera_avgen.0.devname="berirom"
|
||||
|
||||
#
|
||||
# Expose the DE4 flash via an Avalon "generic" device.
|
||||
#
|
||||
#hint.altera_avgen.0.at="nexus0"
|
||||
#hint.altera_avgen.0.maddr=0x74000000
|
||||
#hint.altera_avgen.0.msize=0x4000000
|
||||
#hint.altera_avgen.0.width=2
|
||||
#hint.altera_avgen.0.fileio="rw"
|
||||
#hint.altera_avgen.0.mmapio="rwx"
|
||||
#hint.altera_avgen.0.devname="de4flash"
|
||||
|
||||
#
|
||||
# Expose the DE4 buttons and switches via an Avalon "generic" device.
|
||||
#
|
||||
hint.altera_avgen.0.at="nexus0"
|
||||
hint.altera_avgen.0.maddr=0x7f009000
|
||||
hint.altera_avgen.0.msize=2
|
||||
hint.altera_avgen.0.width=1
|
||||
hint.altera_avgen.0.fileio="r"
|
||||
hint.altera_avgen.0.devname="de4bsw"
|
||||
|
||||
41
sys/mips/conf/BERI_DE4_BASE
Normal file
41
sys/mips/conf/BERI_DE4_BASE
Normal file
@ -0,0 +1,41 @@
|
||||
#
|
||||
# BERI_DE4_BASE -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible RISC
|
||||
# Implementation) FPGA soft core, as configured in its Terasic DE-4 reference
|
||||
# configuration. This kernel configration must be further specialized to
|
||||
# to include a root filesystem specification.
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
include "BERI_TEMPLATE"
|
||||
|
||||
ident BERI_DE4_BASE
|
||||
|
||||
options NFSCL # New Network Filesystem Client
|
||||
options NFSLOCKD # Network Lock Manager
|
||||
options NFS_ROOT # NFS usable as /, requires NFSCL
|
||||
|
||||
options FDT
|
||||
options FDT_DTB_STATIC
|
||||
makeoptions FDT_DTS_FILE=beripad-de4.dts
|
||||
|
||||
hints "BERI_DE4.hints" # Flash partitions still use hints.
|
||||
|
||||
device altera_atse
|
||||
device altera_avgen
|
||||
device altera_jtag_uart
|
||||
device altera_sdcard
|
||||
device terasic_de4led
|
||||
device terasic_mtl
|
||||
|
||||
device bpf
|
||||
device cfi
|
||||
device cfid
|
||||
options CFI_SUPPORT_STRATAFLASH
|
||||
device sc
|
||||
|
||||
device uart
|
||||
|
||||
device miibus
|
||||
options DEVICE_POLLING
|
||||
|
||||
@ -1,29 +1,19 @@
|
||||
#
|
||||
# BERI_DE4 -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible RISC
|
||||
# Implementation) FPGA soft core, as configured in its Terasic DE-4 reference
|
||||
# configuration.
|
||||
# BERI_DE4_MDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible
|
||||
# RISC # Implementation) FPGA soft core, as configured in its Terasic DE-4
|
||||
# reference configuration.
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
include "BERI_TEMPLATE"
|
||||
include "BERI_DE4_BASE"
|
||||
|
||||
ident BERI_DE4_MDROOT
|
||||
|
||||
hints "BERI_DE4.hints" #Default places to look for devices.
|
||||
|
||||
#
|
||||
# This kernel configuration uses an embedded 8MB memory root file system.
|
||||
# Adjust the following path based on local requirements.
|
||||
#
|
||||
options MD_ROOT # MD is a potential root device
|
||||
options MD_ROOT_SIZE=8192
|
||||
options MD_ROOT_SIZE=26112 # 25.5MB
|
||||
options ROOTDEVNAME=\"ufs:md0\"
|
||||
|
||||
device altera_avgen
|
||||
device altera_jtag_uart
|
||||
device altera_sdcard
|
||||
device terasic_de4led
|
||||
device terasic_mtl
|
||||
|
||||
device sc
|
||||
|
||||
@ -1,23 +1,16 @@
|
||||
#
|
||||
# BERI_DE4 -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible RISC
|
||||
# Implementation) FPGA soft core, as configured in its Terasic DE-4 reference
|
||||
# configuration.
|
||||
# BERI_DE4_SDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible
|
||||
# RISC Implementation) FPGA soft core, as configured in its Terasic DE-4
|
||||
# reference configuration.
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
include "BERI_TEMPLATE"
|
||||
include "BERI_DE4_BASE"
|
||||
|
||||
ident BERI_DE4_SDROOT
|
||||
|
||||
hints "BERI_DE4.hints" #Default places to look for devices.
|
||||
|
||||
options ROOTDEVNAME=\"ufs:altera_sdcard0\"
|
||||
|
||||
device altera_avgen
|
||||
device altera_jtag_uart
|
||||
device altera_sdcard
|
||||
device terasic_de4led
|
||||
device terasic_mtl
|
||||
|
||||
device sc
|
||||
#
|
||||
# This kernel expects to find its root filesystem on the SD Card.
|
||||
#
|
||||
options ROOTDEVNAME=\"ufs:/dev/altera_sdcard0\"
|
||||
|
||||
19
sys/mips/conf/BERI_SIM_BASE
Normal file
19
sys/mips/conf/BERI_SIM_BASE
Normal file
@ -0,0 +1,19 @@
|
||||
#
|
||||
# BERI_SIM_BASE -- Base kernel for the SRI/Cambridge "BERI" (Bluespec
|
||||
# Extensible RISC Implementation) FPGA soft core, as configured for
|
||||
# simulation.
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
include "BERI_TEMPLATE"
|
||||
|
||||
options FDT
|
||||
options FDT_DTB_STATIC
|
||||
makeoptions FDT_DTS_FILE=beri-sim.dts
|
||||
|
||||
options ALTERA_SDCARD_FAST_SIM
|
||||
|
||||
device altera_avgen
|
||||
device altera_jtag_uart
|
||||
device altera_sdcard
|
||||
@ -1,24 +1,18 @@
|
||||
#
|
||||
# BERI_SIM -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible RISC
|
||||
# Implementation) FPGA soft core, as configured for simulation.
|
||||
# BERI_SIM_MDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible
|
||||
# RISC Implementation) FPGA soft core, as configured for simulation.
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
include "BERI_TEMPLATE"
|
||||
include "BERI_SIM_BASE"
|
||||
|
||||
ident BERI_SIM_MDROOT
|
||||
|
||||
hints "BERI_SIM.hints" #Default places to look for devices.
|
||||
|
||||
#
|
||||
# This kernel configuration uses an embedded 8MB memory root file system.
|
||||
# This kernel configuration uses an embedded memory root file system.
|
||||
# Adjust the following path based on local requirements.
|
||||
#
|
||||
options MD_ROOT # MD is a potential root device
|
||||
options MD_ROOT_SIZE=8192
|
||||
options MD_ROOT_SIZE=26112 # 25.5MB
|
||||
options ROOTDEVNAME=\"ufs:md0\"
|
||||
|
||||
device altera_avgen
|
||||
device altera_jtag_uart
|
||||
device altera_sdcard
|
||||
|
||||
15
sys/mips/conf/BERI_SIM_SDROOT
Normal file
15
sys/mips/conf/BERI_SIM_SDROOT
Normal file
@ -0,0 +1,15 @@
|
||||
#
|
||||
# BERI_SIM_SDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible
|
||||
# RISC Implementation) FPGA soft core, as configured for simulation.
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
include "BERI_SIM_BASE"
|
||||
|
||||
ident BERI_SIM_SDROOT
|
||||
|
||||
#
|
||||
# This kernel expects to find its root filesystem on the SD Card.
|
||||
#
|
||||
options ROOTDEVNAME=\"ufs:/dev/altera_sdcard0\"
|
||||
@ -39,7 +39,9 @@ options FFS #Berkeley Fast Filesystem
|
||||
|
||||
options INET
|
||||
options INET6
|
||||
options KGSSAPI
|
||||
options NFSCL
|
||||
options NFSLOCKD
|
||||
options NFS_ROOT
|
||||
|
||||
# Debugging for use in -current
|
||||
@ -49,10 +51,11 @@ options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required
|
||||
#options WITNESS #Enable checks to detect deadlocks and cycles
|
||||
#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
|
||||
|
||||
device geom_map
|
||||
|
||||
device md
|
||||
device crypto
|
||||
device cryptodev
|
||||
device ether
|
||||
device geom_map
|
||||
device loop
|
||||
device md
|
||||
device random
|
||||
device snp
|
||||
|
||||
Loading…
Reference in New Issue
Block a user