Add imx6 compatibility and make the driver work for any clock frequency.
There are still a couple references to imx51 ccm driver functions that will need to be changed after an imx6 ccm driver is written. Reviewed by: ray
This commit is contained in:
Ian Lepore
parent
a1df5ac10a
commit
e0511b6c67
@ -57,8 +57,6 @@ __FBSDID("$FreeBSD$");
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#include <sys/kdb.h>
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#include <arm/freescale/imx/imx51_ccmvar.h>
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#define MIN_PERIOD 100LLU
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#define WRITE4(_sc, _r, _v) \
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bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v))
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#define READ4(_sc, _r) \
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@ -82,11 +80,27 @@ static struct timecounter imx_gpt_timecounter = {
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.tc_get_timecount = imx_gpt_get_timecount,
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.tc_counter_mask = ~0u,
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.tc_frequency = 0,
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.tc_quality = 500,
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.tc_quality = 1000,
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};
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/* Global softc pointer for use in DELAY(). */
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struct imx_gpt_softc *imx_gpt_sc = NULL;
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static volatile int imx_gpt_delay_count = 300;
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/*
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* Hand-calibrated delay-loop counter. This was calibrated on an i.MX6 running
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* at 792mhz. It will delay a bit too long on slower processors -- that's
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* better than not delaying long enough. In practice this is unlikely to get
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* used much since the clock driver is one of the first to start up, and once
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* we're attached the delay loop switches to using the timer hardware.
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*/
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static const int imx_gpt_delay_count = 78;
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/* Try to divide down an available fast clock to this frequency. */
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#define TARGET_FREQUENCY 1000000
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/* Don't try to set an event timer period smaller than this. */
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#define MIN_ET_PERIOD 10LLU
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static struct resource_spec imx_gpt_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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@ -101,7 +115,7 @@ imx_gpt_probe(device_t dev)
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if (!ofw_bus_is_compatible(dev, "fsl,imx51-gpt"))
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return (ENXIO);
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device_set_desc(dev, "Freescale i.MXxxx GPT timer");
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device_set_desc(dev, "Freescale i.MX GPT timer");
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return (BUS_PROBE_DEFAULT);
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}
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@ -109,7 +123,8 @@ static int
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imx_gpt_attach(device_t dev)
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{
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struct imx_gpt_softc *sc;
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int err;
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int ctlreg, err;
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uint32_t basefreq, prescale;
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sc = device_get_softc(dev);
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@ -119,49 +134,96 @@ imx_gpt_attach(device_t dev)
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}
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sc->sc_dev = dev;
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sc->sc_clksrc = GPT_CR_CLKSRC_IPG;
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sc->sc_iot = rman_get_bustag(sc->res[0]);
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sc->sc_ioh = rman_get_bushandle(sc->res[0]);
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/*
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* For now, just automatically choose a good clock for the hardware
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* we're running on. Eventually we could allow selection from the fdt;
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* the code in this driver will cope with any clock frequency.
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*/
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if (ofw_bus_is_compatible(dev, "fsl,imx6-gpt"))
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sc->sc_clksrc = GPT_CR_CLKSRC_24M;
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else
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sc->sc_clksrc = GPT_CR_CLKSRC_IPG;
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ctlreg = 0;
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switch (sc->sc_clksrc) {
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case GPT_CR_CLKSRC_NONE:
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device_printf(dev, "can't run timer without clock source\n");
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return (EINVAL);
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case GPT_CR_CLKSRC_EXT:
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device_printf(dev, "Not implemented. Geve me the way to get "
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"external clock source frequency\n");
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return (EINVAL);
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case GPT_CR_CLKSRC_32K:
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sc->clkfreq = 32768;
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basefreq = 32768;
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break;
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case GPT_CR_CLKSRC_IPG:
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basefreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
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break;
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case GPT_CR_CLKSRC_IPG_HIGH:
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sc->clkfreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT) * 2;
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basefreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT) * 2;
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break;
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case GPT_CR_CLKSRC_24M:
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ctlreg |= GPT_CR_24MEN;
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basefreq = 24000000;
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break;
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case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */
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case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */
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default:
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sc->clkfreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
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device_printf(dev, "Unsupported clock source '%d'\n",
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sc->sc_clksrc);
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return (EINVAL);
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}
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device_printf(dev, "Run on %dKHz clock.\n", sc->clkfreq / 1000);
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/* Reset */
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WRITE4(sc, IMX_GPT_CR, GPT_CR_SWR);
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/* Enable and setup counters */
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WRITE4(sc, IMX_GPT_CR,
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GPT_CR_CLKSRC_IPG | /* Use IPG clock */
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GPT_CR_FRR | /* Just count (FreeRunner mode) */
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GPT_CR_STOPEN | /* Run in STOP mode */
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GPT_CR_WAITEN | /* Run in WAIT mode */
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GPT_CR_DBGEN); /* Run in DEBUG mode */
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/* Disable interrupts */
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/*
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* The following setup sequence is from the I.MX6 reference manual,
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* "Selecting the clock source". First, disable the clock and
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* interrupts. This also clears input and output mode bits and in
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* general completes several of the early steps in the procedure.
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*/
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WRITE4(sc, IMX_GPT_CR, 0);
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WRITE4(sc, IMX_GPT_IR, 0);
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/* Tick every 10us */
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/* XXX: must be calculated from clock source frequency */
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WRITE4(sc, IMX_GPT_PR, 665);
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/* Use 100 KHz */
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sc->clkfreq = 100000;
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/* Choose the clock and the power-saving behaviors. */
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ctlreg |=
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sc->sc_clksrc | /* Use selected clock */
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GPT_CR_FRR | /* Just count (FreeRunner mode) */
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GPT_CR_STOPEN | /* Run in STOP mode */
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GPT_CR_DOZEEN | /* Run in DOZE mode */
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GPT_CR_WAITEN | /* Run in WAIT mode */
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GPT_CR_DBGEN; /* Run in DEBUG mode */
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WRITE4(sc, IMX_GPT_CR, ctlreg);
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/* Setup and enable the timer interrupt */
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/*
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* The datasheet says to do the software reset after choosing the clock
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* source. It says nothing about needing to wait for the reset to
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* complete, but the register description does document the fact that
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* the reset isn't complete until the SWR bit reads 0, so let's be safe.
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* The reset also clears all registers except for a few of the bits in
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* CR, but we'll rewrite all the CR bits when we start the counter.
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*/
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WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR);
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while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR)
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continue;
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/* Set a prescaler value that gets us near the target frequency. */
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if (basefreq < TARGET_FREQUENCY) {
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prescale = 0;
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sc->clkfreq = basefreq;
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} else {
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prescale = basefreq / TARGET_FREQUENCY;
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sc->clkfreq = basefreq / prescale;
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prescale -= 1; /* 1..n range is 0..n-1 in hardware. */
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}
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WRITE4(sc, IMX_GPT_PR, prescale);
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/* Clear the status register. */
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WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL);
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/* Start the counter. */
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WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN);
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if (bootverbose)
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device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n",
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sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR));
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/* Setup the timer interrupt. */
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err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr,
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NULL, sc, &sc->sc_ih);
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if (err != 0) {
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@ -171,35 +233,25 @@ imx_gpt_attach(device_t dev)
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return (ENXIO);
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}
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/* Register as an eventtimer. */
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sc->et.et_name = "i.MXxxx GPT Eventtimer";
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sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
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sc->et.et_quality = 1000;
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sc->et.et_frequency = sc->clkfreq;
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sc->et.et_min_period = (MIN_PERIOD << 32) / sc->et.et_frequency;
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sc->et.et_min_period = (MIN_ET_PERIOD << 32) / sc->et.et_frequency;
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sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
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sc->et.et_start = imx_gpt_timer_start;
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sc->et.et_stop = imx_gpt_timer_stop;
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sc->et.et_priv = sc;
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et_register(&sc->et);
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/* Disable interrupts */
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WRITE4(sc, IMX_GPT_IR, 0);
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/* ACK any panding interrupts */
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WRITE4(sc, IMX_GPT_SR, (GPT_IR_ROV << 1) - 1);
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if (device_get_unit(dev) == 0)
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imx_gpt_sc = sc;
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/* Register as a timecounter. */
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imx_gpt_timecounter.tc_frequency = sc->clkfreq;
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tc_init(&imx_gpt_timecounter);
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printf("clock: hz=%d stathz = %d\n", hz, stathz);
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device_printf(sc->sc_dev, "timer clock frequency %d\n", sc->clkfreq);
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imx_gpt_delay_count = imx51_get_clock(IMX51CLK_ARM_ROOT) / 4000000;
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SET4(sc, IMX_GPT_CR, GPT_CR_EN);
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/* If this is the first unit, store the softc for use in DELAY. */
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if (device_get_unit(dev) == 0)
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imx_gpt_sc = sc;
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return (0);
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}
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@ -267,16 +319,11 @@ void
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cpu_initclocks(void)
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{
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if (!imx_gpt_sc) {
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panic("%s: driver has not been initialized!", __func__);
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if (imx_gpt_sc == NULL) {
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panic("%s: i.MX GPT driver has not been initialized!", __func__);
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}
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cpu_initclocks_bsp();
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/* Switch to DELAY using counter */
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imx_gpt_delay_count = 0;
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device_printf(imx_gpt_sc->sc_dev,
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"switch DELAY to use H/W counter\n");
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}
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static int
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@ -342,29 +389,30 @@ EARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, imx_gpt_devclass, 0,
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void
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DELAY(int usec)
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{
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int32_t counts;
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uint32_t last;
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uint64_t curcnt, endcnt, startcnt, ticks;
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/*
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* Check the timers are setup, if not just use a for loop for the
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* meantime.
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*/
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if (imx_gpt_delay_count) {
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for (; usec > 0; usec--)
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for (counts = imx_gpt_delay_count; counts > 0;
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counts--)
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/* Prevent optimizing out the loop */
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/* If the timer hardware is not accessible, just use a loop. */
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if (imx_gpt_sc == NULL) {
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while (usec-- > 0)
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for (ticks = 0; ticks < imx_gpt_delay_count; ++ticks)
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cpufunc_nullop();
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return;
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}
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/* At least 1 count */
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usec = MAX(1, usec / 100);
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last = READ4(imx_gpt_sc, IMX_GPT_CNT) + usec;
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while (READ4(imx_gpt_sc, IMX_GPT_CNT) < last) {
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/* Prevent optimizing out the loop */
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cpufunc_nullop();
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/*
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* Calculate the tick count with 64-bit values so that it works for any
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* clock frequency. Loop until the hardware count reaches start+ticks.
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* If the 32-bit hardware count rolls over while we're looping, just
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* manually do a carry into the high bits after each read; don't worry
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* that doing this on each loop iteration is inefficient -- we're trying
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* to waste time here.
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*/
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ticks = 1 + ((uint64_t)usec * imx_gpt_sc->clkfreq) / 1000000;
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curcnt = startcnt = READ4(imx_gpt_sc, IMX_GPT_CNT);
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endcnt = startcnt + ticks;
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while (curcnt < endcnt) {
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curcnt = READ4(imx_gpt_sc, IMX_GPT_CNT);
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if (curcnt < startcnt)
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curcnt += 1ULL << 32;
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}
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/* TODO: use interrupt on OCR2 */
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}
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@ -55,13 +55,16 @@
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#define GPT_CR_IMX_FEDGE 2
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#define GPT_CR_IMX_BOTH 3
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#define GPT_CR_SWR (1 << 15)
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#define GPT_CR_24MEN (1 << 10)
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#define GPT_CR_FRR (1 << 9)
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#define GPT_CR_CLKSRC_NONE 0x00000000
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#define GPT_CR_CLKSRC_IPG 0x00000040
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#define GPT_CR_CLKSRC_IPG_HIGH 0x00000080
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#define GPT_CR_CLKSRC_EXT 0x000000c0
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#define GPT_CR_CLKSRC_32K 0x00000100
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#define GPT_CR_CLKSRC_NONE (0 << 6)
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#define GPT_CR_CLKSRC_IPG (1 << 6)
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#define GPT_CR_CLKSRC_IPG_HIGH (2 << 6)
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#define GPT_CR_CLKSRC_EXT (3 << 6)
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#define GPT_CR_CLKSRC_32K (4 << 6)
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#define GPT_CR_CLKSRC_24M (5 << 6)
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#define GPT_CR_STOPEN (1 << 5)
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#define GPT_CR_DOZEEN (1 << 4)
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#define GPT_CR_WAITEN (1 << 3)
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#define GPT_CR_DBGEN (1 << 2)
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#define GPT_CR_ENMOD (1 << 1)
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@ -70,6 +73,8 @@
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#define IMX_GPT_PR 0x0004 /* Prescaler Register R/W */
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#define GPT_PR_VALUE_SHIFT 0
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#define GPT_PR_VALUE_MASK 0x00000fff
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#define GPT_PR_VALUE_SHIFT_24M 12
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#define GPT_PR_VALUE_MASK_24M 0x0000f000
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/* Same map for SR and IR */
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#define IMX_GPT_SR 0x0008 /* Status Register R/W */
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