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Add support for assembling and disassembling Intel Random Number

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Generator extensions (e.g. the 'rdrand' mnemonic) to our copy of
binutils.

Approved by:	re (kib)
Obtained from:	OpenBSD, via pfg
MFC after:	1 week
This commit is contained in:
Dimitry Andric 2013-10-07 16:33:16 +00:00
parent 8a675a6396
commit e1a5a8a74a
4 changed files with 40 additions and 8 deletions
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22
contrib/binutils/opcodes/i386-dis.c
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@ -6438,14 +6438,22 @@ VMX_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
static void static void
OP_VMX (int bytemode, int sizeflag) OP_VMX (int bytemode, int sizeflag)
{ {
used_prefixes |= (prefixes & (PREFIX_DATA | PREFIX_REPZ)); if (modrm.mod == 3)
if (prefixes & PREFIX_DATA) {
strcpy (obuf, "vmclear"); strcpy (obuf, "rdrand");
else if (prefixes & PREFIX_REPZ) OP_E (v_mode, sizeflag);
strcpy (obuf, "vmxon"); }
else else
strcpy (obuf, "vmptrld"); {
OP_E (bytemode, sizeflag); used_prefixes |= (prefixes & (PREFIX_DATA | PREFIX_REPZ));
if (prefixes & PREFIX_DATA)
strcpy (obuf, "vmclear");
else if (prefixes & PREFIX_REPZ)
strcpy (obuf, "vmxon");
else
strcpy (obuf, "vmptrld");
OP_E (bytemode, sizeflag);
}
} }
static void static void

3
contrib/binutils/opcodes/i386-opc.h
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@ -79,6 +79,7 @@ typedef struct template
#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */ #define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
#define CpuPCLMUL 0x10000000 /* Carry-less Multiplication extensions */ #define CpuPCLMUL 0x10000000 /* Carry-less Multiplication extensions */
#define CpuRdRnd 0x20000000 /* Intel Random Number Generator extensions */
/* SSE4.1/4.2 Instructions required */ /* SSE4.1/4.2 Instructions required */
#define CpuSSE4 (CpuSSE4_1|CpuSSE4_2) #define CpuSSE4 (CpuSSE4_1|CpuSSE4_2)
@ -87,7 +88,7 @@ typedef struct template
#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \ #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \ |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \ |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \
|CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL) |CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL|CpuRdRnd)
/* the bits in opcode_modifier are used to generate the final opcode from /* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of the base_opcode. These bits also are used to detect alternate forms of

18
contrib/binutils/opcodes/i386-opc.tbl
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@ -1502,3 +1502,21 @@ xrstor, 1, 0xfae, 0x5, CpuXSAVE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
// INVPCID // INVPCID
invpcid, 2, 0x660f3882, None, CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 } invpcid, 2, 0x660f3882, None, CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
invpcid, 2, 0x660f3882, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 } invpcid, 2, 0x660f3882, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
// Intel AES extensions
aesdec, 2, 0x660f38de, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
aesdeclast, 2, 0x660f38df, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
aesenc, 2, 0x660f38dc, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
aesenclast, 2, 0x660f38dd, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
aesimc, 2, 0x660f38db, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
aeskeygenassist, 3, 0x660f3adf, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM|LLongMem, RegXMM }
// Intel Carry-less Multiplication extensions
pclmulqdq, 3, 0x660f3a44, None, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM|LLongMem, RegXMM }
pclmullqlqdq, 2, 0x660f3a44, 0x0, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM }
pclmulhqlqdq, 2, 0x660f3a44, 0x1, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM }
pclmullqhqdq, 2, 0x660f3a44, 0x10, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM }
pclmulhqhqdq, 2, 0x660f3a44, 0x11, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM }
// Intel Random Number Generator extensions
rdrand, 1, 0x0fc7, 0x6, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 }

5
contrib/binutils/opcodes/i386-tbl.h
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@ -4374,6 +4374,11 @@ const template i386_optab[] =
Modrm|IgnoreSize|NoSuf|ImmExt, Modrm|IgnoreSize|NoSuf|ImmExt,
{ RegXMM|LLongMem, { RegXMM|LLongMem,
RegXMM } }, RegXMM } },
/* Intel Random Number Generator extensions */
{"rdrand", 1, 0x0fc7, 0x6, CpuRdRnd,
Modrm|NoSuf,
{ Reg16|Reg32|Reg64 } },
{ NULL, 0, 0, 0, 0, 0, { 0 } } { NULL, 0, 0, 0, 0, 0, { 0 } }
}; };