Add support for the Linksys WMP-11, Prism 2.5, PCI adaptor.
Submitted by: Thomas Skibo <skibo@pacbell.net> MFC after: 2 weeks
This commit is contained in:
Brooks Davis
parent
02ccbdf67a
commit
e2119ba50b
@ -223,12 +223,14 @@ static driver_t wi_pci_driver = {
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static struct {
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unsigned int vendor,device;
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int bus_type;
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char *desc;
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} pci_ids[] = {
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{0x1638, 0x1100, "PRISM2STA PCI WaveLAN/IEEE 802.11"},
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{0x1385, 0x4100, "Netgear MA301 PCI IEEE 802.11b"},
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{0x16ab, 0x1101, "GLPRISM2 PCI WaveLAN/IEEE 802.11"},
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{0x16ab, 0x1102, "Linksys WDT11 PCI IEEE 802.11b"},
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{0x1638, 0x1100, WI_BUS_PCI_PLX, "PRISM2STA PCI WaveLAN/IEEE 802.11"},
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{0x1385, 0x4100, WI_BUS_PCI_PLX, "Netgear MA301 PCI IEEE 802.11b"},
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{0x16ab, 0x1101, WI_BUS_PCI_PLX, "GLPRISM2 PCI WaveLAN/IEEE 802.11"},
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{0x16ab, 0x1102, WI_BUS_PCI_PLX, "Linksys WDT11 PCI IEEE 802.11b"},
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{0x1260, 0x3873, WI_BUS_PCI_NATIVE, "Linksys WMP11 PCI Prism2.5"},
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{0, 0, NULL}
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};
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#endif
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@ -291,6 +293,7 @@ wi_pccard_probe(dev)
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sc = device_get_softc(dev);
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sc->wi_gone = 0;
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sc->wi_bus_type = WI_BUS_PCCARD;
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error = wi_alloc(dev, 0);
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if (error)
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@ -318,6 +321,7 @@ wi_pci_probe(dev)
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if ((pci_get_vendor(dev) == pci_ids[i].vendor) &&
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(pci_get_device(dev) == pci_ids[i].device)) {
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sc->wi_prism2 = 1;
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sc->wi_bus_type = pci_ids[i].bus_type;
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device_set_desc(dev, pci_ids[i].desc);
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return (0);
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}
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@ -383,6 +387,7 @@ wi_pci_attach(device_t dev)
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u_int32_t command, wanted;
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u_int16_t reg;
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int error;
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int timeout;
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sc = device_get_softc(dev);
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@ -396,47 +401,77 @@ wi_pci_attach(device_t dev)
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return (ENXIO);
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}
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error = wi_alloc(dev, WI_PCI_IORES);
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if (error)
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return (error);
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if (sc->wi_bus_type != WI_BUS_PCI_NATIVE) {
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error = wi_alloc(dev, WI_PCI_IORES);
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if (error)
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return (error);
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/* Make sure interrupts are disabled. */
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CSR_WRITE_2(sc, WI_INT_EN, 0);
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CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
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/* Make sure interrupts are disabled. */
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CSR_WRITE_2(sc, WI_INT_EN, 0);
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CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
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/* We have to do a magic PLX poke to enable interrupts */
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sc->local_rid = WI_PCI_LOCALRES;
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sc->local = bus_alloc_resource(dev, SYS_RES_IOPORT,
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&sc->local_rid, 0, ~0, 1, RF_ACTIVE);
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sc->wi_localtag = rman_get_bustag(sc->local);
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sc->wi_localhandle = rman_get_bushandle(sc->local);
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command = bus_space_read_4(sc->wi_localtag, sc->wi_localhandle,
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WI_LOCAL_INTCSR);
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command |= WI_LOCAL_INTEN;
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bus_space_write_4(sc->wi_localtag, sc->wi_localhandle,
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WI_LOCAL_INTCSR, command);
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bus_release_resource(dev, SYS_RES_IOPORT, sc->local_rid, sc->local);
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sc->local = NULL;
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/* We have to do a magic PLX poke to enable interrupts */
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sc->local_rid = WI_PCI_LOCALRES;
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sc->local = bus_alloc_resource(dev, SYS_RES_IOPORT,
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&sc->local_rid, 0, ~0, 1, RF_ACTIVE);
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sc->wi_localtag = rman_get_bustag(sc->local);
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sc->wi_localhandle = rman_get_bushandle(sc->local);
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command = bus_space_read_4(sc->wi_localtag, sc->wi_localhandle,
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WI_LOCAL_INTCSR);
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command |= WI_LOCAL_INTEN;
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bus_space_write_4(sc->wi_localtag, sc->wi_localhandle,
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WI_LOCAL_INTCSR, command);
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bus_release_resource(dev, SYS_RES_IOPORT, sc->local_rid,
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sc->local);
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sc->local = NULL;
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sc->mem_rid = WI_PCI_MEMRES;
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sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->mem_rid,
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0, ~0, 1, RF_ACTIVE);
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if (sc->mem == NULL) {
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device_printf(dev, "couldn't allocate memory\n");
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wi_free(dev);
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return (ENXIO);
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sc->mem_rid = WI_PCI_MEMRES;
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sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->mem_rid,
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0, ~0, 1, RF_ACTIVE);
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if (sc->mem == NULL) {
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device_printf(dev, "couldn't allocate memory\n");
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wi_free(dev);
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return (ENXIO);
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}
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sc->wi_bmemtag = rman_get_bustag(sc->mem);
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sc->wi_bmemhandle = rman_get_bushandle(sc->mem);
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/*
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* From Linux driver:
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* Write COR to enable PC card
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* This is a subset of the protocol that the pccard bus code
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* would do.
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*/
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CSM_WRITE_1(sc, WI_COR_OFFSET, WI_COR_VALUE);
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reg = CSM_READ_1(sc, WI_COR_OFFSET);
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if (reg != WI_COR_VALUE) {
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device_printf(dev, "CSM_READ_1(WI_COR_OFFSET) "
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"wanted %d, got %d\n", WI_COR_VALUE, reg);
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wi_free(dev);
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return (ENXIO);
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}
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} else {
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error = wi_alloc(dev, WI_PCI_LMEMRES);
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if (error)
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return (error);
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CSR_WRITE_2(sc, WI_HFA384X_PCICOR_OFF, 0x0080);
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DELAY(250000);
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CSR_WRITE_2(sc, WI_HFA384X_PCICOR_OFF, 0x0000);
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DELAY(500000);
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timeout=2000000;
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while ((--timeout > 0) &&
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(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY))
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DELAY(10);
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if (timeout == 0) {
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device_printf(dev, "couldn't reset prism2.5 core.\n");
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wi_free(dev);
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return(ENXIO);
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}
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}
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sc->wi_bmemtag = rman_get_bustag(sc->mem);
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sc->wi_bmemhandle = rman_get_bushandle(sc->mem);
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/*
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* From Linux driver:
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* Write COR to enable PC card
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* This is a subset of the protocol that the pccard bus code
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* would do.
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*/
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CSM_WRITE_1(sc, WI_COR_OFFSET, WI_COR_VALUE);
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reg = CSM_READ_1(sc, WI_COR_OFFSET);
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CSR_WRITE_2(sc, WI_HFA384X_SWSUPPORT0_OFF, WI_PRISM2STA_MAGIC);
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reg = CSR_READ_2(sc, WI_HFA384X_SWSUPPORT0_OFF);
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@ -955,6 +990,7 @@ wi_cmd(sc, cmd, val)
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DELAY(10*1000); /* 10 m sec */
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}
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if (i == 0) {
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device_printf(sc->dev, "wi_cmd: busy bit won't clear.\n" );
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return(ETIMEDOUT);
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}
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@ -968,8 +1004,8 @@ wi_cmd(sc, cmd, val)
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* Wait for 'command complete' bit to be
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* set in the event status register.
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*/
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s = CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_CMD;
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if (s) {
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s = CSR_READ_2(sc, WI_EVENT_STAT);
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if (s & WI_EV_CMD) {
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/* Ack the event and read result code. */
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s = CSR_READ_2(sc, WI_STATUS);
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CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_CMD);
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@ -981,12 +1017,14 @@ wi_cmd(sc, cmd, val)
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return(EIO);
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break;
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}
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if (cmd == WI_CMD_INI)
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DELAY(100);
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DELAY(WI_DELAY);
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}
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if (i == WI_TIMEOUT)
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if (i == WI_TIMEOUT) {
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device_printf(sc->dev,
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"timeout in wi_cmd %x; event status %x\n", cmd, s);
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return(ETIMEDOUT);
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}
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return(0);
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}
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@ -1001,7 +1039,7 @@ wi_reset(sc)
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for (i = 0; i < WI_INIT_TRIES; i++) {
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if (wi_cmd(sc, WI_CMD_INI, 0) == 0)
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break;
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DELAY(50 * 1000); /* 50ms */
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DELAY(WI_DELAY * 1000);
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}
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if (i == WI_INIT_TRIES)
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device_printf(sc->dev, "init failed\n");
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@ -1216,6 +1254,7 @@ wi_seek(sc, id, off, chan)
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status = CSR_READ_2(sc, offreg);
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if (!(status & (WI_OFF_BUSY|WI_OFF_ERR)))
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break;
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DELAY(WI_DELAY);
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}
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if (i == WI_TIMEOUT) {
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@ -1322,6 +1361,7 @@ wi_alloc_nicmem(sc, len, id)
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for (i = 0; i < WI_TIMEOUT; i++) {
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if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_ALLOC)
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break;
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DELAY(WI_DELAY);
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}
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if (i == WI_TIMEOUT) {
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@ -2077,24 +2117,45 @@ wi_watchdog(ifp)
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}
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static int
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wi_alloc(dev, io_rid)
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wi_alloc(dev, rid)
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device_t dev;
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int io_rid;
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int rid;
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{
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struct wi_softc *sc = device_get_softc(dev);
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sc->iobase_rid = io_rid;
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sc->iobase = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->iobase_rid,
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0, ~0, (1 << 6),
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rman_make_alignment_flags(1 << 6) | RF_ACTIVE);
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if (!sc->iobase) {
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device_printf(dev, "No I/O space?!\n");
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return (ENXIO);
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if (sc->wi_bus_type != WI_BUS_PCI_NATIVE) {
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sc->iobase_rid = rid;
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sc->iobase = bus_alloc_resource(dev, SYS_RES_IOPORT,
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&sc->iobase_rid, 0, ~0, (1 << 6),
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rman_make_alignment_flags(1 << 6) | RF_ACTIVE);
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if (!sc->iobase) {
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device_printf(dev, "No I/O space?!\n");
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return (ENXIO);
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}
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sc->wi_io_addr = rman_get_start(sc->iobase);
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sc->wi_btag = rman_get_bustag(sc->iobase);
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sc->wi_bhandle = rman_get_bushandle(sc->iobase);
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} else {
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sc->mem_rid = rid;
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sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY,
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&sc->mem_rid, 0, ~0, 1, RF_ACTIVE);
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if (!sc->mem) {
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device_printf(dev, "No Mem space on prism2.5?\n");
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return (ENXIO);
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}
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sc->wi_btag = rman_get_bustag(sc->mem);
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sc->wi_bhandle = rman_get_bushandle(sc->mem);
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}
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sc->irq_rid = 0;
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sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid,
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0, ~0, 1, RF_ACTIVE);
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0, ~0, 1, RF_ACTIVE |
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((sc->wi_bus_type == WI_BUS_PCCARD) ? 0 : RF_SHAREABLE));
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if (!sc->irq) {
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wi_free(dev);
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device_printf(dev, "No irq?!\n");
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@ -2103,9 +2164,6 @@ wi_alloc(dev, io_rid)
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sc->dev = dev;
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sc->wi_unit = device_get_unit(dev);
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sc->wi_io_addr = rman_get_start(sc->iobase);
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sc->wi_btag = rman_get_bustag(sc->iobase);
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sc->wi_bhandle = rman_get_bushandle(sc->iobase);
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return (0);
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}
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@ -137,12 +137,14 @@ struct wi_softc {
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struct mtx wi_mtx;
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int wi_prism2;
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int wi_prism2_ver;
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int wi_bus_type; /* Bus attachment type */
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};
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#define WI_LOCK(_sc)
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#define WI_UNLOCK(_sc)
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#define WI_TIMEOUT 65536
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#define WI_DELAY 5
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#define WI_TIMEOUT (500000/WI_DELAY) /* 500 ms */
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#define WI_PORT0 0
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#define WI_PORT1 1
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@ -151,6 +153,7 @@ struct wi_softc {
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#define WI_PORT4 4
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#define WI_PORT5 5
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#define WI_PCI_LMEMRES 0x10 /* PCI Memory (native PCI implementations) */
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#define WI_PCI_LOCALRES 0x14 /* The PLX chip's local registers */
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#define WI_PCI_MEMRES 0x18 /* The PCCard's attribute memory */
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#define WI_PCI_IORES 0x1C /* The PCCard's I/O space */
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@ -159,6 +162,7 @@ struct wi_softc {
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#define WI_LOCAL_INTEN 0x40
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#define WI_HFA384X_SWSUPPORT0_OFF 0x28
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#define WI_PRISM2STA_MAGIC 0x4A2D
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#define WI_HFA384X_PCICOR_OFF 0x26
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/* Default port: 0 (only 0 exists on stations) */
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#define WI_DEFAULT_PORT (WI_PORT0 << 8)
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@ -187,29 +191,38 @@ struct wi_softc {
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#define WI_DEFAULT_CHAN 3
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#define WI_BUS_PCCARD 0 /* pccard device */
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#define WI_BUS_PCI_PLX 1 /* PCI card w/ PLX PCI/PCMICA bridge */
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#define WI_BUS_PCI_NATIVE 2 /* native PCI device (Prism 2.5) */
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/*
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* register space access macros
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*/
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4(sc->wi_btag, sc->wi_bhandle, reg, val)
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2(sc->wi_btag, sc->wi_bhandle, reg, val)
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#define CSR_WRITE_1(sc, reg, val) \
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bus_space_write_1(sc->wi_btag, sc->wi_bhandle, reg, val)
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4((sc)->wi_btag, (sc)->wi_bhandle, \
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(sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg), val)
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2((sc)->wi_btag, (sc)->wi_bhandle, \
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(sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg), val)
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#define CSR_WRITE_1(sc, reg, val) \
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bus_space_write_1((sc)->wi_btag, (sc)->wi_bhandle, \
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(sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg), val)
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4(sc->wi_btag, sc->wi_bhandle, reg)
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2(sc->wi_btag, sc->wi_bhandle, reg)
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#define CSR_READ_1(sc, reg) \
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bus_space_read_1(sc->wi_btag, sc->wi_bhandle, reg)
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4((sc)->wi_btag, (sc)->wi_bhandle, \
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(sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg))
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2((sc)->wi_btag, (sc)->wi_bhandle, \
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(sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg))
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#define CSR_READ_1(sc, reg) \
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bus_space_read_1((sc)->wi_btag, (sc)->wi_bhandle, \
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(sc)->wi_bus_type == WI_BUS_PCI_NATIVE ? (reg)*2 : (reg))
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#define CSM_WRITE_1(sc, off, val) \
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bus_space_write_1(sc->wi_bmemtag, sc->wi_bmemhandle, off, val)
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bus_space_write_1((sc)->wi_bmemtag, (sc)->wi_bmemhandle, off, val)
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#define CSM_READ_1(sc, off) \
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bus_space_read_1(sc->wi_bmemtag, sc->wi_bmemhandle, off)
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bus_space_read_1((sc)->wi_bmemtag, (sc)->wi_bmemhandle, off)
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/*
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* The WaveLAN/IEEE cards contain an 802.11 MAC controller which Lucent
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