Enable use of the PCIe connected wifi on the DB120 (AR9344) board.
The on-board NIC is an 3x3 AR9380 with 5GHz only. * enable pci code in AR9344_BASE * enable ath_pci and the firmware loading bits in DB120 * add in the relevant hints in DB120.hints to inform the probe/attach code where the PCIe fixup data is for the onboard chip. This is only relevant for a default development board. I also have a DB120 with the on-board PCIe wifi NIC disabled and it's exposed as a real PCIe slot (to put normal PCIe NICs in); the fixup code will need to be disabled to make this work correctly. Tested: * DB120
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@ -102,6 +102,9 @@ options USB_DEBUG
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options USB_HOST_ALIGN=32 # AR71XX (MIPS in general?) requires this
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device ehci
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device pci
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device ar724x_pci
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device scbus
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device umass
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device da
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@ -22,6 +22,10 @@ hint.ehci.0.maddr=0x1b000100
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hint.ehci.0.msize=0x00001000
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hint.ehci.0.irq=1
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# pci
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hint.pcib.0.at="nexus0"
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hint.pcib.0.irq=0
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hint.arge.0.at="nexus0"
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hint.arge.0.maddr=0x19000000
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hint.arge.0.msize=0x1000
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@ -42,5 +42,11 @@ options GEOM_UNCOMPRESS
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# Used for the static uboot partition map
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device geom_map
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# yes, this board has a PCI connected atheros device
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device ath_pci
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options AR71XX_ATH_EEPROM
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device firmware # Used by the above
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options ATH_EEPROM_FIRMWARE
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# Boot off of the rootfs, as defined in the geom_map setup.
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options ROOTDEVNAME=\"ufs:map/rootfs.uncompress\"
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@ -60,6 +60,13 @@ hint.ath.0.eepromsize=16384
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# host registers on the NIC) and then we teach ath where
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# to find it.
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# ath1 hint - pcie slot 0
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hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000
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hint.pcib.0.bus.0.0.0.ath_fixup_size=16384
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# ath0 - eeprom comes from here
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hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
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# flash layout:
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#
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# bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)
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