Add support for the 'rdseed' instruction.
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@ -85,6 +85,7 @@ static void OP_MS (int, int);
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static void OP_XS (int, int);
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static void OP_M (int, int);
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static void OP_VMX (int, int);
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static void OP_VMX2 (int, int);
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static void OP_0fae (int, int);
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static void OP_0f07 (int, int);
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static void NOP_Fixup1 (int, int);
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@ -318,6 +319,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define EMC { OP_EMC, v_mode }
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#define MXC { OP_MXC, 0 }
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#define VM { OP_VMX, q_mode }
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#define VM2 { OP_VMX2, q_mode }
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#define OPSUF { OP_3DNowSuffix, 0 }
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#define OPSIMD { OP_SIMD_Suffix, 0 }
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#define XMM0 { XMM_Fixup, 0 }
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@ -1732,7 +1734,7 @@ static const struct dis386 grps[][8] = {
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{ "(bad)", { XX } },
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{ "(bad)", { XX } },
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{ "", { VM } }, /* See OP_VMX. */
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{ "vmptrst", { Mq } },
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{ "", { VM2 } }, /* See OP_VMX2. */
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},
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/* GRP11_C6 */
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{
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@ -6466,6 +6468,21 @@ OP_VMX (int bytemode, int sizeflag)
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}
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}
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static void
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OP_VMX2 (int bytemode, int sizeflag)
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{
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if (modrm.mod == 3)
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{
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strcpy (obuf, "rdseed");
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OP_E (v_mode, sizeflag);
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}
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else
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{
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strcpy (obuf, "vmptrst");
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OP_M (q_mode, sizeflag);
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}
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}
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static void
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REP_Fixup (int bytemode, int sizeflag)
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{
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@ -1524,3 +1524,4 @@ pclmulhqhqdq, 2, 0x660f3a44, 0x11, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|N
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// Intel Random Number Generator extensions
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rdrand, 1, 0x0fc7, 0x6, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 }
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rdseed, 1, 0x0fc7, 0x7, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 }
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@ -4391,6 +4391,9 @@ const template i386_optab[] =
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{"rdrand", 1, 0x0fc7, 0x6, CpuRdRnd,
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Modrm|NoSuf,
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{ Reg16|Reg32|Reg64 } },
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{"rdseed", 1, 0x0fc7, 0x7, CpuRdRnd,
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Modrm|NoSuf,
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{ Reg16|Reg32|Reg64 } },
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/* Intel Supervisor Mode Access Prevention extensions */
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{"clac", 0, 0x0f01, 0xca, CpuSMAP,
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