Add Reset Manager driver. This driver provides generic way to reset
and provides sysctl tunables for enable/disable FPGA<->HPS bridges. Sponsored by: DARPA, AFRL
This commit is contained in:
br
parent
c3c60bff50
commit
e32ad75659
@ -16,3 +16,4 @@ arm/arm/mpcore_timer.c standard
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arm/altera/socfpga/socfpga_common.c standard
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arm/altera/socfpga/socfpga_machdep.c standard
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arm/altera/socfpga/socfpga_manager.c standard
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arm/altera/socfpga/socfpga_rstmgr.c standard
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@ -42,20 +42,31 @@ __FBSDID("$FreeBSD$");
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#define RESMAN_BASE 0xFFD05000
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#define RESMAN_CTRL 0x4
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#define SWWARMRSTREQ (1 << 1)
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#include <arm/altera/socfpga/socfpga_rstmgr.h>
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void
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cpu_reset(void)
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{
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uint32_t addr, paddr;
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bus_addr_t vaddr;
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phandle_t node;
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if (bus_space_map(fdtbus_bs_tag, RESMAN_BASE, 0x10, 0, &vaddr) == 0) {
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if (rstmgr_warmreset() == 0)
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goto end;
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node = OF_finddevice("rstmgr");
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if (node == -1)
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goto end;
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if ((OF_getprop(node, "reg", &paddr, sizeof(paddr))) > 0) {
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addr = fdt32_to_cpu(paddr);
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if (bus_space_map(fdtbus_bs_tag, addr, 0x8, 0, &vaddr) == 0) {
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bus_space_write_4(fdtbus_bs_tag, vaddr,
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RESMAN_CTRL, SWWARMRSTREQ);
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RSTMGR_CTRL, CTRL_SWWARMRSTREQ);
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}
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}
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end:
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while (1);
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}
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54
sys/arm/altera/socfpga/socfpga_l3regs.h
Normal file
54
sys/arm/altera/socfpga/socfpga_l3regs.h
Normal file
@ -0,0 +1,54 @@
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/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define L3REGS_REMAP 0x0 /* Remap */
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#define REMAP_LWHPS2FPGA (1 << 4)
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#define REMAP_HPS2FPGA (1 << 3)
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#define REMAP_MPUZERO (1 << 0)
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#define L3REGS_L4MAIN 0x8 /* L4 main peripherals security */
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#define L3REGS_L4SP 0xC /* L4 SP Peripherals Security */
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#define L3REGS_L4MP 0x10 /* L4 MP Peripherals Security */
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#define L3REGS_L4OSC1 0x14 /* L4 OSC1 Peripherals Security */
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#define L3REGS_L4SPIM 0x18 /* L4 SPIM Peripherals Security */
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#define L3REGS_STM 0x1C /* STM Peripheral Security */
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#define L3REGS_LWHPS2FPGAREGS 0x20 /* LWHPS2FPGA AXI Bridge Security */
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#define L3REGS_USB1 0x28 /* USB1 Peripheral Security */
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#define L3REGS_NANDDATA 0x2C /* NAND Flash Controller Data Sec */
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#define L3REGS_USB0 0x80 /* USB0 Peripheral Security */
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#define L3REGS_NANDREGS 0x84 /* NAND Flash Controller Security */
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#define L3REGS_QSPIDATA 0x88 /* QSPI Flash Controller Data Sec */
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#define L3REGS_FPGAMGRDATA 0x8C /* FPGA Manager Data Peripheral Sec */
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#define L3REGS_HPS2FPGAREGS 0x90 /* HPS2FPGA AXI Bridge Perip. Sec */
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#define L3REGS_ACP 0x94 /* MPU ACP Peripheral Security */
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#define L3REGS_ROM 0x98 /* ROM Peripheral Security */
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#define L3REGS_OCRAM 0x9C /* On-chip RAM Peripheral Security */
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#define L3REGS_SDRDATA 0xA0 /* SDRAM Data Peripheral Security */
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259
sys/arm/altera/socfpga/socfpga_rstmgr.c
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259
sys/arm/altera/socfpga/socfpga_rstmgr.c
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@ -0,0 +1,259 @@
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/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* SOCFPGA Reset Manager.
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* Chapter 3, Cyclone V Device Handbook (CV-5V2 2014.07.22)
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/sysctl.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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#include <machine/fdt.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <arm/altera/socfpga/socfpga_common.h>
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#include <arm/altera/socfpga/socfpga_rstmgr.h>
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#include <arm/altera/socfpga/socfpga_l3regs.h>
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struct rstmgr_softc {
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struct resource *res[1];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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device_t dev;
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};
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struct rstmgr_softc *rstmgr_sc;
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static struct resource_spec rstmgr_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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enum {
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RSTMGR_SYSCTL_FPGA2HPS,
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RSTMGR_SYSCTL_LWHPS2FPGA,
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RSTMGR_SYSCTL_HPS2FPGA
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};
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static int
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l3remap(struct rstmgr_softc *sc, int remap, int enable)
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{
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uint32_t addr, paddr;
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bus_addr_t vaddr;
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phandle_t node;
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int reg;
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/*
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* Control whether bridge is visible to L3 masters or not.
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* Register is write-only.
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*/
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reg = REMAP_MPUZERO;
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if (enable)
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reg |= (remap);
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else
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reg &= ~(remap);
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node = OF_finddevice("l3regs");
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if (node == -1) {
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device_printf(sc->dev, "Can't find l3regs node\n");
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return (1);
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}
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if ((OF_getprop(node, "reg", &paddr, sizeof(paddr))) > 0) {
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addr = fdt32_to_cpu(paddr);
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if (bus_space_map(fdtbus_bs_tag, addr, 0x4, 0, &vaddr) == 0) {
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bus_space_write_4(fdtbus_bs_tag, vaddr,
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L3REGS_REMAP, reg);
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return (0);
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}
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}
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return (1);
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}
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static int
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rstmgr_sysctl(SYSCTL_HANDLER_ARGS)
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{
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struct rstmgr_softc *sc;
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int enable;
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int remap;
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int err;
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int reg;
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int bit;
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sc = arg1;
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switch (arg2) {
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case RSTMGR_SYSCTL_FPGA2HPS:
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bit = BRGMODRST_FPGA2HPS;
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remap = 0;
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break;
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case RSTMGR_SYSCTL_LWHPS2FPGA:
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bit = BRGMODRST_LWHPS2FPGA;
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remap = REMAP_LWHPS2FPGA;
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break;
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case RSTMGR_SYSCTL_HPS2FPGA:
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bit = BRGMODRST_HPS2FPGA;
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remap = REMAP_HPS2FPGA;
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break;
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default:
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return (1);
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};
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reg = READ4(sc, RSTMGR_BRGMODRST);
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enable = reg & bit ? 0 : 1;
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err = sysctl_handle_int(oidp, &enable, 0, req);
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if (err || !req->newptr)
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return (err);
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if (enable == 1)
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reg &= ~(bit);
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else if (enable == 0)
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reg |= (bit);
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else
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return (EINVAL);
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WRITE4(sc, RSTMGR_BRGMODRST, reg);
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l3remap(sc, remap, enable);
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return (0);
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}
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int
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rstmgr_warmreset(void)
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{
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struct rstmgr_softc *sc;
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sc = rstmgr_sc;
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if (sc == NULL)
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return (1);
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/* Request warm reset */
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WRITE4(sc, RSTMGR_CTRL,
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CTRL_SWWARMRSTREQ);
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return (0);
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}
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static int
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rstmgr_add_sysctl(struct rstmgr_softc *sc)
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{
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struct sysctl_oid_list *children;
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struct sysctl_ctx_list *ctx;
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ctx = device_get_sysctl_ctx(sc->dev);
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children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
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SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fpga2hps",
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CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_FPGA2HPS,
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rstmgr_sysctl, "I", "Enable fpga2hps bridge");
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SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lwhps2fpga",
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CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_LWHPS2FPGA,
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rstmgr_sysctl, "I", "Enable lwhps2fpga bridge");
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SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hps2fpga",
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CTLTYPE_UINT | CTLFLAG_RW, sc, RSTMGR_SYSCTL_HPS2FPGA,
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rstmgr_sysctl, "I", "Enable hps2fpga bridge");
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return (0);
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}
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static int
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rstmgr_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "altr,rst-mgr"))
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return (ENXIO);
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device_set_desc(dev, "Reset Manager");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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rstmgr_attach(device_t dev)
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{
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struct rstmgr_softc *sc;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, rstmgr_spec, sc->res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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/* Memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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rstmgr_sc = sc;
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rstmgr_add_sysctl(sc);
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return (0);
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}
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static device_method_t rstmgr_methods[] = {
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DEVMETHOD(device_probe, rstmgr_probe),
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DEVMETHOD(device_attach, rstmgr_attach),
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{ 0, 0 }
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};
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static driver_t rstmgr_driver = {
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"rstmgr",
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rstmgr_methods,
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sizeof(struct rstmgr_softc),
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};
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static devclass_t rstmgr_devclass;
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DRIVER_MODULE(rstmgr, simplebus, rstmgr_driver, rstmgr_devclass, 0, 0);
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46
sys/arm/altera/socfpga/socfpga_rstmgr.h
Normal file
46
sys/arm/altera/socfpga/socfpga_rstmgr.h
Normal file
@ -0,0 +1,46 @@
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/*-
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* Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
|
||||
* All rights reserved.
|
||||
*
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||||
* This software was developed by SRI International and the University of
|
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
|
||||
* ("CTSRD"), as part of the DARPA CRASH research programme.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
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||||
* $FreeBSD$
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||||
*/
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||||
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#define RSTMGR_STAT 0x0 /* Status */
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#define RSTMGR_CTRL 0x4 /* Control */
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#define CTRL_SWWARMRSTREQ (1 << 1) /* Trigger warm reset */
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#define RSTMGR_COUNTS 0x8 /* Reset Cycles Count */
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#define RSTMGR_MPUMODRST 0x10 /* MPU Module Reset */
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#define RSTMGR_PERMODRST 0x14 /* Peripheral Module Reset */
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#define RSTMGR_PER2MODRST 0x18 /* Peripheral 2 Module Reset */
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#define RSTMGR_BRGMODRST 0x1C /* Bridge Module Reset */
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#define BRGMODRST_FPGA2HPS (1 << 2)
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#define BRGMODRST_LWHPS2FPGA (1 << 1)
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#define BRGMODRST_HPS2FPGA (1 << 0)
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#define RSTMGR_MISCMODRST 0x20 /* Miscellaneous Module Reset */
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int rstmgr_warmreset(void);
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@ -39,6 +39,8 @@
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aliases {
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soc = &SOC;
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rstmgr = &rstmgr;
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l3regs = &l3regs;
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serial0 = &serial0;
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serial1 = &serial1;
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};
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@ -69,6 +71,16 @@
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interrupt-parent = < &GIC >;
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};
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rstmgr: rstmgr@ffd05000 {
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compatible = "altr,rst-mgr";
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reg = <0xffd05000 0x1000>;
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};
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l3regs: l3regs@ff800000 {
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compatible = "altr,l3regs";
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reg = <0xff800000 0x1000>;
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};
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fpgamgr: fpgamgr@ff706000 {
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compatible = "altr,fpga-mgr";
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reg = <0xff706000 0x1000>, /* FPGAMGRREGS */
|
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|
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Loading…
Reference in New Issue
Block a user