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arm64: rockchip: Correctly set armclk

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Parent needs to be the same frequency as the armclk, not twice the freq.
The real divider is incremented by one so write it with - 1
The rate can be at index 0

Pointy Hat To: myself
This commit is contained in:
Emmanuel Vadot 2018-06-12 11:47:21 +00:00
parent 6ee7d5afcc
commit e34425be26
1 changed files with 4 additions and 3 deletions
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7
sys/arm64/rockchip/clk/rk_clk_armclk.c
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@ -154,12 +154,13 @@ rk_clk_armclk_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
if (sc->rates[i].freq == *fout) {
best = sc->rates[i].freq;
div = sc->rates[i].div;
best_p = best * (div + 1);
best_p = best * div;
rate = i;
break;
}
}
if (rate == 0)
if (rate == sc->nrates)
return (0);
err = clknode_set_freq(p_main, best_p, 0, 1);
@ -177,7 +178,7 @@ rk_clk_armclk_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
DEVICE_LOCK(clk);
READ4(clk, sc->muxdiv_offset, &val);
val &= ~sc->div_mask;
val |= div << sc->div_shift;
val |= (div - 1) << sc->div_shift;
WRITE4(clk, sc->muxdiv_offset, val | RK_CLK_ARMCLK_MASK);
DEVICE_UNLOCK(clk);