From 0eed04c802f4a50c9409a6682a474852bebee990 Mon Sep 17 00:00:00 2001 From: Ruslan Bukin Date: Fri, 31 Jul 2020 23:02:17 +0000 Subject: [PATCH 001/141] Add iommu_domain_map_ops virtual table with map/unmap methods so x86 can support Intel DMAR and AMD IOMMU simultaneously. Reviewed by: kib Sponsored by: DARPA/AFRL Differential Revision: https://reviews.freebsd.org/D25894 --- sys/dev/iommu/iommu.h | 8 ++++++++ sys/dev/iommu/iommu_gas.c | 15 ++++++--------- sys/x86/iommu/intel_ctx.c | 5 ++++- sys/x86/iommu/intel_dmar.h | 5 +---- sys/x86/iommu/intel_idpgtbl.c | 23 ++++++++++++++++++++--- 5 files changed, 39 insertions(+), 17 deletions(-) diff --git a/sys/dev/iommu/iommu.h b/sys/dev/iommu/iommu.h index e6ad0569a9ac..31f9e5959698 100644 --- a/sys/dev/iommu/iommu.h +++ b/sys/dev/iommu/iommu.h @@ -100,6 +100,13 @@ struct iommu_unit { uint32_t buswide_ctxs[(PCI_BUSMAX + 1) / NBBY / sizeof(uint32_t)]; }; +struct iommu_domain_map_ops { + int (*map)(struct iommu_domain *domain, iommu_gaddr_t base, + iommu_gaddr_t size, vm_page_t *ma, uint64_t pflags, int flags); + int (*unmap)(struct iommu_domain *domain, iommu_gaddr_t base, + iommu_gaddr_t size, int flags); +}; + /* * Locking annotations: * (u) - Protected by iommu unit lock @@ -109,6 +116,7 @@ struct iommu_unit { struct iommu_domain { struct iommu_unit *iommu; /* (c) */ + const struct iommu_domain_map_ops *ops; struct mtx lock; /* (c) */ struct task unload_task; /* (c) */ u_int entries_cnt; /* (d) */ diff --git a/sys/dev/iommu/iommu_gas.c b/sys/dev/iommu/iommu_gas.c index 04d7d9667109..fe5d59329b9d 100644 --- a/sys/dev/iommu/iommu_gas.c +++ b/sys/dev/iommu/iommu_gas.c @@ -66,10 +66,7 @@ __FBSDID("$FreeBSD$"); #include #include #if defined(__amd64__) || defined(__i386__) -#include -#include #include -#include #endif #include @@ -620,9 +617,9 @@ iommu_gas_map(struct iommu_domain *domain, entry->flags |= eflags; IOMMU_DOMAIN_UNLOCK(domain); - error = domain_map_buf(domain, entry->start, entry->end - entry->start, - ma, eflags, - ((flags & IOMMU_MF_CANWAIT) != 0 ? IOMMU_PGF_WAITOK : 0)); + error = domain->ops->map(domain, entry->start, + entry->end - entry->start, ma, eflags, + ((flags & IOMMU_MF_CANWAIT) != 0 ? IOMMU_PGF_WAITOK : 0)); if (error == ENOMEM) { iommu_domain_unload_entry(entry, true); return (error); @@ -658,9 +655,9 @@ iommu_gas_map_region(struct iommu_domain *domain, struct iommu_map_entry *entry, if (entry->end == entry->start) return (0); - error = domain_map_buf(domain, entry->start, entry->end - entry->start, - ma + OFF_TO_IDX(start - entry->start), eflags, - ((flags & IOMMU_MF_CANWAIT) != 0 ? IOMMU_PGF_WAITOK : 0)); + error = domain->ops->map(domain, entry->start, + entry->end - entry->start, ma + OFF_TO_IDX(start - entry->start), + eflags, ((flags & IOMMU_MF_CANWAIT) != 0 ? IOMMU_PGF_WAITOK : 0)); if (error == ENOMEM) { iommu_domain_unload_entry(entry, false); return (error); diff --git a/sys/x86/iommu/intel_ctx.c b/sys/x86/iommu/intel_ctx.c index 234a920d1ded..2f02bd1cdf2c 100644 --- a/sys/x86/iommu/intel_ctx.c +++ b/sys/x86/iommu/intel_ctx.c @@ -341,6 +341,7 @@ dmar_domain_alloc(struct dmar_unit *dmar, bool id_mapped) mtx_init(&domain->iodom.lock, "dmardom", NULL, MTX_DEF); domain->dmar = dmar; domain->iodom.iommu = &dmar->iommu; + domain_pgtbl_init(domain); /* * For now, use the maximal usable physical address of the @@ -842,15 +843,17 @@ dmar_domain_unload(struct dmar_domain *domain, struct iommu_map_entries_tailq *entries, bool cansleep) { struct dmar_unit *unit; + struct iommu_domain *iodom; struct iommu_map_entry *entry, *entry1; int error; + iodom = (struct iommu_domain *)domain; unit = (struct dmar_unit *)domain->iodom.iommu; TAILQ_FOREACH_SAFE(entry, entries, dmamap_link, entry1) { KASSERT((entry->flags & IOMMU_MAP_ENTRY_MAP) != 0, ("not mapped entry %p %p", domain, entry)); - error = domain_unmap_buf(domain, entry->start, entry->end - + error = iodom->ops->unmap(iodom, entry->start, entry->end - entry->start, cansleep ? IOMMU_PGF_WAITOK : 0); KASSERT(error == 0, ("unmap %p error %d", domain, error)); if (!unit->qi_enabled) { diff --git a/sys/x86/iommu/intel_dmar.h b/sys/x86/iommu/intel_dmar.h index eae01bcc134d..23cffe6f6fb6 100644 --- a/sys/x86/iommu/intel_dmar.h +++ b/sys/x86/iommu/intel_dmar.h @@ -244,14 +244,11 @@ void dmar_qi_invalidate_iec(struct dmar_unit *unit, u_int start, u_int cnt); vm_object_t domain_get_idmap_pgtbl(struct dmar_domain *domain, iommu_gaddr_t maxaddr); void put_idmap_pgtbl(vm_object_t obj); -int domain_map_buf(struct iommu_domain *domain, iommu_gaddr_t base, - iommu_gaddr_t size, vm_page_t *ma, uint64_t pflags, int flags); -int domain_unmap_buf(struct dmar_domain *domain, iommu_gaddr_t base, - iommu_gaddr_t size, int flags); void domain_flush_iotlb_sync(struct dmar_domain *domain, iommu_gaddr_t base, iommu_gaddr_t size); int domain_alloc_pgtbl(struct dmar_domain *domain); void domain_free_pgtbl(struct dmar_domain *domain); +void domain_pgtbl_init(struct dmar_domain *domain); int dmar_dev_depth(device_t child); void dmar_dev_path(device_t child, int *busno, void *path1, int depth); diff --git a/sys/x86/iommu/intel_idpgtbl.c b/sys/x86/iommu/intel_idpgtbl.c index 4c151ffffef8..9e4beea9031b 100644 --- a/sys/x86/iommu/intel_idpgtbl.c +++ b/sys/x86/iommu/intel_idpgtbl.c @@ -498,7 +498,7 @@ domain_map_buf_locked(struct dmar_domain *domain, iommu_gaddr_t base, return (0); } -int +static int domain_map_buf(struct iommu_domain *iodom, iommu_gaddr_t base, iommu_gaddr_t size, vm_page_t *ma, uint64_t eflags, int flags) { @@ -684,12 +684,15 @@ domain_unmap_buf_locked(struct dmar_domain *domain, iommu_gaddr_t base, return (0); } -int -domain_unmap_buf(struct dmar_domain *domain, iommu_gaddr_t base, +static int +domain_unmap_buf(struct iommu_domain *iodom, iommu_gaddr_t base, iommu_gaddr_t size, int flags) { + struct dmar_domain *domain; int error; + domain = (struct dmar_domain *)iodom; + DMAR_DOMAIN_PGLOCK(domain); error = domain_unmap_buf_locked(domain, base, size, flags); DMAR_DOMAIN_PGUNLOCK(domain); @@ -809,3 +812,17 @@ domain_flush_iotlb_sync(struct dmar_domain *domain, iommu_gaddr_t base, } DMAR_UNLOCK(unit); } + +static const struct iommu_domain_map_ops dmar_domain_map_ops = { + .map = domain_map_buf, + .unmap = domain_unmap_buf, +}; + +void +domain_pgtbl_init(struct dmar_domain *domain) +{ + struct iommu_domain *iodom; + + iodom = (struct iommu_domain *)domain; + iodom->ops = &dmar_domain_map_ops; +} From cb889ce631b9d37bf0fe82290616bf4e4596d47f Mon Sep 17 00:00:00 2001 From: Rick Macklem Date: Fri, 31 Jul 2020 23:35:49 +0000 Subject: [PATCH 002/141] Add optional support for ext_pgs mbufs to the NFS server's read, readlink and getxattr operations. This patch optionally enables generation of read, readlink and getxattr replies in ext_pgs mbufs. Since neither of ND_EXTPG or ND_TLS are currently ever set, there is no change in semantics at this time. It also corrects the message in a couple of panic()s that should never occur. This is another in the series of commits that add support to the NFS client and server for building RPC messages in ext_pgs mbufs with anonymous pages. This is useful so that the entire mbuf list does not need to be copied before calling sosend() when NFS over TLS is enabled. Use of ext_pgs mbufs will not be enabled until the kernel RPC is updated to handle TLS. --- sys/fs/nfs/nfs_var.h | 6 +- sys/fs/nfsserver/nfs_nfsdport.c | 109 +++++++++++++++++++++++++++++--- sys/fs/nfsserver/nfs_nfsdserv.c | 73 ++++++++++++++++++--- 3 files changed, 165 insertions(+), 23 deletions(-) diff --git a/sys/fs/nfs/nfs_var.h b/sys/fs/nfs/nfs_var.h index 1cf792edeced..7bf89011d2fd 100644 --- a/sys/fs/nfs/nfs_var.h +++ b/sys/fs/nfs/nfs_var.h @@ -680,9 +680,9 @@ int nfsvno_namei(struct nfsrv_descript *, struct nameidata *, vnode_t, int, struct nfsexstuff *, NFSPROC_T *, vnode_t *); void nfsvno_setpathbuf(struct nameidata *, char **, u_long **); void nfsvno_relpathbuf(struct nameidata *); -int nfsvno_readlink(vnode_t, struct ucred *, NFSPROC_T *, struct mbuf **, +int nfsvno_readlink(vnode_t, struct ucred *, int, NFSPROC_T *, struct mbuf **, struct mbuf **, int *); -int nfsvno_read(vnode_t, off_t, int, struct ucred *, NFSPROC_T *, +int nfsvno_read(vnode_t, off_t, int, struct ucred *, int, NFSPROC_T *, struct mbuf **, struct mbuf **); int nfsvno_write(vnode_t, off_t, int, int *, struct mbuf *, char *, struct ucred *, NFSPROC_T *); @@ -748,7 +748,7 @@ int nfsvno_seek(struct nfsrv_descript *, struct vnode *, u_long, off_t *, int, bool *, struct ucred *, NFSPROC_T *); int nfsvno_allocate(struct vnode *, off_t, off_t, struct ucred *, NFSPROC_T *); int nfsvno_getxattr(struct vnode *, char *, uint32_t, struct ucred *, - struct thread *, struct mbuf **, struct mbuf **, int *); + uint64_t, int, struct thread *, struct mbuf **, struct mbuf **, int *); int nfsvno_setxattr(struct vnode *, char *, int, struct mbuf *, char *, struct ucred *, struct thread *); int nfsvno_rmxattr(struct nfsrv_descript *, struct vnode *, char *, diff --git a/sys/fs/nfsserver/nfs_nfsdport.c b/sys/fs/nfsserver/nfs_nfsdport.c index eb971d73d534..2dda74d885db 100644 --- a/sys/fs/nfsserver/nfs_nfsdport.c +++ b/sys/fs/nfsserver/nfs_nfsdport.c @@ -108,6 +108,8 @@ extern struct nfsdevicehead nfsrv_devidhead; static int nfsrv_createiovec(int, struct mbuf **, struct mbuf **, struct iovec **); +static int nfsrv_createiovec_extpgs(int, int, struct mbuf **, + struct mbuf **, struct iovec **); static int nfsrv_createiovecw(int, struct mbuf *, char *, struct iovec **, int *); static void nfsrv_pnfscreate(struct vnode *, struct vattr *, struct ucred *, @@ -738,8 +740,8 @@ nfsvno_relpathbuf(struct nameidata *ndp) * Readlink vnode op into an mbuf list. */ int -nfsvno_readlink(struct vnode *vp, struct ucred *cred, struct thread *p, - struct mbuf **mpp, struct mbuf **mpendp, int *lenp) +nfsvno_readlink(struct vnode *vp, struct ucred *cred, int maxextsiz, + struct thread *p, struct mbuf **mpp, struct mbuf **mpendp, int *lenp) { struct iovec *iv; struct uio io, *uiop = &io; @@ -747,7 +749,11 @@ nfsvno_readlink(struct vnode *vp, struct ucred *cred, struct thread *p, int len, tlen, error = 0; len = NFS_MAXPATHLEN; - uiop->uio_iovcnt = nfsrv_createiovec(len, &mp3, &mp, &iv); + if (maxextsiz > 0) + uiop->uio_iovcnt = nfsrv_createiovec_extpgs(len, maxextsiz, + &mp3, &mp, &iv); + else + uiop->uio_iovcnt = nfsrv_createiovec(len, &mp3, &mp, &iv); uiop->uio_iov = iv; uiop->uio_offset = 0; uiop->uio_resid = len; @@ -819,7 +825,7 @@ nfsrv_createiovec(int len, struct mbuf **mpp, struct mbuf **mpendp, i = 0; while (left > 0) { if (m == NULL) - panic("nfsvno_read iov"); + panic("nfsrv_createiovec iov"); siz = min(M_TRAILINGSPACE(m), left); if (siz > 0) { iv->iov_base = mtod(m, caddr_t) + m->m_len; @@ -836,12 +842,77 @@ nfsrv_createiovec(int len, struct mbuf **mpp, struct mbuf **mpendp, return (i); } +/* + * Create an mbuf chain and an associated iovec that can be used to Read + * or Getextattr of data. + * Upon success, return pointers to the first and last mbufs in the chain + * plus the malloc'd iovec and its iovlen. + * Same as above, but creates ext_pgs mbuf(s). + */ +static int +nfsrv_createiovec_extpgs(int len, int maxextsiz, struct mbuf **mpp, + struct mbuf **mpendp, struct iovec **ivp) +{ + struct mbuf *m, *m2 = NULL, *m3; + struct iovec *iv; + int i, left, pgno, siz; + + left = len; + m3 = NULL; + /* + * Generate the mbuf list with the uio_iov ref. to it. + */ + i = 0; + while (left > 0) { + siz = min(left, maxextsiz); + m = mb_alloc_ext_plus_pages(siz, M_WAITOK); + left -= siz; + i += m->m_epg_npgs; + if (m3 != NULL) + m2->m_next = m; + else + m3 = m; + m2 = m; + } + *ivp = iv = malloc(i * sizeof (struct iovec), M_TEMP, M_WAITOK); + m = m3; + left = len; + i = 0; + pgno = 0; + while (left > 0) { + if (m == NULL) + panic("nfsvno_createiovec_extpgs iov"); + siz = min(PAGE_SIZE, left); + if (siz > 0) { + iv->iov_base = (void *)PHYS_TO_DMAP(m->m_epg_pa[pgno]); + iv->iov_len = siz; + m->m_len += siz; + if (pgno == m->m_epg_npgs - 1) + m->m_epg_last_len = siz; + left -= siz; + iv++; + i++; + pgno++; + } + if (pgno == m->m_epg_npgs && left > 0) { + m = m->m_next; + if (m == NULL) + panic("nfsvno_createiovec_extpgs iov"); + pgno = 0; + } + } + *mpp = m3; + *mpendp = m2; + return (i); +} + /* * Read vnode op call into mbuf list. */ int nfsvno_read(struct vnode *vp, off_t off, int cnt, struct ucred *cred, - struct thread *p, struct mbuf **mpp, struct mbuf **mpendp) + int maxextsiz, struct thread *p, struct mbuf **mpp, + struct mbuf **mpendp) { struct mbuf *m; struct iovec *iv; @@ -860,7 +931,11 @@ nfsvno_read(struct vnode *vp, off_t off, int cnt, struct ucred *cred, return (error); len = NFSM_RNDUP(cnt); - uiop->uio_iovcnt = nfsrv_createiovec(len, &m3, &m, &iv); + if (maxextsiz > 0) + uiop->uio_iovcnt = nfsrv_createiovec_extpgs(len, maxextsiz, + &m3, &m, &iv); + else + uiop->uio_iovcnt = nfsrv_createiovec(len, &m3, &m, &iv); uiop->uio_iov = iv; uiop->uio_offset = off; uiop->uio_resid = len; @@ -938,7 +1013,7 @@ nfsrv_createiovecw(int retlen, struct mbuf *m, char *cp, struct iovec **ivpp, len = retlen; while (len > 0) { if (mp == NULL) - panic("nfsvno_write"); + panic("nfsrv_createiovecw"); if (i > 0) { i = min(i, len); ivp->iov_base = cp; @@ -6241,8 +6316,8 @@ nfsvno_allocate(struct vnode *vp, off_t off, off_t len, struct ucred *cred, */ int nfsvno_getxattr(struct vnode *vp, char *name, uint32_t maxresp, - struct ucred *cred, struct thread *p, struct mbuf **mpp, - struct mbuf **mpendp, int *lenp) + struct ucred *cred, uint64_t flag, int maxextsiz, struct thread *p, + struct mbuf **mpp, struct mbuf **mpendp, int *lenp) { struct iovec *iv; struct uio io, *uiop = &io; @@ -6260,7 +6335,21 @@ nfsvno_getxattr(struct vnode *vp, char *name, uint32_t maxresp, len = siz; tlen = NFSM_RNDUP(len); if (tlen > 0) { - uiop->uio_iovcnt = nfsrv_createiovec(tlen, &m, &m2, &iv); + /* + * If cnt > MCLBYTES and the reply will not be saved, use + * ext_pgs mbufs for TLS. + * For NFSv4.0, we do not know for sure if the reply will + * be saved, so do not use ext_pgs mbufs for NFSv4.0. + * Always use ext_pgs mbufs if ND_EXTPG is set. + */ + if ((flag & ND_EXTPG) != 0 || (tlen > MCLBYTES && + (flag & (ND_TLS | ND_SAVEREPLY)) == ND_TLS && + (flag & (ND_NFSV4 | ND_NFSV41)) != ND_NFSV4)) + uiop->uio_iovcnt = nfsrv_createiovec_extpgs(tlen, + maxextsiz, &m, &m2, &iv); + else + uiop->uio_iovcnt = nfsrv_createiovec(tlen, &m, &m2, + &iv); uiop->uio_iov = iv; } else { uiop->uio_iovcnt = 0; diff --git a/sys/fs/nfsserver/nfs_nfsdserv.c b/sys/fs/nfsserver/nfs_nfsdserv.c index 1b34cb27dd01..d2fe9e60a0ea 100644 --- a/sys/fs/nfsserver/nfs_nfsdserv.c +++ b/sys/fs/nfsserver/nfs_nfsdserv.c @@ -667,6 +667,7 @@ nfsrvd_readlink(struct nfsrv_descript *nd, __unused int isdgram, int getret = 1, len; struct nfsvattr nva; struct thread *p = curthread; + uint16_t off; if (nd->nd_repstat) { nfsrv_postopattr(nd, getret, &nva); @@ -678,9 +679,14 @@ nfsrvd_readlink(struct nfsrv_descript *nd, __unused int isdgram, else nd->nd_repstat = EINVAL; } - if (!nd->nd_repstat) - nd->nd_repstat = nfsvno_readlink(vp, nd->nd_cred, p, - &mp, &mpend, &len); + if (nd->nd_repstat == 0) { + if ((nd->nd_flag & ND_EXTPG) != 0) + nd->nd_repstat = nfsvno_readlink(vp, nd->nd_cred, + nd->nd_maxextsiz, p, &mp, &mpend, &len); + else + nd->nd_repstat = nfsvno_readlink(vp, nd->nd_cred, + 0, p, &mp, &mpend, &len); + } if (nd->nd_flag & ND_NFSV3) getret = nfsvno_getattr(vp, &nva, nd, p, 1, NULL); vput(vp); @@ -693,7 +699,16 @@ nfsrvd_readlink(struct nfsrv_descript *nd, __unused int isdgram, if (mp != NULL) { nd->nd_mb->m_next = mp; nd->nd_mb = mpend; - nd->nd_bpos = mtod(mpend, caddr_t) + mpend->m_len; + if ((mpend->m_flags & M_EXTPG) != 0) { + nd->nd_bextpg = mpend->m_epg_npgs - 1; + nd->nd_bpos = (char *)(void *) + PHYS_TO_DMAP(mpend->m_epg_pa[nd->nd_bextpg]); + off = (nd->nd_bextpg == 0) ? mpend->m_epg_1st_off : 0; + nd->nd_bpos += off + mpend->m_epg_last_len; + nd->nd_bextpgsiz = PAGE_SIZE - mpend->m_epg_last_len - + off; + } else + nd->nd_bpos = mtod(mpend, char *) + mpend->m_len; } out: @@ -718,6 +733,7 @@ nfsrvd_read(struct nfsrv_descript *nd, __unused int isdgram, nfsv4stateid_t stateid; nfsquad_t clientid; struct thread *p = curthread; + uint16_t poff; if (nd->nd_repstat) { nfsrv_postopattr(nd, getret, &nva); @@ -839,8 +855,21 @@ nfsrvd_read(struct nfsrv_descript *nd, __unused int isdgram, cnt = reqlen; m3 = NULL; if (cnt > 0) { - nd->nd_repstat = nfsvno_read(vp, off, cnt, nd->nd_cred, p, - &m3, &m2); + /* + * If cnt > MCLBYTES and the reply will not be saved, use + * ext_pgs mbufs for TLS. + * For NFSv4.0, we do not know for sure if the reply will + * be saved, so do not use ext_pgs mbufs for NFSv4.0. + * Always use ext_pgs mbufs if ND_EXTPG is set. + */ + if ((nd->nd_flag & ND_EXTPG) != 0 || (cnt > MCLBYTES && + (nd->nd_flag & (ND_TLS | ND_SAVEREPLY)) == ND_TLS && + (nd->nd_flag & (ND_NFSV4 | ND_NFSV41)) != ND_NFSV4)) + nd->nd_repstat = nfsvno_read(vp, off, cnt, nd->nd_cred, + nd->nd_maxextsiz, p, &m3, &m2); + else + nd->nd_repstat = nfsvno_read(vp, off, cnt, nd->nd_cred, + 0, p, &m3, &m2); if (!(nd->nd_flag & ND_NFSV4)) { getret = nfsvno_getattr(vp, &nva, nd, p, 1, NULL); if (!nd->nd_repstat) @@ -875,7 +904,17 @@ nfsrvd_read(struct nfsrv_descript *nd, __unused int isdgram, if (m3) { nd->nd_mb->m_next = m3; nd->nd_mb = m2; - nd->nd_bpos = mtod(m2, caddr_t) + m2->m_len; + if ((m2->m_flags & M_EXTPG) != 0) { + nd->nd_flag |= ND_EXTPG; + nd->nd_bextpg = m2->m_epg_npgs - 1; + nd->nd_bpos = (char *)(void *) + PHYS_TO_DMAP(m2->m_epg_pa[nd->nd_bextpg]); + poff = (nd->nd_bextpg == 0) ? m2->m_epg_1st_off : 0; + nd->nd_bpos += poff + m2->m_epg_last_len; + nd->nd_bextpgsiz = PAGE_SIZE - m2->m_epg_last_len - + poff; + } else + nd->nd_bpos = mtod(m2, char *) + m2->m_len; } out: @@ -5536,6 +5575,7 @@ nfsrvd_getxattr(struct nfsrv_descript *nd, __unused int isdgram, int error, len; char *name; struct thread *p = curthread; + uint16_t off; error = 0; if (nfs_rootfhset == 0 || nfsd_checkrootexp(nd) != 0) { @@ -5555,8 +5595,9 @@ nfsrvd_getxattr(struct nfsrv_descript *nd, __unused int isdgram, name = malloc(len + 1, M_TEMP, M_WAITOK); nd->nd_repstat = nfsrv_mtostr(nd, name, len); if (nd->nd_repstat == 0) - nd->nd_repstat = nfsvno_getxattr(vp, name, nd->nd_maxresp, - nd->nd_cred, p, &mp, &mpend, &len); + nd->nd_repstat = nfsvno_getxattr(vp, name, + nd->nd_maxresp, nd->nd_cred, nd->nd_flag, + nd->nd_maxextsiz, p, &mp, &mpend, &len); if (nd->nd_repstat == ENOATTR) nd->nd_repstat = NFSERR_NOXATTR; else if (nd->nd_repstat == EOPNOTSUPP) @@ -5567,7 +5608,19 @@ nfsrvd_getxattr(struct nfsrv_descript *nd, __unused int isdgram, if (len > 0) { nd->nd_mb->m_next = mp; nd->nd_mb = mpend; - nd->nd_bpos = mtod(mpend, caddr_t) + mpend->m_len; + if ((mpend->m_flags & M_EXTPG) != 0) { + nd->nd_flag |= ND_EXTPG; + nd->nd_bextpg = mpend->m_epg_npgs - 1; + nd->nd_bpos = (char *)(void *) + PHYS_TO_DMAP(mpend->m_epg_pa[nd->nd_bextpg]); + off = (nd->nd_bextpg == 0) ? + mpend->m_epg_1st_off : 0; + nd->nd_bpos += off + mpend->m_epg_last_len; + nd->nd_bextpgsiz = PAGE_SIZE - + mpend->m_epg_last_len - off; + } else + nd->nd_bpos = mtod(mpend, char *) + + mpend->m_len; } } free(name, M_TEMP); From c5112a4e2d1f6ef0ef4cbd9215d30c663f01b0d3 Mon Sep 17 00:00:00 2001 From: Gregory Neil Shapiro Date: Sat, 1 Aug 2020 04:57:30 +0000 Subject: [PATCH 003/141] Mirror recommendation from Handbook to avoid linking conflicts when pulling in SASL libraries. PR: 247959 Reported by: Scott Allendorf MFC after: 3 days --- share/examples/etc/make.conf | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/share/examples/etc/make.conf b/share/examples/etc/make.conf index 37b3b774c8d2..a7afe4d8b6eb 100644 --- a/share/examples/etc/make.conf +++ b/share/examples/etc/make.conf @@ -239,13 +239,11 @@ # # with SASLv1: # SENDMAIL_CFLAGS=-I/usr/local/include/sasl1 -DSASL -# SENDMAIL_LDFLAGS=-L/usr/local/lib -# SENDMAIL_LDADD=-lsasl +# SENDMAIL_LDADD=/usr/local/lib/libsasl.so # # with SASLv2: # SENDMAIL_CFLAGS=-I/usr/local/include -DSASL=2 -# SENDMAIL_LDFLAGS=-L/usr/local/lib -# SENDMAIL_LDADD=-lsasl2 +# SENDMAIL_LDADD=/usr/local/lib/libsasl2.so # # Note: If you are using Cyrus SASL with other applications which require # access to the sasldb file, you should add the following to your From fe4f491461580265714d24c4dde1ee80c9618f75 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Sat, 1 Aug 2020 06:31:58 +0000 Subject: [PATCH 004/141] capsicum: move global caps to caprights.h .. for easier inclusion --- sys/sys/caprights.h | 48 +++++++++++++++++++++++++++++++++++++++++++++ sys/sys/capsicum.h | 45 ------------------------------------------ 2 files changed, 48 insertions(+), 45 deletions(-) diff --git a/sys/sys/caprights.h b/sys/sys/caprights.h index 8698483ce22c..9f396a0df553 100644 --- a/sys/sys/caprights.h +++ b/sys/sys/caprights.h @@ -60,4 +60,52 @@ struct cap_rights { typedef struct cap_rights cap_rights_t; #endif +#ifdef _KERNEL +extern cap_rights_t cap_accept_rights; +extern cap_rights_t cap_bind_rights; +extern cap_rights_t cap_connect_rights; +extern cap_rights_t cap_event_rights; +extern cap_rights_t cap_fchdir_rights; +extern cap_rights_t cap_fchflags_rights; +extern cap_rights_t cap_fchmod_rights; +extern cap_rights_t cap_fchown_rights; +extern cap_rights_t cap_fcntl_rights; +extern cap_rights_t cap_fexecve_rights; +extern cap_rights_t cap_flock_rights; +extern cap_rights_t cap_fpathconf_rights; +extern cap_rights_t cap_fstat_rights; +extern cap_rights_t cap_fstatfs_rights; +extern cap_rights_t cap_fsync_rights; +extern cap_rights_t cap_ftruncate_rights; +extern cap_rights_t cap_futimes_rights; +extern cap_rights_t cap_getpeername_rights; +extern cap_rights_t cap_getsockopt_rights; +extern cap_rights_t cap_getsockname_rights; +extern cap_rights_t cap_ioctl_rights; +extern cap_rights_t cap_linkat_source_rights; +extern cap_rights_t cap_linkat_target_rights; +extern cap_rights_t cap_listen_rights; +extern cap_rights_t cap_mkdirat_rights; +extern cap_rights_t cap_mkfifoat_rights; +extern cap_rights_t cap_mknodat_rights; +extern cap_rights_t cap_mmap_rights; +extern cap_rights_t cap_no_rights; +extern cap_rights_t cap_pdgetpid_rights; +extern cap_rights_t cap_pdkill_rights; +extern cap_rights_t cap_pread_rights; +extern cap_rights_t cap_pwrite_rights; +extern cap_rights_t cap_read_rights; +extern cap_rights_t cap_recv_rights; +extern cap_rights_t cap_renameat_source_rights; +extern cap_rights_t cap_renameat_target_rights; +extern cap_rights_t cap_seek_rights; +extern cap_rights_t cap_send_rights; +extern cap_rights_t cap_send_connect_rights; +extern cap_rights_t cap_setsockopt_rights; +extern cap_rights_t cap_shutdown_rights; +extern cap_rights_t cap_symlinkat_rights; +extern cap_rights_t cap_unlinkat_rights; +extern cap_rights_t cap_write_rights; +#endif + #endif /* !_SYS_CAPRIGHTS_H_ */ diff --git a/sys/sys/capsicum.h b/sys/sys/capsicum.h index bc9a2fe8053c..af596cd179f4 100644 --- a/sys/sys/capsicum.h +++ b/sys/sys/capsicum.h @@ -419,51 +419,6 @@ __END_DECLS #ifdef _KERNEL #include -extern cap_rights_t cap_accept_rights; -extern cap_rights_t cap_bind_rights; -extern cap_rights_t cap_connect_rights; -extern cap_rights_t cap_event_rights; -extern cap_rights_t cap_fchdir_rights; -extern cap_rights_t cap_fchflags_rights; -extern cap_rights_t cap_fchmod_rights; -extern cap_rights_t cap_fchown_rights; -extern cap_rights_t cap_fcntl_rights; -extern cap_rights_t cap_fexecve_rights; -extern cap_rights_t cap_flock_rights; -extern cap_rights_t cap_fpathconf_rights; -extern cap_rights_t cap_fstat_rights; -extern cap_rights_t cap_fstatfs_rights; -extern cap_rights_t cap_fsync_rights; -extern cap_rights_t cap_ftruncate_rights; -extern cap_rights_t cap_futimes_rights; -extern cap_rights_t cap_getpeername_rights; -extern cap_rights_t cap_getsockopt_rights; -extern cap_rights_t cap_getsockname_rights; -extern cap_rights_t cap_ioctl_rights; -extern cap_rights_t cap_linkat_source_rights; -extern cap_rights_t cap_linkat_target_rights; -extern cap_rights_t cap_listen_rights; -extern cap_rights_t cap_mkdirat_rights; -extern cap_rights_t cap_mkfifoat_rights; -extern cap_rights_t cap_mknodat_rights; -extern cap_rights_t cap_mmap_rights; -extern cap_rights_t cap_no_rights; -extern cap_rights_t cap_pdgetpid_rights; -extern cap_rights_t cap_pdkill_rights; -extern cap_rights_t cap_pread_rights; -extern cap_rights_t cap_pwrite_rights; -extern cap_rights_t cap_read_rights; -extern cap_rights_t cap_recv_rights; -extern cap_rights_t cap_renameat_source_rights; -extern cap_rights_t cap_renameat_target_rights; -extern cap_rights_t cap_seek_rights; -extern cap_rights_t cap_send_rights; -extern cap_rights_t cap_send_connect_rights; -extern cap_rights_t cap_setsockopt_rights; -extern cap_rights_t cap_shutdown_rights; -extern cap_rights_t cap_symlinkat_rights; -extern cap_rights_t cap_unlinkat_rights; -extern cap_rights_t cap_write_rights; #define IN_CAPABILITY_MODE(td) (((td)->td_ucred->cr_flags & CRED_FLAG_CAPMODE) != 0) From 21c162605b1d937704cbabcf6168e647132af538 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Sat, 1 Aug 2020 06:32:25 +0000 Subject: [PATCH 005/141] vfs: make rights mandatory for NDINIT_ALL --- sys/kern/vfs_lookup.c | 6 ++---- sys/sys/namei.h | 6 +++--- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/sys/kern/vfs_lookup.c b/sys/kern/vfs_lookup.c index 7e90d86bb6a1..2e06319a25b3 100644 --- a/sys/kern/vfs_lookup.c +++ b/sys/kern/vfs_lookup.c @@ -1371,6 +1371,7 @@ NDINIT_ALL(struct nameidata *ndp, u_long op, u_long flags, enum uio_seg segflg, struct thread *td) { + MPASS(rightsp != NULL); ndp->ni_cnd.cn_nameiop = op; ndp->ni_cnd.cn_flags = flags; ndp->ni_segflg = segflg; @@ -1380,10 +1381,7 @@ NDINIT_ALL(struct nameidata *ndp, u_long op, u_long flags, enum uio_seg segflg, ndp->ni_resflags = 0; filecaps_init(&ndp->ni_filecaps); ndp->ni_cnd.cn_thread = td; - if (rightsp != NULL) - ndp->ni_rightsneeded = *rightsp; - else - cap_rights_init_zero(&ndp->ni_rightsneeded); + ndp->ni_rightsneeded = *rightsp; } /* diff --git a/sys/sys/namei.h b/sys/sys/namei.h index 0950b0a8f583..cd9687282af9 100644 --- a/sys/sys/namei.h +++ b/sys/sys/namei.h @@ -188,13 +188,13 @@ int cache_fplookup(struct nameidata *ndp, enum cache_fpl_status *status, * Initialization of a nameidata structure. */ #define NDINIT(ndp, op, flags, segflg, namep, td) \ - NDINIT_ALL(ndp, op, flags, segflg, namep, AT_FDCWD, NULL, 0, td) + NDINIT_ALL(ndp, op, flags, segflg, namep, AT_FDCWD, NULL, &cap_no_rights, td) #define NDINIT_AT(ndp, op, flags, segflg, namep, dirfd, td) \ - NDINIT_ALL(ndp, op, flags, segflg, namep, dirfd, NULL, 0, td) + NDINIT_ALL(ndp, op, flags, segflg, namep, dirfd, NULL, &cap_no_rights, td) #define NDINIT_ATRIGHTS(ndp, op, flags, segflg, namep, dirfd, rightsp, td) \ NDINIT_ALL(ndp, op, flags, segflg, namep, dirfd, NULL, rightsp, td) #define NDINIT_ATVP(ndp, op, flags, segflg, namep, vp, td) \ - NDINIT_ALL(ndp, op, flags, segflg, namep, AT_FDCWD, vp, 0, td) + NDINIT_ALL(ndp, op, flags, segflg, namep, AT_FDCWD, vp, &cap_no_rights, td) void NDINIT_ALL(struct nameidata *ndp, u_long op, u_long flags, enum uio_seg segflg, const char *namep, int dirfd, struct vnode *startdir, From 14576629bb22f3d138eefb61cf9b1f76d718846a Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Sat, 1 Aug 2020 06:33:11 +0000 Subject: [PATCH 006/141] vfs: convert ni_rigthsneeded to a pointer Shaves 8 bytes of struct nameidata on 64-bit platforms. --- sys/kern/vfs_lookup.c | 6 +++--- sys/sys/namei.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/sys/kern/vfs_lookup.c b/sys/kern/vfs_lookup.c index 2e06319a25b3..fd6f3189e253 100644 --- a/sys/kern/vfs_lookup.c +++ b/sys/kern/vfs_lookup.c @@ -347,7 +347,7 @@ namei_setup(struct nameidata *ndp, struct vnode **dpp, struct pwd **pwdp) *dpp = pwd->pwd_cdir; vrefact(*dpp); } else { - rights = ndp->ni_rightsneeded; + rights = *ndp->ni_rightsneeded; cap_rights_set_one(&rights, CAP_LOOKUP); if (cnp->cn_flags & AUDITVNODE1) @@ -403,7 +403,7 @@ namei_setup(struct nameidata *ndp, struct vnode **dpp, struct pwd **pwdp) ndp->ni_beneath_latch = pwd->pwd_cdir; vrefact(ndp->ni_beneath_latch); } else { - rights = ndp->ni_rightsneeded; + rights = *ndp->ni_rightsneeded; cap_rights_set_one(&rights, CAP_LOOKUP); error = fgetvp_rights(td, ndp->ni_dirfd, &rights, &dirfd_caps, &ndp->ni_beneath_latch); @@ -1381,7 +1381,7 @@ NDINIT_ALL(struct nameidata *ndp, u_long op, u_long flags, enum uio_seg segflg, ndp->ni_resflags = 0; filecaps_init(&ndp->ni_filecaps); ndp->ni_cnd.cn_thread = td; - ndp->ni_rightsneeded = *rightsp; + ndp->ni_rightsneeded = rightsp; } /* diff --git a/sys/sys/namei.h b/sys/sys/namei.h index cd9687282af9..d65b0bc66026 100644 --- a/sys/sys/namei.h +++ b/sys/sys/namei.h @@ -69,7 +69,7 @@ struct nameidata { */ const char *ni_dirp; /* pathname pointer */ enum uio_seg ni_segflg; /* location of pathname */ - cap_rights_t ni_rightsneeded; /* rights required to look up vnode */ + cap_rights_t *ni_rightsneeded; /* rights required to look up vnode */ /* * Arguments to lookup. */ From 85cf316172d0290ed94738fffd8c6868eeb3d634 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Sat, 1 Aug 2020 06:33:38 +0000 Subject: [PATCH 007/141] vfs: inline NDINIT_ALL The routine takes more than 6 arguments, which on amd64 means some of them have to be passed through the stack. --- sys/kern/vfs_lookup.c | 19 ------------------- sys/sys/namei.h | 19 ++++++++++++++++--- 2 files changed, 16 insertions(+), 22 deletions(-) diff --git a/sys/kern/vfs_lookup.c b/sys/kern/vfs_lookup.c index fd6f3189e253..2b37bda9ee3b 100644 --- a/sys/kern/vfs_lookup.c +++ b/sys/kern/vfs_lookup.c @@ -1365,25 +1365,6 @@ relookup(struct vnode *dvp, struct vnode **vpp, struct componentname *cnp) return (error); } -void -NDINIT_ALL(struct nameidata *ndp, u_long op, u_long flags, enum uio_seg segflg, - const char *namep, int dirfd, struct vnode *startdir, cap_rights_t *rightsp, - struct thread *td) -{ - - MPASS(rightsp != NULL); - ndp->ni_cnd.cn_nameiop = op; - ndp->ni_cnd.cn_flags = flags; - ndp->ni_segflg = segflg; - ndp->ni_dirp = namep; - ndp->ni_dirfd = dirfd; - ndp->ni_startdir = startdir; - ndp->ni_resflags = 0; - filecaps_init(&ndp->ni_filecaps); - ndp->ni_cnd.cn_thread = td; - ndp->ni_rightsneeded = rightsp; -} - /* * Free data allocated by namei(); see namei(9) for details. */ diff --git a/sys/sys/namei.h b/sys/sys/namei.h index d65b0bc66026..05a5239b36e3 100644 --- a/sys/sys/namei.h +++ b/sys/sys/namei.h @@ -196,9 +196,22 @@ int cache_fplookup(struct nameidata *ndp, enum cache_fpl_status *status, #define NDINIT_ATVP(ndp, op, flags, segflg, namep, vp, td) \ NDINIT_ALL(ndp, op, flags, segflg, namep, AT_FDCWD, vp, &cap_no_rights, td) -void NDINIT_ALL(struct nameidata *ndp, u_long op, u_long flags, - enum uio_seg segflg, const char *namep, int dirfd, struct vnode *startdir, - cap_rights_t *rightsp, struct thread *td); +#define NDINIT_ALL(ndp, op, flags, segflg, namep, dirfd, startdir, rightsp, td) \ +do { \ + struct nameidata *_ndp = (ndp); \ + cap_rights_t *_rightsp = (rightsp); \ + MPASS(_rightsp != NULL); \ + _ndp->ni_cnd.cn_nameiop = op; \ + _ndp->ni_cnd.cn_flags = flags; \ + _ndp->ni_segflg = segflg; \ + _ndp->ni_dirp = namep; \ + _ndp->ni_dirfd = dirfd; \ + _ndp->ni_startdir = startdir; \ + _ndp->ni_resflags = 0; \ + filecaps_init(&_ndp->ni_filecaps); \ + _ndp->ni_cnd.cn_thread = td; \ + _ndp->ni_rightsneeded = _rightsp; \ +} while (0) #define NDF_NO_DVP_RELE 0x00000001 #define NDF_NO_DVP_UNLOCK 0x00000002 From 5a3944334c65b90696c3f962efb7f48e3584b5b7 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Sat, 1 Aug 2020 06:34:18 +0000 Subject: [PATCH 008/141] cache: mark climb_mount as __noinline --- sys/kern/vfs_cache.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 6eff71606ac9..fe4739d165e4 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -3448,7 +3448,7 @@ cache_fplookup_mp_supported(struct mount *mp) * By the end of successful walk we are guaranteed the reached state was * indeed present at least at some point which matches the regular lookup. */ -static int +static int __noinline cache_fplookup_climb_mount(struct cache_fpl *fpl) { struct mount *mp, *prev_mp; @@ -3457,9 +3457,8 @@ cache_fplookup_climb_mount(struct cache_fpl *fpl) vp = fpl->tvp; vp_seqc = fpl->tvp_seqc; - if (vp->v_type != VDIR) - return (0); + VNPASS(vp->v_type == VDIR || vp->v_type == VBAD, vp); mp = atomic_load_ptr(&vp->v_mountedhere); if (mp == NULL) return (0); @@ -3503,6 +3502,26 @@ cache_fplookup_climb_mount(struct cache_fpl *fpl) return (0); } +static bool +cache_fplookup_need_climb_mount(struct cache_fpl *fpl) +{ + struct mount *mp; + struct vnode *vp; + + vp = fpl->tvp; + + /* + * Hack: while this is a union, the pointer tends to be NULL so save on + * a branch. + */ + mp = atomic_load_ptr(&vp->v_mountedhere); + if (mp == NULL) + return (false); + if (vp->v_type == VDIR) + return (true); + return (false); +} + /* * Parse the path. * @@ -3689,9 +3708,11 @@ cache_fplookup_impl(struct vnode *dvp, struct cache_fpl *fpl) VNPASS(!seqc_in_modify(fpl->tvp_seqc), fpl->tvp); - error = cache_fplookup_climb_mount(fpl); - if (__predict_false(error != 0)) { - break; + if (cache_fplookup_need_climb_mount(fpl)) { + error = cache_fplookup_climb_mount(fpl); + if (__predict_false(error != 0)) { + break; + } } VNPASS(!seqc_in_modify(fpl->tvp_seqc), fpl->tvp); From 8a7ec170952a35f12b89d56b83dde95a52fb56e9 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Sat, 1 Aug 2020 06:35:18 +0000 Subject: [PATCH 009/141] cache: reshuffle struct cache_fpl and nameidata_saved Shaves 16 bytes. --- sys/kern/vfs_cache.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index fe4739d165e4..72cf7522ed48 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -2890,24 +2890,24 @@ cache_fpl_handle_root(struct nameidata *ndp, struct vnode **dpp) * need restoring in case fast path lookup fails. */ struct nameidata_saved { - int cn_flags; long cn_namelen; char *cn_nameptr; size_t ni_pathlen; + int cn_flags; }; struct cache_fpl { - int line; - enum cache_fpl_status status; - bool in_smr; struct nameidata *ndp; - struct nameidata_saved snd; struct componentname *cnp; - struct vnode *dvp; - seqc_t dvp_seqc; - struct vnode *tvp; - seqc_t tvp_seqc; struct pwd *pwd; + struct vnode *dvp; + struct vnode *tvp; + seqc_t dvp_seqc; + seqc_t tvp_seqc; + struct nameidata_saved snd; + int line; + enum cache_fpl_status status:8; + bool in_smr; }; static void From d53c862742a86e0ac160414bf10620846c0ea7a4 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Sat, 1 Aug 2020 06:37:26 +0000 Subject: [PATCH 010/141] Bump __FreeBSD_version after making rights mandatory for NDINIT_ALL --- sys/sys/param.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/sys/param.h b/sys/sys/param.h index e196d4038feb..074ad41645c4 100644 --- a/sys/sys/param.h +++ b/sys/sys/param.h @@ -60,7 +60,7 @@ * in the range 5 to 9. */ #undef __FreeBSD_version -#define __FreeBSD_version 1300102 /* Master, propagated to newvers */ +#define __FreeBSD_version 1300103 /* Master, propagated to newvers */ /* * __FreeBSD_kernel__ indicates that this system uses the kernel of FreeBSD, From 208fb7e5cf3154ed506a7ed8d4d4b1b6e100ce26 Mon Sep 17 00:00:00 2001 From: Michal Meloun Date: Sat, 1 Aug 2020 09:06:16 +0000 Subject: [PATCH 011/141] Add missing dependency for cpsw module. Reported by: mjg MFC with: r363700 --- sys/modules/cpsw/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/modules/cpsw/Makefile b/sys/modules/cpsw/Makefile index 130a659a11b9..de6e57c37466 100644 --- a/sys/modules/cpsw/Makefile +++ b/sys/modules/cpsw/Makefile @@ -3,6 +3,6 @@ .PATH: ${SRCTOP}/sys/arm/ti/cpsw KMOD= if_cpsw -SRCS= if_cpsw.c device_if.h bus_if.h ofw_bus_if.h miibus_if.h +SRCS= if_cpsw.c device_if.h bus_if.h ofw_bus_if.h miibus_if.h syscon_if.h .include From acdc9154615de09e89a6469fbb8af281c334e044 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Sat, 1 Aug 2020 09:40:19 +0000 Subject: [PATCH 012/141] Fix TX csum handling in if_mvneta The mvneta device requires MVNETA_TX_CMD_L4_CHECKSUM_NONE bit to be set in the tx descriptor is checksum not required. However, mvneta_tx_set_csumflag() is not setting this flag currently, causing the hardware to randomly corrupt IP header during transmission. This affects injected IPv4 packets that skips kernel IP stack processing (e.g. DHCP), as well as all IPv6 packets, since the driver currently does not offload csum for IPv6. The fix is to remove all the early return paths from mvneta_tx_set_csumflag() which do not set the MVNETA_TX_CMD_L4_CHECKSUM_NONE flag. PR: 248306 Submitted by: Mike Cui Reported by: Mike Cui --- sys/dev/neta/if_mvneta.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/sys/dev/neta/if_mvneta.c b/sys/dev/neta/if_mvneta.c index fbf7ade862c4..c5cdf8bcb9ee 100644 --- a/sys/dev/neta/if_mvneta.c +++ b/sys/dev/neta/if_mvneta.c @@ -2828,18 +2828,15 @@ mvneta_tx_set_csumflag(struct ifnet *ifp, csum_flags = ifp->if_hwassist & m->m_pkthdr.csum_flags; eh = mtod(m, struct ether_header *); - if (csum_flags == 0) - return; - switch (ntohs(eh->ether_type)) { case ETHERTYPE_IP: ipoff = ETHER_HDR_LEN; break; - case ETHERTYPE_IPV6: - return; case ETHERTYPE_VLAN: ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; break; + default: + csum_flags = 0; } if (__predict_true(csum_flags & (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP))) { From 936c24fabaf5f532b16489d03e88350c3cee4cc7 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Sat, 1 Aug 2020 16:02:32 +0000 Subject: [PATCH 013/141] cred: add more asserts for td_realucred == td_ucred --- sys/kern/kern_prot.c | 4 +++- sys/kern/kern_thread.c | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/sys/kern/kern_prot.c b/sys/kern/kern_prot.c index 3dbf3e19acbe..20995223b6d2 100644 --- a/sys/kern/kern_prot.c +++ b/sys/kern/kern_prot.c @@ -1881,7 +1881,8 @@ crunuse(struct thread *td) { struct ucred *cr, *crold; - cr = td->td_ucred; + MPASS(td->td_realucred == td->td_ucred); + cr = td->td_realucred; mtx_lock(&cr->cr_mtx); cr->cr_ref += td->td_ucredref; td->td_ucredref = 0; @@ -1897,6 +1898,7 @@ crunuse(struct thread *td) crold = NULL; } mtx_unlock(&cr->cr_mtx); + td->td_realucred = NULL; return (crold); } diff --git a/sys/kern/kern_thread.c b/sys/kern/kern_thread.c index 8216c31ef0c0..37120a06d1e2 100644 --- a/sys/kern/kern_thread.c +++ b/sys/kern/kern_thread.c @@ -543,6 +543,7 @@ thread_exit(void) (long)p->p_pid, td->td_name); SDT_PROBE0(proc, , , lwp__exit); KASSERT(TAILQ_EMPTY(&td->td_sigqueue.sq_list), ("signal pending")); + MPASS(td->td_realucred == td->td_ucred); /* * drop FPU & debug register state storage, or any other From 9da903e5d3fa686b67df0c8d460fcf3ca9444172 Mon Sep 17 00:00:00 2001 From: Conrad Meyer Date: Sun, 2 Aug 2020 16:34:27 +0000 Subject: [PATCH 014/141] Unlocked getblk: Fix new false-positive assertion A free buf's lock may be held (temporarily) due to unlocked lookup, so buf_alloc() must acquire it without LK_NOWAIT. The unlocked getblk path should unlock it promptly once it realizes the identity does not match the buffer it was searching for. Reported by: gallatin Reviewed by: kib Tested by: pho X-MFC-With: r363482 Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D25914 --- sys/kern/vfs_bio.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/sys/kern/vfs_bio.c b/sys/kern/vfs_bio.c index 524554cdd48f..adc44082d972 100644 --- a/sys/kern/vfs_bio.c +++ b/sys/kern/vfs_bio.c @@ -1637,7 +1637,7 @@ static struct buf * buf_alloc(struct bufdomain *bd) { struct buf *bp; - int freebufs; + int freebufs, error; /* * We can only run out of bufs in the buf zone if the average buf @@ -1660,8 +1660,10 @@ buf_alloc(struct bufdomain *bd) if (freebufs == bd->bd_lofreebuffers) bufspace_daemon_wakeup(bd); - if (BUF_LOCK(bp, LK_EXCLUSIVE | LK_NOWAIT, NULL) != 0) - panic("getnewbuf_empty: Locked buf %p on free queue.", bp); + error = BUF_LOCK(bp, LK_EXCLUSIVE, NULL); + KASSERT(error == 0, ("%s: BUF_LOCK on free buf %p: %d.", __func__, bp, + error)); + (void)error; KASSERT(bp->b_vp == NULL, ("bp: %p still has vnode %p.", bp, bp->b_vp)); From ea27bce3361c81978292e5596f791ef6e4e64e3e Mon Sep 17 00:00:00 2001 From: Mateusz Piotrowski <0mp@FreeBSD.org> Date: Sun, 2 Aug 2020 16:41:36 +0000 Subject: [PATCH 015/141] Document automatic handling of font height for BDF files PR: 248395 Submitted by: Dmitry Wagin Reviewed by: bcr, emaste, tsoome Differential Revision: https://reviews.freebsd.org/D25907 --- usr.bin/vtfontcvt/vtfontcvt.8 | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/usr.bin/vtfontcvt/vtfontcvt.8 b/usr.bin/vtfontcvt/vtfontcvt.8 index e585220d5dfa..451f8134181b 100644 --- a/usr.bin/vtfontcvt/vtfontcvt.8 +++ b/usr.bin/vtfontcvt/vtfontcvt.8 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd Mar 10, 2020 +.Dd August 2, 2020 .Dt VTFONTCVT 8 .Os .Sh NAME @@ -63,7 +63,7 @@ file. .It Fl h Ar height Set font height. The default is 16. -Font height is set automatically for HEX files that have a +Font height is set automatically for BDF files and for HEX files that have a .Ql # Height: Ar height comment before any font data. .It Fl n @@ -75,7 +75,7 @@ Display verbose statistics about the converted font. .It Fl w Ar width Set font width. The default is 8. -Font width is set automatically for HEX files that have a +Font width is set automatically for BDF files and for HEX files that have a .Ql # Width: Ar width comment before any font data. .El From c7b00f0071ae5454acfe9863c46c33539d536825 Mon Sep 17 00:00:00 2001 From: Mateusz Piotrowski <0mp@FreeBSD.org> Date: Sun, 2 Aug 2020 16:59:14 +0000 Subject: [PATCH 016/141] core(5) appeared in Version 1 AT&T UNIX Based on the scans of manual pages available at https://www.bell-labs.com/usr/dmr/www/man51.pdf, which are a part of the following collection: https://www.bell-labs.com/usr/dmr/www/1stEdman.html. Obtained from: NetBSD Differential Revision: https://reviews.freebsd.org/D25849 --- share/man/man5/core.5 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/share/man/man5/core.5 b/share/man/man5/core.5 index c7449637b910..500da31a310c 100644 --- a/share/man/man5/core.5 +++ b/share/man/man5/core.5 @@ -28,7 +28,7 @@ .\" @(#)core.5 8.3 (Berkeley) 12/11/93 .\" $FreeBSD$ .\" -.Dd February 13, 2018 +.Dd August 2, 2020 .Dt CORE 5 .Os .Sh NAME @@ -171,4 +171,4 @@ command can be used: A .Nm file format appeared in -.At v6 . +.At v1 . From 838984de32be2b16354523d62e33a751ad2c519d Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Sun, 2 Aug 2020 19:42:06 +0000 Subject: [PATCH 017/141] vfs: move namecache initialisation into cache_vnode_init --- sys/kern/vfs_cache.c | 9 +++++++++ sys/kern/vfs_subr.c | 3 +-- sys/sys/vnode.h | 1 + 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 72cf7522ed48..00215fc014cd 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -2070,6 +2070,15 @@ nchinit(void *dummy __unused) } SYSINIT(vfs, SI_SUB_VFS, SI_ORDER_SECOND, nchinit, NULL); +void +cache_vnode_init(struct vnode *vp) +{ + + LIST_INIT(&vp->v_cache_src); + TAILQ_INIT(&vp->v_cache_dst); + vp->v_cache_dd = NULL; +} + void cache_changesize(u_long newmaxvnodes) { diff --git a/sys/kern/vfs_subr.c b/sys/kern/vfs_subr.c index d7a69b49d7f0..a34f83c09860 100644 --- a/sys/kern/vfs_subr.c +++ b/sys/kern/vfs_subr.c @@ -563,8 +563,7 @@ vnode_init(void *mem, int size, int flags) /* * Initialize namecache. */ - LIST_INIT(&vp->v_cache_src); - TAILQ_INIT(&vp->v_cache_dst); + cache_vnode_init(vp); /* * Initialize rangelocks. */ diff --git a/sys/sys/vnode.h b/sys/sys/vnode.h index 3a83ea5af6e1..983e4ac3a531 100644 --- a/sys/sys/vnode.h +++ b/sys/sys/vnode.h @@ -635,6 +635,7 @@ void cache_enter_time(struct vnode *dvp, struct vnode *vp, struct timespec *dtsp); int cache_lookup(struct vnode *dvp, struct vnode **vpp, struct componentname *cnp, struct timespec *tsp, int *ticksp); +void cache_vnode_init(struct vnode *vp); void cache_purge(struct vnode *vp); void cache_purge_negative(struct vnode *vp); void cache_purgevfs(struct mount *mp, bool force); From b145e389342e51220525bb8fa63e60a48f91011b Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Sun, 2 Aug 2020 20:00:43 +0000 Subject: [PATCH 018/141] vfs: shorten v_iflag and v_vflag While here renumber VI_* flags to remove the gaps. Reviewed by: kib Differential Revision: https://reviews.freebsd.org/D25921 --- sys/sys/vnode.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/sys/sys/vnode.h b/sys/sys/vnode.h index 983e4ac3a531..bed5c0f4086f 100644 --- a/sys/sys/vnode.h +++ b/sys/sys/vnode.h @@ -107,6 +107,7 @@ struct vnode { enum vtype v_type:8; /* u vnode type */ short v_irflag; /* i frequently read flags */ seqc_t v_seqc; /* i modification count */ + uint32_t v_nchash; /* u namecache hash */ struct vop_vector *v_op; /* u vnode operations vector */ void *v_data; /* u private data for fs */ @@ -171,8 +172,8 @@ struct vnode { u_int v_holdcnt; /* I prevents recycling. */ u_int v_usecount; /* I ref count of users */ - u_int v_iflag; /* i vnode flags (see below) */ - u_int v_vflag; /* v vnode flags */ + u_short v_iflag; /* i vnode flags (see below) */ + u_short v_vflag; /* v vnode flags */ u_short v_mflag; /* l mnt-specific vnode flags */ short v_dbatchcpu; /* i LRU requeue deferral batch */ int v_writecount; /* I ref count of writers or @@ -245,10 +246,10 @@ struct xvnode { #define VIRF_DOOMED 0x0001 /* This vnode is being recycled */ #define VI_TEXT_REF 0x0001 /* Text ref grabbed use ref */ -#define VI_MOUNT 0x0020 /* Mount in progress */ -#define VI_DOINGINACT 0x0800 /* VOP_INACTIVE is in progress */ -#define VI_OWEINACT 0x1000 /* Need to call inactive */ -#define VI_DEFINACT 0x2000 /* deferred inactive */ +#define VI_MOUNT 0x0002 /* Mount in progress */ +#define VI_DOINGINACT 0x0004 /* VOP_INACTIVE is in progress */ +#define VI_OWEINACT 0x0008 /* Need to call inactive */ +#define VI_DEFINACT 0x0010 /* deferred inactive */ #define VV_ROOT 0x0001 /* root of its filesystem */ #define VV_ISTTY 0x0002 /* vnode represents a tty */ From 7ad2f1105ea47a41a1a3fe2a6a8193f208e3d206 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Sun, 2 Aug 2020 20:02:06 +0000 Subject: [PATCH 019/141] vfs: store precomputed namecache hash in the vnode This significantly speeds up path lookup, Cascade Lake doing access(2) on ufs on /usr/obj/usr/src/amd64.amd64/sys/GENERIC/vnode_if.c, ops/s: before: 2535298 after: 2797621 Over +10%. The reversed order of computation here does not seem to matter for hash distribution. Reviewed by: kib Differential Revision: https://reviews.freebsd.org/D25921 --- sys/kern/vfs_cache.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 00215fc014cd..24638d39ee18 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -490,14 +490,22 @@ cache_assert_vnode_locked(struct vnode *vp) cache_assert_vlp_locked(vlp); } +/* + * TODO: With the value stored we can do better than computing the hash based + * on the address and the choice of FNV should also be revisisted. + */ +static void +cache_prehash(struct vnode *vp) +{ + + vp->v_nchash = fnv_32_buf(&vp, sizeof(vp), FNV1_32_INIT); +} + static uint32_t cache_get_hash(char *name, u_char len, struct vnode *dvp) { - uint32_t hash; - hash = fnv_32_buf(name, len, FNV1_32_INIT); - hash = fnv_32_buf(&dvp, sizeof(dvp), hash); - return (hash); + return (fnv_32_buf(name, len, dvp->v_nchash)); } static inline struct rwlock * @@ -2077,6 +2085,7 @@ cache_vnode_init(struct vnode *vp) LIST_INIT(&vp->v_cache_src); TAILQ_INIT(&vp->v_cache_dst); vp->v_cache_dd = NULL; + cache_prehash(vp); } void From 9fce5c4b3ce8580bb441923d0174df797f74a860 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Sun, 2 Aug 2020 20:03:23 +0000 Subject: [PATCH 020/141] Bump __FreeBSD_version after vnode layout changes --- sys/sys/param.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/sys/param.h b/sys/sys/param.h index 074ad41645c4..cc2aae21f3ca 100644 --- a/sys/sys/param.h +++ b/sys/sys/param.h @@ -60,7 +60,7 @@ * in the range 5 to 9. */ #undef __FreeBSD_version -#define __FreeBSD_version 1300103 /* Master, propagated to newvers */ +#define __FreeBSD_version 1300104 /* Master, propagated to newvers */ /* * __FreeBSD_kernel__ indicates that this system uses the kernel of FreeBSD, From 4fdb1b227cf6853f31fb655bc3e327ae16e7f09b Mon Sep 17 00:00:00 2001 From: "Jason A. Harmening" Date: Sun, 2 Aug 2020 20:18:37 +0000 Subject: [PATCH 021/141] vt(4): CONS_HISTORY/CONS_CLRHIST should operate on issuing terminal Currently the CONS_HISTORY and CONS_CLRHIST ioctls modify the state of the active terminal instead of the terminal against which the ioctl was issued. Because of the way vidcontrol(1) works, these are the same in most cases. But a poorly-timed window switch can make them differ. This is reproducible by issuing e.g. 'vidcontrol -s 2 && vidcontrol -C' to switch from vty 1 to vty 2; teken will reset the cursor position on vty 1 but vt(4) will clear the history buffer of vty 2, producing an interesting state of affairs. Differential Revision: https://reviews.freebsd.org/D25564 --- sys/dev/vt/vt_core.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/sys/dev/vt/vt_core.c b/sys/dev/vt/vt_core.c index 5311a8bd6788..952dcbbbb6b9 100644 --- a/sys/dev/vt/vt_core.c +++ b/sys/dev/vt/vt_core.c @@ -454,7 +454,7 @@ vt_window_postswitch(struct vt_window *vw) return (0); } -/* vt_late_window_switch will done VT switching for regular case. */ +/* vt_late_window_switch will do VT switching for regular case. */ static int vt_late_window_switch(struct vt_window *vw) { @@ -2326,12 +2326,11 @@ vtterm_ioctl(struct terminal *tm, u_long cmd, caddr_t data, case CONS_HISTORY: if (*(int *)data < 0) return EINVAL; - if (*(int *)data != vd->vd_curwindow->vw_buf.vb_history_size) - vtbuf_sethistory_size(&vd->vd_curwindow->vw_buf, - *(int *)data); + if (*(int *)data != vw->vw_buf.vb_history_size) + vtbuf_sethistory_size(&vw->vw_buf, *(int *)data); return (0); case CONS_CLRHIST: - vtbuf_clearhistory(&vd->vd_curwindow->vw_buf); + vtbuf_clearhistory(&vw->vw_buf); /* * Invalidate the entire visible window; it is not guaranteed * that this operation will be immediately followed by a scroll @@ -2339,9 +2338,11 @@ vtterm_ioctl(struct terminal *tm, u_long cmd, caddr_t data, * to remain visible. */ VT_LOCK(vd); - vd->vd_flags |= VDF_INVALID; + if (vw == vd->vd_curwindow) { + vd->vd_flags |= VDF_INVALID; + vt_resume_flush_timer(vw, 0); + } VT_UNLOCK(vd); - vt_resume_flush_timer(vd->vd_curwindow, 0); return (0); case CONS_GET: /* XXX */ From 31e34625cafcb33789b7fd95fa6ab15ddf91b1d0 Mon Sep 17 00:00:00 2001 From: Andrew Turner Date: Mon, 3 Aug 2020 10:19:50 +0000 Subject: [PATCH 022/141] Handle Raspberry Pi 4 xhci firmware loading. The newer hardware revisions of the Raspberry Pi 4 removed the ability of the VIA VL805 xhci controller to load its own firmware. Instead the firmware must be installed at the appropriate time by the VideoCore coprocessor. Submitted by: Robert Crowston Differential Revision: https://reviews.freebsd.org/D25261 --- sys/arm/broadcom/bcm2835/bcm2835_mbox.c | 23 +- sys/arm/broadcom/bcm2835/bcm2835_mbox_prop.h | 18 ++ sys/arm/broadcom/bcm2835/bcm2838_xhci.c | 217 +++++++++++++++++++ sys/arm/broadcom/bcm2835/files.bcm283x | 1 + sys/conf/files.arm64 | 1 + sys/dev/usb/controller/xhci.h | 3 + sys/dev/usb/controller/xhci_pci.c | 12 +- 7 files changed, 266 insertions(+), 9 deletions(-) create mode 100644 sys/arm/broadcom/bcm2835/bcm2838_xhci.c diff --git a/sys/arm/broadcom/bcm2835/bcm2835_mbox.c b/sys/arm/broadcom/bcm2835/bcm2835_mbox.c index d722c7aae7a7..9d71399de861 100644 --- a/sys/arm/broadcom/bcm2835/bcm2835_mbox.c +++ b/sys/arm/broadcom/bcm2835/bcm2835_mbox.c @@ -397,10 +397,10 @@ int bcm2835_mbox_property(void *msg, size_t msg_size) { struct bcm_mbox_softc *sc; - struct msg_set_power_state *buf; bus_dma_tag_t msg_tag; bus_dmamap_t msg_map; bus_addr_t msg_phys; + char *buf; uint32_t reg; device_t mbox; int err; @@ -467,6 +467,26 @@ bcm2835_mbox_set_power_state(uint32_t device_id, boolean_t on) return (err); } +int +bcm2835_mbox_notify_xhci_reset(uint32_t pci_dev_addr) +{ + struct msg_notify_xhci_reset msg; + int err; + + memset(&msg, 0, sizeof(msg)); + msg.hdr.buf_size = sizeof(msg); + msg.hdr.code = BCM2835_MBOX_CODE_REQ; + msg.tag_hdr.tag = BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET; + msg.tag_hdr.val_buf_size = sizeof(msg.body); + msg.tag_hdr.val_len = sizeof(msg.body.req); + msg.body.req.pci_device_addr = pci_dev_addr; + msg.end_tag = 0; + + err = bcm2835_mbox_property(&msg, sizeof(msg)); + + return (err); +} + int bcm2835_mbox_get_clock_rate(uint32_t clock_id, uint32_t *hz) { @@ -572,3 +592,4 @@ bcm2835_mbox_fb_init(struct bcm2835_fb_config *fb) return (err); } + diff --git a/sys/arm/broadcom/bcm2835/bcm2835_mbox_prop.h b/sys/arm/broadcom/bcm2835/bcm2835_mbox_prop.h index 15f48aefa536..92496c5aae92 100644 --- a/sys/arm/broadcom/bcm2835/bcm2835_mbox_prop.h +++ b/sys/arm/broadcom/bcm2835/bcm2835_mbox_prop.h @@ -112,6 +112,24 @@ struct msg_set_power_state { /* Sets the power state for a given device */ int bcm2835_mbox_set_power_state(uint32_t, boolean_t); +#define BCM2835_MBOX_TAG_NOTIFY_XHCI_RESET 0x00030058 + +struct msg_notify_xhci_reset { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + uint32_t pci_device_addr; + } req; + struct { + } resp; + } body; + uint32_t end_tag; +}; + +/* Prompts the VideoCore processor to reload the xhci firmware. */ +int bcm2835_mbox_notify_xhci_reset(uint32_t); + #define BCM2835_MBOX_CLOCK_ID_EMMC 0x00000001 #define BCM2838_MBOX_CLOCK_ID_EMMC2 0x0000000c diff --git a/sys/arm/broadcom/bcm2835/bcm2838_xhci.c b/sys/arm/broadcom/bcm2835/bcm2838_xhci.c new file mode 100644 index 000000000000..29bc73691a47 --- /dev/null +++ b/sys/arm/broadcom/bcm2835/bcm2838_xhci.c @@ -0,0 +1,217 @@ +/*- + * SPDX-License-Identifier: ISC + * + * Copyright (c) 2020 Dr Robert Harvey Crowston + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * + * $FreeBSD$ + * + */ + +/* + * VIA VL805 controller on the Raspberry Pi 4. + * The VL805 is a generic xhci controller. However, in the newer hardware + * revisions of the Raspberry Pi 4, it is incapable of loading its own firmware. + * Instead, the VideoCore GPU must load the firmware into the controller at the + * appropriate time. This driver is a shim that pre-loads the firmware before + * handing control to the xhci generic driver. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#define VL805_FIRMWARE_REG 0x50 +#define PCIE_BUS_SHIFT 20 +#define PCIE_SLOT_SHIFT 15 +#define PCIE_FUNC_SHIFT 12 + +static int +bcm_xhci_probe(device_t dev) +{ + phandle_t root; + uint32_t device_id; + + device_id = pci_get_devid(dev); + if (device_id != 0x34831106) /* VIA VL805 USB 3.0 controller. */ + return (ENXIO); + + /* + * The VIA chip is not unique to the Pi, but we only want to use this + * driver if the SoC is a Raspberry Pi 4. Walk the device tree to + * discover if the system is a Pi 4. + */ + root = OF_finddevice("/"); + if (root == -1) + return (ENXIO); + if (!ofw_bus_node_is_compatible(root, "raspberrypi,4-model-b")) + return (ENXIO); + + /* + * On the Pi 4, the VIA chip with the firmware-loading limitation is + * soldered-on to a particular bus/slot/function. But, it's possible a + * user could desolder the VIA chip, replace it with a pci-pci bridge, + * then plug in a commodity VIA PCI-e card on the new bridge. In that + * case we don't want to try to load the firmware to a commodity + * expansion card. + */ + if (pci_get_bus(dev) != 1 || pci_get_slot(dev) != 0 || + pci_get_function(dev) != 0 ) + return (ENXIO); + + device_set_desc(dev, + "VL805 USB 3.0 controller (on the Raspberry Pi 4b)"); + + return (BUS_PROBE_SPECIFIC); +} + +static uint32_t +bcm_xhci_check_firmware(device_t dev, bool expect_loaded) +{ + uint32_t revision; + bool loaded; + + revision = pci_read_config(dev, VL805_FIRMWARE_REG, 4); + loaded = !(revision == 0 || revision == 0xffffffff); + + if (expect_loaded && !loaded) + device_printf(dev, "warning: xhci firmware not found.\n"); + else if (bootverbose && !loaded) + device_printf(dev, "note: xhci firmware not found.\n"); + else if (bootverbose) + device_printf(dev, + "note: xhci firmware detected; firmware is revision %x.\n", + revision); + + if (!loaded) + return 0; + + return (revision); +} + +static void +bcm_xhci_install_xhci_firmware(device_t dev) +{ + uint32_t revision, dev_addr; + int error; + + revision = bcm_xhci_check_firmware(dev, false); + if (revision > 0) { + /* + * With the pre-June 2020 boot firmware, it does not seem + * possible to reload already-installed xhci firmware. + */ + return; + } + + /* + * Notify the VideoCore gpu processor that it needs to reload the xhci + * firmware into the xhci controller. This needs to happen after the pci + * bridge topology is registered with the controller. + */ + if (bootverbose) + device_printf(dev, "note: installing xhci firmware.\n"); + + dev_addr = + pci_get_bus(dev) << PCIE_BUS_SHIFT | + pci_get_slot(dev) << PCIE_SLOT_SHIFT | + pci_get_function(dev) << PCIE_FUNC_SHIFT; + + error = bcm2835_mbox_notify_xhci_reset(dev_addr); + if (error) + device_printf(dev, + "warning: xhci firmware install failed (error %d).\n", + error); + + DELAY(1000); + bcm_xhci_check_firmware(dev, true); + + return; +} + +static int +bcm_xhci_attach(device_t dev) +{ + struct xhci_softc *sc; + int error; + + sc = device_get_softc(dev); + + bcm_xhci_install_xhci_firmware(dev); + + error = xhci_pci_attach(dev); + if (error) + return (error); + + /* 32 bit DMA is a limitation of the PCI-e controller, not the VL805. */ + sc->sc_bus.dma_bits = 32; + if (bootverbose) + device_printf(dev, "note: switched to 32-bit DMA.\n"); + + return (0); +} + +/* + * Device method table. + */ +static device_method_t bcm_xhci_methods[] = { + /* Device interface. */ + DEVMETHOD(device_probe, bcm_xhci_probe), + DEVMETHOD(device_attach, bcm_xhci_attach), +}; + +DEFINE_CLASS_1(bcm_xhci, bcm_xhci_driver, bcm_xhci_methods, + sizeof(struct xhci_softc), xhci_pci_driver); + +static devclass_t xhci_devclass; +DRIVER_MODULE(bcm_xhci, pci, bcm_xhci_driver, xhci_devclass, 0, 0); MODULE_DEPEND(bcm_xhci, usb, 1, 1, 1); + diff --git a/sys/arm/broadcom/bcm2835/files.bcm283x b/sys/arm/broadcom/bcm2835/files.bcm283x index d4faae8e338c..0af397566c17 100644 --- a/sys/arm/broadcom/bcm2835/files.bcm283x +++ b/sys/arm/broadcom/bcm2835/files.bcm283x @@ -19,6 +19,7 @@ arm/broadcom/bcm2835/bcm2835_vcbus.c standard arm/broadcom/bcm2835/bcm2835_vcio.c standard arm/broadcom/bcm2835/bcm2835_wdog.c standard arm/broadcom/bcm2835/bcm2838_pci.c optional pci +arm/broadcom/bcm2835/bcm2838_xhci.c optional xhci arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt dev/mbox/mbox_if.m standard diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64 index 44155655a7ba..e8a0cfc95f0d 100644 --- a/sys/conf/files.arm64 +++ b/sys/conf/files.arm64 @@ -107,6 +107,7 @@ arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt | soc_brcm_bc arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 | dwcotg fdt soc_brcm_bcm2838 arm/broadcom/bcm2835/bcm2838_pci.c optional soc_brcm_bcm2838 fdt pci +arm/broadcom/bcm2835/bcm2838_xhci.c optional soc_brcm_bcm2838 fdt pci xhci arm/freescale/vybrid/vf_i2c.c optional vf_i2c iicbus SOC_NXP_LS arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt arm/mv/a37x0_iic.c optional a37x0_iic iicbus fdt diff --git a/sys/dev/usb/controller/xhci.h b/sys/dev/usb/controller/xhci.h index 6bfd342e0620..c0427e0cf11f 100644 --- a/sys/dev/usb/controller/xhci.h +++ b/sys/dev/usb/controller/xhci.h @@ -544,5 +544,8 @@ usb_error_t xhci_init(struct xhci_softc *, device_t, uint8_t); usb_error_t xhci_start_controller(struct xhci_softc *); void xhci_interrupt(struct xhci_softc *); void xhci_uninit(struct xhci_softc *); +int xhci_pci_attach(device_t); + +DECLARE_CLASS(xhci_pci_driver); #endif /* _XHCI_H_ */ diff --git a/sys/dev/usb/controller/xhci_pci.c b/sys/dev/usb/controller/xhci_pci.c index 5c59d7c989dc..15677c23b785 100644 --- a/sys/dev/usb/controller/xhci_pci.c +++ b/sys/dev/usb/controller/xhci_pci.c @@ -63,7 +63,6 @@ __FBSDID("$FreeBSD$"); #include "usb_if.h" static device_probe_t xhci_pci_probe; -static device_attach_t xhci_pci_attach; static device_detach_t xhci_pci_detach; static usb_take_controller_t xhci_pci_take_controller; @@ -80,15 +79,12 @@ static device_method_t xhci_device_methods[] = { DEVMETHOD_END }; -static driver_t xhci_driver = { - .name = "xhci", - .methods = xhci_device_methods, - .size = sizeof(struct xhci_softc), -}; +DEFINE_CLASS_0(xhci, xhci_pci_driver, xhci_device_methods, + sizeof(struct xhci_softc)); static devclass_t xhci_devclass; -DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL); +DRIVER_MODULE(xhci, pci, xhci_pci_driver, xhci_devclass, NULL, NULL); MODULE_DEPEND(xhci, usb, 1, 1, 1); static const char * @@ -223,7 +219,7 @@ xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) return (0); } -static int +int xhci_pci_attach(device_t self) { struct xhci_softc *sc = device_get_softc(self); From 7393b267c6ceb3afd573e207587f49507154ead8 Mon Sep 17 00:00:00 2001 From: Kristof Provost Date: Mon, 3 Aug 2020 12:48:51 +0000 Subject: [PATCH 023/141] libc: Provide sub fp(s|g)etmask() implementations for RISC-V RISC-V doesn't support floating-point exceptions. RISC-V Instruction Set Manual: Volume I: User-Level ISA, 11.2 Floating-Point Control and Status Register: "As allowed by the standard, we do not support traps on floating-point exceptions in the base ISA, but instead require explicit checks of the flags in software. We considered adding branches controlled directly by the contents of the floating-point accrued exception flags, but ultimately chose to omit these instructions to keep the ISA simple." We still need these functions, because some applications (notably Perl) call them, but we cannot provide a meaningful implementation. Sponsored by: Axiado Differential Revision: https://reviews.freebsd.org/D25740 --- lib/libc/riscv/gen/Makefile.inc | 2 ++ lib/libc/riscv/gen/fpgetmask.c | 41 +++++++++++++++++++++++++ lib/libc/riscv/gen/fpsetmask.c | 53 +++++++++++++++++++++++++++++++++ sys/riscv/include/ieeefp.h | 1 + 4 files changed, 97 insertions(+) create mode 100644 lib/libc/riscv/gen/fpgetmask.c create mode 100644 lib/libc/riscv/gen/fpsetmask.c diff --git a/lib/libc/riscv/gen/Makefile.inc b/lib/libc/riscv/gen/Makefile.inc index 6380db6c265a..f13800829d7f 100644 --- a/lib/libc/riscv/gen/Makefile.inc +++ b/lib/libc/riscv/gen/Makefile.inc @@ -3,6 +3,8 @@ SRCS+= _ctx_start.S \ fabs.S \ flt_rounds.c \ + fpgetmask.c \ + fpsetmask.c \ infinity.c \ ldexp.c \ makecontext.c \ diff --git a/lib/libc/riscv/gen/fpgetmask.c b/lib/libc/riscv/gen/fpgetmask.c new file mode 100644 index 000000000000..f461cc2ba10e --- /dev/null +++ b/lib/libc/riscv/gen/fpgetmask.c @@ -0,0 +1,41 @@ +/*- + * Copyright (c) 2020 Axiado + * All rights reserved. + * + * This software was developed by Kristof Provost under + * sponsorship from Axiado. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include + +fp_except_t +fpgetmask(void) +{ + + return (0); +} diff --git a/lib/libc/riscv/gen/fpsetmask.c b/lib/libc/riscv/gen/fpsetmask.c new file mode 100644 index 000000000000..6eeac9de8bef --- /dev/null +++ b/lib/libc/riscv/gen/fpsetmask.c @@ -0,0 +1,53 @@ +/*- + * Copyright (c) 2020 Axiado + * All rights reserved. + * + * This software was developed by Kristof Provost under + * sponsorship from Axiado. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include + +/** + * RISC-V doesn't support floating-point exceptions: RISC-V Instruction Set + * Manual: Volume I: User-Level ISA, 11.2 Floating-Point Control and Status + * Register: "As allowed by the standard, we do not support traps on + * floating-point exceptions in the base ISA, but instead require explicit + * checks of the flags in software. We considered adding branches controlled + * directly by the contents of the floating-point accrued exception flags, but + * ultimately chose to omit these instructions to keep the ISA simple." + * + * We still need this function, because some applications (notably Perl) call + * it, but we cannot provide a meaningful implementation. + **/ +fp_except_t +fpsetmask(fp_except_t mask) +{ + + return (0); +} diff --git a/sys/riscv/include/ieeefp.h b/sys/riscv/include/ieeefp.h index f7d44f3a0daf..72a48f4f9b74 100644 --- a/sys/riscv/include/ieeefp.h +++ b/sys/riscv/include/ieeefp.h @@ -4,5 +4,6 @@ #define _MACHINE_IEEEFP_H_ /* TODO */ +typedef int fp_except_t; #endif /* _MACHINE_IEEEFP_H_ */ From 7dd966b1420cde0b9e4351f686622eb8c9741ec3 Mon Sep 17 00:00:00 2001 From: Li-Wen Hsu Date: Mon, 3 Aug 2020 12:51:14 +0000 Subject: [PATCH 024/141] Disable tests failing after r363679 PR: 248452 Sponsored by: The FreeBSD Foundation --- contrib/googletest/googletest/test/googletest-port-test.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/contrib/googletest/googletest/test/googletest-port-test.cc b/contrib/googletest/googletest/test/googletest-port-test.cc index 399316f95b63..0b68d72e75bc 100644 --- a/contrib/googletest/googletest/test/googletest-port-test.cc +++ b/contrib/googletest/googletest/test/googletest-port-test.cc @@ -403,6 +403,8 @@ typedef testing::Types< TYPED_TEST_CASE(RETest, StringTypes); // Tests RE's implicit constructors. +/* +https://bugs.freebsd.org/248452 TYPED_TEST(RETest, ImplicitConstructorWorks) { const RE empty(TypeParam("")); EXPECT_STREQ("", empty.pattern()); @@ -413,6 +415,7 @@ TYPED_TEST(RETest, ImplicitConstructorWorks) { const RE normal(TypeParam(".*(\\w+)")); EXPECT_STREQ(".*(\\w+)", normal.pattern()); } +*/ // Tests that RE's constructors reject invalid regular expressions. TYPED_TEST(RETest, RejectsInvalidRegex) { @@ -861,6 +864,8 @@ TEST(MatchRegexAnywhereTest, ReturnsTrueWhenMatchingNonPrefix) { } // Tests RE's implicit constructors. +/* +https://bugs.freebsd.org/248452 TEST(RETest, ImplicitConstructorWorks) { const RE empty(""); EXPECT_STREQ("", empty.pattern()); @@ -868,6 +873,7 @@ TEST(RETest, ImplicitConstructorWorks) { const RE simple("hello"); EXPECT_STREQ("hello", simple.pattern()); } +*/ // Tests that RE's constructors reject invalid regular expressions. TEST(RETest, RejectsInvalidRegex) { From 8c72577900e317393dc43be3df159e0dd4036ddc Mon Sep 17 00:00:00 2001 From: Mateusz Piotrowski <0mp@FreeBSD.org> Date: Mon, 3 Aug 2020 13:12:07 +0000 Subject: [PATCH 025/141] Do not mention portsnap(8) in ports.7 As we are moving away from portsnap, let's not recommend it in the manual page. Reviewed by: bcr (manpages), mat (portmgr) Differential Revision: https://reviews.freebsd.org/D25847 --- share/man/man7/ports.7 | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/share/man/man7/ports.7 b/share/man/man7/ports.7 index eb65d117bded..3a9fe60aa018 100644 --- a/share/man/man7/ports.7 +++ b/share/man/man7/ports.7 @@ -25,7 +25,7 @@ .\" .\" $FreeBSD$ .\" -.Dd July 17, 2020 +.Dd August 3, 2020 .Dt PORTS 7 .Os .Sh NAME @@ -70,9 +70,7 @@ branch contains all the latest changes, while the branches only provide critical fixes. The .Em head -branch can be installed or updated using either -.Xr portsnap 8 , -or from Subversion repository at: +branch can be installed or updated from the Subversion repository located at: .Pp .Lk https://svn.FreeBSD.org/ports/head .Pp @@ -626,8 +624,7 @@ is going to be built with Python 3.7 support.) .Xr make 1 , .Xr make.conf 5 , .Xr development 7 , -.Xr pkg 7 , -.Xr portsnap 8 +.Xr pkg 7 .Pp Additional developer documentation: .Bl -dash -width "" -offset indent From bc9b178cd01a5ce7642ade237975e44b096413a8 Mon Sep 17 00:00:00 2001 From: Andrew Turner Date: Mon, 3 Aug 2020 16:26:10 +0000 Subject: [PATCH 026/141] Allow child classes of simplebus to call attach directly Reduce code duplication when a bus is subclassed from simplebus by allowing them to call simplebus_attach directly. This is useful when the child bus will just implement the same calls. As not all children will expect to have a ranges property, e.g. the Raspberry Pi firmware, allow this property to be missing. Reviewed by: manu Sponsored by: Innovate UK Differential Revision: https://reviews.freebsd.org/D25925 --- sys/dev/fdt/simplebus.c | 6 +++--- sys/dev/fdt/simplebus.h | 5 +++++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/sys/dev/fdt/simplebus.c b/sys/dev/fdt/simplebus.c index 2f4fa8608626..60387a9e7a81 100644 --- a/sys/dev/fdt/simplebus.c +++ b/sys/dev/fdt/simplebus.c @@ -46,7 +46,6 @@ __FBSDID("$FreeBSD$"); * Bus interface. */ static int simplebus_probe(device_t dev); -static int simplebus_attach(device_t dev); static struct resource *simplebus_alloc_resource(device_t, device_t, int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); static void simplebus_probe_nomatch(device_t bus, device_t child); @@ -134,7 +133,7 @@ simplebus_probe(device_t dev) return (BUS_PROBE_GENERIC); } -static int +int simplebus_attach(device_t dev) { struct simplebus_softc *sc; @@ -142,7 +141,8 @@ simplebus_attach(device_t dev) sc = device_get_softc(dev); simplebus_init(dev, 0); - if (simplebus_fill_ranges(sc->node, sc) < 0) { + if ((sc->flags & SB_FLAG_NO_RANGES) == 0 && + simplebus_fill_ranges(sc->node, sc) < 0) { device_printf(dev, "could not get ranges\n"); return (ENXIO); } diff --git a/sys/dev/fdt/simplebus.h b/sys/dev/fdt/simplebus.h index bc695578e874..b416f1b94cfb 100644 --- a/sys/dev/fdt/simplebus.h +++ b/sys/dev/fdt/simplebus.h @@ -47,6 +47,8 @@ struct simplebus_softc { struct simplebus_range *ranges; int nranges; +#define SB_FLAG_NO_RANGES (1 << 0) /* Bus doesn't have ranges property */ + int flags; pcell_t acells, scells; }; @@ -63,4 +65,7 @@ struct simplebus_devinfo *simplebus_setup_dinfo(device_t dev, phandle_t node, struct simplebus_devinfo *di); int simplebus_fill_ranges(phandle_t node, struct simplebus_softc *sc); + +int simplebus_attach(device_t dev); + #endif /* _FDT_SIMPLEBUS_H */ From 7e077ed00c102a996ec38525225db7a1b3d1dd3d Mon Sep 17 00:00:00 2001 From: Andrew Turner Date: Mon, 3 Aug 2020 16:43:40 +0000 Subject: [PATCH 027/141] Allow the Raspberry Pi firmware driver to be a bus There are child nodes in the device tree, e.g. the Raspberry Pi firmware GPIO device. Add support for this to be a bus so we can attach these children. Reviewed by: manu Sponsored by: Innovate UK Differential Revision: https://reviews.freebsd.org/D25848 --- sys/arm/broadcom/bcm2835/bcm2835_firmware.c | 24 +++++++++++---------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/sys/arm/broadcom/bcm2835/bcm2835_firmware.c b/sys/arm/broadcom/bcm2835/bcm2835_firmware.c index 44201ec80f7d..1a061e60a823 100644 --- a/sys/arm/broadcom/bcm2835/bcm2835_firmware.c +++ b/sys/arm/broadcom/bcm2835/bcm2835_firmware.c @@ -38,6 +38,8 @@ __FBSDID("$FreeBSD$"); #include #include +#include + #include #include @@ -47,7 +49,7 @@ __FBSDID("$FreeBSD$"); #include struct bcm2835_firmware_softc { - device_t sc_dev; + struct simplebus_softc sc; phandle_t sc_mbox; }; @@ -82,7 +84,6 @@ bcm2835_firmware_attach(device_t dev) int rv; sc = device_get_softc(dev); - sc->sc_dev = dev; node = ofw_bus_get_node(dev); rv = OF_getencprop(node, "mboxes", &mbox, sizeof(mbox)); @@ -94,14 +95,17 @@ bcm2835_firmware_attach(device_t dev) OF_device_register_xref(OF_xref_from_node(node), dev); - ctx = device_get_sysctl_ctx(sc->sc_dev); - tree_node = device_get_sysctl_tree(sc->sc_dev); + ctx = device_get_sysctl_ctx(dev); + tree_node = device_get_sysctl_tree(dev); tree = SYSCTL_CHILDREN(tree_node); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "revision", CTLTYPE_UINT | CTLFLAG_RD, sc, sizeof(*sc), sysctl_bcm2835_firmware_get_revision, "IU", "Firmware revision"); - return (0); + + /* The firmwaare doesn't have a ranges property */ + sc->sc.flags |= SB_FLAG_NO_RANGES; + return (simplebus_attach(dev)); } int @@ -150,7 +154,7 @@ sysctl_bcm2835_firmware_get_revision(SYSCTL_HANDLER_ARGS) uint32_t rev; int err; - if (bcm2835_firmware_property(sc->sc_dev, + if (bcm2835_firmware_property(sc->sc.dev, BCM2835_MBOX_TAG_FIRMWARE_REVISION, &rev, sizeof(rev)) != 0) return (ENXIO); @@ -171,11 +175,9 @@ static device_method_t bcm2835_firmware_methods[] = { }; static devclass_t bcm2835_firmware_devclass; -static driver_t bcm2835_firmware_driver = { - "bcm2835_firmware", - bcm2835_firmware_methods, - sizeof(struct bcm2835_firmware_softc), -}; +DEFINE_CLASS_1(bcm2835_firmware, bcm2835_firmware_driver, + bcm2835_firmware_methods, sizeof(struct bcm2835_firmware_softc), + simplebus_driver); EARLY_DRIVER_MODULE(bcm2835_firmware, simplebus, bcm2835_firmware_driver, bcm2835_firmware_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); From ca9a39acb38fc0ff328995a1c3c12c78c68f442d Mon Sep 17 00:00:00 2001 From: Konstantin Belousov Date: Mon, 3 Aug 2020 17:17:17 +0000 Subject: [PATCH 028/141] Provide more correct description for sysctl kern.smp.cores. Reported by: dewayne@heuristicsystems.com.au PR: 248454 Sponsored by: The FreeBSD Foundation MFC after: 3 days --- sys/kern/subr_smp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/kern/subr_smp.c b/sys/kern/subr_smp.c index 2024997cd1fa..411b2280b30b 100644 --- a/sys/kern/subr_smp.c +++ b/sys/kern/subr_smp.c @@ -104,7 +104,7 @@ SYSCTL_INT(_kern_smp, OID_AUTO, threads_per_core, CTLFLAG_RD|CTLFLAG_CAPRD, int mp_ncores = -1; /* how many physical cores running */ SYSCTL_INT(_kern_smp, OID_AUTO, cores, CTLFLAG_RD|CTLFLAG_CAPRD, &mp_ncores, 0, - "Number of CPUs online"); + "Number of physical cores online"); int smp_topology = 0; /* Which topology we're using. */ SYSCTL_INT(_kern_smp, OID_AUTO, topology, CTLFLAG_RDTUN, &smp_topology, 0, From 9ca3eaf0bdc12f0609580207aa1afbe51d99f080 Mon Sep 17 00:00:00 2001 From: Andrew Turner Date: Mon, 3 Aug 2020 17:18:12 +0000 Subject: [PATCH 029/141] Add a GPIO driver for the Raspberry Pi firmware GPIOs These exist on the Raspberry Pi 3 and 4 and control and external IO expander. Reviewed by: manu Sponsored by: Innovate UK Differential Revision: https://reviews.freebsd.org/D25858 --- sys/arm/broadcom/bcm2835/raspberrypi_gpio.c | 457 ++++++++++++++++++++ sys/conf/files.arm64 | 1 + 2 files changed, 458 insertions(+) create mode 100644 sys/arm/broadcom/bcm2835/raspberrypi_gpio.c diff --git a/sys/arm/broadcom/bcm2835/raspberrypi_gpio.c b/sys/arm/broadcom/bcm2835/raspberrypi_gpio.c new file mode 100644 index 000000000000..d79d39ff1497 --- /dev/null +++ b/sys/arm/broadcom/bcm2835/raspberrypi_gpio.c @@ -0,0 +1,457 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2012 Oleksandr Tymoshenko + * Copyright (c) 2012-2015 Luiz Otavio O Souza + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ +#include +__FBSDID("$FreeBSD$"); + +#include "opt_platform.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "gpio_if.h" + +#define RPI_FW_GPIO_PINS 8 +#define RPI_FW_GPIO_BASE 128 +#define RPI_FW_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT) + +struct rpi_fw_gpio_softc { + device_t sc_busdev; + device_t sc_firmware; + struct sx sc_sx; + struct gpio_pin sc_gpio_pins[RPI_FW_GPIO_PINS]; + uint8_t sc_gpio_state; +}; + +#define RPI_FW_GPIO_LOCK(_sc) sx_xlock(&(_sc)->sc_sx) +#define RPI_FW_GPIO_UNLOCK(_sc) sx_xunlock(&(_sc)->sc_sx) + +static struct ofw_compat_data compat_data[] = { + {"raspberrypi,firmware-gpio", 1}, + {NULL, 0} +}; + +static int +rpi_fw_gpio_pin_configure(struct rpi_fw_gpio_softc *sc, struct gpio_pin *pin, + unsigned int flags) +{ + union msg_get_gpio_config old_cfg; + union msg_set_gpio_config new_cfg; + int rv; + + bzero(&old_cfg, sizeof(old_cfg)); + bzero(&new_cfg, sizeof(new_cfg)); + old_cfg.req.gpio = RPI_FW_GPIO_BASE + pin->gp_pin; + + RPI_FW_GPIO_LOCK(sc); + rv = bcm2835_firmware_property(sc->sc_firmware, + BCM2835_FIRMWARE_TAG_GET_GPIO_CONFIG, &old_cfg, sizeof(old_cfg)); + if (rv == 0 && old_cfg.resp.gpio != 0) + rv = EIO; + if (rv != 0) + goto fail; + + new_cfg.req.gpio = RPI_FW_GPIO_BASE + pin->gp_pin; + if (flags & GPIO_PIN_INPUT) { + new_cfg.req.dir = BCM2835_FIRMWARE_GPIO_IN; + new_cfg.req.state = 0; + pin->gp_flags = GPIO_PIN_INPUT; + } else if (flags & GPIO_PIN_OUTPUT) { + new_cfg.req.dir = BCM2835_FIRMWARE_GPIO_OUT; + if (flags & (GPIO_PIN_PRESET_HIGH | GPIO_PIN_PRESET_LOW)) { + if (flags & GPIO_PIN_PRESET_HIGH) { + new_cfg.req.state = 1; + sc->sc_gpio_state |= (1 << pin->gp_pin); + } else { + new_cfg.req.state = 0; + sc->sc_gpio_state &= ~(1 << pin->gp_pin); + } + } else { + if ((sc->sc_gpio_state & (1 << pin->gp_pin)) != 0) { + new_cfg.req.state = 1; + } else { + new_cfg.req.state = 0; + } + } + pin->gp_flags = GPIO_PIN_OUTPUT; + } else { + new_cfg.req.dir = old_cfg.resp.dir; + /* Use the old state to decide high/low */ + if ((sc->sc_gpio_state & (1 << pin->gp_pin)) != 0) + new_cfg.req.state = 1; + else + new_cfg.req.state = 0; + } + new_cfg.req.pol = old_cfg.resp.pol; + new_cfg.req.term_en = 0; + new_cfg.req.term_pull_up = 0; + + rv = bcm2835_firmware_property(sc->sc_firmware, + BCM2835_FIRMWARE_TAG_SET_GPIO_CONFIG, &new_cfg, sizeof(new_cfg)); + +fail: + RPI_FW_GPIO_UNLOCK(sc); + + return (rv); +} + +static device_t +rpi_fw_gpio_get_bus(device_t dev) +{ + struct rpi_fw_gpio_softc *sc; + + sc = device_get_softc(dev); + + return (sc->sc_busdev); +} + +static int +rpi_fw_gpio_pin_max(device_t dev, int *maxpin) +{ + + *maxpin = RPI_FW_GPIO_PINS - 1; + return (0); +} + +static int +rpi_fw_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) +{ + struct rpi_fw_gpio_softc *sc; + int i; + + sc = device_get_softc(dev); + for (i = 0; i < RPI_FW_GPIO_PINS; i++) { + if (sc->sc_gpio_pins[i].gp_pin == pin) + break; + } + + if (i >= RPI_FW_GPIO_PINS) + return (EINVAL); + + *caps = RPI_FW_GPIO_DEFAULT_CAPS; + return (0); +} + +static int +rpi_fw_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) +{ + struct rpi_fw_gpio_softc *sc = device_get_softc(dev); + int i; + + for (i = 0; i < RPI_FW_GPIO_PINS; i++) { + if (sc->sc_gpio_pins[i].gp_pin == pin) + break; + } + + if (i >= RPI_FW_GPIO_PINS) + return (EINVAL); + + RPI_FW_GPIO_LOCK(sc); + *flags = sc->sc_gpio_pins[i].gp_flags; + RPI_FW_GPIO_UNLOCK(sc); + + return (0); +} + +static int +rpi_fw_gpio_pin_getname(device_t dev, uint32_t pin, char *name) +{ + struct rpi_fw_gpio_softc *sc; + int i; + + sc = device_get_softc(dev); + for (i = 0; i < RPI_FW_GPIO_PINS; i++) { + if (sc->sc_gpio_pins[i].gp_pin == pin) + break; + } + + if (i >= RPI_FW_GPIO_PINS) + return (EINVAL); + + RPI_FW_GPIO_LOCK(sc); + memcpy(name, sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME); + RPI_FW_GPIO_UNLOCK(sc); + + return (0); +} + +static int +rpi_fw_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) +{ + struct rpi_fw_gpio_softc *sc; + int i; + + sc = device_get_softc(dev); + for (i = 0; i < RPI_FW_GPIO_PINS; i++) { + if (sc->sc_gpio_pins[i].gp_pin == pin) + break; + } + + if (i >= RPI_FW_GPIO_PINS) + return (EINVAL); + + return (rpi_fw_gpio_pin_configure(sc, &sc->sc_gpio_pins[i], flags)); +} + +static int +rpi_fw_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) +{ + struct rpi_fw_gpio_softc *sc; + union msg_set_gpio_state state; + int i, rv; + + sc = device_get_softc(dev); + for (i = 0; i < RPI_FW_GPIO_PINS; i++) { + if (sc->sc_gpio_pins[i].gp_pin == pin) + break; + } + if (i >= RPI_FW_GPIO_PINS) + return (EINVAL); + + state.req.gpio = RPI_FW_GPIO_BASE + pin; + state.req.state = value; + + RPI_FW_GPIO_LOCK(sc); + rv = bcm2835_firmware_property(sc->sc_firmware, + BCM2835_FIRMWARE_TAG_SET_GPIO_STATE, &state, sizeof(state)); + /* The firmware sets gpio to 0 on success */ + if (rv == 0 && state.resp.gpio != 0) + rv = EINVAL; + if (rv == 0) { + sc->sc_gpio_pins[i].gp_flags &= ~(GPIO_PIN_PRESET_HIGH | + GPIO_PIN_PRESET_LOW); + if (value) + sc->sc_gpio_state |= (1 << i); + else + sc->sc_gpio_state &= ~(1 << i); + } + RPI_FW_GPIO_UNLOCK(sc); + + return (rv); +} + +static int +rpi_fw_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) +{ + struct rpi_fw_gpio_softc *sc; + union msg_get_gpio_state state; + int i, rv; + + sc = device_get_softc(dev); + for (i = 0; i < RPI_FW_GPIO_PINS; i++) { + if (sc->sc_gpio_pins[i].gp_pin == pin) + break; + } + if (i >= RPI_FW_GPIO_PINS) + return (EINVAL); + + bzero(&state, sizeof(state)); + state.req.gpio = RPI_FW_GPIO_BASE + pin; + + RPI_FW_GPIO_LOCK(sc); + rv = bcm2835_firmware_property(sc->sc_firmware, + BCM2835_FIRMWARE_TAG_GET_GPIO_STATE, &state, sizeof(state)); + RPI_FW_GPIO_UNLOCK(sc); + + /* The firmware sets gpio to 0 on success */ + if (rv == 0 && state.resp.gpio != 0) + rv = EINVAL; + if (rv == 0) + *val = !state.resp.state; + + return (rv); +} + +static int +rpi_fw_gpio_pin_toggle(device_t dev, uint32_t pin) +{ + struct rpi_fw_gpio_softc *sc; + union msg_get_gpio_state old_state; + union msg_set_gpio_state new_state; + int i, rv; + + sc = device_get_softc(dev); + for (i = 0; i < RPI_FW_GPIO_PINS; i++) { + if (sc->sc_gpio_pins[i].gp_pin == pin) + break; + } + if (i >= RPI_FW_GPIO_PINS) + return (EINVAL); + + bzero(&old_state, sizeof(old_state)); + bzero(&new_state, sizeof(new_state)); + + old_state.req.gpio = RPI_FW_GPIO_BASE + pin; + new_state.req.gpio = RPI_FW_GPIO_BASE + pin; + + RPI_FW_GPIO_LOCK(sc); + rv = bcm2835_firmware_property(sc->sc_firmware, + BCM2835_FIRMWARE_TAG_GET_GPIO_STATE, &old_state, sizeof(old_state)); + /* The firmware sets gpio to 0 on success */ + if (rv == 0 && old_state.resp.gpio == 0) { + /* Set the new state to invert the GPIO */ + new_state.req.state = !old_state.resp.state; + rv = bcm2835_firmware_property(sc->sc_firmware, + BCM2835_FIRMWARE_TAG_SET_GPIO_STATE, &new_state, + sizeof(new_state)); + } + if (rv == 0 && (old_state.resp.gpio != 0 || new_state.resp.gpio != 0)) + rv = EINVAL; + RPI_FW_GPIO_UNLOCK(sc); + + return (rv); +} + +static int +rpi_fw_gpio_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Raspberry Pi Firmware GPIO controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +rpi_fw_gpio_attach(device_t dev) +{ + union msg_get_gpio_config cfg; + struct rpi_fw_gpio_softc *sc; + char *names; + phandle_t gpio; + int i, nelems, elm_pos, rv; + + sc = device_get_softc(dev); + sc->sc_firmware = device_get_parent(dev); + sx_init(&sc->sc_sx, "Raspberry Pi firmware gpio"); + /* Find our node. */ + gpio = ofw_bus_get_node(dev); + if (!OF_hasprop(gpio, "gpio-controller")) + /* This is not a GPIO controller. */ + goto fail; + + nelems = OF_getprop_alloc(gpio, "gpio-line-names", (void **)&names); + if (nelems <= 0) + names = NULL; + elm_pos = 0; + for (i = 0; i < RPI_FW_GPIO_PINS; i++) { + /* Set the current pin name */ + if (names != NULL && elm_pos < nelems && + names[elm_pos] != '\0') { + snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME, + "%s", names + elm_pos); + /* Find the next pin name */ + elm_pos += strlen(names + elm_pos) + 1; + } else { + snprintf(sc->sc_gpio_pins[i].gp_name, GPIOMAXNAME, + "pin %d", i); + } + + sc->sc_gpio_pins[i].gp_pin = i; + sc->sc_gpio_pins[i].gp_caps = RPI_FW_GPIO_DEFAULT_CAPS; + + bzero(&cfg, sizeof(cfg)); + cfg.req.gpio = RPI_FW_GPIO_BASE + i; + rv = bcm2835_firmware_property(sc->sc_firmware, + BCM2835_FIRMWARE_TAG_GET_GPIO_CONFIG, &cfg, sizeof(cfg)); + if (rv == 0 && cfg.resp.gpio == 0) { + if (cfg.resp.dir == BCM2835_FIRMWARE_GPIO_IN) + sc->sc_gpio_pins[i].gp_flags = GPIO_PIN_INPUT; + else + sc->sc_gpio_pins[i].gp_flags = GPIO_PIN_OUTPUT; + } else { + sc->sc_gpio_pins[i].gp_flags = GPIO_PIN_INPUT; + } + } + free(names, M_OFWPROP); + sc->sc_busdev = gpiobus_attach_bus(dev); + if (sc->sc_busdev == NULL) + goto fail; + + return (0); + +fail: + sx_destroy(&sc->sc_sx); + + return (ENXIO); +} + +static int +rpi_fw_gpio_detach(device_t dev) +{ + + return (EBUSY); +} + +static device_method_t rpi_fw_gpio_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rpi_fw_gpio_probe), + DEVMETHOD(device_attach, rpi_fw_gpio_attach), + DEVMETHOD(device_detach, rpi_fw_gpio_detach), + + /* GPIO protocol */ + DEVMETHOD(gpio_get_bus, rpi_fw_gpio_get_bus), + DEVMETHOD(gpio_pin_max, rpi_fw_gpio_pin_max), + DEVMETHOD(gpio_pin_getname, rpi_fw_gpio_pin_getname), + DEVMETHOD(gpio_pin_getflags, rpi_fw_gpio_pin_getflags), + DEVMETHOD(gpio_pin_getcaps, rpi_fw_gpio_pin_getcaps), + DEVMETHOD(gpio_pin_setflags, rpi_fw_gpio_pin_setflags), + DEVMETHOD(gpio_pin_get, rpi_fw_gpio_pin_get), + DEVMETHOD(gpio_pin_set, rpi_fw_gpio_pin_set), + DEVMETHOD(gpio_pin_toggle, rpi_fw_gpio_pin_toggle), + + DEVMETHOD_END +}; + +static devclass_t rpi_fw_gpio_devclass; + +static driver_t rpi_fw_gpio_driver = { + "gpio", + rpi_fw_gpio_methods, + sizeof(struct rpi_fw_gpio_softc), +}; + +EARLY_DRIVER_MODULE(rpi_fw_gpio, bcm2835_firmware, rpi_fw_gpio_driver, + rpi_fw_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64 index e8a0cfc95f0d..7bae8741eec6 100644 --- a/sys/conf/files.arm64 +++ b/sys/conf/files.arm64 @@ -108,6 +108,7 @@ arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm283 arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 | dwcotg fdt soc_brcm_bcm2838 arm/broadcom/bcm2835/bcm2838_pci.c optional soc_brcm_bcm2838 fdt pci arm/broadcom/bcm2835/bcm2838_xhci.c optional soc_brcm_bcm2838 fdt pci xhci +arm/broadcom/bcm2835/raspberrypi_gpio.c optional soc_brcm_bcm2837 gpio | soc_brcm_bcm2838 gpio arm/freescale/vybrid/vf_i2c.c optional vf_i2c iicbus SOC_NXP_LS arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt arm/mv/a37x0_iic.c optional a37x0_iic iicbus fdt From 338b22234b4f300b948ea8d1292bc023976516b8 Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Mon, 3 Aug 2020 17:53:15 +0000 Subject: [PATCH 030/141] Pass the full CFLAGS to cpp for MKlib_gen.sh. GCC's cpp was exiting immediately when it failed to find requested includes ( and ). clang-cpp emitted an error for the missing header files but continued processing the file (thus not honoring any macros defined in the missing headers). Arguably, the awk script is buggy since it doesn't check the return value of the command it executes. Reviewed by: kevans Differential Revision: https://reviews.freebsd.org/D25731 --- lib/ncurses/ncurses/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/ncurses/ncurses/Makefile b/lib/ncurses/ncurses/Makefile index 5b61df983ce9..efa38691115e 100644 --- a/lib/ncurses/ncurses/Makefile +++ b/lib/ncurses/ncurses/Makefile @@ -345,7 +345,7 @@ codes.c: MKcodes.awk ${AWK} -f ${NCURSES_DIR}/ncurses/tinfo/MKcodes.awk bigstrings=${USE_BIG_STRINGS} ${NCURSES_DIR}/include/Caps > codes.c lib_gen.c: MKlib_gen.sh curses.h ncurses_dll.h - LC_ALL=C sh ${NCURSES_DIR}/ncurses/base/MKlib_gen.sh "${CPP:N${CCACHE_BIN}} ${CPPFLAGS}" \ + LC_ALL=C sh ${NCURSES_DIR}/ncurses/base/MKlib_gen.sh "${CPP:N${CCACHE_BIN}} ${CFLAGS}" \ "${AWK}" generated < curses.h >$@ lib_keyname.c: keys.list MKkeyname.awk From 9053c1a4316e0168d52ec2de8a7669bf0fd5e2c1 Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Mon, 3 Aug 2020 18:08:04 +0000 Subject: [PATCH 031/141] Allow building setmode.c on Linux/macOS We bootstrap this file to allow compiling FreeBSD on Linux systems since some boostrap tools use setmode(). Unfortunately, glibc's sys/stat.h declares a non-static getumask() function (which is unimplemented!) and that conflicts with the local getumask() function. To work around this simply use a different name here. Reviewed By: brooks, emaste Differential Revision: https://reviews.freebsd.org/D25929 --- lib/libc/gen/setmode.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/lib/libc/gen/setmode.c b/lib/libc/gen/setmode.c index 05fe58952e9d..66976cdd7bcf 100644 --- a/lib/libc/gen/setmode.c +++ b/lib/libc/gen/setmode.c @@ -70,7 +70,7 @@ typedef struct bitcmd { #define CMD2_OBITS 0x08 #define CMD2_UBITS 0x10 -static mode_t getumask(void); +static mode_t get_current_umask(void); static BITCMD *addcmd(BITCMD *, mode_t, mode_t, mode_t, mode_t); static void compress_mode(BITCMD *); #ifdef SETMODE_DEBUG @@ -186,7 +186,7 @@ setmode(const char *p) * Get a copy of the mask for the permissions that are mask relative. * Flip the bits, we want what's not set. */ - mask = ~getumask(); + mask = ~get_current_umask(); setlen = SET_LEN + 2; @@ -343,13 +343,14 @@ apply: if (!*p) } static mode_t -getumask(void) +get_current_umask(void) { sigset_t sigset, sigoset; size_t len; mode_t mask; u_short smask; +#ifdef KERN_PROC_UMASK /* * First try requesting the umask without temporarily modifying it. * Note that this does not work if the sysctl @@ -359,7 +360,7 @@ getumask(void) if (sysctl((int[4]){ CTL_KERN, KERN_PROC, KERN_PROC_UMASK, 0 }, 4, &smask, &len, NULL, 0) == 0) return (smask); - +#endif /* * Since it's possible that the caller is opening files inside a signal * handler, protect them as best we can. From c4bd82d701879af2a073472eaf8d4599047793ed Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Mon, 3 Aug 2020 18:08:10 +0000 Subject: [PATCH 032/141] Allow bootstrapping mtree on Linux systems Linux glibc has a dummy lchmod that always fails and emitting a linker warning when used. Don't fail the build due to that warning when bootstrapping by setting LD_FATAL_WARNINGS=no. Reviewed By: brooks, emaste Differential Revision: https://reviews.freebsd.org/D25930 --- usr.sbin/nmtree/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/usr.sbin/nmtree/Makefile b/usr.sbin/nmtree/Makefile index c29974ff7fcc..57705671f155 100644 --- a/usr.sbin/nmtree/Makefile +++ b/usr.sbin/nmtree/Makefile @@ -22,4 +22,10 @@ MLINKS= mtree.8 nmtree.8 HAS_TESTS= SUBDIR.${MK_TESTS}+= tests +.if defined(BOOTSTRAPPING) +# Linux glibc has a dummy lchmod that always fails. Don't fail due to +# the linker warning that it emits. +LD_FATAL_WARNINGS=no +.endif + .include From a68dea2ff90f2e77fe8c6a9e022aa1ac258106b7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Stefan=20E=C3=9Fer?= Date: Mon, 3 Aug 2020 18:55:39 +0000 Subject: [PATCH 033/141] Import version 3.1.4 This version makes dc exit after processing all commands passed via -e or -f instead of waiting for more input on STDIN (add "-f -" to the command line to emulate the behavior of versionm 3.1.3 and earlier, if desired). The version and copyright message are no longer printed for interactive sessions as was the case with the prior implementation in the FreeBSD base system. Obtained from: https://git.yzena.com/gavin/bc --- Makefile.in | 2 +- NEWS.md | 19 ++++++++++ README.md | 8 ++-- include/bc.h | 3 -- include/vm.h | 18 +++------ manuals/bc.1.md.in | 26 +++++-------- manuals/bc/A.1 | 35 +++++++----------- manuals/bc/A.1.md | 26 +++++-------- manuals/bc/E.1 | 35 +++++++----------- manuals/bc/E.1.md | 26 +++++-------- manuals/bc/EH.1 | 35 +++++++----------- manuals/bc/EH.1.md | 26 +++++-------- manuals/bc/EHN.1 | 35 +++++++----------- manuals/bc/EHN.1.md | 26 +++++-------- manuals/bc/EHNP.1 | 35 +++++++----------- manuals/bc/EHNP.1.md | 26 +++++-------- manuals/bc/EHP.1 | 35 +++++++----------- manuals/bc/EHP.1.md | 26 +++++-------- manuals/bc/EN.1 | 35 +++++++----------- manuals/bc/EN.1.md | 26 +++++-------- manuals/bc/ENP.1 | 35 +++++++----------- manuals/bc/ENP.1.md | 26 +++++-------- manuals/bc/EP.1 | 35 +++++++----------- manuals/bc/EP.1.md | 26 +++++-------- manuals/bc/H.1 | 35 +++++++----------- manuals/bc/H.1.md | 26 +++++-------- manuals/bc/HN.1 | 35 +++++++----------- manuals/bc/HN.1.md | 26 +++++-------- manuals/bc/HNP.1 | 35 +++++++----------- manuals/bc/HNP.1.md | 26 +++++-------- manuals/bc/HP.1 | 35 +++++++----------- manuals/bc/HP.1.md | 26 +++++-------- manuals/bc/N.1 | 35 +++++++----------- manuals/bc/N.1.md | 26 +++++-------- manuals/bc/NP.1 | 35 +++++++----------- manuals/bc/NP.1.md | 26 +++++-------- manuals/bc/P.1 | 35 +++++++----------- manuals/bc/P.1.md | 26 +++++-------- manuals/dc.1.md.in | 12 +++--- manuals/dc/A.1 | 17 +++++---- manuals/dc/A.1.md | 12 +++--- manuals/dc/E.1 | 17 +++++---- manuals/dc/E.1.md | 12 +++--- manuals/dc/EH.1 | 17 +++++---- manuals/dc/EH.1.md | 12 +++--- manuals/dc/EHN.1 | 17 +++++---- manuals/dc/EHN.1.md | 12 +++--- manuals/dc/EHNP.1 | 17 +++++---- manuals/dc/EHNP.1.md | 12 +++--- manuals/dc/EHP.1 | 17 +++++---- manuals/dc/EHP.1.md | 12 +++--- manuals/dc/EN.1 | 17 +++++---- manuals/dc/EN.1.md | 12 +++--- manuals/dc/ENP.1 | 17 +++++---- manuals/dc/ENP.1.md | 12 +++--- manuals/dc/EP.1 | 17 +++++---- manuals/dc/EP.1.md | 12 +++--- manuals/dc/H.1 | 17 +++++---- manuals/dc/H.1.md | 12 +++--- manuals/dc/HN.1 | 17 +++++---- manuals/dc/HN.1.md | 12 +++--- manuals/dc/HNP.1 | 17 +++++---- manuals/dc/HNP.1.md | 12 +++--- manuals/dc/HP.1 | 17 +++++---- manuals/dc/HP.1.md | 12 +++--- manuals/dc/N.1 | 17 +++++---- manuals/dc/N.1.md | 12 +++--- manuals/dc/NP.1 | 17 +++++---- manuals/dc/NP.1.md | 12 +++--- manuals/dc/P.1 | 17 +++++---- manuals/dc/P.1.md | 12 +++--- src/args.c | 14 +++++-- src/bc/bc.c | 2 +- src/bc/parse.c | 18 ++++----- src/dc/dc.c | 2 +- src/vm.c | 74 ++++++++++++++++--------------------- tests/bc/all.txt | 2 + tests/bc/misc6.txt | 1 + tests/bc/misc6_results.txt | 1 + tests/bc/misc7.txt | 1 + tests/bc/misc7_results.txt | 1 + tests/bc/stdin1.txt | 2 + tests/bc/stdin1_results.txt | 1 + tests/bc/stdin2.txt | 1 + tests/bc/stdin2_results.txt | 3 ++ 85 files changed, 737 insertions(+), 914 deletions(-) create mode 120000 tests/bc/misc6.txt create mode 120000 tests/bc/misc6_results.txt create mode 120000 tests/bc/misc7.txt create mode 120000 tests/bc/misc7_results.txt create mode 100644 tests/bc/stdin1.txt create mode 100644 tests/bc/stdin1_results.txt create mode 100644 tests/bc/stdin2.txt create mode 100644 tests/bc/stdin2_results.txt diff --git a/Makefile.in b/Makefile.in index 2c67e92d13de..fa087ad67aff 100644 --- a/Makefile.in +++ b/Makefile.in @@ -29,7 +29,7 @@ # .POSIX: -VERSION = 3.1.3 +VERSION = 3.1.4 SRC = %%SRC%% OBJ = %%OBJ%% diff --git a/NEWS.md b/NEWS.md index 64e8deb9853d..ba528dbe907b 100644 --- a/NEWS.md +++ b/NEWS.md @@ -1,5 +1,24 @@ # News +## 3.1.4 + +This is a production release that fixes one bug, changes two behaviors, and +removes one environment variable. + +The bug is like the one in the last release except it applies if files are being +executed. I also made the fix more general. + +The behavior that was changed is that `bc` now exits when given `-e`, `-f`, +`--expression` or `--file`. However, if the last one of those is `-f-` (using +`stdin` as the file), `bc` does not exit. If `-f-` exists and is not the last of +the `-e` and `-f` options (and equivalents), `bc` gives a fatal error and exits. + +Next, I removed the `BC_EXPR_EXIT` and `DC_EXPR_EXIT` environment variables +since their use is not needed with the behavior change. + +Finally, I made it so `bc` does not print the header, though the `-q` and +`--quiet` options were kept for compatibility with GNU `bc`. + ## 3.1.3 This is a production release that fixes one minor bug: if `bc` was invoked like diff --git a/README.md b/README.md index f2165e554221..8aacb21b004c 100644 --- a/README.md +++ b/README.md @@ -262,8 +262,8 @@ Other projects based on this bc are: toybox `bc` should be reported there. * [FreeBSD `bc`][23]. While the `bc` in FreeBSD is kept up-to-date, it is better - to report bugs there, and the maintainers of the package will contact me if - necessary. + to [report bugs there][24], as well as [submit patches][25], and the + maintainers of the package will contact me if necessary. ## Language @@ -332,4 +332,6 @@ Folders: [20]: https://git.yzena.com/gavin/bc [21]: https://gavinhoward.com/2020/04/i-am-moving-away-from-github/ [22]: https://www.deepl.com/translator -[23]: https://github.com/freebsd/freebsd/tree/master/contrib/bc +[23]: https://svnweb.freebsd.org/base/head/contrib/bc/ +[24]: https://bugs.freebsd.org/ +[25]: https://reviews.freebsd.org/ diff --git a/include/bc.h b/include/bc.h index ade18c828c28..4423525bad3e 100644 --- a/include/bc.h +++ b/include/bc.h @@ -159,9 +159,6 @@ void bc_parse_expr(BcParse *p, uint8_t flags); void bc_parse_parse(BcParse *p); void bc_parse_expr_status(BcParse *p, uint8_t flags, BcParseNext next); -// This is necessary to clear up for if statements at the end of files. -void bc_parse_noElse(BcParse *p); - extern const char bc_sig_msg[]; extern const uchar bc_sig_msg_len; diff --git a/include/vm.h b/include/vm.h index cdadfc8bed13..f178c0390853 100644 --- a/include/vm.h +++ b/include/vm.h @@ -102,11 +102,10 @@ #define BC_FLAG_G (UINTMAX_C(1)<<4) #endif // BC_ENABLED -#define BC_FLAG_Q (UINTMAX_C(1)<<5) -#define BC_FLAG_I (UINTMAX_C(1)<<6) -#define BC_FLAG_P (UINTMAX_C(1)<<7) -#define BC_FLAG_TTYIN (UINTMAX_C(1)<<8) -#define BC_FLAG_TTY (UINTMAX_C(1)<<9) +#define BC_FLAG_I (UINTMAX_C(1)<<5) +#define BC_FLAG_P (UINTMAX_C(1)<<6) +#define BC_FLAG_TTYIN (UINTMAX_C(1)<<7) +#define BC_FLAG_TTY (UINTMAX_C(1)<<8) #define BC_TTYIN (vm.flags & BC_FLAG_TTYIN) #define BC_TTY (vm.flags & BC_FLAG_TTY) @@ -279,12 +278,6 @@ #define BC_VM_INVALID_CATALOG ((nl_catd) -1) -// dc does not use is_stdin. -#if !BC_ENABLED -#define bc_vm_process(text, is_stdin) bc_vm_process(text) -#else // BC_ENABLED -#endif // BC_ENABLED - typedef struct BcVm { volatile sig_atomic_t status; @@ -310,6 +303,7 @@ typedef struct BcVm { uint16_t nchars; uint16_t line_len; + bool no_exit_exprs; bool eof; BcBigDig maxes[BC_PROG_GLOBALS_LEN + BC_ENABLE_EXTRA_MATH]; @@ -360,7 +354,7 @@ typedef struct BcVm { void bc_vm_info(const char* const help); void bc_vm_boot(int argc, char *argv[], const char *env_len, - const char* const env_args, const char* env_exp_quit); + const char* const env_args); void bc_vm_shutdown(void); void bc_vm_printf(const char *fmt, ...); diff --git a/manuals/bc.1.md.in b/manuals/bc.1.md.in index ed2fa8beae7b..80892e742345 100644 --- a/manuals/bc.1.md.in +++ b/manuals/bc.1.md.in @@ -195,10 +195,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -229,9 +229,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -241,9 +242,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -1615,12 +1615,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/A.1 b/manuals/bc/A.1 index 6421238febb6..f0966ba9d877 100644 --- a/manuals/bc/A.1 +++ b/manuals/bc/A.1 @@ -187,13 +187,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -231,10 +231,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -246,10 +248,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1915,14 +1916,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/A.1.md b/manuals/bc/A.1.md index 31b491a3bc70..e67c20656e23 100644 --- a/manuals/bc/A.1.md +++ b/manuals/bc/A.1.md @@ -153,10 +153,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -187,9 +187,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -199,9 +200,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -1524,12 +1524,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/E.1 b/manuals/bc/E.1 index 70afc2b716f4..d85db650606c 100644 --- a/manuals/bc/E.1 +++ b/manuals/bc/E.1 @@ -148,13 +148,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -192,10 +192,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -207,10 +209,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1161,14 +1162,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/E.1.md b/manuals/bc/E.1.md index 4b5b95ab4d27..ab432274fa52 100644 --- a/manuals/bc/E.1.md +++ b/manuals/bc/E.1.md @@ -137,10 +137,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -171,9 +171,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -183,9 +184,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -920,12 +920,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/EH.1 b/manuals/bc/EH.1 index 90708661143a..c9b196f7452a 100644 --- a/manuals/bc/EH.1 +++ b/manuals/bc/EH.1 @@ -145,13 +145,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -189,10 +189,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -204,10 +206,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1158,14 +1159,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/EH.1.md b/manuals/bc/EH.1.md index 60efac2dd904..32ef6e0d009f 100644 --- a/manuals/bc/EH.1.md +++ b/manuals/bc/EH.1.md @@ -134,10 +134,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -168,9 +168,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -180,9 +181,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -917,12 +917,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/EHN.1 b/manuals/bc/EHN.1 index 203cc531e8b7..0117a4cd0b68 100644 --- a/manuals/bc/EHN.1 +++ b/manuals/bc/EHN.1 @@ -145,13 +145,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -189,10 +189,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -204,10 +206,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1158,14 +1159,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/EHN.1.md b/manuals/bc/EHN.1.md index 6264e7bf5c81..38b7cf78d76a 100644 --- a/manuals/bc/EHN.1.md +++ b/manuals/bc/EHN.1.md @@ -134,10 +134,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -168,9 +168,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -180,9 +181,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -917,12 +917,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/EHNP.1 b/manuals/bc/EHNP.1 index da6a25888ce0..02b96492075d 100644 --- a/manuals/bc/EHNP.1 +++ b/manuals/bc/EHNP.1 @@ -140,13 +140,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -184,10 +184,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -199,10 +201,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1153,14 +1154,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/EHNP.1.md b/manuals/bc/EHNP.1.md index 917b7bc6665c..df608db015b4 100644 --- a/manuals/bc/EHNP.1.md +++ b/manuals/bc/EHNP.1.md @@ -130,10 +130,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -164,9 +164,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -176,9 +177,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -913,12 +913,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/EHP.1 b/manuals/bc/EHP.1 index 3352c2ee5610..cc2920f84403 100644 --- a/manuals/bc/EHP.1 +++ b/manuals/bc/EHP.1 @@ -140,13 +140,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -184,10 +184,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -199,10 +201,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1153,14 +1154,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/EHP.1.md b/manuals/bc/EHP.1.md index 30e411236e46..0ce1f5209c21 100644 --- a/manuals/bc/EHP.1.md +++ b/manuals/bc/EHP.1.md @@ -130,10 +130,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -164,9 +164,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -176,9 +177,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -913,12 +913,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/EN.1 b/manuals/bc/EN.1 index a662d40fdda9..d7f967d96cd5 100644 --- a/manuals/bc/EN.1 +++ b/manuals/bc/EN.1 @@ -148,13 +148,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -192,10 +192,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -207,10 +209,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1161,14 +1162,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/EN.1.md b/manuals/bc/EN.1.md index cefe8630da75..55ca344ddeb2 100644 --- a/manuals/bc/EN.1.md +++ b/manuals/bc/EN.1.md @@ -137,10 +137,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -171,9 +171,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -183,9 +184,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -920,12 +920,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/ENP.1 b/manuals/bc/ENP.1 index b98a2a2ce2fe..736e26bd9acd 100644 --- a/manuals/bc/ENP.1 +++ b/manuals/bc/ENP.1 @@ -143,13 +143,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -187,10 +187,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -202,10 +204,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1156,14 +1157,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/ENP.1.md b/manuals/bc/ENP.1.md index 6d7194f31cf6..1eae3dee00d1 100644 --- a/manuals/bc/ENP.1.md +++ b/manuals/bc/ENP.1.md @@ -133,10 +133,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -167,9 +167,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -179,9 +180,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -916,12 +916,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/EP.1 b/manuals/bc/EP.1 index 9c841d8bab4b..107342a54361 100644 --- a/manuals/bc/EP.1 +++ b/manuals/bc/EP.1 @@ -143,13 +143,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -187,10 +187,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -202,10 +204,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1156,14 +1157,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/EP.1.md b/manuals/bc/EP.1.md index 090b07f0a2d0..7e3d6aca7384 100644 --- a/manuals/bc/EP.1.md +++ b/manuals/bc/EP.1.md @@ -133,10 +133,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -167,9 +167,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -179,9 +180,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -916,12 +916,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/H.1 b/manuals/bc/H.1 index 17a913896886..48ccfb55b962 100644 --- a/manuals/bc/H.1 +++ b/manuals/bc/H.1 @@ -182,13 +182,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -226,10 +226,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -241,10 +243,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1910,14 +1911,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/H.1.md b/manuals/bc/H.1.md index 089953f9706a..413032534554 100644 --- a/manuals/bc/H.1.md +++ b/manuals/bc/H.1.md @@ -149,10 +149,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -183,9 +183,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -195,9 +196,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -1520,12 +1520,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/HN.1 b/manuals/bc/HN.1 index f275ceaffb9b..9126c9209da5 100644 --- a/manuals/bc/HN.1 +++ b/manuals/bc/HN.1 @@ -182,13 +182,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -226,10 +226,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -241,10 +243,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1910,14 +1911,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/HN.1.md b/manuals/bc/HN.1.md index 2e1935a12539..c9ac146efbb2 100644 --- a/manuals/bc/HN.1.md +++ b/manuals/bc/HN.1.md @@ -149,10 +149,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -183,9 +183,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -195,9 +196,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -1520,12 +1520,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/HNP.1 b/manuals/bc/HNP.1 index e3583a545c74..ad09513f0528 100644 --- a/manuals/bc/HNP.1 +++ b/manuals/bc/HNP.1 @@ -177,13 +177,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -221,10 +221,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -236,10 +238,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1905,14 +1906,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/HNP.1.md b/manuals/bc/HNP.1.md index 7501316421d6..dc8c70ac09a9 100644 --- a/manuals/bc/HNP.1.md +++ b/manuals/bc/HNP.1.md @@ -145,10 +145,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -179,9 +179,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -191,9 +192,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -1516,12 +1516,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/HP.1 b/manuals/bc/HP.1 index 9c7d0abab262..3ede3a2d5ca8 100644 --- a/manuals/bc/HP.1 +++ b/manuals/bc/HP.1 @@ -177,13 +177,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -221,10 +221,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -236,10 +238,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1905,14 +1906,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/HP.1.md b/manuals/bc/HP.1.md index cafab919d324..2c4053a302d0 100644 --- a/manuals/bc/HP.1.md +++ b/manuals/bc/HP.1.md @@ -145,10 +145,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -179,9 +179,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -191,9 +192,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -1516,12 +1516,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/N.1 b/manuals/bc/N.1 index 83049e7c7b14..5c3e86157ba7 100644 --- a/manuals/bc/N.1 +++ b/manuals/bc/N.1 @@ -187,13 +187,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -231,10 +231,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -246,10 +248,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1915,14 +1916,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/N.1.md b/manuals/bc/N.1.md index 49aaf0fbbcfd..9eabb2591eab 100644 --- a/manuals/bc/N.1.md +++ b/manuals/bc/N.1.md @@ -153,10 +153,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -187,9 +187,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -199,9 +200,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -1524,12 +1524,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/NP.1 b/manuals/bc/NP.1 index a50dfe2dcc17..8c2a2994a17f 100644 --- a/manuals/bc/NP.1 +++ b/manuals/bc/NP.1 @@ -182,13 +182,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -226,10 +226,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -241,10 +243,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1910,14 +1911,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/NP.1.md b/manuals/bc/NP.1.md index a5aa258659d2..be11fe236209 100644 --- a/manuals/bc/NP.1.md +++ b/manuals/bc/NP.1.md @@ -149,10 +149,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -183,9 +183,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -195,9 +196,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -1520,12 +1520,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/bc/P.1 b/manuals/bc/P.1 index 4f6b4ece227c..db807e440c28 100644 --- a/manuals/bc/P.1 +++ b/manuals/bc/P.1 @@ -182,13 +182,13 @@ This is a \f[B]non\-portable extension\f[]. .RE .TP .B \f[B]\-q\f[], \f[B]\-\-quiet\f[] -Do not print copyright header. -bc(1) will also suppress the header in non\-interactive mode. +This option is for compatibility with the GNU +bc(1) (https://www.gnu.org/software/bc/); it is a no\-op. +Without this option, GNU bc(1) prints a copyright header. +This bc(1) only prints the copyright header if one or more of the +\f[B]\-v\f[], \f[B]\-V\f[], or \f[B]\-\-version\f[] options are given. .RS .PP -This is mostly for compatibility with the GNU -bc(1) (https://www.gnu.org/software/bc/). -.PP This is a \f[B]non\-portable extension\f[]. .RE .TP @@ -226,10 +226,12 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the expressions and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -241,10 +243,9 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other bc(1) implementations, this option causes the program to -execute the files and then exit. -This bc(1) does not, unless the \f[B]BC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, bc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -1910,14 +1911,6 @@ the backslash (\f[B]\\\f[]). The default line length is \f[B]70\f[]. .RS .RE -.TP -.B \f[B]BC_EXPR_EXIT\f[] -If this variable exists (no matter the contents), bc(1) will exit -immediately after executing expressions and files given by the -\f[B]\-e\f[] and/or \f[B]\-f\f[] command\-line options (and any -equivalents). -.RS -.RE .SH EXIT STATUS .PP bc(1) returns the following exit statuses: diff --git a/manuals/bc/P.1.md b/manuals/bc/P.1.md index 1f7379ebfe41..1058a91aa6d2 100644 --- a/manuals/bc/P.1.md +++ b/manuals/bc/P.1.md @@ -149,10 +149,10 @@ The following are the options that bc(1) accepts. **-q**, **--quiet** -: Do not print copyright header. bc(1) will also suppress the header in - non-interactive mode. - - This is mostly for compatibility with the [GNU bc(1)][2]. +: This option is for compatibility with the [GNU bc(1)][2]; it is a no-op. + Without this option, GNU bc(1) prints a copyright header. This bc(1) only + prints the copyright header if one or more of the **-v**, **-V**, or + **--version** options are given. This is a **non-portable extension**. @@ -183,9 +183,10 @@ The following are the options that bc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other bc(1) implementations, this option causes the program to execute - the expressions and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. @@ -195,9 +196,8 @@ The following are the options that bc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other bc(1) implementations, this option causes the program to execute - the files and then exit. This bc(1) does not, unless the - **BC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, bc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -1520,12 +1520,6 @@ bc(1) recognizes the following environment variables: lines to that length, including the backslash (**\\**). The default line length is **70**. -**BC_EXPR_EXIT** - -: If this variable exists (no matter the contents), bc(1) will exit - immediately after executing expressions and files given by the **-e** and/or - **-f** command-line options (and any equivalents). - # EXIT STATUS bc(1) returns the following exit statuses: diff --git a/manuals/dc.1.md.in b/manuals/dc.1.md.in index b6d252a2276e..abb1c4aac773 100644 --- a/manuals/dc.1.md.in +++ b/manuals/dc.1.md.in @@ -106,9 +106,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -118,9 +117,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/A.1 b/manuals/dc/A.1 index 10627cb197ec..001fe5a1f2c5 100644 --- a/manuals/dc/A.1 +++ b/manuals/dc/A.1 @@ -118,10 +118,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -133,10 +132,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/A.1.md b/manuals/dc/A.1.md index 36b20862c57f..50c7c8f08c6b 100644 --- a/manuals/dc/A.1.md +++ b/manuals/dc/A.1.md @@ -101,9 +101,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -113,9 +112,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/E.1 b/manuals/dc/E.1 index 7f11a33bb18a..f5b1f194f206 100644 --- a/manuals/dc/E.1 +++ b/manuals/dc/E.1 @@ -118,10 +118,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -133,10 +132,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/E.1.md b/manuals/dc/E.1.md index 028e61b42bcc..bb2ab4b0366d 100644 --- a/manuals/dc/E.1.md +++ b/manuals/dc/E.1.md @@ -101,9 +101,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -113,9 +112,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/EH.1 b/manuals/dc/EH.1 index d7efbd649a76..9c5cf7d14c92 100644 --- a/manuals/dc/EH.1 +++ b/manuals/dc/EH.1 @@ -118,10 +118,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -133,10 +132,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/EH.1.md b/manuals/dc/EH.1.md index 774ba6e32b3a..e1a0540d1243 100644 --- a/manuals/dc/EH.1.md +++ b/manuals/dc/EH.1.md @@ -101,9 +101,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -113,9 +112,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/EHN.1 b/manuals/dc/EHN.1 index a77032398174..4d95b4a1ac96 100644 --- a/manuals/dc/EHN.1 +++ b/manuals/dc/EHN.1 @@ -118,10 +118,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -133,10 +132,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/EHN.1.md b/manuals/dc/EHN.1.md index b4845bf77d86..1fe5ab8cac09 100644 --- a/manuals/dc/EHN.1.md +++ b/manuals/dc/EHN.1.md @@ -101,9 +101,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -113,9 +112,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/EHNP.1 b/manuals/dc/EHNP.1 index fb350b8ed2f9..aceea91027ad 100644 --- a/manuals/dc/EHNP.1 +++ b/manuals/dc/EHNP.1 @@ -113,10 +113,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -128,10 +127,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/EHNP.1.md b/manuals/dc/EHNP.1.md index 71a24ac4e635..97585bba14bb 100644 --- a/manuals/dc/EHNP.1.md +++ b/manuals/dc/EHNP.1.md @@ -98,9 +98,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -110,9 +109,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/EHP.1 b/manuals/dc/EHP.1 index 2a47184695cb..70e45ae52363 100644 --- a/manuals/dc/EHP.1 +++ b/manuals/dc/EHP.1 @@ -113,10 +113,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -128,10 +127,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/EHP.1.md b/manuals/dc/EHP.1.md index 5445e17e5811..d101695a1c89 100644 --- a/manuals/dc/EHP.1.md +++ b/manuals/dc/EHP.1.md @@ -98,9 +98,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -110,9 +109,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/EN.1 b/manuals/dc/EN.1 index cc6ec8baaefd..4c57b0dd03e3 100644 --- a/manuals/dc/EN.1 +++ b/manuals/dc/EN.1 @@ -118,10 +118,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -133,10 +132,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/EN.1.md b/manuals/dc/EN.1.md index 114c4d1916b1..e1826daa4e18 100644 --- a/manuals/dc/EN.1.md +++ b/manuals/dc/EN.1.md @@ -101,9 +101,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -113,9 +112,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/ENP.1 b/manuals/dc/ENP.1 index 01a49aff21ae..2e8e2341a739 100644 --- a/manuals/dc/ENP.1 +++ b/manuals/dc/ENP.1 @@ -113,10 +113,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -128,10 +127,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/ENP.1.md b/manuals/dc/ENP.1.md index df9c398527c8..cc5eea424fb2 100644 --- a/manuals/dc/ENP.1.md +++ b/manuals/dc/ENP.1.md @@ -98,9 +98,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -110,9 +109,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/EP.1 b/manuals/dc/EP.1 index 00d29fc3ff9c..f97f2a8ae98f 100644 --- a/manuals/dc/EP.1 +++ b/manuals/dc/EP.1 @@ -113,10 +113,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -128,10 +127,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/EP.1.md b/manuals/dc/EP.1.md index 99bb462fb0a0..cd58549b17a5 100644 --- a/manuals/dc/EP.1.md +++ b/manuals/dc/EP.1.md @@ -98,9 +98,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -110,9 +109,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/H.1 b/manuals/dc/H.1 index 02825b898261..44617c0b1a3c 100644 --- a/manuals/dc/H.1 +++ b/manuals/dc/H.1 @@ -118,10 +118,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -133,10 +132,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/H.1.md b/manuals/dc/H.1.md index ab3b13fbf758..327e27a0c893 100644 --- a/manuals/dc/H.1.md +++ b/manuals/dc/H.1.md @@ -101,9 +101,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -113,9 +112,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/HN.1 b/manuals/dc/HN.1 index cb97ca4cafb3..8b032e82f1f9 100644 --- a/manuals/dc/HN.1 +++ b/manuals/dc/HN.1 @@ -118,10 +118,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -133,10 +132,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/HN.1.md b/manuals/dc/HN.1.md index a4d3b9f6ca9e..f128840138a5 100644 --- a/manuals/dc/HN.1.md +++ b/manuals/dc/HN.1.md @@ -101,9 +101,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -113,9 +112,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/HNP.1 b/manuals/dc/HNP.1 index fefaa2a56c9d..f5152fa781d4 100644 --- a/manuals/dc/HNP.1 +++ b/manuals/dc/HNP.1 @@ -113,10 +113,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -128,10 +127,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/HNP.1.md b/manuals/dc/HNP.1.md index b97a4a118d89..fc71488f8b53 100644 --- a/manuals/dc/HNP.1.md +++ b/manuals/dc/HNP.1.md @@ -98,9 +98,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -110,9 +109,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/HP.1 b/manuals/dc/HP.1 index 45b0cc111be8..eeae02949fc0 100644 --- a/manuals/dc/HP.1 +++ b/manuals/dc/HP.1 @@ -113,10 +113,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -128,10 +127,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/HP.1.md b/manuals/dc/HP.1.md index fb7569dab186..88e0914d6266 100644 --- a/manuals/dc/HP.1.md +++ b/manuals/dc/HP.1.md @@ -98,9 +98,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -110,9 +109,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/N.1 b/manuals/dc/N.1 index a4fb86637c1f..a7ca5b5fec27 100644 --- a/manuals/dc/N.1 +++ b/manuals/dc/N.1 @@ -118,10 +118,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -133,10 +132,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/N.1.md b/manuals/dc/N.1.md index ac7e27b6e5a3..6e843649b37d 100644 --- a/manuals/dc/N.1.md +++ b/manuals/dc/N.1.md @@ -101,9 +101,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -113,9 +112,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/NP.1 b/manuals/dc/NP.1 index 9b0b407bb327..bfd1c0e59d4f 100644 --- a/manuals/dc/NP.1 +++ b/manuals/dc/NP.1 @@ -113,10 +113,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -128,10 +127,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/NP.1.md b/manuals/dc/NP.1.md index f521c3df205e..b83d20a806bb 100644 --- a/manuals/dc/NP.1.md +++ b/manuals/dc/NP.1.md @@ -98,9 +98,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -110,9 +109,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/manuals/dc/P.1 b/manuals/dc/P.1 index 4ba6c64322d9..6f5cd4cec1d3 100644 --- a/manuals/dc/P.1 +++ b/manuals/dc/P.1 @@ -113,10 +113,9 @@ This means that if a file is given before an expression, the file is read in and evaluated first. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the expressions and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. .PP This is a \f[B]non\-portable extension\f[]. .RE @@ -128,10 +127,12 @@ If expressions are also given (see above), the expressions are evaluated in the order given. .RS .PP -In other dc(1) implementations, this option causes the program to -execute the files and then exit. -This dc(1) does not, unless the \f[B]DC_EXPR_EXIT\f[] is defined (see -the \f[B]ENVIRONMENT VARIABLES\f[] section). +After processing all expressions and files, dc(1) will exit, unless +\f[B]\-\f[] (\f[B]stdin\f[]) was given as an argument at least once to +\f[B]\-f\f[] or \f[B]\-\-file\f[]. +However, if any other \f[B]\-e\f[], \f[B]\-\-expression\f[], +\f[B]\-f\f[], or \f[B]\-\-file\f[] arguments are given after that, bc(1) +will give a fatal error and exit. .PP This is a \f[B]non\-portable extension\f[]. .RE diff --git a/manuals/dc/P.1.md b/manuals/dc/P.1.md index dc6d3d950067..41aad658bb3d 100644 --- a/manuals/dc/P.1.md +++ b/manuals/dc/P.1.md @@ -98,9 +98,8 @@ The following are the options that dc(1) accepts. evaluated in the order given. This means that if a file is given before an expression, the file is read in and evaluated first. - In other dc(1) implementations, this option causes the program to execute - the expressions and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. This is a **non-portable extension**. @@ -110,9 +109,10 @@ The following are the options that dc(1) accepts. through **stdin**. If expressions are also given (see above), the expressions are evaluated in the order given. - In other dc(1) implementations, this option causes the program to execute - the files and then exit. This dc(1) does not, unless the - **DC_EXPR_EXIT** is defined (see the **ENVIRONMENT VARIABLES** section). + After processing all expressions and files, dc(1) will exit, unless **-** + (**stdin**) was given as an argument at least once to **-f** or **--file**. + However, if any other **-e**, **--expression**, **-f**, or **--file** + arguments are given after that, bc(1) will give a fatal error and exit. This is a **non-portable extension**. diff --git a/src/args.c b/src/args.c index 1626ad4944e4..029237627786 100644 --- a/src/args.c +++ b/src/args.c @@ -108,13 +108,20 @@ void bc_args(int argc, char *argv[]) { case 'e': { + if (vm.no_exit_exprs) + bc_vm_verr(BC_ERROR_FATAL_OPTION, "-e (--expression)"); bc_args_exprs(opts.optarg); break; } case 'f': { - bc_args_file(opts.optarg); + if (!strcmp(opts.optarg, "-")) vm.no_exit_exprs = true; + else { + if (vm.no_exit_exprs) + bc_vm_verr(BC_ERROR_FATAL_OPTION, "-f (--file)"); + bc_args_file(opts.optarg); + } break; } @@ -155,7 +162,7 @@ void bc_args(int argc, char *argv[]) { case 'q': { assert(BC_IS_BC); - vm.flags |= BC_FLAG_Q; + // Do nothing. break; } @@ -205,9 +212,8 @@ void bc_args(int argc, char *argv[]) { if (version) bc_vm_info(NULL); if (do_exit) exit((int) vm.status); - if (vm.exprs.len > 1 || BC_IS_DC) vm.flags |= BC_FLAG_Q; - if (opts.optind < (size_t) argc) + if (opts.optind < (size_t) argc && vm.files.v == NULL) bc_vec_init(&vm.files, sizeof(char*), NULL); for (i = opts.optind; i < (size_t) argc; ++i) diff --git a/src/bc/bc.c b/src/bc/bc.c index ef0fc3d6865d..3d488b5640c8 100644 --- a/src/bc/bc.c +++ b/src/bc/bc.c @@ -52,6 +52,6 @@ void bc_main(int argc, char **argv) { vm.parse = bc_parse_parse; vm.expr = bc_parse_expr; - bc_vm_boot(argc, argv, "BC_LINE_LENGTH", "BC_ENV_ARGS", "BC_EXPR_EXIT"); + bc_vm_boot(argc, argv, "BC_LINE_LENGTH", "BC_ENV_ARGS"); } #endif // BC_ENABLED diff --git a/src/bc/parse.c b/src/bc/parse.c index 2aa9d97468ff..329c1a84b419 100644 --- a/src/bc/parse.c +++ b/src/bc/parse.c @@ -179,10 +179,10 @@ static void bc_parse_params(BcParse *p, uint8_t flags) { bc_lex_next(&p->l); - for (nparams = 0; p->l.t != BC_LEX_RPAREN; ++nparams) { + flags &= ~(BC_PARSE_PRINT | BC_PARSE_REL); + flags |= (BC_PARSE_ARRAY | BC_PARSE_NEEDVAL); - flags &= ~(BC_PARSE_PRINT | BC_PARSE_REL); - flags |= (BC_PARSE_ARRAY | BC_PARSE_NEEDVAL); + for (nparams = 0; p->l.t != BC_LEX_RPAREN; ++nparams) { bc_parse_expr_status(p, flags, bc_parse_next_param); @@ -516,6 +516,12 @@ static void bc_parse_return(BcParse *p) { } } +static void bc_parse_noElse(BcParse *p) { + uint16_t *flag_ptr = BC_PARSE_TOP_FLAG_PTR(p); + *flag_ptr = (*flag_ptr & ~(BC_PARSE_FLAG_IF_END)); + bc_parse_setLabel(p); +} + static void bc_parse_endBody(BcParse *p, bool brace) { bool has_brace, new_else = false; @@ -610,12 +616,6 @@ static void bc_parse_startBody(BcParse *p, uint16_t flags) { bc_vec_push(&p->flags, &flags); } -void bc_parse_noElse(BcParse *p) { - uint16_t *flag_ptr = BC_PARSE_TOP_FLAG_PTR(p); - *flag_ptr = (*flag_ptr & ~(BC_PARSE_FLAG_IF_END)); - bc_parse_setLabel(p); -} - static void bc_parse_if(BcParse *p) { size_t idx; diff --git a/src/dc/dc.c b/src/dc/dc.c index 21d7bfbd4385..8c03ccf0e414 100644 --- a/src/dc/dc.c +++ b/src/dc/dc.c @@ -52,6 +52,6 @@ void dc_main(int argc, char **argv) { vm.parse = dc_parse_parse; vm.expr = dc_parse_expr; - bc_vm_boot(argc, argv, "DC_LINE_LENGTH", "DC_ENV_ARGS", "DC_EXPR_EXIT"); + bc_vm_boot(argc, argv, "DC_LINE_LENGTH", "DC_ENV_ARGS"); } #endif // DC_ENABLED diff --git a/src/vm.c b/src/vm.c index 905613563e8d..9818ce4f35f4 100644 --- a/src/vm.c +++ b/src/vm.c @@ -452,7 +452,7 @@ static void bc_vm_clean(void) { } } -static void bc_vm_process(const char *text, bool is_stdin) { +static void bc_vm_process(const char *text) { bc_parse_text(&vm.prs, text); @@ -464,21 +464,6 @@ static void bc_vm_process(const char *text, bool is_stdin) { while (BC_PARSE_CAN_PARSE(vm.prs)) vm.parse(&vm.prs); -#if BC_ENABLED - if (BC_IS_BC) { - - uint16_t *flags = BC_PARSE_TOP_FLAG_PTR(&vm.prs); - - if (!is_stdin && vm.prs.flags.len == 1 && - *flags == BC_PARSE_FLAG_IF_END) - { - bc_parse_noElse(&vm.prs); - } - - if (BC_PARSE_NO_EXEC(&vm.prs)) return; - } -#endif // BC_ENABLED - bc_program_exec(&vm.prog); assert(BC_IS_DC || vm.prog.results.len == 0); @@ -488,6 +473,28 @@ static void bc_vm_process(const char *text, bool is_stdin) { } while (vm.prs.l.t != BC_LEX_EOF); } +#if BC_ENABLED +static void bc_vm_endif(void) { + + size_t i; + bool good; + + if (BC_NO_ERR(!BC_PARSE_NO_EXEC(&vm.prs))) return; + + good = true; + + for (i = 0; good && i < vm.prs.flags.len; ++i) { + uint16_t flag = *((uint16_t*) bc_vec_item(&vm.prs.flags, i)); + good = ((flag & BC_PARSE_FLAG_BRACE) != BC_PARSE_FLAG_BRACE); + } + + if (good) { + while (BC_PARSE_IF_END(&vm.prs)) bc_vm_process("else {}"); + } + else bc_parse_err(&vm.prs, BC_ERROR_PARSE_BLOCK); +} +#endif // BC_ENABLED + static void bc_vm_file(const char *file) { char *data = NULL; @@ -504,11 +511,10 @@ static void bc_vm_file(const char *file) { BC_SIG_UNLOCK; - bc_vm_process(data, false); + bc_vm_process(data); #if BC_ENABLED - if (BC_IS_BC && BC_ERR(BC_PARSE_NO_EXEC(&vm.prs))) - bc_parse_err(&vm.prs, BC_ERROR_PARSE_BLOCK); + if (BC_IS_BC) bc_vm_endif(); #endif // BC_ENABLED err: @@ -589,7 +595,7 @@ static void bc_vm_stdin(void) { if (vm.history.stdin_has_data) continue; #endif // BC_ENABLE_HISTORY - bc_vm_process(buffer.v, true); + bc_vm_process(buffer.v); bc_vec_empty(&buffer); if (vm.eof) break; @@ -602,21 +608,7 @@ static void bc_vm_stdin(void) { else if (BC_ERR(string)) bc_parse_err(&vm.prs, BC_ERROR_PARSE_STRING); #if BC_ENABLED - else if (BC_IS_BC && BC_ERR(BC_PARSE_NO_EXEC(&vm.prs))) { - - size_t i; - bool good = true; - - for (i = 0; good && i < vm.prs.flags.len; ++i) { - uint16_t flag = *((uint16_t*) bc_vec_item(&vm.prs.flags, i)); - good = ((flag & BC_PARSE_FLAG_BRACE) != BC_PARSE_FLAG_BRACE); - } - - if (good) { - while (BC_PARSE_IF_END(&vm.prs)) bc_vm_process("else {}", true); - } - else bc_parse_err(&vm.prs, BC_ERROR_PARSE_BLOCK); - } + else if (BC_IS_BC) bc_vm_endif(); #endif // BC_ENABLED } @@ -706,7 +698,7 @@ static void bc_vm_gettext(void) { #endif // BC_ENABLE_NLS } -static void bc_vm_exec(const char* env_exp_exit) { +static void bc_vm_exec(void) { size_t i; bool has_file = false; @@ -743,7 +735,7 @@ static void bc_vm_exec(const char* env_exp_exit) { more = bc_read_buf(&buf, vm.exprs.v, &len); bc_vec_pushByte(&buf, '\0'); - bc_vm_process(buf.v, false); + bc_vm_process(buf.v); bc_vec_npop(&buf, buf.len); @@ -758,7 +750,7 @@ static void bc_vm_exec(const char* env_exp_exit) { BC_SIG_UNLOCK; - if (getenv(env_exp_exit) != NULL) return; + if (!vm.no_exit_exprs) return; } for (i = 0; i < vm.files.len; ++i) { @@ -784,7 +776,7 @@ static void bc_vm_exec(const char* env_exp_exit) { } void bc_vm_boot(int argc, char *argv[], const char *env_len, - const char* const env_args, const char* env_exp_exit) + const char* const env_args) { int ttyin, ttyout, ttyerr; struct sigaction sa; @@ -863,9 +855,7 @@ void bc_vm_boot(int argc, char *argv[], const char *env_len, vm.maxes[BC_PROG_GLOBALS_IBASE] = BC_NUM_MAX_IBASE; #endif // BC_ENABLED - if (BC_IS_BC && BC_I && !(vm.flags & BC_FLAG_Q)) bc_vm_info(NULL); - BC_SIG_UNLOCK; - bc_vm_exec(env_exp_exit); + bc_vm_exec(); } diff --git a/tests/bc/all.txt b/tests/bc/all.txt index 069e60942404..b623e8a11b71 100644 --- a/tests/bc/all.txt +++ b/tests/bc/all.txt @@ -39,6 +39,8 @@ misc2 misc3 misc4 misc5 +misc6 +misc7 void rand lib2 diff --git a/tests/bc/misc6.txt b/tests/bc/misc6.txt new file mode 120000 index 000000000000..1ddbfa42bea4 --- /dev/null +++ b/tests/bc/misc6.txt @@ -0,0 +1 @@ +stdin1.txt \ No newline at end of file diff --git a/tests/bc/misc6_results.txt b/tests/bc/misc6_results.txt new file mode 120000 index 000000000000..a0374545ed82 --- /dev/null +++ b/tests/bc/misc6_results.txt @@ -0,0 +1 @@ +stdin1_results.txt \ No newline at end of file diff --git a/tests/bc/misc7.txt b/tests/bc/misc7.txt new file mode 120000 index 000000000000..17ea58ae3ffd --- /dev/null +++ b/tests/bc/misc7.txt @@ -0,0 +1 @@ +stdin2.txt \ No newline at end of file diff --git a/tests/bc/misc7_results.txt b/tests/bc/misc7_results.txt new file mode 120000 index 000000000000..394d3e9d57c1 --- /dev/null +++ b/tests/bc/misc7_results.txt @@ -0,0 +1 @@ +stdin2_results.txt \ No newline at end of file diff --git a/tests/bc/stdin1.txt b/tests/bc/stdin1.txt new file mode 100644 index 000000000000..3721c265baa2 --- /dev/null +++ b/tests/bc/stdin1.txt @@ -0,0 +1,2 @@ +if (1 < 3) + if (2 < 3) 1 diff --git a/tests/bc/stdin1_results.txt b/tests/bc/stdin1_results.txt new file mode 100644 index 000000000000..d00491fd7e5b --- /dev/null +++ b/tests/bc/stdin1_results.txt @@ -0,0 +1 @@ +1 diff --git a/tests/bc/stdin2.txt b/tests/bc/stdin2.txt new file mode 100644 index 000000000000..f260cfa7dbcf --- /dev/null +++ b/tests/bc/stdin2.txt @@ -0,0 +1 @@ +for (i = 0; i < 3; ++i) if (2 < 3) 1 diff --git a/tests/bc/stdin2_results.txt b/tests/bc/stdin2_results.txt new file mode 100644 index 000000000000..e8183f05f5db --- /dev/null +++ b/tests/bc/stdin2_results.txt @@ -0,0 +1,3 @@ +1 +1 +1 From 2ead2969a0bd202c427a4c17a91376d6189b5c1e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Stefan=20E=C3=9Fer?= Date: Mon, 3 Aug 2020 19:18:38 +0000 Subject: [PATCH 034/141] Upgrade to version 3.1.4 This version omits the printing of a copyright header in interactive mode and the dc command now exits after execution of the commands passed via -e or -f instead of switching to interactive mode. To pass further commands via STDIN when dc has been invoked with -e or -f, add "-f -" to the parameter list. --- usr.bin/gh-bc/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/usr.bin/gh-bc/Makefile b/usr.bin/gh-bc/Makefile index f630685504fb..654752e0df82 100644 --- a/usr.bin/gh-bc/Makefile +++ b/usr.bin/gh-bc/Makefile @@ -59,6 +59,10 @@ MAN_SRC_DC= dc/A.1 CFLAGS+= -flto .endif +.if ${MK_TESTS} != "no" +#SUBDIR+= tests +.endif + .for catalog in ${CATALOGS} NLS+= ${catalog:C/.*://} NLSSRCFILES_${catalog:C/.*://}= ${catalog:C/.*://}.msg From f022d2cd17af99bc785bdcb8ea6dca44a8ec03a4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Stefan=20E=C3=9Fer?= Date: Mon, 3 Aug 2020 20:26:04 +0000 Subject: [PATCH 035/141] Connect the tests provided with the new bc and dc The tests compare the command output (including of error cases) with the expected output and exit code. Not all tests are executed, since some expect to have a known good bc and dc binary installed and compare results of large amounts of generated data being processed by both versions to test for regressions. --- etc/mtree/BSD.tests.dist | 2 ++ usr.bin/gh-bc/Makefile | 5 ++- usr.bin/gh-bc/tests/Makefile | 67 ++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+), 3 deletions(-) create mode 100644 usr.bin/gh-bc/tests/Makefile diff --git a/etc/mtree/BSD.tests.dist b/etc/mtree/BSD.tests.dist index 80c4b3e47dc3..8bc8c7e96ac3 100644 --- a/etc/mtree/BSD.tests.dist +++ b/etc/mtree/BSD.tests.dist @@ -1002,6 +1002,8 @@ .. getconf .. + gh-bc + .. grep .. gzip diff --git a/usr.bin/gh-bc/Makefile b/usr.bin/gh-bc/Makefile index 654752e0df82..87910da8937e 100644 --- a/usr.bin/gh-bc/Makefile +++ b/usr.bin/gh-bc/Makefile @@ -59,9 +59,8 @@ MAN_SRC_DC= dc/A.1 CFLAGS+= -flto .endif -.if ${MK_TESTS} != "no" -#SUBDIR+= tests -.endif +HAS_TESTS= +SUBDIR.${MK_TESTS}+= tests .for catalog in ${CATALOGS} NLS+= ${catalog:C/.*://} diff --git a/usr.bin/gh-bc/tests/Makefile b/usr.bin/gh-bc/tests/Makefile new file mode 100644 index 000000000000..b66509549bee --- /dev/null +++ b/usr.bin/gh-bc/tests/Makefile @@ -0,0 +1,67 @@ +# $FreeBSD$ + +.include + +PACKAGE= tests + +TEST_DIR= ${SRCTOP}/contrib/bc + +TESTSDIR= ${TESTSBASE}/usr.bin/gh-bc + +.PATH: ${SRCTOP}/tests + +FILESGROUPS+= FILESf +FILESfPACKAGE= ${PACKAGE} +FILESfDIR= ${TESTSDIR} +FILESf= ${TEST_DIR}/functions.sh +FILESfMODE= 0755 + +FILESGROUPS+= FILEStests +FILEStestsPACKAGE= ${PACKAGE} +FILEStestsDIR= ${TESTSDIR}/tests +FILEStests!= echo ${TEST_DIR}/tests/*.py ${TEST_DIR}/tests/*.sh ${TEST_DIR}/tests/*.txt +FILEStestsMODE= 0755 + +FILESGROUPS+= FILESbc +FILESbcPACKAGE= ${PACKAGE} +FILESbcDIR= ${TESTSDIR}/tests/bc +FILESbc!= echo ${TEST_DIR}/tests/bc/*.* + +FILESGROUPS+= FILESbc_errors +FILESbc_errorsPACKAGE= ${PACKAGE} +FILESbc_errorsDIR= ${TESTSDIR}/tests/bc/errors +FILESbc_errors!= echo ${TEST_DIR}/tests/bc/errors/*.* + +FILESGROUPS+= FILESbc_scripts +FILESbc_scriptsPACKAGE= ${PACKAGE} +FILESbc_scriptsDIR= ${TESTSDIR}/tests/bc/scripts +FILESbc_scripts!= echo ${TEST_DIR}/tests/bc/scripts/*.* +FILESbc_scriptsMODE= 0755 + +FILESGROUPS+= FILESdc +FILESdcPACKAGE= ${PACKAGE} +FILESdcDIR= ${TESTSDIR}/tests/dc +FILESdc!= echo ${TEST_DIR}/tests/dc/*.* + +FILESGROUPS+= FILESdc_errors +FILESdc_errorsPACKAGE= ${PACKAGE} +FILESdc_errorsDIR= ${TESTSDIR}/tests/dc/errors +FILESdc_errors!= echo ${TEST_DIR}/tests/dc/errors/*.* + +FILESGROUPS+= FILESdc_scripts +FILESdc_scriptsPACKAGE= ${PACKAGE} +FILESdc_scriptsDIR= ${TESTSDIR}/tests/dc/scripts +FILESdc_scripts!= echo ${TEST_DIR}/tests/dc/scripts/*.* +FILESdc_scriptsMODE= 0755 + +PLAIN_TESTS_SH= bc_tests dc_tests + +bc_tests.sh: + echo "#!/bin/sh" > ${.TARGET} + echo "env LANG=C ${TESTSDIR}/tests/all.sh bc 1 1 0 0 bc" >> ${.TARGET} + +dc_tests.sh: + echo "#!/bin/sh" > ${.TARGET} + echo "env LANG=C ${TESTSDIR}/tests/all.sh dc 1 1 0 0 dc" >> ${.TARGET} + +.include From e67c55c998417a2b3ad6d25086e14a96e6fabe69 Mon Sep 17 00:00:00 2001 From: Warner Losh Date: Mon, 3 Aug 2020 22:12:18 +0000 Subject: [PATCH 036/141] Some function had the blank lines, others didn't. Most of the ones that didn't were newer, so remove this now-optional blank line everywhere. --- sys/kern/subr_bus.c | 30 ------------------------------ 1 file changed, 30 deletions(-) diff --git a/sys/kern/subr_bus.c b/sys/kern/subr_bus.c index f75ab7df40bb..ca99201577d2 100644 --- a/sys/kern/subr_bus.c +++ b/sys/kern/subr_bus.c @@ -234,7 +234,6 @@ devclass_sysctl_handler(SYSCTL_HANDLER_ARGS) static void devclass_sysctl_init(devclass_t dc) { - if (dc->sysctl_tree != NULL) return; sysctl_ctx_init(&dc->sysctl_ctx); @@ -453,7 +452,6 @@ devinit(void) static int devopen(struct cdev *dev, int oflags, int devtype, struct thread *td) { - mtx_lock(&devsoftc.mtx); if (devsoftc.inuse) { mtx_unlock(&devsoftc.mtx); @@ -468,7 +466,6 @@ devopen(struct cdev *dev, int oflags, int devtype, struct thread *td) static int devclose(struct cdev *dev, int fflag, int devtype, struct thread *td) { - mtx_lock(&devsoftc.mtx); devsoftc.inuse = 0; devsoftc.nonblock = 0; @@ -522,7 +519,6 @@ static int devioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag, struct thread *td) { switch (cmd) { - case FIONBIO: if (*(int*)data) devsoftc.nonblock = 1; @@ -585,7 +581,6 @@ devkqfilter(struct cdev *dev, struct knote *kn) static void filt_devctl_detach(struct knote *kn) { - knlist_remove(&devsoftc.sel.si_note, kn, 0); } @@ -661,7 +656,6 @@ devctl_queue_data_f(char *data, int flags) void devctl_queue_data(char *data) { - devctl_queue_data_f(data, M_NOWAIT); } @@ -704,7 +698,6 @@ void devctl_notify(const char *system, const char *subsystem, const char *type, const char *data) { - devctl_notify_f(system, subsystem, type, data, M_NOWAIT); } @@ -876,7 +869,6 @@ sysctl_devctl_queue(SYSCTL_HANDLER_ARGS) void devctl_safe_quote_sb(struct sbuf *sb, const char *src) { - while (*src != '\0') { if (*src == '"' || *src == '\\') sbuf_putc(sb, '\\'); @@ -2597,7 +2589,6 @@ device_claim_softc(device_t dev) void * device_get_ivars(device_t dev) { - KASSERT(dev != NULL, ("device_get_ivars(NULL, ...)")); return (dev->ivars); } @@ -2608,7 +2599,6 @@ device_get_ivars(device_t dev) void device_set_ivars(device_t dev, void * ivars) { - KASSERT(dev != NULL, ("device_set_ivars(NULL, ...)")); dev->ivars = ivars; } @@ -3087,7 +3077,6 @@ device_detach(device_t dev) int device_quiesce(device_t dev) { - PDEBUG(("%s", DEVICENAME(dev))); if (dev->state == DS_BUSY) return (EBUSY); @@ -3148,7 +3137,6 @@ device_set_unit(device_t dev, int unit) void resource_init_map_request_impl(struct resource_map_request *args, size_t sz) { - bzero(args, sz); args->size = sz; args->memattr = VM_MEMATTR_UNCACHEABLE; @@ -3704,7 +3692,6 @@ resource_list_purge(struct resource_list *rl) device_t bus_generic_add_child(device_t dev, u_int order, const char *name, int unit) { - return (device_add_child_ordered(dev, order, name, unit)); } @@ -3852,7 +3839,6 @@ bus_generic_suspend_child(device_t dev, device_t child) int bus_generic_resume_child(device_t dev, device_t child) { - DEVICE_RESUME(child); child->flags &= ~DF_SUSPENDED; @@ -3944,7 +3930,6 @@ bus_helper_reset_post(device_t dev, int flags) static void bus_helper_reset_prepare_rollback(device_t dev, device_t child, int flags) { - child = TAILQ_NEXT(child, link); if (child == NULL) return; @@ -4356,7 +4341,6 @@ int bus_generic_bind_intr(device_t dev, device_t child, struct resource *irq, int cpu) { - /* Propagate up the bus hierarchy until someone handles it. */ if (dev->parent) return (BUS_BIND_INTR(dev->parent, child, irq, cpu)); @@ -4373,7 +4357,6 @@ int bus_generic_config_intr(device_t dev, int irq, enum intr_trigger trig, enum intr_polarity pol) { - /* Propagate up the bus hierarchy until someone handles it. */ if (dev->parent) return (BUS_CONFIG_INTR(dev->parent, irq, trig, pol)); @@ -4390,7 +4373,6 @@ int bus_generic_describe_intr(device_t dev, device_t child, struct resource *irq, void *cookie, const char *descr) { - /* Propagate up the bus hierarchy until someone handles it. */ if (dev->parent) return (BUS_DESCRIBE_INTR(dev->parent, child, irq, cookie, @@ -4408,7 +4390,6 @@ int bus_generic_get_cpus(device_t dev, device_t child, enum cpu_sets op, size_t setsize, cpuset_t *cpuset) { - /* Propagate up the bus hierarchy until someone handles it. */ if (dev->parent != NULL) return (BUS_GET_CPUS(dev->parent, child, op, setsize, cpuset)); @@ -4424,7 +4405,6 @@ bus_generic_get_cpus(device_t dev, device_t child, enum cpu_sets op, bus_dma_tag_t bus_generic_get_dma_tag(device_t dev, device_t child) { - /* Propagate up the bus hierarchy until someone handles it. */ if (dev->parent != NULL) return (BUS_GET_DMA_TAG(dev->parent, child)); @@ -4440,7 +4420,6 @@ bus_generic_get_dma_tag(device_t dev, device_t child) bus_space_tag_t bus_generic_get_bus_tag(device_t dev, device_t child) { - /* Propagate up the bus hierarchy until someone handles it. */ if (dev->parent != NULL) return (BUS_GET_BUS_TAG(dev->parent, child)); @@ -4587,7 +4566,6 @@ bus_generic_child_present(device_t dev, device_t child) int bus_generic_get_domain(device_t dev, device_t child, int *domain) { - if (dev->parent) return (BUS_GET_DOMAIN(dev->parent, dev, domain)); @@ -4603,7 +4581,6 @@ bus_generic_get_domain(device_t dev, device_t child, int *domain) int bus_null_rescan(device_t dev) { - return (ENXIO); } @@ -5101,7 +5078,6 @@ static int root_get_cpus(device_t dev, device_t child, enum cpu_sets op, size_t setsize, cpuset_t *cpuset) { - switch (op) { case INTR_CPUS: /* Default to returning the set of all CPUs. */ @@ -5182,7 +5158,6 @@ DECLARE_MODULE(rootbus, root_bus_mod, SI_SUB_DRIVERS, SI_ORDER_FIRST); void root_bus_configure(void) { - PDEBUG((".")); /* Eventually this will be split up, but this is sufficient for now. */ @@ -5556,7 +5531,6 @@ bus_data_generation_check(int generation) void bus_data_generation_update(void) { - atomic_add_int(&bus_data_generation, 1); } @@ -5944,7 +5918,6 @@ static struct cdevsw devctl2_cdevsw = { static void devctl2_init(void) { - make_dev_credf(MAKEDEV_ETERNAL, &devctl2_cdevsw, 0, NULL, UID_ROOT, GID_WHEEL, 0600, "devctl2"); } @@ -5960,7 +5933,6 @@ SYSCTL_INT(_debug, OID_AUTO, obsolete_panic, CTLFLAG_RWTUN, &obsolete_panic, 0, static void gone_panic(int major, int running, const char *msg) { - switch (obsolete_panic) { case 0: @@ -5977,7 +5949,6 @@ gone_panic(int major, int running, const char *msg) void _gone_in(int major, const char *msg) { - gone_panic(major, P_OSREL_MAJOR(__FreeBSD_version), msg); if (P_OSREL_MAJOR(__FreeBSD_version) >= major) printf("Obsolete code will be removed soon: %s\n", msg); @@ -5989,7 +5960,6 @@ _gone_in(int major, const char *msg) void _gone_in_dev(device_t dev, int major, const char *msg) { - gone_panic(major, P_OSREL_MAJOR(__FreeBSD_version), msg); if (P_OSREL_MAJOR(__FreeBSD_version) >= major) device_printf(dev, From 6e0c8e1ae292e567ba6260d9a6c0b771629a89e3 Mon Sep 17 00:00:00 2001 From: Konstantin Belousov Date: Mon, 3 Aug 2020 22:13:02 +0000 Subject: [PATCH 037/141] Add SOL_LOCAL symbolic constant for unix socket option level. The constant seems to exists on MacOS X >= 10.8. Requested by: swills Reviewed by: allanjude, kevans Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D25933 --- lib/libc/gen/getpeereid.c | 2 +- share/man/man4/unix.4 | 6 ++++-- sys/kern/uipc_usrreq.c | 2 +- sys/sys/un.h | 2 ++ 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/lib/libc/gen/getpeereid.c b/lib/libc/gen/getpeereid.c index 530ae0e6100e..86396d359ba3 100644 --- a/lib/libc/gen/getpeereid.c +++ b/lib/libc/gen/getpeereid.c @@ -47,7 +47,7 @@ getpeereid(int s, uid_t *euid, gid_t *egid) int error; xuclen = sizeof(xuc); - error = _getsockopt(s, 0, LOCAL_PEERCRED, &xuc, &xuclen); + error = _getsockopt(s, SOL_LOCAL, LOCAL_PEERCRED, &xuc, &xuclen); if (error != 0) return (error); if (xuc.cr_version != XUCRED_VERSION) { diff --git a/share/man/man4/unix.4 b/share/man/man4/unix.4 index 8832e5eff870..569e6dd25208 100644 --- a/share/man/man4/unix.4 +++ b/share/man/man4/unix.4 @@ -28,7 +28,7 @@ .\" @(#)unix.4 8.1 (Berkeley) 6/9/93 .\" $FreeBSD$ .\" -.Dd August 19, 2018 +.Dd August 3, 2020 .Dt UNIX 4 .Os .Sh NAME @@ -195,7 +195,9 @@ The sending process could have exited and its process ID already been reused for a new process. .Sh SOCKET OPTIONS .Tn UNIX -domain sockets support a number of socket options which can be set with +domain sockets support a number of socket options for the options level +.Dv SOL_LOCAL , +which can be set with .Xr setsockopt 2 and tested with .Xr getsockopt 2 : diff --git a/sys/kern/uipc_usrreq.c b/sys/kern/uipc_usrreq.c index efd592f82fe2..6261135f64ad 100644 --- a/sys/kern/uipc_usrreq.c +++ b/sys/kern/uipc_usrreq.c @@ -1470,7 +1470,7 @@ uipc_ctloutput(struct socket *so, struct sockopt *sopt) struct xucred xu; int error, optval; - if (sopt->sopt_level != 0) + if (sopt->sopt_level != SOL_LOCAL) return (EINVAL); unp = sotounpcb(so); diff --git a/sys/sys/un.h b/sys/sys/un.h index 3c408628ce0a..3a011aeef635 100644 --- a/sys/sys/un.h +++ b/sys/sys/un.h @@ -62,6 +62,8 @@ struct sockaddr_un { #if __BSD_VISIBLE +#define SOL_LOCAL 0 /* Options for local socket */ + /* Socket options. */ #define LOCAL_PEERCRED 1 /* retrieve peer credentials */ #define LOCAL_CREDS 2 /* pass credentials to receiver */ From ba8b64de05d0df84ad9064be950ca38bc7bafe7d Mon Sep 17 00:00:00 2001 From: Kyle Evans Date: Tue, 4 Aug 2020 02:06:49 +0000 Subject: [PATCH 038/141] regex(3): belatedly document REG_POSIX from r363734 My original patch included this documented, but it appears that I failed to include the manpage update. Do so now. --- lib/libc/regex/regex.3 | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/lib/libc/regex/regex.3 b/lib/libc/regex/regex.3 index 8959272e9891..d22dec1e87f7 100644 --- a/lib/libc/regex/regex.3 +++ b/lib/libc/regex/regex.3 @@ -32,7 +32,7 @@ .\" @(#)regex.3 8.4 (Berkeley) 3/20/94 .\" $FreeBSD$ .\" -.Dd May 25, 2016 +.Dd April 15, 2017 .Dt REGEX 3 .Os .Sh NAME @@ -183,6 +183,17 @@ compatible with but not specified by .St -p1003.2 , and should be used with caution in software intended to be portable to other systems. +.It Dv REG_POSIX +Compile only +.St -p1003.2 +compliant expressions. +This flag has no effect unless linking against +.Nm libregex . +This is an extension, +compatible with but not specified by +.St -p1003.2 , +and should be used with +caution in software intended to be portable to other systems. .El .Pp When successful, From 18a1e2e9b9f109a78c5a9274e4cfb4777801b4fb Mon Sep 17 00:00:00 2001 From: Kyle Evans Date: Tue, 4 Aug 2020 02:14:51 +0000 Subject: [PATCH 039/141] libregex: Implement a subset of the GNU extensions The entire patch-set is not yet mature enough for commit, but this usable subset is generally enough for googletest to be happy with and mostly map to some existing concepts, so they're not as invasive. The specific changes included here are: - Branching in BREs with \| - \w and \W for [[:alnum:]] and [^[:alnum:]] respectively - \s and \S for [[:space:]] and [^[:space:]] respectively - Additional quantifiers in BREs, \? and \+ (self-explanatory) There's some #ifdef'd out work for allowing empty branches as a match-all. This is a feature that's under assessment... future work will determine how standard this behavior is and act accordingly. --- lib/libc/regex/regcomp.c | 314 ++++++++++++++++++++++++++++----------- lib/libc/regex/regex2.h | 1 + 2 files changed, 230 insertions(+), 85 deletions(-) diff --git a/lib/libc/regex/regcomp.c b/lib/libc/regex/regcomp.c index 28bad13ac365..527d0cd3cb42 100644 --- a/lib/libc/regex/regcomp.c +++ b/lib/libc/regex/regcomp.c @@ -92,6 +92,7 @@ struct parse { const char *next; /* next character in RE */ const char *end; /* end of string (-> NUL normally) */ int error; /* has an error been seen? */ + int gnuext; sop *strip; /* malloced strip */ sopno ssize; /* malloced strip size (allocated) */ sopno slen; /* malloced strip length (used) */ @@ -131,7 +132,9 @@ static int p_count(struct parse *p); static void p_bracket(struct parse *p); static int p_range_cmp(wchar_t c1, wchar_t c2); static void p_b_term(struct parse *p, cset *cs); +static int p_b_pseudoclass(struct parse *p, char c); static void p_b_cclass(struct parse *p, cset *cs); +static void p_b_cclass_named(struct parse *p, cset *cs, const char[]); static void p_b_eclass(struct parse *p, cset *cs); static wint_t p_b_symbol(struct parse *p); static wint_t p_b_coll_elem(struct parse *p, wint_t endc); @@ -181,6 +184,7 @@ static char nuls[10]; /* place to point scanner in event of error */ #define SEESPEC(a) (p->bre ? SEETWO('\\', a) : SEE(a)) #define EAT(c) ((SEE(c)) ? (NEXT(), 1) : 0) #define EATTWO(a, b) ((SEETWO(a, b)) ? (NEXT2(), 1) : 0) +#define EATSPEC(a) (p->bre ? EATTWO('\\', a) : EAT(a)) #define NEXT() (p->next++) #define NEXT2() (p->next += 2) #define NEXTn(n) (p->next += (n)) @@ -270,14 +274,22 @@ regcomp_internal(regex_t * __restrict preg, p->pbegin[i] = 0; p->pend[i] = 0; } +#ifdef LIBREGEX + if (cflags®_POSIX) { + p->gnuext = false; + p->allowbranch = (cflags & REG_EXTENDED) != 0; + } else + p->gnuext = p->allowbranch = true; +#else + p->gnuext = false; + p->allowbranch = (cflags & REG_EXTENDED) != 0; +#endif if (cflags & REG_EXTENDED) { - p->allowbranch = true; p->bre = false; p->parse_expr = p_ere_exp; p->pre_parse = NULL; p->post_parse = NULL; } else { - p->allowbranch = false; p->bre = true; p->parse_expr = p_simp_re; p->pre_parse = p_bre_pre_parse; @@ -388,6 +400,10 @@ p_ere_exp(struct parse *p, struct branchc *bc) sopno pos; int count; int count2; +#ifdef LIBREGEX + int i; + int handled; +#endif sopno subno; int wascaret = 0; @@ -395,6 +411,9 @@ p_ere_exp(struct parse *p, struct branchc *bc) assert(MORE()); /* caller should have ensured this */ c = GETNEXT(); +#ifdef LIBREGEX + handled = 0; +#endif pos = HERE(); switch (c) { case '(': @@ -457,6 +476,47 @@ p_ere_exp(struct parse *p, struct branchc *bc) case '\\': (void)REQUIRE(MORE(), REG_EESCAPE); wc = WGETNEXT(); +#ifdef LIBREGEX + if (p->gnuext) { + handled = 1; + switch (wc) { + case 'W': + case 'w': + case 'S': + case 's': + p_b_pseudoclass(p, wc); + break; + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + i = wc - '0'; + assert(i < NPAREN); + if (p->pend[i] != 0) { + assert(i <= p->g->nsub); + EMIT(OBACK_, i); + assert(p->pbegin[i] != 0); + assert(OP(p->strip[p->pbegin[i]]) == OLPAREN); + assert(OP(p->strip[p->pend[i]]) == ORPAREN); + (void) dupl(p, p->pbegin[i]+1, p->pend[i]); + EMIT(O_BACK, i); + } else + SETERROR(REG_ESUBREG); + p->g->backrefs = 1; + break; + default: + handled = 0; + } + /* Don't proceed to the POSIX bits if we've already handled it */ + if (handled) + break; + } +#endif switch (wc) { case '<': EMIT(OBOW, 0); @@ -567,7 +627,7 @@ p_branch_eat_delim(struct parse *p, struct branchc *bc) (void)bc; nskip = 0; - while (EAT('|')) + while (EATSPEC('|')) ++nskip; return (nskip); } @@ -619,9 +679,15 @@ static bool p_branch_empty(struct parse *p, struct branchc *bc) { +#if defined(LIBREGEX) && defined(NOTYET) + if (bc->outer) + p->g->iflags |= EMPTBR; + return (true); +#else (void)bc; SETERROR(REG_EMPTY); return (false); +#endif } /* @@ -713,7 +779,11 @@ p_re(struct parse *p, } if (p->post_parse != NULL) p->post_parse(p, &bc); - (void) REQUIRE(HERE() != bc.start, REG_EMPTY); + (void) REQUIRE(p->gnuext || HERE() != bc.start, REG_EMPTY); +#ifdef LIBREGEX + if (HERE() == bc.start && !p_branch_empty(p, &bc)) + break; +#endif if (!p->allowbranch) break; /* @@ -740,101 +810,122 @@ static bool /* was the simple RE an unbackslashed $? */ p_simp_re(struct parse *p, struct branchc *bc) { int c; + int cc; /* convenient/control character */ int count; int count2; sopno pos; + bool handled; int i; wint_t wc; sopno subno; # define BACKSL (1<g->cflags®_NEWLINE) - nonnewline(p); - else - EMIT(OANY, 0); - break; - case '[': - p_bracket(p); - break; - case BACKSL|'<': - EMIT(OBOW, 0); - break; - case BACKSL|'>': - EMIT(OEOW, 0); - break; - case BACKSL|'{': - SETERROR(REG_BADRPT); - break; - case BACKSL|'(': - p->g->nsub++; - subno = p->g->nsub; - if (subno < NPAREN) - p->pbegin[subno] = HERE(); - EMIT(OLPAREN, subno); - /* the MORE here is an error heuristic */ - if (MORE() && !SEETWO('\\', ')')) - p_re(p, '\\', ')'); - if (subno < NPAREN) { - p->pend[subno] = HERE(); - assert(p->pend[subno] != 0); + cc = GETNEXT(); + c = BACKSL | cc; +#ifdef LIBREGEX + if (p->gnuext) { + handled = true; + switch (c) { + case BACKSL|'W': + case BACKSL|'w': + case BACKSL|'S': + case BACKSL|'s': + p_b_pseudoclass(p, cc); + break; + default: + handled = false; + } + } +#endif + } + if (!handled) { + switch (c) { + case '.': + if (p->g->cflags®_NEWLINE) + nonnewline(p); + else + EMIT(OANY, 0); + break; + case '[': + p_bracket(p); + break; + case BACKSL|'<': + EMIT(OBOW, 0); + break; + case BACKSL|'>': + EMIT(OEOW, 0); + break; + case BACKSL|'{': + SETERROR(REG_BADRPT); + break; + case BACKSL|'(': + p->g->nsub++; + subno = p->g->nsub; + if (subno < NPAREN) + p->pbegin[subno] = HERE(); + EMIT(OLPAREN, subno); + /* the MORE here is an error heuristic */ + if (MORE() && !SEETWO('\\', ')')) + p_re(p, '\\', ')'); + if (subno < NPAREN) { + p->pend[subno] = HERE(); + assert(p->pend[subno] != 0); + } + EMIT(ORPAREN, subno); + (void)REQUIRE(EATTWO('\\', ')'), REG_EPAREN); + break; + case BACKSL|')': /* should not get here -- must be user */ + SETERROR(REG_EPAREN); + break; + case BACKSL|'1': + case BACKSL|'2': + case BACKSL|'3': + case BACKSL|'4': + case BACKSL|'5': + case BACKSL|'6': + case BACKSL|'7': + case BACKSL|'8': + case BACKSL|'9': + i = (c&~BACKSL) - '0'; + assert(i < NPAREN); + if (p->pend[i] != 0) { + assert(i <= p->g->nsub); + EMIT(OBACK_, i); + assert(p->pbegin[i] != 0); + assert(OP(p->strip[p->pbegin[i]]) == OLPAREN); + assert(OP(p->strip[p->pend[i]]) == ORPAREN); + (void) dupl(p, p->pbegin[i]+1, p->pend[i]); + EMIT(O_BACK, i); + } else + SETERROR(REG_ESUBREG); + p->g->backrefs = 1; + break; + case '*': + /* + * Ordinary if used as the first character beyond BOL anchor of + * a (sub-)expression, counts as a bad repetition operator if it + * appears otherwise. + */ + (void)REQUIRE(bc->nchain == 0, REG_BADRPT); + /* FALLTHROUGH */ + default: + if (p->error != 0) + return (false); /* Definitely not $... */ + p->next--; + wc = WGETNEXT(); + if ((c & BACKSL) == 0 || may_escape(p, wc)) + ordinary(p, wc); + else + SETERROR(REG_EESCAPE); + break; } - EMIT(ORPAREN, subno); - (void)REQUIRE(EATTWO('\\', ')'), REG_EPAREN); - break; - case BACKSL|')': /* should not get here -- must be user */ - SETERROR(REG_EPAREN); - break; - case BACKSL|'1': - case BACKSL|'2': - case BACKSL|'3': - case BACKSL|'4': - case BACKSL|'5': - case BACKSL|'6': - case BACKSL|'7': - case BACKSL|'8': - case BACKSL|'9': - i = (c&~BACKSL) - '0'; - assert(i < NPAREN); - if (p->pend[i] != 0) { - assert(i <= p->g->nsub); - EMIT(OBACK_, i); - assert(p->pbegin[i] != 0); - assert(OP(p->strip[p->pbegin[i]]) == OLPAREN); - assert(OP(p->strip[p->pend[i]]) == ORPAREN); - (void) dupl(p, p->pbegin[i]+1, p->pend[i]); - EMIT(O_BACK, i); - } else - SETERROR(REG_ESUBREG); - p->g->backrefs = 1; - break; - case '*': - /* - * Ordinary if used as the first character beyond BOL anchor of - * a (sub-)expression, counts as a bad repetition operator if it - * appears otherwise. - */ - (void)REQUIRE(bc->nchain == 0, REG_BADRPT); - /* FALLTHROUGH */ - default: - if (p->error != 0) - return (false); /* Definitely not $... */ - p->next--; - wc = WGETNEXT(); - if ((c & BACKSL) == 0 || may_escape(p, wc)) - ordinary(p, wc); - else - SETERROR(REG_EESCAPE); - break; } if (EAT('*')) { /* implemented as +? */ @@ -843,6 +934,14 @@ p_simp_re(struct parse *p, struct branchc *bc) ASTERN(O_PLUS, pos); INSERT(OQUEST_, pos); ASTERN(O_QUEST, pos); +#ifdef LIBREGEX + } else if (p->gnuext && EATTWO('\\', '?')) { + INSERT(OQUEST_, pos); + ASTERN(O_QUEST, pos); + } else if (p->gnuext && EATTWO('\\', '+')) { + INSERT(OPLUS_, pos); + ASTERN(O_PLUS, pos); +#endif } else if (EATTWO('\\', '{')) { count = p_count(p); if (EAT(',')) { @@ -1034,6 +1133,41 @@ p_b_term(struct parse *p, cset *cs) } } +/* + - p_b_pseudoclass - parse a pseudo-class (\w, \W, \s, \S) + == static int p_b_pseudoclass(struct parse *p, char c) + */ +static int +p_b_pseudoclass(struct parse *p, char c) { + cset *cs; + + if ((cs = allocset(p)) == NULL) + return(0); + + if (p->g->cflags®_ICASE) + cs->icase = 1; + + switch (c) { + case 'W': + cs->invert = 1; + /* PASSTHROUGH */ + case 'w': + p_b_cclass_named(p, cs, "alnum"); + break; + case 'S': + cs->invert = 1; + /* PASSTHROUGH */ + case 's': + p_b_cclass_named(p, cs, "space"); + break; + default: + return(0); + } + + EMIT(OANYOF, (int)(cs - p->g->sets)); + return(1); +} + /* - p_b_cclass - parse a character-class name and deal with it == static void p_b_cclass(struct parse *p, cset *cs); @@ -1043,7 +1177,6 @@ p_b_cclass(struct parse *p, cset *cs) { const char *sp = p->next; size_t len; - wctype_t wct; char clname[16]; while (MORE() && isalpha((uch)PEEK())) @@ -1055,6 +1188,17 @@ p_b_cclass(struct parse *p, cset *cs) } memcpy(clname, sp, len); clname[len] = '\0'; + + p_b_cclass_named(p, cs, clname); +} +/* + - p_b_cclass_named - deal with a named character class + == static void p_b_cclass_named(struct parse *p, cset *cs, const char []); + */ +static void +p_b_cclass_named(struct parse *p, cset *cs, const char clname[]) { + wctype_t wct; + if ((wct = wctype(clname)) == 0) { SETERROR(REG_ECTYPE); return; diff --git a/lib/libc/regex/regex2.h b/lib/libc/regex/regex2.h index a1a37172a55b..d608dc603683 100644 --- a/lib/libc/regex/regex2.h +++ b/lib/libc/regex/regex2.h @@ -182,6 +182,7 @@ struct re_guts { # define USEBOL 01 /* used ^ */ # define USEEOL 02 /* used $ */ # define BAD 04 /* something wrong */ +# define EMPTBR 010 /* empty branch present */ int nbol; /* number of ^ used */ int neol; /* number of $ used */ char *must; /* match must contain this string */ From 61898cde69374d5a9994e2074605bc4101aff72d Mon Sep 17 00:00:00 2001 From: Kyle Evans Date: Tue, 4 Aug 2020 02:16:43 +0000 Subject: [PATCH 040/141] libregex: disable some of the unimplemented test cases for now This should allow the tests to actually pass. Future work will uncomment the unimplemented tests as they're implemented. --- lib/libregex/tests/gnuext.in | 22 ++++++++++++---------- lib/libregex/tests/libregex_test.sh | 4 ---- 2 files changed, 12 insertions(+), 14 deletions(-) diff --git a/lib/libregex/tests/gnuext.in b/lib/libregex/tests/gnuext.in index 86afe499f50a..7d9e4823a67f 100644 --- a/lib/libregex/tests/gnuext.in +++ b/lib/libregex/tests/gnuext.in @@ -17,14 +17,16 @@ a\|b\|c b abc a \s\+ b aSNTb SNT # Word boundaries (\b, \B, \<, \>, \`, \') # (is/not boundary, start/end word, start/end subject string) -\babc\b & abc +# Most of these are disabled for the moment, and will be re-enabled as +# we become feature complete. +#\babc\b & abc \ & abc -\Babc\B & abc -\B[abc]\B & b -\B[abc]+ - bc -\B[abc]\+ b bc -\`abc\' & abc abc -\`.+\' - abNc abNc -\`.\+\' b abNc abNc -(\`a) - Na -(a\') - aN +#\Babc\B & abc +#\B[abc]\B & b +#\B[abc]+ - bc +#\B[abc]\+ b bc +#\`abc\' & abc abc +#\`.+\' - abNc abNc +#\`.\+\' b abNc abNc +#(\`a) - Na +#(a\') - aN diff --git a/lib/libregex/tests/libregex_test.sh b/lib/libregex/tests/libregex_test.sh index 9e41db67e10b..5e4e49c3ad38 100755 --- a/lib/libregex/tests/libregex_test.sh +++ b/lib/libregex/tests/libregex_test.sh @@ -30,10 +30,6 @@ check() { local dataname="${1}"; shift - if [ "${dataname}" == "gnuext" ]; then - atf_expect_fail "GNU extensions are not currently implemented" - fi - prog="$(atf_get_srcdir)/h_regex" data="$(atf_get_srcdir)/data/${dataname}.in" From b4af4f93c682e445bf159f0d1ec90b636296c946 Mon Sep 17 00:00:00 2001 From: Kyle Evans Date: Tue, 4 Aug 2020 02:18:24 +0000 Subject: [PATCH 041/141] gtest: link against libregex for GNU extensions gtest tests want to use \w ([[:alnum:]]) at the very least, which was causing them to fail after r363679. Start linking against libregex so that this shorthand is implemented. PR: 248452 --- lib/googletest/gtest/Makefile | 2 +- share/mk/src.libnames.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/googletest/gtest/Makefile b/lib/googletest/gtest/Makefile index b580c33eb45a..103bf84db5b2 100644 --- a/lib/googletest/gtest/Makefile +++ b/lib/googletest/gtest/Makefile @@ -45,7 +45,7 @@ INTERNAL_CUSTOM_INCS+= gtest/internal/custom/gtest.h SRCS+= gtest-all.cc -LIBADD+= pthread +LIBADD+= pthread regex HAS_TESTS= SUBDIR.${MK_TESTS}+= tests diff --git a/share/mk/src.libnames.mk b/share/mk/src.libnames.mk index f47e50fb94d5..c2c3d6c4110b 100644 --- a/share/mk/src.libnames.mk +++ b/share/mk/src.libnames.mk @@ -320,7 +320,7 @@ _DP_dpv= dialog figpar util ncursesw _DP_dialog= ncursesw m _DP_cuse= pthread _DP_atf_cxx= atf_c -_DP_gtest= pthread +_DP_gtest= pthread regex _DP_gmock= gtest _DP_gmock_main= gmock _DP_gtest_main= gtest From 1546dc216f090ce326f5bbdff1211f3661643bfc Mon Sep 17 00:00:00 2001 From: Kyle Evans Date: Tue, 4 Aug 2020 02:20:15 +0000 Subject: [PATCH 042/141] Re-enable disabled googletest-port-test tests after r363820 gtest now links against libregex here, and the tests pass locally. PR: 248452 --- contrib/googletest/googletest/test/googletest-port-test.cc | 6 ------ 1 file changed, 6 deletions(-) diff --git a/contrib/googletest/googletest/test/googletest-port-test.cc b/contrib/googletest/googletest/test/googletest-port-test.cc index 0b68d72e75bc..399316f95b63 100644 --- a/contrib/googletest/googletest/test/googletest-port-test.cc +++ b/contrib/googletest/googletest/test/googletest-port-test.cc @@ -403,8 +403,6 @@ typedef testing::Types< TYPED_TEST_CASE(RETest, StringTypes); // Tests RE's implicit constructors. -/* -https://bugs.freebsd.org/248452 TYPED_TEST(RETest, ImplicitConstructorWorks) { const RE empty(TypeParam("")); EXPECT_STREQ("", empty.pattern()); @@ -415,7 +413,6 @@ TYPED_TEST(RETest, ImplicitConstructorWorks) { const RE normal(TypeParam(".*(\\w+)")); EXPECT_STREQ(".*(\\w+)", normal.pattern()); } -*/ // Tests that RE's constructors reject invalid regular expressions. TYPED_TEST(RETest, RejectsInvalidRegex) { @@ -864,8 +861,6 @@ TEST(MatchRegexAnywhereTest, ReturnsTrueWhenMatchingNonPrefix) { } // Tests RE's implicit constructors. -/* -https://bugs.freebsd.org/248452 TEST(RETest, ImplicitConstructorWorks) { const RE empty(""); EXPECT_STREQ("", empty.pattern()); @@ -873,7 +868,6 @@ TEST(RETest, ImplicitConstructorWorks) { const RE simple("hello"); EXPECT_STREQ("hello", simple.pattern()); } -*/ // Tests that RE's constructors reject invalid regular expressions. TEST(RETest, RejectsInvalidRegex) { From cab7d341dcd98138443bbdb51649f966093a3a84 Mon Sep 17 00:00:00 2001 From: Kyle Evans Date: Tue, 4 Aug 2020 02:47:24 +0000 Subject: [PATCH 043/141] bsdgrep: switch to libregex for GNU_GREP_COMPAT libregex is incomplete, but it's a bit less buggy than the in-base libgnuregex and mostly OK. While here, rename -DIWTH_GNU -> -DWITH_GNU_COMPAT; the option implies that we're compatible with the GNU counterpart, not that we're including GNU anything. --- usr.bin/grep/Makefile | 4 ++-- usr.bin/grep/grep.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/usr.bin/grep/Makefile b/usr.bin/grep/Makefile index c3b07b9252c6..b51f51c8bd5e 100644 --- a/usr.bin/grep/Makefile +++ b/usr.bin/grep/Makefile @@ -61,8 +61,8 @@ MLINKS+= grep.1 egrep.1 \ .endif .if ${MK_GNU_GREP_COMPAT} != "no" -CFLAGS+= -I${SYSROOT:U${DESTDIR}}/usr/include/gnu -DWITH_GNU -LIBADD+= gnuregex +CFLAGS+= -DWITH_GNU_COMPAT +LIBADD+= regex .endif HAS_TESTS= diff --git a/usr.bin/grep/grep.c b/usr.bin/grep/grep.c index 731e46bb112e..576ea96d4f96 100644 --- a/usr.bin/grep/grep.c +++ b/usr.bin/grep/grep.c @@ -555,7 +555,7 @@ main(int argc, char *argv[]) filebehave = FILE_MMAP; break; case 'V': -#ifdef WITH_GNU +#ifdef WITH_GNU_COMPAT printf(errstr[9], getprogname(), VERSION); #else printf(errstr[8], getprogname(), VERSION); From eb578fec7fd0a044097a44f60e2b2f9137894bea Mon Sep 17 00:00:00 2001 From: Kyle Evans Date: Tue, 4 Aug 2020 03:43:28 +0000 Subject: [PATCH 044/141] Ensure libregex is built in time for googletest In lib/Makefile, we document the dependency with SUBDIR_DEPEND For buildworld orchestration, just prebuild libregex if GOOGLETEST is enabled. googletest will get built in a later pass. --- Makefile.inc1 | 4 ++++ lib/Makefile | 1 + 2 files changed, 5 insertions(+) diff --git a/Makefile.inc1 b/Makefile.inc1 index 805a42befb48..94fd5ef5c515 100644 --- a/Makefile.inc1 +++ b/Makefile.inc1 @@ -2741,6 +2741,10 @@ _prebuild_libs+= gnu/lib/libdialog gnu/lib/libdialog__L: lib/msun__L lib/ncurses/ncursesw__L .endif +.if ${MK_GOOGLETEST} != "no" +_prebuild_libs+= lib/libregex +.endif + .if ${MK_LIBCPLUSPLUS} != "no" _prebuild_libs+= lib/libc++ .endif diff --git a/lib/Makefile b/lib/Makefile index 3c29635ffda8..45c10e7e5c57 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -107,6 +107,7 @@ SUBDIR= ${SUBDIR_BOOTSTRAP} \ # libraries, those libraries should be listed as build order dependencies here. SUBDIR_DEPEND_geom= libufs +SUBDIR_DEPEND_googletest= libregex SUBDIR_DEPEND_libarchive= libz libbz2 libexpat liblzma libmd libzstd SUBDIR_DEPEND_libauditdm= libbsm SUBDIR_DEPEND_libbsnmp= ${_libnetgraph} From 74f32f086b05e181ddfec349ef5c85cc736de36c Mon Sep 17 00:00:00 2001 From: Gordon Bergling Date: Tue, 4 Aug 2020 08:46:28 +0000 Subject: [PATCH 045/141] directory(3): Add an ERRORS section - Add an ERRORS section for opendir(3) and closedir(3) - Document also the errors of readdir(3), readdir_r(3) and telldir(3) - Convert the code sample into an EXAMPLES section PR: 75711 Submitted by: abc Reviewed by: 0mp, bcr, jilles Approved by: 0mp, bcr, jilles Obtained from: partial from OpenBSD MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D25892 --- lib/libc/gen/directory.3 | 74 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/lib/libc/gen/directory.3 b/lib/libc/gen/directory.3 index 835236e50066..f517a00386c6 100644 --- a/lib/libc/gen/directory.3 +++ b/lib/libc/gen/directory.3 @@ -28,7 +28,7 @@ .\" @(#)directory.3 8.1 (Berkeley) 6/4/93 .\" $FreeBSD$ .\" -.Dd April 30, 2019 +.Dd August 1, 2020 .Dt DIRECTORY 3 .Os .Sh NAME @@ -242,7 +242,7 @@ returns the integer file descriptor associated with the named .Em directory stream , see .Xr open 2 . -.Pp +.Sh EXAMPLES Sample code which searches a directory for entry ``name'' is: .Bd -literal -offset indent dirp = opendir("."); @@ -258,6 +258,76 @@ while ((dp = readdir(dirp)) != NULL) { (void)closedir(dirp); return (NOT_FOUND); .Ed +.Sh ERRORS +The +.Fn opendir +function will fail if: +.Bl -tag -width Er +.It Bq Er EACCES +Search permission is denied for the component of the path prefix of +.Fa filename +or read permission is denied for +.Fa filename . +.It Bq Er ELOOP +A loop exists in symbolic links encountered during resolution of the +.Fa filename +argument. +.It Bq Er ENAMETOOLONG +The length of the +.Fa filename +argument exceeds +.Brq Dv PATH_MAX +or +a pathname component is longer than +.Brq Dv NAME_MAX . +.It Bq Er ENOENT +A component of +.Fa filename +does not name an existing directory or +.Fa filename +is an empty string. +.It Bq Er ENOTDIR +A component of +.Fa filename +is not a directory. +.El +.Pp +The +.Fn fdopendir +function will fail if: +.Bl -tag -width Er +.It Bq Er EBADF +The +.Fa fd +argument is not a valid file descriptor open for reading. +.It Bq Er ENOTDIR +The descriptor +.Fa fd +is not associated with a directory. +.El +.Pp +The +.Fn readdir +and +.Fn readdir_r +functions may also fail and set +.Va errno +for any of the errors specified for the routine +.Xr getdents 2 . +.Pp +The +.Fn telldir +function may also fail and set +.Va errno +for any of the errors specified for the routine +.Xr realloc 3 . +.Pp +The +.Fn closedir +function may also fail and set +.Va errno +for any of the errors specified for the routine +.Xr close 2 . .Sh SEE ALSO .Xr close 2 , .Xr lseek 2 , From 3422ca83ba48e5c9174542a2d3ba8225275779a6 Mon Sep 17 00:00:00 2001 From: Gordon Bergling Date: Tue, 4 Aug 2020 11:13:13 +0000 Subject: [PATCH 046/141] iovctl.conf(5): Use Lk macro for the URL of the UCL website PR: 248334 Reported by: chuck at tuffli dot net Reviewed by: bcr, 0mp Approved by: bcr, 0mp MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D25891 --- usr.sbin/iovctl/iovctl.conf.5 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usr.sbin/iovctl/iovctl.conf.5 b/usr.sbin/iovctl/iovctl.conf.5 index ad8661280402..a9630f3b3b13 100644 --- a/usr.sbin/iovctl/iovctl.conf.5 +++ b/usr.sbin/iovctl/iovctl.conf.5 @@ -51,7 +51,7 @@ The .Nm file uses UCL format. UCL syntax is documented at the official UCL website: -http://github.com/vstakhov/libucl. +.Lk http://github.com/vstakhov/libucl . .Pp There are three types of sections in the .Nm From 96ad26eefb45c365d423b6dd9be05a1d70958dc1 Mon Sep 17 00:00:00 2001 From: Mark Johnston Date: Tue, 4 Aug 2020 13:58:36 +0000 Subject: [PATCH 047/141] Remove free_domain() and uma_zfree_domain(). These functions were introduced before UMA started ensuring that freed memory gets placed in domain-local caches. They no longer serve any purpose since UMA now provides their functionality by default. Remove them to simplyify the kernel memory allocator interfaces a bit. Reviewed by: cem, kib Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D25937 --- ObsoleteFiles.inc | 4 ++++ share/man/man9/Makefile | 2 -- share/man/man9/malloc.9 | 6 +----- share/man/man9/zone.9 | 9 +-------- sys/dev/hwpmc/hwpmc_mod.c | 14 +++++++------- sys/dev/ioat/ioat.c | 2 +- sys/dev/iommu/busdma_iommu.c | 8 ++++---- sys/dev/nvme/nvme_qpair.c | 4 ++-- sys/kern/kern_malloc.c | 34 ---------------------------------- sys/kern/subr_bus.c | 6 +++--- sys/net/if.c | 5 +---- sys/sys/malloc.h | 1 - sys/vm/uma.h | 10 ---------- sys/vm/uma_core.c | 18 ------------------ sys/x86/x86/busdma_bounce.c | 8 ++++---- 15 files changed, 28 insertions(+), 103 deletions(-) diff --git a/ObsoleteFiles.inc b/ObsoleteFiles.inc index 6db60ca13866..160de5f37f4e 100644 --- a/ObsoleteFiles.inc +++ b/ObsoleteFiles.inc @@ -36,6 +36,10 @@ # xargs -n1 | sort | uniq -d; # done +# 20200803: remove free_domain(9) and uma_zfree_domain(9) +OLD_FILES+=usr/share/man/man9/free_domain.9.gz +OLD_FILES+=usr/share/man/man9/uma_zfree_domain.9.gz + # 20200729: remove long expired serial drivers OLD_FILES+=usr/share/man/man4/cy.4.gz OLD_FILES+=usr/share/man/man4/rc.4.gz diff --git a/share/man/man9/Makefile b/share/man/man9/Makefile index ee065b020999..01aaed947fa1 100644 --- a/share/man/man9/Makefile +++ b/share/man/man9/Makefile @@ -1378,7 +1378,6 @@ MLINKS+=make_dev.9 destroy_dev.9 \ make_dev.9 make_dev_s.9 MLINKS+=malloc.9 free.9 \ malloc.9 malloc_domainset.9 \ - malloc.9 free_domain.9 \ malloc.9 mallocarray.9 \ malloc.9 MALLOC_DECLARE.9 \ malloc.9 MALLOC_DEFINE.9 \ @@ -2343,7 +2342,6 @@ MLINKS+=zone.9 uma.9 \ zone.9 uma_zdestroy.9 \ zone.9 uma_zfree.9 \ zone.9 uma_zfree_arg.9 \ - zone.9 uma_zfree_domain.9 \ zone.9 uma_zfree_pcpu.9 \ zone.9 uma_zfree_pcpu_arg.9 \ zone.9 uma_zone_get_cur.9 \ diff --git a/share/man/man9/malloc.9 b/share/man/man9/malloc.9 index 7a5e36e6243c..c10a007ec2cb 100644 --- a/share/man/man9/malloc.9 +++ b/share/man/man9/malloc.9 @@ -29,7 +29,7 @@ .\" $NetBSD: malloc.9,v 1.3 1996/11/11 00:05:11 lukem Exp $ .\" $FreeBSD$ .\" -.Dd October 30, 2018 +.Dd August 3, 2020 .Dt MALLOC 9 .Os .Sh NAME @@ -64,8 +64,6 @@ .In sys/domainset.h .Ft void * .Fn malloc_domainset "size_t size" "struct malloc_type *type" "struct domainset *ds" "int flags" -.Ft void -.Fn free_domain "void *addr" "struct malloc_type *type" .Sh DESCRIPTION The .Fn malloc @@ -81,8 +79,6 @@ domain using the specified domain selection policy. See .Xr domainset 9 for some example policies. -Memory allocated with this function should be returned with -.Fn free_domain . .Pp The .Fn mallocarray diff --git a/share/man/man9/zone.9 b/share/man/man9/zone.9 index 756cf77f8a83..8efcf00c7b24 100644 --- a/share/man/man9/zone.9 +++ b/share/man/man9/zone.9 @@ -25,7 +25,7 @@ .\" .\" $FreeBSD$ .\" -.Dd February 4, 2020 +.Dd August 3, 2020 .Dt UMA 9 .Os .Sh NAME @@ -86,8 +86,6 @@ typedef void (*uma_free)(void *item, vm_size_t size, uint8_t pflag); .Ft void .Fn uma_zfree_arg "uma_zone_t zone" "void *item" "void *arg" .Ft void -.Fn uma_zfree_domain "uma_zone_t zone" "void *item" "void *arg" -.Ft void .Fn uma_zfree_pcpu "uma_zone_t zone" "void *item" .Ft void .Fn uma_zfree_pcpu_arg "uma_zone_t zone" "void *item" "void *arg" @@ -394,11 +392,6 @@ function allows callers to specify a fixed domain to allocate from. This uses a guaranteed but slow path in the allocator which reduces concurrency. -The -.Fn uma_zfree_domain -function should be used to return memory allocated in this fashion. -This function infers the domain from the pointer and does not require it as an -argument. .Pp The .Fn uma_zone_prealloc diff --git a/sys/dev/hwpmc/hwpmc_mod.c b/sys/dev/hwpmc/hwpmc_mod.c index d343bdced22d..3e4f0de2c7e4 100644 --- a/sys/dev/hwpmc/hwpmc_mod.c +++ b/sys/dev/hwpmc/hwpmc_mod.c @@ -5893,13 +5893,13 @@ pmc_cleanup(void) KASSERT(pmc_pcpu[cpu]->pc_sb[PMC_UR] != NULL, ("[pmc,%d] Null userret cpu sample buffer cpu=%d", __LINE__, cpu)); - free_domain(pmc_pcpu[cpu]->pc_sb[PMC_HR]->ps_callchains, M_PMC); - free_domain(pmc_pcpu[cpu]->pc_sb[PMC_HR], M_PMC); - free_domain(pmc_pcpu[cpu]->pc_sb[PMC_SR]->ps_callchains, M_PMC); - free_domain(pmc_pcpu[cpu]->pc_sb[PMC_SR], M_PMC); - free_domain(pmc_pcpu[cpu]->pc_sb[PMC_UR]->ps_callchains, M_PMC); - free_domain(pmc_pcpu[cpu]->pc_sb[PMC_UR], M_PMC); - free_domain(pmc_pcpu[cpu], M_PMC); + free(pmc_pcpu[cpu]->pc_sb[PMC_HR]->ps_callchains, M_PMC); + free(pmc_pcpu[cpu]->pc_sb[PMC_HR], M_PMC); + free(pmc_pcpu[cpu]->pc_sb[PMC_SR]->ps_callchains, M_PMC); + free(pmc_pcpu[cpu]->pc_sb[PMC_SR], M_PMC); + free(pmc_pcpu[cpu]->pc_sb[PMC_UR]->ps_callchains, M_PMC); + free(pmc_pcpu[cpu]->pc_sb[PMC_UR], M_PMC); + free(pmc_pcpu[cpu], M_PMC); } free(pmc_pcpu, M_PMC); diff --git a/sys/dev/ioat/ioat.c b/sys/dev/ioat/ioat.c index f9660a2b233d..7e6a33a4285b 100644 --- a/sys/dev/ioat/ioat.c +++ b/sys/dev/ioat/ioat.c @@ -1578,7 +1578,7 @@ ioat_free_ring(struct ioat_softc *ioat, uint32_t size, struct ioat_descriptor *ring) { - free_domain(ring, M_IOAT); + free(ring, M_IOAT); } static struct ioat_descriptor * diff --git a/sys/dev/iommu/busdma_iommu.c b/sys/dev/iommu/busdma_iommu.c index dd1309fd7dc6..428880f85d01 100644 --- a/sys/dev/iommu/busdma_iommu.c +++ b/sys/dev/iommu/busdma_iommu.c @@ -410,7 +410,7 @@ iommu_bus_dma_tag_destroy(bus_dma_tag_t dmat1) 1) { if (dmat == dmat->ctx->tag) iommu_free_ctx(dmat->ctx); - free_domain(dmat->segments, M_IOMMU_DMAMAP); + free(dmat->segments, M_IOMMU_DMAMAP); free(dmat, M_DEVBUF); dmat = parent; } else @@ -447,7 +447,7 @@ iommu_bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp) tag->common.nsegments, M_IOMMU_DMAMAP, DOMAINSET_PREF(tag->common.domain), M_NOWAIT); if (tag->segments == NULL) { - free_domain(map, M_IOMMU_DMAMAP); + free(map, M_IOMMU_DMAMAP); *mapp = NULL; return (ENOMEM); } @@ -479,7 +479,7 @@ iommu_bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map1) return (EBUSY); } IOMMU_DOMAIN_UNLOCK(domain); - free_domain(map, M_IOMMU_DMAMAP); + free(map, M_IOMMU_DMAMAP); } tag->map_count--; return (0); @@ -537,7 +537,7 @@ iommu_bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map1) map = (struct bus_dmamap_iommu *)map1; if ((map->flags & BUS_DMAMAP_IOMMU_MALLOC) != 0) { - free_domain(vaddr, M_DEVBUF); + free(vaddr, M_DEVBUF); map->flags &= ~BUS_DMAMAP_IOMMU_MALLOC; } else { KASSERT((map->flags & BUS_DMAMAP_IOMMU_KMEM_ALLOC) != 0, diff --git a/sys/dev/nvme/nvme_qpair.c b/sys/dev/nvme/nvme_qpair.c index bd2e65857d2f..863b9f58ac3b 100644 --- a/sys/dev/nvme/nvme_qpair.c +++ b/sys/dev/nvme/nvme_qpair.c @@ -819,7 +819,7 @@ nvme_qpair_destroy(struct nvme_qpair *qpair) } if (qpair->act_tr) { - free_domain(qpair->act_tr, M_NVME); + free(qpair->act_tr, M_NVME); qpair->act_tr = NULL; } @@ -828,7 +828,7 @@ nvme_qpair_destroy(struct nvme_qpair *qpair) TAILQ_REMOVE(&qpair->free_tr, tr, tailq); bus_dmamap_destroy(qpair->dma_tag_payload, tr->payload_dma_map); - free_domain(tr, M_NVME); + free(tr, M_NVME); } if (qpair->cmd != NULL) { diff --git a/sys/kern/kern_malloc.c b/sys/kern/kern_malloc.c index 22c4a8f9e195..300a1692e7df 100644 --- a/sys/kern/kern_malloc.c +++ b/sys/kern/kern_malloc.c @@ -862,40 +862,6 @@ zfree(void *addr, struct malloc_type *mtp) malloc_type_freed(mtp, size); } -void -free_domain(void *addr, struct malloc_type *mtp) -{ - uma_zone_t zone; - uma_slab_t slab; - u_long size; - -#ifdef MALLOC_DEBUG - if (free_dbg(&addr, mtp) != 0) - return; -#endif - - /* free(NULL, ...) does nothing */ - if (addr == NULL) - return; - - vtozoneslab((vm_offset_t)addr & (~UMA_SLAB_MASK), &zone, &slab); - if (slab == NULL) - panic("free_domain: address %p(%p) has not been allocated.\n", - addr, (void *)((u_long)addr & (~UMA_SLAB_MASK))); - - if (__predict_true(!malloc_large_slab(slab))) { - size = zone->uz_size; -#ifdef INVARIANTS - free_save_type(addr, mtp, size); -#endif - uma_zfree_domain(zone, addr, slab); - } else { - size = malloc_large_size(slab); - free_large(addr, size); - } - malloc_type_freed(mtp, size); -} - /* * realloc: change the size of a memory block */ diff --git a/sys/kern/subr_bus.c b/sys/kern/subr_bus.c index ca99201577d2..4bf772a9a94a 100644 --- a/sys/kern/subr_bus.c +++ b/sys/kern/subr_bus.c @@ -2542,7 +2542,7 @@ void device_set_softc(device_t dev, void *softc) { if (dev->softc && !(dev->flags & DF_EXTERNALSOFTC)) - free_domain(dev->softc, M_BUS_SC); + free(dev->softc, M_BUS_SC); dev->softc = softc; if (dev->softc) dev->flags |= DF_EXTERNALSOFTC; @@ -2559,7 +2559,7 @@ device_set_softc(device_t dev, void *softc) void device_free_softc(void *softc) { - free_domain(softc, M_BUS_SC); + free(softc, M_BUS_SC); } /** @@ -2826,7 +2826,7 @@ device_set_driver(device_t dev, driver_t *driver) return (0); if (dev->softc && !(dev->flags & DF_EXTERNALSOFTC)) { - free_domain(dev->softc, M_BUS_SC); + free(dev->softc, M_BUS_SC); dev->softc = NULL; } device_set_desc(dev, NULL); diff --git a/sys/net/if.c b/sys/net/if.c index 59dd38267cfc..a837be09544a 100644 --- a/sys/net/if.c +++ b/sys/net/if.c @@ -629,10 +629,7 @@ if_free_internal(struct ifnet *ifp) free(ifp->if_description, M_IFDESCR); free(ifp->if_hw_addr, M_IFADDR); - if (ifp->if_numa_domain == IF_NODOM) - free(ifp, M_IFNET); - else - free_domain(ifp, M_IFNET); + free(ifp, M_IFNET); } static void diff --git a/sys/sys/malloc.h b/sys/sys/malloc.h index 5714e9b73db8..403d85feecb8 100644 --- a/sys/sys/malloc.h +++ b/sys/sys/malloc.h @@ -180,7 +180,6 @@ void *contigmalloc_domainset(unsigned long size, struct malloc_type *type, __malloc_like __result_use_check __alloc_size(1) __alloc_align(7); void free(void *addr, struct malloc_type *type); void zfree(void *addr, struct malloc_type *type); -void free_domain(void *addr, struct malloc_type *type); void *malloc(size_t size, struct malloc_type *type, int flags) __malloc_like __result_use_check __alloc_size(1); /* diff --git a/sys/vm/uma.h b/sys/vm/uma.h index 70f598dfbfee..8de57c35a04e 100644 --- a/sys/vm/uma.h +++ b/sys/vm/uma.h @@ -386,16 +386,6 @@ void uma_zfree_pcpu_arg(uma_zone_t zone, void *item, void *arg); /* Use with SMR zones. */ void uma_zfree_smr(uma_zone_t zone, void *item); -/* - * Frees an item back to the specified zone's domain specific pool. - * - * Arguments: - * zone The zone the item was originally allocated out of. - * item The memory to be freed. - * arg Argument passed to the destructor - */ -void uma_zfree_domain(uma_zone_t zone, void *item, void *arg); - /* * Frees an item back to a zone without supplying an argument * diff --git a/sys/vm/uma_core.c b/sys/vm/uma_core.c index 17da063e3cff..d90423bd9c5f 100644 --- a/sys/vm/uma_core.c +++ b/sys/vm/uma_core.c @@ -4338,24 +4338,6 @@ cache_free(uma_zone_t zone, uma_cache_t cache, void *udata, void *item, return (true); } -void -uma_zfree_domain(uma_zone_t zone, void *item, void *udata) -{ - - /* Enable entropy collection for RANDOM_ENABLE_UMA kernel option */ - random_harvest_fast_uma(&zone, sizeof(zone), RANDOM_UMA); - - CTR2(KTR_UMA, "uma_zfree_domain zone %s(%p)", zone->uz_name, zone); - - KASSERT(curthread->td_critnest == 0 || SCHEDULER_STOPPED(), - ("uma_zfree_domain: called with spinlock or critical section held")); - - /* uma_zfree(..., NULL) does nothing, to match free(9). */ - if (item == NULL) - return; - zone_free_item(zone, item, udata, SKIP_NONE); -} - static void slab_free_item(uma_zone_t zone, uma_slab_t slab, void *item) { diff --git a/sys/x86/x86/busdma_bounce.c b/sys/x86/x86/busdma_bounce.c index 01ad5be99932..59c4ed206b37 100644 --- a/sys/x86/x86/busdma_bounce.c +++ b/sys/x86/x86/busdma_bounce.c @@ -271,7 +271,7 @@ bounce_bus_dma_tag_destroy(bus_dma_tag_t dmat) atomic_subtract_int(&dmat->common.ref_count, 1); if (dmat->common.ref_count == 0) { if (dmat->segments != NULL) - free_domain(dmat->segments, M_DEVBUF); + free(dmat->segments, M_DEVBUF); free(dmat, M_DEVBUF); /* * Last reference count, so @@ -387,7 +387,7 @@ bounce_bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map) } if (dmat->bounce_zone) dmat->bounce_zone->map_count--; - free_domain(map, M_DEVBUF); + free(map, M_DEVBUF); } dmat->map_count--; CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat); @@ -504,7 +504,7 @@ bounce_bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map) if (map != NULL) panic("bus_dmamem_free: Invalid map freed\n"); if ((dmat->bounce_flags & BUS_DMA_KMEM_ALLOC) == 0) - free_domain(vaddr, M_DEVBUF); + free(vaddr, M_DEVBUF); else kmem_free((vm_offset_t)vaddr, dmat->common.maxsize); CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat, @@ -1188,7 +1188,7 @@ alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages) M_DEVBUF, DOMAINSET_PREF(dmat->common.domain), M_NOWAIT, 0ul, bz->lowaddr, PAGE_SIZE, 0); if (bpage->vaddr == 0) { - free_domain(bpage, M_DEVBUF); + free(bpage, M_DEVBUF); break; } bpage->busaddr = pmap_kextract(bpage->vaddr); From 16fdd8b7ad2945520853dd149110796fb9e66120 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 4 Aug 2020 14:42:38 +0000 Subject: [PATCH 048/141] linuxkpi: Add linux/sizes.h This file contain some defines for common sizes. Sponsored-by: The FreeBSD Foundation Reviewed by: hselasky, emaste MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D25941 --- .../linuxkpi/common/include/linux/sizes.h | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 sys/compat/linuxkpi/common/include/linux/sizes.h diff --git a/sys/compat/linuxkpi/common/include/linux/sizes.h b/sys/compat/linuxkpi/common/include/linux/sizes.h new file mode 100644 index 000000000000..a180cee5f022 --- /dev/null +++ b/sys/compat/linuxkpi/common/include/linux/sizes.h @@ -0,0 +1,51 @@ +/*- + * Copyright (c) 2020 The FreeBSD Foundation + * + * This software was developed by Emmanuel Vadot under sponsorship + * from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef __LINUX_SIZES_H__ +#define __LINUX_SIZES_H__ + +#define SZ_1K (1024 * 1) +#define SZ_4K (1024 * 4) +#define SZ_8K (1024 * 8) +#define SZ_16K (1024 * 16) +#define SZ_32K (1024 * 32) +#define SZ_64K (1024 * 64) +#define SZ_128K (1024 * 128) +#define SZ_256K (1024 * 256) +#define SZ_512K (1024 * 512) + +#define SZ_1M (1024 * 1024 * 1) +#define SZ_2M (1024 * 1024 * 2) +#define SZ_8M (1024 * 1024 * 8) +#define SZ_16M (1024 * 1024 * 16) +#define SZ_32M (1024 * 1024 * 32) +#define SZ_64M (1024 * 1024 * 64) + +#endif From 7237a74f3b8f88abe74b03d78f272b104ab33a60 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 4 Aug 2020 14:44:16 +0000 Subject: [PATCH 049/141] linuxkpi: Add kref_put_lock Same as kref_put but in addition to calling the rel function it will acquire the lock first. Sponsored by: The FreeBSD Foundation Reviewed by: hselasky, emaste Differential Revision: https://reviews.freebsd.org/D25942 --- sys/compat/linuxkpi/common/include/linux/kref.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/sys/compat/linuxkpi/common/include/linux/kref.h b/sys/compat/linuxkpi/common/include/linux/kref.h index 7411694ad650..cfc5c0231e23 100644 --- a/sys/compat/linuxkpi/common/include/linux/kref.h +++ b/sys/compat/linuxkpi/common/include/linux/kref.h @@ -38,6 +38,7 @@ #include #include #include +#include #include @@ -77,6 +78,20 @@ kref_put(struct kref *kref, void (*rel)(struct kref *kref)) return 0; } +static inline int +kref_put_lock(struct kref *kref, void (*rel)(struct kref *kref), + spinlock_t *lock) +{ + + if (refcount_release(&kref->refcount.counter)) { + spin_lock(lock); + rel(kref); + return (1); + } + return (0); +} + + static inline int kref_sub(struct kref *kref, unsigned int count, void (*rel)(struct kref *kref)) From 2d946b2e129844aaaa0ac3e10f01509234791da1 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 4 Aug 2020 14:45:22 +0000 Subject: [PATCH 050/141] linuxkpi: Add nested variant of mutex_lock_interruptible We don't do anything with the _nesteds variant so just call mutex_lock_interruptible Sponsoredby: The FreeBSD Foundation Reviewed by: hselasky MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D25944 --- sys/compat/linuxkpi/common/include/linux/mutex.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sys/compat/linuxkpi/common/include/linux/mutex.h b/sys/compat/linuxkpi/common/include/linux/mutex.h index 7558a410f5ef..bdf0b4dbdb2d 100644 --- a/sys/compat/linuxkpi/common/include/linux/mutex.h +++ b/sys/compat/linuxkpi/common/include/linux/mutex.h @@ -67,6 +67,8 @@ typedef struct mutex { linux_mutex_lock_interruptible(_m); \ }) +#define mutex_lock_interruptible_nested(m, c) mutex_lock_interruptible(m) + /* * Reuse the interruptable method since the SX * lock handles both signals and interrupts: From dd8c2fa31b68aa7b1fa9831921b90e34e1f18d69 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 4 Aug 2020 14:48:45 +0000 Subject: [PATCH 051/141] pkgbase: Remove the last users of the FreeBSD-example package Reviewed by: emaste Differential Revision: https://reviews.freebsd.org/D24176 --- share/examples/ipfilter/Makefile | 2 +- share/examples/smbfs/Makefile | 2 +- share/examples/smbfs/print/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/share/examples/ipfilter/Makefile b/share/examples/ipfilter/Makefile index e2d2e02897a5..18c8ac734406 100644 --- a/share/examples/ipfilter/Makefile +++ b/share/examples/ipfilter/Makefile @@ -1,6 +1,6 @@ # $FreeBSD$ -PACKAGE=examples +PACKAGE=ipf FILES= README # dist sample files diff --git a/share/examples/smbfs/Makefile b/share/examples/smbfs/Makefile index e8e5f1cc0d32..a653507f54b0 100644 --- a/share/examples/smbfs/Makefile +++ b/share/examples/smbfs/Makefile @@ -1,6 +1,6 @@ # $FreeBSD$ -PACKAGE=examples +PACKAGE=utilities FILESDIR= ${SHAREDIR}/examples/smbfs FILES= dot.nsmbrc diff --git a/share/examples/smbfs/print/Makefile b/share/examples/smbfs/print/Makefile index 410e9526593f..0c080c0861b3 100644 --- a/share/examples/smbfs/print/Makefile +++ b/share/examples/smbfs/print/Makefile @@ -1,6 +1,6 @@ # $FreeBSD$ -PACKAGE=examples +PACKAGE=utilities FILESDIR= ${SHAREDIR}/examples/smbfs/print FILES= lj6l ljspool printcap.sample tolj From 38ba9c8bac106517a4a6db9e99bb83fbfa27dd3b Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 4 Aug 2020 14:53:41 +0000 Subject: [PATCH 052/141] Re-apply r363564. We now have linux/sizes.h in the tree. --- sys/compat/linuxkpi/common/include/linux/dma-mapping.h | 1 + 1 file changed, 1 insertion(+) diff --git a/sys/compat/linuxkpi/common/include/linux/dma-mapping.h b/sys/compat/linuxkpi/common/include/linux/dma-mapping.h index 2662923eb905..291bd4a8e7ce 100644 --- a/sys/compat/linuxkpi/common/include/linux/dma-mapping.h +++ b/sys/compat/linuxkpi/common/include/linux/dma-mapping.h @@ -38,6 +38,7 @@ #include #include #include +#include #include #include From efec381dd1d9e0e449bcc4cb1f189434f9c7d55c Mon Sep 17 00:00:00 2001 From: Mark Johnston Date: Tue, 4 Aug 2020 14:59:43 +0000 Subject: [PATCH 053/141] Remove most lingering references to the page lock in comments. Finish updating comments to reflect new locking protocols introduced over the past year. In particular, vm_page_lock is now effectively unused. Reviewed by: kib Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D25868 --- sys/vm/vm_page.c | 19 +++++-------------- sys/vm/vm_page.h | 35 ++++++++++++++++------------------- sys/vm/vm_pageout.c | 7 +++---- sys/vm/vnode_pager.c | 2 +- 4 files changed, 25 insertions(+), 38 deletions(-) diff --git a/sys/vm/vm_page.c b/sys/vm/vm_page.c index ce107645d6a6..593af4b5a2e4 100644 --- a/sys/vm/vm_page.c +++ b/sys/vm/vm_page.c @@ -2675,7 +2675,7 @@ vm_page_scan_contig(u_long npages, vm_page_t m_start, vm_page_t m_end, * ascending order.) (2) It is not reserved, and it is * transitioning from free to allocated. (Conversely, * the transition from allocated to free for managed - * pages is blocked by the page lock.) (3) It is + * pages is blocked by the page busy lock.) (3) It is * allocated but not contained by an object and not * wired, e.g., allocated by Xen's balloon driver. */ @@ -3622,8 +3622,6 @@ vm_page_pqbatch_drain(void) * Request removal of the given page from its current page * queue. Physical removal from the queue may be deferred * indefinitely. - * - * The page must be locked. */ void vm_page_dequeue_deferred(vm_page_t m) @@ -3804,8 +3802,8 @@ vm_page_free_prep(vm_page_t m) * Returns the given page to the free list, disassociating it * from any VM object. * - * The object must be locked. The page must be locked if it is - * managed. + * The object must be locked. The page must be exclusively busied if it + * belongs to an object. */ static void vm_page_free_toq(vm_page_t m) @@ -3834,9 +3832,6 @@ vm_page_free_toq(vm_page_t m) * Returns a list of pages to the free list, disassociating it * from any VM object. In other words, this is equivalent to * calling vm_page_free_toq() for each page of a list of VM objects. - * - * The objects must be locked. The pages must be locked if it is - * managed. */ void vm_page_free_pages_toq(struct spglist *free, bool update_wire_count) @@ -3974,8 +3969,6 @@ vm_page_unwire_managed(vm_page_t m, uint8_t nqueue, bool noreuse) * of wirings transitions to zero and the page is eligible for page out, then * the page is added to the specified paging queue. If the released wiring * represented the last reference to the page, the page is freed. - * - * A managed page must be locked. */ void vm_page_unwire(vm_page_t m, uint8_t nqueue) @@ -4022,8 +4015,6 @@ vm_page_unwire_noq(vm_page_t m) * Ensure that the page ends up in the specified page queue. If the page is * active or being moved to the active queue, ensure that its act_count is * at least ACT_INIT but do not otherwise mess with it. - * - * A managed page must be locked. */ static __always_inline void vm_page_mvqueue(vm_page_t m, const uint8_t nqueue, const uint16_t nflag) @@ -4269,14 +4260,14 @@ vm_page_try_remove_write(vm_page_t m) * vm_page_advise * * Apply the specified advice to the given page. - * - * The object and page must be locked. */ void vm_page_advise(vm_page_t m, int advice) { VM_OBJECT_ASSERT_WLOCKED(m->object); + vm_page_assert_xbusied(m); + if (advice == MADV_FREE) /* * Mark the page clean. This will allow the page to be freed diff --git a/sys/vm/vm_page.h b/sys/vm/vm_page.h index 93b3dc411925..039e467491d0 100644 --- a/sys/vm/vm_page.h +++ b/sys/vm/vm_page.h @@ -95,19 +95,17 @@ * synchronized using either one of or a combination of locks. If a * field is annotated with two of these locks then holding either is * sufficient for read access but both are required for write access. - * The physical address of a page is used to select its page lock from - * a pool. The queue lock for a page depends on the value of its queue - * field and is described in detail below. + * The queue lock for a page depends on the value of its queue field and is + * described in detail below. * * The following annotations are possible: * (A) the field must be accessed using atomic(9) and may require * additional synchronization. * (B) the page busy lock. * (C) the field is immutable. - * (F) the per-domain lock for the free queues + * (F) the per-domain lock for the free queues. * (M) Machine dependent, defined by pmap layer. * (O) the object that the page belongs to. - * (P) the page lock. * (Q) the page's queue lock. * * The busy lock is an embedded reader-writer lock that protects the @@ -270,7 +268,7 @@ struct vm_page { * cleared only when the corresponding object's write lock is held. * * VPRC_BLOCKED is used to atomically block wirings via pmap lookups while - * attempting to tear down all mappings of a given page. The page lock and + * attempting to tear down all mappings of a given page. The page busy lock and * object write lock must both be held in order to set or clear this bit. */ #define VPRC_BLOCKED 0x40000000u /* mappings are being removed */ @@ -411,26 +409,25 @@ extern struct mtx_padalign pa_lock[]; * * PGA_ENQUEUED is set and cleared when a page is inserted into or removed * from a page queue, respectively. It determines whether the plinks.q field - * of the page is valid. To set or clear this flag, the queue lock for the - * page must be held: the page queue lock corresponding to the page's "queue" - * field if its value is not PQ_NONE, and the page lock otherwise. + * of the page is valid. To set or clear this flag, page's "queue" field must + * be a valid queue index, and the corresponding page queue lock must be held. * * PGA_DEQUEUE is set when the page is scheduled to be dequeued from a page * queue, and cleared when the dequeue request is processed. A page may * have PGA_DEQUEUE set and PGA_ENQUEUED cleared, for instance if a dequeue * is requested after the page is scheduled to be enqueued but before it is - * actually inserted into the page queue. For allocated pages, the page lock - * must be held to set this flag, but it may be set by vm_page_free_prep() - * without the page lock held. The page queue lock must be held to clear the - * PGA_DEQUEUE flag. + * actually inserted into the page queue. * * PGA_REQUEUE is set when the page is scheduled to be enqueued or requeued - * in its page queue. The page lock must be held to set this flag, and the - * queue lock for the page must be held to clear it. + * in its page queue. * * PGA_REQUEUE_HEAD is a special flag for enqueuing pages near the head of - * the inactive queue, thus bypassing LRU. The page lock must be held to - * set this flag, and the queue lock for the page must be held to clear it. + * the inactive queue, thus bypassing LRU. + * + * The PGA_DEQUEUE, PGA_REQUEUE and PGA_REQUEUE_HEAD flags must be set using an + * atomic RMW operation to ensure that the "queue" field is a valid queue index, + * and the corresponding page queue lock must be held when clearing any of the + * flags. * * PGA_SWAP_FREE is used to defer freeing swap space to the pageout daemon * when the context that dirties the page does not have the object write lock @@ -451,8 +448,8 @@ extern struct mtx_padalign pa_lock[]; #define PGA_QUEUE_STATE_MASK (PGA_ENQUEUED | PGA_QUEUE_OP_MASK) /* - * Page flags. If changed at any other time than page allocation or - * freeing, the modification must be protected by the vm_page lock. + * Page flags. Updates to these flags are not synchronized, and thus they must + * be set during page allocation or free to avoid races. * * The PG_PCPU_CACHE flag is set at allocation time if the page was * allocated from a per-CPU cache. It is cleared the next time that the diff --git a/sys/vm/vm_pageout.c b/sys/vm/vm_pageout.c index 429e8f4edc91..db2aa5f1c1cf 100644 --- a/sys/vm/vm_pageout.c +++ b/sys/vm/vm_pageout.c @@ -257,10 +257,9 @@ vm_pageout_end_scan(struct scan_state *ss) * physically dequeued if the caller so requests. Otherwise, the returned * batch may contain marker pages, and it is up to the caller to handle them. * - * When processing the batch queue, vm_page_queue() must be used to - * determine whether the page has been logically dequeued by another thread. - * Once this check is performed, the page lock guarantees that the page will - * not be disassociated from the queue. + * When processing the batch queue, vm_pageout_defer() must be used to + * determine whether the page has been logically dequeued since the batch was + * collected. */ static __always_inline void vm_pageout_collect_batch(struct scan_state *ss, const bool dequeue) diff --git a/sys/vm/vnode_pager.c b/sys/vm/vnode_pager.c index fa9f4cab16f9..0a1518e94a24 100644 --- a/sys/vm/vnode_pager.c +++ b/sys/vm/vnode_pager.c @@ -1307,7 +1307,7 @@ vnode_pager_generic_putpages(struct vnode *vp, vm_page_t *ma, int bytecount, * the last page is partially invalid. In this case the filesystem * may not properly clear the dirty bits for the entire page (which * could be VM_PAGE_BITS_ALL due to the page having been mmap()d). - * With the page locked we are free to fix-up the dirty bits here. + * With the page busied we are free to fix up the dirty bits here. * * We do not under any circumstances truncate the valid bits, as * this will screw up bogus page replacement. From cfae6a92ac013c3fd069ba802840b823f87e9457 Mon Sep 17 00:00:00 2001 From: Mark Johnston Date: Tue, 4 Aug 2020 15:00:02 +0000 Subject: [PATCH 054/141] Remove an incorrect assertion from in6p_lookup_mcast_ifp(). The socket may be bound to an IPv4-mapped IPv6 address. However, the inp address is not relevant to the JOIN_GROUP or LEAVE_GROUP operations. While here remove an unnecessary check for inp == NULL. Reported by: syzbot+d01ab3d5e6c1516a393c@syzkaller.appspotmail.com Reviewed by: hselasky MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D25888 --- sys/netinet6/in6_mcast.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/sys/netinet6/in6_mcast.c b/sys/netinet6/in6_mcast.c index 9da4fcb775e8..5332aeac99ec 100644 --- a/sys/netinet6/in6_mcast.c +++ b/sys/netinet6/in6_mcast.c @@ -1817,31 +1817,27 @@ ip6_getmoptions(struct inpcb *inp, struct sockopt *sopt) * * This routine exists to support legacy IPv6 multicast applications. * - * If inp is non-NULL, use this socket's current FIB number for any - * required FIB lookup. Look up the group address in the unicast FIB, - * and use its ifp; usually, this points to the default next-hop. - * If the FIB lookup fails, return NULL. + * Use the socket's current FIB number for any required FIB lookup. Look up the + * group address in the unicast FIB, and use its ifp; usually, this points to + * the default next-hop. If the FIB lookup fails, return NULL. * * FUTURE: Support multiple forwarding tables for IPv6. * * Returns NULL if no ifp could be found. */ static struct ifnet * -in6p_lookup_mcast_ifp(const struct inpcb *inp, - const struct sockaddr_in6 *gsin6) +in6p_lookup_mcast_ifp(const struct inpcb *inp, const struct sockaddr_in6 *gsin6) { struct nhop_object *nh; struct in6_addr dst; uint32_t scopeid; uint32_t fibnum; - KASSERT(inp->inp_vflag & INP_IPV6, - ("%s: not INP_IPV6 inpcb", __func__)); KASSERT(gsin6->sin6_family == AF_INET6, ("%s: not AF_INET6 group", __func__)); in6_splitscope(&gsin6->sin6_addr, &dst, &scopeid); - fibnum = inp ? inp->inp_inc.inc_fibnum : RT_DEFAULT_FIB; + fibnum = inp->inp_inc.inc_fibnum; nh = fib6_lookup(fibnum, &dst, scopeid, 0, 0); return (nh ? nh->nh_ifp : NULL); From 334680ab074cae5c7fa78ebcb04a9765bbf4fcea Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 4 Aug 2020 15:25:22 +0000 Subject: [PATCH 055/141] linuxkpi: Add clear_bit_unlock This calls clear_bit and adds a memory barrier. Sponsored by: The FreeBSD Foundation Reviewed by: hselasky MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D25943 --- sys/compat/linuxkpi/common/include/linux/bitops.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/sys/compat/linuxkpi/common/include/linux/bitops.h b/sys/compat/linuxkpi/common/include/linux/bitops.h index f3c62596bcf5..7e259760f7c3 100644 --- a/sys/compat/linuxkpi/common/include/linux/bitops.h +++ b/sys/compat/linuxkpi/common/include/linux/bitops.h @@ -275,6 +275,13 @@ find_next_zero_bit(const unsigned long *addr, unsigned long size, #define test_bit(i, a) \ !!(READ_ONCE(((volatile const unsigned long *)(a))[BIT_WORD(i)]) & BIT_MASK(i)) +static inline void +clear_bit_unlock(long bit, volatile unsigned long *var) +{ + clear_bit(bit, var); + wmb(); +} + static inline int test_and_clear_bit(long bit, volatile unsigned long *var) { From dfb4ecb38b8d9e24667f3c0c7fbb8e5b97186613 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 4 Aug 2020 15:27:32 +0000 Subject: [PATCH 056/141] linuxkpi: Add time_after32 and time_before32 This compare two 32 bits times Sponsored by: The FreeBSD Foundation Reviewed by: kib, hselasky MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D25700 --- sys/compat/linuxkpi/common/include/linux/jiffies.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sys/compat/linuxkpi/common/include/linux/jiffies.h b/sys/compat/linuxkpi/common/include/linux/jiffies.h index c8fc57725e54..ed2c5f774d23 100644 --- a/sys/compat/linuxkpi/common/include/linux/jiffies.h +++ b/sys/compat/linuxkpi/common/include/linux/jiffies.h @@ -45,7 +45,9 @@ #define MAX_JIFFY_OFFSET ((INT_MAX >> 1) - 1) #define time_after(a, b) ((int)((b) - (a)) < 0) +#define time_after32(a, b) ((int32_t)((uint32_t)(b) - (uint32_t)(a)) < 0) #define time_before(a, b) time_after(b,a) +#define time_before32(a, b) time_after32(b, a) #define time_after_eq(a, b) ((int)((a) - (b)) >= 0) #define time_before_eq(a, b) time_after_eq(b, a) #define time_in_range(a,b,c) \ From a02fb76280fd663aa46843423002d605a7bd0796 Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Tue, 4 Aug 2020 18:19:29 +0000 Subject: [PATCH 057/141] Turn off errors for -Wmaybe-uninitialized in GCC 6+. Recent changes to trigger this warning and seem like a false positive. Differential Revision: https://reviews.freebsd.org/D25726 --- share/mk/bsd.sys.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/share/mk/bsd.sys.mk b/share/mk/bsd.sys.mk index 9f96b74dff76..2f2bbe578f30 100644 --- a/share/mk/bsd.sys.mk +++ b/share/mk/bsd.sys.mk @@ -150,7 +150,8 @@ CWARNFLAGS+= -Wno-error=address \ # GCC 6.1.0 .if ${COMPILER_VERSION} >= 60100 -CWARNFLAGS+= -Wno-error=nonnull-compare \ +CWARNFLAGS+= -Wno-error=maybe-uninitialized \ + -Wno-error=nonnull-compare \ -Wno-error=shift-negative-value \ -Wno-error=tautological-compare \ -Wno-error=unused-const-variable From 0ea6e5109d681b55886f61822ec23a4404d3eac5 Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Tue, 4 Aug 2020 18:20:39 +0000 Subject: [PATCH 058/141] Disable errors for -Wredundant-decls for GCC 6+. GCC triggers warnings for this that clang does not for duplicate declarations of yylex(). Differential Revision: https://reviews.freebsd.org/D25727 --- share/mk/bsd.sys.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/share/mk/bsd.sys.mk b/share/mk/bsd.sys.mk index 2f2bbe578f30..afa374f68bca 100644 --- a/share/mk/bsd.sys.mk +++ b/share/mk/bsd.sys.mk @@ -152,6 +152,7 @@ CWARNFLAGS+= -Wno-error=address \ .if ${COMPILER_VERSION} >= 60100 CWARNFLAGS+= -Wno-error=maybe-uninitialized \ -Wno-error=nonnull-compare \ + -Wno-error=redundant-decls \ -Wno-error=shift-negative-value \ -Wno-error=tautological-compare \ -Wno-error=unused-const-variable From ec71044958e62e7fc4ea85932beeb12b56b3b98a Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Tue, 4 Aug 2020 18:23:32 +0000 Subject: [PATCH 059/141] ld.bfd requires an explicit emulation for MIPS for ld -r. Unlike lld, ld.bfd doesn't infer the emulation from the first object file, but assumes its compiled in default for ld -r. Differential Revision: https://reviews.freebsd.org/D25728 --- lib/csu/mips/Makefile | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/lib/csu/mips/Makefile b/lib/csu/mips/Makefile index a0c6cdf0be53..372f98d5b18e 100644 --- a/lib/csu/mips/Makefile +++ b/lib/csu/mips/Makefile @@ -2,6 +2,27 @@ .PATH: ${.CURDIR:H}/common +.include + CFLAGS+= -DCRT_IRELOC_SUPPRESS +.if ${MACHINE_ARCH:Mmips64} +ELFCLASS= 64 +.else +ELFCLASS= 32 +.endif +.if ${MACHINE_ARCH:Mmips*el} +ENDIAN= l +.else +ENDIAN= b +.endif +.if ${MACHINE_ARCH:Mmipsn32*} +SUFFIX= n32 +.else +SUFFIX= +.endif + +# binutils requires an explicit emulation for ld -r +LDFLAGS.bfd+= -Wl,-m -Wl,elf${ELFCLASS}${ENDIAN}tsmip${SUFFIX}_fbsd + .include From 776b260ae2ec0e4b9ad241541dd5f6d4dba1a0bd Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Tue, 4 Aug 2020 18:24:46 +0000 Subject: [PATCH 060/141] Disable errors for -Wsystem-headers for GCC on aarch64. GCC's own arm_neon.h triggers multiple warnings on both GCC 6 and GCC 9. Differential Revision: https://reviews.freebsd.org/D25729 --- share/mk/bsd.sys.mk | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/share/mk/bsd.sys.mk b/share/mk/bsd.sys.mk index afa374f68bca..3aa6c7e938e4 100644 --- a/share/mk/bsd.sys.mk +++ b/share/mk/bsd.sys.mk @@ -184,6 +184,11 @@ CWARNFLAGS+= -Wno-error=aggressive-loop-optimizations \ -Wno-error=sizeof-pointer-memaccess \ -Wno-error=stringop-truncation .endif + +# GCC's own arm_neon.h triggers various warnings +.if ${MACHINE_ARCH} == "aarch64" +CWARNFLAGS+= -Wno-system-headers +.endif .endif # gcc # How to handle FreeBSD custom printf format specifiers. From 2554fe8f89383d8dedd834b46a9f616a277f8af4 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 4 Aug 2020 19:05:45 +0000 Subject: [PATCH 061/141] Import DTS from Linux 5.8 --- Bindings/{ABI.txt => ABI.rst} | 5 +- Bindings/Makefile | 56 +- Bindings/arm/altera.yaml | 6 +- Bindings/arm/amlogic.yaml | 6 +- .../amlogic/amlogic,meson-gx-ao-secure.yaml | 2 +- Bindings/arm/arm,scmi.txt | 3 +- Bindings/arm/arm,vexpress-juno.yaml | 34 +- Bindings/arm/atmel-at91.yaml | 7 + Bindings/arm/bitmain.yaml | 2 +- Bindings/arm/calxeda/hb-sregs.yaml | 49 + Bindings/arm/calxeda/l2ecc.txt | 15 - Bindings/arm/calxeda/l2ecc.yaml | 42 + Bindings/arm/coresight-cti.yaml | 20 +- Bindings/arm/cpus.yaml | 86 +- Bindings/arm/freescale/fsl,scu.txt | 8 +- Bindings/arm/fsl.yaml | 4 + Bindings/arm/l2c2x0.yaml | 87 +- Bindings/arm/mediatek.yaml | 22 + Bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 + Bindings/arm/mediatek/mediatek,audsys.txt | 1 + Bindings/arm/mediatek/mediatek,camsys.txt | 1 + Bindings/arm/mediatek/mediatek,imgsys.txt | 1 + Bindings/arm/mediatek/mediatek,infracfg.txt | 1 + Bindings/arm/mediatek/mediatek,mipi0a.txt | 28 + Bindings/arm/mediatek/mediatek,mmsys.txt | 8 +- Bindings/arm/mediatek/mediatek,pericfg.txt | 36 - Bindings/arm/mediatek/mediatek,pericfg.yaml | 65 + Bindings/arm/mediatek/mediatek,topckgen.txt | 1 + Bindings/arm/mediatek/mediatek,vcodecsys.txt | 27 + Bindings/arm/nxp/lpc32xx.yaml | 9 +- Bindings/arm/psci.yaml | 16 +- Bindings/arm/qcom.yaml | 7 + Bindings/arm/realtek.yaml | 21 + Bindings/arm/renesas,prr.yaml | 2 +- Bindings/arm/renesas.yaml | 10 + Bindings/arm/rockchip.yaml | 5 + Bindings/arm/samsung/exynos-chipid.yaml | 5 +- Bindings/arm/samsung/samsung-boards.yaml | 1 + Bindings/arm/socionext/uniphier.yaml | 27 +- Bindings/arm/stm32/st,mlahb.yaml | 2 +- Bindings/arm/stm32/st,stm32-syscon.yaml | 6 +- Bindings/arm/stm32/stm32.yaml | 3 + Bindings/arm/sunxi.yaml | 5 + Bindings/arm/syna.txt | 2 +- Bindings/arm/tegra/nvidia,tegra20-pmc.yaml | 7 +- Bindings/ata/faraday,ftide010.yaml | 4 +- Bindings/ata/renesas,rcar-sata.yaml | 1 + Bindings/ata/sata_highbank.txt | 44 - Bindings/ata/sata_highbank.yaml | 92 ++ Bindings/auxdisplay/hit,hd44780.txt | 45 - Bindings/auxdisplay/hit,hd44780.yaml | 96 ++ Bindings/bus/allwinner,sun50i-a64-de2.yaml | 5 +- Bindings/bus/allwinner,sun8i-a23-rsb.yaml | 4 +- Bindings/bus/arm,integrator-ap-lm.yaml | 83 ++ Bindings/bus/baikal,bt1-apb.yaml | 90 ++ Bindings/bus/baikal,bt1-axi.yaml | 107 ++ .../bus/socionext,uniphier-system-bus.yaml | 4 +- .../clock/allwinner,sun4i-a10-gates-clk.yaml | 8 +- Bindings/clock/baikal,bt1-ccu-div.yaml | 188 +++ Bindings/clock/baikal,bt1-ccu-pll.yaml | 131 ++ Bindings/clock/bitmain,bm1880-clk.yaml | 2 +- Bindings/clock/calxeda.txt | 17 - Bindings/clock/calxeda.yaml | 82 ++ Bindings/clock/cirrus,lochnagar.txt | 94 -- Bindings/clock/cirrus,lochnagar.yaml | 78 ++ Bindings/clock/fixed-factor-clock.yaml | 5 +- Bindings/clock/fsl,plldig.yaml | 19 +- Bindings/clock/idt,versaclock5.txt | 1 + Bindings/clock/imx1-clock.txt | 26 - Bindings/clock/imx1-clock.yaml | 51 + Bindings/clock/imx21-clock.txt | 27 - Bindings/clock/imx21-clock.yaml | 51 + Bindings/clock/imx23-clock.txt | 70 - Bindings/clock/imx23-clock.yaml | 92 ++ Bindings/clock/imx25-clock.txt | 160 --- Bindings/clock/imx25-clock.yaml | 186 +++ Bindings/clock/imx27-clock.txt | 27 - Bindings/clock/imx27-clock.yaml | 55 + Bindings/clock/imx28-clock.txt | 93 -- Bindings/clock/imx28-clock.yaml | 115 ++ Bindings/clock/imx31-clock.txt | 90 -- Bindings/clock/imx31-clock.yaml | 120 ++ Bindings/clock/imx35-clock.txt | 114 -- Bindings/clock/imx35-clock.yaml | 139 ++ Bindings/clock/imx5-clock.txt | 28 - Bindings/clock/imx5-clock.yaml | 65 + Bindings/clock/imx6q-clock.txt | 41 - Bindings/clock/imx6q-clock.yaml | 71 + Bindings/clock/imx6sl-clock.txt | 10 - Bindings/clock/imx6sl-clock.yaml | 47 + Bindings/clock/imx6sll-clock.txt | 36 - Bindings/clock/imx6sll-clock.yaml | 65 + Bindings/clock/imx6sx-clock.txt | 13 - Bindings/clock/imx6sx-clock.yaml | 69 + Bindings/clock/imx6ul-clock.txt | 13 - Bindings/clock/imx6ul-clock.yaml | 65 + Bindings/clock/imx7d-clock.txt | 13 - Bindings/clock/imx7d-clock.yaml | 65 + Bindings/clock/imx8qxp-lpcg.txt | 51 - Bindings/clock/imx8qxp-lpcg.yaml | 73 + Bindings/clock/ingenic,cgu.txt | 57 - Bindings/clock/ingenic,cgu.yaml | 124 ++ Bindings/clock/intel,agilex.yaml | 46 + Bindings/clock/intel,cgu-lgm.yaml | 44 + Bindings/clock/marvell,mmp2-audio-clock.yaml | 75 ++ Bindings/clock/marvell,mmp2-clock.yaml | 5 + Bindings/clock/qcom,a53pll.txt | 22 - Bindings/clock/qcom,a53pll.yaml | 40 + Bindings/clock/qcom,gcc-sc7180.yaml | 2 +- Bindings/clock/qcom,gcc-sm8150.yaml | 2 +- Bindings/clock/qcom,gcc-sm8250.yaml | 2 +- Bindings/clock/qcom,gcc.yaml | 3 + Bindings/clock/qcom,mmcc.yaml | 20 +- Bindings/clock/qcom,sc7180-dispcc.yaml | 2 +- Bindings/clock/qcom,sc7180-gpucc.yaml | 2 +- Bindings/clock/qcom,sc7180-mss.yaml | 2 +- Bindings/clock/qcom,sc7180-videocc.yaml | 2 +- Bindings/clock/qcom,sdm845-dispcc.yaml | 2 +- Bindings/clock/qcom,sdm845-gpucc.yaml | 2 +- Bindings/clock/qcom,sdm845-videocc.yaml | 2 +- Bindings/clock/renesas,cpg-div6-clock.yaml | 60 + Bindings/clock/renesas,cpg-div6-clocks.txt | 40 - Bindings/clock/renesas,cpg-mssr.yaml | 1 + Bindings/clock/renesas,cpg-mstp-clocks.txt | 60 - Bindings/clock/renesas,cpg-mstp-clocks.yaml | 82 ++ .../clock/renesas,rcar-usb2-clock-sel.txt | 4 +- Bindings/clock/silabs,si5341.txt | 11 +- Bindings/clock/sprd,sc9863a-clk.yaml | 28 +- Bindings/connector/usb-connector.yaml | 73 +- Bindings/cpufreq/nvidia,tegra20-cpufreq.txt | 56 + .../crypto/allwinner,sun4i-a10-crypto.yaml | 14 +- Bindings/crypto/allwinner,sun8i-ce.yaml | 16 +- Bindings/crypto/amlogic,gxl-crypto.yaml | 4 +- Bindings/crypto/st,stm32-hash.yaml | 9 +- .../allwinner,sun4i-a10-display-engine.yaml | 7 +- .../display/allwinner,sun4i-a10-hdmi.yaml | 40 +- .../display/allwinner,sun4i-a10-tcon.yaml | 63 +- .../display/allwinner,sun6i-a31-mipi-dsi.yaml | 30 +- .../display/allwinner,sun8i-a83t-dw-hdmi.yaml | 10 +- Bindings/display/bridge/adi,adv7123.txt | 50 - Bindings/display/bridge/analogix,anx7814.yaml | 119 ++ Bindings/display/bridge/anx6345.yaml | 8 + Bindings/display/bridge/anx7814.txt | 42 - Bindings/display/bridge/chrontel,ch7033.yaml | 77 ++ Bindings/display/bridge/dumb-vga-dac.txt | 50 - Bindings/display/bridge/dw_mipi_dsi.txt | 32 - Bindings/display/bridge/ite,it6505.yaml | 91 ++ Bindings/display/bridge/lvds-codec.yaml | 26 +- Bindings/display/bridge/nwl-dsi.yaml | 226 ++++ Bindings/display/bridge/ps8640.yaml | 8 + Bindings/display/bridge/sii902x.txt | 2 +- Bindings/display/bridge/simple-bridge.yaml | 99 ++ Bindings/display/bridge/snps,dw-mipi-dsi.yaml | 68 + .../display/bridge/thine,thc63lvd1024.txt | 66 - .../display/bridge/thine,thc63lvd1024.yaml | 121 ++ Bindings/display/bridge/ti,ths813x.txt | 51 - Bindings/display/dsi-controller.yaml | 4 +- Bindings/display/imx/fsl-imx-drm.txt | 4 +- Bindings/display/imx/ldb.txt | 4 +- Bindings/display/mediatek/mediatek,dpi.txt | 6 + Bindings/display/mediatek/mediatek,dsi.txt | 10 + .../display/panel/arm,versatile-tft-panel.txt | 31 - .../panel/arm,versatile-tft-panel.yaml | 54 + .../panel/asus,z00t-tm5p5-nt35596.yaml | 56 + Bindings/display/panel/boe,himax8279d.txt | 24 - Bindings/display/panel/boe,himax8279d.yaml | 59 + Bindings/display/panel/boe,tv101wum-nl6.yaml | 2 + Bindings/display/panel/display-timings.yaml | 8 +- .../display/panel/feiyang,fy07024di26a30d.txt | 20 - .../panel/feiyang,fy07024di26a30d.yaml | 58 + Bindings/display/panel/ilitek,ili9322.txt | 49 - Bindings/display/panel/ilitek,ili9322.yaml | 71 + Bindings/display/panel/ilitek,ili9881c.txt | 20 - Bindings/display/panel/ilitek,ili9881c.yaml | 50 + Bindings/display/panel/innolux,p097pfg.txt | 24 - Bindings/display/panel/innolux,p097pfg.yaml | 56 + .../display/panel/innolux,p120zdg-bf1.txt | 22 - .../display/panel/innolux,p120zdg-bf1.yaml | 43 + Bindings/display/panel/jdi,lt070me05000.txt | 31 - Bindings/display/panel/jdi,lt070me05000.yaml | 69 + .../panel/kingdisplay,kd035g6-54nt.txt | 42 - .../panel/kingdisplay,kd035g6-54nt.yaml | 65 + .../display/panel/kingdisplay,kd097d04.txt | 22 - .../display/panel/leadtek,ltk050h3146w.yaml | 51 + Bindings/display/panel/lg,acx467akm-7.txt | 7 - Bindings/display/panel/lg,ld070wx3-sl01.txt | 7 - Bindings/display/panel/lg,lg4573.txt | 19 - Bindings/display/panel/lg,lg4573.yaml | 45 + Bindings/display/panel/lg,lh500wx1-sd03.txt | 7 - Bindings/display/panel/lgphilips,lb035q02.txt | 33 - .../display/panel/lgphilips,lb035q02.yaml | 59 + .../display/panel/olimex,lcd-olinuxino.txt | 42 - .../display/panel/olimex,lcd-olinuxino.yaml | 70 + .../panel/osddisplays,osd101t2587-53ts.txt | 14 - Bindings/display/panel/panel-common.yaml | 28 +- Bindings/display/panel/panel-simple-dsi.yaml | 14 + Bindings/display/panel/panel-simple.yaml | 22 +- Bindings/display/panel/panel-timing.yaml | 120 +- Bindings/display/panel/raydium,rm67191.txt | 41 - Bindings/display/panel/raydium,rm67191.yaml | 75 ++ .../panel/samsung,amoled-mipi-dsi.yaml | 65 + Bindings/display/panel/samsung,ld9040.txt | 66 - Bindings/display/panel/samsung,ld9040.yaml | 107 ++ Bindings/display/panel/samsung,s6d16d0.txt | 30 - Bindings/display/panel/samsung,s6d16d0.yaml | 56 + Bindings/display/panel/samsung,s6e3ha2.txt | 31 - Bindings/display/panel/samsung,s6e63j0x03.txt | 24 - Bindings/display/panel/samsung,s6e63m0.txt | 33 - Bindings/display/panel/samsung,s6e63m0.yaml | 60 + Bindings/display/panel/seiko,43wvf1g.txt | 23 - Bindings/display/panel/seiko,43wvf1g.yaml | 50 + Bindings/display/panel/sharp,lq150x1lg11.txt | 36 - Bindings/display/panel/sharp,lq150x1lg11.yaml | 58 + Bindings/display/panel/sharp,ls037v7dw01.txt | 43 - Bindings/display/panel/sharp,ls037v7dw01.yaml | 68 + Bindings/display/panel/sharp,ls043t1le01.txt | 22 - Bindings/display/panel/sharp,ls043t1le01.yaml | 51 + Bindings/display/panel/simple-panel.txt | 1 - Bindings/display/panel/sitronix,st7701.txt | 30 - Bindings/display/panel/sitronix,st7701.yaml | 69 + Bindings/display/panel/sitronix,st7789v.txt | 37 - Bindings/display/panel/sitronix,st7789v.yaml | 63 + Bindings/display/panel/sony,acx424akp.yaml | 2 +- Bindings/display/panel/sony,acx565akm.txt | 30 - Bindings/display/panel/sony,acx565akm.yaml | 57 + .../display/panel/startek,startek-kd050c.txt | 4 - .../display/panel/startek,startek-kd050c.yaml | 33 + Bindings/display/panel/tpo,td.yaml | 65 + Bindings/display/panel/tpo,td028ttec1.txt | 32 - Bindings/display/panel/tpo,td043mtea1.txt | 33 - Bindings/display/panel/visionox,rm69299.yaml | 57 + .../display/panel/xinpeng,xpp055c272.yaml | 4 +- Bindings/display/renesas,cmm.yaml | 18 +- Bindings/display/renesas,du.txt | 10 + .../display/rockchip/rockchip,rk3066-hdmi.txt | 72 - .../rockchip/rockchip,rk3066-hdmi.yaml | 140 ++ Bindings/display/rockchip/rockchip-drm.yaml | 2 +- Bindings/display/rockchip/rockchip-vop.txt | 74 -- Bindings/display/rockchip/rockchip-vop.yaml | 134 ++ .../display/tegra/nvidia,tegra20-host1x.txt | 73 +- Bindings/display/ti/ti,am65x-dss.yaml | 19 +- Bindings/display/ti/ti,j721e-dss.yaml | 34 +- Bindings/dma/dma-common.yaml | 3 +- Bindings/dma/ingenic,dma.yaml | 80 ++ Bindings/dma/jz4780-dma.txt | 64 - Bindings/dma/mtk-uart-apdma.txt | 3 +- Bindings/dma/renesas,rcar-dmac.txt | 117 -- Bindings/dma/renesas,rcar-dmac.yaml | 150 +++ Bindings/dma/renesas,usb-dmac.txt | 55 - Bindings/dma/renesas,usb-dmac.yaml | 102 ++ Bindings/dma/sifive,fu540-c000-pdma.yaml | 2 +- Bindings/dma/st,stm32-dma.yaml | 5 + Bindings/dma/ti/k3-udma.yaml | 29 +- Bindings/dsp/fsl,dsp.yaml | 2 + Bindings/eeprom/at24.yaml | 13 +- Bindings/example-schema.yaml | 17 +- Bindings/extcon/extcon-arizona.txt | 76 -- Bindings/extcon/extcon-usbc-cros-ec.yaml | 3 +- Bindings/extcon/wlf,arizona.yaml | 125 ++ Bindings/firmware/intel,stratix10-svc.txt | 2 +- .../fpga/intel-stratix10-soc-fpga-mgr.txt | 3 +- Bindings/gpio/brcm,xgs-iproc-gpio.yaml | 2 +- Bindings/gpio/fsl-imx-gpio.txt | 35 - Bindings/gpio/fsl-imx-gpio.yaml | 68 + Bindings/gpio/gpio-mxs.txt | 88 -- Bindings/gpio/gpio-mxs.yaml | 136 ++ Bindings/gpio/mediatek,mt7621-gpio.txt | 2 +- Bindings/gpio/renesas,em-gio.yaml | 70 + Bindings/gpio/renesas,gpio-rcar.txt | 94 -- Bindings/gpio/renesas,rcar-gpio.yaml | 144 ++ Bindings/gpio/sifive,gpio.yaml | 2 +- Bindings/gpio/snps,dw-apb-gpio.yaml | 133 ++ Bindings/gpio/snps-dwapb-gpio.txt | 65 - Bindings/gpu/arm,mali-bifrost.yaml | 6 + Bindings/gpu/arm,mali-midgard.yaml | 20 +- Bindings/gpu/arm,mali-utgard.yaml | 6 + Bindings/gpu/vivante,gc.yaml | 2 +- Bindings/hwmon/adi,axi-fan-control.yaml | 3 +- Bindings/hwmon/adi,ltc2947.yaml | 32 +- Bindings/hwmon/adt7475.yaml | 18 +- Bindings/hwmon/baikal,bt1-pvt.yaml | 107 ++ Bindings/hwmon/cirrus,lochnagar.txt | 26 - Bindings/hwmon/cirrus,lochnagar.yaml | 35 + Bindings/hwmon/ti,tmp513.yaml | 21 +- Bindings/i2c/brcm,bcm2835-i2c.txt | 2 +- Bindings/i2c/cdns,i2c-r1p10.yaml | 58 + Bindings/i2c/i2c-cadence.txt | 28 - Bindings/i2c/i2c-designware.txt | 73 - Bindings/i2c/i2c-jz4780.txt | 33 - Bindings/i2c/i2c-mt65xx.txt | 1 + Bindings/i2c/i2c-qcom-cci.txt | 92 ++ Bindings/i2c/i2c-rk3x.yaml | 10 +- Bindings/i2c/i2c-xiic.txt | 25 - Bindings/i2c/i2c.txt | 73 +- Bindings/i2c/ingenic,i2c.yaml | 88 ++ Bindings/i2c/nuvoton,npcm7xx-i2c.yaml | 62 + Bindings/i2c/nvidia,tegra20-i2c.txt | 6 + Bindings/i2c/renesas,i2c.txt | 1 + Bindings/i2c/renesas,iic.txt | 1 + Bindings/i2c/snps,designware-i2c.yaml | 156 +++ Bindings/i2c/st,stm32-i2c.yaml | 23 +- Bindings/i2c/xlnx,xps-iic-2.00.a.yaml | 49 + Bindings/iio/accel/bma180.txt | 8 +- Bindings/iio/adc/adi,ad7124.yaml | 9 +- Bindings/iio/adc/adi,ad9467.yaml | 65 + Bindings/iio/adc/adi,axi-adc.yaml | 62 + Bindings/iio/adc/lltc,ltc2496.yaml | 9 +- Bindings/iio/adc/maxim,max1241.yaml | 63 + Bindings/iio/adc/microchip,mcp3911.yaml | 7 +- Bindings/iio/adc/rockchip-saradc.txt | 37 - Bindings/iio/adc/rockchip-saradc.yaml | 80 ++ Bindings/iio/adc/st,stm32-adc.yaml | 35 +- Bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 27 +- Bindings/iio/chemical/ams,ccs811.yaml | 53 + Bindings/iio/chemical/atlas,sensor.yaml | 8 +- Bindings/iio/common.yaml | 35 + Bindings/iio/dac/ltc2632.txt | 8 +- Bindings/iio/dac/st,stm32-dac.txt | 63 - Bindings/iio/dac/st,stm32-dac.yaml | 110 ++ Bindings/iio/gyroscope/bmg160.txt | 2 +- Bindings/iio/imu/adi,adis16475.yaml | 136 ++ Bindings/iio/imu/bmi160.txt | 37 - Bindings/iio/imu/bosch,bmi160.yaml | 75 ++ Bindings/iio/light/amstaos,tsl2563.yaml | 48 + Bindings/iio/light/tsl2563.txt | 19 - Bindings/iio/light/tsl2772.yaml | 13 +- Bindings/iio/light/vcnl4000.txt | 24 - Bindings/iio/light/vishay,vcnl4000.yaml | 50 + Bindings/iio/magnetometer/ak8974.txt | 4 +- Bindings/iio/proximity/vishay,vcnl3020.yaml | 62 + Bindings/iio/st-sensors.txt | 1 + Bindings/iio/temperature/adi,ltc2983.yaml | 60 +- Bindings/index.rst | 12 + .../input/allwinner,sun4i-a10-lradc-keys.yaml | 9 +- Bindings/input/elants_i2c.txt | 34 - Bindings/input/gpio-keys-polled.txt | 45 - Bindings/input/gpio-keys.txt | 58 - Bindings/input/gpio-keys.yaml | 149 +++ Bindings/input/input.yaml | 9 +- Bindings/input/iqs269a.yaml | 555 ++++++++ Bindings/input/iqs62x-keys.yaml | 7 +- Bindings/input/msm-vibrator.txt | 36 - .../input/touchscreen/cypress,cy8ctma140.yaml | 72 + Bindings/input/touchscreen/edt-ft5x06.yaml | 30 +- .../input/touchscreen/elan,elants_i2c.yaml | 69 + Bindings/input/touchscreen/goodix.yaml | 2 +- Bindings/input/touchscreen/mms114.txt | 3 +- Bindings/interconnect/fsl,imx8m-noc.yaml | 101 ++ Bindings/interconnect/qcom,msm8916.yaml | 4 +- Bindings/interconnect/qcom,msm8974.yaml | 4 +- Bindings/interconnect/qcom,qcs404.yaml | 4 +- Bindings/interconnect/qcom,sc7180.yaml | 6 +- Bindings/interconnect/qcom,sdm845.yaml | 4 +- .../allwinner,sun7i-a20-sc-nmi.yaml | 12 +- Bindings/interrupt-controller/arm,gic-v3.yaml | 39 +- Bindings/interrupt-controller/arm,gic.yaml | 9 + Bindings/interrupt-controller/csky,mpintc.txt | 2 +- .../interrupt-controller/fsl,irqsteer.txt | 35 - .../interrupt-controller/fsl,irqsteer.yaml | 89 ++ .../interrupt-controller/ingenic,intc.txt | 28 - .../interrupt-controller/ingenic,intc.yaml | 63 + .../intel,ixp4xx-interrupt.yaml | 8 +- .../interrupt-controller/loongson,htvec.yaml | 57 + .../loongson,liointc.yaml | 8 +- .../loongson,pch-msi.yaml | 60 + .../loongson,pch-pic.yaml | 55 + .../renesas,intc-irqpin.txt | 62 - .../renesas,intc-irqpin.yaml | 107 ++ .../interrupt-controller/renesas,irqc.yaml | 3 +- .../interrupt-controller/st,stm32-exti.yaml | 12 +- Bindings/iommu/allwinner,sun50i-h6-iommu.yaml | 61 + Bindings/iommu/arm,smmu.yaml | 8 +- Bindings/iommu/renesas,ipmmu-vmsa.txt | 73 - Bindings/iommu/renesas,ipmmu-vmsa.yaml | 98 ++ Bindings/iommu/samsung,sysmmu.yaml | 10 +- Bindings/ipmi/ipmi-smic.txt | 25 - Bindings/ipmi/ipmi-smic.yaml | 61 + Bindings/leds/backlight/qcom-wled.txt | 154 --- Bindings/leds/backlight/qcom-wled.yaml | 252 ++++ Bindings/leds/common.yaml | 13 +- Bindings/leds/leds-aw2013.yaml | 90 ++ Bindings/leds/leds-gpio.yaml | 3 +- Bindings/leds/leds-sgm3140.yaml | 61 + Bindings/leds/rohm,bd71828-leds.yaml | 9 +- Bindings/mailbox/fsl,mu.txt | 58 - Bindings/mailbox/fsl,mu.yaml | 91 ++ Bindings/mailbox/qcom,apcs-kpss-global.txt | 88 -- Bindings/mailbox/qcom,apcs-kpss-global.yaml | 86 ++ Bindings/mailbox/qcom-ipcc.yaml | 80 ++ Bindings/mailbox/sprd-mailbox.yaml | 60 + Bindings/mailbox/st,stm32-ipcc.yaml | 7 +- Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 2 +- Bindings/media/allwinner,sun4i-a10-csi.yaml | 28 +- .../allwinner,sun4i-a10-video-engine.yaml | 3 + Bindings/media/amlogic,gx-vdec.yaml | 20 +- Bindings/media/amlogic,meson-gx-ao-cec.yaml | 5 +- Bindings/media/i2c/imx219.yaml | 3 +- Bindings/media/i2c/ov8856.yaml | 141 ++ Bindings/media/marvell,mmp2-ccic.txt | 50 - Bindings/media/marvell,mmp2-ccic.yaml | 99 ++ Bindings/media/qcom,sc7180-venus.yaml | 2 +- Bindings/media/qcom,sdm845-venus-v2.yaml | 2 +- Bindings/media/qcom,sdm845-venus.yaml | 2 +- Bindings/media/rc.yaml | 265 ++-- Bindings/media/renesas,ceu.yaml | 37 +- Bindings/media/renesas,csi2.yaml | 2 +- Bindings/media/renesas,vin.yaml | 21 +- Bindings/media/rockchip,vdec.yaml | 73 + Bindings/media/rockchip-rga.txt | 34 - Bindings/media/rockchip-rga.yaml | 83 ++ Bindings/media/rockchip-vpu.txt | 43 - Bindings/media/rockchip-vpu.yaml | 77 ++ Bindings/media/ti,vpe.yaml | 2 +- Bindings/media/video-interfaces.txt | 370 +++++- .../memory-controllers/baikal,bt1-l2-ctl.yaml | 63 + .../memory-controllers/calxeda-ddr-ctrlr.txt | 16 - .../memory-controllers/calxeda-ddr-ctrlr.yaml | 42 + Bindings/memory-controllers/exynos-srom.yaml | 13 +- .../memory-controllers/fsl/imx8m-ddrc.yaml | 6 +- .../ingenic,jz4780-nemc.txt | 76 -- Bindings/memory-controllers/ingenic,nemc.yaml | 125 ++ .../nvidia,tegra124-emc.yaml | 13 +- .../nvidia,tegra124-mc.yaml | 5 +- .../nvidia,tegra210-emc.yaml | 82 ++ .../nvidia,tegra30-emc.yaml | 9 +- .../memory-controllers/nvidia,tegra30-mc.yaml | 3 +- Bindings/memory-controllers/renesas,dbsc.txt | 44 - Bindings/memory-controllers/renesas,dbsc.yaml | 56 + Bindings/mfd/allwinner,sun4i-a10-ts.yaml | 20 +- Bindings/mfd/arizona.txt | 101 -- Bindings/mfd/cirrus,lochnagar.txt | 85 -- Bindings/mfd/cirrus,lochnagar.yaml | 352 +++++ Bindings/mfd/cirrus,madera.yaml | 299 +++++ Bindings/mfd/gateworks-gsc.yaml | 196 +++ Bindings/mfd/madera.txt | 114 -- Bindings/mfd/max8998.txt | 8 + Bindings/mfd/mps,mp2629.yaml | 62 + Bindings/mfd/mt6397.txt | 19 +- Bindings/mfd/st,stm32-lptimer.yaml | 4 +- Bindings/mfd/st,stm32-timers.yaml | 37 +- Bindings/mfd/st,stpmic1.yaml | 9 +- Bindings/mfd/syscon.yaml | 17 +- Bindings/mfd/wlf,arizona.yaml | 280 ++++ Bindings/mips/ingenic/devices.yaml | 4 + Bindings/mips/loongson/rs780e-acpi.yaml | 40 + Bindings/misc/olpc,xo1.75-ec.txt | 2 +- Bindings/mmc/amlogic,meson-mx-sdhc.yaml | 68 + Bindings/mmc/arasan,sdhci.txt | 57 + Bindings/mmc/aspeed,sdhci.yaml | 4 +- Bindings/mmc/cdns,sdhci.yaml | 79 +- Bindings/mmc/ingenic,mmc.yaml | 79 ++ Bindings/mmc/jz4740.txt | 41 - Bindings/mmc/mmc-controller.yaml | 37 +- Bindings/mmc/owl-mmc.yaml | 2 +- Bindings/mmc/renesas,mmcif.txt | 5 +- Bindings/mmc/renesas,sdhi.txt | 1 + Bindings/mmc/rockchip-dw-mshc.yaml | 24 +- Bindings/mmc/sdhci-msm.txt | 14 + Bindings/mmc/sdhci-pxa.txt | 50 - Bindings/mmc/sdhci-pxa.yaml | 102 ++ Bindings/mmc/socionext,uniphier-sd.yaml | 14 +- Bindings/mmc/synopsys-dw-mshc-common.yaml | 14 +- Bindings/mtd/allwinner,sun4i-a10-nand.yaml | 13 +- Bindings/mtd/arasan,nand-controller.yaml | 63 + Bindings/mtd/brcm,brcmnand.txt | 2 + Bindings/mtd/denali,nand.yaml | 4 +- Bindings/mtd/ingenic,jz4780-nand.txt | 92 -- Bindings/mtd/ingenic,nand.yaml | 132 ++ Bindings/mtd/nand-controller.yaml | 27 +- Bindings/mtd/partition.txt | 3 + Bindings/net/allwinner,sun8i-a83t-emac.yaml | 4 +- Bindings/net/amlogic,meson-dwmac.yaml | 23 +- Bindings/net/calxeda-xgmac.txt | 18 - Bindings/net/calxeda-xgmac.yaml | 49 + Bindings/net/can/bosch,m_can.yaml | 105 +- Bindings/net/ethernet-controller.yaml | 34 +- Bindings/net/ethernet-phy.yaml | 3 +- Bindings/net/fsl-fec.txt | 8 +- Bindings/net/imx-dwmac.txt | 56 + Bindings/net/mdio.yaml | 50 +- Bindings/net/mediatek,star-emac.yaml | 89 ++ Bindings/net/mediatek-bluetooth.txt | 2 +- Bindings/net/nxp,tja11xx.yaml | 61 + Bindings/net/qca,ar71xx.txt | 45 - Bindings/net/qca,ar71xx.yaml | 216 +++ Bindings/net/qca,ar803x.yaml | 17 +- Bindings/net/qcom,ipa.yaml | 22 +- Bindings/net/qcom,ipq4019-mdio.yaml | 61 + Bindings/net/qualcomm-bluetooth.txt | 6 + Bindings/net/realtek-bluetooth.yaml | 54 + Bindings/net/renesas,ether.yaml | 9 +- Bindings/net/renesas,ravb.txt | 1 + Bindings/net/snps,dwmac.yaml | 30 +- Bindings/net/socionext,uniphier-ave4.txt | 64 - Bindings/net/socionext,uniphier-ave4.yaml | 111 ++ Bindings/net/stm32-dwmac.txt | 44 - Bindings/net/stm32-dwmac.yaml | 148 +++ Bindings/net/ti,cpsw-switch.yaml | 18 +- Bindings/net/ti,davinci-mdio.yaml | 34 +- Bindings/net/ti,dp83867.txt | 68 - Bindings/net/ti,dp83867.yaml | 127 ++ Bindings/net/ti,dp83869.yaml | 2 +- Bindings/net/ti,k3-am654-cpsw-nuss.yaml | 107 +- Bindings/net/ti,k3-am654-cpts.yaml | 143 ++ Bindings/net/wireless/mediatek,mt76.txt | 3 + Bindings/net/wireless/qcom,ath10k.txt | 14 + Bindings/nvmem/imx-iim.txt | 22 - Bindings/nvmem/imx-iim.yaml | 57 + Bindings/nvmem/imx-ocotp.txt | 50 - Bindings/nvmem/imx-ocotp.yaml | 95 ++ Bindings/nvmem/mxs-ocotp.txt | 24 - Bindings/nvmem/mxs-ocotp.yaml | 50 + Bindings/nvmem/nvmem.yaml | 2 - Bindings/nvmem/rockchip-efuse.txt | 54 - Bindings/nvmem/rockchip-efuse.yaml | 70 + Bindings/nvmem/st,stm32-romem.yaml | 17 + Bindings/opp/opp.txt | 17 +- Bindings/pci/aardvark-pci.txt | 4 + Bindings/pci/brcm,stb-pcie.yaml | 2 + Bindings/pci/cdns,cdns-pcie-ep.yaml | 2 +- Bindings/pci/cdns,cdns-pcie-host.yaml | 3 +- Bindings/pci/cdns-pcie-ep.yaml | 24 + Bindings/pci/cdns-pcie-host.yaml | 12 +- Bindings/pci/cdns-pcie.yaml | 8 - Bindings/pci/intel-gw-pcie.yaml | 7 +- Bindings/pci/loongson.yaml | 62 + Bindings/pci/pci-ep.yaml | 9 +- Bindings/pci/pci-rcar-gen2.txt | 3 +- Bindings/pci/rcar-pci-ep.yaml | 77 ++ Bindings/pci/rcar-pci.txt | 3 +- Bindings/pci/socionext,uniphier-pcie-ep.yaml | 92 ++ .../amlogic,meson-axg-mipi-pcie-analog.yaml | 2 +- Bindings/phy/amlogic,meson-axg-pcie.yaml | 2 +- Bindings/phy/amlogic,meson8b-usb2-phy.yaml | 64 + Bindings/phy/calxeda-combophy.txt | 17 - Bindings/phy/calxeda-combophy.yaml | 50 + Bindings/phy/cdns,salvo-phy.yaml | 52 + Bindings/phy/intel,combo-phy.yaml | 101 ++ Bindings/phy/intel,lgm-emmc-phy.yaml | 2 +- Bindings/phy/meson-gxl-usb3-phy.txt | 31 - Bindings/phy/meson8b-usb2-phy.txt | 28 - Bindings/phy/phy-cadence-torrent.yaml | 59 +- Bindings/phy/qcom,qmp-phy.yaml | 317 +++++ Bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 140 ++ Bindings/phy/qcom,qusb2-phy.yaml | 65 +- Bindings/phy/qcom,usb-snps-femto-v2.yaml | 80 ++ Bindings/phy/qcom-qmp-phy.txt | 242 ---- Bindings/phy/qcom-usb-ipq4019-phy.yaml | 50 + Bindings/phy/rcar-gen2-phy.txt | 3 +- Bindings/phy/rcar-gen3-phy-usb2.txt | 70 - Bindings/phy/rcar-gen3-phy-usb3.txt | 52 - Bindings/phy/renesas,usb2-phy.yaml | 117 ++ Bindings/phy/renesas,usb3-phy.yaml | 78 ++ Bindings/phy/rockchip,px30-dsi-dphy.yaml | 2 +- Bindings/phy/rockchip-mipi-dphy-rx0.yaml | 73 + Bindings/phy/socionext,uniphier-pcie-phy.yaml | 77 ++ Bindings/phy/socionext,uniphier-usb2-phy.yaml | 85 ++ .../phy/socionext,uniphier-usb3hs-phy.yaml | 103 ++ .../phy/socionext,uniphier-usb3ss-phy.yaml | 96 ++ Bindings/phy/uniphier-pcie-phy.txt | 36 - Bindings/phy/uniphier-usb2-phy.txt | 45 - Bindings/phy/uniphier-usb3-hsphy.txt | 69 - Bindings/phy/uniphier-usb3-ssphy.txt | 58 - .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 12 +- Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml | 37 +- Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml | 46 +- Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml | 108 +- Bindings/pinctrl/brcm,bcm2835-gpio.txt | 5 +- Bindings/pinctrl/cirrus,lochnagar.txt | 141 -- Bindings/pinctrl/cirrus,lochnagar.yaml | 190 +++ Bindings/pinctrl/cirrus,madera-pinctrl.txt | 99 -- Bindings/pinctrl/cirrus,madera.yaml | 122 ++ Bindings/pinctrl/fsl,imx8mm-pinctrl.yaml | 31 +- Bindings/pinctrl/fsl,imx8mn-pinctrl.yaml | 31 +- Bindings/pinctrl/fsl,imx8mp-pinctrl.yaml | 31 +- Bindings/pinctrl/fsl,imx8mq-pinctrl.yaml | 31 +- Bindings/pinctrl/intel,lgm-io.yaml | 4 +- Bindings/pinctrl/mscc,ocelot-pinctrl.txt | 4 +- Bindings/pinctrl/pinmux-node.yaml | 3 +- Bindings/pinctrl/qcom,ipq6018-pinctrl.yaml | 3 +- Bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 147 +++ Bindings/pinctrl/renesas,pfc-pinctrl.txt | 3 +- Bindings/pinctrl/rockchip,pinctrl.txt | 4 +- Bindings/pinctrl/st,stm32-pinctrl.yaml | 57 +- Bindings/power/amlogic,meson-ee-pwrc.yaml | 105 +- Bindings/power/fsl,imx-gpc.txt | 91 -- Bindings/power/fsl,imx-gpc.yaml | 124 ++ Bindings/power/fsl,imx-gpcv2.txt | 77 -- Bindings/power/fsl,imx-gpcv2.yaml | 108 ++ Bindings/power/qcom,rpmpd.yaml | 1 + Bindings/power/renesas,apmu.yaml | 1 + Bindings/power/renesas,rcar-sysc.yaml | 1 + Bindings/power/reset/syscon-reboot-mode.txt | 35 - Bindings/power/reset/syscon-reboot-mode.yaml | 55 + Bindings/power/reset/syscon-reboot.yaml | 15 +- Bindings/power/supply/battery.txt | 6 + Bindings/power/supply/bq27xxx.txt | 56 - Bindings/power/supply/bq27xxx.yaml | 91 ++ Bindings/power/supply/cw2015_battery.yaml | 79 ++ Bindings/power/supply/power-supply.yaml | 40 + Bindings/power/supply/power_supply.txt | 25 +- Bindings/power/supply/rohm,bd99954.yaml | 155 +++ Bindings/power/supply/sbs,sbs-battery.yaml | 81 ++ Bindings/power/supply/sbs_sbs-battery.txt | 27 - Bindings/property-units.txt | 4 + Bindings/pwm/imx-pwm.txt | 27 - Bindings/pwm/imx-pwm.yaml | 64 + Bindings/pwm/imx-tpm-pwm.txt | 22 - Bindings/pwm/imx-tpm-pwm.yaml | 55 + Bindings/pwm/mxs-pwm.txt | 17 - Bindings/pwm/mxs-pwm.yaml | 43 + Bindings/pwm/pwm-samsung.yaml | 27 +- Bindings/pwm/renesas,pwm-rcar.yaml | 3 +- Bindings/regulator/anatop-regulator.txt | 40 - Bindings/regulator/anatop-regulator.yaml | 94 ++ Bindings/regulator/arizona-regulator.txt | 18 - Bindings/regulator/cirrus,lochnagar.txt | 82 -- Bindings/regulator/gpio-regulator.yaml | 35 +- Bindings/regulator/maxim,max77826.yaml | 65 + Bindings/regulator/mps,mp5416.yaml | 6 +- Bindings/regulator/mps,mpq7920.yaml | 28 +- Bindings/regulator/regulator.yaml | 5 +- .../regulator/rohm,bd71828-regulator.yaml | 34 +- .../regulator/rohm,bd71837-regulator.yaml | 27 +- .../regulator/rohm,bd71847-regulator.yaml | 27 +- Bindings/regulator/st,stm32-booster.yaml | 3 +- Bindings/regulator/st,stm32mp1-pwr-reg.yaml | 3 +- Bindings/regulator/wlf,arizona.yaml | 37 + Bindings/remoteproc/ingenic,vpu.yaml | 77 ++ Bindings/remoteproc/qcom,adsp.txt | 12 + Bindings/remoteproc/qcom,q6v5.txt | 25 +- Bindings/remoteproc/st,stm32-rproc.yaml | 11 +- Bindings/reserved-memory/ramoops.txt | 13 +- Bindings/reserved-memory/reserved-memory.txt | 2 + .../reset/brcm,bcm7216-pcie-sata-rescal.yaml | 4 +- Bindings/reset/fsl,imx7-src.txt | 6 +- Bindings/reset/intel,rcu-gw.yaml | 3 +- Bindings/reset/renesas,rst.yaml | 1 + Bindings/riscv/cpus.yaml | 20 +- Bindings/rng/arm-cctrng.yaml | 52 + Bindings/rtc/dw-apb.txt | 32 - Bindings/rtc/renesas,sh-rtc.yaml | 5 + Bindings/rtc/rtc-mxc.txt | 26 - Bindings/rtc/rtc-mxc.yaml | 57 + Bindings/rtc/rtc-mxc_v2.txt | 17 - Bindings/rtc/rtc-mxc_v2.yaml | 46 + Bindings/rtc/st,stm32-rtc.yaml | 47 +- Bindings/serial/8250.txt | 100 -- Bindings/serial/8250.yaml | 233 ++++ Bindings/serial/amlogic,meson-uart.yaml | 16 +- Bindings/serial/ingenic,uart.txt | 28 - Bindings/serial/ingenic,uart.yaml | 94 ++ Bindings/serial/mrvl-serial.txt | 4 - Bindings/serial/nxp,sc16is7xx.txt | 4 + Bindings/serial/pl011.yaml | 10 +- Bindings/serial/qca,ar9330-uart.txt | 31 - Bindings/serial/qca,ar9330-uart.yaml | 50 + Bindings/serial/renesas,em-uart.yaml | 49 + Bindings/serial/renesas,hscif.yaml | 1 + Bindings/serial/renesas,scif.yaml | 1 + Bindings/serial/renesas,scifa.yaml | 15 +- Bindings/serial/renesas,scifb.yaml | 1 + Bindings/serial/rs485.yaml | 47 +- Bindings/serial/samsung_uart.yaml | 12 +- Bindings/serial/serial.yaml | 8 + Bindings/serial/sifive-serial.yaml | 2 +- Bindings/serial/st,stm32-uart.yaml | 14 + Bindings/soc/amlogic/amlogic,canvas.yaml | 10 +- Bindings/soc/qcom/qcom,aoss-qmp.txt | 1 + Bindings/soc/qcom/qcom,apr.txt | 20 +- Bindings/soc/qcom/qcom,geni-se.txt | 94 -- Bindings/soc/qcom/qcom,geni-se.yaml | 222 ++++ Bindings/soc/ti/k3-socinfo.yaml | 40 + Bindings/sound/adi,adau7118.yaml | 20 +- Bindings/sound/allwinner,sun4i-a10-codec.yaml | 47 +- Bindings/sound/amlogic,aiu.yaml | 3 +- Bindings/sound/amlogic,g12a-toacodec.yaml | 2 +- Bindings/sound/amlogic,t9015.yaml | 3 +- Bindings/sound/audio-graph-card.txt | 2 +- Bindings/sound/cirrus,lochnagar.txt | 39 - Bindings/sound/cirrus,lochnagar.yaml | 52 + Bindings/sound/cirrus,madera.yaml | 113 ++ Bindings/sound/da7213.txt | 8 +- Bindings/sound/fsl,asrc.txt | 4 + Bindings/sound/fsl,easrc.yaml | 98 ++ Bindings/sound/fsl,esai.txt | 1 + Bindings/sound/madera.txt | 67 - Bindings/sound/marvell,mmp-sspa.yaml | 122 ++ Bindings/sound/nau8810.txt | 5 +- Bindings/sound/nau8825.txt | 2 +- Bindings/sound/nvidia,tegra-audio-wm8903.txt | 1 + Bindings/sound/qcom,lpass-cpu.txt | 25 + Bindings/sound/qcom,q6adm.txt | 2 +- Bindings/sound/qcom,q6afe.txt | 46 +- Bindings/sound/qcom,q6asm.txt | 7 +- Bindings/sound/qcom,q6core.txt | 2 +- Bindings/sound/qcom,wcd934x.yaml | 3 +- Bindings/sound/renesas,fsi.yaml | 41 +- Bindings/sound/renesas,rsnd.txt | 1 + Bindings/sound/rockchip-i2s.yaml | 18 +- Bindings/sound/rt1016.txt | 17 + Bindings/sound/simple-card.txt | 351 ----- Bindings/sound/simple-card.yaml | 491 +++++++ Bindings/sound/st,sti-asoc-card.txt | 2 +- Bindings/sound/tdm-slot.txt | 4 +- Bindings/sound/tlv320adcx140.yaml | 59 +- Bindings/sound/wlf,arizona.txt | 53 - Bindings/sound/wlf,arizona.yaml | 114 ++ Bindings/sound/wm8994.txt | 18 +- Bindings/sound/zl38060.yaml | 69 + Bindings/spi/amlogic,meson-gx-spicc.yaml | 26 +- Bindings/spi/brcm,spi-bcm-qspi.txt | 10 + Bindings/spi/marvell,mmp2-ssp.yaml | 58 + Bindings/spi/mikrotik,rb4xx-spi.yaml | 36 + Bindings/spi/qcom,spi-geni-qcom.txt | 2 +- Bindings/spi/qcom,spi-qcom-qspi.yaml | 10 +- Bindings/spi/renesas,hspi.yaml | 4 +- Bindings/spi/renesas,rspi.yaml | 144 ++ Bindings/spi/renesas,sh-msiof.yaml | 44 +- Bindings/spi/snps,dw-apb-ssi.txt | 41 - Bindings/spi/snps,dw-apb-ssi.yaml | 133 ++ Bindings/spi/socionext,uniphier-spi.yaml | 57 + Bindings/spi/spi-controller.yaml | 14 +- Bindings/spi/spi-dw.txt | 24 - Bindings/spi/spi-pl022.yaml | 57 +- Bindings/spi/spi-pxa2xx.txt | 27 - Bindings/spi/spi-rspi.txt | 73 - Bindings/spi/spi-sifive.yaml | 25 +- Bindings/spi/spi-uniphier.txt | 28 - Bindings/spi/st,stm32-qspi.yaml | 4 +- Bindings/spi/ti_qspi.txt | 2 +- .../allwinner,sun4i-a10-system-control.yaml | 64 +- Bindings/sram/rockchip-pmu-sram.txt | 16 - Bindings/sram/sram.yaml | 28 +- ...ing-patches.txt => submitting-patches.rst} | 12 +- Bindings/thermal/amlogic,thermal.yaml | 10 +- Bindings/thermal/imx-thermal.txt | 61 - Bindings/thermal/imx-thermal.yaml | 102 ++ Bindings/thermal/imx8mm-thermal.txt | 15 - Bindings/thermal/imx8mm-thermal.yaml | 58 + Bindings/thermal/qcom-tsens.yaml | 7 +- Bindings/thermal/rcar-gen3-thermal.txt | 60 - Bindings/thermal/rcar-gen3-thermal.yaml | 99 ++ Bindings/thermal/rcar-thermal.yaml | 7 +- .../thermal/socionext,uniphier-thermal.yaml | 58 + Bindings/thermal/sprd-thermal.yaml | 2 +- Bindings/thermal/thermal-cooling-devices.yaml | 116 ++ Bindings/thermal/thermal-idle.yaml | 145 ++ Bindings/thermal/thermal-sensor.yaml | 72 + Bindings/thermal/thermal-zones.yaml | 341 +++++ Bindings/thermal/ti,am654-thermal.yaml | 56 + Bindings/thermal/uniphier-thermal.txt | 65 - Bindings/timer/arm,arch_timer.yaml | 10 +- Bindings/timer/arm,arch_timer_mmio.yaml | 11 +- Bindings/timer/cadence,ttc-timer.txt | 21 - Bindings/timer/cdns,ttc.yaml | 48 + Bindings/timer/csky,mptimer.txt | 2 +- Bindings/timer/fsl,imxgpt.txt | 45 - Bindings/timer/fsl,imxgpt.yaml | 72 + Bindings/timer/ingenic,tcu.txt | 138 -- Bindings/timer/ingenic,tcu.yaml | 280 ++++ Bindings/timer/nxp,sysctr-timer.txt | 25 - Bindings/timer/nxp,sysctr-timer.yaml | 54 + Bindings/timer/nxp,tpm-timer.txt | 28 - Bindings/timer/nxp,tpm-timer.yaml | 61 + Bindings/timer/renesas,cmt.txt | 110 -- Bindings/timer/renesas,cmt.yaml | 182 +++ Bindings/timer/renesas,em-sti.yaml | 46 + Bindings/timer/renesas,mtu2.txt | 42 - Bindings/timer/renesas,mtu2.yaml | 76 ++ Bindings/timer/renesas,ostm.txt | 31 - Bindings/timer/renesas,ostm.yaml | 59 + Bindings/timer/snps,dw-apb-timer.yaml | 88 ++ Bindings/ufs/ti,j721e-ufs.yaml | 63 +- Bindings/usb/amlogic,dwc3.txt | 42 - Bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml | 76 +- Bindings/usb/aspeed,usb-vhub.yaml | 80 +- Bindings/usb/atmel-usb.txt | 56 +- Bindings/usb/brcm,bcm7445-ehci.yaml | 59 + Bindings/usb/dwc2.yaml | 11 +- Bindings/usb/dwc3.txt | 2 - Bindings/usb/ehci-mv.txt | 23 - Bindings/usb/generic-ehci.yaml | 27 +- Bindings/usb/generic-ohci.yaml | 6 + Bindings/usb/ingenic,musb.yaml | 3 + Bindings/usb/keystone-usb.txt | 56 - Bindings/usb/marvell,pxau2o-ehci.yaml | 62 + Bindings/usb/nvidia,tegra-xudc.yaml | 10 +- Bindings/usb/qcom,dwc3.txt | 104 -- Bindings/usb/qcom,dwc3.yaml | 174 +++ Bindings/usb/renesas,usb3-peri.yaml | 2 +- Bindings/usb/renesas,usbhs.yaml | 3 +- Bindings/usb/ti,j721e-usb.yaml | 54 +- Bindings/usb/ti,keystone-dwc3.yaml | 77 ++ Bindings/usb/ti,tps6598x.yaml | 64 + Bindings/usb/usb-conn-gpio.txt | 30 - Bindings/usb/usb-xhci.txt | 2 + Bindings/vendor-prefixes.yaml | 40 +- Bindings/watchdog/arm-smc-wdt.yaml | 36 + Bindings/watchdog/fsl-imx-wdt.txt | 24 - Bindings/watchdog/fsl-imx-wdt.yaml | 54 + Bindings/watchdog/fsl-imx7ulp-wdt.txt | 22 - Bindings/watchdog/fsl-imx7ulp-wdt.yaml | 60 + Bindings/watchdog/renesas,wdt.txt | 50 - Bindings/watchdog/renesas,wdt.yaml | 101 ++ Bindings/watchdog/socionext,uniphier-wdt.yaml | 36 + Bindings/watchdog/ti,rti-wdt.yaml | 2 +- Bindings/watchdog/uniphier-wdt.txt | 20 - ...ting-bindings.txt => writing-bindings.rst} | 9 +- Bindings/xilinx.txt | 143 -- include/dt-bindings/clock/agilex-clock.h | 70 + include/dt-bindings/clock/at91.h | 4 + include/dt-bindings/clock/bt1-ccu.h | 48 + include/dt-bindings/clock/imx7ulp-clock.h | 5 +- include/dt-bindings/clock/imx8mp-clock.h | 90 +- include/dt-bindings/clock/intel,lgm-clk.h | 165 +++ .../dt-bindings/clock/marvell,mmp2-audio.h | 10 + include/dt-bindings/clock/marvell,mmp2.h | 3 + include/dt-bindings/clock/meson8b-clkc.h | 1 + include/dt-bindings/clock/mt6765-clk.h | 313 +++++ include/dt-bindings/clock/qcom,gcc-msm8939.h | 206 +++ include/dt-bindings/clock/qcom,gcc-msm8998.h | 1 + include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 + include/dt-bindings/clock/r8a7742-cpg-mssr.h | 42 + include/dt-bindings/clock/sprd,sc9863a-clk.h | 5 + include/dt-bindings/clock/tegra114-car.h | 14 +- .../dt-bindings/clock/tegra124-car-common.h | 14 +- include/dt-bindings/clock/tegra20-car.h | 2 +- include/dt-bindings/clock/tegra210-car.h | 20 +- include/dt-bindings/clock/tegra30-car.h | 14 +- include/dt-bindings/clock/x1000-cgu.h | 64 +- include/dt-bindings/clock/x1830-cgu.h | 55 + include/dt-bindings/firmware/imx/rsrc.h | 84 ++ include/dt-bindings/input/linux-event-codes.h | 3 +- include/dt-bindings/interconnect/imx8mm.h | 50 + include/dt-bindings/interconnect/imx8mn.h | 41 + include/dt-bindings/interconnect/imx8mq.h | 48 + include/dt-bindings/mailbox/qcom-ipcc.h | 33 + include/dt-bindings/phy/phy.h | 1 + include/dt-bindings/pinctrl/pads-imx8dxl.h | 639 +++++++++ include/dt-bindings/pinctrl/rockchip.h | 11 - include/dt-bindings/power/marvell,mmp2.h | 11 + include/dt-bindings/power/meson-gxbb-power.h | 13 + include/dt-bindings/power/meson8-power.h | 13 + include/dt-bindings/power/qcom-rpmpd.h | 12 + include/dt-bindings/power/r8a7742-sysc.h | 29 + .../reset/amlogic,meson-gxbb-reset.h | 2 +- include/dt-bindings/reset/bt1-ccu.h | 25 + include/dt-bindings/reset/imx8mp-reset.h | 50 + include/dt-bindings/reset/imx8mq-reset.h | 56 +- include/dt-bindings/reset/qcom,gcc-msm8939.h | 110 ++ include/dt-bindings/reset/realtek,rtd1195.h | 74 ++ include/dt-bindings/reset/realtek,rtd1295.h | 3 + src/arm/am335x-baltos.dtsi | 2 +- src/arm/am335x-boneblack-common.dtsi | 1 + src/arm/am335x-boneblack-wireless.dts | 1 - src/arm/am335x-boneblue.dts | 1 - src/arm/am335x-bonegreen-wireless.dts | 1 - src/arm/am335x-evm.dts | 3 +- src/arm/am335x-evmsk.dts | 2 +- src/arm/am335x-guardian.dts | 1 + src/arm/am335x-lxm.dts | 2 +- src/arm/am335x-moxa-uc-2100-common.dtsi | 2 +- src/arm/am335x-moxa-uc-8100-me-t.dts | 2 +- src/arm/am335x-pepper.dts | 4 +- src/arm/am335x-phycore-som.dtsi | 2 +- src/arm/am335x-pocketbeagle.dts | 1 - src/arm/am33xx-l4.dtsi | 12 +- src/arm/am33xx.dtsi | 27 +- src/arm/am3517-evm.dts | 1 + src/arm/am3517.dtsi | 24 +- src/arm/am4372.dtsi | 23 +- src/arm/am437x-cm-t43.dts | 2 +- src/arm/am437x-gp-evm.dts | 20 +- src/arm/am437x-l4.dtsi | 26 +- src/arm/am437x-sk-evm.dts | 18 +- src/arm/am43x-epos-evm.dts | 16 - src/arm/am571x-idk.dts | 48 +- src/arm/am5729-beagleboneai.dts | 731 ++++++++++ src/arm/am572x-idk-common.dtsi | 63 +- src/arm/am57xx-beagle-x15-common.dtsi | 63 +- src/arm/am57xx-idk-common.dtsi | 58 + src/arm/armada-370-xp.dtsi | 2 - src/arm/armada-375.dtsi | 2 - src/arm/armada-38x.dtsi | 5 +- src/arm/armada-39x.dtsi | 4 - src/arm/aspeed-ast2600-evb.dts | 4 + src/arm/aspeed-bmc-facebook-tiogapass.dts | 78 +- src/arm/aspeed-bmc-facebook-yosemitev2.dts | 231 ++++ src/arm/aspeed-bmc-ibm-rainier.dts | 202 ++- src/arm/aspeed-bmc-opp-mihawk.dts | 310 ++++- src/arm/aspeed-bmc-opp-nicole.dts | 326 +++++ src/arm/aspeed-bmc-opp-romulus.dts | 35 +- src/arm/aspeed-bmc-opp-tacoma.dts | 112 ++ src/arm/aspeed-bmc-opp-witherspoon.dts | 34 + src/arm/aspeed-bmc-opp-zaius.dts | 37 +- src/arm/aspeed-g4.dtsi | 10 + src/arm/aspeed-g5.dtsi | 43 +- src/arm/aspeed-g6.dtsi | 64 +- src/arm/at91-dvk_su60_somc.dtsi | 2 +- src/arm/at91-kizbox3-hs.dts | 4 +- src/arm/at91-kizbox3_common.dtsi | 48 +- src/arm/at91-sam9x60ek.dts | 23 + src/arm/at91-sama5d27_som1.dtsi | 54 + src/arm/at91-sama5d27_som1_ek.dts | 64 +- src/arm/at91-sama5d27_wlsom1.dtsi | 16 +- src/arm/at91-sama5d27_wlsom1_ek.dts | 12 - src/arm/at91-sama5d2_icp.dts | 767 +++++++++++ src/arm/at91-sama5d2_ptc_ek.dts | 25 +- src/arm/at91-sama5d2_xplained.dts | 118 +- src/arm/at91-wb50n.dtsi | 4 - src/arm/at91rm9200.dtsi | 296 +---- src/arm/at91sam9g45.dtsi | 392 +----- src/arm/at91sam9m10g45ek.dts | 4 +- src/arm/at91sam9n12.dtsi | 324 +---- src/arm/at91sam9n12ek.dts | 2 +- src/arm/at91sam9rl.dtsi | 54 - src/arm/at91sam9x5.dtsi | 54 - src/arm/bcm-nsp.dtsi | 10 +- src/arm/bcm2711-rpi-4-b.dts | 13 +- src/arm/bcm2835-common.dtsi | 1 - src/arm/bcm2835-rpi-common.dtsi | 12 + src/arm/bcm2835.dtsi | 1 + src/arm/bcm2836.dtsi | 1 + src/arm/bcm2837.dtsi | 1 + src/arm/bcm47094-luxul-xwc-2000.dts | 1 + src/arm/bcm958522er.dts | 4 + src/arm/bcm958525er.dts | 4 + src/arm/bcm958525xmc.dts | 4 + src/arm/bcm958622hr.dts | 4 + src/arm/bcm958623hr.dts | 4 + src/arm/bcm958625hr.dts | 4 + src/arm/bcm958625k.dts | 4 + src/arm/berlin2.dtsi | 6 +- src/arm/berlin2cd.dtsi | 2 +- src/arm/berlin2q.dtsi | 6 +- src/arm/dm814x.dtsi | 74 +- src/arm/dm816x.dtsi | 78 +- src/arm/dove.dtsi | 3 +- src/arm/dra7-evm-common.dtsi | 21 +- src/arm/dra7-evm.dts | 54 + src/arm/dra7-ipu-dsp-common.dtsi | 39 + src/arm/dra7-l4.dtsi | 63 +- src/arm/dra7.dtsi | 46 + src/arm/dra71-evm.dts | 42 + src/arm/dra72-evm-common.dtsi | 18 +- src/arm/dra72-evm-revc.dts | 42 + src/arm/dra72-evm.dts | 42 + src/arm/dra72x.dtsi | 6 + src/arm/dra74-ipu-dsp-common.dtsi | 18 + src/arm/dra74x.dtsi | 21 + src/arm/dra76-evm.dts | 54 + src/arm/e60k02.dtsi | 2 + src/arm/exynos3250-monk.dts | 3 +- src/arm/exynos3250-rinato.dts | 48 +- src/arm/exynos4210-i9100.dts | 768 +++++++++++ src/arm/exynos4210-origen.dts | 7 +- src/arm/exynos4210-trats.dts | 41 +- src/arm/exynos4210-universal_c210.dts | 33 +- src/arm/exynos4412-galaxy-s3.dtsi | 6 +- src/arm/exynos4412-midas.dtsi | 17 +- src/arm/exynos4412-odroid-common.dtsi | 8 +- src/arm/exynos4412-origen.dts | 14 +- src/arm/exynos5250-arndale.dts | 13 +- src/arm/exynos5420-arndale-octa.dts | 2 +- src/arm/imx50.dtsi | 8 +- src/arm/imx51.dtsi | 3 +- src/arm/imx53-cx9020.dts | 25 +- src/arm/imx53.dtsi | 3 +- src/arm/imx6dl-colibri-v1_1-eval-v3.dts | 31 + src/arm/imx6q-dhcom-pdk2.dts | 115 +- src/arm/imx6qdl-colibri-v1_1-uhs.dtsi | 44 + src/arm/imx6qdl-colibri.dtsi | 11 +- src/arm/imx6qdl-gw551x.dtsi | 2 +- src/arm/imx6qdl-gw552x.dtsi | 14 + src/arm/imx6qdl-gw560x.dtsi | 31 + src/arm/imx6qdl-gw5904.dtsi | 31 + src/arm/imx6qdl-gw5910.dtsi | 35 +- src/arm/imx6qdl-icore.dtsi | 3 +- src/arm/imx6qdl-sabresd.dtsi | 1 + src/arm/imx6qdl-sr-som.dtsi | 11 + src/arm/imx6qdl.dtsi | 15 +- src/arm/imx6sl.dtsi | 13 +- src/arm/imx6sx-sabreauto.dts | 2 +- src/arm/imx6sx-sdb.dtsi | 2 +- src/arm/imx6sx.dtsi | 4 +- src/arm/imx6ul-kontron-n6x1x-s.dtsi | 13 - src/arm/imx6ul-kontron-n6x1x-som-common.dtsi | 13 + src/arm/imx6ul.dtsi | 4 +- src/arm/imx7-tqma7.dtsi | 2 +- src/arm/imx7d-cl-som-imx7.dts | 4 + src/arm/imx7d-colibri.dtsi | 4 + src/arm/imx7d-nitrogen7.dts | 4 + src/arm/imx7d-pinfunc.h | 2 +- src/arm/imx7d-sdb.dts | 4 + src/arm/imx7d-tqma7.dtsi | 4 + src/arm/imx7d-zii-rmu2.dts | 2 +- src/arm/imx7d-zii-rpu2.dts | 2 +- src/arm/imx7d.dtsi | 1 + src/arm/imx7s.dtsi | 3 +- src/arm/integratorap-im-pd1.dts | 270 ++++ src/arm/integratorap.dts | 53 +- src/arm/keystone-k2e.dtsi | 4 +- src/arm/keystone-k2g-evm.dts | 103 +- src/arm/keystone-k2g.dtsi | 26 +- src/arm/keystone-k2hk.dtsi | 4 +- src/arm/keystone-k2l.dtsi | 4 +- src/arm/kirkwood-l-50.dts | 438 ++++++ src/arm/kirkwood-netgear_readynas_nv+_v2.dts | 14 + src/arm/kirkwood.dtsi | 2 +- src/arm/logicpd-torpedo-baseboard.dtsi | 1 + src/arm/ls1021a-twr.dts | 14 + src/arm/meson.dtsi | 5 +- src/arm/meson8b-odroidc1.dts | 3 +- src/arm/meson8b.dtsi | 5 +- src/arm/meson8m2-mxiii-plus.dts | 4 +- src/arm/meson8m2.dtsi | 13 +- src/arm/mmp2.dtsi | 2 +- src/arm/mmp3.dtsi | 26 +- src/arm/motorola-cpcap-mapphone.dtsi | 4 +- src/arm/mt2701-evb.dts | 21 + src/arm/mt2701.dtsi | 33 + src/arm/mt7623.dtsi | 25 + src/arm/mt7623n-rfb-emmc.dts | 1 + src/arm/omap2.dtsi | 31 +- src/arm/omap2420.dtsi | 68 +- src/arm/omap2430.dtsi | 68 +- src/arm/omap3-beagle.dts | 33 + src/arm/omap3-devkit8000.dts | 33 + src/arm/omap3-gta04.dtsi | 1 + src/arm/omap3-n900.dts | 12 +- src/arm/omap3.dtsi | 134 +- src/arm/omap4-duovero-parlor.dts | 2 +- src/arm/omap4-l4.dtsi | 4 +- src/arm/omap4.dtsi | 10 + src/arm/omap5-l4.dtsi | 35 +- src/arm/omap5.dtsi | 96 ++ src/arm/pxa168.dtsi | 8 +- src/arm/pxa3xx.dtsi | 2 +- src/arm/pxa910.dtsi | 4 +- src/arm/qcom-ipq4019.dtsi | 29 + src/arm/qcom-ipq8064.dtsi | 6 + src/arm/qcom-msm8974-samsung-klte.dts | 405 +++++- src/arm/qcom-msm8974.dtsi | 11 + src/arm/r8a7740.dtsi | 2 +- src/arm/r8a7742-iwg21d-q7.dts | 37 + src/arm/r8a7742-iwg21m.dtsi | 53 + src/arm/r8a7742.dtsi | 648 +++++++++ src/arm/r8a7743.dtsi | 12 +- src/arm/r8a7744.dtsi | 12 +- src/arm/r8a7745.dtsi | 12 +- src/arm/r8a7790.dtsi | 12 +- src/arm/r8a7791.dtsi | 95 +- src/arm/r8a7793.dtsi | 14 +- src/arm/r8a7794.dtsi | 12 +- src/arm/rk3036-kylin.dts | 2 +- src/arm/rk3066a-mk808.dts | 2 +- src/arm/rk3188-radxarock.dts | 6 +- src/arm/rk3229-xms6.dts | 19 +- src/arm/rk322x.dtsi | 10 + src/arm/rk3288-firefly-reload.dts | 12 +- src/arm/rk3288-firefly.dtsi | 12 +- src/arm/rk3288-miqi.dts | 2 +- src/arm/rk3288-phycore-som.dtsi | 6 +- src/arm/rk3288-rock2-square.dts | 4 +- src/arm/rk3288-tinker.dtsi | 6 +- src/arm/rk3288.dtsi | 1 - src/arm/rtd1195-horseradish.dts | 32 + src/arm/rtd1195-mele-x1000.dts | 32 + src/arm/rtd1195.dtsi | 217 +++ src/arm/s5pv210-aries.dtsi | 359 ++++- src/arm/s5pv210-fascinate4g.dts | 249 ++++ src/arm/s5pv210-galaxys.dts | 292 ++++ src/arm/s5pv210-pinctrl.dtsi | 9 +- src/arm/s5pv210.dtsi | 23 +- src/arm/sama5d2.dtsi | 415 ++++-- src/arm/sama5d3.dtsi | 537 +------- src/arm/sama5d3_can.dtsi | 20 +- src/arm/sama5d3_emac.dtsi | 8 +- src/arm/sama5d3_gmac.dtsi | 11 +- src/arm/sama5d3_lcd.dtsi | 19 +- src/arm/sama5d3_mci2.dtsi | 11 +- src/arm/sama5d3_tcb1.dtsi | 12 +- src/arm/sama5d3_uart.dtsi | 20 +- src/arm/sama5d3xmb.dtsi | 6 +- src/arm/sama5d3xmb_cmp.dtsi | 6 +- src/arm/sama5d4.dtsi | 126 +- src/arm/sh73a0.dtsi | 2 +- src/arm/socfpga.dtsi | 18 +- src/arm/socfpga_arria10.dtsi | 2 +- src/arm/ste-ux500-samsung-golden.dts | 65 + src/arm/ste-ux500-samsung-skomer.dts | 39 +- src/arm/stih407-family.dtsi | 14 - src/arm/stih418.dtsi | 8 +- src/arm/stm32f429.dtsi | 4 +- src/arm/stm32h743.dtsi | 4 +- src/arm/stm32mp15-pinctrl.dtsi | 666 +++++++++- src/arm/stm32mp151.dtsi | 37 +- src/arm/stm32mp157.dtsi | 8 +- src/arm/stm32mp157a-avenger96.dts | 314 +---- src/arm/stm32mp157a-dhcor-avenger96.dts | 38 + src/arm/stm32mp157a-iot-box.dts | 68 + src/arm/stm32mp157a-stinger96.dts | 12 + src/arm/stm32mp157a-stinger96.dtsi | 342 +++++ src/arm/stm32mp157c-dhcom-pdk2.dts | 265 +--- src/arm/stm32mp157c-dk2.dts | 8 - src/arm/stm32mp157c-ed1.dts | 7 +- src/arm/stm32mp157c-ev1.dts | 14 +- src/arm/stm32mp157c-lxa-mc1.dts | 252 ++++ src/arm/stm32mp15xx-dhcom-pdk2.dtsi | 337 +++++ ...om-som.dtsi => stm32mp15xx-dhcom-som.dtsi} | 9 +- src/arm/stm32mp15xx-dhcor-avenger96.dtsi | 401 ++++++ src/arm/stm32mp15xx-dhcor-io1v8.dtsi | 23 + src/arm/stm32mp15xx-dhcor-som.dtsi | 209 +++ src/arm/stm32mp15xx-dkx.dtsi | 20 +- src/arm/stm32mp15xx-osd32.dtsi | 230 ++++ src/arm/sun4i-a10.dtsi | 2 +- src/arm/sun5i.dtsi | 2 +- src/arm/sun7i-a20-olinuxino-lime-emmc.dts | 32 + src/arm/sun7i-a20.dtsi | 2 +- src/arm/sun8i-a83t.dtsi | 10 + src/arm/sun8i-h2-plus-bananapi-m2-zero.dts | 2 +- src/arm/sun8i-h3.dtsi | 24 +- src/arm/sunxi-h3-h5.dtsi | 10 + src/arm/tegra114-dalmore.dts | 3 +- src/arm/tegra124-venice2.dts | 2 +- src/arm/tegra20-colibri-eval-v3.dts | 2 +- src/arm/tegra20-colibri-iris.dts | 2 +- src/arm/tegra20-harmony.dts | 2 +- src/arm/tegra20-medcom-wide.dts | 2 +- src/arm/tegra20-paz00.dts | 2 +- src/arm/tegra20-seaboard.dts | 2 +- src/arm/tegra20-ventana.dts | 2 +- src/arm/tegra30-apalis-eval.dts | 2 +- src/arm/tegra30-apalis-v1.1-eval.dts | 2 +- src/arm/tegra30-beaver.dts | 40 +- src/arm/tegra30-cardhu.dtsi | 2 +- src/arm/tegra30-colibri-eval-v3.dts | 2 +- src/arm/uniphier-ld4.dtsi | 2 + src/arm/uniphier-ld6b-ref.dts | 1 + src/arm/uniphier-pro4-ace.dts | 1 + src/arm/uniphier-pro4-ref.dts | 1 + src/arm/uniphier-pro4-sanji.dts | 1 + src/arm/uniphier-pro4.dtsi | 10 + src/arm/uniphier-pro5.dtsi | 12 + src/arm/uniphier-pxs2-gentil.dts | 1 + src/arm/uniphier-pxs2-vodka.dts | 1 + src/arm/uniphier-pxs2.dtsi | 12 + src/arm/uniphier-sld8.dtsi | 2 + src/arm/vexpress-v2m-rs1.dtsi | 304 ++--- src/arm64/allwinner/sun50i-a64-olinuxino.dts | 9 + src/arm64/allwinner/sun50i-a64.dtsi | 12 + src/arm64/allwinner/sun50i-h6-beelink-gs1.dts | 9 +- src/arm64/allwinner/sun50i-h6-cpu-opp.dtsi | 117 ++ src/arm64/allwinner/sun50i-h6-orangepi-3.dts | 3 + .../allwinner/sun50i-h6-orangepi-lite2.dts | 65 + src/arm64/allwinner/sun50i-h6-orangepi.dtsi | 17 +- src/arm64/allwinner/sun50i-h6-pine-h64.dts | 43 +- src/arm64/allwinner/sun50i-h6-tanix-tx6.dts | 13 + src/arm64/allwinner/sun50i-h6.dtsi | 61 + src/arm64/altera/socfpga_stratix10.dtsi | 8 +- src/arm64/altera/socfpga_stratix10_socdk.dts | 1 + .../altera/socfpga_stratix10_socdk_nand.dts | 7 +- src/arm64/amlogic/meson-axg.dtsi | 6 +- src/arm64/amlogic/meson-g12-common.dtsi | 11 + src/arm64/amlogic/meson-g12.dtsi | 32 +- src/arm64/amlogic/meson-g12b-gtking-pro.dts | 125 ++ src/arm64/amlogic/meson-g12b-gtking.dts | 145 ++ src/arm64/amlogic/meson-g12b-khadas-vim3.dtsi | 18 +- src/arm64/amlogic/meson-g12b-s922x.dtsi | 15 + src/arm64/amlogic/meson-g12b-ugoos-am6.dts | 377 +----- src/arm64/amlogic/meson-g12b-w400.dtsi | 423 ++++++ src/arm64/amlogic/meson-g12b.dtsi | 22 + src/arm64/amlogic/meson-gx-libretech-pc.dtsi | 78 +- src/arm64/amlogic/meson-gx-p23x-q20x.dtsi | 98 +- src/arm64/amlogic/meson-gx.dtsi | 23 +- src/arm64/amlogic/meson-gxbb-kii-pro.dts | 2 +- src/arm64/amlogic/meson-gxbb-nanopi-k2.dts | 2 +- src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts | 2 +- src/arm64/amlogic/meson-gxbb-odroidc2.dts | 2 +- src/arm64/amlogic/meson-gxbb-vega-s95.dtsi | 2 +- src/arm64/amlogic/meson-gxbb-wetek-play2.dts | 4 +- src/arm64/amlogic/meson-gxbb-wetek.dtsi | 6 +- src/arm64/amlogic/meson-gxbb.dtsi | 23 + .../amlogic/meson-gxl-s805x-libretech-ac.dts | 75 +- src/arm64/amlogic/meson-gxl-s805x-p241.dts | 5 +- src/arm64/amlogic/meson-gxl-s805x.dtsi | 24 + .../amlogic/meson-gxl-s905d-phicomm-n1.dts | 4 + .../amlogic/meson-gxl-s905d-sml5442tw.dts | 80 ++ src/arm64/amlogic/meson-gxl-s905w-p281.dts | 4 + .../amlogic/meson-gxl-s905w-tx3-mini.dts | 4 + .../amlogic/meson-gxl-s905x-khadas-vim.dts | 4 + .../amlogic/meson-gxl-s905x-libretech-cc.dts | 77 +- .../amlogic/meson-gxl-s905x-nexbox-a95x.dts | 3 +- src/arm64/amlogic/meson-gxl-s905x-p212.dtsi | 3 +- src/arm64/amlogic/meson-gxl.dtsi | 84 +- src/arm64/amlogic/meson-gxm-khadas-vim2.dts | 3 +- src/arm64/amlogic/meson-gxm-nexbox-a1.dts | 3 +- src/arm64/amlogic/meson-gxm-rbox-pro.dts | 4 +- src/arm64/amlogic/meson-gxm-vega-s96.dts | 4 + src/arm64/amlogic/meson-gxm.dtsi | 7 +- src/arm64/amlogic/meson-khadas-vim3.dtsi | 4 +- src/arm64/amlogic/meson-sm1-odroid-c4.dts | 402 ++++++ src/arm64/amlogic/meson-sm1-sei610.dts | 2 +- src/arm64/amlogic/meson-sm1.dtsi | 24 + src/arm64/arm/foundation-v8-gicv2.dtsi | 4 +- src/arm64/arm/foundation-v8-gicv3.dtsi | 11 +- src/arm64/arm/foundation-v8.dtsi | 140 +- src/arm64/arm/fvp-base-revc.dts | 10 +- src/arm64/arm/juno-base.dtsi | 78 +- src/arm64/arm/juno-motherboard.dtsi | 174 +-- src/arm64/arm/rtsm_ve-aemv8a.dts | 2 +- src/arm64/arm/rtsm_ve-motherboard-rs2.dtsi | 4 +- src/arm64/arm/rtsm_ve-motherboard.dtsi | 152 +-- src/arm64/arm/vexpress-v2m-rs1.dtsi | 304 ++--- src/arm64/freescale/fsl-ls1012a-frdm.dts | 15 + src/arm64/freescale/fsl-ls1012a-frwy.dts | 15 + src/arm64/freescale/fsl-ls1012a-qds.dts | 15 + src/arm64/freescale/fsl-ls1012a-rdb.dts | 15 + src/arm64/freescale/fsl-ls1012a.dtsi | 13 + .../fsl-ls1028a-kontron-sl28-var2.dts | 4 +- .../freescale/fsl-ls1028a-kontron-sl28.dts | 5 + src/arm64/freescale/fsl-ls1028a.dtsi | 6 + src/arm64/freescale/fsl-ls1043a-rdb.dts | 33 + src/arm64/freescale/fsl-ls1043a.dtsi | 65 + src/arm64/freescale/fsl-lx2160a.dtsi | 130 +- .../freescale/imx8mm-beacon-baseboard.dtsi | 285 ++++ src/arm64/freescale/imx8mm-beacon-kit.dts | 19 + src/arm64/freescale/imx8mm-beacon-som.dtsi | 410 ++++++ src/arm64/freescale/imx8mm-evk.dts | 16 +- src/arm64/freescale/imx8mm.dtsi | 14 +- src/arm64/freescale/imx8mn-ddr4-evk.dts | 16 +- src/arm64/freescale/imx8mn.dtsi | 12 +- src/arm64/freescale/imx8mp.dtsi | 88 +- src/arm64/freescale/imx8mq-librem5-devkit.dts | 4 +- src/arm64/freescale/imx8mq.dtsi | 10 +- src/arm64/freescale/imx8qxp-mek.dts | 95 +- src/arm64/freescale/imx8qxp.dtsi | 18 +- src/arm64/freescale/qoriq-fman3-0.dtsi | 1 + src/arm64/hisilicon/hi3660.dtsi | 4 +- src/arm64/hisilicon/hi6220-coresight.dtsi | 130 +- src/arm64/hisilicon/hikey960-pinctrl.dtsi | 6 +- src/arm64/intel/socfpga_agilex.dtsi | 4 +- src/arm64/intel/socfpga_agilex_socdk.dts | 1 + src/arm64/marvell/armada-3720-db.dts | 3 + .../marvell/armada-3720-espressobin.dtsi | 2 +- src/arm64/marvell/armada-3720-turris-mox.dts | 10 +- src/arm64/marvell/armada-3720-uDPU.dts | 22 +- src/arm64/marvell/armada-37xx.dtsi | 4 +- .../marvell/armada-8040-clearfog-gt-8k.dts | 7 +- .../marvell/armada-8040-mcbin-singleshot.dts | 4 +- src/arm64/marvell/armada-8040-mcbin.dts | 4 +- src/arm64/marvell/armada-ap80x.dtsi | 1 - src/arm64/mediatek/mt2712-evb.dts | 74 ++ src/arm64/mediatek/mt2712e.dtsi | 158 ++- src/arm64/mediatek/mt6358.dtsi | 358 +++++ src/arm64/mediatek/mt6797-x20-dev.dts | 49 + src/arm64/mediatek/mt6797.dtsi | 231 +++- .../mediatek/mt7622-bananapi-bpi-r64.dts | 4 + src/arm64/mediatek/mt7622-rfb1.dts | 4 + src/arm64/mediatek/mt7622.dtsi | 11 + src/arm64/mediatek/mt8173-elm-hana-rev7.dts | 27 + src/arm64/mediatek/mt8173-elm-hana.dts | 14 + src/arm64/mediatek/mt8173-elm-hana.dtsi | 70 + src/arm64/mediatek/mt8173-elm.dts | 14 + src/arm64/mediatek/mt8173-elm.dtsi | 1173 +++++++++++++++++ src/arm64/mediatek/mt8173.dtsi | 80 +- src/arm64/mediatek/mt8183-evb.dts | 147 +++ src/arm64/mediatek/mt8183.dtsi | 50 +- src/arm64/mediatek/mt8516.dtsi | 17 + src/arm64/mediatek/pumpkin-common.dtsi | 34 + src/arm64/nvidia/tegra132-norrin.dts | 2 +- src/arm64/nvidia/tegra186-p3310.dtsi | 3 +- src/arm64/nvidia/tegra194-p2888.dtsi | 5 +- src/arm64/nvidia/tegra194.dtsi | 30 +- src/arm64/nvidia/tegra210-p2180.dtsi | 3 +- src/arm64/nvidia/tegra210-p2597.dtsi | 10 + src/arm64/nvidia/tegra210-p3450-0000.dts | 7 +- src/arm64/nvidia/tegra210.dtsi | 89 +- src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi | 74 -- src/arm64/qcom/apq8016-sbc-soc-pins.dtsi | 89 -- src/arm64/qcom/apq8016-sbc.dtsi | 257 +++- src/arm64/qcom/apq8096-db820c.dtsi | 53 +- src/arm64/qcom/ipq8074-hk01.dts | 108 +- src/arm64/qcom/ipq8074.dtsi | 502 +++---- src/arm64/qcom/msm8916-longcheer-l8150.dts | 25 +- src/arm64/qcom/msm8916-pins.dtsi | 221 ++-- .../qcom/msm8916-samsung-a2015-common.dtsi | 98 +- src/arm64/qcom/msm8916-samsung-a3u-eur.dts | 54 + src/arm64/qcom/msm8916-samsung-a5u-eur.dts | 35 + src/arm64/qcom/msm8916.dtsi | 228 +++- src/arm64/qcom/msm8996.dtsi | 87 +- src/arm64/qcom/msm8998.dtsi | 38 +- src/arm64/qcom/pm8150.dtsi | 14 +- src/arm64/qcom/pm8150b.dtsi | 14 +- src/arm64/qcom/pm8150l.dtsi | 14 +- src/arm64/qcom/pmi8994.dtsi | 6 + src/arm64/qcom/qcs404-evb.dtsi | 85 +- src/arm64/qcom/qcs404.dtsi | 100 ++ src/arm64/qcom/sc7180-idp.dts | 66 +- src/arm64/qcom/sc7180.dtsi | 963 ++++++++++++-- src/arm64/qcom/sdm660-xiaomi-lavender.dts | 46 + src/arm64/qcom/sdm660.dtsi | 372 ++++++ src/arm64/qcom/sdm845-cheza.dtsi | 7 + src/arm64/qcom/sdm845-db845c.dts | 210 +++ src/arm64/qcom/sdm845-mtp.dts | 2 +- src/arm64/qcom/sdm845.dtsi | 106 +- src/arm64/qcom/sdm850-lenovo-yoga-c630.dts | 13 + src/arm64/qcom/sm8250-mtp.dts | 351 +++++ src/arm64/qcom/sm8250.dtsi | 126 +- src/arm64/realtek/rtd1293-ds418j.dts | 6 +- src/arm64/realtek/rtd1293.dtsi | 12 +- src/arm64/realtek/rtd1295-mele-v9.dts | 6 +- src/arm64/realtek/rtd1295-probox2-ava.dts | 6 +- src/arm64/realtek/rtd1295-xnano-x5.dts | 30 + src/arm64/realtek/rtd1295-zidoo-x9s.dts | 4 +- src/arm64/realtek/rtd1295.dtsi | 21 +- src/arm64/realtek/rtd1296-ds418.dts | 4 +- src/arm64/realtek/rtd1296.dtsi | 8 +- src/arm64/realtek/rtd129x.dtsi | 209 ++- src/arm64/realtek/rtd1395-bpi-m4.dts | 30 + src/arm64/realtek/rtd1395-lionskin.dts | 36 + src/arm64/realtek/rtd1395.dtsi | 65 + src/arm64/realtek/rtd139x.dtsi | 193 +++ src/arm64/realtek/rtd1619-mjolnir.dts | 44 + src/arm64/realtek/rtd1619.dtsi | 12 + src/arm64/realtek/rtd16xx.dtsi | 229 ++++ .../aistarvision-mipi-adapter-2.1.dtsi | 94 ++ src/arm64/renesas/r8a774a1.dtsi | 18 +- src/arm64/renesas/r8a774b1.dtsi | 18 +- src/arm64/renesas/r8a774c0-ek874-mipi-2.1.dts | 72 + src/arm64/renesas/r8a774c0.dtsi | 18 +- src/arm64/renesas/r8a77950.dtsi | 14 +- src/arm64/renesas/r8a77951.dtsi | 34 +- src/arm64/renesas/r8a77960.dtsi | 22 +- src/arm64/renesas/r8a77961.dtsi | 403 +++++- src/arm64/renesas/r8a77965.dtsi | 20 +- src/arm64/renesas/r8a77970.dtsi | 10 +- src/arm64/renesas/r8a77980.dtsi | 16 +- src/arm64/renesas/r8a77990.dtsi | 20 +- src/arm64/renesas/r8a77995.dtsi | 20 +- src/arm64/rockchip/px30.dtsi | 3 + src/arm64/rockchip/rk3308-roc-cc.dts | 7 +- src/arm64/rockchip/rk3326-odroid-go2.dts | 557 ++++++++ src/arm64/rockchip/rk3326.dtsi | 15 + src/arm64/rockchip/rk3328-a1.dts | 2 +- src/arm64/rockchip/rk3328-roc-cc.dts | 4 +- src/arm64/rockchip/rk3328-rock64.dts | 4 +- src/arm64/rockchip/rk3328.dtsi | 2 +- src/arm64/rockchip/rk3368-geekbox.dts | 4 +- src/arm64/rockchip/rk3368-orion-r68-meta.dts | 4 +- src/arm64/rockchip/rk3368-r88.dts | 2 +- src/arm64/rockchip/rk3399-ficus.dts | 29 +- src/arm64/rockchip/rk3399-firefly.dts | 10 +- src/arm64/rockchip/rk3399-hugsun-x99.dts | 7 +- src/arm64/rockchip/rk3399-nanopi4.dtsi | 4 +- src/arm64/rockchip/rk3399-orangepi.dts | 4 +- src/arm64/rockchip/rk3399-pinebook-pro.dts | 11 +- src/arm64/rockchip/rk3399-rock960.dts | 29 +- src/arm64/rockchip/rk3399-rockpro64.dtsi | 27 + src/arm64/rockchip/rk3399.dtsi | 34 +- src/arm64/socionext/uniphier-ld11-global.dts | 1 + src/arm64/socionext/uniphier-ld11-ref.dts | 1 + src/arm64/socionext/uniphier-ld11.dtsi | 12 + src/arm64/socionext/uniphier-ld20-akebi96.dts | 189 +++ src/arm64/socionext/uniphier-ld20-global.dts | 1 + src/arm64/socionext/uniphier-ld20-ref.dts | 1 + src/arm64/socionext/uniphier-ld20.dtsi | 16 + src/arm64/socionext/uniphier-pxs3-ref.dts | 18 + src/arm64/socionext/uniphier-pxs3.dtsi | 12 + src/arm64/sprd/sc9863a.dtsi | 66 + src/arm64/sprd/sharkl3.dtsi | 164 +++ src/arm64/ti/k3-am65-main.dtsi | 126 ++ src/arm64/ti/k3-am65-mcu.dtsi | 21 + src/arm64/ti/k3-am65-wakeup.dtsi | 11 + src/arm64/ti/k3-am654-industrial-thermal.dtsi | 45 + src/arm64/ti/k3-j721e-common-proc-board.dts | 20 + src/arm64/ti/k3-j721e-main.dtsi | 87 ++ src/arm64/ti/k3-j721e-mcu-wakeup.dtsi | 11 + src/arm64/xilinx/zynqmp.dtsi | 6 +- src/mips/ingenic/ci20.dts | 3 + src/mips/ingenic/gcw0.dts | 507 ++++++- src/mips/ingenic/gcw0_proto.dts | 13 + src/mips/ingenic/jz4740.dtsi | 33 +- src/mips/ingenic/jz4770.dtsi | 227 +++- src/mips/ingenic/jz4780.dtsi | 65 +- src/mips/ingenic/x1000.dtsi | 9 +- src/mips/loongson/rs780e-pch.dtsi | 17 + src/mips/mscc/ocelot.dtsi | 2 +- src/mips/qca/ar9331.dtsi | 2 +- src/mips/qca/ar9331_dpt_module.dts | 6 +- src/powerpc/ep405.dts | 230 ---- src/powerpc/pcm032.dts | 4 +- src/powerpc/virtex440-ml507.dts | 406 ------ src/powerpc/virtex440-ml510.dts | 466 ------- src/powerpc/walnut.dts | 246 ---- 1396 files changed, 55802 insertions(+), 18784 deletions(-) rename Bindings/{ABI.txt => ABI.rst} (94%) create mode 100644 Bindings/arm/calxeda/hb-sregs.yaml delete mode 100644 Bindings/arm/calxeda/l2ecc.txt create mode 100644 Bindings/arm/calxeda/l2ecc.yaml create mode 100644 Bindings/arm/mediatek/mediatek,mipi0a.txt delete mode 100644 Bindings/arm/mediatek/mediatek,pericfg.txt create mode 100644 Bindings/arm/mediatek/mediatek,pericfg.yaml create mode 100644 Bindings/arm/mediatek/mediatek,vcodecsys.txt delete mode 100644 Bindings/ata/sata_highbank.txt create mode 100644 Bindings/ata/sata_highbank.yaml delete mode 100644 Bindings/auxdisplay/hit,hd44780.txt create mode 100644 Bindings/auxdisplay/hit,hd44780.yaml create mode 100644 Bindings/bus/arm,integrator-ap-lm.yaml create mode 100644 Bindings/bus/baikal,bt1-apb.yaml create mode 100644 Bindings/bus/baikal,bt1-axi.yaml create mode 100644 Bindings/clock/baikal,bt1-ccu-div.yaml create mode 100644 Bindings/clock/baikal,bt1-ccu-pll.yaml delete mode 100644 Bindings/clock/calxeda.txt create mode 100644 Bindings/clock/calxeda.yaml delete mode 100644 Bindings/clock/cirrus,lochnagar.txt create mode 100644 Bindings/clock/cirrus,lochnagar.yaml delete mode 100644 Bindings/clock/imx1-clock.txt create mode 100644 Bindings/clock/imx1-clock.yaml delete mode 100644 Bindings/clock/imx21-clock.txt create mode 100644 Bindings/clock/imx21-clock.yaml delete mode 100644 Bindings/clock/imx23-clock.txt create mode 100644 Bindings/clock/imx23-clock.yaml delete mode 100644 Bindings/clock/imx25-clock.txt create mode 100644 Bindings/clock/imx25-clock.yaml delete mode 100644 Bindings/clock/imx27-clock.txt create mode 100644 Bindings/clock/imx27-clock.yaml delete mode 100644 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delete mode 100644 Bindings/clock/imx8qxp-lpcg.txt create mode 100644 Bindings/clock/imx8qxp-lpcg.yaml delete mode 100644 Bindings/clock/ingenic,cgu.txt create mode 100644 Bindings/clock/ingenic,cgu.yaml create mode 100644 Bindings/clock/intel,agilex.yaml create mode 100644 Bindings/clock/intel,cgu-lgm.yaml create mode 100644 Bindings/clock/marvell,mmp2-audio-clock.yaml delete mode 100644 Bindings/clock/qcom,a53pll.txt create mode 100644 Bindings/clock/qcom,a53pll.yaml create mode 100644 Bindings/clock/renesas,cpg-div6-clock.yaml delete mode 100644 Bindings/clock/renesas,cpg-div6-clocks.txt delete mode 100644 Bindings/clock/renesas,cpg-mstp-clocks.txt create mode 100644 Bindings/clock/renesas,cpg-mstp-clocks.yaml create mode 100644 Bindings/cpufreq/nvidia,tegra20-cpufreq.txt delete mode 100644 Bindings/display/bridge/adi,adv7123.txt create mode 100644 Bindings/display/bridge/analogix,anx7814.yaml delete mode 100644 Bindings/display/bridge/anx7814.txt create mode 100644 Bindings/display/bridge/chrontel,ch7033.yaml delete mode 100644 Bindings/display/bridge/dumb-vga-dac.txt delete mode 100644 Bindings/display/bridge/dw_mipi_dsi.txt create mode 100644 Bindings/display/bridge/ite,it6505.yaml create mode 100644 Bindings/display/bridge/nwl-dsi.yaml create mode 100644 Bindings/display/bridge/simple-bridge.yaml create mode 100644 Bindings/display/bridge/snps,dw-mipi-dsi.yaml delete mode 100644 Bindings/display/bridge/thine,thc63lvd1024.txt create mode 100644 Bindings/display/bridge/thine,thc63lvd1024.yaml delete mode 100644 Bindings/display/bridge/ti,ths813x.txt delete mode 100644 Bindings/display/panel/arm,versatile-tft-panel.txt create mode 100644 Bindings/display/panel/arm,versatile-tft-panel.yaml create mode 100644 Bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml delete mode 100644 Bindings/display/panel/boe,himax8279d.txt create mode 100644 Bindings/display/panel/boe,himax8279d.yaml delete mode 100644 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Bindings/mmc/amlogic,meson-mx-sdhc.yaml create mode 100644 Bindings/mmc/ingenic,mmc.yaml delete mode 100644 Bindings/mmc/jz4740.txt delete mode 100644 Bindings/mmc/sdhci-pxa.txt create mode 100644 Bindings/mmc/sdhci-pxa.yaml create mode 100644 Bindings/mtd/arasan,nand-controller.yaml delete mode 100644 Bindings/mtd/ingenic,jz4780-nand.txt create mode 100644 Bindings/mtd/ingenic,nand.yaml delete mode 100644 Bindings/net/calxeda-xgmac.txt create mode 100644 Bindings/net/calxeda-xgmac.yaml create mode 100644 Bindings/net/imx-dwmac.txt create mode 100644 Bindings/net/mediatek,star-emac.yaml create mode 100644 Bindings/net/nxp,tja11xx.yaml delete mode 100644 Bindings/net/qca,ar71xx.txt create mode 100644 Bindings/net/qca,ar71xx.yaml create mode 100644 Bindings/net/qcom,ipq4019-mdio.yaml create mode 100644 Bindings/net/realtek-bluetooth.yaml delete mode 100644 Bindings/net/socionext,uniphier-ave4.txt create mode 100644 Bindings/net/socionext,uniphier-ave4.yaml delete mode 100644 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create mode 100644 Bindings/phy/cdns,salvo-phy.yaml create mode 100644 Bindings/phy/intel,combo-phy.yaml delete mode 100644 Bindings/phy/meson-gxl-usb3-phy.txt delete mode 100644 Bindings/phy/meson8b-usb2-phy.txt create mode 100644 Bindings/phy/qcom,qmp-phy.yaml create mode 100644 Bindings/phy/qcom,qmp-usb3-dp-phy.yaml create mode 100644 Bindings/phy/qcom,usb-snps-femto-v2.yaml delete mode 100644 Bindings/phy/qcom-qmp-phy.txt create mode 100644 Bindings/phy/qcom-usb-ipq4019-phy.yaml delete mode 100644 Bindings/phy/rcar-gen3-phy-usb2.txt delete mode 100644 Bindings/phy/rcar-gen3-phy-usb3.txt create mode 100644 Bindings/phy/renesas,usb2-phy.yaml create mode 100644 Bindings/phy/renesas,usb3-phy.yaml create mode 100644 Bindings/phy/rockchip-mipi-dphy-rx0.yaml create mode 100644 Bindings/phy/socionext,uniphier-pcie-phy.yaml create mode 100644 Bindings/phy/socionext,uniphier-usb2-phy.yaml create mode 100644 Bindings/phy/socionext,uniphier-usb3hs-phy.yaml create mode 100644 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create mode 100644 Bindings/power/supply/cw2015_battery.yaml create mode 100644 Bindings/power/supply/power-supply.yaml create mode 100644 Bindings/power/supply/rohm,bd99954.yaml create mode 100644 Bindings/power/supply/sbs,sbs-battery.yaml delete mode 100644 Bindings/power/supply/sbs_sbs-battery.txt delete mode 100644 Bindings/pwm/imx-pwm.txt create mode 100644 Bindings/pwm/imx-pwm.yaml delete mode 100644 Bindings/pwm/imx-tpm-pwm.txt create mode 100644 Bindings/pwm/imx-tpm-pwm.yaml delete mode 100644 Bindings/pwm/mxs-pwm.txt create mode 100644 Bindings/pwm/mxs-pwm.yaml delete mode 100644 Bindings/regulator/anatop-regulator.txt create mode 100644 Bindings/regulator/anatop-regulator.yaml delete mode 100644 Bindings/regulator/arizona-regulator.txt delete mode 100644 Bindings/regulator/cirrus,lochnagar.txt create mode 100644 Bindings/regulator/maxim,max77826.yaml create mode 100644 Bindings/regulator/wlf,arizona.yaml create mode 100644 Bindings/remoteproc/ingenic,vpu.yaml create mode 100644 Bindings/rng/arm-cctrng.yaml delete mode 100644 Bindings/rtc/dw-apb.txt delete mode 100644 Bindings/rtc/rtc-mxc.txt create mode 100644 Bindings/rtc/rtc-mxc.yaml delete mode 100644 Bindings/rtc/rtc-mxc_v2.txt create mode 100644 Bindings/rtc/rtc-mxc_v2.yaml delete mode 100644 Bindings/serial/8250.txt create mode 100644 Bindings/serial/8250.yaml delete mode 100644 Bindings/serial/ingenic,uart.txt create mode 100644 Bindings/serial/ingenic,uart.yaml delete mode 100644 Bindings/serial/mrvl-serial.txt delete mode 100644 Bindings/serial/qca,ar9330-uart.txt create mode 100644 Bindings/serial/qca,ar9330-uart.yaml create mode 100644 Bindings/serial/renesas,em-uart.yaml delete mode 100644 Bindings/soc/qcom/qcom,geni-se.txt create mode 100644 Bindings/soc/qcom/qcom,geni-se.yaml create mode 100644 Bindings/soc/ti/k3-socinfo.yaml delete mode 100644 Bindings/sound/cirrus,lochnagar.txt create mode 100644 Bindings/sound/cirrus,lochnagar.yaml create mode 100644 Bindings/sound/cirrus,madera.yaml create mode 100644 Bindings/sound/fsl,easrc.yaml delete mode 100644 Bindings/sound/madera.txt create mode 100644 Bindings/sound/marvell,mmp-sspa.yaml create mode 100644 Bindings/sound/rt1016.txt delete mode 100644 Bindings/sound/simple-card.txt create mode 100644 Bindings/sound/simple-card.yaml delete mode 100644 Bindings/sound/wlf,arizona.txt create mode 100644 Bindings/sound/wlf,arizona.yaml create mode 100644 Bindings/sound/zl38060.yaml create mode 100644 Bindings/spi/marvell,mmp2-ssp.yaml create mode 100644 Bindings/spi/mikrotik,rb4xx-spi.yaml create mode 100644 Bindings/spi/renesas,rspi.yaml delete mode 100644 Bindings/spi/snps,dw-apb-ssi.txt create mode 100644 Bindings/spi/snps,dw-apb-ssi.yaml create mode 100644 Bindings/spi/socionext,uniphier-spi.yaml delete mode 100644 Bindings/spi/spi-dw.txt delete mode 100644 Bindings/spi/spi-pxa2xx.txt delete mode 100644 Bindings/spi/spi-rspi.txt delete mode 100644 Bindings/spi/spi-uniphier.txt delete mode 100644 Bindings/sram/rockchip-pmu-sram.txt rename Bindings/{submitting-patches.txt => submitting-patches.rst} (92%) delete mode 100644 Bindings/thermal/imx-thermal.txt create mode 100644 Bindings/thermal/imx-thermal.yaml delete mode 100644 Bindings/thermal/imx8mm-thermal.txt create mode 100644 Bindings/thermal/imx8mm-thermal.yaml delete mode 100644 Bindings/thermal/rcar-gen3-thermal.txt create mode 100644 Bindings/thermal/rcar-gen3-thermal.yaml create mode 100644 Bindings/thermal/socionext,uniphier-thermal.yaml create mode 100644 Bindings/thermal/thermal-cooling-devices.yaml create mode 100644 Bindings/thermal/thermal-idle.yaml create mode 100644 Bindings/thermal/thermal-sensor.yaml create mode 100644 Bindings/thermal/thermal-zones.yaml create mode 100644 Bindings/thermal/ti,am654-thermal.yaml delete mode 100644 Bindings/thermal/uniphier-thermal.txt delete mode 100644 Bindings/timer/cadence,ttc-timer.txt create mode 100644 Bindings/timer/cdns,ttc.yaml delete mode 100644 Bindings/timer/fsl,imxgpt.txt create mode 100644 Bindings/timer/fsl,imxgpt.yaml delete mode 100644 Bindings/timer/ingenic,tcu.txt create mode 100644 Bindings/timer/ingenic,tcu.yaml delete mode 100644 Bindings/timer/nxp,sysctr-timer.txt create mode 100644 Bindings/timer/nxp,sysctr-timer.yaml delete mode 100644 Bindings/timer/nxp,tpm-timer.txt create mode 100644 Bindings/timer/nxp,tpm-timer.yaml delete mode 100644 Bindings/timer/renesas,cmt.txt create mode 100644 Bindings/timer/renesas,cmt.yaml create mode 100644 Bindings/timer/renesas,em-sti.yaml delete mode 100644 Bindings/timer/renesas,mtu2.txt create mode 100644 Bindings/timer/renesas,mtu2.yaml delete mode 100644 Bindings/timer/renesas,ostm.txt create mode 100644 Bindings/timer/renesas,ostm.yaml create mode 100644 Bindings/timer/snps,dw-apb-timer.yaml delete mode 100644 Bindings/usb/amlogic,dwc3.txt create mode 100644 Bindings/usb/brcm,bcm7445-ehci.yaml delete mode 100644 Bindings/usb/ehci-mv.txt delete mode 100644 Bindings/usb/keystone-usb.txt create mode 100644 Bindings/usb/marvell,pxau2o-ehci.yaml delete mode 100644 Bindings/usb/qcom,dwc3.txt create mode 100644 Bindings/usb/qcom,dwc3.yaml create mode 100644 Bindings/usb/ti,keystone-dwc3.yaml create mode 100644 Bindings/usb/ti,tps6598x.yaml delete mode 100644 Bindings/usb/usb-conn-gpio.txt create mode 100644 Bindings/watchdog/arm-smc-wdt.yaml delete mode 100644 Bindings/watchdog/fsl-imx-wdt.txt create mode 100644 Bindings/watchdog/fsl-imx-wdt.yaml delete mode 100644 Bindings/watchdog/fsl-imx7ulp-wdt.txt create mode 100644 Bindings/watchdog/fsl-imx7ulp-wdt.yaml delete mode 100644 Bindings/watchdog/renesas,wdt.txt create mode 100644 Bindings/watchdog/renesas,wdt.yaml create mode 100644 Bindings/watchdog/socionext,uniphier-wdt.yaml delete mode 100644 Bindings/watchdog/uniphier-wdt.txt rename Bindings/{writing-bindings.txt => writing-bindings.rst} (89%) create mode 100644 include/dt-bindings/clock/agilex-clock.h create mode 100644 include/dt-bindings/clock/bt1-ccu.h create mode 100644 include/dt-bindings/clock/intel,lgm-clk.h create mode 100644 include/dt-bindings/clock/marvell,mmp2-audio.h create mode 100644 include/dt-bindings/clock/mt6765-clk.h create mode 100644 include/dt-bindings/clock/qcom,gcc-msm8939.h create mode 100644 include/dt-bindings/clock/r8a7742-cpg-mssr.h create mode 100644 include/dt-bindings/clock/x1830-cgu.h create mode 100644 include/dt-bindings/interconnect/imx8mm.h create mode 100644 include/dt-bindings/interconnect/imx8mn.h create mode 100644 include/dt-bindings/interconnect/imx8mq.h create mode 100644 include/dt-bindings/mailbox/qcom-ipcc.h create mode 100644 include/dt-bindings/pinctrl/pads-imx8dxl.h create mode 100644 include/dt-bindings/power/marvell,mmp2.h create mode 100644 include/dt-bindings/power/meson-gxbb-power.h create mode 100644 include/dt-bindings/power/meson8-power.h create mode 100644 include/dt-bindings/power/r8a7742-sysc.h create mode 100644 include/dt-bindings/reset/bt1-ccu.h create mode 100644 include/dt-bindings/reset/imx8mp-reset.h create mode 100644 include/dt-bindings/reset/qcom,gcc-msm8939.h create mode 100644 include/dt-bindings/reset/realtek,rtd1195.h create mode 100644 src/arm/am5729-beagleboneai.dts create mode 100644 src/arm/aspeed-bmc-facebook-yosemitev2.dts create mode 100644 src/arm/aspeed-bmc-opp-nicole.dts create mode 100644 src/arm/at91-sama5d2_icp.dts create mode 100644 src/arm/bcm2835-rpi-common.dtsi create mode 100644 src/arm/dra7-ipu-dsp-common.dtsi create mode 100644 src/arm/dra74-ipu-dsp-common.dtsi create mode 100644 src/arm/exynos4210-i9100.dts create mode 100644 src/arm/imx6dl-colibri-v1_1-eval-v3.dts create mode 100644 src/arm/imx6qdl-colibri-v1_1-uhs.dtsi create mode 100644 src/arm/integratorap-im-pd1.dts create mode 100644 src/arm/kirkwood-l-50.dts create mode 100644 src/arm/r8a7742-iwg21d-q7.dts create mode 100644 src/arm/r8a7742-iwg21m.dtsi create mode 100644 src/arm/r8a7742.dtsi create mode 100644 src/arm/rtd1195-horseradish.dts create mode 100644 src/arm/rtd1195-mele-x1000.dts create mode 100644 src/arm/rtd1195.dtsi create mode 100644 src/arm/stm32mp157a-dhcor-avenger96.dts create mode 100644 src/arm/stm32mp157a-iot-box.dts create mode 100644 src/arm/stm32mp157a-stinger96.dts create mode 100644 src/arm/stm32mp157a-stinger96.dtsi create mode 100644 src/arm/stm32mp157c-lxa-mc1.dts create mode 100644 src/arm/stm32mp15xx-dhcom-pdk2.dtsi rename src/arm/{stm32mp157c-dhcom-som.dtsi => stm32mp15xx-dhcom-som.dtsi} (98%) create mode 100644 src/arm/stm32mp15xx-dhcor-avenger96.dtsi create mode 100644 src/arm/stm32mp15xx-dhcor-io1v8.dtsi create mode 100644 src/arm/stm32mp15xx-dhcor-som.dtsi create mode 100644 src/arm/stm32mp15xx-osd32.dtsi create mode 100644 src/arm/sun7i-a20-olinuxino-lime-emmc.dts create mode 100644 src/arm64/allwinner/sun50i-h6-cpu-opp.dtsi create mode 100644 src/arm64/amlogic/meson-g12b-gtking-pro.dts create mode 100644 src/arm64/amlogic/meson-g12b-gtking.dts create mode 100644 src/arm64/amlogic/meson-g12b-w400.dtsi create mode 100644 src/arm64/amlogic/meson-gxl-s805x.dtsi create mode 100644 src/arm64/amlogic/meson-gxl-s905d-sml5442tw.dts create mode 100644 src/arm64/amlogic/meson-sm1-odroid-c4.dts create mode 100644 src/arm64/freescale/imx8mm-beacon-baseboard.dtsi create mode 100644 src/arm64/freescale/imx8mm-beacon-kit.dts create mode 100644 src/arm64/freescale/imx8mm-beacon-som.dtsi create mode 100644 src/arm64/mediatek/mt6358.dtsi create mode 100644 src/arm64/mediatek/mt8173-elm-hana-rev7.dts create mode 100644 src/arm64/mediatek/mt8173-elm-hana.dts create mode 100644 src/arm64/mediatek/mt8173-elm-hana.dtsi create mode 100644 src/arm64/mediatek/mt8173-elm.dts create mode 100644 src/arm64/mediatek/mt8173-elm.dtsi delete mode 100644 src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi delete mode 100644 src/arm64/qcom/apq8016-sbc-soc-pins.dtsi create mode 100644 src/arm64/qcom/sdm660-xiaomi-lavender.dts create mode 100644 src/arm64/qcom/sdm660.dtsi create mode 100644 src/arm64/realtek/rtd1295-xnano-x5.dts create mode 100644 src/arm64/realtek/rtd1395-bpi-m4.dts create mode 100644 src/arm64/realtek/rtd1395-lionskin.dts create mode 100644 src/arm64/realtek/rtd1395.dtsi create mode 100644 src/arm64/realtek/rtd139x.dtsi create mode 100644 src/arm64/realtek/rtd1619-mjolnir.dts create mode 100644 src/arm64/realtek/rtd1619.dtsi create mode 100644 src/arm64/realtek/rtd16xx.dtsi create mode 100644 src/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi create mode 100644 src/arm64/renesas/r8a774c0-ek874-mipi-2.1.dts create mode 100644 src/arm64/rockchip/rk3326-odroid-go2.dts create mode 100644 src/arm64/rockchip/rk3326.dtsi create mode 100644 src/arm64/socionext/uniphier-ld20-akebi96.dts create mode 100644 src/arm64/ti/k3-am654-industrial-thermal.dtsi create mode 100644 src/mips/ingenic/gcw0_proto.dts delete mode 100644 src/powerpc/ep405.dts delete mode 100644 src/powerpc/virtex440-ml507.dts delete mode 100644 src/powerpc/virtex440-ml510.dts delete mode 100644 src/powerpc/walnut.dts diff --git a/Bindings/ABI.txt b/Bindings/ABI.rst similarity index 94% rename from Bindings/ABI.txt rename to Bindings/ABI.rst index d25f8d379680..a885713cf184 100644 --- a/Bindings/ABI.txt +++ b/Bindings/ABI.rst @@ -1,5 +1,8 @@ +.. SPDX-License-Identifier: GPL-2.0 - Devicetree (DT) ABI +=================== +Devicetree (DT) ABI +=================== I. Regarding stable bindings/ABI, we quote from the 2013 ARM mini-summit summary document: diff --git a/Bindings/Makefile b/Bindings/Makefile index 7782d9985082..91c4d00e96d3 100644 --- a/Bindings/Makefile +++ b/Bindings/Makefile @@ -2,13 +2,20 @@ DT_DOC_CHECKER ?= dt-doc-validate DT_EXTRACT_EX ?= dt-extract-example DT_MK_SCHEMA ?= dt-mk-schema -DT_MK_SCHEMA_USERONLY_FLAG := $(if $(DT_SCHEMA_FILES), -u) + +DT_SCHEMA_MIN_VERSION = 2020.5 + +PHONY += check_dtschema_version +check_dtschema_version: + @{ echo $(DT_SCHEMA_MIN_VERSION); \ + $(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -VC || \ + { echo "ERROR: dtschema minimum version is v$(DT_SCHEMA_MIN_VERSION)" >&2; false; } quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<) cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \ $(DT_EXTRACT_EX) $< > $@ -$(obj)/%.example.dts: $(src)/%.yaml FORCE +$(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE $(call if_changed,chk_binding) # Use full schemas when checking %.example.dts @@ -27,21 +34,40 @@ quiet_cmd_mk_schema = SCHEMA $@ DT_DOCS = $(shell $(find_cmd) | sed -e 's|^$(srctree)/||') -DT_SCHEMA_FILES ?= $(DT_DOCS) +override DTC_FLAGS := \ + -Wno-avoid_unnecessary_addr_size \ + -Wno-graph_child_address \ + -Wno-interrupt_provider + +$(obj)/processed-schema-examples.yaml: $(DT_DOCS) check_dtschema_version FORCE + $(call if_changed,mk_schema) + +ifeq ($(DT_SCHEMA_FILES),) + +# Unless DT_SCHEMA_FILES is specified, use the full schema for dtbs_check too. +# Just copy processed-schema-examples.yaml + +$(obj)/processed-schema.yaml: $(obj)/processed-schema-examples.yaml FORCE + $(call if_changed,copy) + +DT_SCHEMA_FILES = $(DT_DOCS) + +else + +# If DT_SCHEMA_FILES is specified, use it for processed-schema.yaml + +$(obj)/processed-schema.yaml: DT_MK_SCHEMA_FLAGS := -u +$(obj)/processed-schema.yaml: $(DT_SCHEMA_FILES) check_dtschema_version FORCE + $(call if_changed,mk_schema) + +endif extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES)) extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES)) extra-$(CHECK_DT_BINDING) += processed-schema-examples.yaml +extra-$(CHECK_DTBS) += processed-schema.yaml -override DTC_FLAGS := \ - -Wno-avoid_unnecessary_addr_size \ - -Wno-graph_child_address - -$(obj)/processed-schema-examples.yaml: $(DT_DOCS) FORCE - $(call if_changed,mk_schema) - -$(obj)/processed-schema.yaml: DT_MK_SCHEMA_FLAGS := $(DT_MK_SCHEMA_USERONLY_FLAG) -$(obj)/processed-schema.yaml: $(DT_SCHEMA_FILES) FORCE - $(call if_changed,mk_schema) - -extra-y += processed-schema.yaml +# Hack: avoid 'Argument list too long' error for 'make clean'. Remove most of +# build artifacts here before they are processed by scripts/Makefile.clean +clean-files = $(shell find $(obj) \( -name '*.example.dts' -o \ + -name '*.example.dt.yaml' \) -delete 2>/dev/null) diff --git a/Bindings/arm/altera.yaml b/Bindings/arm/altera.yaml index 49e0362ddc11..b388c5aa7984 100644 --- a/Bindings/arm/altera.yaml +++ b/Bindings/arm/altera.yaml @@ -13,8 +13,8 @@ properties: compatible: items: - enum: - - altr,socfpga-cyclone5 - - altr,socfpga-arria5 - - altr,socfpga-arria10 + - altr,socfpga-cyclone5 + - altr,socfpga-arria5 + - altr,socfpga-arria10 - const: altr,socfpga ... diff --git a/Bindings/arm/amlogic.yaml b/Bindings/arm/amlogic.yaml index f74aba48cec1..378229fa8310 100644 --- a/Bindings/arm/amlogic.yaml +++ b/Bindings/arm/amlogic.yaml @@ -17,7 +17,7 @@ description: |+ any time. Be sure to use a device tree binary and a kernel image generated from the same source tree. - Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a + Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a stable binding/ABI. properties: @@ -107,6 +107,7 @@ properties: - amlogic,p231 - libretech,aml-s905d-pc - phicomm,n1 + - smartlabs,sml5442tw - const: amlogic,s905d - const: amlogic,meson-gxl @@ -148,6 +149,8 @@ properties: - description: Boards with the Amlogic Meson G12B S922X SoC items: - enum: + - azw,gtking + - azw,gtking-pro - hardkernel,odroid-n2 - khadas,vim3 - ugoos,am6 @@ -159,6 +162,7 @@ properties: - enum: - seirobotics,sei610 - khadas,vim3l + - hardkernel,odroid-c4 - const: amlogic,sm1 - description: Boards with the Amlogic Meson A1 A113L SoC diff --git a/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml index 66213bd95e6e..6cc74523ebfd 100644 --- a/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml +++ b/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml @@ -25,7 +25,7 @@ select: properties: compatible: - items: + items: - const: amlogic,meson-gx-ao-secure - const: syscon diff --git a/Bindings/arm/arm,scmi.txt b/Bindings/arm/arm,scmi.txt index dc102c4e4a78..1f293ea24cd8 100644 --- a/Bindings/arm/arm,scmi.txt +++ b/Bindings/arm/arm,scmi.txt @@ -14,7 +14,7 @@ Required properties: The scmi node with the following properties shall be under the /firmware/ node. -- compatible : shall be "arm,scmi" +- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports - mboxes: List of phandle and mailbox channel specifiers. It should contain exactly one or two mailboxes, one for transmitting messages("tx") and another optional for receiving the notifications("rx") if @@ -25,6 +25,7 @@ The scmi node with the following properties shall be under the /firmware/ node. protocol identifier for a given sub-node. - #size-cells : should be '0' as 'reg' property doesn't have any size associated with it. +- arm,smc-id : SMC id required when using smc or hvc transports Optional properties: diff --git a/Bindings/arm/arm,vexpress-juno.yaml b/Bindings/arm/arm,vexpress-juno.yaml index 8c06a73f716c..a3420c81cf35 100644 --- a/Bindings/arm/arm,vexpress-juno.yaml +++ b/Bindings/arm/arm,vexpress-juno.yaml @@ -131,26 +131,23 @@ properties: property, describing the physical location of the children nodes. 0 means motherboard site, while 1 and 2 are daughterboard sites, and 0xf means "sisterboard" which is the site containing the main CPU tile. - allOf: - - $ref: '/schemas/types.yaml#/definitions/uint32' - - minimum: 0 - maximum: 15 + $ref: '/schemas/types.yaml#/definitions/uint32' + minimum: 0 + maximum: 15 arm,vexpress,position: description: When daughterboards are stacked on one site, their position in the stack be be described this attribute. - allOf: - - $ref: '/schemas/types.yaml#/definitions/uint32' - - minimum: 0 - maximum: 3 + $ref: '/schemas/types.yaml#/definitions/uint32' + minimum: 0 + maximum: 3 arm,vexpress,dcc: description: When describing tiles consisting of more than one DCC, its number can be specified with this attribute. - allOf: - - $ref: '/schemas/types.yaml#/definitions/uint32' - - minimum: 0 - maximum: 3 + $ref: '/schemas/types.yaml#/definitions/uint32' + minimum: 0 + maximum: 3 patternProperties: "^bus@[0-9a-f]+$": @@ -162,8 +159,7 @@ patternProperties: "simple-bus". If the compatible is placed in the "motherboard" node, it is stricter and always has two compatibles. type: object - allOf: - - $ref: '/schemas/simple-bus.yaml' + $ref: '/schemas/simple-bus.yaml' properties: compatible: @@ -195,11 +191,11 @@ patternProperties: - const: simple-bus arm,v2m-memory-map: description: This describes the memory map type. - allOf: - - $ref: '/schemas/types.yaml#/definitions/string' - - enum: - - rs1 - - rs2 + $ref: '/schemas/types.yaml#/definitions/string' + enum: + - rs1 + - rs2 + required: - compatible required: diff --git a/Bindings/arm/atmel-at91.yaml b/Bindings/arm/atmel-at91.yaml index 0357314076bc..31b0c54fa2cf 100644 --- a/Bindings/arm/atmel-at91.yaml +++ b/Bindings/arm/atmel-at91.yaml @@ -82,6 +82,13 @@ properties: - const: atmel,sama5d2 - const: atmel,sama5 + - description: Microchip SAMA5D2 Industrial Connectivity Platform + items: + - const: microchip,sama5d2-icp + - const: atmel,sama5d27 + - const: atmel,sama5d2 + - const: atmel,sama5 + - description: SAM9X60-EK board items: - const: microchip,sam9x60ek diff --git a/Bindings/arm/bitmain.yaml b/Bindings/arm/bitmain.yaml index 0efdb4ac028e..5cd5b36cff2d 100644 --- a/Bindings/arm/bitmain.yaml +++ b/Bindings/arm/bitmain.yaml @@ -13,6 +13,6 @@ properties: compatible: items: - enum: - - bitmain,sophon-edge + - bitmain,sophon-edge - const: bitmain,bm1880 ... diff --git a/Bindings/arm/calxeda/hb-sregs.yaml b/Bindings/arm/calxeda/hb-sregs.yaml new file mode 100644 index 000000000000..dfdc97083efb --- /dev/null +++ b/Bindings/arm/calxeda/hb-sregs.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank system registers + +description: | + The Calxeda Highbank system has a block of MMIO registers controlling + several generic system aspects. Those can be used to control some power + management, they also contain some gate and PLL clocks. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: calxeda,hb-sregs + + reg: + maxItems: 1 + + clocks: + type: object + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + sregs@fff3c000 { + compatible = "calxeda,hb-sregs"; + reg = <0xfff3c000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333000>; + }; + }; + }; diff --git a/Bindings/arm/calxeda/l2ecc.txt b/Bindings/arm/calxeda/l2ecc.txt deleted file mode 100644 index 94e642a33db0..000000000000 --- a/Bindings/arm/calxeda/l2ecc.txt +++ /dev/null @@ -1,15 +0,0 @@ -Calxeda Highbank L2 cache ECC - -Properties: -- compatible : Should be "calxeda,hb-sregs-l2-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. - -Example: - - sregs@fff3c200 { - compatible = "calxeda,hb-sregs-l2-ecc"; - reg = <0xfff3c200 0x100>; - interrupts = <0 71 4 0 72 4>; - }; diff --git a/Bindings/arm/calxeda/l2ecc.yaml b/Bindings/arm/calxeda/l2ecc.yaml new file mode 100644 index 000000000000..a9fe01238a88 --- /dev/null +++ b/Bindings/arm/calxeda/l2ecc.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank L2 cache ECC + +description: | + Binding for the Calxeda Highbank L2 cache controller ECC device. + This does not cover the actual L2 cache controller control registers, + but just the error reporting functionality. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: "calxeda,hb-sregs-l2-ecc" + + reg: + maxItems: 1 + + interrupts: + items: + - description: single bit error interrupt + - description: double bit error interrupt + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + sregs@fff3c200 { + compatible = "calxeda,hb-sregs-l2-ecc"; + reg = <0xfff3c200 0x100>; + interrupts = <0 71 4>, <0 72 4>; + }; diff --git a/Bindings/arm/coresight-cti.yaml b/Bindings/arm/coresight-cti.yaml index 3db3642bd532..17df5cd12d8d 100644 --- a/Bindings/arm/coresight-cti.yaml +++ b/Bindings/arm/coresight-cti.yaml @@ -140,16 +140,14 @@ patternProperties: maxItems: 1 arm,trig-in-sigs: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 maxItems: 32 description: List of CTI trigger in signal numbers in use by a trig-conns node. arm,trig-in-types: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 maxItems: 32 description: @@ -159,16 +157,14 @@ patternProperties: completely, then the types will default to GEN_IO. arm,trig-out-sigs: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 maxItems: 32 description: List of CTI trigger out signal numbers in use by a trig-conns node. arm,trig-out-types: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 maxItems: 32 description: @@ -178,8 +174,7 @@ patternProperties: or omitted completely, then the types will default to GEN_IO. arm,trig-filters: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 maxItems: 32 description: @@ -187,8 +182,7 @@ patternProperties: active, unless filtering is disabled on the driver. arm,trig-conn-name: - allOf: - - $ref: /schemas/types.yaml#/definitions/string + $ref: /schemas/types.yaml#/definitions/string description: Defines a connection name that will be displayed, if the cpu or arm,cs-dev-assoc properties are not being used in this connection. @@ -301,7 +295,7 @@ examples: - | cti@20110000 { compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0 0x20110000 0 0x1000>; + reg = <0x20110000 0x1000>; clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; diff --git a/Bindings/arm/cpus.yaml b/Bindings/arm/cpus.yaml index a01814765ddb..40f692c846f0 100644 --- a/Bindings/arm/cpus.yaml +++ b/Bindings/arm/cpus.yaml @@ -167,53 +167,53 @@ properties: - qcom,kryo260 - qcom,kryo280 - qcom,kryo385 + - qcom,kryo468 - qcom,kryo485 - qcom,scorpion enable-method: - allOf: - - $ref: '/schemas/types.yaml#/definitions/string' - - oneOf: - # On ARM v8 64-bit this property is required - - enum: - - psci - - spin-table - # On ARM 32-bit systems this property is optional - - enum: - - actions,s500-smp - - allwinner,sun6i-a31 - - allwinner,sun8i-a23 - - allwinner,sun9i-a80-smp - - allwinner,sun8i-a83t-smp - - amlogic,meson8-smp - - amlogic,meson8b-smp - - arm,realview-smp - - aspeed,ast2600-smp - - brcm,bcm11351-cpu-method - - brcm,bcm23550 - - brcm,bcm2836-smp - - brcm,bcm63138 - - brcm,bcm-nsp-smp - - brcm,brahma-b15 - - marvell,armada-375-smp - - marvell,armada-380-smp - - marvell,armada-390-smp - - marvell,armada-xp-smp - - marvell,98dx3236-smp - - marvell,mmp3-smp - - mediatek,mt6589-smp - - mediatek,mt81xx-tz-smp - - qcom,gcc-msm8660 - - qcom,kpss-acc-v1 - - qcom,kpss-acc-v2 - - renesas,apmu - - renesas,r9a06g032-smp - - rockchip,rk3036-smp - - rockchip,rk3066-smp - - socionext,milbeaut-m10v-smp - - ste,dbx500-smp - - ti,am3352 - - ti,am4372 + $ref: '/schemas/types.yaml#/definitions/string' + oneOf: + # On ARM v8 64-bit this property is required + - enum: + - psci + - spin-table + # On ARM 32-bit systems this property is optional + - enum: + - actions,s500-smp + - allwinner,sun6i-a31 + - allwinner,sun8i-a23 + - allwinner,sun9i-a80-smp + - allwinner,sun8i-a83t-smp + - amlogic,meson8-smp + - amlogic,meson8b-smp + - arm,realview-smp + - aspeed,ast2600-smp + - brcm,bcm11351-cpu-method + - brcm,bcm23550 + - brcm,bcm2836-smp + - brcm,bcm63138 + - brcm,bcm-nsp-smp + - brcm,brahma-b15 + - marvell,armada-375-smp + - marvell,armada-380-smp + - marvell,armada-390-smp + - marvell,armada-xp-smp + - marvell,98dx3236-smp + - marvell,mmp3-smp + - mediatek,mt6589-smp + - mediatek,mt81xx-tz-smp + - qcom,gcc-msm8660 + - qcom,kpss-acc-v1 + - qcom,kpss-acc-v2 + - renesas,apmu + - renesas,r9a06g032-smp + - rockchip,rk3036-smp + - rockchip,rk3066-smp + - socionext,milbeaut-m10v-smp + - ste,dbx500-smp + - ti,am3352 + - ti,am4372 cpu-release-addr: $ref: '/schemas/types.yaml#/definitions/uint64' diff --git a/Bindings/arm/freescale/fsl,scu.txt b/Bindings/arm/freescale/fsl,scu.txt index 623fedf12180..10b8459e49f8 100644 --- a/Bindings/arm/freescale/fsl,scu.txt +++ b/Bindings/arm/freescale/fsl,scu.txt @@ -47,7 +47,7 @@ Required properties: &lsio_mu1 1 2 &lsio_mu1 1 3 &lsio_mu1 3 3>; - See Documentation/devicetree/bindings/mailbox/fsl,mu.txt + See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml for detailed mailbox binding. Note: Each mu which supports general interrupt should have an alias correctly @@ -108,7 +108,8 @@ This binding uses the i.MX common pinctrl binding[3]. Required properties: - compatible: Should be one of: "fsl,imx8qm-iomuxc", - "fsl,imx8qxp-iomuxc". + "fsl,imx8qxp-iomuxc", + "fsl,imx8dxl-iomuxc". Required properties for Pinctrl sub nodes: - fsl,pins: Each entry consists of 3 integers which represents @@ -116,7 +117,8 @@ Required properties for Pinctrl sub nodes: integers are specified using a PIN_FUNC_ID macro, which can be found in , - . + , + . The last integer CONFIG is the pad setting value like pull-up on this pin. diff --git a/Bindings/arm/fsl.yaml b/Bindings/arm/fsl.yaml index cd3fbe7e3948..05906e291e38 100644 --- a/Bindings/arm/fsl.yaml +++ b/Bindings/arm/fsl.yaml @@ -119,6 +119,7 @@ properties: - fsl,imx6q-sabreauto - fsl,imx6q-sabrelite - fsl,imx6q-sabresd + - kontron,imx6q-samx6i # Kontron i.MX6 Dual/Quad SMARC Module - technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf - technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit - technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph @@ -170,6 +171,7 @@ properties: - emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base - fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board - fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board + - kontron,imx6dl-samx6i # Kontron i.MX6 Solo SMARC Module - technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf - technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit - technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph @@ -177,7 +179,9 @@ properties: - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 - toradex,colibri_imx6dl # Colibri iMX6 Module + - toradex,colibri_imx6dl-v1_1 # Colibri iMX6 Module V1.1 - toradex,colibri_imx6dl-eval-v3 # Colibri iMX6 Module on Colibri Evaluation Board V3 + - toradex,colibri_imx6dl-v1_1-eval-v3 # Colibri iMX6 Module V1.1 on Colibri Evaluation Board V3 - ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board - ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board - ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board diff --git a/Bindings/arm/l2c2x0.yaml b/Bindings/arm/l2c2x0.yaml index 5d1d50eea26e..6b8f4d4fa580 100644 --- a/Bindings/arm/l2c2x0.yaml +++ b/Bindings/arm/l2c2x0.yaml @@ -70,43 +70,39 @@ properties: description: Cycles of latency for Data RAM accesses. Specifies 3 cells of read, write and setup latencies. Minimum valid values are 1. Controllers without setup latency control should use a value of 0. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 2 - maxItems: 3 - items: - minimum: 0 - maximum: 8 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 3 + items: + minimum: 0 + maximum: 8 arm,tag-latency: description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of read, write and setup latencies. Controllers without setup latency control should use 0. Controllers without separate read and write Tag RAM latency values should only use the first cell. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 1 - maxItems: 3 - items: - minimum: 0 - maximum: 8 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 3 + items: + minimum: 0 + maximum: 8 arm,dirty-latency: description: Cycles of latency for Dirty RAMs. This is a single cell. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 1 - maximum: 8 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 8 arm,filter-ranges: description: Starting address and length of window to filter. Addresses in the filter window are directed to the M1 port. Other addresses will go to the M0 port. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - items: - minItems: 2 - maxItems: 2 + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + minItems: 2 + maxItems: 2 arm,io-coherent: description: indicates that the system is operating in an hardware @@ -131,36 +127,31 @@ properties: arm,double-linefill: description: Override double linefill enable setting. Enable if non-zero, disable if zero. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 0, 1 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] arm,double-linefill-incr: description: Override double linefill on INCR read. Enable if non-zero, disable if zero. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 0, 1 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] arm,double-linefill-wrap: description: Override double linefill on WRAP read. Enable if non-zero, disable if zero. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 0, 1 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] arm,prefetch-drop: description: Override prefetch drop enable setting. Enable if non-zero, disable if zero. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 0, 1 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] arm,prefetch-offset: description: Override prefetch offset value. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31] arm,shared-override: description: The default behavior of the L220 or PL310 cache @@ -193,35 +184,31 @@ properties: description: | Data prefetch. Value: <0> (forcibly disable), <1> (forcibly enable), property absent (retain settings set by firmware) - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 0, 1 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] prefetch-instr: description: | Instruction prefetch. Value: <0> (forcibly disable), <1> (forcibly enable), property absent (retain settings set by firmware) - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 0, 1 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] arm,dynamic-clock-gating: description: | L2 dynamic clock gating. Value: <0> (forcibly disable), <1> (forcibly enable), property absent (OS specific behavior, preferably retain firmware settings) - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 0, 1 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] arm,standby-mode: description: L2 standby mode enable. Value <0> (forcibly disable), <1> (forcibly enable), property absent (OS specific behavior, preferably retain firmware settings) - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 0, 1 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] arm,early-bresp-disable: description: Disable the CA9 optimization Early BRESP (PL310) diff --git a/Bindings/arm/mediatek.yaml b/Bindings/arm/mediatek.yaml index 4043c5046441..abc544dde692 100644 --- a/Bindings/arm/mediatek.yaml +++ b/Bindings/arm/mediatek.yaml @@ -84,6 +84,28 @@ properties: - enum: - mediatek,mt8135-evbp1 - const: mediatek,mt8135 + - description: Google Elm (Acer Chromebook R13) + items: + - const: google,elm-rev8 + - const: google,elm-rev7 + - const: google,elm-rev6 + - const: google,elm-rev5 + - const: google,elm-rev4 + - const: google,elm-rev3 + - const: google,elm + - const: mediatek,mt8173 + - description: Google Hana (Lenovo Chromebook N23 Yoga, C330, 300e,...) + items: + - const: google,hana-rev6 + - const: google,hana-rev5 + - const: google,hana-rev4 + - const: google,hana-rev3 + - const: google,hana + - const: mediatek,mt8173 + - description: Google Hana rev7 (Poin2 Chromebook 11C) + items: + - const: google,hana-rev7 + - const: mediatek,mt8173 - items: - enum: - mediatek,mt8173-evb diff --git a/Bindings/arm/mediatek/mediatek,apmixedsys.txt b/Bindings/arm/mediatek/mediatek,apmixedsys.txt index ff000ccade78..bd7a0fa5801b 100644 --- a/Bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-apmixedsys" - "mediatek,mt2712-apmixedsys", "syscon" + - "mediatek,mt6765-apmixedsys", "syscon" - "mediatek,mt6779-apmixedsys", "syscon" - "mediatek,mt6797-apmixedsys" - "mediatek,mt7622-apmixedsys" diff --git a/Bindings/arm/mediatek/mediatek,audsys.txt b/Bindings/arm/mediatek/mediatek,audsys.txt index e4ca7b703123..38309db115f5 100644 --- a/Bindings/arm/mediatek/mediatek,audsys.txt +++ b/Bindings/arm/mediatek/mediatek,audsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-audsys", "syscon" + - "mediatek,mt6765-audsys", "syscon" - "mediatek,mt6779-audio", "syscon" - "mediatek,mt7622-audsys", "syscon" - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" diff --git a/Bindings/arm/mediatek/mediatek,camsys.txt b/Bindings/arm/mediatek/mediatek,camsys.txt index 1f4aaa15a37e..a0ce82085ad0 100644 --- a/Bindings/arm/mediatek/mediatek,camsys.txt +++ b/Bindings/arm/mediatek/mediatek,camsys.txt @@ -6,6 +6,7 @@ The MediaTek camsys controller provides various clocks to the system. Required Properties: - compatible: Should be one of: + - "mediatek,mt6765-camsys", "syscon" - "mediatek,mt6779-camsys", "syscon" - "mediatek,mt8183-camsys", "syscon" - #clock-cells: Must be 1 diff --git a/Bindings/arm/mediatek/mediatek,imgsys.txt b/Bindings/arm/mediatek/mediatek,imgsys.txt index 2b693e343c56..1e1f00718a7d 100644 --- a/Bindings/arm/mediatek/mediatek,imgsys.txt +++ b/Bindings/arm/mediatek/mediatek,imgsys.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-imgsys", "syscon" - "mediatek,mt2712-imgsys", "syscon" + - "mediatek,mt6765-imgsys", "syscon" - "mediatek,mt6779-imgsys", "syscon" - "mediatek,mt6797-imgsys", "syscon" - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon" diff --git a/Bindings/arm/mediatek/mediatek,infracfg.txt b/Bindings/arm/mediatek/mediatek,infracfg.txt index db2f4fd754e7..49a968be1a80 100644 --- a/Bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Bindings/arm/mediatek/mediatek,infracfg.txt @@ -9,6 +9,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-infracfg", "syscon" - "mediatek,mt2712-infracfg", "syscon" + - "mediatek,mt6765-infracfg", "syscon" - "mediatek,mt6779-infracfg_ao", "syscon" - "mediatek,mt6797-infracfg", "syscon" - "mediatek,mt7622-infracfg", "syscon" diff --git a/Bindings/arm/mediatek/mediatek,mipi0a.txt b/Bindings/arm/mediatek/mediatek,mipi0a.txt new file mode 100644 index 000000000000..8be5978f388d --- /dev/null +++ b/Bindings/arm/mediatek/mediatek,mipi0a.txt @@ -0,0 +1,28 @@ +Mediatek mipi0a (mipi_rx_ana_csi0a) controller +============================ + +The Mediatek mipi0a controller provides various clocks +to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt6765-mipi0a", "syscon" +- #clock-cells: Must be 1 + +The mipi0a controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +The mipi0a controller also uses the common power domain from +Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +The available power doamins are defined in dt-bindings/power/mt*-power.h. + +Example: + +mipi0a: clock-controller@11c10000 { + compatible = "mediatek,mt6765-mipi0a", "syscon"; + reg = <0 0x11c10000 0 0x1000>; + power-domains = <&scpsys MT6765_POWER_DOMAIN_CAM>; + #clock-cells = <1>; +}; diff --git a/Bindings/arm/mediatek/mediatek,mmsys.txt b/Bindings/arm/mediatek/mediatek,mmsys.txt index 301eefbe1618..d8c9108c3b4a 100644 --- a/Bindings/arm/mediatek/mediatek,mmsys.txt +++ b/Bindings/arm/mediatek/mediatek,mmsys.txt @@ -1,13 +1,15 @@ Mediatek mmsys controller ============================ -The Mediatek mmsys controller provides various clocks to the system. +The Mediatek mmsys system controller provides clock control, routing control, +and miscellaneous control in mmsys partition. Required Properties: - compatible: Should be one of: - "mediatek,mt2701-mmsys", "syscon" - "mediatek,mt2712-mmsys", "syscon" + - "mediatek,mt6765-mmsys", "syscon" - "mediatek,mt6779-mmsys", "syscon" - "mediatek,mt6797-mmsys", "syscon" - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" @@ -15,13 +17,13 @@ Required Properties: - "mediatek,mt8183-mmsys", "syscon" - #clock-cells: Must be 1 -The mmsys controller uses the common clk binding from +For the clock control, the mmsys controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. Example: -mmsys: clock-controller@14000000 { +mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; diff --git a/Bindings/arm/mediatek/mediatek,pericfg.txt b/Bindings/arm/mediatek/mediatek,pericfg.txt deleted file mode 100644 index ecf027a9003a..000000000000 --- a/Bindings/arm/mediatek/mediatek,pericfg.txt +++ /dev/null @@ -1,36 +0,0 @@ -Mediatek pericfg controller -=========================== - -The Mediatek pericfg controller provides various clocks and reset -outputs to the system. - -Required Properties: - -- compatible: Should be one of: - - "mediatek,mt2701-pericfg", "syscon" - - "mediatek,mt2712-pericfg", "syscon" - - "mediatek,mt7622-pericfg", "syscon" - - "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon" - - "mediatek,mt7629-pericfg", "syscon" - - "mediatek,mt8135-pericfg", "syscon" - - "mediatek,mt8173-pericfg", "syscon" - - "mediatek,mt8183-pericfg", "syscon" -- #clock-cells: Must be 1 -- #reset-cells: Must be 1 - -The pericfg controller uses the common clk binding from -Documentation/devicetree/bindings/clock/clock-bindings.txt -The available clocks are defined in dt-bindings/clock/mt*-clk.h. -Also it uses the common reset controller binding from -Documentation/devicetree/bindings/reset/reset.txt. -The available reset outputs are defined in -dt-bindings/reset/mt*-resets.h - -Example: - -pericfg: power-controller@10003000 { - compatible = "mediatek,mt8173-pericfg", "syscon"; - reg = <0 0x10003000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; diff --git a/Bindings/arm/mediatek/mediatek,pericfg.yaml b/Bindings/arm/mediatek/mediatek,pericfg.yaml new file mode 100644 index 000000000000..e271c4682ebc --- /dev/null +++ b/Bindings/arm/mediatek/mediatek,pericfg.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Peripheral Configuration Controller + +maintainers: + - Bartosz Golaszewski + +description: + The Mediatek pericfg controller provides various clocks and reset outputs + to the system. + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-pericfg + - mediatek,mt2712-pericfg + - mediatek,mt6765-pericfg + - mediatek,mt7622-pericfg + - mediatek,mt7629-pericfg + - mediatek,mt8135-pericfg + - mediatek,mt8173-pericfg + - mediatek,mt8183-pericfg + - mediatek,mt8516-pericfg + - const: syscon + - items: + # Special case for mt7623 for backward compatibility + - const: mediatek,mt7623-pericfg + - const: mediatek,mt2701-pericfg + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + +examples: + - | + pericfg@10003000 { + compatible = "mediatek,mt8173-pericfg", "syscon"; + reg = <0x10003000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + - | + pericfg@10003000 { + compatible = "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"; + reg = <0x10003000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Bindings/arm/mediatek/mediatek,topckgen.txt b/Bindings/arm/mediatek/mediatek,topckgen.txt index 0293d693ce0c..9b0394cbbdc9 100644 --- a/Bindings/arm/mediatek/mediatek,topckgen.txt +++ b/Bindings/arm/mediatek/mediatek,topckgen.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-topckgen" - "mediatek,mt2712-topckgen", "syscon" + - "mediatek,mt6765-topckgen", "syscon" - "mediatek,mt6779-topckgen", "syscon" - "mediatek,mt6797-topckgen" - "mediatek,mt7622-topckgen" diff --git a/Bindings/arm/mediatek/mediatek,vcodecsys.txt b/Bindings/arm/mediatek/mediatek,vcodecsys.txt new file mode 100644 index 000000000000..c877bcc1a5c5 --- /dev/null +++ b/Bindings/arm/mediatek/mediatek,vcodecsys.txt @@ -0,0 +1,27 @@ +Mediatek vcodecsys controller +============================ + +The Mediatek vcodecsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt6765-vcodecsys", "syscon" +- #clock-cells: Must be 1 + +The vcodecsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +The vcodecsys controller also uses the common power domain from +Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +The available power doamins are defined in dt-bindings/power/mt*-power.h. + +Example: + +venc_gcon: clock-controller@17000000 { + compatible = "mediatek,mt6765-vcodecsys", "syscon"; + reg = <0 0x17000000 0 0x10000>; + power-domains = <&scpsys MT6765_POWER_DOMAIN_VCODEC>; + #clock-cells = <1>; +}; diff --git a/Bindings/arm/nxp/lpc32xx.yaml b/Bindings/arm/nxp/lpc32xx.yaml index 07f39d3eee7e..f7f024910e71 100644 --- a/Bindings/arm/nxp/lpc32xx.yaml +++ b/Bindings/arm/nxp/lpc32xx.yaml @@ -17,9 +17,8 @@ properties: - nxp,lpc3230 - nxp,lpc3240 - items: - - enum: - - ea,ea3250 - - phytec,phy3250 - - const: nxp,lpc3250 - + - enum: + - ea,ea3250 + - phytec,phy3250 + - const: nxp,lpc3250 ... diff --git a/Bindings/arm/psci.yaml b/Bindings/arm/psci.yaml index 9247b58c26fc..8b77cf83a095 100644 --- a/Bindings/arm/psci.yaml +++ b/Bindings/arm/psci.yaml @@ -69,13 +69,11 @@ properties: method: description: The method of calling the PSCI firmware. - allOf: - - $ref: /schemas/types.yaml#/definitions/string-array - - enum: - # SMC #0, with the register assignments specified in this binding. - - smc - # HVC #0, with the register assignments specified in this binding. - - hvc + $ref: /schemas/types.yaml#/definitions/string-array + enum: + - smc + # HVC #0, with the register assignments specified in this binding. + - hvc cpu_suspend: $ref: /schemas/types.yaml#/definitions/uint32 @@ -107,8 +105,8 @@ properties: patternProperties: "^power-domain-": - allOf: - - $ref: "../power/power-domain.yaml#" + $ref: "../power/power-domain.yaml#" + type: object description: | ARM systems can have multiple cores, sometimes in an hierarchical diff --git a/Bindings/arm/qcom.yaml b/Bindings/arm/qcom.yaml index 64ddae3bd39f..6031aee0f5a8 100644 --- a/Bindings/arm/qcom.yaml +++ b/Bindings/arm/qcom.yaml @@ -37,6 +37,8 @@ description: | msm8994 msm8996 sc7180 + sdm630 + sdm660 sdm845 The 'board' element must be one of the following strings: @@ -153,6 +155,11 @@ properties: - qcom,sc7180-idp - const: qcom,sc7180 + - items: + - enum: + - xiaomi,lavender + - const: qcom,sdm660 + - items: - enum: - qcom,ipq6018-cp01-c1 diff --git a/Bindings/arm/realtek.yaml b/Bindings/arm/realtek.yaml index ab59de17152d..845f9c76d6f7 100644 --- a/Bindings/arm/realtek.yaml +++ b/Bindings/arm/realtek.yaml @@ -14,6 +14,13 @@ properties: const: '/' compatible: oneOf: + # RTD1195 SoC based boards + - items: + - enum: + - mele,x1000 # MeLE X1000 + - realtek,horseradish # Realtek Horseradish EVB + - const: realtek,rtd1195 + # RTD1293 SoC based boards - items: - enum: @@ -25,6 +32,7 @@ properties: - enum: - mele,v9 # MeLE V9 - probox2,ava # ProBox2 AVA + - xnano,x5 # Xnano X5 - zidoo,x9s # Zidoo X9S - const: realtek,rtd1295 @@ -33,4 +41,17 @@ properties: - enum: - synology,ds418 # Synology DiskStation DS418 - const: realtek,rtd1296 + + # RTD1395 SoC based boards + - items: + - enum: + - bananapi,bpi-m4 # Banana Pi BPI-M4 + - realtek,lion-skin # Realtek Lion Skin EVB + - const: realtek,rtd1395 + + # RTD1619 SoC based boards + - items: + - enum: + - realtek,mjolnir # Realtek Mjolnir EVB + - const: realtek,rtd1619 ... diff --git a/Bindings/arm/renesas,prr.yaml b/Bindings/arm/renesas,prr.yaml index dd087643a9f8..1f80767da38b 100644 --- a/Bindings/arm/renesas,prr.yaml +++ b/Bindings/arm/renesas,prr.yaml @@ -33,5 +33,5 @@ examples: - | prr: chipid@ff000044 { compatible = "renesas,prr"; - reg = <0 0xff000044 0 4>; + reg = <0xff000044 4>; }; diff --git a/Bindings/arm/renesas.yaml b/Bindings/arm/renesas.yaml index 611094d9186b..b7d2e921150a 100644 --- a/Bindings/arm/renesas.yaml +++ b/Bindings/arm/renesas.yaml @@ -54,6 +54,16 @@ properties: - description: RZ/G1H (R8A77420) items: + - enum: + # iWave Systems RZ/G1H Qseven System On Module (iW-RainboW-G21M-Qseven) + - iwave,g21m + - const: renesas,r8a7742 + + - items: + - enum: + # iWave Systems RZ/G1H Qseven Development Platform (iW-RainboW-G21D-Qseven) + - iwave,g21d + - const: iwave,g21m - const: renesas,r8a7742 - description: RZ/G1M (R8A77430) diff --git a/Bindings/arm/rockchip.yaml b/Bindings/arm/rockchip.yaml index 715586dea9bb..d4a4045092df 100644 --- a/Bindings/arm/rockchip.yaml +++ b/Bindings/arm/rockchip.yaml @@ -358,6 +358,11 @@ properties: - const: haoyu,marsboard-rk3066 - const: rockchip,rk3066a + - description: Hardkernel Odroid Go Advance + items: + - const: hardkernel,rk3326-odroid-go2 + - const: rockchip,rk3326 + - description: Hugsun X99 TV Box items: - const: hugsun,x99 diff --git a/Bindings/arm/samsung/exynos-chipid.yaml b/Bindings/arm/samsung/exynos-chipid.yaml index 0425d333b50d..f99c0c6df21b 100644 --- a/Bindings/arm/samsung/exynos-chipid.yaml +++ b/Bindings/arm/samsung/exynos-chipid.yaml @@ -22,9 +22,8 @@ properties: Adaptive Supply Voltage bin selection. This can be used to determine the ASV bin of an SoC if respective information is missing in the CHIPID registers or in the OTP memory. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 0, 1, 2, 3 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] required: - compatible diff --git a/Bindings/arm/samsung/samsung-boards.yaml b/Bindings/arm/samsung/samsung-boards.yaml index 63acd57c4799..eb92f9eefaba 100644 --- a/Bindings/arm/samsung/samsung-boards.yaml +++ b/Bindings/arm/samsung/samsung-boards.yaml @@ -52,6 +52,7 @@ properties: items: - enum: - insignal,origen # Insignal Origen + - samsung,i9100 # Samsung Galaxy S2 (GT-I9100) - samsung,smdkv310 # Samsung SMDKV310 eval - samsung,trats # Samsung Tizen Reference - samsung,universal_c210 # Samsung C210 diff --git a/Bindings/arm/socionext/uniphier.yaml b/Bindings/arm/socionext/uniphier.yaml index 65ad6d8a3c99..6caf1f9be390 100644 --- a/Bindings/arm/socionext/uniphier.yaml +++ b/Bindings/arm/socionext/uniphier.yaml @@ -17,45 +17,46 @@ properties: - description: LD4 SoC boards items: - enum: - - socionext,uniphier-ld4-ref + - socionext,uniphier-ld4-ref - const: socionext,uniphier-ld4 - description: Pro4 SoC boards items: - enum: - - socionext,uniphier-pro4-ace - - socionext,uniphier-pro4-ref - - socionext,uniphier-pro4-sanji + - socionext,uniphier-pro4-ace + - socionext,uniphier-pro4-ref + - socionext,uniphier-pro4-sanji - const: socionext,uniphier-pro4 - description: sLD8 SoC boards items: - enum: - - socionext,uniphier-sld8-ref + - socionext,uniphier-sld8-ref - const: socionext,uniphier-sld8 - description: PXs2 SoC boards items: - enum: - - socionext,uniphier-pxs2-gentil - - socionext,uniphier-pxs2-vodka + - socionext,uniphier-pxs2-gentil + - socionext,uniphier-pxs2-vodka - const: socionext,uniphier-pxs2 - description: LD6b SoC boards items: - enum: - - socionext,uniphier-ld6b-ref + - socionext,uniphier-ld6b-ref - const: socionext,uniphier-ld6b - description: LD11 SoC boards items: - enum: - - socionext,uniphier-ld11-global - - socionext,uniphier-ld11-ref + - socionext,uniphier-ld11-global + - socionext,uniphier-ld11-ref - const: socionext,uniphier-ld11 - description: LD20 SoC boards items: - enum: - - socionext,uniphier-ld20-global - - socionext,uniphier-ld20-ref + - socionext,uniphier-ld20-akebi96 + - socionext,uniphier-ld20-global + - socionext,uniphier-ld20-ref - const: socionext,uniphier-ld20 - description: PXs3 SoC boards items: - enum: - - socionext,uniphier-pxs3-ref + - socionext,uniphier-pxs3-ref - const: socionext,uniphier-pxs3 diff --git a/Bindings/arm/stm32/st,mlahb.yaml b/Bindings/arm/stm32/st,mlahb.yaml index 55f7938c4826..9f276bc9efa0 100644 --- a/Bindings/arm/stm32/st,mlahb.yaml +++ b/Bindings/arm/stm32/st,mlahb.yaml @@ -20,7 +20,7 @@ description: | [2]: https://wiki.st.com/stm32mpu/wiki/STM32MP15_RAM_mapping allOf: - - $ref: /schemas/simple-bus.yaml# + - $ref: /schemas/simple-bus.yaml# properties: compatible: diff --git a/Bindings/arm/stm32/st,stm32-syscon.yaml b/Bindings/arm/stm32/st,stm32-syscon.yaml index baff80197d5a..cf5db5e273f3 100644 --- a/Bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Bindings/arm/stm32/st,stm32-syscon.yaml @@ -14,9 +14,9 @@ properties: compatible: oneOf: - items: - - enum: - - st,stm32mp157-syscfg - - const: syscon + - enum: + - st,stm32mp157-syscfg + - const: syscon reg: maxItems: 1 diff --git a/Bindings/arm/stm32/stm32.yaml b/Bindings/arm/stm32/stm32.yaml index 1fcf306bd2d1..790e6dd48e34 100644 --- a/Bindings/arm/stm32/stm32.yaml +++ b/Bindings/arm/stm32/stm32.yaml @@ -38,6 +38,9 @@ properties: - items: - enum: - arrow,stm32mp157a-avenger96 # Avenger96 + - lxa,stm32mp157c-mc1 + - shiratech,stm32mp157a-iot-box # IoT Box + - shiratech,stm32mp157a-stinger96 # Stinger96 - st,stm32mp157c-ed1 - st,stm32mp157a-dk1 - st,stm32mp157c-dk2 diff --git a/Bindings/arm/sunxi.yaml b/Bindings/arm/sunxi.yaml index abf2d97fb7ae..87817ff0cd35 100644 --- a/Bindings/arm/sunxi.yaml +++ b/Bindings/arm/sunxi.yaml @@ -561,6 +561,11 @@ properties: - const: olimex,a20-olinuxino-lime - const: allwinner,sun7i-a20 + - description: Olimex A20-OlinuXino LIME (with eMMC) + items: + - const: olimex,a20-olinuxino-lime-emmc + - const: allwinner,sun7i-a20 + - description: Olimex A20-OlinuXino LIME2 items: - const: olimex,a20-olinuxino-lime2 diff --git a/Bindings/arm/syna.txt b/Bindings/arm/syna.txt index 2face46a5f64..d8b48f2edf1b 100644 --- a/Bindings/arm/syna.txt +++ b/Bindings/arm/syna.txt @@ -13,7 +13,7 @@ considered "unstable". Any Marvell Berlin device tree binding may change at any time. Be sure to use a device tree binary and a kernel image generated from the same source tree. -Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a +Please refer to Documentation/devicetree/bindings/ABI.rst for a definition of a stable binding/ABI. --------------------------------------------------------------- diff --git a/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml index f17bb353f65e..b71a20af5f70 100644 --- a/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml +++ b/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml @@ -85,9 +85,8 @@ properties: CPU power good signal from external PMIC to PMC is enabled. nvidia,suspend-mode: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [0, 1, 2] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] description: The suspend mode that the platform should use. Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh @@ -323,7 +322,7 @@ examples: tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra210-pmc"; - reg = <0x0 0x7000e400 0x0 0x400>; + reg = <0x7000e400 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; #clock-cells = <1>; diff --git a/Bindings/ata/faraday,ftide010.yaml b/Bindings/ata/faraday,ftide010.yaml index bfc6357476fd..6451928dd2ce 100644 --- a/Bindings/ata/faraday,ftide010.yaml +++ b/Bindings/ata/faraday,ftide010.yaml @@ -26,8 +26,8 @@ properties: oneOf: - const: faraday,ftide010 - items: - - const: cortina,gemini-pata - - const: faraday,ftide010 + - const: cortina,gemini-pata + - const: faraday,ftide010 reg: maxItems: 1 diff --git a/Bindings/ata/renesas,rcar-sata.yaml b/Bindings/ata/renesas,rcar-sata.yaml index 7b69831060d8..d06096a7ba4b 100644 --- a/Bindings/ata/renesas,rcar-sata.yaml +++ b/Bindings/ata/renesas,rcar-sata.yaml @@ -17,6 +17,7 @@ properties: - renesas,sata-r8a7779 # R-Car H1 - items: - enum: + - renesas,sata-r8a7742 # RZ/G1H - renesas,sata-r8a7790-es1 # R-Car H2 ES1 - renesas,sata-r8a7790 # R-Car H2 other than ES1 - renesas,sata-r8a7791 # R-Car M2-W diff --git a/Bindings/ata/sata_highbank.txt b/Bindings/ata/sata_highbank.txt deleted file mode 100644 index aa83407cb7a4..000000000000 --- a/Bindings/ata/sata_highbank.txt +++ /dev/null @@ -1,44 +0,0 @@ -* Calxeda AHCI SATA Controller - -SATA nodes are defined to describe on-chip Serial ATA controllers. -The Calxeda SATA controller mostly conforms to the AHCI interface -with some special extensions to add functionality. -Each SATA controller should have its own node. - -Required properties: -- compatible : compatible list, contains "calxeda,hb-ahci" -- interrupts : -- reg : - -Optional properties: -- dma-coherent : Present if dma operations are coherent -- calxeda,port-phys : phandle-combophy and lane assignment, which maps each - SATA port to a combophy and a lane within that - combophy -- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off, - which indicates that the driver supports SGPIO - indicator lights using the indicated GPIOs -- calxeda,led-order : a u32 array that map port numbers to offsets within the - SGPIO bitstream. -- calxeda,tx-atten : a u32 array that contains TX attenuation override - codes, one per port. The upper 3 bytes are always - 0 and thus ignored. -- calxeda,pre-clocks : a u32 that indicates the number of additional clock - cycles to transmit before sending an SGPIO pattern -- calxeda,post-clocks: a u32 that indicates the number of additional clock - cycles to transmit after sending an SGPIO pattern - -Example: - sata@ffe08000 { - compatible = "calxeda,hb-ahci"; - reg = <0xffe08000 0x1000>; - interrupts = <115>; - dma-coherent; - calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1 - &combophy0 2 &combophy0 3>; - calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>; - calxeda,led-order = <4 0 1 2 3>; - calxeda,tx-atten = <0xff 22 0xff 0xff 23>; - calxeda,pre-clocks = <10>; - calxeda,post-clocks = <0>; - }; diff --git a/Bindings/ata/sata_highbank.yaml b/Bindings/ata/sata_highbank.yaml new file mode 100644 index 000000000000..5e2a2394e600 --- /dev/null +++ b/Bindings/ata/sata_highbank.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/sata_highbank.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda AHCI SATA Controller + +description: | + The Calxeda SATA controller mostly conforms to the AHCI interface + with some special extensions to add functionality, to map GPIOs for + activity LEDs and for mapping the ComboPHYs. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: calxeda,hb-ahci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dma-coherent: true + + calxeda,pre-clocks: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Indicates the number of additional clock cycles to transmit before + sending an SGPIO pattern. + + calxeda,post-clocks: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Indicates the number of additional clock cycles to transmit after + sending an SGPIO pattern. + + calxeda,led-order: + description: Maps port numbers to offsets within the SGPIO bitstream. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + + calxeda,port-phys: + description: | + phandle-combophy and lane assignment, which maps each SATA port to a + combophy and a lane within that combophy + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 8 + + calxeda,tx-atten: + description: | + Contains TX attenuation override codes, one per port. + The upper 24 bits of each entry are always 0 and thus ignored. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + + calxeda,sgpio-gpio: + description: | + phandle-gpio bank, bit offset, and default on or off, which indicates + that the driver supports SGPIO indicator lights using the indicated + GPIOs. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + sata@ffe08000 { + compatible = "calxeda,hb-ahci"; + reg = <0xffe08000 0x1000>; + interrupts = <115>; + dma-coherent; + calxeda,port-phys = <&combophy5 0>, <&combophy0 0>, <&combophy0 1>, + <&combophy0 2>, <&combophy0 3>; + calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>, <&gpioh 7 1>; + calxeda,led-order = <4 0 1 2 3>; + calxeda,tx-atten = <0xff 22 0xff 0xff 23>; + calxeda,pre-clocks = <10>; + calxeda,post-clocks = <0>; + }; + +... diff --git a/Bindings/auxdisplay/hit,hd44780.txt b/Bindings/auxdisplay/hit,hd44780.txt deleted file mode 100644 index 2aa24b889923..000000000000 --- a/Bindings/auxdisplay/hit,hd44780.txt +++ /dev/null @@ -1,45 +0,0 @@ -DT bindings for the Hitachi HD44780 Character LCD Controller - -The Hitachi HD44780 Character LCD Controller is commonly used on character LCDs -that can display one or more lines of text. It exposes an M6800 bus interface, -which can be used in either 4-bit or 8-bit mode. - -Required properties: - - compatible: Must contain "hit,hd44780", - - data-gpios: Must contain an array of either 4 or 8 GPIO specifiers, - referring to the GPIO pins connected to the data signal lines DB0-DB7 - (8-bit mode) or DB4-DB7 (4-bit mode) of the LCD Controller's bus interface, - - enable-gpios: Must contain a GPIO specifier, referring to the GPIO pin - connected to the "E" (Enable) signal line of the LCD Controller's bus - interface, - - rs-gpios: Must contain a GPIO specifier, referring to the GPIO pin - connected to the "RS" (Register Select) signal line of the LCD Controller's - bus interface, - - display-height-chars: Height of the display, in character cells, - - display-width-chars: Width of the display, in character cells. - -Optional properties: - - rw-gpios: Must contain a GPIO specifier, referring to the GPIO pin - connected to the "RW" (Read/Write) signal line of the LCD Controller's bus - interface, - - backlight-gpios: Must contain a GPIO specifier, referring to the GPIO pin - used for enabling the LCD's backlight, - - internal-buffer-width: Internal buffer width (default is 40 for displays - with 1 or 2 lines, and display-width-chars for displays with more than 2 - lines). - -Example: - - auxdisplay { - compatible = "hit,hd44780"; - - data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>, - <&hc595 1 GPIO_ACTIVE_HIGH>, - <&hc595 2 GPIO_ACTIVE_HIGH>, - <&hc595 3 GPIO_ACTIVE_HIGH>; - enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; - rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; - - display-height-chars = <2>; - display-width-chars = <16>; - }; diff --git a/Bindings/auxdisplay/hit,hd44780.yaml b/Bindings/auxdisplay/hit,hd44780.yaml new file mode 100644 index 000000000000..9222b06e93a0 --- /dev/null +++ b/Bindings/auxdisplay/hit,hd44780.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/auxdisplay/hit,hd44780.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hitachi HD44780 Character LCD Controller + +maintainers: + - Geert Uytterhoeven + +description: + The Hitachi HD44780 Character LCD Controller is commonly used on character + LCDs that can display one or more lines of text. It exposes an M6800 bus + interface, which can be used in either 4-bit or 8-bit mode. + +properties: + compatible: + const: hit,hd44780 + + data-gpios: + description: + GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or + DB4-DB7 (4-bit mode) of the LCD Controller's bus interface. + oneOf: + - maxItems: 4 + - maxItems: 8 + + enable-gpios: + description: + GPIO pin connected to the "E" (Enable) signal line of the LCD + Controller's bus interface. + maxItems: 1 + + rs-gpios: + description: + GPIO pin connected to the "RS" (Register Select) signal line of the LCD + Controller's bus interface. + maxItems: 1 + + rw-gpios: + description: + GPIO pin connected to the "RW" (Read/Write) signal line of the LCD + Controller's bus interface. + maxItems: 1 + + backlight-gpios: + description: GPIO pin used for enabling the LCD's backlight. + maxItems: 1 + + display-height-chars: + description: Height of the display, in character cells, + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 4 + + display-width-chars: + description: Width of the display, in character cells. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 64 + + internal-buffer-width: + description: + Internal buffer width (default is 40 for displays with 1 or 2 lines, and + display-width-chars for displays with more than 2 lines). + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 64 + +required: + - compatible + - data-gpios + - enable-gpios + - rs-gpios + - display-height-chars + - display-width-chars + +additionalProperties: false + +examples: + - | + #include + auxdisplay { + compatible = "hit,hd44780"; + + data-gpios = <&hc595 0 GPIO_ACTIVE_HIGH>, + <&hc595 1 GPIO_ACTIVE_HIGH>, + <&hc595 2 GPIO_ACTIVE_HIGH>, + <&hc595 3 GPIO_ACTIVE_HIGH>; + enable-gpios = <&hc595 4 GPIO_ACTIVE_HIGH>; + rs-gpios = <&hc595 5 GPIO_ACTIVE_HIGH>; + + display-height-chars = <2>; + display-width-chars = <16>; + }; diff --git a/Bindings/bus/allwinner,sun50i-a64-de2.yaml b/Bindings/bus/allwinner,sun50i-a64-de2.yaml index f0b3d30fbb76..0503651cd214 100644 --- a/Bindings/bus/allwinner,sun50i-a64-de2.yaml +++ b/Bindings/bus/allwinner,sun50i-a64-de2.yaml @@ -31,12 +31,11 @@ properties: maxItems: 1 allwinner,sram: - allOf: - - $ref: /schemas/types.yaml#definitions/phandle-array - - maxItems: 1 description: The SRAM that needs to be claimed to access the display engine bus. + $ref: /schemas/types.yaml#definitions/phandle-array + maxItems: 1 ranges: true diff --git a/Bindings/bus/allwinner,sun8i-a23-rsb.yaml b/Bindings/bus/allwinner,sun8i-a23-rsb.yaml index 80973619342d..32d33b983d66 100644 --- a/Bindings/bus/allwinner,sun8i-a23-rsb.yaml +++ b/Bindings/bus/allwinner,sun8i-a23-rsb.yaml @@ -21,8 +21,8 @@ properties: oneOf: - const: allwinner,sun8i-a23-rsb - items: - - const: allwinner,sun8i-a83t-rsb - - const: allwinner,sun8i-a23-rsb + - const: allwinner,sun8i-a83t-rsb + - const: allwinner,sun8i-a23-rsb reg: maxItems: 1 diff --git a/Bindings/bus/arm,integrator-ap-lm.yaml b/Bindings/bus/arm,integrator-ap-lm.yaml new file mode 100644 index 000000000000..47227427c1c0 --- /dev/null +++ b/Bindings/bus/arm,integrator-ap-lm.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/arm,integrator-ap-lm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Integrator/AP Logic Module extension bus + +maintainers: + - Linus Walleij + +description: The Integrator/AP is a prototyping platform and as such has a + site for stacking up to four logic modules (LM) designed specifically for + use with this platform. A special system controller register can be read to + determine if a logic module is connected at index 0, 1, 2 or 3. The logic + module connector is described in this binding. The logic modules per se + then have their own specific per-module bindings and they will be described + as subnodes under this logic module extension bus. + +properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + compatible: + items: + - const: arm,integrator-ap-lm + + ranges: true + dma-ranges: true + +patternProperties: + "^bus(@[0-9a-f]*)?$": + description: Nodes on the Logic Module bus represent logic modules + and are named with bus. The first module is at 0xc0000000, the second + at 0xd0000000 and so on until the top of the memory of the system at + 0xffffffff. All information about the memory used by the module is + in ranges and dma-ranges. + type: object + + required: + - compatible + +required: + - compatible + +examples: + - | + bus@c0000000 { + compatible = "arm,integrator-ap-lm"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc0000000 0xc0000000 0x40000000>; + dma-ranges; + + bus@c0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xc0000000 0x10000000>; + /* The Logic Modules sees the Core Module 0 RAM @80000000 */ + dma-ranges = <0x00000000 0x80000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + + serial@100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00100000 0x1000>; + interrupts-extended = <&impd1_vic 1>; + }; + + impd1_vic: interrupt-controller@3000000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x03000000 0x1000>; + valid-mask = <0x00000bff>; + interrupts-extended = <&pic 9>; + }; + }; + }; + +additionalProperties: false diff --git a/Bindings/bus/baikal,bt1-apb.yaml b/Bindings/bus/baikal,bt1-apb.yaml new file mode 100644 index 000000000000..68b0131a31d0 --- /dev/null +++ b/Bindings/bus/baikal,bt1-apb.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 APB-bus + +maintainers: + - Serge Semin + +description: | + Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect + which routes them to the AXI-APB bridge. This interface is a single master + multiple slaves bus in turn serializing IO accesses and routing them to the + addressed APB slave devices. In case of any APB protocol collisions, slave + device not responding on timeout an IRQ is raised with an erroneous address + reported to the APB terminator (APB Errors Handler Block). + +allOf: + - $ref: /schemas/simple-bus.yaml# + +properties: + compatible: + contains: + const: baikal,bt1-apb + + reg: + items: + - description: APB EHB MMIO registers + - description: APB MMIO region with no any device mapped + + reg-names: + items: + - const: ehb + - const: nodev + + interrupts: + maxItems: 1 + + clocks: + items: + - description: APB reference clock + + clock-names: + items: + - const: pclk + + resets: + items: + - description: APB domain reset line + + reset-names: + items: + - const: prst + +unevaluatedProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + +examples: + - | + #include + + bus@1f059000 { + compatible = "baikal,bt1-apb", "simple-bus"; + reg = <0x1f059000 0x1000>, + <0x1d000000 0x2040000>; + reg-names = "ehb", "nodev"; + #address-cells = <1>; + #size-cells = <1>; + + ranges; + + interrupts = ; + + clocks = <&ccu_sys 1>; + clock-names = "pclk"; + + resets = <&ccu_sys 1>; + reset-names = "prst"; + }; +... diff --git a/Bindings/bus/baikal,bt1-axi.yaml b/Bindings/bus/baikal,bt1-axi.yaml new file mode 100644 index 000000000000..29e1aaea132b --- /dev/null +++ b/Bindings/bus/baikal,bt1-axi.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 AXI-bus + +maintainers: + - Serge Semin + +description: | + AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all + high-speed peripheral IP-cores with RAM controller and with MIPS P5600 + cores. Traffic arbitration is done by means of DW AXI Interconnect (so + called AXI Main Interconnect) routing IO requests from one block to + another: from CPU to SoC peripherals and between some SoC peripherals + (mostly between peripheral devices and RAM, but also between DMA and + some peripherals). In case of any protocol error, device not responding + an IRQ is raised and a faulty situation is reported to the AXI EHB + (Errors Handler Block) embedded on top of the DW AXI Interconnect and + accessible by means of the Baikal-T1 System Controller. + +allOf: + - $ref: /schemas/simple-bus.yaml# + +properties: + compatible: + contains: + const: baikal,bt1-axi + + reg: + minItems: 1 + items: + - description: Synopsys DesignWare AXI Interconnect QoS registers + - description: AXI EHB MMIO system controller registers + + reg-names: + minItems: 1 + items: + - const: qos + - const: ehb + + '#interconnect-cells': + const: 1 + + syscon: + $ref: /schemas/types.yaml#definitions/phandle + description: Phandle to the Baikal-T1 System Controller DT node + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Main Interconnect uplink reference clock + + clock-names: + items: + - const: aclk + + resets: + items: + - description: Main Interconnect reset line + + reset-names: + items: + - const: arst + +unevaluatedProperties: false + +required: + - compatible + - reg + - reg-names + - syscon + - interrupts + - clocks + - clock-names + +examples: + - | + #include + + bus@1f05a000 { + compatible = "baikal,bt1-axi", "simple-bus"; + reg = <0x1f05a000 0x1000>, + <0x1f04d110 0x8>; + reg-names = "qos", "ehb"; + #address-cells = <1>; + #size-cells = <1>; + #interconnect-cells = <1>; + + syscon = <&syscon>; + + ranges; + + interrupts = ; + + clocks = <&ccu_axi 0>; + clock-names = "aclk"; + + resets = <&ccu_axi 0>; + reset-names = "arst"; + }; +... diff --git a/Bindings/bus/socionext,uniphier-system-bus.yaml b/Bindings/bus/socionext,uniphier-system-bus.yaml index c4c9119e4a20..a0c6c5d2b70f 100644 --- a/Bindings/bus/socionext,uniphier-system-bus.yaml +++ b/Bindings/bus/socionext,uniphier-system-bus.yaml @@ -80,14 +80,14 @@ examples: ranges = <1 0x00000000 0x42000000 0x02000000>, <5 0x00000000 0x46000000 0x01000000>; - ethernet@1,01f00000 { + ethernet@1,1f00000 { compatible = "smsc,lan9115"; reg = <1 0x01f00000 0x1000>; interrupts = <0 48 4>; phy-mode = "mii"; }; - uart@5,00200000 { + serial@5,200000 { compatible = "ns16550a"; reg = <5 0x00200000 0x20>; interrupts = <0 49 4>; diff --git a/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml b/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml index ed1b2126a81b..9a37a357cb4e 100644 --- a/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml +++ b/Bindings/clock/allwinner,sun4i-a10-gates-clk.yaml @@ -52,12 +52,12 @@ properties: - const: allwinner,sun4i-a10-dram-gates-clk - items: - - const: allwinner,sun5i-a13-dram-gates-clk - - const: allwinner,sun4i-a10-gates-clk + - const: allwinner,sun5i-a13-dram-gates-clk + - const: allwinner,sun4i-a10-gates-clk - items: - - const: allwinner,sun8i-h3-apb0-gates-clk - - const: allwinner,sun4i-a10-gates-clk + - const: allwinner,sun8i-h3-apb0-gates-clk + - const: allwinner,sun4i-a10-gates-clk reg: maxItems: 1 diff --git a/Bindings/clock/baikal,bt1-ccu-div.yaml b/Bindings/clock/baikal,bt1-ccu-div.yaml new file mode 100644 index 000000000000..2821425ee445 --- /dev/null +++ b/Bindings/clock/baikal,bt1-ccu-div.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 Clock Control Unit Dividers + +maintainers: + - Serge Semin + +description: | + Clocks Control Unit is the core of Baikal-T1 SoC System Controller + responsible for the chip subsystems clocking and resetting. The CCU is + connected with an external fixed rate oscillator, which signal is transformed + into clocks of various frequencies and then propagated to either individual + IP-blocks or to groups of blocks (clock domains). The transformation is done + by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The + later ones are described in this binding. Each clock domain can be also + individually reset by using the domain clocks divider configuration + registers. Baikal-T1 CCU is logically divided into the next components: + 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but + in general can provide any frequency supported by the CCU PLLs). + 2) PLLs clocks generators (PLLs). + 3) AXI-bus clock dividers (AXI) - described in this binding file. + 4) System devices reference clock dividers (SYS) - described in this binding + file. + which are connected with each other as shown on the next figure: + + +---------------+ + | Baikal-T1 CCU | + | +----+------|- MIPS P5600 cores + | +-|PLLs|------|- DDR controller + | | +----+ | + +----+ | | | | | + |XTAL|--|-+ | | +---+-| + +----+ | | | +-|AXI|-|- AXI-bus + | | | +---+-| + | | | | + | | +----+---+-|- APB-bus + | +-------|SYS|-|- Low-speed Devices + | +---+-|- High-speed Devices + +---------------+ + + Each sub-block is represented as a separate DT node and has an individual + driver to be bound with. + + In order to create signals of wide range frequencies the external oscillator + output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are + then passed over CCU dividers to create signals required for the target clock + domain (like AXI-bus or System Device consumers). The dividers have the + following structure: + + +--------------+ + CLKIN --|->+----+ 1|\ | + SETCLK--|--|/DIV|->| | | + CLKDIV--|--| | | |-|->CLKLOUT + LOCK----|--+----+ | | | + | |/ | + | | | + EN------|-----------+ | + RST-----|--------------|->RSTOUT + +--------------+ + + where CLKIN is the reference clock coming either from CCU PLLs or from an + external clock oscillator, SETCLK - a command to update the output clock in + accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of + the output clock stabilization, EN - enable/disable the divider block, + RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core + peculiarities the dividers may lack of some functionality depicted on the + figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding + clock provider just doesn't expose either switching functions, or the rate + configuration, or both of them. + + The clock dividers, which output clock is then consumed by the SoC individual + devices, are united into a single clocks provider called System Devices CCU. + Similarly the dividers with output clocks utilized as AXI-bus reference clocks + are called AXI-bus CCU. Both of them use the common clock bindings with no + custom properties. The list of exported clocks and reset signals can be found + in the files: 'include/dt-bindings/clock/bt1-ccu.h' and + 'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU + are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed + to be a children of later one. + +if: + properties: + compatible: + contains: + const: baikal,bt1-ccu-axi + +then: + properties: + clocks: + items: + - description: CCU SATA PLL output clock + - description: CCU PCIe PLL output clock + - description: CCU Ethernet PLL output clock + + clock-names: + items: + - const: sata_clk + - const: pcie_clk + - const: eth_clk + +else: + properties: + clocks: + items: + - description: External reference clock + - description: CCU SATA PLL output clock + - description: CCU PCIe PLL output clock + - description: CCU Ethernet PLL output clock + + clock-names: + items: + - const: ref_clk + - const: sata_clk + - const: pcie_clk + - const: eth_clk + +properties: + compatible: + enum: + - baikal,bt1-ccu-axi + - baikal,bt1-ccu-sys + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +unevaluatedProperties: false + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + +examples: + # AXI-bus Clock Control Unit node: + - | + #include + + clock-controller@1f04d030 { + compatible = "baikal,bt1-ccu-axi"; + reg = <0x1f04d030 0x030>; + #clock-cells = <1>; + #reset-cells = <1>; + + clocks = <&ccu_pll CCU_SATA_PLL>, + <&ccu_pll CCU_PCIE_PLL>, + <&ccu_pll CCU_ETH_PLL>; + clock-names = "sata_clk", "pcie_clk", "eth_clk"; + }; + # System Devices Clock Control Unit node: + - | + #include + + clock-controller@1f04d060 { + compatible = "baikal,bt1-ccu-sys"; + reg = <0x1f04d060 0x0a0>; + #clock-cells = <1>; + #reset-cells = <1>; + + clocks = <&clk25m>, + <&ccu_pll CCU_SATA_PLL>, + <&ccu_pll CCU_PCIE_PLL>, + <&ccu_pll CCU_ETH_PLL>; + clock-names = "ref_clk", "sata_clk", "pcie_clk", + "eth_clk"; + }; + # Required Clock Control Unit PLL node: + - | + ccu_pll: clock-controller@1f04d000 { + compatible = "baikal,bt1-ccu-pll"; + reg = <0x1f04d000 0x028>; + #clock-cells = <1>; + + clocks = <&clk25m>; + clock-names = "ref_clk"; + }; +... diff --git a/Bindings/clock/baikal,bt1-ccu-pll.yaml b/Bindings/clock/baikal,bt1-ccu-pll.yaml new file mode 100644 index 000000000000..97131bfa6f87 --- /dev/null +++ b/Bindings/clock/baikal,bt1-ccu-pll.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 Clock Control Unit PLL + +maintainers: + - Serge Semin + +description: | + Clocks Control Unit is the core of Baikal-T1 SoC System Controller + responsible for the chip subsystems clocking and resetting. The CCU is + connected with an external fixed rate oscillator, which signal is transformed + into clocks of various frequencies and then propagated to either individual + IP-blocks or to groups of blocks (clock domains). The transformation is done + by means of PLLs and gateable/non-gateable dividers embedded into the CCU. + It's logically divided into the next components: + 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but + in general can provide any frequency supported by the CCU PLLs). + 2) PLLs clocks generators (PLLs) - described in this binding file. + 3) AXI-bus clock dividers (AXI). + 4) System devices reference clock dividers (SYS). + which are connected with each other as shown on the next figure: + + +---------------+ + | Baikal-T1 CCU | + | +----+------|- MIPS P5600 cores + | +-|PLLs|------|- DDR controller + | | +----+ | + +----+ | | | | | + |XTAL|--|-+ | | +---+-| + +----+ | | | +-|AXI|-|- AXI-bus + | | | +---+-| + | | | | + | | +----+---+-|- APB-bus + | +-------|SYS|-|- Low-speed Devices + | +---+-|- High-speed Devices + +---------------+ + + Each CCU sub-block is represented as a separate dts-node and has an + individual driver to be bound with. + + In order to create signals of wide range frequencies the external oscillator + output is primarily connected to a set of CCU PLLs. There are five PLLs + to create a clock for the MIPS P5600 cores, the embedded DDR controller, + SATA, Ethernet and PCIe domains. The last three domains though named by the + biggest system interfaces in fact include nearly all of the rest SoC + peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core + with an interface wrapper (so called safe PLL' clocks switcher) to simplify + the PLL configuration procedure. The PLLs work as depicted on the next + diagram: + + +--------------------------+ + | | + +-->+---+ +---+ +---+ | +---+ 0|\ + CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| | + +---+ +->+---+ +---+ /->+---+ | |--->CLKOUT + CLKOD---------C----------------+ 1| | + +--------C--------------------------->|/ + | | ^ + Rclk-+->+---+ | | + CLKR--->|/NR|-+ | + +---+ | + BYPASS--------------------------------------+ + BWADJ---> + + where Rclk is the reference clock coming from XTAL, NR - reference clock + divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT - + output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment + the binding supports the PLL dividers configuration in accordance with a + requested rate, while bypassing and bandwidth adjustment settings can be + added in future if it gets to be necessary. + + The PLLs CLKOUT is then either directly connected with the corresponding + clocks consumer (like P5600 cores or DDR controller) or passed over a CCU + divider to create a signal required for the clock domain. + + The CCU PLL dts-node uses the common clock bindings with no custom + parameters. The list of exported clocks can be found in + 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the + Baikal-T1 SoC System Controller its DT node is supposed to be a child of + later one. + +properties: + compatible: + const: baikal,bt1-ccu-pll + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + clocks: + description: External reference clock + maxItems: 1 + + clock-names: + const: ref_clk + +unevaluatedProperties: false + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + +examples: + # Clock Control Unit PLL node: + - | + clock-controller@1f04d000 { + compatible = "baikal,bt1-ccu-pll"; + reg = <0x1f04d000 0x028>; + #clock-cells = <1>; + + clocks = <&clk25m>; + clock-names = "ref_clk"; + }; + # Required external oscillator: + - | + clk25m: clock-oscillator-25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "clk25m"; + }; +... diff --git a/Bindings/clock/bitmain,bm1880-clk.yaml b/Bindings/clock/bitmain,bm1880-clk.yaml index 8559fe8f7efd..228c9313df53 100644 --- a/Bindings/clock/bitmain,bm1880-clk.yaml +++ b/Bindings/clock/bitmain,bm1880-clk.yaml @@ -65,7 +65,7 @@ examples: - | uart0: serial@58018000 { compatible = "snps,dw-apb-uart"; - reg = <0x0 0x58018000 0x0 0x2000>; + reg = <0x58018000 0x2000>; clocks = <&clk 45>, <&clk 46>; clock-names = "baudclk", "apb_pclk"; interrupts = <0 9 4>; diff --git a/Bindings/clock/calxeda.txt b/Bindings/clock/calxeda.txt deleted file mode 100644 index 0a6ac1bdcda1..000000000000 --- a/Bindings/clock/calxeda.txt +++ /dev/null @@ -1,17 +0,0 @@ -Device Tree Clock bindings for Calxeda highbank platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be one of the following: - "calxeda,hb-pll-clock" - for a PLL clock - "calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the - A9 clock. - "calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock. - "calxeda,hb-emmc-clock" - Divided clock for MMC/SD controller. -- reg : shall be the control register offset from SYSREGs base for the clock. -- clocks : shall be the input parent clock phandle for the clock. This is - either an oscillator or a pll output. -- #clock-cells : from common clock binding; shall be set to 0. diff --git a/Bindings/clock/calxeda.yaml b/Bindings/clock/calxeda.yaml new file mode 100644 index 000000000000..a34cbf3c9aaf --- /dev/null +++ b/Bindings/clock/calxeda.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/calxeda.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device Tree Clock bindings for Calxeda highbank platform + +description: | + This binding covers the Calxeda SoC internal peripheral and bus clocks + as used by peripherals. The clocks live inside the "system register" + region of the SoC, so are typically presented as children of an + "hb-sregs" node. + +maintainers: + - Andre Przywara + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - calxeda,hb-pll-clock + - calxeda,hb-a9periph-clock + - calxeda,hb-a9bus-clock + - calxeda,hb-emmc-clock + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - "#clock-cells" + - compatible + - clocks + - reg + +additionalProperties: false + +examples: + - | + sregs@3fffc000 { + compatible = "calxeda,hb-sregs"; + reg = <0x3fffc000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333000>; + }; + + ddrpll: ddrpll@108 { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x108>; + }; + + a9pll: a9pll@100 { + #clock-cells = <0>; + compatible = "calxeda,hb-pll-clock"; + clocks = <&osc>; + reg = <0x100>; + }; + + a9periphclk: a9periphclk@104 { + #clock-cells = <0>; + compatible = "calxeda,hb-a9periph-clock"; + clocks = <&a9pll>; + reg = <0x104>; + }; + }; + }; + +... diff --git a/Bindings/clock/cirrus,lochnagar.txt b/Bindings/clock/cirrus,lochnagar.txt deleted file mode 100644 index 52a064c789ee..000000000000 --- a/Bindings/clock/cirrus,lochnagar.txt +++ /dev/null @@ -1,94 +0,0 @@ -Cirrus Logic Lochnagar Audio Development Board - -Lochnagar is an evaluation and development board for Cirrus Logic -Smart CODEC and Amp devices. It allows the connection of most Cirrus -Logic devices on mini-cards, as well as allowing connection of -various application processor systems to provide a full evaluation -platform. Audio system topology, clocking and power can all be -controlled through the Lochnagar, allowing the device under test -to be used in a variety of possible use cases. - -This binding document describes the binding for the clock portion of -the driver. - -Also see these documents for generic binding information: - [1] Clock : ../clock/clock-bindings.txt - -And these for relevant defines: - [2] include/dt-bindings/clock/lochnagar.h - -This binding must be part of the Lochnagar MFD binding: - [3] ../mfd/cirrus,lochnagar.txt - -Required properties: - - - compatible : One of the following strings: - "cirrus,lochnagar1-clk" - "cirrus,lochnagar2-clk" - - - #clock-cells : Must be 1. The first cell indicates the clock - number, see [2] for available clocks and [1]. - -Optional properties: - - - clocks : Must contain an entry for each clock in clock-names. - - clock-names : May contain entries for each of the following - clocks: - - ln-cdc-clkout : Output clock from CODEC card. - - ln-dsp-clkout : Output clock from DSP card. - - ln-gf-mclk1,ln-gf-mclk2,ln-gf-mclk3,ln-gf-mclk4 : Optional - input audio clocks from host system. - - ln-psia1-mclk, ln-psia2-mclk : Optional input audio clocks from - external connector. - - ln-spdif-mclk : Optional input audio clock from SPDIF. - - ln-spdif-clkout : Optional input audio clock from SPDIF. - - ln-adat-mclk : Optional input audio clock from ADAT. - - ln-pmic-32k : On board fixed clock. - - ln-clk-12m : On board fixed clock. - - ln-clk-11m : On board fixed clock. - - ln-clk-24m : On board fixed clock. - - ln-clk-22m : On board fixed clock. - - ln-clk-8m : On board fixed clock. - - ln-usb-clk-24m : On board fixed clock. - - ln-usb-clk-12m : On board fixed clock. - - - assigned-clocks : A list of Lochnagar clocks to be reparented, see - [2] for available clocks. - - assigned-clock-parents : Parents to be assigned to the clocks - listed in "assigned-clocks". - -Optional nodes: - - - fixed-clock nodes may be registered for the following on board clocks: - - ln-pmic-32k : 32768 Hz - - ln-clk-12m : 12288000 Hz - - ln-clk-11m : 11298600 Hz - - ln-clk-24m : 24576000 Hz - - ln-clk-22m : 22579200 Hz - - ln-clk-8m : 8192000 Hz - - ln-usb-clk-24m : 24576000 Hz - - ln-usb-clk-12m : 12288000 Hz - -Example: - -lochnagar { - lochnagar-clk { - compatible = "cirrus,lochnagar2-clk"; - - #clock-cells = <1>; - - clocks = <&clk-audio>, <&clk_pmic>; - clock-names = "ln-gf-mclk2", "ln-pmic-32k"; - - assigned-clocks = <&lochnagar-clk LOCHNAGAR_CDC_MCLK1>, - <&lochnagar-clk LOCHNAGAR_CDC_MCLK2>; - assigned-clock-parents = <&clk-audio>, - <&clk-pmic>; - }; - - clk-pmic: clk-pmic { - compatible = "fixed-clock"; - clock-cells = <0>; - clock-frequency = <32768>; - }; -}; diff --git a/Bindings/clock/cirrus,lochnagar.yaml b/Bindings/clock/cirrus,lochnagar.yaml new file mode 100644 index 000000000000..59de125647ec --- /dev/null +++ b/Bindings/clock/cirrus,lochnagar.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/cirrus,lochnagar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic Lochnagar Audio Development Board + +maintainers: + - patches@opensource.cirrus.com + +description: | + Lochnagar is an evaluation and development board for Cirrus Logic + Smart CODEC and Amp devices. It allows the connection of most Cirrus + Logic devices on mini-cards, as well as allowing connection of various + application processor systems to provide a full evaluation platform. + Audio system topology, clocking and power can all be controlled through + the Lochnagar, allowing the device under test to be used in a variety of + possible use cases. + + This binding document describes the binding for the clock portion of the + driver. + + Also see these documents for generic binding information: + [1] Clock : ../clock/clock-bindings.txt + + And these for relevant defines: + [2] include/dt-bindings/clock/lochnagar.h + + This binding must be part of the Lochnagar MFD binding: + [3] ../mfd/cirrus,lochnagar.yaml + +properties: + compatible: + enum: + - cirrus,lochnagar1-clk + - cirrus,lochnagar2-clk + + '#clock-cells': + description: + The first cell indicates the clock number, see [2] for available + clocks and [1]. + const: 1 + + clock-names: + items: + enum: + - ln-cdc-clkout # Output clock from CODEC card. + - ln-dsp-clkout # Output clock from DSP card. + - ln-gf-mclk1 # Optional input clock from host system. + - ln-gf-mclk2 # Optional input clock from host system. + - ln-gf-mclk3 # Optional input clock from host system. + - ln-gf-mclk4 # Optional input clock from host system. + - ln-psia1-mclk # Optional input clock from external connector. + - ln-psia2-mclk # Optional input clock from external connector. + - ln-spdif-mclk # Optional input clock from SPDIF. + - ln-spdif-clkout # Optional input clock from SPDIF. + - ln-adat-mclk # Optional input clock from ADAT. + - ln-pmic-32k # On board fixed clock. + - ln-clk-12m # On board fixed clock. + - ln-clk-11m # On board fixed clock. + - ln-clk-24m # On board fixed clock. + - ln-clk-22m # On board fixed clock. + - ln-clk-8m # On board fixed clock. + - ln-usb-clk-24m # On board fixed clock. + - ln-usb-clk-12m # On board fixed clock. + minItems: 1 + maxItems: 19 + + clocks: true + assigned-clocks: true + assigned-clock-parents: true + +additionalProperties: false + +required: + - compatible + - '#clock-cells' diff --git a/Bindings/clock/fixed-factor-clock.yaml b/Bindings/clock/fixed-factor-clock.yaml index b567f8092f8c..f415845b38dd 100644 --- a/Bindings/clock/fixed-factor-clock.yaml +++ b/Bindings/clock/fixed-factor-clock.yaml @@ -24,9 +24,8 @@ properties: clock-div: description: Fixed divider - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 clock-mult: description: Fixed multiplier diff --git a/Bindings/clock/fsl,plldig.yaml b/Bindings/clock/fsl,plldig.yaml index a203d5d498db..9ac716dfa602 100644 --- a/Bindings/clock/fsl,plldig.yaml +++ b/Bindings/clock/fsl,plldig.yaml @@ -28,15 +28,14 @@ properties: const: 0 fsl,vco-hz: - description: Optional for VCO frequency of the PLL in Hertz. - The VCO frequency of this PLL cannot be changed during runtime - only at startup. Therefore, the output frequencies are very - limited and might not even closely match the requested frequency. - To work around this restriction the user may specify its own - desired VCO frequency for the PLL. - minimum: 650000000 - maximum: 1300000000 - default: 1188000000 + description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency + of this PLL cannot be changed during runtime only at startup. Therefore, + the output frequencies are very limited and might not even closely match + the requested frequency. To work around this restriction the user may specify + its own desired VCO frequency for the PLL. + minimum: 650000000 + maximum: 1300000000 + default: 1188000000 required: - compatible @@ -51,7 +50,7 @@ examples: - | dpclk: clock-display@f1f0000 { compatible = "fsl,ls1028a-plldig"; - reg = <0x0 0xf1f0000 0x0 0xffff>; + reg = <0xf1f0000 0xffff>; #clock-cells = <0>; clocks = <&osc_27m>; }; diff --git a/Bindings/clock/idt,versaclock5.txt b/Bindings/clock/idt,versaclock5.txt index 05a245c9df08..bcff681a4bd0 100644 --- a/Bindings/clock/idt,versaclock5.txt +++ b/Bindings/clock/idt,versaclock5.txt @@ -12,6 +12,7 @@ Required properties: "idt,5p49v5933" "idt,5p49v5935" "idt,5p49v6901" + "idt,5p49v6965" - reg: i2c device address, shall be 0x68 or 0x6a. - #clock-cells: from common clock binding; shall be set to 1. - clocks: from common clock binding; list of parent clock handles, diff --git a/Bindings/clock/imx1-clock.txt b/Bindings/clock/imx1-clock.txt deleted file mode 100644 index 9823baf7acb6..000000000000 --- a/Bindings/clock/imx1-clock.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Clock bindings for Freescale i.MX1 CPUs - -Required properties: -- compatible: Should be "fsl,imx1-ccm". -- reg: Address and length of the register set. -- #clock-cells: Should be <1>. - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h -for the full list of i.MX1 clock IDs. - -Examples: - clks: ccm@21b000 { - #clock-cells = <1>; - compatible = "fsl,imx1-ccm"; - reg = <0x0021b000 0x1000>; - }; - - pwm: pwm@208000 { - #pwm-cells = <2>; - compatible = "fsl,imx1-pwm"; - reg = <0x00208000 0x1000>; - interrupts = <34>; - clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>; - clock-names = "ipg", "per"; - }; diff --git a/Bindings/clock/imx1-clock.yaml b/Bindings/clock/imx1-clock.yaml new file mode 100644 index 000000000000..f4833a29b79e --- /dev/null +++ b/Bindings/clock/imx1-clock.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx1-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX1 CPUs + +maintainers: + - Alexander Shiyan + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h + for the full list of i.MX1 clock IDs. + +properties: + compatible: + const: fsl,imx1-ccm + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@21b000 { + #clock-cells = <1>; + compatible = "fsl,imx1-ccm"; + reg = <0x0021b000 0x1000>; + }; + + pwm@208000 { + #pwm-cells = <2>; + compatible = "fsl,imx1-pwm"; + reg = <0x00208000 0x1000>; + interrupts = <34>; + clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + }; diff --git a/Bindings/clock/imx21-clock.txt b/Bindings/clock/imx21-clock.txt deleted file mode 100644 index 806f63d628bd..000000000000 --- a/Bindings/clock/imx21-clock.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Clock bindings for Freescale i.MX21 - -Required properties: -- compatible : Should be "fsl,imx21-ccm". -- reg : Address and length of the register set. -- interrupts : Should contain CCM interrupt. -- #clock-cells: Should be <1>. - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h -for the full list of i.MX21 clock IDs. - -Examples: - clks: ccm@10027000{ - compatible = "fsl,imx21-ccm"; - reg = <0x10027000 0x800>; - #clock-cells = <1>; - }; - - uart1: serial@1000a000 { - compatible = "fsl,imx21-uart"; - reg = <0x1000a000 0x1000>; - interrupts = <20>; - clocks = <&clks IMX21_CLK_UART1_IPG_GATE>, - <&clks IMX21_CLK_PER1>; - clock-names = "ipg", "per"; - }; diff --git a/Bindings/clock/imx21-clock.yaml b/Bindings/clock/imx21-clock.yaml new file mode 100644 index 000000000000..518ad9a4733c --- /dev/null +++ b/Bindings/clock/imx21-clock.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx21-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX21 + +maintainers: + - Alexander Shiyan + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx21-clock.h + for the full list of i.MX21 clock IDs. + +properties: + compatible: + const: fsl,imx21-ccm + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@10027000 { + compatible = "fsl,imx21-ccm"; + reg = <0x10027000 0x800>; + #clock-cells = <1>; + }; + + serial@1000a000 { + compatible = "fsl,imx21-uart"; + reg = <0x1000a000 0x1000>; + interrupts = <20>; + clocks = <&clks IMX21_CLK_UART1_IPG_GATE>, + <&clks IMX21_CLK_PER1>; + clock-names = "ipg", "per"; + }; diff --git a/Bindings/clock/imx23-clock.txt b/Bindings/clock/imx23-clock.txt deleted file mode 100644 index 8385348d3bd9..000000000000 --- a/Bindings/clock/imx23-clock.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Clock bindings for Freescale i.MX23 - -Required properties: -- compatible: Should be "fsl,imx23-clkctrl" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX23 -clocks and IDs. - - Clock ID - ------------------ - ref_xtal 0 - pll 1 - ref_cpu 2 - ref_emi 3 - ref_pix 4 - ref_io 5 - saif_sel 6 - lcdif_sel 7 - gpmi_sel 8 - ssp_sel 9 - emi_sel 10 - cpu 11 - etm_sel 12 - cpu_pll 13 - cpu_xtal 14 - hbus 15 - xbus 16 - lcdif_div 17 - ssp_div 18 - gpmi_div 19 - emi_pll 20 - emi_xtal 21 - etm_div 22 - saif_div 23 - clk32k_div 24 - rtc 25 - adc 26 - spdif_div 27 - clk32k 28 - dri 29 - pwm 30 - filt 31 - uart 32 - ssp 33 - gpmi 34 - spdif 35 - emi 36 - saif 37 - lcdif 38 - etm 39 - usb 40 - usb_phy 41 - -Examples: - -clks: clkctrl@80040000 { - compatible = "fsl,imx23-clkctrl"; - reg = <0x80040000 0x2000>; - #clock-cells = <1>; -}; - -auart0: serial@8006c000 { - compatible = "fsl,imx23-auart"; - reg = <0x8006c000 0x2000>; - interrupts = <24 25 23>; - clocks = <&clks 32>; -}; diff --git a/Bindings/clock/imx23-clock.yaml b/Bindings/clock/imx23-clock.yaml new file mode 100644 index 000000000000..66cb238a1040 --- /dev/null +++ b/Bindings/clock/imx23-clock.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx23-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX23 + +maintainers: + - Shawn Guo + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. The following is a full list of i.MX23 + clocks and IDs. + + Clock ID + ------------------ + ref_xtal 0 + pll 1 + ref_cpu 2 + ref_emi 3 + ref_pix 4 + ref_io 5 + saif_sel 6 + lcdif_sel 7 + gpmi_sel 8 + ssp_sel 9 + emi_sel 10 + cpu 11 + etm_sel 12 + cpu_pll 13 + cpu_xtal 14 + hbus 15 + xbus 16 + lcdif_div 17 + ssp_div 18 + gpmi_div 19 + emi_pll 20 + emi_xtal 21 + etm_div 22 + saif_div 23 + clk32k_div 24 + rtc 25 + adc 26 + spdif_div 27 + clk32k 28 + dri 29 + pwm 30 + filt 31 + uart 32 + ssp 33 + gpmi 34 + spdif 35 + emi 36 + saif 37 + lcdif 38 + etm 39 + usb 40 + usb_phy 41 + +properties: + compatible: + const: fsl,imx23-clkctrl + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@80040000 { + compatible = "fsl,imx23-clkctrl"; + reg = <0x80040000 0x2000>; + #clock-cells = <1>; + }; + + serial@8006c000 { + compatible = "fsl,imx23-auart"; + reg = <0x8006c000 0x2000>; + interrupts = <24 25 23>; + clocks = <&clks 32>; + }; diff --git a/Bindings/clock/imx25-clock.txt b/Bindings/clock/imx25-clock.txt deleted file mode 100644 index f8135ea9ca4e..000000000000 --- a/Bindings/clock/imx25-clock.txt +++ /dev/null @@ -1,160 +0,0 @@ -* Clock bindings for Freescale i.MX25 - -Required properties: -- compatible: Should be "fsl,imx25-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX25 -clocks and IDs. - - Clock ID - --------------------------- - dummy 0 - osc 1 - mpll 2 - upll 3 - mpll_cpu_3_4 4 - cpu_sel 5 - cpu 6 - ahb 7 - usb_div 8 - ipg 9 - per0_sel 10 - per1_sel 11 - per2_sel 12 - per3_sel 13 - per4_sel 14 - per5_sel 15 - per6_sel 16 - per7_sel 17 - per8_sel 18 - per9_sel 19 - per10_sel 20 - per11_sel 21 - per12_sel 22 - per13_sel 23 - per14_sel 24 - per15_sel 25 - per0 26 - per1 27 - per2 28 - per3 29 - per4 30 - per5 31 - per6 32 - per7 33 - per8 34 - per9 35 - per10 36 - per11 37 - per12 38 - per13 39 - per14 40 - per15 41 - csi_ipg_per 42 - epit_ipg_per 43 - esai_ipg_per 44 - esdhc1_ipg_per 45 - esdhc2_ipg_per 46 - gpt_ipg_per 47 - i2c_ipg_per 48 - lcdc_ipg_per 49 - nfc_ipg_per 50 - owire_ipg_per 51 - pwm_ipg_per 52 - sim1_ipg_per 53 - sim2_ipg_per 54 - ssi1_ipg_per 55 - ssi2_ipg_per 56 - uart_ipg_per 57 - ata_ahb 58 - reserved 59 - csi_ahb 60 - emi_ahb 61 - esai_ahb 62 - esdhc1_ahb 63 - esdhc2_ahb 64 - fec_ahb 65 - lcdc_ahb 66 - rtic_ahb 67 - sdma_ahb 68 - slcdc_ahb 69 - usbotg_ahb 70 - reserved 71 - reserved 72 - reserved 73 - reserved 74 - can1_ipg 75 - can2_ipg 76 - csi_ipg 77 - cspi1_ipg 78 - cspi2_ipg 79 - cspi3_ipg 80 - dryice_ipg 81 - ect_ipg 82 - epit1_ipg 83 - epit2_ipg 84 - reserved 85 - esdhc1_ipg 86 - esdhc2_ipg 87 - fec_ipg 88 - reserved 89 - reserved 90 - reserved 91 - gpt1_ipg 92 - gpt2_ipg 93 - gpt3_ipg 94 - gpt4_ipg 95 - reserved 96 - reserved 97 - reserved 98 - iim_ipg 99 - reserved 100 - reserved 101 - kpp_ipg 102 - lcdc_ipg 103 - reserved 104 - pwm1_ipg 105 - pwm2_ipg 106 - pwm3_ipg 107 - pwm4_ipg 108 - rngb_ipg 109 - reserved 110 - scc_ipg 111 - sdma_ipg 112 - sim1_ipg 113 - sim2_ipg 114 - slcdc_ipg 115 - spba_ipg 116 - ssi1_ipg 117 - ssi2_ipg 118 - tsc_ipg 119 - uart1_ipg 120 - uart2_ipg 121 - uart3_ipg 122 - uart4_ipg 123 - uart5_ipg 124 - reserved 125 - wdt_ipg 126 - cko_div 127 - cko_sel 128 - cko 129 - -Examples: - -clks: ccm@53f80000 { - compatible = "fsl,imx25-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>; -}; - -uart1: serial@43f90000 { - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - interrupts = <45>; - clocks = <&clks 79>, <&clks 50>; - clock-names = "ipg", "per"; -}; diff --git a/Bindings/clock/imx25-clock.yaml b/Bindings/clock/imx25-clock.yaml new file mode 100644 index 000000000000..2a2b10778e72 --- /dev/null +++ b/Bindings/clock/imx25-clock.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx25-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX25 + +maintainers: + - Sascha Hauer + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. The following is a full list of i.MX25 + clocks and IDs. + + Clock ID + -------------------------- + dummy 0 + osc 1 + mpll 2 + upll 3 + mpll_cpu_3_4 4 + cpu_sel 5 + cpu 6 + ahb 7 + usb_div 8 + ipg 9 + per0_sel 10 + per1_sel 11 + per2_sel 12 + per3_sel 13 + per4_sel 14 + per5_sel 15 + per6_sel 16 + per7_sel 17 + per8_sel 18 + per9_sel 19 + per10_sel 20 + per11_sel 21 + per12_sel 22 + per13_sel 23 + per14_sel 24 + per15_sel 25 + per0 26 + per1 27 + per2 28 + per3 29 + per4 30 + per5 31 + per6 32 + per7 33 + per8 34 + per9 35 + per10 36 + per11 37 + per12 38 + per13 39 + per14 40 + per15 41 + csi_ipg_per 42 + epit_ipg_per 43 + esai_ipg_per 44 + esdhc1_ipg_per 45 + esdhc2_ipg_per 46 + gpt_ipg_per 47 + i2c_ipg_per 48 + lcdc_ipg_per 49 + nfc_ipg_per 50 + owire_ipg_per 51 + pwm_ipg_per 52 + sim1_ipg_per 53 + sim2_ipg_per 54 + ssi1_ipg_per 55 + ssi2_ipg_per 56 + uart_ipg_per 57 + ata_ahb 58 + reserved 59 + csi_ahb 60 + emi_ahb 61 + esai_ahb 62 + esdhc1_ahb 63 + esdhc2_ahb 64 + fec_ahb 65 + lcdc_ahb 66 + rtic_ahb 67 + sdma_ahb 68 + slcdc_ahb 69 + usbotg_ahb 70 + reserved 71 + reserved 72 + reserved 73 + reserved 74 + can1_ipg 75 + can2_ipg 76 + csi_ipg 77 + cspi1_ipg 78 + cspi2_ipg 79 + cspi3_ipg 80 + dryice_ipg 81 + ect_ipg 82 + epit1_ipg 83 + epit2_ipg 84 + reserved 85 + esdhc1_ipg 86 + esdhc2_ipg 87 + fec_ipg 88 + reserved 89 + reserved 90 + reserved 91 + gpt1_ipg 92 + gpt2_ipg 93 + gpt3_ipg 94 + gpt4_ipg 95 + reserved 96 + reserved 97 + reserved 98 + iim_ipg 99 + reserved 100 + reserved 101 + kpp_ipg 102 + lcdc_ipg 103 + reserved 104 + pwm1_ipg 105 + pwm2_ipg 106 + pwm3_ipg 107 + pwm4_ipg 108 + rngb_ipg 109 + reserved 110 + scc_ipg 111 + sdma_ipg 112 + sim1_ipg 113 + sim2_ipg 114 + slcdc_ipg 115 + spba_ipg 116 + ssi1_ipg 117 + ssi2_ipg 118 + tsc_ipg 119 + uart1_ipg 120 + uart2_ipg 121 + uart3_ipg 122 + uart4_ipg 123 + uart5_ipg 124 + reserved 125 + wdt_ipg 126 + cko_div 127 + cko_sel 128 + cko 129 + +properties: + compatible: + const: fsl,imx25-ccm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@53f80000 { + compatible = "fsl,imx25-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <31>; + #clock-cells = <1>; + }; + + serial@43f90000 { + compatible = "fsl,imx25-uart", "fsl,imx21-uart"; + reg = <0x43f90000 0x4000>; + interrupts = <45>; + clocks = <&clks 79>, <&clks 50>; + clock-names = "ipg", "per"; + }; diff --git a/Bindings/clock/imx27-clock.txt b/Bindings/clock/imx27-clock.txt deleted file mode 100644 index 4c95c048d3b2..000000000000 --- a/Bindings/clock/imx27-clock.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Clock bindings for Freescale i.MX27 - -Required properties: -- compatible: Should be "fsl,imx27-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h -for the full list of i.MX27 clock IDs. - -Examples: - clks: ccm@10027000{ - compatible = "fsl,imx27-ccm"; - reg = <0x10027000 0x1000>; - #clock-cells = <1>; - }; - - uart1: serial@1000a000 { - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; - reg = <0x1000a000 0x1000>; - interrupts = <20>; - clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; - }; diff --git a/Bindings/clock/imx27-clock.yaml b/Bindings/clock/imx27-clock.yaml new file mode 100644 index 000000000000..a75365453dbc --- /dev/null +++ b/Bindings/clock/imx27-clock.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx27-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX27 + +maintainers: + - Fabio Estevam + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx27-clock.h + for the full list of i.MX27 clock IDs. + +properties: + compatible: + const: fsl,imx27-ccm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@10027000 { + compatible = "fsl,imx27-ccm"; + reg = <0x10027000 0x1000>; + interrupts = <31>; + #clock-cells = <1>; + }; + + serial@1000a000 { + compatible = "fsl,imx27-uart", "fsl,imx21-uart"; + reg = <0x1000a000 0x1000>; + interrupts = <20>; + clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + }; diff --git a/Bindings/clock/imx28-clock.txt b/Bindings/clock/imx28-clock.txt deleted file mode 100644 index d84a37d2885f..000000000000 --- a/Bindings/clock/imx28-clock.txt +++ /dev/null @@ -1,93 +0,0 @@ -* Clock bindings for Freescale i.MX28 - -Required properties: -- compatible: Should be "fsl,imx28-clkctrl" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX28 -clocks and IDs. - - Clock ID - ------------------ - ref_xtal 0 - pll0 1 - pll1 2 - pll2 3 - ref_cpu 4 - ref_emi 5 - ref_io0 6 - ref_io1 7 - ref_pix 8 - ref_hsadc 9 - ref_gpmi 10 - saif0_sel 11 - saif1_sel 12 - gpmi_sel 13 - ssp0_sel 14 - ssp1_sel 15 - ssp2_sel 16 - ssp3_sel 17 - emi_sel 18 - etm_sel 19 - lcdif_sel 20 - cpu 21 - ptp_sel 22 - cpu_pll 23 - cpu_xtal 24 - hbus 25 - xbus 26 - ssp0_div 27 - ssp1_div 28 - ssp2_div 29 - ssp3_div 30 - gpmi_div 31 - emi_pll 32 - emi_xtal 33 - lcdif_div 34 - etm_div 35 - ptp 36 - saif0_div 37 - saif1_div 38 - clk32k_div 39 - rtc 40 - lradc 41 - spdif_div 42 - clk32k 43 - pwm 44 - uart 45 - ssp0 46 - ssp1 47 - ssp2 48 - ssp3 49 - gpmi 50 - spdif 51 - emi 52 - saif0 53 - saif1 54 - lcdif 55 - etm 56 - fec 57 - can0 58 - can1 59 - usb0 60 - usb1 61 - usb0_phy 62 - usb1_phy 63 - enet_out 64 - -Examples: - -clks: clkctrl@80040000 { - compatible = "fsl,imx28-clkctrl"; - reg = <0x80040000 0x2000>; - #clock-cells = <1>; -}; - -auart0: serial@8006a000 { - compatible = "fsl,imx28-auart", "fsl,imx23-auart"; - reg = <0x8006a000 0x2000>; - interrupts = <112 70 71>; - clocks = <&clks 45>; -}; diff --git a/Bindings/clock/imx28-clock.yaml b/Bindings/clock/imx28-clock.yaml new file mode 100644 index 000000000000..72328d5ca09a --- /dev/null +++ b/Bindings/clock/imx28-clock.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx28-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX28 + +maintainers: + - Shawn Guo + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. The following is a full list of i.MX28 + clocks and IDs. + + Clock ID + ------------------ + ref_xtal 0 + pll0 1 + pll1 2 + pll2 3 + ref_cpu 4 + ref_emi 5 + ref_io0 6 + ref_io1 7 + ref_pix 8 + ref_hsadc 9 + ref_gpmi 10 + saif0_sel 11 + saif1_sel 12 + gpmi_sel 13 + ssp0_sel 14 + ssp1_sel 15 + ssp2_sel 16 + ssp3_sel 17 + emi_sel 18 + etm_sel 19 + lcdif_sel 20 + cpu 21 + ptp_sel 22 + cpu_pll 23 + cpu_xtal 24 + hbus 25 + xbus 26 + ssp0_div 27 + ssp1_div 28 + ssp2_div 29 + ssp3_div 30 + gpmi_div 31 + emi_pll 32 + emi_xtal 33 + lcdif_div 34 + etm_div 35 + ptp 36 + saif0_div 37 + saif1_div 38 + clk32k_div 39 + rtc 40 + lradc 41 + spdif_div 42 + clk32k 43 + pwm 44 + uart 45 + ssp0 46 + ssp1 47 + ssp2 48 + ssp3 49 + gpmi 50 + spdif 51 + emi 52 + saif0 53 + saif1 54 + lcdif 55 + etm 56 + fec 57 + can0 58 + can1 59 + usb0 60 + usb1 61 + usb0_phy 62 + usb1_phy 63 + enet_out 64 + +properties: + compatible: + const: fsl,imx28-clkctrl + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@80040000 { + compatible = "fsl,imx28-clkctrl"; + reg = <0x80040000 0x2000>; + #clock-cells = <1>; + }; + + serial@8006a000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006a000 0x2000>; + interrupts = <112 70 71>; + clocks = <&clks 45>; + }; diff --git a/Bindings/clock/imx31-clock.txt b/Bindings/clock/imx31-clock.txt deleted file mode 100644 index 0a291090e562..000000000000 --- a/Bindings/clock/imx31-clock.txt +++ /dev/null @@ -1,90 +0,0 @@ -* Clock bindings for Freescale i.MX31 - -Required properties: -- compatible: Should be "fsl,imx31-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX31 -clocks and IDs. - - Clock ID - ----------------------- - dummy 0 - ckih 1 - ckil 2 - mpll 3 - spll 4 - upll 5 - mcu_main 6 - hsp 7 - ahb 8 - nfc 9 - ipg 10 - per_div 11 - per 12 - csi_sel 13 - fir_sel 14 - csi_div 15 - usb_div_pre 16 - usb_div_post 17 - fir_div_pre 18 - fir_div_post 19 - sdhc1_gate 20 - sdhc2_gate 21 - gpt_gate 22 - epit1_gate 23 - epit2_gate 24 - iim_gate 25 - ata_gate 26 - sdma_gate 27 - cspi3_gate 28 - rng_gate 29 - uart1_gate 30 - uart2_gate 31 - ssi1_gate 32 - i2c1_gate 33 - i2c2_gate 34 - i2c3_gate 35 - hantro_gate 36 - mstick1_gate 37 - mstick2_gate 38 - csi_gate 39 - rtc_gate 40 - wdog_gate 41 - pwm_gate 42 - sim_gate 43 - ect_gate 44 - usb_gate 45 - kpp_gate 46 - ipu_gate 47 - uart3_gate 48 - uart4_gate 49 - uart5_gate 50 - owire_gate 51 - ssi2_gate 52 - cspi1_gate 53 - cspi2_gate 54 - gacc_gate 55 - emi_gate 56 - rtic_gate 57 - firi_gate 58 - -Examples: - -clks: ccm@53f80000{ - compatible = "fsl,imx31-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>, <53>; - #clock-cells = <1>; -}; - -uart1: serial@43f90000 { - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; - reg = <0x43f90000 0x4000>; - interrupts = <45>; - clocks = <&clks 10>, <&clks 30>; - clock-names = "ipg", "per"; -}; diff --git a/Bindings/clock/imx31-clock.yaml b/Bindings/clock/imx31-clock.yaml new file mode 100644 index 000000000000..a25a374b3b2a --- /dev/null +++ b/Bindings/clock/imx31-clock.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx31-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX31 + +maintainers: + - Fabio Estevam + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. The following is a full list of i.MX31 + clocks and IDs. + + Clock ID + ----------------------- + dummy 0 + ckih 1 + ckil 2 + mpll 3 + spll 4 + upll 5 + mcu_main 6 + hsp 7 + ahb 8 + nfc 9 + ipg 10 + per_div 11 + per 12 + csi_sel 13 + fir_sel 14 + csi_div 15 + usb_div_pre 16 + usb_div_post 17 + fir_div_pre 18 + fir_div_post 19 + sdhc1_gate 20 + sdhc2_gate 21 + gpt_gate 22 + epit1_gate 23 + epit2_gate 24 + iim_gate 25 + ata_gate 26 + sdma_gate 27 + cspi3_gate 28 + rng_gate 29 + uart1_gate 30 + uart2_gate 31 + ssi1_gate 32 + i2c1_gate 33 + i2c2_gate 34 + i2c3_gate 35 + hantro_gate 36 + mstick1_gate 37 + mstick2_gate 38 + csi_gate 39 + rtc_gate 40 + wdog_gate 41 + pwm_gate 42 + sim_gate 43 + ect_gate 44 + usb_gate 45 + kpp_gate 46 + ipu_gate 47 + uart3_gate 48 + uart4_gate 49 + uart5_gate 50 + owire_gate 51 + ssi2_gate 52 + cspi1_gate 53 + cspi2_gate 54 + gacc_gate 55 + emi_gate 56 + rtic_gate 57 + firi_gate 58 + +properties: + compatible: + const: fsl,imx31-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for DVFS when a frequency change is requested, request 2 is + to generate interrupt for DPTC when a voltage change is requested. + items: + - description: CCM DVFS interrupt request 1 + - description: CCM DPTC interrupt request 2 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@53f80000 { + compatible = "fsl,imx31-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <31>, <53>; + #clock-cells = <1>; + }; + + serial@43f90000 { + compatible = "fsl,imx31-uart", "fsl,imx21-uart"; + reg = <0x43f90000 0x4000>; + interrupts = <45>; + clocks = <&clks 10>, <&clks 30>; + clock-names = "ipg", "per"; + }; diff --git a/Bindings/clock/imx35-clock.txt b/Bindings/clock/imx35-clock.txt deleted file mode 100644 index f49783213c56..000000000000 --- a/Bindings/clock/imx35-clock.txt +++ /dev/null @@ -1,114 +0,0 @@ -* Clock bindings for Freescale i.MX35 - -Required properties: -- compatible: Should be "fsl,imx35-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. The following is a full list of i.MX35 -clocks and IDs. - - Clock ID - --------------------------- - ckih 0 - mpll 1 - ppll 2 - mpll_075 3 - arm 4 - hsp 5 - hsp_div 6 - hsp_sel 7 - ahb 8 - ipg 9 - arm_per_div 10 - ahb_per_div 11 - ipg_per 12 - uart_sel 13 - uart_div 14 - esdhc_sel 15 - esdhc1_div 16 - esdhc2_div 17 - esdhc3_div 18 - spdif_sel 19 - spdif_div_pre 20 - spdif_div_post 21 - ssi_sel 22 - ssi1_div_pre 23 - ssi1_div_post 24 - ssi2_div_pre 25 - ssi2_div_post 26 - usb_sel 27 - usb_div 28 - nfc_div 29 - asrc_gate 30 - pata_gate 31 - audmux_gate 32 - can1_gate 33 - can2_gate 34 - cspi1_gate 35 - cspi2_gate 36 - ect_gate 37 - edio_gate 38 - emi_gate 39 - epit1_gate 40 - epit2_gate 41 - esai_gate 42 - esdhc1_gate 43 - esdhc2_gate 44 - esdhc3_gate 45 - fec_gate 46 - gpio1_gate 47 - gpio2_gate 48 - gpio3_gate 49 - gpt_gate 50 - i2c1_gate 51 - i2c2_gate 52 - i2c3_gate 53 - iomuxc_gate 54 - ipu_gate 55 - kpp_gate 56 - mlb_gate 57 - mshc_gate 58 - owire_gate 59 - pwm_gate 60 - rngc_gate 61 - rtc_gate 62 - rtic_gate 63 - scc_gate 64 - sdma_gate 65 - spba_gate 66 - spdif_gate 67 - ssi1_gate 68 - ssi2_gate 69 - uart1_gate 70 - uart2_gate 71 - uart3_gate 72 - usbotg_gate 73 - wdog_gate 74 - max_gate 75 - admux_gate 76 - csi_gate 77 - csi_div 78 - csi_sel 79 - iim_gate 80 - gpu2d_gate 81 - ckli_gate 82 - -Examples: - -clks: ccm@53f80000 { - compatible = "fsl,imx35-ccm"; - reg = <0x53f80000 0x4000>; - interrupts = <31>; - #clock-cells = <1>; -}; - -esdhc1: esdhc@53fb4000 { - compatible = "fsl,imx35-esdhc"; - reg = <0x53fb4000 0x4000>; - interrupts = <7>; - clocks = <&clks 9>, <&clks 8>, <&clks 43>; - clock-names = "ipg", "ahb", "per"; -}; diff --git a/Bindings/clock/imx35-clock.yaml b/Bindings/clock/imx35-clock.yaml new file mode 100644 index 000000000000..bd871da6fc7c --- /dev/null +++ b/Bindings/clock/imx35-clock.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx35-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX35 + +maintainers: + - Steffen Trumtrar + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. The following is a full list of i.MX35 + clocks and IDs. + + Clock ID + --------------------------- + ckih 0 + mpll 1 + ppll 2 + mpll_075 3 + arm 4 + hsp 5 + hsp_div 6 + hsp_sel 7 + ahb 8 + ipg 9 + arm_per_div 10 + ahb_per_div 11 + ipg_per 12 + uart_sel 13 + uart_div 14 + esdhc_sel 15 + esdhc1_div 16 + esdhc2_div 17 + esdhc3_div 18 + spdif_sel 19 + spdif_div_pre 20 + spdif_div_post 21 + ssi_sel 22 + ssi1_div_pre 23 + ssi1_div_post 24 + ssi2_div_pre 25 + ssi2_div_post 26 + usb_sel 27 + usb_div 28 + nfc_div 29 + asrc_gate 30 + pata_gate 31 + audmux_gate 32 + can1_gate 33 + can2_gate 34 + cspi1_gate 35 + cspi2_gate 36 + ect_gate 37 + edio_gate 38 + emi_gate 39 + epit1_gate 40 + epit2_gate 41 + esai_gate 42 + esdhc1_gate 43 + esdhc2_gate 44 + esdhc3_gate 45 + fec_gate 46 + gpio1_gate 47 + gpio2_gate 48 + gpio3_gate 49 + gpt_gate 50 + i2c1_gate 51 + i2c2_gate 52 + i2c3_gate 53 + iomuxc_gate 54 + ipu_gate 55 + kpp_gate 56 + mlb_gate 57 + mshc_gate 58 + owire_gate 59 + pwm_gate 60 + rngc_gate 61 + rtc_gate 62 + rtic_gate 63 + scc_gate 64 + sdma_gate 65 + spba_gate 66 + spdif_gate 67 + ssi1_gate 68 + ssi2_gate 69 + uart1_gate 70 + uart2_gate 71 + uart3_gate 72 + usbotg_gate 73 + wdog_gate 74 + max_gate 75 + admux_gate 76 + csi_gate 77 + csi_div 78 + csi_sel 79 + iim_gate 80 + gpu2d_gate 81 + ckli_gate 82 + +properties: + compatible: + const: fsl,imx35-ccm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@53f80000 { + compatible = "fsl,imx35-ccm"; + reg = <0x53f80000 0x4000>; + interrupts = <31>; + #clock-cells = <1>; + }; + + esdhc@53fb4000 { + compatible = "fsl,imx35-esdhc"; + reg = <0x53fb4000 0x4000>; + interrupts = <7>; + clocks = <&clks 9>, <&clks 8>, <&clks 43>; + clock-names = "ipg", "ahb", "per"; + }; diff --git a/Bindings/clock/imx5-clock.txt b/Bindings/clock/imx5-clock.txt deleted file mode 100644 index a24ca9e582d2..000000000000 --- a/Bindings/clock/imx5-clock.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Clock bindings for Freescale i.MX5 - -Required properties: -- compatible: Should be "fsl,-ccm" , where can be imx51 or imx53 -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h -for the full list of i.MX5 clock IDs. - -Examples (for mx53): - -clks: ccm@53fd4000{ - compatible = "fsl,imx53-ccm"; - reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; - #clock-cells = <1>; -}; - -can1: can@53fc8000 { - compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; - reg = <0x53fc8000 0x4000>; - interrupts = <82>; - clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>; - clock-names = "ipg", "per"; -}; diff --git a/Bindings/clock/imx5-clock.yaml b/Bindings/clock/imx5-clock.yaml new file mode 100644 index 000000000000..4d9e7c73dce9 --- /dev/null +++ b/Bindings/clock/imx5-clock.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx5-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX5 + +maintainers: + - Fabio Estevam + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx5-clock.h + for the full list of i.MX5 clock IDs. + +properties: + compatible: + enum: + - fsl,imx53-ccm + - fsl,imx51-ccm + - fsl,imx50-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for frequency or mux change, request 2 is to generate + interrupt for oscillator read or PLL lock. + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + clock-controller@53fd4000{ + compatible = "fsl,imx53-ccm"; + reg = <0x53fd4000 0x4000>; + interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>, + <0 72 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + }; + + can@53fc8000 { + compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; + reg = <0x53fc8000 0x4000>; + interrupts = <82>; + clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>; + clock-names = "ipg", "per"; + }; diff --git a/Bindings/clock/imx6q-clock.txt b/Bindings/clock/imx6q-clock.txt deleted file mode 100644 index 13d36d4c6991..000000000000 --- a/Bindings/clock/imx6q-clock.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Clock bindings for Freescale i.MX6 Quad - -Required properties: -- compatible: Should be "fsl,imx6q-ccm" -- reg: Address and length of the register set -- interrupts: Should contain CCM interrupt -- #clock-cells: Should be <1> - -Optional properties: -- fsl,pmic-stby-poweroff: Configure CCM to assert PMIC_STBY_REQ signal - on power off. - Use this property if the SoC should be powered off by external power - management IC (PMIC) triggered via PMIC_STBY_REQ signal. - Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should - be using "syscon-poweroff" driver instead. -- clocks: list of clock specifiers, must contain an entry for each entry - in clock-names -- clock-names: valid names are "osc", "ckil", "ckih1", "anaclk1" and "anaclk2" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h -for the full list of i.MX6 Quad and DualLite clock IDs. - -Examples: - -#include - -clks: ccm@20c4000 { - compatible = "fsl,imx6q-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = <0 87 0x04 0 88 0x04>; - #clock-cells = <1>; -}; - -uart1: serial@2020000 { - compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = <0 26 0x04>; - clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>; - clock-names = "ipg", "per"; -}; diff --git a/Bindings/clock/imx6q-clock.yaml b/Bindings/clock/imx6q-clock.yaml new file mode 100644 index 000000000000..92a8e545e212 --- /dev/null +++ b/Bindings/clock/imx6q-clock.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx6q-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX6 Quad + +maintainers: + - Anson Huang + +properties: + compatible: + const: fsl,imx6q-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for frequency or mux change, request 2 is to generate + interrupt for oscillator read or PLL lock. + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: 24m osc + - description: 32k osc + - description: ckih1 clock input + - description: anaclk1 clock input + - description: anaclk2 clock input + + clock-names: + items: + - const: osc + - const: ckil + - const: ckih1 + - const: anaclk1 + - const: anaclk2 + + fsl,pmic-stby-poweroff: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Use this property if the SoC should be powered off by external power + management IC (PMIC) triggered via PMIC_STBY_REQ signal. + Boards that are designed to initiate poweroff on PMIC_ON_REQ signal should + be using "syscon-poweroff" driver instead. + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + +examples: + # Clock Control Module node: + - | + #include + + clock-controller@20c4000 { + compatible = "fsl,imx6q-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, + <0 88 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + }; diff --git a/Bindings/clock/imx6sl-clock.txt b/Bindings/clock/imx6sl-clock.txt deleted file mode 100644 index 15e40bdf147d..000000000000 --- a/Bindings/clock/imx6sl-clock.txt +++ /dev/null @@ -1,10 +0,0 @@ -* Clock bindings for Freescale i.MX6 SoloLite - -Required properties: -- compatible: Should be "fsl,imx6sl-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sl-clock.h -for the full list of i.MX6 SoloLite clock IDs. diff --git a/Bindings/clock/imx6sl-clock.yaml b/Bindings/clock/imx6sl-clock.yaml new file mode 100644 index 000000000000..c97bf95b4150 --- /dev/null +++ b/Bindings/clock/imx6sl-clock.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx6sl-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX6 SoloLite + +maintainers: + - Anson Huang + +properties: + compatible: + const: fsl,imx6sl-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for frequency or mux change, request 2 is to generate + interrupt for oscillator read or PLL lock. + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + +examples: + # Clock Control Module node: + - | + #include + + clock-controller@20c4000 { + compatible = "fsl,imx6sl-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, + <0 88 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + }; diff --git a/Bindings/clock/imx6sll-clock.txt b/Bindings/clock/imx6sll-clock.txt deleted file mode 100644 index fee849d5fdd1..000000000000 --- a/Bindings/clock/imx6sll-clock.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Clock bindings for Freescale i.MX6 SLL - -Required properties: -- compatible: Should be "fsl,imx6sll-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h -for the full list of i.MX6 SLL clock IDs. - -Examples: - -#include - -clks: clock-controller@20c4000 { - compatible = "fsl,imx6sll-ccm"; - reg = <0x020c4000 0x4000>; - interrupts = , - ; - #clock-cells = <1>; - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; -}; - -uart1: serial@2020000 { - compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; - reg = <0x02020000 0x4000>; - interrupts = ; - clocks = <&clks IMX6SLL_CLK_UART1_IPG>, - <&clks IMX6SLL_CLK_UART1_SERIAL>; - clock-names = "ipg", "per"; -}; diff --git a/Bindings/clock/imx6sll-clock.yaml b/Bindings/clock/imx6sll-clock.yaml new file mode 100644 index 000000000000..de48924be191 --- /dev/null +++ b/Bindings/clock/imx6sll-clock.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx6sll-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX6 SLL + +maintainers: + - Anson Huang + +properties: + compatible: + const: fsl,imx6sll-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for frequency or mux change, request 2 is to generate + interrupt for oscillator read or PLL lock. + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: 32k osc + - description: 24m osc + - description: ipp_di0 clock input + - description: ipp_di1 clock input + + clock-names: + items: + - const: ckil + - const: osc + - const: ipp_di0 + - const: ipp_di1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + - clocks + - clock-names + +examples: + # Clock Control Module node: + - | + #include + + clock-controller@20c4000 { + compatible = "fsl,imx6sll-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + }; diff --git a/Bindings/clock/imx6sx-clock.txt b/Bindings/clock/imx6sx-clock.txt deleted file mode 100644 index 22362b9b7ba3..000000000000 --- a/Bindings/clock/imx6sx-clock.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Clock bindings for Freescale i.MX6 SoloX - -Required properties: -- compatible: Should be "fsl,imx6sx-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h -for the full list of i.MX6 SoloX clock IDs. diff --git a/Bindings/clock/imx6sx-clock.yaml b/Bindings/clock/imx6sx-clock.yaml new file mode 100644 index 000000000000..e50cddee43c3 --- /dev/null +++ b/Bindings/clock/imx6sx-clock.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx6sx-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX6 SoloX + +maintainers: + - Anson Huang + +properties: + compatible: + const: fsl,imx6sx-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for frequency or mux change, request 2 is to generate + interrupt for oscillator read or PLL lock. + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: 32k osc + - description: 24m osc + - description: ipp_di0 clock input + - description: ipp_di1 clock input + - description: anaclk1 clock input + - description: anaclk2 clock input + + clock-names: + items: + - const: ckil + - const: osc + - const: ipp_di0 + - const: ipp_di1 + - const: anaclk1 + - const: anaclk2 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + - clocks + - clock-names + +examples: + # Clock Control Module node: + - | + #include + + clock-controller@20c4000 { + compatible = "fsl,imx6sx-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; + }; diff --git a/Bindings/clock/imx6ul-clock.txt b/Bindings/clock/imx6ul-clock.txt deleted file mode 100644 index 571d5039f663..000000000000 --- a/Bindings/clock/imx6ul-clock.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Clock bindings for Freescale i.MX6 UltraLite - -Required properties: -- compatible: Should be "fsl,imx6ul-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6ul-clock.h -for the full list of i.MX6 UltraLite clock IDs. diff --git a/Bindings/clock/imx6ul-clock.yaml b/Bindings/clock/imx6ul-clock.yaml new file mode 100644 index 000000000000..36ce7667c972 --- /dev/null +++ b/Bindings/clock/imx6ul-clock.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx6ul-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX6 UltraLite + +maintainers: + - Anson Huang + +properties: + compatible: + const: fsl,imx6ul-ccm + + reg: + maxItems: 1 + + interrupts: + description: CCM provides 2 interrupt requests, request 1 is to generate + interrupt for frequency or mux change, request 2 is to generate + interrupt for oscillator read or PLL lock. + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: 32k osc + - description: 24m osc + - description: ipp_di0 clock input + - description: ipp_di1 clock input + + clock-names: + items: + - const: ckil + - const: osc + - const: ipp_di0 + - const: ipp_di1 + +required: + - compatible + - reg + - interrupts + - '#clock-cells' + - clocks + - clock-names + +examples: + # Clock Control Module node: + - | + #include + + clock-controller@20c4000 { + compatible = "fsl,imx6ul-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + }; diff --git a/Bindings/clock/imx7d-clock.txt b/Bindings/clock/imx7d-clock.txt deleted file mode 100644 index 9d3026d81a68..000000000000 --- a/Bindings/clock/imx7d-clock.txt +++ /dev/null @@ -1,13 +0,0 @@ -* Clock bindings for Freescale i.MX7 Dual - -Required properties: -- compatible: Should be "fsl,imx7d-ccm" -- reg: Address and length of the register set -- #clock-cells: Should be <1> -- clocks: list of clock specifiers, must contain an entry for each required - entry in clock-names -- clock-names: should include entries "ckil", "osc" - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h -for the full list of i.MX7 Dual clock IDs. diff --git a/Bindings/clock/imx7d-clock.yaml b/Bindings/clock/imx7d-clock.yaml new file mode 100644 index 000000000000..cefb61db01a8 --- /dev/null +++ b/Bindings/clock/imx7d-clock.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx7d-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Freescale i.MX7 Dual + +maintainers: + - Frank Li + - Anson Huang + +description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx7d-clock.h + for the full list of i.MX7 Dual clock IDs. + +properties: + compatible: + const: fsl,imx7d-ccm + + reg: + maxItems: 1 + + interrupts: + items: + - description: CCM interrupt request 1 + - description: CCM interrupt request 2 + + '#clock-cells': + const: 1 + + clocks: + items: + - description: 32k osc + - description: 24m osc + + clock-names: + items: + - const: ckil + - const: osc + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@30380000 { + compatible = "fsl,imx7d-ccm"; + reg = <0x30380000 0x10000>; + interrupts = , + ; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>; + clock-names = "ckil", "osc"; + }; diff --git a/Bindings/clock/imx8qxp-lpcg.txt b/Bindings/clock/imx8qxp-lpcg.txt deleted file mode 100644 index 965cfa42e025..000000000000 --- a/Bindings/clock/imx8qxp-lpcg.txt +++ /dev/null @@ -1,51 +0,0 @@ -* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings - -The Low-Power Clock Gate (LPCG) modules contain a local programming -model to control the clock gates for the peripherals. An LPCG module -is used to locally gate the clocks for the associated peripheral. - -Note: -This level of clock gating is provided after the clocks are generated -by the SCU resources and clock controls. Thus even if the clock is -enabled by these control bits, it might still not be running based -on the base resource. - -Required properties: -- compatible: Should be one of: - "fsl,imx8qxp-lpcg-adma", - "fsl,imx8qxp-lpcg-conn", - "fsl,imx8qxp-lpcg-dc", - "fsl,imx8qxp-lpcg-dsp", - "fsl,imx8qxp-lpcg-gpu", - "fsl,imx8qxp-lpcg-hsio", - "fsl,imx8qxp-lpcg-img", - "fsl,imx8qxp-lpcg-lsio", - "fsl,imx8qxp-lpcg-vpu" -- reg: Address and length of the register set -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock by having the clock -ID in its "clocks" phandle cell. -See the full list of clock IDs from: -include/dt-bindings/clock/imx8qxp-clock.h - -Examples: - -#include - -conn_lpcg: clock-controller@5b200000 { - compatible = "fsl,imx8qxp-lpcg-conn"; - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; -}; - -usdhc1: mmc@5b010000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupt-parent = <&gic>; - interrupts = ; - reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; - clock-names = "ipg", "per", "ahb"; -}; diff --git a/Bindings/clock/imx8qxp-lpcg.yaml b/Bindings/clock/imx8qxp-lpcg.yaml new file mode 100644 index 000000000000..33f3010f48c3 --- /dev/null +++ b/Bindings/clock/imx8qxp-lpcg.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings + +maintainers: + - Aisheng Dong + +description: | + The Low-Power Clock Gate (LPCG) modules contain a local programming + model to control the clock gates for the peripherals. An LPCG module + is used to locally gate the clocks for the associated peripheral. + + This level of clock gating is provided after the clocks are generated + by the SCU resources and clock controls. Thus even if the clock is + enabled by these control bits, it might still not be running based + on the base resource. + + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See the full list of clock IDs from: + include/dt-bindings/clock/imx8-clock.h + +properties: + compatible: + enum: + - fsl,imx8qxp-lpcg-adma + - fsl,imx8qxp-lpcg-conn + - fsl,imx8qxp-lpcg-dc + - fsl,imx8qxp-lpcg-dsp + - fsl,imx8qxp-lpcg-gpu + - fsl,imx8qxp-lpcg-hsio + - fsl,imx8qxp-lpcg-img + - fsl,imx8qxp-lpcg-lsio + - fsl,imx8qxp-lpcg-vpu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + + clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg-conn"; + reg = <0x5b200000 0xb0000>; + #clock-cells = <1>; + }; + + mmc@5b010000 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; + interrupts = ; + reg = <0x5b010000 0x10000>; + clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; + clock-names = "ipg", "per", "ahb"; + power-domains = <&pd IMX_SC_R_SDHC_0>; + }; diff --git a/Bindings/clock/ingenic,cgu.txt b/Bindings/clock/ingenic,cgu.txt deleted file mode 100644 index 75598e655067..000000000000 --- a/Bindings/clock/ingenic,cgu.txt +++ /dev/null @@ -1,57 +0,0 @@ -Ingenic SoC CGU binding - -The CGU in an Ingenic SoC provides all the clocks generated on-chip. It -typically includes a variety of PLLs, multiplexers, dividers & gates in order -to provide many different clock signals derived from only 2 external source -clocks. - -Required properties: -- compatible : Should be one of: - * ingenic,jz4740-cgu - * ingenic,jz4725b-cgu - * ingenic,jz4770-cgu - * ingenic,jz4780-cgu - * ingenic,x1000-cgu -- reg : The address & length of the CGU registers. -- clocks : List of phandle & clock specifiers for clocks external to the CGU. - Two such external clocks should be specified - first the external crystal - "ext" and second the RTC clock source "rtc". -- clock-names : List of name strings for the external clocks. -- #clock-cells: Should be 1. - Clock consumers specify this argument to identify a clock. The valid values - may be found in -cgu.h>. - -Example SoC include file: - -/ { - cgu: jz4740-cgu { - compatible = "ingenic,jz4740-cgu"; - reg = <0x10000000 0x100>; - #clock-cells = <1>; - }; - - uart0: serial@10030000 { - clocks = <&cgu JZ4740_CLK_UART0>; - }; -}; - -Example board file: - -/ { - ext: clock@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <12000000>; - }; - - rtc: clock@1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - &cgu { - clocks = <&ext> <&rtc>; - clock-names: "ext", "rtc"; - }; -}; diff --git a/Bindings/clock/ingenic,cgu.yaml b/Bindings/clock/ingenic,cgu.yaml new file mode 100644 index 000000000000..a952d5811823 --- /dev/null +++ b/Bindings/clock/ingenic,cgu.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ingenic,cgu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs CGU devicetree bindings + +description: | + The CGU in an Ingenic SoC provides all the clocks generated on-chip. It + typically includes a variety of PLLs, multiplexers, dividers & gates in order + to provide many different clock signals derived from only 2 external source + clocks. + +maintainers: + - Paul Cercueil + +select: + properties: + compatible: + contains: + enum: + - ingenic,jz4740-cgu + - ingenic,jz4725b-cgu + - ingenic,jz4770-cgu + - ingenic,jz4780-cgu + - ingenic,x1000-cgu + - ingenic,x1830-cgu + required: + - compatible + +properties: + $nodename: + pattern: "^clock-controller@[0-9a-f]+$" + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + "#clock-cells": + const: 1 + + ranges: true + + compatible: + items: + - enum: + - ingenic,jz4740-cgu + - ingenic,jz4725b-cgu + - ingenic,jz4770-cgu + - ingenic,jz4780-cgu + - ingenic,x1000-cgu + - ingenic,x1830-cgu + - const: simple-mfd + minItems: 1 + + reg: + maxItems: 1 + + clocks: + items: + - description: External oscillator clock + - description: Internal 32 kHz RTC clock + + clock-names: + items: + - const: ext + - enum: + - rtc + - osc32k # Different name, same clock + + assigned-clocks: + minItems: 1 + maxItems: 64 + + assigned-clock-parents: + minItems: 1 + maxItems: 64 + + assigned-clock-rates: + minItems: 1 + maxItems: 64 + +required: + - "#clock-cells" + - compatible + - reg + - clocks + - clock-names + +patternProperties: + "^usb-phy@[a-f0-9]+$": + allOf: [ $ref: "../usb/ingenic,jz4770-phy.yaml#" ] + +additionalProperties: false + +examples: + - | + #include + cgu: clock-controller@10000000 { + compatible = "ingenic,jz4770-cgu", "simple-mfd"; + reg = <0x10000000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000000 0x100>; + + clocks = <&ext>, <&osc32k>; + clock-names = "ext", "osc32k"; + + #clock-cells = <1>; + + otg_phy: usb-phy@3c { + compatible = "ingenic,jz4770-phy"; + reg = <0x3c 0x10>; + + clocks = <&cgu JZ4770_CLK_OTG_PHY>; + + vcc-supply = <&ldo5>; + + #phy-cells = <0>; + }; + }; diff --git a/Bindings/clock/intel,agilex.yaml b/Bindings/clock/intel,agilex.yaml new file mode 100644 index 000000000000..cf5a9eb803e6 --- /dev/null +++ b/Bindings/clock/intel,agilex.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,agilex.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA Agilex platform clock controller binding + +maintainers: + - Dinh Nguyen + +description: + The Intel Agilex Clock controller is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + const: intel,agilex-clkmgr + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock controller node: + - | + clkmgr: clock-controller@ffd10000 { + compatible = "intel,agilex-clkmgr"; + reg = <0xffd10000 0x1000>; + clocks = <&osc1>; + #clock-cells = <1>; + }; +... diff --git a/Bindings/clock/intel,cgu-lgm.yaml b/Bindings/clock/intel,cgu-lgm.yaml new file mode 100644 index 000000000000..6dc1414bfb7f --- /dev/null +++ b/Bindings/clock/intel,cgu-lgm.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Lightning Mountain SoC's Clock Controller(CGU) Binding + +maintainers: + - Rahul Tanwar + +description: | + Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides + all means to access the CGU hardware module in order to generate a series + of clocks for the whole system and individual peripherals. + + Please refer to include/dt-bindings/clock/intel,lgm-clk.h header file, it + defines all available clocks as macros. These macros can be used in device + tree sources. + +properties: + compatible: + const: intel,cgu-lgm + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +examples: + - | + cgu: clock-controller@e0200000 { + compatible = "intel,cgu-lgm"; + reg = <0xe0200000 0x33c>; + #clock-cells = <1>; + }; + +... diff --git a/Bindings/clock/marvell,mmp2-audio-clock.yaml b/Bindings/clock/marvell,mmp2-audio-clock.yaml new file mode 100644 index 000000000000..dffa73402da9 --- /dev/null +++ b/Bindings/clock/marvell,mmp2-audio-clock.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,mmp2-audio-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MMP2 Audio Clock Controller + +maintainers: + - Lubomir Rintel + +description: | + The audio clock controller generates and supplies the clocks to the audio + codec. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in + . + +properties: + compatible: + enum: + - marvell,mmp2-audio-clock + + reg: + maxItems: 1 + + clocks: + items: + - description: Audio subsystem clock + - description: The crystal oscillator clock + - description: First I2S clock + - description: Second I2S clock + + clock-names: + items: + - const: audio + - const: vctcxo + - const: i2s0 + - const: i2s1 + + '#clock-cells': + const: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + + clock-controller@d42a0c30 { + compatible = "marvell,mmp2-audio-clock"; + reg = <0xd42a0c30 0x10>; + clock-names = "audio", "vctcxo", "i2s0", "i2s1"; + clocks = <&soc_clocks MMP2_CLK_AUDIO>, + <&soc_clocks MMP2_CLK_VCTCXO>, + <&soc_clocks MMP2_CLK_I2S0>, + <&soc_clocks MMP2_CLK_I2S1>; + power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>; + #clock-cells = <1>; + }; diff --git a/Bindings/clock/marvell,mmp2-clock.yaml b/Bindings/clock/marvell,mmp2-clock.yaml index e2b6ac96bbcb..d68f0d196e7d 100644 --- a/Bindings/clock/marvell,mmp2-clock.yaml +++ b/Bindings/clock/marvell,mmp2-clock.yaml @@ -42,12 +42,16 @@ properties: '#reset-cells': const: 1 + '#power-domain-cells': + const: 1 + required: - compatible - reg - reg-names - '#clock-cells' - '#reset-cells' + - '#power-domain-cells' additionalProperties: false @@ -61,4 +65,5 @@ examples: reg-names = "mpmu", "apmu", "apbc"; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; diff --git a/Bindings/clock/qcom,a53pll.txt b/Bindings/clock/qcom,a53pll.txt deleted file mode 100644 index e3fa8118eaee..000000000000 --- a/Bindings/clock/qcom,a53pll.txt +++ /dev/null @@ -1,22 +0,0 @@ -Qualcomm MSM8916 A53 PLL Binding --------------------------------- -The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies -above 1GHz. - -Required properties : -- compatible : Shall contain only one of the following: - - "qcom,msm8916-a53pll" - -- reg : shall contain base register location and length - -- #clock-cells : must be set to <0> - -Example: - - a53pll: clock@b016000 { - compatible = "qcom,msm8916-a53pll"; - reg = <0xb016000 0x40>; - #clock-cells = <0>; - }; - diff --git a/Bindings/clock/qcom,a53pll.yaml b/Bindings/clock/qcom,a53pll.yaml new file mode 100644 index 000000000000..20d2638b4cd2 --- /dev/null +++ b/Bindings/clock/qcom,a53pll.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,a53pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm A53 PLL Binding + +maintainers: + - Sivaprakash Murugesan + +description: + The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for + frequencies above 1GHz. + +properties: + compatible: + const: qcom,msm8916-a53pll + + reg: + maxItems: 1 + + '#clock-cells': + const: 0 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + #Example 1 - A53 PLL found on MSM8916 devices + - | + a53pll: clock@b016000 { + compatible = "qcom,msm8916-a53pll"; + reg = <0xb016000 0x40>; + #clock-cells = <0>; + }; diff --git a/Bindings/clock/qcom,gcc-sc7180.yaml b/Bindings/clock/qcom,gcc-sc7180.yaml index a345320e0e49..a404c8fbee67 100644 --- a/Bindings/clock/qcom,gcc-sc7180.yaml +++ b/Bindings/clock/qcom,gcc-sc7180.yaml @@ -65,7 +65,7 @@ examples: #include clock-controller@100000 { compatible = "qcom,gcc-sc7180"; - reg = <0 0x00100000 0 0x1f0000>; + reg = <0x00100000 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; diff --git a/Bindings/clock/qcom,gcc-sm8150.yaml b/Bindings/clock/qcom,gcc-sm8150.yaml index 36f3b3668ced..12766a866625 100644 --- a/Bindings/clock/qcom,gcc-sm8150.yaml +++ b/Bindings/clock/qcom,gcc-sm8150.yaml @@ -63,7 +63,7 @@ examples: #include clock-controller@100000 { compatible = "qcom,gcc-sm8150"; - reg = <0 0x00100000 0 0x1f0000>; + reg = <0x00100000 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; diff --git a/Bindings/clock/qcom,gcc-sm8250.yaml b/Bindings/clock/qcom,gcc-sm8250.yaml index 2c40a8aa9815..a5766ff89082 100644 --- a/Bindings/clock/qcom,gcc-sm8250.yaml +++ b/Bindings/clock/qcom,gcc-sm8250.yaml @@ -61,7 +61,7 @@ examples: #include clock-controller@100000 { compatible = "qcom,gcc-sm8250"; - reg = <0 0x00100000 0 0x1f0000>; + reg = <0x00100000 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; clock-names = "bi_tcxo", "sleep_clk"; diff --git a/Bindings/clock/qcom,gcc.yaml b/Bindings/clock/qcom,gcc.yaml index e533bb0cfd2b..ee0467fb5e31 100644 --- a/Bindings/clock/qcom,gcc.yaml +++ b/Bindings/clock/qcom,gcc.yaml @@ -22,6 +22,8 @@ description: | - dt-bindings/reset/qcom,gcc-ipq6018.h - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) + - dt-bindings/clock/qcom,gcc-msm8939.h + - dt-bindings/reset/qcom,gcc-msm8939.h - dt-bindings/clock/qcom,gcc-msm8660.h - dt-bindings/reset/qcom,gcc-msm8660.h - dt-bindings/clock/qcom,gcc-msm8974.h @@ -41,6 +43,7 @@ properties: - qcom,gcc-ipq8064 - qcom,gcc-msm8660 - qcom,gcc-msm8916 + - qcom,gcc-msm8939 - qcom,gcc-msm8960 - qcom,gcc-msm8974 - qcom,gcc-msm8974pro diff --git a/Bindings/clock/qcom,mmcc.yaml b/Bindings/clock/qcom,mmcc.yaml index f684fe67db84..1b16a863b355 100644 --- a/Bindings/clock/qcom,mmcc.yaml +++ b/Bindings/clock/qcom,mmcc.yaml @@ -15,15 +15,15 @@ description: | power domains. properties: - compatible : + compatible: enum: - - qcom,mmcc-apq8064 - - qcom,mmcc-apq8084 - - qcom,mmcc-msm8660 - - qcom,mmcc-msm8960 - - qcom,mmcc-msm8974 - - qcom,mmcc-msm8996 - - qcom,mmcc-msm8998 + - qcom,mmcc-apq8064 + - qcom,mmcc-apq8084 + - qcom,mmcc-msm8660 + - qcom,mmcc-msm8960 + - qcom,mmcc-msm8974 + - qcom,mmcc-msm8996 + - qcom,mmcc-msm8998 clocks: items: @@ -67,6 +67,10 @@ properties: description: Protected clock specifier list as per common clock binding + vdd-gfx-supply: + description: + Regulator supply for the GPU_GX GDSC + required: - compatible - reg diff --git a/Bindings/clock/qcom,sc7180-dispcc.yaml b/Bindings/clock/qcom,sc7180-dispcc.yaml index 58cdfd5924d3..e94847f92770 100644 --- a/Bindings/clock/qcom,sc7180-dispcc.yaml +++ b/Bindings/clock/qcom,sc7180-dispcc.yaml @@ -66,7 +66,7 @@ examples: #include clock-controller@af00000 { compatible = "qcom,sc7180-dispcc"; - reg = <0 0x0af00000 0 0x200000>; + reg = <0x0af00000 0x200000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&dsi_phy 0>, diff --git a/Bindings/clock/qcom,sc7180-gpucc.yaml b/Bindings/clock/qcom,sc7180-gpucc.yaml index 8635e35fd3f0..fe08461fce05 100644 --- a/Bindings/clock/qcom,sc7180-gpucc.yaml +++ b/Bindings/clock/qcom,sc7180-gpucc.yaml @@ -60,7 +60,7 @@ examples: #include clock-controller@5090000 { compatible = "qcom,sc7180-gpucc"; - reg = <0 0x05090000 0 0x9000>; + reg = <0x05090000 0x9000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; diff --git a/Bindings/clock/qcom,sc7180-mss.yaml b/Bindings/clock/qcom,sc7180-mss.yaml index 0dd5d25ae7d7..970030986a86 100644 --- a/Bindings/clock/qcom,sc7180-mss.yaml +++ b/Bindings/clock/qcom,sc7180-mss.yaml @@ -50,7 +50,7 @@ examples: #include clock-controller@41a8000 { compatible = "qcom,sc7180-mss"; - reg = <0 0x041a8000 0 0x8000>; + reg = <0x041a8000 0x8000>; clocks = <&gcc GCC_MSS_MFAB_AXIS_CLK>, <&gcc GCC_MSS_NAV_AXI_CLK>, <&gcc GCC_MSS_CFG_AHB_CLK>; diff --git a/Bindings/clock/qcom,sc7180-videocc.yaml b/Bindings/clock/qcom,sc7180-videocc.yaml index 0071b9701960..2feea2b91aa9 100644 --- a/Bindings/clock/qcom,sc7180-videocc.yaml +++ b/Bindings/clock/qcom,sc7180-videocc.yaml @@ -55,7 +55,7 @@ examples: #include clock-controller@ab00000 { compatible = "qcom,sc7180-videocc"; - reg = <0 0x0ab00000 0 0x10000>; + reg = <0x0ab00000 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; #clock-cells = <1>; diff --git a/Bindings/clock/qcom,sdm845-dispcc.yaml b/Bindings/clock/qcom,sdm845-dispcc.yaml index ad47d747a3e4..4a3be733d042 100644 --- a/Bindings/clock/qcom,sdm845-dispcc.yaml +++ b/Bindings/clock/qcom,sdm845-dispcc.yaml @@ -75,7 +75,7 @@ examples: #include clock-controller@af00000 { compatible = "qcom,sdm845-dispcc"; - reg = <0 0x0af00000 0 0x10000>; + reg = <0x0af00000 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, diff --git a/Bindings/clock/qcom,sdm845-gpucc.yaml b/Bindings/clock/qcom,sdm845-gpucc.yaml index 7a052ac5dc00..8a0c576ba8b3 100644 --- a/Bindings/clock/qcom,sdm845-gpucc.yaml +++ b/Bindings/clock/qcom,sdm845-gpucc.yaml @@ -60,7 +60,7 @@ examples: #include clock-controller@5090000 { compatible = "qcom,sdm845-gpucc"; - reg = <0 0x05090000 0 0x9000>; + reg = <0x05090000 0x9000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; diff --git a/Bindings/clock/qcom,sdm845-videocc.yaml b/Bindings/clock/qcom,sdm845-videocc.yaml index 2a6a81ab0318..f7a0cf53d5f0 100644 --- a/Bindings/clock/qcom,sdm845-videocc.yaml +++ b/Bindings/clock/qcom,sdm845-videocc.yaml @@ -55,7 +55,7 @@ examples: #include clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; - reg = <0 0x0ab00000 0 0x10000>; + reg = <0x0ab00000 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "bi_tcxo"; #clock-cells = <1>; diff --git a/Bindings/clock/renesas,cpg-div6-clock.yaml b/Bindings/clock/renesas,cpg-div6-clock.yaml new file mode 100644 index 000000000000..c55a7c494e01 --- /dev/null +++ b/Bindings/clock/renesas,cpg-div6-clock.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas CPG DIV6 Clock + +maintainers: + - Geert Uytterhoeven + +description: + The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse + Generator (CPG). Their clock input is divided by a configurable factor from 1 + to 64. + +properties: + compatible: + items: + - enum: + - renesas,r8a73a4-div6-clock # R-Mobile APE6 + - renesas,r8a7740-div6-clock # R-Mobile A1 + - renesas,sh73a0-div6-clock # SH-Mobile AG5 + - const: renesas,cpg-div6-clock + + reg: + maxItems: 1 + + clocks: + oneOf: + - maxItems: 1 + - maxItems: 4 + - maxItems: 8 + description: + For clocks with multiple parents, invalid settings must be specified as + "<0>". + + '#clock-cells': + const: 0 + + clock-output-names: true + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + sdhi2_clk: sdhi2_clk@e615007c { + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe615007c 4>; + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, + <&extal2_clk>; + #clock-cells = <0>; + }; diff --git a/Bindings/clock/renesas,cpg-div6-clocks.txt b/Bindings/clock/renesas,cpg-div6-clocks.txt deleted file mode 100644 index ae36ab842919..000000000000 --- a/Bindings/clock/renesas,cpg-div6-clocks.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Renesas CPG DIV6 Clock - -The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse -Generator (CPG). Their clock input is divided by a configurable factor from 1 -to 64. - -Required Properties: - - - compatible: Must be one of the following - - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks - - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks - - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks - - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks - - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks - - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks - - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks - and "renesas,cpg-div6-clock" as a fallback. - - reg: Base address and length of the memory resource used by the DIV6 clock - - clocks: Reference to the parent clock(s); either one, four, or eight - clocks must be specified. For clocks with multiple parents, invalid - settings must be specified as "<0>". - - #clock-cells: Must be 0 - - -Optional Properties: - - - clock-output-names: The name of the clock as a free-form string - - -Example -------- - - sdhi2_clk: sdhi2_clk@e615007c { - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615007c 0 4>; - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, - <0>, <&extal2_clk>; - #clock-cells = <0>; - clock-output-names = "sdhi2ck"; - }; diff --git a/Bindings/clock/renesas,cpg-mssr.yaml b/Bindings/clock/renesas,cpg-mssr.yaml index 9cd102e5fed5..c745bd60719a 100644 --- a/Bindings/clock/renesas,cpg-mssr.yaml +++ b/Bindings/clock/renesas,cpg-mssr.yaml @@ -25,6 +25,7 @@ properties: compatible: enum: - renesas,r7s9210-cpg-mssr # RZ/A2 + - renesas,r8a7742-cpg-mssr # RZ/G1H - renesas,r8a7743-cpg-mssr # RZ/G1M - renesas,r8a7744-cpg-mssr # RZ/G1N - renesas,r8a7745-cpg-mssr # RZ/G1E diff --git a/Bindings/clock/renesas,cpg-mstp-clocks.txt b/Bindings/clock/renesas,cpg-mstp-clocks.txt deleted file mode 100644 index da578ebdda28..000000000000 --- a/Bindings/clock/renesas,cpg-mstp-clocks.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Renesas CPG Module Stop (MSTP) Clocks - -The CPG can gate SoC device clocks. The gates are organized in groups of up to -32 gates. - -This device tree binding describes a single 32 gate clocks group per node. -Clocks are referenced by user nodes by the MSTP node phandle and the clock -index in the group, from 0 to 31. - -Required Properties: - - - compatible: Must be one of the following - - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks - - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks - - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks - - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks - - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks - - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks - - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks - - "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks - - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks - - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks - - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks - and "renesas,cpg-mstp-clocks" as a fallback. - - reg: Base address and length of the I/O mapped registers used by the MSTP - clocks. The first register is the clock control register and is mandatory. - The second register is the clock status register and is optional when not - implemented in hardware. - - clocks: Reference to the parent clocks, one per output clock. The parents - must appear in the same order as the output clocks. - - #clock-cells: Must be 1 - - clock-output-names: The name of the clocks as free-form strings - - clock-indices: Indices of the gate clocks into the group (0 to 31) - -The clocks, clock-output-names and clock-indices properties contain one entry -per gate clock. The MSTP groups are sparsely populated. Unimplemented gate -clocks must not be declared. - - -Example -------- - - #include - - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, - <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, - <&mmc0_clk>; - #clock-cells = <1>; - clock-output-names = - "tpu0", "mmcif1", "sdhi3", "sdhi2", - "sdhi1", "sdhi0", "mmcif0"; - clock-indices = < - R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 - R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 - R8A7790_CLK_MMCIF0 - >; - }; diff --git a/Bindings/clock/renesas,cpg-mstp-clocks.yaml b/Bindings/clock/renesas,cpg-mstp-clocks.yaml new file mode 100644 index 000000000000..9752ac63288b --- /dev/null +++ b/Bindings/clock/renesas,cpg-mstp-clocks.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks + +maintainers: + - Geert Uytterhoeven + +description: + The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are + organized in groups of up to 32 gates. + + This device tree binding describes a single 32 gate clocks group per node. + Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle + and the clock index in the group, from 0 to 31. + +properties: + compatible: + items: + - enum: + - renesas,r7s72100-mstp-clocks # RZ/A1 + - renesas,r8a73a4-mstp-clocks # R-Mobile APE6 + - renesas,r8a7740-mstp-clocks # R-Mobile A1 + - renesas,r8a7778-mstp-clocks # R-Car M1 + - renesas,r8a7779-mstp-clocks # R-Car H1 + - renesas,sh73a0-mstp-clocks # SH-Mobile AG5 + - const: renesas,cpg-mstp-clocks + + reg: + minItems: 1 + items: + - description: Module Stop Control Register (MSTPCR) + - description: Module Stop Status Register (MSTPSR) + + clocks: + minItems: 1 + maxItems: 32 + + '#clock-cells': + const: 1 + + clock-indices: + minItems: 1 + maxItems: 32 + + clock-output-names: + minItems: 1 + maxItems: 32 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - clock-indices + - clock-output-names + +additionalProperties: false + +examples: + - | + #include + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a73a4-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0xe6150138 4>, <0xe6150040 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; + #clock-cells = <1>; + clock-indices = < + R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 + R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 + R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 + R8A73A4_CLK_DMAC + >; + clock-output-names = + "scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3", + "dmac"; + }; diff --git a/Bindings/clock/renesas,rcar-usb2-clock-sel.txt b/Bindings/clock/renesas,rcar-usb2-clock-sel.txt index 4bf6f53bd95e..da92f5748dee 100644 --- a/Bindings/clock/renesas,rcar-usb2-clock-sel.txt +++ b/Bindings/clock/renesas,rcar-usb2-clock-sel.txt @@ -27,7 +27,9 @@ Required properties: - compatible: "renesas,r8a7795-rcar-usb2-clock-sel" if the device is a part of an R8A7795 SoC. "renesas,r8a7796-rcar-usb2-clock-sel" if the device if a part of - an R8A7796 SoC. + an R8A77960 SoC. + "renesas,r8a77961-rcar-usb2-clock-sel" if the device if a part of + an R8A77961 SoC. "renesas,rcar-gen3-usb2-clock-sel" for a generic R-Car Gen3 compatible device. diff --git a/Bindings/clock/silabs,si5341.txt b/Bindings/clock/silabs,si5341.txt index a70c333e4cd4..504cce3abe46 100644 --- a/Bindings/clock/silabs,si5341.txt +++ b/Bindings/clock/silabs,si5341.txt @@ -1,15 +1,21 @@ -Binding for Silicon Labs Si5341 and Si5340 programmable i2c clock generator. +Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable +i2c clock generator. Reference [1] Si5341 Data Sheet https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf [2] Si5341 Reference Manual https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf +[3] Si5345 Reference Manual + https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which in turn can be directed to any of the 10 (or 4) outputs through a divider. The internal structure of the clock generators can be found in [2]. +The Si5345 is similar to the Si5341 with the addition of fractional input +dividers and automatic input selection, as described in [3]. +The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs. The driver can be used in "as is" mode, reading the current settings from the chip at boot, in case you have a (pre-)programmed device. If the PLL is not @@ -28,6 +34,9 @@ Required properties: - compatible: shall be one of the following: "silabs,si5340" - Si5340 A/B/C/D "silabs,si5341" - Si5341 A/B/C/D + "silabs,si5342" - Si5342 A/B/C/D + "silabs,si5344" - Si5344 A/B/C/D + "silabs,si5345" - Si5345 A/B/C/D - reg: i2c device address, usually 0x74 - #clock-cells: from common clock binding; shall be set to 2. The first value is "0" for outputs, "1" for synthesizers. diff --git a/Bindings/clock/sprd,sc9863a-clk.yaml b/Bindings/clock/sprd,sc9863a-clk.yaml index bb3a78d8105e..29813873cfbc 100644 --- a/Bindings/clock/sprd,sc9863a-clk.yaml +++ b/Bindings/clock/sprd,sc9863a-clk.yaml @@ -28,6 +28,7 @@ properties: - sprd,sc9863a-rpll - sprd,sc9863a-dpll - sprd,sc9863a-mm-gate + - sprd,sc9863a-mm-clk - sprd,sc9863a-apapb-gate clocks: @@ -76,29 +77,24 @@ examples: - | ap_clk: clock-controller@21500000 { compatible = "sprd,sc9863a-ap-clk"; - reg = <0 0x21500000 0 0x1000>; + reg = <0x21500000 0x1000>; clocks = <&ext_26m>, <&ext_32k>; clock-names = "ext-26m", "ext-32k"; #clock-cells = <1>; }; - | - soc { - #address-cells = <2>; - #size-cells = <2>; + syscon@20e00000 { + compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd"; + reg = <0x20e00000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x20e00000 0x4000>; - ap_ahb_regs: syscon@20e00000 { - compatible = "sprd,sc9863a-glbregs", "syscon", "simple-mfd"; - reg = <0 0x20e00000 0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x20e00000 0x4000>; - - apahb_gate: apahb-gate@0 { - compatible = "sprd,sc9863a-apahb-gate"; - reg = <0x0 0x1020>; - #clock-cells = <1>; - }; + apahb_gate: apahb-gate@0 { + compatible = "sprd,sc9863a-apahb-gate"; + reg = <0x0 0x1020>; + #clock-cells = <1>; }; }; diff --git a/Bindings/connector/usb-connector.yaml b/Bindings/connector/usb-connector.yaml index 4638d7adb806..9bd52e63c935 100644 --- a/Bindings/connector/usb-connector.yaml +++ b/Bindings/connector/usb-connector.yaml @@ -15,10 +15,15 @@ description: properties: compatible: - enum: - - usb-a-connector - - usb-b-connector - - usb-c-connector + oneOf: + - enum: + - usb-a-connector + - usb-b-connector + - usb-c-connector + + - items: + - const: gpio-usb-b-connector + - const: usb-b-connector label: description: Symbolic name for the connector. @@ -27,8 +32,8 @@ properties: description: Size of the connector, should be specified in case of non-fullsize 'usb-a-connector' or 'usb-b-connector' compatible connectors. - allOf: - - $ref: /schemas/types.yaml#definitions/string + $ref: /schemas/types.yaml#definitions/string + enum: - mini - micro @@ -57,8 +62,8 @@ properties: power-role: description: Determines the power role that the Type C connector will support. "dual" refers to Dual Role Port (DRP). - allOf: - - $ref: /schemas/types.yaml#definitions/string + $ref: /schemas/types.yaml#definitions/string + enum: - source - sink @@ -66,18 +71,18 @@ properties: try-power-role: description: Preferred power role. - allOf: - - $ref: /schemas/types.yaml#definitions/string + $ref: /schemas/types.yaml#definitions/string + enum: - - source - - sink - - dual + - source + - sink + - dual data-role: description: Data role if Type C connector supports USB data. "dual" refers Dual Role Device (DRD). - allOf: - - $ref: /schemas/types.yaml#definitions/string + $ref: /schemas/types.yaml#definitions/string + enum: - host - device @@ -95,8 +100,7 @@ properties: defined in dt-bindings/usb/pd.h. minItems: 1 maxItems: 7 - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array sink-pdos: description: An array of u32 with each entry providing supported power sink @@ -108,8 +112,7 @@ properties: in dt-bindings/usb/pd.h. minItems: 1 maxItems: 7 - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array op-sink-microwatt: description: Sink required operating power in microwatt, if source can't @@ -142,9 +145,22 @@ properties: required: - compatible +allOf: + - if: + properties: + compatible: + contains: + const: gpio-usb-b-connector + then: + anyOf: + - required: + - vbus-gpios + - required: + - id-gpios + examples: # Micro-USB connector with HS lines routed via controller (MUIC). - - |+ + - | muic-max77843 { usb_con1: connector { compatible = "usb-b-connector"; @@ -156,7 +172,7 @@ examples: # USB-C connector attached to CC controller (s2mm005), HS lines routed # to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort. # DisplayPort video lines are routed to the connector via SS mux in USB3 PHY. - - |+ + - | ccic: s2mm005 { usb_con2: connector { compatible = "usb-c-connector"; @@ -190,7 +206,7 @@ examples: # USB-C connector attached to a typec port controller(ptn5110), which has # power delivery support and enables drp. - - |+ + - | #include typec: ptn5110 { usb_con3: connector { @@ -204,3 +220,16 @@ examples: op-sink-microwatt = <10000000>; }; }; + + # USB connector with GPIO control lines + - | + #include + + usb { + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb_p0_vbus>; + }; + }; diff --git a/Bindings/cpufreq/nvidia,tegra20-cpufreq.txt b/Bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file mode 100644 index 000000000000..daeca6ae6b76 --- /dev/null +++ b/Bindings/cpufreq/nvidia,tegra20-cpufreq.txt @@ -0,0 +1,56 @@ +Binding for NVIDIA Tegra20 CPUFreq +================================== + +Required properties: +- clocks: Must contain an entry for the CPU clock. + See ../clocks/clock-bindings.txt for details. +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: Two bitfields indicating: + On Tegra20: + 1. CPU process ID mask + 2. SoC speedo ID mask + + On Tegra30: + 1. CPU process ID mask + 2. CPU speedo ID mask + + A bitwise AND is performed against these values and if any bit + matches, the OPP gets enabled. + +- opp-microvolt: CPU voltage triplet. + +Optional properties: +- cpu-supply: Phandle to the CPU power supply. + +Example: + regulators { + cpu_reg: regulator0 { + regulator-name = "vdd_cpu"; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@456000000 { + clock-latency-ns = <125000>; + opp-microvolt = <825000 825000 1125000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <456000000>; + }; + + ... + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&cpu_reg>; + #cooling-cells = <2>; + }; + }; diff --git a/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml b/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml index 8b9a8f337f16..fc823572bcff 100644 --- a/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml +++ b/Bindings/crypto/allwinner,sun4i-a10-crypto.yaml @@ -15,16 +15,16 @@ properties: oneOf: - const: allwinner,sun4i-a10-crypto - items: - - const: allwinner,sun5i-a13-crypto - - const: allwinner,sun4i-a10-crypto + - const: allwinner,sun5i-a13-crypto + - const: allwinner,sun4i-a10-crypto - items: - - const: allwinner,sun6i-a31-crypto - - const: allwinner,sun4i-a10-crypto + - const: allwinner,sun6i-a31-crypto + - const: allwinner,sun4i-a10-crypto - items: - - const: allwinner,sun7i-a20-crypto - - const: allwinner,sun4i-a10-crypto + - const: allwinner,sun7i-a20-crypto + - const: allwinner,sun4i-a10-crypto - items: - - const: allwinner,sun8i-a33-crypto + - const: allwinner,sun8i-a33-crypto reg: maxItems: 1 diff --git a/Bindings/crypto/allwinner,sun8i-ce.yaml b/Bindings/crypto/allwinner,sun8i-ce.yaml index 2c459b8c76ff..7a60d84289cc 100644 --- a/Bindings/crypto/allwinner,sun8i-ce.yaml +++ b/Bindings/crypto/allwinner,sun8i-ce.yaml @@ -50,16 +50,16 @@ if: const: allwinner,sun50i-h6-crypto then: properties: - clocks: - minItems: 3 - clock-names: - minItems: 3 + clocks: + minItems: 3 + clock-names: + minItems: 3 else: properties: - clocks: - maxItems: 2 - clock-names: - maxItems: 2 + clocks: + maxItems: 2 + clock-names: + maxItems: 2 required: - compatible diff --git a/Bindings/crypto/amlogic,gxl-crypto.yaml b/Bindings/crypto/amlogic,gxl-crypto.yaml index 5becc60a0e28..ecf98a9e72b2 100644 --- a/Bindings/crypto/amlogic,gxl-crypto.yaml +++ b/Bindings/crypto/amlogic,gxl-crypto.yaml @@ -12,7 +12,7 @@ maintainers: properties: compatible: items: - - const: amlogic,gxl-crypto + - const: amlogic,gxl-crypto reg: maxItems: 1 @@ -45,7 +45,7 @@ examples: crypto: crypto-engine@c883e000 { compatible = "amlogic,gxl-crypto"; - reg = <0x0 0xc883e000 0x0 0x36>; + reg = <0xc883e000 0x36>; interrupts = , ; clocks = <&clkc CLKID_BLKMV>; clock-names = "blkmv"; diff --git a/Bindings/crypto/st,stm32-hash.yaml b/Bindings/crypto/st,stm32-hash.yaml index 57ae1c0b6d18..6dd658f0912c 100644 --- a/Bindings/crypto/st,stm32-hash.yaml +++ b/Bindings/crypto/st,stm32-hash.yaml @@ -36,11 +36,10 @@ properties: dma-maxburst: description: Set number of maximum dma burst supported - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - - maximum: 2 - - default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 2 + default: 0 required: - compatible diff --git a/Bindings/display/allwinner,sun4i-a10-display-engine.yaml b/Bindings/display/allwinner,sun4i-a10-display-engine.yaml index 944ff2f1cf93..e77523b02fad 100644 --- a/Bindings/display/allwinner,sun4i-a10-display-engine.yaml +++ b/Bindings/display/allwinner,sun4i-a10-display-engine.yaml @@ -66,10 +66,9 @@ properties: - allwinner,sun50i-h6-display-engine allwinner,pipelines: - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle-array - - minItems: 1 - maxItems: 2 + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 2 description: | Available display engine frontends (DE 1.0) or mixers (DE 2.0/3.0) available. diff --git a/Bindings/display/allwinner,sun4i-a10-hdmi.yaml b/Bindings/display/allwinner,sun4i-a10-hdmi.yaml index 5d4915aed1e2..75e6479397a5 100644 --- a/Bindings/display/allwinner,sun4i-a10-hdmi.yaml +++ b/Bindings/display/allwinner,sun4i-a10-hdmi.yaml @@ -21,8 +21,8 @@ properties: - const: allwinner,sun5i-a10s-hdmi - const: allwinner,sun6i-a31-hdmi - items: - - const: allwinner,sun7i-a20-hdmi - - const: allwinner,sun5i-a10s-hdmi + - const: allwinner,sun7i-a20-hdmi + - const: allwinner,sun5i-a10s-hdmi reg: maxItems: 1 @@ -33,32 +33,32 @@ properties: clocks: oneOf: - items: - - description: The HDMI interface clock - - description: The HDMI module clock - - description: The first video PLL - - description: The second video PLL + - description: The HDMI interface clock + - description: The HDMI module clock + - description: The first video PLL + - description: The second video PLL - items: - - description: The HDMI interface clock - - description: The HDMI module clock - - description: The HDMI DDC clock - - description: The first video PLL - - description: The second video PLL + - description: The HDMI interface clock + - description: The HDMI module clock + - description: The HDMI DDC clock + - description: The first video PLL + - description: The second video PLL clock-names: oneOf: - items: - - const: ahb - - const: mod - - const: pll-0 - - const: pll-1 + - const: ahb + - const: mod + - const: pll-0 + - const: pll-1 - items: - - const: ahb - - const: mod - - const: ddc - - const: pll-0 - - const: pll-1 + - const: ahb + - const: mod + - const: ddc + - const: pll-0 + - const: pll-1 resets: maxItems: 1 diff --git a/Bindings/display/allwinner,sun4i-a10-tcon.yaml b/Bindings/display/allwinner,sun4i-a10-tcon.yaml index e5344c4ae226..4c15a2644a7c 100644 --- a/Bindings/display/allwinner,sun4i-a10-tcon.yaml +++ b/Bindings/display/allwinner,sun4i-a10-tcon.yaml @@ -35,26 +35,26 @@ properties: - const: allwinner,sun9i-a80-tcon-tv - items: - - enum: - - allwinner,sun7i-a20-tcon0 - - allwinner,sun7i-a20-tcon1 - - const: allwinner,sun7i-a20-tcon + - enum: + - allwinner,sun7i-a20-tcon0 + - allwinner,sun7i-a20-tcon1 + - const: allwinner,sun7i-a20-tcon - items: - - enum: - - allwinner,sun50i-a64-tcon-lcd - - const: allwinner,sun8i-a83t-tcon-lcd + - enum: + - allwinner,sun50i-a64-tcon-lcd + - const: allwinner,sun8i-a83t-tcon-lcd - items: - - enum: - - allwinner,sun8i-h3-tcon-tv - - allwinner,sun50i-a64-tcon-tv - - const: allwinner,sun8i-a83t-tcon-tv + - enum: + - allwinner,sun8i-h3-tcon-tv + - allwinner,sun50i-a64-tcon-tv + - const: allwinner,sun8i-a83t-tcon-tv - items: - - enum: - - allwinner,sun50i-h6-tcon-tv - - const: allwinner,sun8i-r40-tcon-tv + - enum: + - allwinner,sun50i-h6-tcon-tv + - const: allwinner,sun8i-r40-tcon-tv reg: maxItems: 1 @@ -71,11 +71,10 @@ properties: maxItems: 4 clock-output-names: - allOf: - - $ref: /schemas/types.yaml#/definitions/string-array - - maxItems: 1 description: Name of the LCD pixel clock created. + $ref: /schemas/types.yaml#/definitions/string-array + maxItems: 1 dmas: maxItems: 1 @@ -83,37 +82,37 @@ properties: resets: anyOf: - items: - - description: TCON Reset Line + - description: TCON Reset Line - items: - - description: TCON Reset Line - - description: TCON LVDS Reset Line + - description: TCON Reset Line + - description: TCON LVDS Reset Line - items: - - description: TCON Reset Line - - description: TCON eDP Reset Line + - description: TCON Reset Line + - description: TCON eDP Reset Line - items: - - description: TCON Reset Line - - description: TCON eDP Reset Line - - description: TCON LVDS Reset Line + - description: TCON Reset Line + - description: TCON eDP Reset Line + - description: TCON LVDS Reset Line reset-names: oneOf: - const: lcd - items: - - const: lcd - - const: lvds + - const: lcd + - const: lvds - items: - - const: lcd - - const: edp + - const: lcd + - const: edp - items: - - const: lcd - - const: edp - - const: lvds + - const: lcd + - const: edp + - const: lvds ports: type: object diff --git a/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml b/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml index 9e90c2b00960..63f948175239 100644 --- a/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml +++ b/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml @@ -76,28 +76,28 @@ required: allOf: - if: properties: - compatible: - contains: - const: allwinner,sun6i-a31-mipi-dsi + compatible: + contains: + const: allwinner,sun6i-a31-mipi-dsi then: - properties: - clocks: - minItems: 2 + properties: + clocks: + minItems: 2 - required: - - clock-names + required: + - clock-names - if: properties: - compatible: - contains: - const: allwinner,sun50i-a64-mipi-dsi + compatible: + contains: + const: allwinner,sun50i-a64-mipi-dsi then: - properties: - clocks: - minItems: 1 + properties: + clocks: + minItems: 1 additionalProperties: false @@ -119,7 +119,7 @@ examples: panel@0 { compatible = "bananapi,lhr050h41", "ilitek,ili9881c"; reg = <0>; - power-gpios = <&pio 1 7 0>; /* PB07 */ + power-supply = <®_display>; reset-gpios = <&r_pio 0 5 1>; /* PL05 */ backlight = <&pwm_bl>; }; diff --git a/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml index 4d6795690ac3..fa4769a0b26e 100644 --- a/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml +++ b/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml @@ -29,11 +29,11 @@ properties: - const: allwinner,sun50i-h6-dw-hdmi - items: - - enum: - - allwinner,sun8i-h3-dw-hdmi - - allwinner,sun8i-r40-dw-hdmi - - allwinner,sun50i-a64-dw-hdmi - - const: allwinner,sun8i-a83t-dw-hdmi + - enum: + - allwinner,sun8i-h3-dw-hdmi + - allwinner,sun8i-r40-dw-hdmi + - allwinner,sun50i-a64-dw-hdmi + - const: allwinner,sun8i-a83t-dw-hdmi reg: maxItems: 1 diff --git a/Bindings/display/bridge/adi,adv7123.txt b/Bindings/display/bridge/adi,adv7123.txt deleted file mode 100644 index d3c2a4914ea2..000000000000 --- a/Bindings/display/bridge/adi,adv7123.txt +++ /dev/null @@ -1,50 +0,0 @@ -Analog Devices ADV7123 Video DAC --------------------------------- - -The ADV7123 is a digital-to-analog converter that outputs VGA signals from a -parallel video input. - -Required properties: - -- compatible: Should be "adi,adv7123" - -Optional properties: - -- psave-gpios: Power save control GPIO - -Required nodes: - -The ADV7123 has two video ports. Their connections are modeled using the OF -graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for DPI input -- Video port 1 for VGA output - - -Example -------- - - adv7123: encoder@0 { - compatible = "adi,adv7123"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adv7123_in: endpoint@0 { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - adv7123_out: endpoint@0 { - remote-endpoint = <&vga_connector_in>; - }; - }; - }; - }; diff --git a/Bindings/display/bridge/analogix,anx7814.yaml b/Bindings/display/bridge/analogix,anx7814.yaml new file mode 100644 index 000000000000..3ba477aefdd7 --- /dev/null +++ b/Bindings/display/bridge/analogix,anx7814.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/analogix,anx7814.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analogix ANX7814 SlimPort (Full-HD Transmitter) + +maintainers: + - Enric Balletbo i Serra + +properties: + compatible: + enum: + - analogix,anx7808 + - analogix,anx7812 + - analogix,anx7814 + - analogix,anx7818 + + reg: + maxItems: 1 + description: I2C address of the device. + + interrupts: + maxItems: 1 + description: Should contain the INTP interrupt. + + hpd-gpios: + deprecated: true + maxItems: 1 + description: Which GPIO to use for hpd. + + pd-gpios: + maxItems: 1 + description: Which GPIO to use for power down. + + reset-gpios: + maxItems: 1 + description: Which GPIO to use for reset. + + dvdd10-supply: + description: Regulator for 1.0V digital core power. + + ports: + type: object + description: + A node containing input and output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + Documentation/devicetree/bindings/graph.txt + + properties: + port@0: + type: object + description: Video port for HDMI input. + + properties: + reg: + const: 0 + + port@1: + type: object + description: + Video port for SlimPort, DisplayPort, eDP or MyDP output. + + properties: + reg: + const: 1 + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - ports + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + anx7814: bridge@38 { + compatible = "analogix,anx7814"; + reg = <0x38>; + interrupt-parent = <&gpio0>; + interrupts = <99 IRQ_TYPE_LEVEL_LOW>; /* INTP */ + pd-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + anx7814_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + + port@1 { + reg = <1>; + anx7814_out: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + }; + }; + +... diff --git a/Bindings/display/bridge/anx6345.yaml b/Bindings/display/bridge/anx6345.yaml index c21103869923..8c0e4f285fbc 100644 --- a/Bindings/display/bridge/anx6345.yaml +++ b/Bindings/display/bridge/anx6345.yaml @@ -37,6 +37,12 @@ properties: type: object properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + port@0: type: object description: | @@ -51,6 +57,8 @@ properties: required: - port@0 + additionalProperties: false + required: - compatible - reg diff --git a/Bindings/display/bridge/anx7814.txt b/Bindings/display/bridge/anx7814.txt deleted file mode 100644 index 17258747fff6..000000000000 --- a/Bindings/display/bridge/anx7814.txt +++ /dev/null @@ -1,42 +0,0 @@ -Analogix ANX7814 SlimPort (Full-HD Transmitter) ------------------------------------------------ - -The ANX7814 is an ultra-low power Full-HD (1080p60) SlimPort transmitter -designed for portable devices. - -Required properties: - - - compatible : Must be one of: - "analogix,anx7808" - "analogix,anx7812" - "analogix,anx7814" - "analogix,anx7818" - - reg : I2C address of the device - - interrupts : Should contain the INTP interrupt - - hpd-gpios : Which GPIO to use for hpd - - pd-gpios : Which GPIO to use for power down - - reset-gpios : Which GPIO to use for reset - -Optional properties: - - - dvdd10-supply : Regulator for 1.0V digital core power. - - Video port for HDMI input, using the DT bindings defined in [1]. - -[1]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - - anx7814: anx7814@38 { - compatible = "analogix,anx7814"; - reg = <0x38>; - interrupt-parent = <&gpio0>; - interrupts = <99 IRQ_TYPE_LEVEL_LOW>; /* INTP */ - hpd-gpios = <&pio 36 GPIO_ACTIVE_HIGH>; - pd-gpios = <&pio 33 GPIO_ACTIVE_HIGH>; - reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>; - port { - anx7814_in: endpoint { - remote-endpoint = <&hdmi0_out>; - }; - }; - }; diff --git a/Bindings/display/bridge/chrontel,ch7033.yaml b/Bindings/display/bridge/chrontel,ch7033.yaml new file mode 100644 index 000000000000..9f38f55fc990 --- /dev/null +++ b/Bindings/display/bridge/chrontel,ch7033.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2019,2020 Lubomir Rintel +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/chrontel,ch7033.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Chrontel CH7033 Video Encoder Device Tree Bindings + +maintainers: + - Lubomir Rintel + +properties: + compatible: + const: chrontel,ch7033 + + reg: + maxItems: 1 + description: I2C address of the device + + ports: + type: object + + properties: + port@0: + type: object + description: | + Video port for RGB input. + + port@1: + type: object + description: | + DVI port, should be connected to a node compatible with the + dvi-connector binding. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - ports + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + vga-dvi-encoder@76 { + compatible = "chrontel,ch7033"; + reg = <0x76>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&lcd0_rgb_out>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dvi_in>; + }; + }; + + }; + }; + }; diff --git a/Bindings/display/bridge/dumb-vga-dac.txt b/Bindings/display/bridge/dumb-vga-dac.txt deleted file mode 100644 index 164cbb15f04c..000000000000 --- a/Bindings/display/bridge/dumb-vga-dac.txt +++ /dev/null @@ -1,50 +0,0 @@ -Dumb RGB to VGA DAC bridge ---------------------------- - -This binding is aimed for dumb RGB to VGA DAC based bridges that do not require -any configuration. - -Required properties: - -- compatible: Must be "dumb-vga-dac" - -Required nodes: - -This device has two video ports. Their connections are modelled using the OF -graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for RGB input -- Video port 1 for VGA output - -Optional properties: -- vdd-supply: Power supply for DAC - -Example -------- - -bridge { - compatible = "dumb-vga-dac"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&tcon0_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; -}; diff --git a/Bindings/display/bridge/dw_mipi_dsi.txt b/Bindings/display/bridge/dw_mipi_dsi.txt deleted file mode 100644 index b13adf30b8d3..000000000000 --- a/Bindings/display/bridge/dw_mipi_dsi.txt +++ /dev/null @@ -1,32 +0,0 @@ -Synopsys DesignWare MIPI DSI host controller -============================================ - -This document defines device tree properties for the Synopsys DesignWare MIPI -DSI host controller. It doesn't constitue a device tree binding specification -by itself but is meant to be referenced by platform-specific device tree -bindings. - -When referenced from platform device tree bindings the properties defined in -this document are defined as follows. The platform device tree bindings are -responsible for defining whether each optional property is used or not. - -- reg: Memory mapped base address and length of the DesignWare MIPI DSI - host controller registers. (mandatory) - -- clocks: References to all the clocks specified in the clock-names property - as specified in [1]. (mandatory) - -- clock-names: - - "pclk" is the peripheral clock for either AHB and APB. (mandatory) - - "px_clk" is the pixel clock for the DPI/RGB input. (optional) - -- resets: References to all the resets specified in the reset-names property - as specified in [2]. (optional) - -- reset-names: string reset name, must be "apb" if used. (optional) - -- panel or bridge node: see [3]. (mandatory) - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/reset/reset.txt -[3] Documentation/devicetree/bindings/display/mipi-dsi-bus.txt diff --git a/Bindings/display/bridge/ite,it6505.yaml b/Bindings/display/bridge/ite,it6505.yaml new file mode 100644 index 000000000000..2c500166c65d --- /dev/null +++ b/Bindings/display/bridge/ite,it6505.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/ite,it6505.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ITE it6505 Device Tree Bindings + +maintainers: + - Allen Chen + +description: | + The IT6505 is a high-performance DisplayPort 1.1a transmitter, + fully compliant with DisplayPort 1.1a, HDCP 1.3 specifications. + The IT6505 supports color depth of up to 36 bits (12 bits/color) + and ensures robust transmission of high-quality uncompressed video + content, along with uncompressed and compressed digital audio content. + + Aside from the various video output formats supported, the IT6505 + also encodes and transmits up to 8 channels of I2S digital audio, + with sampling rate up to 192kHz and sample size up to 24 bits. + In addition, an S/PDIF input port takes in compressed audio of up to + 192kHz frame rate. + + Each IT6505 chip comes preprogrammed with an unique HDCP key, + in compliance with the HDCP 1.3 standard so as to provide secure + transmission of high-definition content. Users of the IT6505 need not + purchase any HDCP keys or ROMs. + +properties: + compatible: + const: ite,it6505 + + ovdd-supply: + maxItems: 1 + description: I/O voltage + + pwr18-supply: + maxItems: 1 + description: core voltage + + interrupts: + maxItems: 1 + description: interrupt specifier of INT pin + + reset-gpios: + maxItems: 1 + description: gpio specifier of RESET pin + + extcon: + maxItems: 1 + description: extcon specifier for the Power Delivery + + port: + type: object + description: A port node pointing to DPI host port node + +required: + - compatible + - ovdd-supply + - pwr18-supply + - interrupts + - reset-gpios + - extcon + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + dp-bridge@5c { + compatible = "ite,it6505"; + interrupts = <152 IRQ_TYPE_EDGE_FALLING 152 0>; + reg = <0x5c>; + pinctrl-names = "default"; + pinctrl-0 = <&it6505_pins>; + ovdd-supply = <&mt6358_vsim1_reg>; + pwr18-supply = <&it6505_pp18_reg>; + reset-gpios = <&pio 179 1>; + extcon = <&usbc_extcon>; + + port { + it6505_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; diff --git a/Bindings/display/bridge/lvds-codec.yaml b/Bindings/display/bridge/lvds-codec.yaml index 8f373029f5d2..68951d56ebba 100644 --- a/Bindings/display/bridge/lvds-codec.yaml +++ b/Bindings/display/bridge/lvds-codec.yaml @@ -32,17 +32,17 @@ properties: compatible: oneOf: - items: - - enum: - - ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer - - ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer - - ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter - - const: lvds-encoder # Generic LVDS encoder compatible fallback + - enum: + - ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer + - ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer + - ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter + - const: lvds-encoder # Generic LVDS encoder compatible fallback - items: - - enum: - - ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver - - const: lvds-decoder # Generic LVDS decoders compatible fallback + - enum: + - ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver + - const: lvds-decoder # Generic LVDS decoders compatible fallback - enum: - - thine,thc63lvdm83d # For the THC63LVDM83D LVDS serializer + - thine,thc63lvdm83d # For the THC63LVDM83D LVDS serializer ports: type: object @@ -50,6 +50,12 @@ properties: This device has two video ports. Their connections are modeled using the OF graph bindings specified in Documentation/devicetree/bindings/graph.txt properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + port@0: type: object description: | @@ -66,6 +72,8 @@ properties: - port@0 - port@1 + additionalProperties: false + powerdown-gpios: description: The GPIO used to control the power down line of this device. diff --git a/Bindings/display/bridge/nwl-dsi.yaml b/Bindings/display/bridge/nwl-dsi.yaml new file mode 100644 index 000000000000..8aff2d68fc33 --- /dev/null +++ b/Bindings/display/bridge/nwl-dsi.yaml @@ -0,0 +1,226 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Northwest Logic MIPI-DSI controller on i.MX SoCs + +maintainers: + - Guido Gúnther + - Robert Chiras + +description: | + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for + the SOCs NWL MIPI-DSI host controller. + +properties: + compatible: + const: fsl,imx8mq-nwl-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + clocks: + items: + - description: DSI core clock + - description: RX_ESC clock (used in escape mode) + - description: TX_ESC clock (used in escape mode) + - description: PHY_REF clock + - description: LCDIF clock + + clock-names: + items: + - const: core + - const: rx_esc + - const: tx_esc + - const: phy_ref + - const: lcdif + + mux-controls: + description: + mux controller node to use for operating the input mux + + phys: + maxItems: 1 + description: + A phandle to the phy module representing the DPHY + + phy-names: + items: + - const: dphy + + power-domains: + maxItems: 1 + + resets: + items: + - description: dsi byte reset line + - description: dsi dpi reset line + - description: dsi esc reset line + - description: dsi pclk reset line + + reset-names: + items: + - const: byte + - const: dpi + - const: esc + - const: pclk + + ports: + type: object + description: + A node containing DSI input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/graph.txt. + properties: + port@0: + type: object + description: + Input port node to receive pixel data from the + display controller. Exactly one endpoint must be + specified. + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + endpoint@0: + description: sub-node describing the input from LCDIF + type: object + + endpoint@1: + description: sub-node describing the input from DCSS + type: object + + reg: + const: 0 + + required: + - '#address-cells' + - '#size-cells' + - reg + + oneOf: + - required: + - endpoint@0 + - required: + - endpoint@1 + + additionalProperties: false + + port@1: + type: object + description: + DSI output port node to the panel or the next bridge + in the chain + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + required: + - '#address-cells' + - '#size-cells' + - port@0 + - port@1 + + additionalProperties: false + +patternProperties: + "^panel@[0-9]+$": + type: object + +required: + - '#address-cells' + - '#size-cells' + - clock-names + - clocks + - compatible + - interrupts + - mux-controls + - phy-names + - phys + - ports + - reg + - reset-names + - resets + +additionalProperties: false + +examples: + - | + + #include + #include + #include + + mipi_dsi: mipi_dsi@30a00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30A00000 0x300>; + clocks = <&clk IMX8MQ_CLK_DSI_CORE>, + <&clk IMX8MQ_CLK_DSI_AHB>, + <&clk IMX8MQ_CLK_DSI_IPG_DIV>, + <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_CLK_LCDIF_PIXEL>; + clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; + interrupts = ; + mux-controls = <&mux 0>; + power-domains = <&pgc_mipi>; + resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, + <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, + <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, + <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; + reset-names = "byte", "dpi", "esc", "pclk"; + phys = <&dphy>; + phy-names = "dphy"; + + panel@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "rocktech,jh057n00900"; + reg = <0>; + port@0 { + reg = <0>; + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #size-cells = <0>; + #address-cells = <1>; + reg = <0>; + mipi_dsi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; diff --git a/Bindings/display/bridge/ps8640.yaml b/Bindings/display/bridge/ps8640.yaml index 5dff93641bea..7e27cfcf770d 100644 --- a/Bindings/display/bridge/ps8640.yaml +++ b/Bindings/display/bridge/ps8640.yaml @@ -50,6 +50,12 @@ properties: Documentation/devicetree/bindings/media/video-interfaces.txt Documentation/devicetree/bindings/graph.txt properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + port@0: type: object description: | @@ -63,6 +69,8 @@ properties: required: - port@0 + additionalProperties: false + required: - compatible - reg diff --git a/Bindings/display/bridge/sii902x.txt b/Bindings/display/bridge/sii902x.txt index 6e14e087c0d0..0d1db3f9da84 100644 --- a/Bindings/display/bridge/sii902x.txt +++ b/Bindings/display/bridge/sii902x.txt @@ -37,7 +37,7 @@ Optional properties: simple-card or audio-graph-card binding. See their binding documents on how to describe the way the sii902x device is connected to the rest of the audio system: - Documentation/devicetree/bindings/sound/simple-card.txt + Documentation/devicetree/bindings/sound/simple-card.yaml Documentation/devicetree/bindings/sound/audio-graph-card.txt Note: In case of the audio-graph-card binding the used port index should be 3. diff --git a/Bindings/display/bridge/simple-bridge.yaml b/Bindings/display/bridge/simple-bridge.yaml new file mode 100644 index 000000000000..0880cbf217d5 --- /dev/null +++ b/Bindings/display/bridge/simple-bridge.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/simple-bridge.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Transparent non-programmable DRM bridges + +maintainers: + - Laurent Pinchart + - Maxime Ripard + +description: | + This binding supports transparent non-programmable bridges that don't require + any configuration, with a single input and a single output. + +properties: + compatible: + oneOf: + - items: + - enum: + - ti,ths8134a + - ti,ths8134b + - const: ti,ths8134 + - enum: + - adi,adv7123 + - dumb-vga-dac + - ti,opa362 + - ti,ths8134 + - ti,ths8135 + + ports: + type: object + description: | + This device has two video ports. Their connections are modeled using the + OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + type: object + description: The bridge input + + port@1: + type: object + description: The bridge output + + required: + - port@0 + - port@1 + + additionalProperties: false + + enable-gpios: + maxItems: 1 + description: GPIO controlling bridge enable + + vdd-supply: + maxItems: 1 + description: Power supply for the bridge + +required: + - compatible + - ports + +additionalProperties: false + +examples: + - | + bridge { + compatible = "ti,ths8134a", "ti,ths8134"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vga_bridge_in: endpoint { + remote-endpoint = <&tcon0_out_vga>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/bridge/snps,dw-mipi-dsi.yaml b/Bindings/display/bridge/snps,dw-mipi-dsi.yaml new file mode 100644 index 000000000000..012aa8e7cb8c --- /dev/null +++ b/Bindings/display/bridge/snps,dw-mipi-dsi.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare MIPI DSI host controller + +maintainers: + - Philippe CORNU + +description: | + This document defines device tree properties for the Synopsys DesignWare MIPI + DSI host controller. It doesn't constitue a device tree binding specification + by itself but is meant to be referenced by platform-specific device tree + bindings. + + When referenced from platform device tree bindings the properties defined in + this document are defined as follows. The platform device tree bindings are + responsible for defining whether each property is required or optional. + +allOf: + - $ref: ../dsi-controller.yaml# + +properties: + reg: + maxItems: 1 + + clocks: + items: + - description: Module clock + - description: DSI bus clock for either AHB and APB + - description: Pixel clock for the DPI/RGB input + minItems: 2 + + clock-names: + items: + - const: ref + - const: pclk + - const: px_clk + minItems: 2 + + resets: + maxItems: 1 + + reset-names: + const: apb + + ports: + type: object + + properties: + port@0: + type: object + description: Input node to receive pixel data. + port@1: + type: object + description: DSI output node to panel. + + required: + - port@0 + - port@1 + +required: + - clock-names + - clocks + - ports + - reg diff --git a/Bindings/display/bridge/thine,thc63lvd1024.txt b/Bindings/display/bridge/thine,thc63lvd1024.txt deleted file mode 100644 index d17d1e5820d7..000000000000 --- a/Bindings/display/bridge/thine,thc63lvd1024.txt +++ /dev/null @@ -1,66 +0,0 @@ -Thine Electronics THC63LVD1024 LVDS decoder -------------------------------------------- - -The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS streams -to parallel data outputs. The chip supports single/dual input/output modes, -handling up to two LVDS input streams and up to two digital CMOS/TTL outputs. - -Single or dual operation mode, output data mapping and DDR output modes are -configured through input signals and the chip does not expose any control bus. - -Required properties: -- compatible: Shall be "thine,thc63lvd1024" -- vcc-supply: Power supply for TTL output, TTL CLOCKOUT signal, LVDS input, - PPL and digital circuitry - -Optional properties: -- powerdown-gpios: Power down GPIO signal, pin name "/PDWN". Active low -- oe-gpios: Output enable GPIO signal, pin name "OE". Active high - -The THC63LVD1024 video port connections are modeled according -to OF graph bindings specified by Documentation/devicetree/bindings/graph.txt - -Required video port nodes: -- port@0: First LVDS input port -- port@2: First digital CMOS/TTL parallel output - -Optional video port nodes: -- port@1: Second LVDS input port -- port@3: Second digital CMOS/TTL parallel output - -The device can operate in single-link mode or dual-link mode. In single-link -mode, all pixels are received on port@0, and port@1 shall not contain any -endpoint. In dual-link mode, even-numbered pixels are received on port@0 and -odd-numbered pixels on port@1, and both port@0 and port@1 shall contain -endpoints. - -Example: --------- - - thc63lvd1024: lvds-decoder { - compatible = "thine,thc63lvd1024"; - - vcc-supply = <®_lvds_vcc>; - powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_dec_in_0: endpoint { - remote-endpoint = <&lvds_out>; - }; - }; - - port@2{ - reg = <2>; - - lvds_dec_out_2: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; diff --git a/Bindings/display/bridge/thine,thc63lvd1024.yaml b/Bindings/display/bridge/thine,thc63lvd1024.yaml new file mode 100644 index 000000000000..469ac4a34273 --- /dev/null +++ b/Bindings/display/bridge/thine,thc63lvd1024.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/thine,thc63lvd1024.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Thine Electronics THC63LVD1024 LVDS Decoder + +maintainers: + - Jacopo Mondi + - Laurent Pinchart + +description: | + The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS + streams to parallel data outputs. The chip supports single/dual input/output + modes, handling up to two LVDS input streams and up to two digital CMOS/TTL + outputs. + + Single or dual operation mode, output data mapping and DDR output modes are + configured through input signals and the chip does not expose any control + bus. + +properties: + compatible: + const: thine,thc63lvd1024 + + ports: + type: object + description: | + This device has four video ports. Their connections are modeled using the + OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. + + The device can operate in single-link mode or dual-link mode. In + single-link mode, all pixels are received on port@0, and port@1 shall not + contain any endpoint. In dual-link mode, even-numbered pixels are + received on port@0 and odd-numbered pixels on port@1, and both port@0 and + port@1 shall contain endpoints. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + type: object + description: First LVDS input port + + port@1: + type: object + description: Second LVDS input port + + port@2: + type: object + description: First digital CMOS/TTL parallel output + + port@3: + type: object + description: Second digital CMOS/TTL parallel output + + required: + - port@0 + - port@2 + + additionalProperties: false + + oe-gpios: + maxItems: 1 + description: Output enable GPIO signal, pin name "OE", active high. + + powerdown-gpios: + maxItems: 1 + description: Power down GPIO signal, pin name "/PDWN", active low. + + vcc-supply: + maxItems: 1 + description: + Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and + digital circuitry. + +required: + - compatible + - ports + - vcc-supply + +additionalProperties: false + +examples: + - | + #include + + lvds-decoder { + compatible = "thine,thc63lvd1024"; + + vcc-supply = <®_lvds_vcc>; + powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_dec_in_0: endpoint { + remote-endpoint = <&lvds_out>; + }; + }; + + port@2 { + reg = <2>; + + lvds_dec_out_2: endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/bridge/ti,ths813x.txt b/Bindings/display/bridge/ti,ths813x.txt deleted file mode 100644 index df3d7c1ac09e..000000000000 --- a/Bindings/display/bridge/ti,ths813x.txt +++ /dev/null @@ -1,51 +0,0 @@ -THS8134 and THS8135 Video DAC ------------------------------ - -This is the binding for Texas Instruments THS8134, THS8134A, THS8134B and -THS8135 Video DAC bridges. - -Required properties: - -- compatible: Must be one of - "ti,ths8134" - "ti,ths8134a," "ti,ths8134" - "ti,ths8134b", "ti,ths8134" - "ti,ths8135" - -Required nodes: - -This device has two video ports. Their connections are modelled using the OF -graph bindings specified in Documentation/devicetree/bindings/graph.txt. - -- Video port 0 for RGB input -- Video port 1 for VGA output - -Example -------- - -vga-bridge { - compatible = "ti,ths8135"; - #address-cells = <1>; - #size-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_bridge_in: endpoint { - remote-endpoint = <&lcdc_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_bridge_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; -}; diff --git a/Bindings/display/dsi-controller.yaml b/Bindings/display/dsi-controller.yaml index fd986c36c737..85b71b1fd28a 100644 --- a/Bindings/display/dsi-controller.yaml +++ b/Bindings/display/dsi-controller.yaml @@ -28,7 +28,7 @@ description: | properties: $nodename: - pattern: "^dsi-controller(@.*)?$" + pattern: "^dsi(@.*)?$" "#address-cells": const: 1 @@ -76,7 +76,7 @@ patternProperties: examples: - | #include - dsi-controller@a0351000 { + dsi@a0351000 { reg = <0xa0351000 0x1000>; #address-cells = <1>; #size-cells = <0>; diff --git a/Bindings/display/imx/fsl-imx-drm.txt b/Bindings/display/imx/fsl-imx-drm.txt index 5bf77f6dd19d..5a99490c17b9 100644 --- a/Bindings/display/imx/fsl-imx-drm.txt +++ b/Bindings/display/imx/fsl-imx-drm.txt @@ -68,7 +68,7 @@ Required properties: datasheet - clocks : phandle to the PRE axi clock input, as described in Documentation/devicetree/bindings/clock/clock-bindings.txt and - Documentation/devicetree/bindings/clock/imx6q-clock.txt. + Documentation/devicetree/bindings/clock/imx6q-clock.yaml. - clock-names: should be "axi" - interrupts: should contain the PRE interrupt - fsl,iram: phandle pointing to the mmio-sram device node, that should be @@ -94,7 +94,7 @@ Required properties: datasheet - clocks : phandles to the PRG ipg and axi clock inputs, as described in Documentation/devicetree/bindings/clock/clock-bindings.txt and - Documentation/devicetree/bindings/clock/imx6q-clock.txt. + Documentation/devicetree/bindings/clock/imx6q-clock.yaml. - clock-names: should be "ipg" and "axi" - fsl,pres: phandles to the PRE units attached to this PRG, with the fixed PRE as the first entry and the muxable PREs following. diff --git a/Bindings/display/imx/ldb.txt b/Bindings/display/imx/ldb.txt index 38c637fa39dd..8e6e7d797943 100644 --- a/Bindings/display/imx/ldb.txt +++ b/Bindings/display/imx/ldb.txt @@ -30,8 +30,8 @@ Required properties: "di2_sel" - IPU2 DI0 mux "di3_sel" - IPU2 DI1 mux The needed clock numbers for each are documented in - Documentation/devicetree/bindings/clock/imx5-clock.txt, and in - Documentation/devicetree/bindings/clock/imx6q-clock.txt. + Documentation/devicetree/bindings/clock/imx5-clock.yaml, and in + Documentation/devicetree/bindings/clock/imx6q-clock.yaml. Optional properties: - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q diff --git a/Bindings/display/mediatek/mediatek,dpi.txt b/Bindings/display/mediatek/mediatek,dpi.txt index 58914cf681b8..77def4456706 100644 --- a/Bindings/display/mediatek/mediatek,dpi.txt +++ b/Bindings/display/mediatek/mediatek,dpi.txt @@ -17,6 +17,9 @@ Required properties: Documentation/devicetree/bindings/graph.txt. This port should be connected to the input port of an attached HDMI or LVDS encoder chip. +Optional properties: +- pinctrl-names: Contain "default" and "sleep". + Example: dpi0: dpi@1401d000 { @@ -27,6 +30,9 @@ dpi0: dpi@1401d000 { <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>; clock-names = "pixel", "engine", "pll"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dpi_pin_func>; + pinctrl-1 = <&dpi_pin_idle>; port { dpi0_out: endpoint { diff --git a/Bindings/display/mediatek/mediatek,dsi.txt b/Bindings/display/mediatek/mediatek,dsi.txt index a19a6cc375ed..8e4729de8c85 100644 --- a/Bindings/display/mediatek/mediatek,dsi.txt +++ b/Bindings/display/mediatek/mediatek,dsi.txt @@ -33,6 +33,13 @@ Required properties: - #clock-cells: must be <0>; - #phy-cells: must be <0>. +Optional properties: +- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And + the step is 200. +- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If + unspecified default values shall be used. +- nvmem-cell-names: Should be "calibration-data" + Example: mipi_tx0: mipi-dphy@10215000 { @@ -42,6 +49,9 @@ mipi_tx0: mipi-dphy@10215000 { clock-output-names = "mipi_tx0_pll"; #clock-cells = <0>; #phy-cells = <0>; + drive-strength-microamp = <4600>; + nvmem-cells= <&mipi_tx_calibration>; + nvmem-cell-names = "calibration-data"; }; dsi0: dsi@1401b000 { diff --git a/Bindings/display/panel/arm,versatile-tft-panel.txt b/Bindings/display/panel/arm,versatile-tft-panel.txt deleted file mode 100644 index 0601a9e34703..000000000000 --- a/Bindings/display/panel/arm,versatile-tft-panel.txt +++ /dev/null @@ -1,31 +0,0 @@ -ARM Versatile TFT Panels - -These panels are connected to the daughterboards found on the -ARM Versatile reference designs. - -This device node must appear as a child to a "syscon"-compatible -node. - -Required properties: -- compatible: should be "arm,versatile-tft-panel" - -Required subnodes: -- port: see display/panel/panel-common.yaml, graph.txt - - -Example: - -sysreg@0 { - compatible = "arm,versatile-sysreg", "syscon", "simple-mfd"; - reg = <0x00000 0x1000>; - - panel: display@0 { - compatible = "arm,versatile-tft-panel"; - - port { - panel_in: endpoint { - remote-endpoint = <&foo>; - }; - }; - }; -}; diff --git a/Bindings/display/panel/arm,versatile-tft-panel.yaml b/Bindings/display/panel/arm,versatile-tft-panel.yaml new file mode 100644 index 000000000000..be69e0cc50fc --- /dev/null +++ b/Bindings/display/panel/arm,versatile-tft-panel.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/arm,versatile-tft-panel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Versatile TFT Panels + +maintainers: + - Linus Walleij + +description: | + These panels are connected to the daughterboards found on the + ARM Versatile reference designs. + + This device node must appear as a child to a "syscon"-compatible + node. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: arm,versatile-tft-panel + + port: true + +required: + - compatible + - port + +additionalProperties: false + +examples: + - | + sysreg@0 { + compatible = "arm,versatile-sysreg", "syscon", "simple-mfd"; + reg = <0x00000 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + panel { + compatible = "arm,versatile-tft-panel"; + + port { + panel_in: endpoint { + remote-endpoint = <&foo>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml b/Bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml new file mode 100644 index 000000000000..083d2b9d0c69 --- /dev/null +++ b/Bindings/display/panel/asus,z00t-tm5p5-nt35596.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/asus,z00t-tm5p5-nt35596.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASUS Z00T TM5P5 NT35596 5.5" 1080×1920 LCD Panel + +maintainers: + - Konrad Dybcio + +description: |+ + This panel seems to only be found in the Asus Z00T + smartphone and we have no straightforward way of + actually getting the correct model number, + as no schematics are released publicly. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: asus,z00t-tm5p5-n35596 + reg: true + reset-gpios: true + vdd-supply: + description: core voltage supply + vddio-supply: + description: vddio supply + +required: + - compatible + - reg + - vdd-supply + - vddio-supply + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + reg = <0>; + + compatible = "asus,z00t-tm5p5-n35596"; + + vdd-supply = <&pm8916_l8>; + vddio-supply = <&pm8916_l6>; + reset-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Bindings/display/panel/boe,himax8279d.txt b/Bindings/display/panel/boe,himax8279d.txt deleted file mode 100644 index 3caea2172b1b..000000000000 --- a/Bindings/display/panel/boe,himax8279d.txt +++ /dev/null @@ -1,24 +0,0 @@ -Boe Himax8279d 1200x1920 TFT LCD panel - -Required properties: -- compatible: should be "boe,himax8279d8p" and one of: "boe,himax8279d10p" -- reg: DSI virtual channel of the peripheral -- enable-gpios: panel enable gpio -- pp33-gpios: a GPIO phandle for the 3.3v pin that provides the supply voltage -- pp18-gpios: a GPIO phandle for the 1.8v pin that provides the supply voltage - -Optional properties: -- backlight: phandle of the backlight device attached to the panel - -Example: - - &mipi_dsi { - panel { - compatible = "boe,himax8279d8p", "boe,himax8279d10p"; - reg = <0>; - backlight = <&backlight>; - enable-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; - pp33-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; - pp18-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/Bindings/display/panel/boe,himax8279d.yaml b/Bindings/display/panel/boe,himax8279d.yaml new file mode 100644 index 000000000000..272a3a018a33 --- /dev/null +++ b/Bindings/display/panel/boe,himax8279d.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/boe,himax8279d.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Boe Himax8279d 1200x1920 TFT LCD panel + +maintainers: + - Jerry Han + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - const: boe,himax8279d8p + - const: boe,himax8279d10p + + backlight: true + enable-gpios: true + reg: true + + pp33-gpios: + maxItems: 1 + description: GPIO for the 3.3v pin that provides the supply voltage + + pp18-gpios: + maxItems: 1 + description: GPIO for the 1.8v pin that provides the supply voltage + +required: + - compatible + - reg + - enable-gpios + - pp33-gpios + - pp18-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "boe,himax8279d8p", "boe,himax8279d10p"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; + pp33-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + pp18-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; + }; + }; + +... diff --git a/Bindings/display/panel/boe,tv101wum-nl6.yaml b/Bindings/display/panel/boe,tv101wum-nl6.yaml index 740213459134..7f5df5851017 100644 --- a/Bindings/display/panel/boe,tv101wum-nl6.yaml +++ b/Bindings/display/panel/boe,tv101wum-nl6.yaml @@ -24,6 +24,8 @@ properties: - boe,tv101wum-n53 # AUO B101UAN08.3 10.1" WUXGA TFT LCD panel - auo,b101uan08.3 + # BOE TV105WUM-NW0 10.5" WUXGA TFT LCD panel + - boe,tv105wum-nw0 reg: description: the virtual channel number of a DSI peripheral diff --git a/Bindings/display/panel/display-timings.yaml b/Bindings/display/panel/display-timings.yaml index c8c0c9cb0492..56903ded005e 100644 --- a/Bindings/display/panel/display-timings.yaml +++ b/Bindings/display/panel/display-timings.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/panel/display-timings.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: display timing bindings +title: display timings bindings maintainers: - Thierry Reding @@ -14,7 +14,7 @@ maintainers: description: | A display panel may be able to handle several display timings, with different resolutions. - The display-timings node makes it possible to specify the timing + The display-timings node makes it possible to specify the timings and to specify the timing that is native for the display. properties: @@ -25,8 +25,8 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: | The default display timing is the one specified as native-mode. - If no native-mode is specified then the first node is assumed the - native mode. + If no native-mode is specified then the first node is assumed + to be the native mode. patternProperties: "^timing": diff --git a/Bindings/display/panel/feiyang,fy07024di26a30d.txt b/Bindings/display/panel/feiyang,fy07024di26a30d.txt deleted file mode 100644 index 82caa7b65ae8..000000000000 --- a/Bindings/display/panel/feiyang,fy07024di26a30d.txt +++ /dev/null @@ -1,20 +0,0 @@ -Feiyang FY07024DI26A30-D 7" MIPI-DSI LCD Panel - -Required properties: -- compatible: must be "feiyang,fy07024di26a30d" -- reg: DSI virtual channel used by that screen -- avdd-supply: analog regulator dc1 switch -- dvdd-supply: 3v3 digital regulator -- reset-gpios: a GPIO phandle for the reset pin - -Optional properties: -- backlight: phandle for the backlight control. - -panel@0 { - compatible = "feiyang,fy07024di26a30d"; - reg = <0>; - avdd-supply = <®_dc1sw>; - dvdd-supply = <®_dldo2>; - reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */ - backlight = <&backlight>; -}; diff --git a/Bindings/display/panel/feiyang,fy07024di26a30d.yaml b/Bindings/display/panel/feiyang,fy07024di26a30d.yaml new file mode 100644 index 000000000000..95acf9e96f1c --- /dev/null +++ b/Bindings/display/panel/feiyang,fy07024di26a30d.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/feiyang,fy07024di26a30d.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Feiyang FY07024DI26A30-D 7" MIPI-DSI LCD Panel + +maintainers: + - Jagan Teki + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: feiyang,fy07024di26a30d + + reg: + description: DSI virtual channel used by that screen + maxItems: 1 + + avdd-supply: + description: analog regulator dc1 switch + + dvdd-supply: + description: 3v3 digital regulator + + reset-gpios: true + + backlight: true + +required: + - compatible + - reg + - avdd-supply + - dvdd-supply + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "feiyang,fy07024di26a30d"; + reg = <0>; + avdd-supply = <®_dc1sw>; + dvdd-supply = <®_dldo2>; + reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */ + backlight = <&backlight>; + }; + }; diff --git a/Bindings/display/panel/ilitek,ili9322.txt b/Bindings/display/panel/ilitek,ili9322.txt deleted file mode 100644 index 3d5ce6ad6ec7..000000000000 --- a/Bindings/display/panel/ilitek,ili9322.txt +++ /dev/null @@ -1,49 +0,0 @@ -Ilitek ILI9322 TFT panel driver with SPI control bus - -This is a driver for 320x240 TFT panels, accepting a variety of input -streams that get adapted and scaled to the panel. The panel output has -960 TFT source driver pins and 240 TFT gate driver pins, VCOM, VCOML and -VCOMH outputs. - -Required properties: - - compatible: "dlink,dir-685-panel", "ilitek,ili9322" - (full system-specific compatible is always required to look up configuration) - - reg: address of the panel on the SPI bus - -Optional properties: - - vcc-supply: core voltage supply, see regulator/regulator.txt - - iovcc-supply: voltage supply for the interface input/output signals, - see regulator/regulator.txt - - vci-supply: voltage supply for analog parts, see regulator/regulator.txt - - reset-gpios: a GPIO spec for the reset pin, see gpio/gpio.txt - - The following optional properties only apply to RGB and YUV input modes and - can be omitted for BT.656 input modes: - - - pixelclk-active: see display/panel/display-timing.txt - - de-active: see display/panel/display-timing.txt - - hsync-active: see display/panel/display-timing.txt - - vsync-active: see display/panel/display-timing.txt - -The panel must obey the rules for a SPI slave device as specified in -spi/spi-bus.txt - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in -media/video-interfaces.txt. This node should describe panel's video bus. - -Example: - -panel: display@0 { - compatible = "dlink,dir-685-panel", "ilitek,ili9322"; - reg = <0>; - vcc-supply = <&vdisp>; - iovcc-supply = <&vdisp>; - vci-supply = <&vdisp>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; -}; diff --git a/Bindings/display/panel/ilitek,ili9322.yaml b/Bindings/display/panel/ilitek,ili9322.yaml new file mode 100644 index 000000000000..177d48c5bd97 --- /dev/null +++ b/Bindings/display/panel/ilitek,ili9322.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/ilitek,ili9322.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ilitek ILI9322 TFT panel driver with SPI control bus + +maintainers: + - Linus Walleij + +description: | + This is a driver for 320x240 TFT panels, accepting a variety of input + streams that get adapted and scaled to the panel. The panel output has + 960 TFT source driver pins and 240 TFT gate driver pins, VCOM, VCOML and + VCOMH outputs. + + The panel must obey the rules for a SPI slave device as specified in + spi/spi-controller.yaml + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - dlink,dir-685-panel + + - const: ilitek,ili9322 + + reset-gpios: true + port: true + + vcc-supply: + description: Core voltage supply + + iovcc-supply: + description: Voltage supply for the interface input/output signals + + vci-supply: + description: Voltage supply for analog parts + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + panel: display@0 { + compatible = "dlink,dir-685-panel", "ilitek,ili9322"; + reg = <0>; + vcc-supply = <&vdisp>; + iovcc-supply = <&vdisp>; + vci-supply = <&vdisp>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/panel/ilitek,ili9881c.txt b/Bindings/display/panel/ilitek,ili9881c.txt deleted file mode 100644 index 4a041acb4e18..000000000000 --- a/Bindings/display/panel/ilitek,ili9881c.txt +++ /dev/null @@ -1,20 +0,0 @@ -Ilitek ILI9881c based MIPI-DSI panels - -Required properties: - - compatible: must be "ilitek,ili9881c" and one of: - * "bananapi,lhr050h41" - - reg: DSI virtual channel used by that screen - - power-supply: phandle to the power regulator - - reset-gpios: a GPIO phandle for the reset pin - -Optional properties: - - backlight: phandle to the backlight used - -Example: -panel@0 { - compatible = "bananapi,lhr050h41", "ilitek,ili9881c"; - reg = <0>; - power-supply = <®_display>; - reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */ - backlight = <&pwm_bl>; -}; diff --git a/Bindings/display/panel/ilitek,ili9881c.yaml b/Bindings/display/panel/ilitek,ili9881c.yaml new file mode 100644 index 000000000000..a39332276bab --- /dev/null +++ b/Bindings/display/panel/ilitek,ili9881c.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/ilitek,ili9881c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ilitek ILI9881c based MIPI-DSI panels + +maintainers: + - Maxime Ripard + +properties: + compatible: + items: + - enum: + - bananapi,lhr050h41 + + - const: ilitek,ili9881c + + backlight: true + power-supply: true + reg: true + reset-gpios: true + +required: + - compatible + - power-supply + - reg + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "bananapi,lhr050h41", "ilitek,ili9881c"; + reg = <0>; + power-supply = <®_display>; + reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */ + backlight = <&pwm_bl>; + }; + }; + +... diff --git a/Bindings/display/panel/innolux,p097pfg.txt b/Bindings/display/panel/innolux,p097pfg.txt deleted file mode 100644 index d1cab3a8f0fb..000000000000 --- a/Bindings/display/panel/innolux,p097pfg.txt +++ /dev/null @@ -1,24 +0,0 @@ -Innolux P097PFG 9.7" 1536x2048 TFT LCD panel - -Required properties: -- compatible: should be "innolux,p097pfg" -- reg: DSI virtual channel of the peripheral -- avdd-supply: phandle of the regulator that provides positive voltage -- avee-supply: phandle of the regulator that provides negative voltage -- enable-gpios: panel enable gpio - -Optional properties: -- backlight: phandle of the backlight device attached to the panel - -Example: - - &mipi_dsi { - panel@0 { - compatible = "innolux,p079zca"; - reg = <0>; - avdd-supply = <...>; - avee-supply = <...>; - backlight = <&backlight>; - enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/Bindings/display/panel/innolux,p097pfg.yaml b/Bindings/display/panel/innolux,p097pfg.yaml new file mode 100644 index 000000000000..5a5f071627fb --- /dev/null +++ b/Bindings/display/panel/innolux,p097pfg.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/innolux,p097pfg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Innolux P097PFG 9.7" 1536x2048 TFT LCD panel + +maintainers: + - Lin Huang + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: innolux,p097pfg + + backlight: true + enable-gpios: true + reg: true + + avdd-supply: + description: The regulator that provides positive voltage + + avee-supply: + description: The regulator that provides negative voltage + +required: + - compatible + - reg + - avdd-supply + - avee-supply + - enable-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "innolux,p097pfg"; + reg = <0>; + avdd-supply = <&avdd>; + avee-supply = <&avee>; + backlight = <&backlight>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + }; + +... diff --git a/Bindings/display/panel/innolux,p120zdg-bf1.txt b/Bindings/display/panel/innolux,p120zdg-bf1.txt deleted file mode 100644 index 513f03466aba..000000000000 --- a/Bindings/display/panel/innolux,p120zdg-bf1.txt +++ /dev/null @@ -1,22 +0,0 @@ -Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. - -Required properties: -- compatible: should be "innolux,p120zdg-bf1" -- power-supply: regulator to provide the supply voltage - -Optional properties: -- enable-gpios: GPIO pin to enable or disable the panel -- backlight: phandle of the backlight device attached to the panel -- no-hpd: If HPD isn't hooked up; add this property. - -Example: - panel_edp: panel-edp { - compatible = "innolux,p120zdg-bf1"; - enable-gpios = <&msmgpio 31 GPIO_ACTIVE_LOW>; - power-supply = <&pm8916_l2>; - backlight = <&backlight>; - no-hpd; - }; diff --git a/Bindings/display/panel/innolux,p120zdg-bf1.yaml b/Bindings/display/panel/innolux,p120zdg-bf1.yaml new file mode 100644 index 000000000000..243dac2416f3 --- /dev/null +++ b/Bindings/display/panel/innolux,p120zdg-bf1.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/innolux,p120zdg-bf1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel + +maintainers: + - Sandeep Panda + - Douglas Anderson + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: innolux,p120zdg-bf1 + + enable-gpios: true + power-supply: true + backlight: true + no-hpd: true + +required: + - compatible + - power-supply + +additionalProperties: false + +examples: + - | + #include + + panel_edp: panel-edp { + compatible = "innolux,p120zdg-bf1"; + enable-gpios = <&msmgpio 31 GPIO_ACTIVE_LOW>; + power-supply = <&pm8916_l2>; + backlight = <&backlight>; + no-hpd; + }; + +... diff --git a/Bindings/display/panel/jdi,lt070me05000.txt b/Bindings/display/panel/jdi,lt070me05000.txt deleted file mode 100644 index 4989c91d505f..000000000000 --- a/Bindings/display/panel/jdi,lt070me05000.txt +++ /dev/null @@ -1,31 +0,0 @@ -JDI model LT070ME05000 1200x1920 7" DSI Panel - -Required properties: -- compatible: should be "jdi,lt070me05000" -- vddp-supply: phandle of the regulator that provides the supply voltage - Power IC supply (3-5V) -- iovcc-supply: phandle of the regulator that provides the supply voltage - IOVCC , power supply for LCM (1.8V) -- enable-gpios: phandle of gpio for enable line - LED_EN, LED backlight enable, High active -- reset-gpios: phandle of gpio for reset line - This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names - XRES, Reset, Low active -- dcdc-en-gpios: phandle of the gpio for power ic line - Power IC supply enable, High active - -Example: - - dsi0: qcom,mdss_dsi@4700000 { - panel@0 { - compatible = "jdi,lt070me05000"; - reg = <0>; - - vddp-supply = <&pm8921_l17>; - iovcc-supply = <&pm8921_lvs7>; - - enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>; - reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>; - dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/Bindings/display/panel/jdi,lt070me05000.yaml b/Bindings/display/panel/jdi,lt070me05000.yaml new file mode 100644 index 000000000000..b8b9435e464c --- /dev/null +++ b/Bindings/display/panel/jdi,lt070me05000.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/jdi,lt070me05000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: JDI model LT070ME05000 1200x1920 7" DSI Panel + +maintainers: + - Vinay Simha BN + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: jdi,lt070me05000 + + enable-gpios: true + reg: true + reset-gpios: true + + vddp-supply: + description: | + The regulator that provides the supply voltage Power IC supply (3-5V) + + iovcc-supply: + description: | + The regulator that provides the supply voltage IOVCC, + power supply for LCM (1.8V) + + dcdc-en-gpios: + description: | + phandle of the gpio for power ic line + Power IC supply enable, High active + +required: + - compatible + - reg + - vddp-supply + - iovcc-supply + - enable-gpios + - reset-gpios + - dcdc-en-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "jdi,lt070me05000"; + reg = <0>; + + vddp-supply = <&pm8921_l17>; + iovcc-supply = <&pm8921_lvs7>; + + enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>; + dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>; + }; + }; + +... diff --git a/Bindings/display/panel/kingdisplay,kd035g6-54nt.txt b/Bindings/display/panel/kingdisplay,kd035g6-54nt.txt deleted file mode 100644 index fa9596082e44..000000000000 --- a/Bindings/display/panel/kingdisplay,kd035g6-54nt.txt +++ /dev/null @@ -1,42 +0,0 @@ -King Display KD035G6-54NT 3.5" (320x240 pixels) 24-bit TFT LCD panel - -Required properties: -- compatible: should be "kingdisplay,kd035g6-54nt" -- power-supply: See panel-common.txt -- reset-gpios: See panel-common.txt - -Optional properties: -- backlight: see panel-common.txt - -The generic bindings for the SPI slaves documented in [1] also apply. - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in [2]. This -node should describe panel's video bus. - -[1]: Documentation/devicetree/bindings/spi/spi-bus.txt -[2]: Documentation/devicetree/bindings/graph.txt - -Example: - -&spi { - panel@0 { - compatible = "kingdisplay,kd035g6-54nt"; - reg = <0>; - - spi-max-frequency = <3125000>; - spi-3wire; - spi-cs-high; - - reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>; - - backlight = <&backlight>; - power-supply = <&ldo6>; - - port { - panel_input: endpoint { - remote-endpoint = <&panel_output>; - }; - }; - }; -}; diff --git a/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml b/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml new file mode 100644 index 000000000000..6960036975fa --- /dev/null +++ b/Bindings/display/panel/kingdisplay,kd035g6-54nt.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/kingdisplay,kd035g6-54nt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: King Display KD035G6-54NT 3.5" (320x240 pixels) 24-bit TFT LCD panel + +description: | + The panel must obey the rules for a SPI slave device as specified in + spi/spi-controller.yaml + +maintainers: + - Paul Cercueil + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: kingdisplay,kd035g6-54nt + + backlight: true + port: true + power-supply: true + reg: true + reset-gpios: true + +required: + - compatible + - power-supply + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "kingdisplay,kd035g6-54nt"; + reg = <0>; + + spi-max-frequency = <3125000>; + spi-3wire; + spi-cs-high; + + reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>; + + backlight = <&backlight>; + power-supply = <&ldo6>; + + port { + panel_input: endpoint { + remote-endpoint = <&panel_output>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/panel/kingdisplay,kd097d04.txt b/Bindings/display/panel/kingdisplay,kd097d04.txt deleted file mode 100644 index cfefff688614..000000000000 --- a/Bindings/display/panel/kingdisplay,kd097d04.txt +++ /dev/null @@ -1,22 +0,0 @@ -Kingdisplay KD097D04 9.7" 1536x2048 TFT LCD panel - -Required properties: -- compatible: should be "kingdisplay,kd097d04" -- reg: DSI virtual channel of the peripheral -- power-supply: phandle of the regulator that provides the supply voltage -- enable-gpios: panel enable gpio - -Optional properties: -- backlight: phandle of the backlight device attached to the panel - -Example: - - &mipi_dsi { - panel@0 { - compatible = "kingdisplay,kd097d04"; - reg = <0>; - power-supply = <...>; - backlight = <&backlight>; - enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/Bindings/display/panel/leadtek,ltk050h3146w.yaml b/Bindings/display/panel/leadtek,ltk050h3146w.yaml new file mode 100644 index 000000000000..a372bdc5bde1 --- /dev/null +++ b/Bindings/display/panel/leadtek,ltk050h3146w.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/leadtek,ltk050h3146w.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Leadtek LTK050H3146W 5.0in 720x1280 DSI panel + +maintainers: + - Heiko Stuebner + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + enum: + - leadtek,ltk050h3146w + - leadtek,ltk050h3146w-a2 + reg: true + backlight: true + reset-gpios: true + iovcc-supply: + description: regulator that supplies the iovcc voltage + vci-supply: + description: regulator that supplies the vci voltage + +required: + - compatible + - reg + - backlight + - iovcc-supply + - vci-supply + +additionalProperties: false + +examples: + - | + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "leadtek,ltk050h3146w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + vci-supply = <&vcc3v3_lcd>; + }; + }; + +... diff --git a/Bindings/display/panel/lg,acx467akm-7.txt b/Bindings/display/panel/lg,acx467akm-7.txt deleted file mode 100644 index fc1e1b325e49..000000000000 --- a/Bindings/display/panel/lg,acx467akm-7.txt +++ /dev/null @@ -1,7 +0,0 @@ -LG ACX467AKM-7 4.95" 1080×1920 LCD Panel - -Required properties: -- compatible: must be "lg,acx467akm-7" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Bindings/display/panel/lg,ld070wx3-sl01.txt b/Bindings/display/panel/lg,ld070wx3-sl01.txt deleted file mode 100644 index 5e649cb9aa1a..000000000000 --- a/Bindings/display/panel/lg,ld070wx3-sl01.txt +++ /dev/null @@ -1,7 +0,0 @@ -LG Corporation 7" WXGA TFT LCD panel - -Required properties: -- compatible: should be "lg,ld070wx3-sl01" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Bindings/display/panel/lg,lg4573.txt b/Bindings/display/panel/lg,lg4573.txt deleted file mode 100644 index 824441f4e95a..000000000000 --- a/Bindings/display/panel/lg,lg4573.txt +++ /dev/null @@ -1,19 +0,0 @@ -LG LG4573 TFT Liquid Crystal Display with SPI control bus - -Required properties: - - compatible: "lg,lg4573" - - reg: address of the panel on the SPI bus - -The panel must obey rules for SPI slave device specified in document [1]. - -[1]: Documentation/devicetree/bindings/spi/spi-bus.txt - -Example: - - lcd_panel: display@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <0>; - }; diff --git a/Bindings/display/panel/lg,lg4573.yaml b/Bindings/display/panel/lg,lg4573.yaml new file mode 100644 index 000000000000..b4314ce7b411 --- /dev/null +++ b/Bindings/display/panel/lg,lg4573.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/lg,lg4573.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LG LG4573 TFT Liquid Crystal Display with SPI control bus + +description: | + The panel must obey the rules for a SPI slave device as specified in + spi/spi-controller.yaml + +maintainers: + - Heiko Schocher + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: lg,lg4573 + + reg: true + spi-max-frequency: true + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + lcd_panel: display@0 { + compatible = "lg,lg4573"; + spi-max-frequency = <10000000>; + reg = <0>; + }; + }; + +... diff --git a/Bindings/display/panel/lg,lh500wx1-sd03.txt b/Bindings/display/panel/lg,lh500wx1-sd03.txt deleted file mode 100644 index a04fd2b2e73d..000000000000 --- a/Bindings/display/panel/lg,lh500wx1-sd03.txt +++ /dev/null @@ -1,7 +0,0 @@ -LG Corporation 5" HD TFT LCD panel - -Required properties: -- compatible: should be "lg,lh500wx1-sd03" - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Bindings/display/panel/lgphilips,lb035q02.txt b/Bindings/display/panel/lgphilips,lb035q02.txt deleted file mode 100644 index 1a1e653e5407..000000000000 --- a/Bindings/display/panel/lgphilips,lb035q02.txt +++ /dev/null @@ -1,33 +0,0 @@ -LG.Philips LB035Q02 Panel -========================= - -Required properties: -- compatible: "lgphilips,lb035q02" -- enable-gpios: panel enable gpio - -Optional properties: -- label: a symbolic name for the panel - -Required nodes: -- Video port for DPI input - -Example -------- - -lcd-panel: panel@0 { - compatible = "lgphilips,lb035q02"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - label = "lcd"; - - enable-gpios = <&gpio7 7 0>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; -}; diff --git a/Bindings/display/panel/lgphilips,lb035q02.yaml b/Bindings/display/panel/lgphilips,lb035q02.yaml new file mode 100644 index 000000000000..830e335ddb53 --- /dev/null +++ b/Bindings/display/panel/lgphilips,lb035q02.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/lgphilips,lb035q02.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LG.Philips LB035Q02 Panel + +description: | + The panel must obey the rules for a SPI slave device as specified in + spi/spi-controller.yaml + +maintainers: + - Tomi Valkeinen + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: lgphilips,lb035q02 + + label: true + enable-gpios: true + port: true + +required: + - compatible + - enable-gpios + - port + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + panel: panel@0 { + compatible = "lgphilips,lb035q02"; + reg = <0>; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + + label = "lcd"; + + enable-gpios = <&gpio7 7 0>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/panel/olimex,lcd-olinuxino.txt b/Bindings/display/panel/olimex,lcd-olinuxino.txt deleted file mode 100644 index a89f9c830a85..000000000000 --- a/Bindings/display/panel/olimex,lcd-olinuxino.txt +++ /dev/null @@ -1,42 +0,0 @@ -Binding for Olimex Ltd. LCD-OLinuXino bridge panel. - -This device can be used as bridge between a host controller and LCD panels. -Currently supported LCDs are: - - LCD-OLinuXino-4.3TS - - LCD-OLinuXino-5 - - LCD-OLinuXino-7 - - LCD-OLinuXino-10 - -The panel itself contains: - - AT24C16C EEPROM holding panel identification and timing requirements - - AR1021 resistive touch screen controller (optional) - - FT5x6 capacitive touch screnn controller (optional) - - GT911/GT928 capacitive touch screen controller (optional) - -The above chips share same I2C bus. The EEPROM is factory preprogrammed with -device information (id, serial, etc.) and timing requirements. - -Touchscreen bingings can be found in these files: - - input/touchscreen/goodix.txt - - input/touchscreen/edt-ft5x06.txt - - input/touchscreen/ar1021.txt - -Required properties: - - compatible: should be "olimex,lcd-olinuxino" - - reg: address of the configuration EEPROM, should be <0x50> - - power-supply: phandle of the regulator that provides the supply voltage - -Optional properties: - - enable-gpios: GPIO pin to enable or disable the panel - - backlight: phandle of the backlight device attacked to the panel - -Example: -&i2c2 { - panel@50 { - compatible = "olimex,lcd-olinuxino"; - reg = <0x50>; - power-supply = <®_vcc5v0>; - enable-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; - }; -}; diff --git a/Bindings/display/panel/olimex,lcd-olinuxino.yaml b/Bindings/display/panel/olimex,lcd-olinuxino.yaml new file mode 100644 index 000000000000..2329d9610f83 --- /dev/null +++ b/Bindings/display/panel/olimex,lcd-olinuxino.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/olimex,lcd-olinuxino.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Binding for Olimex Ltd. LCD-OLinuXino bridge panel. + +maintainers: + - Stefan Mavrodiev + +description: | + This device can be used as bridge between a host controller and LCD panels. + Currently supported LCDs are: + - LCD-OLinuXino-4.3TS + - LCD-OLinuXino-5 + - LCD-OLinuXino-7 + - LCD-OLinuXino-10 + + The panel itself contains: + - AT24C16C EEPROM holding panel identification and timing requirements + - AR1021 resistive touch screen controller (optional) + - FT5x6 capacitive touch screnn controller (optional) + - GT911/GT928 capacitive touch screen controller (optional) + + The above chips share same I2C bus. The EEPROM is factory preprogrammed with + device information (id, serial, etc.) and timing requirements. + + Touchscreen bingings can be found in these files: + - input/touchscreen/goodix.yaml + - input/touchscreen/edt-ft5x06.txt + - input/touchscreen/ar1021.txt + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: olimex,lcd-olinuxino + + backlight: true + enable-gpios: true + power-supply: true + reg: true + +required: + - compatible + - reg + - power-supply + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + panel@50 { + compatible = "olimex,lcd-olinuxino"; + reg = <0x50>; + power-supply = <®_vcc5v0>; + enable-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + }; + }; + +... diff --git a/Bindings/display/panel/osddisplays,osd101t2587-53ts.txt b/Bindings/display/panel/osddisplays,osd101t2587-53ts.txt deleted file mode 100644 index 9d88e96003fc..000000000000 --- a/Bindings/display/panel/osddisplays,osd101t2587-53ts.txt +++ /dev/null @@ -1,14 +0,0 @@ -One Stop Displays OSD101T2587-53TS 10.1" 1920x1200 panel - -The panel is similar to OSD101T2045-53TS, but it needs additional -MIPI_DSI_TURN_ON_PERIPHERAL message from the host. - -Required properties: -- compatible: should be "osddisplays,osd101t2587-53ts" -- power-supply: as specified in the base binding - -Optional properties: -- backlight: as specified in the base binding - -This binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/Bindings/display/panel/panel-common.yaml b/Bindings/display/panel/panel-common.yaml index ed051ba12084..45fe8fe5faba 100644 --- a/Bindings/display/panel/panel-common.yaml +++ b/Bindings/display/panel/panel-common.yaml @@ -48,9 +48,8 @@ properties: rotation: description: Display rotation in degrees counter clockwise (0,90,180,270) - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 0, 90, 180, 270 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 90, 180, 270] # Display Timings panel-timing: @@ -58,16 +57,14 @@ properties: Most display panels are restricted to a single resolution and require specific display timings. The panel-timing subnode expresses those timings. - allOf: - - $ref: panel-timing.yaml# + $ref: panel-timing.yaml# display-timings: description: - Some display panels supports several resolutions with different timing. + Some display panels support several resolutions with different timings. The display-timings bindings supports specifying several timings and - optional specify which is the native mode. - allOf: - - $ref: display-timings.yaml# + optionally specifying which is the native mode. + $ref: display-timings.yaml# # Connectivity port: @@ -96,6 +93,12 @@ properties: (hot plug detect) signal, but the signal isn't hooked up so we should hardcode the max delay from the panel spec when powering up the panel. + hpd-gpios: + maxItems: 1 + description: + If Hot Plug Detect (HPD) is connected to a GPIO in the system rather + than a dedicated HPD pin the pin can be specified here. + # Control I/Os # Many display panels can be controlled through pins driven by GPIOs. The nature @@ -124,6 +127,13 @@ properties: while active. Active high reset signals can be supported by inverting the GPIO specifier polarity flag. + te-gpios: + maxItems: 1 + description: + GPIO spec for the tearing effect synchronization signal. + The tearing effect signal is active high. Active low signals can be + supported by inverting the GPIO specifier polarity flag. + # Power power-supply: description: diff --git a/Bindings/display/panel/panel-simple-dsi.yaml b/Bindings/display/panel/panel-simple-dsi.yaml index b2e8742fd6af..16778ce782fc 100644 --- a/Bindings/display/panel/panel-simple-dsi.yaml +++ b/Bindings/display/panel/panel-simple-dsi.yaml @@ -29,6 +29,20 @@ properties: # compatible must be listed in alphabetical order, ordered by compatible. # The description in the comment is mandatory for each compatible. + # AU Optronics Corporation 8.0" WUXGA TFT LCD panel + - auo,b080uan01 + # Boe Corporation 8.0" WUXGA TFT LCD panel + - boe,tv080wum-nl0 + # Kingdisplay KD097D04 9.7" 1536x2048 TFT LCD panel + - kingdisplay,kd097d04 + # LG ACX467AKM-7 4.95" 1080×1920 LCD Panel + - lg,acx467akm-7 + # LG Corporation 7" WXGA TFT LCD panel + - lg,ld070wx3-sl01 + # One Stop Displays OSD101T2587-53TS 10.1" 1920x1200 panel + - osddisplays,osd101t2587-53ts + # Panasonic 10" WUXGA TFT LCD panel + - panasonic,vvx10f004b00 # Panasonic 10" WUXGA TFT LCD panel - panasonic,vvx10f034n00 diff --git a/Bindings/display/panel/panel-simple.yaml b/Bindings/display/panel/panel-simple.yaml index 393ffc6acbba..d6cca1479633 100644 --- a/Bindings/display/panel/panel-simple.yaml +++ b/Bindings/display/panel/panel-simple.yaml @@ -33,8 +33,6 @@ properties: - ampire,am-480272h3tmqw-t01h # Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel - ampire,am800480r3tmqwa1h - # AU Optronics Corporation 8.0" WUXGA TFT LCD panel - - auo,b080uan01 # AU Optronics Corporation 10.1" WSVGA TFT LCD panel - auo,b101aw03 # AU Optronics Corporation 10.1" WSVGA TFT LCD panel @@ -55,10 +53,16 @@ properties: - auo,g101evn010 # AU Optronics Corporation 10.4" (800x600) color TFT LCD panel - auo,g104sn02 + # AU Optronics Corporation 12.1" (1280x800) TFT LCD panel + - auo,g121ean01 # AU Optronics Corporation 13.3" FHD (1920x1080) TFT LCD panel - auo,g133han01 + # AU Optronics Corporation 15.6" (1366x768) TFT LCD panel + - auo,g156xtn01 # AU Optronics Corporation 18.5" FHD (1920x1080) TFT LCD panel - auo,g185han01 + # AU Optronics Corporation 19.0" (1280x1024) TFT LCD panel + - auo,g190ean01 # AU Optronics Corporation 31.5" FHD (1920x1080) TFT LCD panel - auo,p320hvn03 # AU Optronics Corporation 21.5" FHD (1920x1080) color TFT LCD panel @@ -69,10 +73,12 @@ properties: - boe,hv070wsa-100 # BOE OPTOELECTRONICS TECHNOLOGY 10.1" WXGA TFT LCD panel - boe,nv101wxmn51 + # BOE NV133FHM-N61 13.3" FHD (1920x1080) TFT LCD Panel + - boe,nv133fhm-n61 + # BOE NV133FHM-N62 13.3" FHD (1920x1080) TFT LCD Panel + - boe,nv133fhm-n62 # BOE NV140FHM-N49 14.0" FHD a-Si FT panel - boe,nv140fhmn49 - # Boe Corporation 8.0" WUXGA TFT LCD panel - - boe,tv080wum-nl0 # CDTech(H.K.) Electronics Limited 4.3" 480x272 color TFT-LCD panel - cdtech,s043wq26h-ct7 # CDTech(H.K.) Electronics Limited 7" 800x480 color TFT-LCD panel @@ -82,6 +88,8 @@ properties: # Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel - chunghwa,claa101wa01a # Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel + - chunghwa,claa101wb01 + # Chunghwa Picture Tubes Ltd. 10.1" WXGA TFT LCD panel - chunghwa,claa101wb03 # DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface. - dataimage,scf0700c48ggu18 @@ -127,6 +135,8 @@ properties: - hannstar,hsd100pxn1 # Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel - hit,tx23d38vm0caa + # InfoVision Optoelectronics M133NWF4 R0 13.3" FHD (1920x1080) TFT LCD panel + - ivo,m133nwf4-r0 # Innolux AT043TN24 4.3" WQVGA TFT LCD panel - innolux,at043tn24 # Innolux AT070TN92 7.0" WQVGA TFT LCD panel @@ -155,6 +165,8 @@ properties: - lemaker,bl035-rgb-002 # LG 7" (800x480 pixels) TFT LCD panel - lg,lb070wv8 + # LG Corporation 5" HD TFT LCD panel + - lg,lh500wx1-sd03 # LG LP079QX1-SP0V 7.9" (1536x2048 pixels) TFT LCD panel - lg,lp079qx1-sp0v # LG 9.7" (2048x1536 pixels) TFT LCD panel @@ -227,6 +239,8 @@ properties: - sharp,ls020b1dd01d # Shelly SCA07010-BFN-LNN 7.0" WVGA TFT LCD panel - shelly,sca07010-bfn-lnn + # Starry KR070PE2T 7" WVGA TFT LCD panel + - starry,kr070pe2t # Starry 12.2" (1920x1200 pixels) TFT LCD panel - starry,kr122ea0sra # Tianma Micro-electronics TM070JDHG30 7.0" WXGA TFT LCD panel diff --git a/Bindings/display/panel/panel-timing.yaml b/Bindings/display/panel/panel-timing.yaml index bd558ad7891f..182c19cb7fdd 100644 --- a/Bindings/display/panel/panel-timing.yaml +++ b/Bindings/display/panel/panel-timing.yaml @@ -72,92 +72,80 @@ properties: hfront-porch: description: Horizontal front porch panel timing oneOf: - - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - maxItems: 1 - items: - description: typical number of pixels - - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 3 - maxItems: 3 - items: - description: min, typ, max number of pixels + - $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + items: + description: typical number of pixels + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + items: + description: min, typ, max number of pixels hback-porch: description: Horizontal back porch timing oneOf: - - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - maxItems: 1 - items: - description: typical number of pixels - - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 3 - maxItems: 3 - items: - description: min, typ, max number of pixels + - $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + items: + description: typical number of pixels + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + items: + description: min, typ, max number of pixels hsync-len: description: Horizontal sync length panel timing oneOf: - - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - maxItems: 1 - items: - description: typical number of pixels - - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 3 - maxItems: 3 - items: - description: min, typ, max number of pixels + - $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + items: + description: typical number of pixels + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + items: + description: min, typ, max number of pixels vfront-porch: description: Vertical front porch panel timing oneOf: - - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - maxItems: 1 - items: - description: typical number of lines - - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 3 - maxItems: 3 - items: - description: min, typ, max number of lines + - $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + items: + description: typical number of lines + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + items: + description: min, typ, max number of lines vback-porch: description: Vertical back porch panel timing oneOf: - - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - maxItems: 1 - items: - description: typical number of lines - - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 3 - maxItems: 3 - items: - description: min, typ, max number of lines + - $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + items: + description: typical number of lines + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + items: + description: min, typ, max number of lines vsync-len: description: Vertical sync length panel timing oneOf: - - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - maxItems: 1 - items: - description: typical number of lines - - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 3 - maxItems: 3 - items: - description: min, typ, max number of lines + - $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 + items: + description: typical number of lines + - $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + items: + description: min, typ, max number of lines hsync-active: description: | diff --git a/Bindings/display/panel/raydium,rm67191.txt b/Bindings/display/panel/raydium,rm67191.txt deleted file mode 100644 index 10424695aa02..000000000000 --- a/Bindings/display/panel/raydium,rm67191.txt +++ /dev/null @@ -1,41 +0,0 @@ -Raydium RM67171 OLED LCD panel with MIPI-DSI protocol - -Required properties: -- compatible: "raydium,rm67191" -- reg: virtual channel for MIPI-DSI protocol - must be <0> -- dsi-lanes: number of DSI lanes to be used - must be <3> or <4> -- port: input port node with endpoint definition as - defined in Documentation/devicetree/bindings/graph.txt; - the input port should be connected to a MIPI-DSI device - driver - -Optional properties: -- reset-gpios: a GPIO spec for the RST_B GPIO pin -- v3p3-supply: phandle to 3.3V regulator that powers the VDD_3V3 pin -- v1p8-supply: phandle to 1.8V regulator that powers the VDD_1V8 pin -- width-mm: see panel-common.txt -- height-mm: see panel-common.txt -- video-mode: 0 - burst-mode - 1 - non-burst with sync event - 2 - non-burst with sync pulse - -Example: - - panel@0 { - compatible = "raydium,rm67191"; - reg = <0>; - pinctrl-0 = <&pinctrl_mipi_dsi_0_1_en>; - pinctrl-names = "default"; - reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - dsi-lanes = <4>; - width-mm = <68>; - height-mm = <121>; - - port { - panel_in: endpoint { - remote-endpoint = <&mipi_out>; - }; - }; - }; diff --git a/Bindings/display/panel/raydium,rm67191.yaml b/Bindings/display/panel/raydium,rm67191.yaml new file mode 100644 index 000000000000..745dd247c409 --- /dev/null +++ b/Bindings/display/panel/raydium,rm67191.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/raydium,rm67191.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Raydium RM67171 OLED LCD panel with MIPI-DSI protocol + +maintainers: + - Robert Chiras + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: raydium,rm67191 + + reg: true + port: true + reset-gpios: true + width-mm: true + height-mm: true + + dsi-lanes: + description: Number of DSI lanes to be used must be <3> or <4> + enum: [3, 4] + + v3p3-supply: + description: phandle to 3.3V regulator that powers the VDD_3V3 pin + + v1p8-supply: + description: phandle to 1.8V regulator that powers the VDD_1V8 pin + + video-mode: + description: | + 0 - burst-mode + 1 - non-burst with sync event + 2 - non-burst with sync pulse + enum: [0, 1, 2] + +required: + - compatible + - reg + - dsi-lanes + - port + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "raydium,rm67191"; + reg = <0>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + width-mm = <68>; + height-mm = <121>; + video-mode = <1>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_out>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/panel/samsung,amoled-mipi-dsi.yaml b/Bindings/display/panel/samsung,amoled-mipi-dsi.yaml new file mode 100644 index 000000000000..96bdde9298e0 --- /dev/null +++ b/Bindings/display/panel/samsung,amoled-mipi-dsi.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,amoled-mipi-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung AMOLED MIPI-DSI panels + +maintainers: + - Hoegeun Kwon + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + enum: + # Samsung S6E63J0X03 1.63" 320x320 AMOLED panel + - samsung,s6e63j0x03 + # Samsung S6E3HA2 5.7" 1440x2560 AMOLED panel + - samsung,s6e3ha2 + # Samsung S6E3HF2 5.65" 1600x2560 AMOLED panel + - samsung,s6e3hf2 + + reg: true + reset-gpios: true + enable-gpios: true + te-gpios: true + + vdd3-supply: + description: I/O voltage supply + + vci-supply: + description: voltage supply for analog circuits + +required: + - compatible + - reg + - vdd3-supply + - vci-supply + - reset-gpios + - enable-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,s6e3ha2"; + reg = <0>; + vdd3-supply = <&ldo27_reg>; + vci-supply = <&ldo28_reg>; + reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>; + te-gpios = <&gpf1 3 GPIO_ACTIVE_HIGH>; + }; + }; + +... diff --git a/Bindings/display/panel/samsung,ld9040.txt b/Bindings/display/panel/samsung,ld9040.txt deleted file mode 100644 index 354d4d1df4ff..000000000000 --- a/Bindings/display/panel/samsung,ld9040.txt +++ /dev/null @@ -1,66 +0,0 @@ -Samsung LD9040 AMOLED LCD parallel RGB panel with SPI control bus - -Required properties: - - compatible: "samsung,ld9040" - - reg: address of the panel on SPI bus - - vdd3-supply: core voltage supply - - vci-supply: voltage supply for analog circuits - - reset-gpios: a GPIO spec for the reset pin - - display-timings: timings for the connected panel according to [1] - -The panel must obey rules for SPI slave device specified in document [2]. - -Optional properties: - - power-on-delay: delay after turning regulators on [ms] - - reset-delay: delay after reset sequence [ms] - - panel-width-mm: physical panel width [mm] - - panel-height-mm: physical panel height [mm] - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in [3]. This -node should describe panel's video bus. - -[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt -[2]: Documentation/devicetree/bindings/spi/spi-bus.txt -[3]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - - lcd@0 { - compatible = "samsung,ld9040"; - reg = <0>; - vdd3-supply = <&ldo7_reg>; - vci-supply = <&ldo17_reg>; - reset-gpios = <&gpy4 5 0>; - spi-max-frequency = <1200000>; - spi-cpol; - spi-cpha; - power-on-delay = <10>; - reset-delay = <10>; - panel-width-mm = <90>; - panel-height-mm = <154>; - - display-timings { - timing { - clock-frequency = <23492370>; - hactive = <480>; - vactive = <800>; - hback-porch = <16>; - hfront-porch = <16>; - vback-porch = <2>; - vfront-porch = <28>; - hsync-len = <2>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <0>; - pixelclk-active = <0>; - }; - }; - - port { - lcd_ep: endpoint { - remote-endpoint = <&fimd_dpi_ep>; - }; - }; - }; diff --git a/Bindings/display/panel/samsung,ld9040.yaml b/Bindings/display/panel/samsung,ld9040.yaml new file mode 100644 index 000000000000..060ee27a4749 --- /dev/null +++ b/Bindings/display/panel/samsung,ld9040.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,ld9040.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung LD9040 AMOLED LCD parallel RGB panel with SPI control bus + +description: | + The panel must obey the rules for a SPI slave device as specified in + spi/spi-controller.yaml + +maintainers: + - Andrzej Hajda + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: samsung,ld9040 + + display-timings: true + port: true + reg: true + reset-gpios: true + + vdd3-supply: + description: core voltage supply + + vci-supply: + description: voltage supply for analog circuits + + power-on-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: delay after turning regulators on [ms] + + reset-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: delay after reset sequence [ms] + + panel-width-mm: + description: physical panel width [mm] + + panel-height-mm: + description: physical panel height [mm] + +required: + - compatible + - reg + - vdd3-supply + - vci-supply + - reset-gpios + - display-timings + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + lcd@0 { + compatible = "samsung,ld9040"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + vdd3-supply = <&ldo7_reg>; + vci-supply = <&ldo17_reg>; + reset-gpios = <&gpy4 5 0>; + spi-max-frequency = <1200000>; + spi-cpol; + spi-cpha; + power-on-delay = <10>; + reset-delay = <10>; + panel-width-mm = <90>; + panel-height-mm = <154>; + + display-timings { + timing { + clock-frequency = <23492370>; + hactive = <480>; + vactive = <800>; + hback-porch = <16>; + hfront-porch = <16>; + vback-porch = <2>; + vfront-porch = <28>; + hsync-len = <2>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_dpi_ep>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/panel/samsung,s6d16d0.txt b/Bindings/display/panel/samsung,s6d16d0.txt deleted file mode 100644 index b94e366f451b..000000000000 --- a/Bindings/display/panel/samsung,s6d16d0.txt +++ /dev/null @@ -1,30 +0,0 @@ -Samsung S6D16D0 4" 864x480 AMOLED panel - -Required properties: - - compatible: should be: - "samsung,s6d16d0", - - reg: the virtual channel number of a DSI peripheral - - vdd1-supply: I/O voltage supply - - reset-gpios: a GPIO spec for the reset pin (active low) - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in -media/video-interfaces.txt. This node should describe panel's video bus. - -Example: -&dsi { - ... - - panel@0 { - compatible = "samsung,s6d16d0"; - reg = <0>; - vdd1-supply = <&foo>; - reset-gpios = <&foo_gpio 0 GPIO_ACTIVE_LOW>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi_out>; - }; - }; - }; -}; diff --git a/Bindings/display/panel/samsung,s6d16d0.yaml b/Bindings/display/panel/samsung,s6d16d0.yaml new file mode 100644 index 000000000000..66d147496bc3 --- /dev/null +++ b/Bindings/display/panel/samsung,s6d16d0.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,s6d16d0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S6D16D0 4" 864x480 AMOLED panel + +maintainers: + - Linus Walleij + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: samsung,s6d16d0 + + port: true + reg: true + reset-gpios: true + + vdd1-supply: + description: I/O voltage supply + +required: + - compatible + - reg + - vdd1-supply + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,s6d16d0"; + reg = <0>; + vdd1-supply = <&foo>; + reset-gpios = <&foo_gpio 0 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/panel/samsung,s6e3ha2.txt b/Bindings/display/panel/samsung,s6e3ha2.txt deleted file mode 100644 index 4acea25c244b..000000000000 --- a/Bindings/display/panel/samsung,s6e3ha2.txt +++ /dev/null @@ -1,31 +0,0 @@ -Samsung S6E3HA2 5.7" 1440x2560 AMOLED panel -Samsung S6E3HF2 5.65" 1600x2560 AMOLED panel - -Required properties: - - compatible: should be one of: - "samsung,s6e3ha2", - "samsung,s6e3hf2". - - reg: the virtual channel number of a DSI peripheral - - vdd3-supply: I/O voltage supply - - vci-supply: voltage supply for analog circuits - - reset-gpios: a GPIO spec for the reset pin (active low) - - enable-gpios: a GPIO spec for the panel enable pin (active high) - -Optional properties: - - te-gpios: a GPIO spec for the tearing effect synchronization signal - gpio pin (active high) - -Example: -&dsi { - ... - - panel@0 { - compatible = "samsung,s6e3ha2"; - reg = <0>; - vdd3-supply = <&ldo27_reg>; - vci-supply = <&ldo28_reg>; - reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>; - enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>; - te-gpios = <&gpf1 3 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/Bindings/display/panel/samsung,s6e63j0x03.txt b/Bindings/display/panel/samsung,s6e63j0x03.txt deleted file mode 100644 index 3f1a8392af7f..000000000000 --- a/Bindings/display/panel/samsung,s6e63j0x03.txt +++ /dev/null @@ -1,24 +0,0 @@ -Samsung S6E63J0X03 1.63" 320x320 AMOLED panel (interface: MIPI-DSI command mode) - -Required properties: - - compatible: "samsung,s6e63j0x03" - - reg: the virtual channel number of a DSI peripheral - - vdd3-supply: I/O voltage supply - - vci-supply: voltage supply for analog circuits - - reset-gpios: a GPIO spec for the reset pin (active low) - - te-gpios: a GPIO spec for the tearing effect synchronization signal - gpio pin (active high) - -Example: -&dsi { - ... - - panel@0 { - compatible = "samsung,s6e63j0x03"; - reg = <0>; - vdd3-supply = <&ldo16_reg>; - vci-supply = <&ldo20_reg>; - reset-gpios = <&gpe0 1 GPIO_ACTIVE_LOW>; - te-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>; - }; -}; diff --git a/Bindings/display/panel/samsung,s6e63m0.txt b/Bindings/display/panel/samsung,s6e63m0.txt deleted file mode 100644 index 9fb9ebeef8e4..000000000000 --- a/Bindings/display/panel/samsung,s6e63m0.txt +++ /dev/null @@ -1,33 +0,0 @@ -Samsung s6e63m0 AMOLED LCD panel - -Required properties: - - compatible: "samsung,s6e63m0" - - reset-gpios: GPIO spec for reset pin - - vdd3-supply: VDD regulator - - vci-supply: VCI regulator - -The panel must obey rules for SPI slave device specified in document [1]. - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in [2]. This -node should describe panel's video bus. - -[1]: Documentation/devicetree/bindings/spi/spi-bus.txt -[2]: Documentation/devicetree/bindings/media/video-interfaces.txt - -Example: - - s6e63m0: display@0 { - compatible = "samsung,s6e63m0"; - reg = <0>; - reset-gpio = <&mp05 5 1>; - vdd3-supply = <&ldo12_reg>; - vci-supply = <&ldo11_reg>; - spi-max-frequency = <1200000>; - - port { - lcd_ep: endpoint { - remote-endpoint = <&fimd_ep>; - }; - }; - }; diff --git a/Bindings/display/panel/samsung,s6e63m0.yaml b/Bindings/display/panel/samsung,s6e63m0.yaml new file mode 100644 index 000000000000..1dab80ae1d0a --- /dev/null +++ b/Bindings/display/panel/samsung,s6e63m0.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,s6e63m0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung s6e63m0 AMOLED LCD panel + +maintainers: + - Jonathan Bakker + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: samsung,s6e63m0 + + reg: true + reset-gpios: true + port: true + + vdd3-supply: + description: VDD regulator + + vci-supply: + description: VCI regulator + +required: + - compatible + - reset-gpios + - vdd3-supply + - vci-supply + - port + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + display@0 { + compatible = "samsung,s6e63m0"; + reg = <0>; + reset-gpios = <&mp05 5 1>; + vdd3-supply = <&ldo12_reg>; + vci-supply = <&ldo11_reg>; + spi-max-frequency = <1200000>; + + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_ep>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/panel/seiko,43wvf1g.txt b/Bindings/display/panel/seiko,43wvf1g.txt deleted file mode 100644 index aae57ef36cdd..000000000000 --- a/Bindings/display/panel/seiko,43wvf1g.txt +++ /dev/null @@ -1,23 +0,0 @@ -Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel - -Required properties: -- compatible: should be "sii,43wvf1g". -- "dvdd-supply": 3v3 digital regulator. -- "avdd-supply": 5v analog regulator. - -Optional properties: -- backlight: phandle for the backlight control. - -Example: - - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; diff --git a/Bindings/display/panel/seiko,43wvf1g.yaml b/Bindings/display/panel/seiko,43wvf1g.yaml new file mode 100644 index 000000000000..cfaa50cf5f5d --- /dev/null +++ b/Bindings/display/panel/seiko,43wvf1g.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/seiko,43wvf1g.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel + +maintainers: + - Marco Franchi + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sii,43wvf1g + + backlight: true + port: true + + dvdd-supply: + description: 3v3 digital regulator + + avdd-supply: + description: 5v analog regulator + +required: + - compatible + - dvdd-supply + - avdd-supply + +additionalProperties: false + +examples: + - | + panel { + compatible = "sii,43wvf1g"; + + backlight = <&backlight_display>; + dvdd-supply = <®_lcd_3v3>; + avdd-supply = <®_lcd_5v>; + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + +... diff --git a/Bindings/display/panel/sharp,lq150x1lg11.txt b/Bindings/display/panel/sharp,lq150x1lg11.txt deleted file mode 100644 index 0f57c3143506..000000000000 --- a/Bindings/display/panel/sharp,lq150x1lg11.txt +++ /dev/null @@ -1,36 +0,0 @@ -Sharp 15" LQ150X1LG11 XGA TFT LCD panel - -Required properties: -- compatible: should be "sharp,lq150x1lg11" -- power-supply: regulator to provide the VCC supply voltage (3.3 volts) - -Optional properties: -- backlight: phandle of the backlight device -- rlud-gpios: a single GPIO for the RL/UD (rotate 180 degrees) pin. -- sellvds-gpios: a single GPIO for the SELLVDS pin. - -If rlud-gpios and/or sellvds-gpios are not specified, the RL/UD and/or SELLVDS -pins are assumed to be handled appropriately by the hardware. - -Example: - - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm 0 100000>; /* VBR */ - - brightness-levels = <0 20 40 60 80 100>; - default-brightness-level = <2>; - - power-supply = <&vdd_12v_reg>; /* VDD */ - enable-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; /* XSTABY */ - }; - - panel { - compatible = "sharp,lq150x1lg11"; - - power-supply = <&vcc_3v3_reg>; /* VCC */ - - backlight = <&backlight>; - rlud-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* RL/UD */ - sellvds-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; /* SELLVDS */ - }; diff --git a/Bindings/display/panel/sharp,lq150x1lg11.yaml b/Bindings/display/panel/sharp,lq150x1lg11.yaml new file mode 100644 index 000000000000..92f2d12f4f4c --- /dev/null +++ b/Bindings/display/panel/sharp,lq150x1lg11.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sharp,lq150x1lg11.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sharp 15" LQ150X1LG11 XGA TFT LCD panel + +maintainers: + - Peter Rosin + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sharp,lq150x1lg11 + + power-supply: true + backlight: true + + rlud-gpios: + maxItems: 1 + description: | + GPIO for the RL/UD (rotate 180 degrees) pin. + If rlud-gpios and/or sellvds-gpios are not specified, + the RL/UD and/or SELLVDS pins are assumed to be handled + appropriately by the hardware. + + sellvds-gpios: + maxItems: 1 + description: | + GPIO for the SELLVDS pin. + If rlud-gpios and/or sellvds-gpios are not specified, + the RL/UD and/or SELLVDS pins are assumed to be handled + appropriately by the hardware. + +required: + - compatible + - power-supply + +additionalProperties: false + +examples: + - | + #include + + panel { + compatible = "sharp,lq150x1lg11"; + + power-supply = <&vcc_3v3_reg>; /* VCC */ + + backlight = <&backlight>; + rlud-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; /* RL/UD */ + sellvds-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; /* SELLVDS */ + }; + +... diff --git a/Bindings/display/panel/sharp,ls037v7dw01.txt b/Bindings/display/panel/sharp,ls037v7dw01.txt deleted file mode 100644 index 0cc8981e9d49..000000000000 --- a/Bindings/display/panel/sharp,ls037v7dw01.txt +++ /dev/null @@ -1,43 +0,0 @@ -SHARP LS037V7DW01 TFT-LCD panel -=================================== - -Required properties: -- compatible: "sharp,ls037v7dw01" - -Optional properties: -- label: a symbolic name for the panel -- enable-gpios: a GPIO spec for the optional enable pin. - This pin is the INI pin as specified in the LS037V7DW01.pdf file. -- reset-gpios: a GPIO spec for the optional reset pin. - This pin is the RESB pin as specified in the LS037V7DW01.pdf file. -- mode-gpios: a GPIO - ordered MO, LR, and UD as specified in the LS037V7DW01.pdf file. - -Required nodes: -- Video port for DPI input - -This panel can have zero to five GPIOs to configure to change configuration -between QVGA and VGA mode and the scan direction. As these pins can be also -configured with external pulls, all the GPIOs are considered optional with holes -in the array. - -Example -------- - -Example when connected to a omap2+ based device: - -lcd0: display { - compatible = "sharp,ls037v7dw01"; - power-supply = <&lcd_3v3>; - enable-gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; /* gpio152, lcd INI */ - reset-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd RESB */ - mode-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH /* gpio154, lcd MO */ - &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */ - &gpio1 3 GPIO_ACTIVE_HIGH>; /* gpio3, lcd UD */ - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; -}; diff --git a/Bindings/display/panel/sharp,ls037v7dw01.yaml b/Bindings/display/panel/sharp,ls037v7dw01.yaml new file mode 100644 index 000000000000..8c47a9b0b507 --- /dev/null +++ b/Bindings/display/panel/sharp,ls037v7dw01.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sharp,ls037v7dw01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SHARP LS037V7DW01 TFT-LCD panel + +description: | + This panel can have zero to five GPIOs to configure to change configuration + between QVGA and VGA mode and the scan direction. As these pins can be also + configured with external pulls, all the GPIOs are considered optional with holes + in the array. + +maintainers: + - Tony Lindgren + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sharp,ls037v7dw01 + + label: true + enable-gpios: true + reset-gpios: true + port: true + power-supply: true + + mode-gpios: + minItems: 1 + maxItems: 3 + description: | + GPIO ordered MO, LR, and UD as specified in LS037V7DW01.pdf + This panel can have zero to three GPIOs to configure to + change configuration between QVGA and VGA mode and the + scan direction. As these pins can be also configured + with external pulls, all the GPIOs are considered + optional with holes in the array. + +required: + - compatible + - port + +additionalProperties: false + +examples: + - | + #include + + lcd0: display { + compatible = "sharp,ls037v7dw01"; + power-supply = <&lcd_3v3>; + enable-gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; /* gpio152, lcd INI */ + reset-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd RESB */ + mode-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH /* gpio154, lcd MO */ + &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */ + &gpio1 3 GPIO_ACTIVE_HIGH>; /* gpio3, lcd UD */ + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + +... diff --git a/Bindings/display/panel/sharp,ls043t1le01.txt b/Bindings/display/panel/sharp,ls043t1le01.txt deleted file mode 100644 index 3770a111968b..000000000000 --- a/Bindings/display/panel/sharp,ls043t1le01.txt +++ /dev/null @@ -1,22 +0,0 @@ -Sharp Microelectronics 4.3" qHD TFT LCD panel - -Required properties: -- compatible: should be "sharp,ls043t1le01-qhd" -- reg: DSI virtual channel of the peripheral -- power-supply: phandle of the regulator that provides the supply voltage - -Optional properties: -- backlight: phandle of the backlight device attached to the panel -- reset-gpios: a GPIO spec for the reset pin - -Example: - - mdss_dsi@fd922800 { - panel@0 { - compatible = "sharp,ls043t1le01-qhd"; - reg = <0>; - avdd-supply = <&pm8941_l22>; - backlight = <&pm8941_wled>; - reset-gpios = <&pm8941_gpios 19 GPIO_ACTIVE_HIGH>; - }; - }; diff --git a/Bindings/display/panel/sharp,ls043t1le01.yaml b/Bindings/display/panel/sharp,ls043t1le01.yaml new file mode 100644 index 000000000000..a90d0d8bf7c9 --- /dev/null +++ b/Bindings/display/panel/sharp,ls043t1le01.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sharp,ls043t1le01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sharp Microelectronics 4.3" qHD TFT LCD panel + +maintainers: + - Werner Johansson + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sharp,ls043t1le01-qhd + + reg: true + backlight: true + reset-gpios: true + port: true + + avdd-supply: + description: handle of the regulator that provides the supply voltage + +required: + - compatible + - reg + - avdd-supply + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "sharp,ls043t1le01-qhd"; + reg = <0>; + avdd-supply = <&pm8941_l22>; + backlight = <&pm8941_wled>; + reset-gpios = <&pm8941_gpios 19 GPIO_ACTIVE_HIGH>; + }; + }; + +... diff --git a/Bindings/display/panel/simple-panel.txt b/Bindings/display/panel/simple-panel.txt deleted file mode 100644 index e11208fb7da8..000000000000 --- a/Bindings/display/panel/simple-panel.txt +++ /dev/null @@ -1 +0,0 @@ -See panel-common.yaml in this directory. diff --git a/Bindings/display/panel/sitronix,st7701.txt b/Bindings/display/panel/sitronix,st7701.txt deleted file mode 100644 index ccd17597f1f6..000000000000 --- a/Bindings/display/panel/sitronix,st7701.txt +++ /dev/null @@ -1,30 +0,0 @@ -Sitronix ST7701 based LCD panels - -ST7701 designed for small and medium sizes of TFT LCD display, is -capable of supporting up to 480RGBX864 in resolution. It provides -several system interfaces like MIPI/RGB/SPI. - -Techstar TS8550B is 480x854, 2-lane MIPI DSI LCD panel which has -inbuilt ST7701 chip. - -Required properties: -- compatible: must be "sitronix,st7701" and one of - * "techstar,ts8550b" -- reset-gpios: a GPIO phandle for the reset pin - -Required properties for techstar,ts8550b: -- reg: DSI virtual channel used by that screen -- VCC-supply: analog regulator for MIPI circuit -- IOVCC-supply: I/O system regulator - -Optional properties: -- backlight: phandle for the backlight control. - -panel@0 { - compatible = "techstar,ts8550b", "sitronix,st7701"; - reg = <0>; - VCC-supply = <®_dldo2>; - IOVCC-supply = <®_dldo2>; - reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */ - backlight = <&backlight>; -}; diff --git a/Bindings/display/panel/sitronix,st7701.yaml b/Bindings/display/panel/sitronix,st7701.yaml new file mode 100644 index 000000000000..6dff59fe4be1 --- /dev/null +++ b/Bindings/display/panel/sitronix,st7701.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sitronix,st7701.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sitronix ST7701 based LCD panels + +maintainers: + - Jagan Teki + +description: | + ST7701 designed for small and medium sizes of TFT LCD display, is + capable of supporting up to 480RGBX864 in resolution. It provides + several system interfaces like MIPI/RGB/SPI. + + Techstar TS8550B is 480x854, 2-lane MIPI DSI LCD panel which has + inbuilt ST7701 chip. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - techstar,ts8550b + - const: sitronix,st7701 + + reg: + description: DSI virtual channel used by that screen + maxItems: 1 + + VCC-supply: + description: analog regulator for MIPI circuit + + IOVCC-supply: + description: I/O system regulator + + reset-gpios: true + + backlight: true + +required: + - compatible + - reg + - VCC-supply + - IOVCC-supply + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "techstar,ts8550b", "sitronix,st7701"; + reg = <0>; + VCC-supply = <®_dldo2>; + IOVCC-supply = <®_dldo2>; + reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */ + backlight = <&backlight>; + }; + }; diff --git a/Bindings/display/panel/sitronix,st7789v.txt b/Bindings/display/panel/sitronix,st7789v.txt deleted file mode 100644 index c6995dde641b..000000000000 --- a/Bindings/display/panel/sitronix,st7789v.txt +++ /dev/null @@ -1,37 +0,0 @@ -Sitronix ST7789V RGB panel with SPI control bus - -Required properties: - - compatible: "sitronix,st7789v" - - reg: Chip select of the panel on the SPI bus - - reset-gpios: a GPIO phandle for the reset pin - - power-supply: phandle of the regulator that provides the supply voltage - -Optional properties: - - backlight: phandle to the backlight used - -The generic bindings for the SPI slaves documented in [1] also applies - -The device node can contain one 'port' child node with one child -'endpoint' node, according to the bindings defined in [2]. This -node should describe panel's video bus. - -[1]: Documentation/devicetree/bindings/spi/spi-bus.txt -[2]: Documentation/devicetree/bindings/graph.txt - -Example: - -panel@0 { - compatible = "sitronix,st7789v"; - reg = <0>; - reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; - backlight = <&pwm_bl>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - port { - panel_input: endpoint { - remote-endpoint = <&tcon0_out_panel>; - }; - }; -}; diff --git a/Bindings/display/panel/sitronix,st7789v.yaml b/Bindings/display/panel/sitronix,st7789v.yaml new file mode 100644 index 000000000000..fa46d151e7b3 --- /dev/null +++ b/Bindings/display/panel/sitronix,st7789v.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sitronix,st7789v.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sitronix ST7789V RGB panel with SPI control bus + +description: | + The panel must obey the rules for a SPI slave device as specified in + spi/spi-controller.yaml + +maintainers: + - Maxime Ripard + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sitronix,st7789v + + reg: true + reset-gpios: true + power-supply: true + backlight: true + port: true + +required: + - compatible + - reg + - reset-gpios + - power-supply + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; + backlight = <&pwm_bl>; + power-supply = <&power>; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + + port { + panel_input: endpoint { + remote-endpoint = <&tcon0_out_panel>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/panel/sony,acx424akp.yaml b/Bindings/display/panel/sony,acx424akp.yaml index 185dcc8fd1f9..78d060097052 100644 --- a/Bindings/display/panel/sony,acx424akp.yaml +++ b/Bindings/display/panel/sony,acx424akp.yaml @@ -18,7 +18,7 @@ properties: reg: true reset-gpios: true vddi-supply: - description: regulator that supplies the vddi voltage + description: regulator that supplies the vddi voltage enforce-video-mode: true required: diff --git a/Bindings/display/panel/sony,acx565akm.txt b/Bindings/display/panel/sony,acx565akm.txt deleted file mode 100644 index e12333280749..000000000000 --- a/Bindings/display/panel/sony,acx565akm.txt +++ /dev/null @@ -1,30 +0,0 @@ -Sony ACX565AKM SDI Panel -======================== - -Required properties: -- compatible: "sony,acx565akm" - -Optional properties: -- label: a symbolic name for the panel -- reset-gpios: panel reset gpio - -Required nodes: -- Video port for SDI input - -Example -------- - -acx565akm@2 { - compatible = "sony,acx565akm"; - spi-max-frequency = <6000000>; - reg = <2>; - - label = "lcd"; - reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */ - - port { - lcd_in: endpoint { - remote-endpoint = <&sdi_out>; - }; - }; -}; diff --git a/Bindings/display/panel/sony,acx565akm.yaml b/Bindings/display/panel/sony,acx565akm.yaml new file mode 100644 index 000000000000..95d053c548ab --- /dev/null +++ b/Bindings/display/panel/sony,acx565akm.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/sony,acx565akm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony ACX565AKM SDI Panel + +description: | + The panel must obey the rules for a SPI slave device as specified in + spi/spi-controller.yaml + +maintainers: + - Tomi Valkeinen + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: sony,acx565akm + + label: true + reset-gpios: true + port: true + +required: + - compatible + - port + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + panel@2 { + compatible = "sony,acx565akm"; + spi-max-frequency = <6000000>; + reg = <2>; + + label = "lcd"; + reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */ + + port { + lcd_in: endpoint { + remote-endpoint = <&sdi_out>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/panel/startek,startek-kd050c.txt b/Bindings/display/panel/startek,startek-kd050c.txt deleted file mode 100644 index 70cd8d18d841..000000000000 --- a/Bindings/display/panel/startek,startek-kd050c.txt +++ /dev/null @@ -1,4 +0,0 @@ -Startek Electronic Technology Co. KD050C 5.0" WVGA TFT LCD panel - -Required properties: -- compatible: should be "startek,startek-kd050c" diff --git a/Bindings/display/panel/startek,startek-kd050c.yaml b/Bindings/display/panel/startek,startek-kd050c.yaml new file mode 100644 index 000000000000..fd668640afd1 --- /dev/null +++ b/Bindings/display/panel/startek,startek-kd050c.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/startek,startek-kd050c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Startek Electronic Technology Co. KD050C 5.0" WVGA TFT LCD panel + +maintainers: + - Nikita Kiryanov + +allOf: + - $ref: panel-dpi.yaml# + +properties: + compatible: + items: + - const: startek,startek-kd050c + - {} # panel-dpi, but not listed here to avoid false select + + backlight: true + enable-gpios: true + height-mm: true + label: true + panel-timing: true + port: true + power-supply: true + reset-gpios: true + width-mm: true + +additionalProperties: false + +... diff --git a/Bindings/display/panel/tpo,td.yaml b/Bindings/display/panel/tpo,td.yaml new file mode 100644 index 000000000000..4aa605613445 --- /dev/null +++ b/Bindings/display/panel/tpo,td.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/tpo,td.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toppoly TD Panels + +description: | + The panel must obey the rules for a SPI slave device as specified in + spi/spi-controller.yaml + +maintainers: + - Marek Belisko + - H. Nikolaus Schaller + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + enum: + # Toppoly TD028TTEC1 Panel + - tpo,td028ttec1 + # Toppoly TD043MTEA1 Panel + - tpo,td043mtea1 + + reg: true + label: true + reset-gpios: true + backlight: true + port: true + +required: + - compatible + - port + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + panel: panel@0 { + compatible = "tpo,td043mtea1"; + reg = <0>; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + + label = "lcd"; + + reset-gpios = <&gpio7 7 0>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/panel/tpo,td028ttec1.txt b/Bindings/display/panel/tpo,td028ttec1.txt deleted file mode 100644 index 898e06ecf4ef..000000000000 --- a/Bindings/display/panel/tpo,td028ttec1.txt +++ /dev/null @@ -1,32 +0,0 @@ -Toppoly TD028TTEC1 Panel -======================== - -Required properties: -- compatible: "tpo,td028ttec1" - -Optional properties: -- label: a symbolic name for the panel -- backlight: phandle of the backlight device - -Required nodes: -- Video port for DPI input - -Example -------- - -lcd-panel: td028ttec1@0 { - compatible = "tpo,td028ttec1"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - label = "lcd"; - backlight = <&backlight>; - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; -}; - diff --git a/Bindings/display/panel/tpo,td043mtea1.txt b/Bindings/display/panel/tpo,td043mtea1.txt deleted file mode 100644 index ec6d62975162..000000000000 --- a/Bindings/display/panel/tpo,td043mtea1.txt +++ /dev/null @@ -1,33 +0,0 @@ -TPO TD043MTEA1 Panel -==================== - -Required properties: -- compatible: "tpo,td043mtea1" -- reset-gpios: panel reset gpio - -Optional properties: -- label: a symbolic name for the panel - -Required nodes: -- Video port for DPI input - -Example -------- - -lcd-panel: panel@0 { - compatible = "tpo,td043mtea1"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - label = "lcd"; - - reset-gpios = <&gpio7 7 0>; - - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; -}; diff --git a/Bindings/display/panel/visionox,rm69299.yaml b/Bindings/display/panel/visionox,rm69299.yaml new file mode 100644 index 000000000000..b36f39f6b233 --- /dev/null +++ b/Bindings/display/panel/visionox,rm69299.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/visionox,rm69299.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Visionox model RM69299 Panels Device Tree Bindings. + +maintainers: + - Harigovindan P + +description: | + This binding is for display panels using a Visionox RM692999 panel. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: visionox,rm69299-1080p-display + + vdda-supply: + description: | + Phandle of the regulator that provides the vdda supply voltage. + + vdd3p3-supply: + description: | + Phandle of the regulator that provides the vdd3p3 supply voltage. + + port: true + reset-gpios: true + +additionalProperties: false + +required: + - compatible + - vdda-supply + - vdd3p3-supply + - reset-gpios + - port + +examples: + - | + panel { + compatible = "visionox,rm69299-1080p-display"; + + vdda-supply = <&src_pp1800_l8c>; + vdd3p3-supply = <&src_pp2800_l18a>; + + reset-gpios = <&pm6150l_gpio 3 0>; + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +... diff --git a/Bindings/display/panel/xinpeng,xpp055c272.yaml b/Bindings/display/panel/xinpeng,xpp055c272.yaml index 6913923df569..d5c46a3cc2b0 100644 --- a/Bindings/display/panel/xinpeng,xpp055c272.yaml +++ b/Bindings/display/panel/xinpeng,xpp055c272.yaml @@ -19,9 +19,9 @@ properties: backlight: true reset-gpios: true iovcc-supply: - description: regulator that supplies the iovcc voltage + description: regulator that supplies the iovcc voltage vci-supply: - description: regulator that supplies the vci voltage + description: regulator that supplies the vci voltage required: - compatible diff --git a/Bindings/display/renesas,cmm.yaml b/Bindings/display/renesas,cmm.yaml index a57037b9e9ba..561efaaa5a91 100644 --- a/Bindings/display/renesas,cmm.yaml +++ b/Bindings/display/renesas,cmm.yaml @@ -21,15 +21,15 @@ properties: compatible: oneOf: - items: - - enum: - - renesas,r8a7795-cmm - - renesas,r8a7796-cmm - - renesas,r8a77965-cmm - - renesas,r8a77990-cmm - - renesas,r8a77995-cmm - - const: renesas,rcar-gen3-cmm + - enum: + - renesas,r8a7795-cmm + - renesas,r8a7796-cmm + - renesas,r8a77965-cmm + - renesas,r8a77990-cmm + - renesas,r8a77995-cmm + - const: renesas,rcar-gen3-cmm - items: - - const: renesas,rcar-gen2-cmm + - const: renesas,rcar-gen2-cmm reg: maxItems: 1 @@ -60,7 +60,7 @@ examples: cmm0: cmm@fea40000 { compatible = "renesas,r8a7796-cmm", "renesas,rcar-gen3-cmm"; - reg = <0 0xfea40000 0 0x1000>; + reg = <0xfea40000 0x1000>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; clocks = <&cpg CPG_MOD 711>; resets = <&cpg 711>; diff --git a/Bindings/display/renesas,du.txt b/Bindings/display/renesas,du.txt index eb4ae41fe41f..51cd4d162770 100644 --- a/Bindings/display/renesas,du.txt +++ b/Bindings/display/renesas,du.txt @@ -50,6 +50,14 @@ Required Properties: VSP instance that serves the DU channel, and the channel index identifies the LIF instance in that VSP. +Optional properties: + - resets: A list of phandle + reset-specifier pairs, one for each entry in + the reset-names property. + - reset-names: Names of the resets. This property is model-dependent. + - All but R8A7779 use one reset for a group of one or more successive + channels. The resets must be named "du.x" with "x" being the numerical + index of the lowest channel in the group. + Required nodes: The connections to the DU output video ports are modeled using the OF graph @@ -96,6 +104,8 @@ Example: R8A7795 (R-Car H3) ES2.0 DU <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>; clock-names = "du.0", "du.1", "du.2", "du.3"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.2"; renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>; diff --git a/Bindings/display/rockchip/rockchip,rk3066-hdmi.txt b/Bindings/display/rockchip/rockchip,rk3066-hdmi.txt deleted file mode 100644 index d1ad31bca8d9..000000000000 --- a/Bindings/display/rockchip/rockchip,rk3066-hdmi.txt +++ /dev/null @@ -1,72 +0,0 @@ -Rockchip specific extensions for rk3066 HDMI -============================================ - -Required properties: -- compatible: - "rockchip,rk3066-hdmi"; -- reg: - Physical base address and length of the controller's registers. -- clocks, clock-names: - Phandle to HDMI controller clock, name should be "hclk". -- interrupts: - HDMI interrupt number. -- power-domains: - Phandle to the RK3066_PD_VIO power domain. -- rockchip,grf: - This soc uses GRF regs to switch the HDMI TX input between vop0 and vop1. -- ports: - Contains one port node with two endpoints, numbered 0 and 1, - connected respectively to vop0 and vop1. - Contains one port node with one endpoint - connected to a hdmi-connector node. -- pinctrl-0, pinctrl-name: - Switch the iomux for the HPD/I2C pins to HDMI function. - -Example: - hdmi: hdmi@10116000 { - compatible = "rockchip,rk3066-hdmi"; - reg = <0x10116000 0x2000>; - interrupts = ; - clocks = <&cru HCLK_HDMI>; - clock-names = "hclk"; - power-domains = <&power RK3066_PD_VIO>; - rockchip,grf = <&grf>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vop0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop0_out_hdmi>; - }; - hdmi_in_vop1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vop1_out_hdmi>; - }; - }; - hdmi_out: port@1 { - reg = <1>; - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; - }; - }; - }; - -&pinctrl { - hdmi { - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; - }; - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, - <0 RK_PA2 1 &pcfg_pull_none>; - }; - }; -}; diff --git a/Bindings/display/rockchip/rockchip,rk3066-hdmi.yaml b/Bindings/display/rockchip/rockchip,rk3066-hdmi.yaml new file mode 100644 index 000000000000..4110d003ce1f --- /dev/null +++ b/Bindings/display/rockchip/rockchip,rk3066-hdmi.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3066-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3066 HDMI controller + +maintainers: + - Sandy Huang + - Heiko Stuebner + +properties: + compatible: + const: rockchip,rk3066-hdmi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: hclk + + pinctrl-0: + maxItems: 2 + + pinctrl-names: + const: default + description: + Switch the iomux for the HPD/I2C pins to HDMI function. + + power-domains: + maxItems: 1 + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + This soc uses GRF regs to switch the HDMI TX input between vop0 and vop1. + + ports: + type: object + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + port@0: + type: object + description: + Port node with two endpoints, numbered 0 and 1, + connected respectively to vop0 and vop1. + + port@1: + type: object + description: + Port node with one endpoint connected to a hdmi-connector node. + + required: + - "#address-cells" + - "#size-cells" + - port@0 + - port@1 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - pinctrl-0 + - pinctrl-names + - power-domains + - rockchip,grf + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + hdmi: hdmi@10116000 { + compatible = "rockchip,rk3066-hdmi"; + reg = <0x10116000 0x2000>; + interrupts = ; + clocks = <&cru HCLK_HDMI>; + clock-names = "hclk"; + pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>; + pinctrl-names = "default"; + power-domains = <&power RK3066_PD_VIO>; + rockchip,grf = <&grf>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vop0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop0_out_hdmi>; + }; + hdmi_in_vop1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vop1_out_hdmi>; + }; + }; + hdmi_out: port@1 { + reg = <1>; + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; + }; + }; + }; + + pinctrl { + hdmi { + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>; + }; + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>, + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + }; diff --git a/Bindings/display/rockchip/rockchip-drm.yaml b/Bindings/display/rockchip/rockchip-drm.yaml index ec8ae742d4da..7204da5eb4c5 100644 --- a/Bindings/display/rockchip/rockchip-drm.yaml +++ b/Bindings/display/rockchip/rockchip-drm.yaml @@ -24,7 +24,7 @@ properties: description: | Should contain a list of phandles pointing to display interface port of vop devices. vop definitions as defined in - Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt + Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml required: - compatible diff --git a/Bindings/display/rockchip/rockchip-vop.txt b/Bindings/display/rockchip/rockchip-vop.txt deleted file mode 100644 index 8b3a5f514205..000000000000 --- a/Bindings/display/rockchip/rockchip-vop.txt +++ /dev/null @@ -1,74 +0,0 @@ -device-tree bindings for rockchip soc display controller (vop) - -VOP (Visual Output Processor) is the Display Controller for the Rockchip -series of SoCs which transfers the image data from a video memory -buffer to an external LCD interface. - -Required properties: -- compatible: value should be one of the following - "rockchip,rk3036-vop"; - "rockchip,rk3126-vop"; - "rockchip,px30-vop-lit"; - "rockchip,px30-vop-big"; - "rockchip,rk3066-vop"; - "rockchip,rk3188-vop"; - "rockchip,rk3288-vop"; - "rockchip,rk3368-vop"; - "rockchip,rk3366-vop"; - "rockchip,rk3399-vop-big"; - "rockchip,rk3399-vop-lit"; - "rockchip,rk3228-vop"; - "rockchip,rk3328-vop"; - -- reg: Must contain one entry corresponding to the base address and length - of the register space. Can optionally contain a second entry - corresponding to the CRTC gamma LUT address. - -- interrupts: should contain a list of all VOP IP block interrupts in the - order: VSYNC, LCD_SYSTEM. The interrupt specifier - format depends on the interrupt controller used. - -- clocks: must include clock specifiers corresponding to entries in the - clock-names property. - -- clock-names: Must contain - aclk_vop: for ddr buffer transfer. - hclk_vop: for ahb bus to R/W the phy regs. - dclk_vop: pixel clock. - -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - axi - - ahb - - dclk - -- iommus: required a iommu node - -- port: A port node with endpoint definitions as defined in - Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: -SoC specific DT entry: - vopb: vopb@ff930000 { - compatible = "rockchip,rk3288-vop"; - reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; - interrupts = ; - clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vopb_mmu>; - vopb_out: port { - #address-cells = <1>; - #size-cells = <0>; - vopb_out_edp: endpoint@0 { - reg = <0>; - remote-endpoint=<&edp_in_vopb>; - }; - vopb_out_hdmi: endpoint@1 { - reg = <1>; - remote-endpoint=<&hdmi_in_vopb>; - }; - }; - }; diff --git a/Bindings/display/rockchip/rockchip-vop.yaml b/Bindings/display/rockchip/rockchip-vop.yaml new file mode 100644 index 000000000000..ed8148e26e24 --- /dev/null +++ b/Bindings/display/rockchip/rockchip-vop.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoC display controller (VOP) + +description: + VOP (Video Output Processor) is the display controller for the Rockchip + series of SoCs which transfers the image data from a video memory + buffer to an external LCD interface. + +maintainers: + - Sandy Huang + - Heiko Stuebner + +properties: + compatible: + enum: + - rockchip,px30-vop-big + - rockchip,px30-vop-lit + - rockchip,rk3036-vop + - rockchip,rk3066-vop + - rockchip,rk3126-vop + - rockchip,rk3188-vop + - rockchip,rk3228-vop + - rockchip,rk3288-vop + - rockchip,rk3328-vop + - rockchip,rk3366-vop + - rockchip,rk3368-vop + - rockchip,rk3399-vop-big + - rockchip,rk3399-vop-lit + + reg: + minItems: 1 + items: + - description: + Must contain one entry corresponding to the base address and length + of the register space. + - description: + Can optionally contain a second entry corresponding to + the CRTC gamma LUT address. + + interrupts: + maxItems: 1 + description: + The VOP interrupt is shared by several interrupt sources, such as + frame start (VSYNC), line flag and other status interrupts. + + clocks: + items: + - description: Clock for ddr buffer transfer. + - description: Pixel clock. + - description: Clock for the ahb bus to R/W the phy regs. + + clock-names: + items: + - const: aclk_vop + - const: dclk_vop + - const: hclk_vop + + resets: + maxItems: 3 + + reset-names: + items: + - const: axi + - const: ahb + - const: dclk + + port: + type: object + description: + A port node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + + assigned-clocks: + maxItems: 2 + + assigned-clock-rates: + maxItems: 2 + + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - port + +additionalProperties: false + +examples: + - | + #include + #include + #include + vopb: vopb@ff930000 { + compatible = "rockchip,rk3288-vop"; + reg = <0xff930000 0x19c>, + <0xff931000 0x1000>; + interrupts = ; + clocks = <&cru ACLK_VOP0>, + <&cru DCLK_VOP0>, + <&cru HCLK_VOP0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3288_PD_VIO>; + resets = <&cru SRST_LCDC1_AXI>, + <&cru SRST_LCDC1_AHB>, + <&cru SRST_LCDC1_DCLK>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vopb_mmu>; + vopb_out: port { + #address-cells = <1>; + #size-cells = <0>; + vopb_out_edp: endpoint@0 { + reg = <0>; + remote-endpoint=<&edp_in_vopb>; + }; + vopb_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint=<&hdmi_in_vopb>; + }; + }; + }; diff --git a/Bindings/display/tegra/nvidia,tegra20-host1x.txt b/Bindings/display/tegra/nvidia,tegra20-host1x.txt index 9999255ac5b6..47319214b5f6 100644 --- a/Bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -40,14 +40,30 @@ of the following host1x client modules: Required properties: - compatible: "nvidia,tegra-vi" - - reg: Physical base address and length of the controller's registers. + - reg: Physical base address and length of the controller registers. - interrupts: The interrupt outputs from the controller. - - clocks: Must contain one entry, for the module clock. + - clocks: clocks: Must contain one entry, for the module clock. See ../clocks/clock-bindings.txt for details. - - resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names: Must include the following entries: - - vi + - Tegra20/Tegra30/Tegra114/Tegra124: + - resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must include the following entries: + - vi + - Tegra210: + - power-domains: Must include venc powergate node as vi is in VE partition. + - Tegra210 has CSI part of VI sharing same host interface and register space. + So, VI device node should have CSI child node. + + - csi: mipi csi interface to vi + + Required properties: + - compatible: "nvidia,tegra210-csi" + - reg: Physical base address offset to parent and length of the controller + registers. + - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks. + See ../clocks/clock-bindings.txt for details. + - power-domains: Must include sor powergate node as csicil is in + SOR partition. - epp: encoder pre-processor @@ -309,13 +325,44 @@ Example: reset-names = "mpe"; }; - vi { - compatible = "nvidia,tegra20-vi"; - reg = <0x54080000 0x00040000>; - interrupts = <0 69 0x04>; - clocks = <&tegra_car TEGRA20_CLK_VI>; - resets = <&tegra_car 100>; - reset-names = "vi"; + vi@54080000 { + compatible = "nvidia,tegra210-vi"; + reg = <0x0 0x54080000 0x0 0x700>; + interrupts = ; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>, + <972000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; + power-domains = <&pd_sor>; + }; }; epp { diff --git a/Bindings/display/ti/ti,am65x-dss.yaml b/Bindings/display/ti/ti,am65x-dss.yaml index eb04c2330698..4f9185462ed3 100644 --- a/Bindings/display/ti/ti,am65x-dss.yaml +++ b/Bindings/display/ti/ti,am65x-dss.yaml @@ -88,9 +88,8 @@ properties: - "#size-cells" ti,am65x-oldi-io-ctrl: - allOf: - - $ref: "/schemas/types.yaml#/definitions/phandle-array" - - maxItems: 1 + $ref: "/schemas/types.yaml#/definitions/phandle-array" + maxItems: 1 description: phandle to syscon device node mapping OLDI IO_CTRL registers. The mapped range should point to OLDI_DAT0_IO_CTRL, map it and @@ -123,13 +122,13 @@ examples: dss: dss@4a00000 { compatible = "ti,am65x-dss"; - reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ - <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ - <0x0 0x04a06000 0x0 0x1000>, /* vid */ - <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ - <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ - <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + reg = <0x04a00000 0x1000>, /* common */ + <0x04a02000 0x1000>, /* vidl1 */ + <0x04a06000 0x1000>, /* vid */ + <0x04a07000 0x1000>, /* ovr1 */ + <0x04a08000 0x1000>, /* ovr2 */ + <0x04a0a000 0x1000>, /* vp1 */ + <0x04a0b000 0x1000>; /* vp2 */ reg-names = "common", "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; diff --git a/Bindings/display/ti/ti,j721e-dss.yaml b/Bindings/display/ti/ti,j721e-dss.yaml index eb4b1a266210..bbd76591c180 100644 --- a/Bindings/display/ti/ti,j721e-dss.yaml +++ b/Bindings/display/ti/ti,j721e-dss.yaml @@ -156,23 +156,23 @@ examples: dss: dss@4a00000 { compatible = "ti,j721e-dss"; - reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ - <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ - <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ - <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ - <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ - <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ - <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ - <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ - <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ - <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ - <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ - <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ - <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ - <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ - <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ - <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ - <0x00 0x04af0000 0x00 0x10000>; /* wb */ + reg = <0x04a00000 0x10000>, /* common_m */ + <0x04a10000 0x10000>, /* common_s0*/ + <0x04b00000 0x10000>, /* common_s1*/ + <0x04b10000 0x10000>, /* common_s2*/ + <0x04a20000 0x10000>, /* vidl1 */ + <0x04a30000 0x10000>, /* vidl2 */ + <0x04a50000 0x10000>, /* vid1 */ + <0x04a60000 0x10000>, /* vid2 */ + <0x04a70000 0x10000>, /* ovr1 */ + <0x04a90000 0x10000>, /* ovr2 */ + <0x04ab0000 0x10000>, /* ovr3 */ + <0x04ad0000 0x10000>, /* ovr4 */ + <0x04a80000 0x10000>, /* vp1 */ + <0x04aa0000 0x10000>, /* vp2 */ + <0x04ac0000 0x10000>, /* vp3 */ + <0x04ae0000 0x10000>, /* vp4 */ + <0x04af0000 0x10000>; /* wb */ reg-names = "common_m", "common_s0", "common_s1", "common_s2", "vidl1", "vidl2","vid1","vid2", diff --git a/Bindings/dma/dma-common.yaml b/Bindings/dma/dma-common.yaml index 02a34ba2b49b..c36592683340 100644 --- a/Bindings/dma/dma-common.yaml +++ b/Bindings/dma/dma-common.yaml @@ -31,8 +31,7 @@ properties: kernel. i.e. first channel corresponds to LSB. The first item in the array is for channels 0-31, the second is for channels 32-63, etc. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array items: minItems: 1 # Should be enough diff --git a/Bindings/dma/ingenic,dma.yaml b/Bindings/dma/ingenic,dma.yaml new file mode 100644 index 000000000000..92794c500589 --- /dev/null +++ b/Bindings/dma/ingenic,dma.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/ingenic,dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs DMA Controller DT bindings + +maintainers: + - Paul Cercueil + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + enum: + - ingenic,jz4740-dma + - ingenic,jz4725b-dma + - ingenic,jz4770-dma + - ingenic,jz4780-dma + - ingenic,x1000-dma + - ingenic,x1830-dma + + reg: + items: + - description: Channel-specific registers + - description: System control registers + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + "#dma-cells": + const: 2 + description: > + DMA clients must use the format described in dma.txt, giving a phandle + to the DMA controller plus the following 2 integer cells: + + - Request type: The DMA request type for transfers to/from the + device on the allocated channel, as defined in the SoC documentation. + + - Channel: If set to 0xffffffff, any available channel will be allocated + for the client. Otherwise, the exact channel specified will be used. + The channel should be reserved on the DMA controller using the + ingenic,reserved-channels property. + + ingenic,reserved-channels: + $ref: /schemas/types.yaml#definitions/uint32 + description: > + Bitmask of channels to reserve for devices that need a specific + channel. These channels will only be assigned when explicitely + requested by a client. The primary use for this is channels 0 and + 1, which can be configured to have special behaviour for NAND/BCH + when using programmable firmware. + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + #include + dma: dma-controller@13420000 { + compatible = "ingenic,jz4780-dma"; + reg = <0x13420000 0x400>, <0x13421000 0x40>; + + interrupt-parent = <&intc>; + interrupts = <10>; + + clocks = <&cgu JZ4780_CLK_PDMA>; + + #dma-cells = <2>; + + ingenic,reserved-channels = <0x3>; + }; diff --git a/Bindings/dma/jz4780-dma.txt b/Bindings/dma/jz4780-dma.txt deleted file mode 100644 index 3459e77be294..000000000000 --- a/Bindings/dma/jz4780-dma.txt +++ /dev/null @@ -1,64 +0,0 @@ -* Ingenic XBurst DMA Controller - -Required properties: - -- compatible: Should be one of: - * ingenic,jz4740-dma - * ingenic,jz4725b-dma - * ingenic,jz4770-dma - * ingenic,jz4780-dma - * ingenic,x1000-dma - * ingenic,x1830-dma -- reg: Should contain the DMA channel registers location and length, followed - by the DMA controller registers location and length. -- interrupts: Should contain the interrupt specifier of the DMA controller. -- clocks: Should contain a clock specifier for the JZ4780/X1000/X1830 PDMA - clock. -- #dma-cells: Must be <2>. Number of integer cells in the dmas property of - DMA clients (see below). - -Optional properties: - -- ingenic,reserved-channels: Bitmask of channels to reserve for devices that - need a specific channel. These channels will only be assigned when explicitly - requested by a client. The primary use for this is channels 0 and 1, which - can be configured to have special behaviour for NAND/BCH when using - programmable firmware. - -Example: - -dma: dma-controller@13420000 { - compatible = "ingenic,jz4780-dma"; - reg = <0x13420000 0x400 - 0x13421000 0x40>; - - interrupt-parent = <&intc>; - interrupts = <10>; - - clocks = <&cgu JZ4780_CLK_PDMA>; - - #dma-cells = <2>; - - ingenic,reserved-channels = <0x3>; -}; - -DMA clients must use the format described in dma.txt, giving a phandle to the -DMA controller plus the following 2 integer cells: - -1. Request type: The DMA request type for transfers to/from the device on - the allocated channel, as defined in the SoC documentation. - -2. Channel: If set to 0xffffffff, any available channel will be allocated for - the client. Otherwise, the exact channel specified will be used. The channel - should be reserved on the DMA controller using the ingenic,reserved-channels - property. - -Example: - -uart0: serial@10030000 { - ... - dmas = <&dma 0x14 0xffffffff - &dma 0x15 0xffffffff>; - dma-names = "tx", "rx"; - ... -}; diff --git a/Bindings/dma/mtk-uart-apdma.txt b/Bindings/dma/mtk-uart-apdma.txt index 5d6f98c43e3d..2117db0ce4f2 100644 --- a/Bindings/dma/mtk-uart-apdma.txt +++ b/Bindings/dma/mtk-uart-apdma.txt @@ -21,7 +21,8 @@ Required properties: Examples: apdma: dma-controller@11000400 { - compatible = "mediatek,mt2712-uart-dma"; + compatible = "mediatek,mt2712-uart-dma", + "mediatek,mt6577-uart-dma"; reg = <0 0x11000400 0 0x80>, <0 0x11000480 0 0x80>, <0 0x11000500 0 0x80>, diff --git a/Bindings/dma/renesas,rcar-dmac.txt b/Bindings/dma/renesas,rcar-dmac.txt deleted file mode 100644 index b7f81c63be8b..000000000000 --- a/Bindings/dma/renesas,rcar-dmac.txt +++ /dev/null @@ -1,117 +0,0 @@ -* Renesas R-Car (RZ/G) DMA Controller Device Tree bindings - -Renesas R-Car (Gen 2/3) and RZ/G SoCs have multiple multi-channel DMA -controller instances named DMAC capable of serving multiple clients. Channels -can be dedicated to specific clients or shared between a large number of -clients. - -Each DMA client is connected to one dedicated port of the DMAC, identified by -an 8-bit port number called the MID/RID. A DMA controller can thus serve up to -256 clients in total. When the number of hardware channels is lower than the -number of clients to be served, channels must be shared between multiple DMA -clients. The association of DMA clients to DMAC channels is fully dynamic and -not described in these device tree bindings. - -Required Properties: - -- compatible: "renesas,dmac-", "renesas,rcar-dmac" as fallback. - Examples with soctypes are: - - "renesas,dmac-r8a7743" (RZ/G1M) - - "renesas,dmac-r8a7744" (RZ/G1N) - - "renesas,dmac-r8a7745" (RZ/G1E) - - "renesas,dmac-r8a77470" (RZ/G1C) - - "renesas,dmac-r8a774a1" (RZ/G2M) - - "renesas,dmac-r8a774b1" (RZ/G2N) - - "renesas,dmac-r8a774c0" (RZ/G2E) - - "renesas,dmac-r8a7790" (R-Car H2) - - "renesas,dmac-r8a7791" (R-Car M2-W) - - "renesas,dmac-r8a7792" (R-Car V2H) - - "renesas,dmac-r8a7793" (R-Car M2-N) - - "renesas,dmac-r8a7794" (R-Car E2) - - "renesas,dmac-r8a7795" (R-Car H3) - - "renesas,dmac-r8a7796" (R-Car M3-W) - - "renesas,dmac-r8a77961" (R-Car M3-W+) - - "renesas,dmac-r8a77965" (R-Car M3-N) - - "renesas,dmac-r8a77970" (R-Car V3M) - - "renesas,dmac-r8a77980" (R-Car V3H) - - "renesas,dmac-r8a77990" (R-Car E3) - - "renesas,dmac-r8a77995" (R-Car D3) - -- reg: base address and length of the registers block for the DMAC - -- interrupts: interrupt specifiers for the DMAC, one for each entry in - interrupt-names. -- interrupt-names: one entry for the error interrupt, named "error", plus one - entry per channel, named "ch%u", where %u is the channel number ranging from - zero to the number of channels minus one. - -- clock-names: "fck" for the functional clock -- clocks: a list of phandle + clock-specifier pairs, one for each entry - in clock-names. -- clock-names: must contain "fck" for the functional clock. - -- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port - connected to the DMA client -- dma-channels: number of DMA channels - -Example: R8A7790 (R-Car H2) SYS-DMACs - - dmac0: dma-controller@e6700000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xe6700000 0 0x20000>; - interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH - 0 200 IRQ_TYPE_LEVEL_HIGH - 0 201 IRQ_TYPE_LEVEL_HIGH - 0 202 IRQ_TYPE_LEVEL_HIGH - 0 203 IRQ_TYPE_LEVEL_HIGH - 0 204 IRQ_TYPE_LEVEL_HIGH - 0 205 IRQ_TYPE_LEVEL_HIGH - 0 206 IRQ_TYPE_LEVEL_HIGH - 0 207 IRQ_TYPE_LEVEL_HIGH - 0 208 IRQ_TYPE_LEVEL_HIGH - 0 209 IRQ_TYPE_LEVEL_HIGH - 0 210 IRQ_TYPE_LEVEL_HIGH - 0 211 IRQ_TYPE_LEVEL_HIGH - 0 212 IRQ_TYPE_LEVEL_HIGH - 0 213 IRQ_TYPE_LEVEL_HIGH - 0 214 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; - clock-names = "fck"; - #dma-cells = <1>; - dma-channels = <15>; - }; - - dmac1: dma-controller@e6720000 { - compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; - reg = <0 0xe6720000 0 0x20000>; - interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH - 0 216 IRQ_TYPE_LEVEL_HIGH - 0 217 IRQ_TYPE_LEVEL_HIGH - 0 218 IRQ_TYPE_LEVEL_HIGH - 0 219 IRQ_TYPE_LEVEL_HIGH - 0 308 IRQ_TYPE_LEVEL_HIGH - 0 309 IRQ_TYPE_LEVEL_HIGH - 0 310 IRQ_TYPE_LEVEL_HIGH - 0 311 IRQ_TYPE_LEVEL_HIGH - 0 312 IRQ_TYPE_LEVEL_HIGH - 0 313 IRQ_TYPE_LEVEL_HIGH - 0 314 IRQ_TYPE_LEVEL_HIGH - 0 315 IRQ_TYPE_LEVEL_HIGH - 0 316 IRQ_TYPE_LEVEL_HIGH - 0 317 IRQ_TYPE_LEVEL_HIGH - 0 318 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; - clock-names = "fck"; - #dma-cells = <1>; - dma-channels = <15>; - }; diff --git a/Bindings/dma/renesas,rcar-dmac.yaml b/Bindings/dma/renesas,rcar-dmac.yaml new file mode 100644 index 000000000000..b842dfd96a89 --- /dev/null +++ b/Bindings/dma/renesas,rcar-dmac.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car and RZ/G DMA Controller + +maintainers: + - Yoshihiro Shimoda + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + items: + - enum: + - renesas,dmac-r8a7743 # RZ/G1M + - renesas,dmac-r8a7744 # RZ/G1N + - renesas,dmac-r8a7745 # RZ/G1E + - renesas,dmac-r8a77470 # RZ/G1C + - renesas,dmac-r8a774a1 # RZ/G2M + - renesas,dmac-r8a774b1 # RZ/G2N + - renesas,dmac-r8a774c0 # RZ/G2E + - renesas,dmac-r8a7790 # R-Car H2 + - renesas,dmac-r8a7791 # R-Car M2-W + - renesas,dmac-r8a7792 # R-Car V2H + - renesas,dmac-r8a7793 # R-Car M2-N + - renesas,dmac-r8a7794 # R-Car E2 + - renesas,dmac-r8a7795 # R-Car H3 + - renesas,dmac-r8a7796 # R-Car M3-W + - renesas,dmac-r8a77961 # R-Car M3-W+ + - renesas,dmac-r8a77965 # R-Car M3-N + - renesas,dmac-r8a77970 # R-Car V3M + - renesas,dmac-r8a77980 # R-Car V3H + - renesas,dmac-r8a77990 # R-Car E3 + - renesas,dmac-r8a77995 # R-Car D3 + - const: renesas,rcar-dmac + + reg: + maxItems: 1 + + interrupts: + minItems: 9 + maxItems: 17 + + interrupt-names: + minItems: 9 + maxItems: 17 + items: + - const: error + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + - pattern: "^ch([0-9]|1[0-5])$" + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + items: + - const: fck + + '#dma-cells': + const: 1 + description: + The cell specifies the MID/RID of the DMAC port connected to + the DMA client. + + dma-channels: + minimum: 8 + maximum: 16 + + dma-channel-mask: true + + iommus: + minItems: 8 + maxItems: 16 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - '#dma-cells' + - dma-channels + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; + reg = <0xe6700000 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; diff --git a/Bindings/dma/renesas,usb-dmac.txt b/Bindings/dma/renesas,usb-dmac.txt deleted file mode 100644 index e8f6c42e80f2..000000000000 --- a/Bindings/dma/renesas,usb-dmac.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Renesas USB DMA Controller Device Tree bindings - -Required Properties: --compatible: "renesas,-usb-dmac", "renesas,usb-dmac" as fallback. - Examples with soctypes are: - - "renesas,r8a7743-usb-dmac" (RZ/G1M) - - "renesas,r8a7744-usb-dmac" (RZ/G1N) - - "renesas,r8a7745-usb-dmac" (RZ/G1E) - - "renesas,r8a77470-usb-dmac" (RZ/G1C) - - "renesas,r8a774a1-usb-dmac" (RZ/G2M) - - "renesas,r8a774b1-usb-dmac" (RZ/G2N) - - "renesas,r8a774c0-usb-dmac" (RZ/G2E) - - "renesas,r8a7790-usb-dmac" (R-Car H2) - - "renesas,r8a7791-usb-dmac" (R-Car M2-W) - - "renesas,r8a7793-usb-dmac" (R-Car M2-N) - - "renesas,r8a7794-usb-dmac" (R-Car E2) - - "renesas,r8a7795-usb-dmac" (R-Car H3) - - "renesas,r8a7796-usb-dmac" (R-Car M3-W) - - "renesas,r8a77961-usb-dmac" (R-Car M3-W+) - - "renesas,r8a77965-usb-dmac" (R-Car M3-N) - - "renesas,r8a77990-usb-dmac" (R-Car E3) - - "renesas,r8a77995-usb-dmac" (R-Car D3) -- reg: base address and length of the registers block for the DMAC -- interrupts: interrupt specifiers for the DMAC, one for each entry in - interrupt-names. -- interrupt-names: one entry per channel, named "ch%u", where %u is the - channel number ranging from zero to the number of channels minus one. -- clocks: a list of phandle + clock-specifier pairs. -- #dma-cells: must be <1>, the cell specifies the channel number of the DMAC - port connected to the DMA client. -- dma-channels: number of DMA channels - -Example: R8A7790 (R-Car H2) USB-DMACs - - usb_dmac0: dma-controller@e65a0000 { - compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac"; - reg = <0 0xe65a0000 0 0x100>; - interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH - 0 109 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; - #dma-cells = <1>; - dma-channels = <2>; - }; - - usb_dmac1: dma-controller@e65b0000 { - compatible = "renesas,usb-dmac"; - reg = <0 0xe65b0000 0 0x100>; - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH - 0 110 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; - #dma-cells = <1>; - dma-channels = <2>; - }; diff --git a/Bindings/dma/renesas,usb-dmac.yaml b/Bindings/dma/renesas,usb-dmac.yaml new file mode 100644 index 000000000000..9ca6d8ddf232 --- /dev/null +++ b/Bindings/dma/renesas,usb-dmac.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/renesas,usb-dmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas USB DMA Controller + +maintainers: + - Yoshihiro Shimoda + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + items: + - enum: + - renesas,r8a7743-usb-dmac # RZ/G1M + - renesas,r8a7744-usb-dmac # RZ/G1N + - renesas,r8a7745-usb-dmac # RZ/G1E + - renesas,r8a77470-usb-dmac # RZ/G1C + - renesas,r8a774a1-usb-dmac # RZ/G2M + - renesas,r8a774b1-usb-dmac # RZ/G2N + - renesas,r8a774c0-usb-dmac # RZ/G2E + - renesas,r8a7790-usb-dmac # R-Car H2 + - renesas,r8a7791-usb-dmac # R-Car M2-W + - renesas,r8a7793-usb-dmac # R-Car M2-N + - renesas,r8a7794-usb-dmac # R-Car E2 + - renesas,r8a7795-usb-dmac # R-Car H3 + - renesas,r8a7796-usb-dmac # R-Car M3-W + - renesas,r8a77961-usb-dmac # R-Car M3-W+ + - renesas,r8a77965-usb-dmac # R-Car M3-N + - renesas,r8a77990-usb-dmac # R-Car E3 + - renesas,r8a77995-usb-dmac # R-Car D3 + - const: renesas,usb-dmac + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 2 + + interrupt-names: + items: + - pattern: ch0 + - pattern: ch1 + + clocks: + maxItems: 1 + + '#dma-cells': + const: 1 + description: + The cell specifies the channel number of the DMAC port connected to + the DMA client. + + dma-channels: + const: 2 + + iommus: + minItems: 2 + maxItems: 2 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - '#dma-cells' + - dma-channels + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac"; + reg = <0xe65a0000 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; diff --git a/Bindings/dma/sifive,fu540-c000-pdma.yaml b/Bindings/dma/sifive,fu540-c000-pdma.yaml index e7f2ad7dab5e..d32a71b975fe 100644 --- a/Bindings/dma/sifive,fu540-c000-pdma.yaml +++ b/Bindings/dma/sifive,fu540-c000-pdma.yaml @@ -49,7 +49,7 @@ examples: - | dma@3000000 { compatible = "sifive,fu540-c000-pdma"; - reg = <0x0 0x3000000 0x0 0x8000>; + reg = <0x3000000 0x8000>; interrupts = <23 24 25 26 27 28 29 30>; #dma-cells = <1>; }; diff --git a/Bindings/dma/st,stm32-dma.yaml b/Bindings/dma/st,stm32-dma.yaml index 0c0ac11ad55f..71987878e4ae 100644 --- a/Bindings/dma/st,stm32-dma.yaml +++ b/Bindings/dma/st,stm32-dma.yaml @@ -36,6 +36,11 @@ description: | 0x1: 1/2 full FIFO 0x2: 3/4 full FIFO 0x3: full FIFO + -bit 2: DMA direct mode + 0x0: FIFO mode with threshold selectable with bit 0-1 + 0x1: Direct mode: each DMA request immediately initiates a transfer + from/to the memory, FIFO is bypassed. + maintainers: - Amelie Delaunay diff --git a/Bindings/dma/ti/k3-udma.yaml b/Bindings/dma/ti/k3-udma.yaml index 39ea05e6e5ff..dd70ddab4fd1 100644 --- a/Bindings/dma/ti/k3-udma.yaml +++ b/Bindings/dma/ti/k3-udma.yaml @@ -69,34 +69,30 @@ properties: maxItems: 3 reg-names: - items: - - const: gcfg - - const: rchanrt - - const: tchanrt + items: + - const: gcfg + - const: rchanrt + - const: tchanrt msi-parent: true ti,sci: description: phandle to TI-SCI compatible System controller node - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle ti,sci-dev-id: description: TI-SCI device id of UDMAP - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 ti,ringacc: description: phandle to the ring accelerator node - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle ti,sci-rm-range-tchan: description: | Array of UDMA tchan resource subtypes for resource allocation for this host - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 # Should be enough maxItems: 255 @@ -105,8 +101,7 @@ properties: description: | Array of UDMA rchan resource subtypes for resource allocation for this host - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 # Should be enough maxItems: 255 @@ -115,8 +110,7 @@ properties: description: | Array of UDMA rflow resource subtypes for resource allocation for this host - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 # Should be enough maxItems: 255 @@ -142,8 +136,7 @@ then: properties: ti,udma-atype: description: ATYPE value which should be used by non slave channels - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 required: - ti,udma-atype diff --git a/Bindings/dsp/fsl,dsp.yaml b/Bindings/dsp/fsl,dsp.yaml index a5dc070d0ca7..3bbe9521c0bc 100644 --- a/Bindings/dsp/fsl,dsp.yaml +++ b/Bindings/dsp/fsl,dsp.yaml @@ -17,6 +17,8 @@ properties: compatible: enum: - fsl,imx8qxp-dsp + - fsl,imx8qm-dsp + - fsl,imx8mp-dsp reg: description: Should contain register location and length diff --git a/Bindings/eeprom/at24.yaml b/Bindings/eeprom/at24.yaml index a15787e504f0..4cee72d53318 100644 --- a/Bindings/eeprom/at24.yaml +++ b/Bindings/eeprom/at24.yaml @@ -34,7 +34,7 @@ properties: - minItems: 1 maxItems: 2 items: - - pattern: "^(atmel|catalyst|microchip|nxp|ramtron|renesas|rohm|st),(24(c|cs|mac)[0-9]+|spd)$" + - pattern: "^(atmel|catalyst|microchip|nxp|ramtron|renesas|rohm|st),(24(c|cs|lc|mac)[0-9]+|spd)$" - pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$" - oneOf: - items: @@ -118,14 +118,13 @@ properties: maxItems: 1 pagesize: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 description: The length of the pagesize for writing. Please consult the manual of your device, that value varies a lot. A wrong value may result in data loss! If not specified, a safety value of '1' is used which will be very slow. - enum: [ 1, 8, 16, 32, 64, 128, 258 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 8, 16, 32, 64, 128, 256] default: 1 read-only: @@ -148,18 +147,16 @@ properties: wp-gpios: true address-width: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 description: Number of address bits. + $ref: /schemas/types.yaml#/definitions/uint32 default: 8 enum: [ 8, 16 ] num-addresses: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 description: Total number of i2c slave addresses this device takes. + $ref: /schemas/types.yaml#/definitions/uint32 default: 1 minimum: 1 maximum: 8 diff --git a/Bindings/example-schema.yaml b/Bindings/example-schema.yaml index 62811a1b5058..c9534d2164a2 100644 --- a/Bindings/example-schema.yaml +++ b/Bindings/example-schema.yaml @@ -138,12 +138,8 @@ properties: # 'description'. vendor,int-property: description: Vendor specific properties must have a description - # 'allOf' is the json-schema way of subclassing a schema. Here the base - # type schema is referenced and then additional constraints on the values - # are added. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [2, 4, 6, 8, 10] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 4, 6, 8, 10] vendor,bool-property: description: Vendor specific properties must have a description. Boolean @@ -154,11 +150,10 @@ properties: vendor,string-array-property: description: Vendor specific properties should reference a type in the core schema. - allOf: - - $ref: /schemas/types.yaml#/definitions/string-array - - items: - - enum: [ foo, bar ] - - enum: [ baz, boo ] + $ref: /schemas/types.yaml#/definitions/string-array + items: + - enum: [foo, bar] + - enum: [baz, boo] vendor,property-in-standard-units-microvolt: description: Vendor specific properties having a standard unit suffix diff --git a/Bindings/extcon/extcon-arizona.txt b/Bindings/extcon/extcon-arizona.txt deleted file mode 100644 index 208daaff0be4..000000000000 --- a/Bindings/extcon/extcon-arizona.txt +++ /dev/null @@ -1,76 +0,0 @@ -Cirrus Logic Arizona class audio SoCs - -These devices are audio SoCs with extensive digital capabilities and a range -of analogue I/O. - -This document lists Extcon specific bindings, see the primary binding document: - ../mfd/arizona.txt - -Optional properties: - - - wlf,hpdet-channel : Headphone detection channel. - ARIZONA_ACCDET_MODE_HPL or 1 - Headphone detect mode is set to HPDETL - ARIZONA_ACCDET_MODE_HPR or 2 - Headphone detect mode is set to HPDETR - If this node is not mentioned or if the value is unknown, then - headphone detection mode is set to HPDETL. - - - wlf,use-jd2 : Use the additional JD input along with JD1 for dual pin jack - detection. - - wlf,use-jd2-nopull : Internal pull on JD2 is disabled when used for - jack detection. - - wlf,jd-invert : Invert the polarity of the jack detection switch - - - wlf,micd-software-compare : Use a software comparison to determine mic - presence - - wlf,micd-detect-debounce : Additional software microphone detection - debounce specified in milliseconds. - - wlf,micd-pol-gpio : GPIO specifier for the GPIO controlling the headset - polarity if one exists. - - wlf,micd-bias-start-time : Time allowed for MICBIAS to startup prior to - performing microphone detection, specified as per the ARIZONA_MICD_TIME_XXX - defines. - - wlf,micd-rate : Delay between successive microphone detection measurements, - specified as per the ARIZONA_MICD_TIME_XXX defines. - - wlf,micd-dbtime : Microphone detection hardware debounces specified as the - number of measurements to take, valid values being 2 and 4. - - wlf,micd-timeout-ms : Timeout for microphone detection, specified in - milliseconds. - - wlf,micd-force-micbias : Force MICBIAS continuously on during microphone - detection. - - wlf,micd-configs : Headset polarity configurations (generally used for - detection of CTIA / OMTP headsets), the field can be of variable length - but should always be a multiple of 3 cells long, each three cell group - represents one polarity configuration. - The first cell defines the accessory detection pin, zero will use MICDET1 - and all other values will use MICDET2. - The second cell represents the MICBIAS to be used. - The third cell represents the value of the micd-pol-gpio pin. - - - wlf,gpsw : Settings for the general purpose switch, set as one of the - ARIZONA_GPSW_XXX defines. - -Example: - -codec: wm8280@0 { - compatible = "wlf,wm8280"; - reg = <0>; - ... - - wlf,use-jd2; - wlf,use-jd2-nopull; - wlf,jd-invert; - - wlf,micd-software-compare; - wlf,micd-detect-debounce = <0>; - wlf,micd-pol-gpio = <&codec 2 0>; - wlf,micd-rate = ; - wlf,micd-dbtime = <4>; - wlf,micd-timeout-ms = <100>; - wlf,micd-force-micbias; - wlf,micd-configs = < - 0 1 0 /* MICDET1 MICBIAS1 GPIO=low */ - 1 2 1 /* MICDET2 MICBIAS2 GPIO=high */ - >; - - wlf,gpsw = ; -}; diff --git a/Bindings/extcon/extcon-usbc-cros-ec.yaml b/Bindings/extcon/extcon-usbc-cros-ec.yaml index 9c5849b341ea..20e1ccfc8630 100644 --- a/Bindings/extcon/extcon-usbc-cros-ec.yaml +++ b/Bindings/extcon/extcon-usbc-cros-ec.yaml @@ -22,8 +22,7 @@ properties: const: google,extcon-usbc-cros-ec google,usb-port-id: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 description: the port id minimum: 0 maximum: 255 diff --git a/Bindings/extcon/wlf,arizona.yaml b/Bindings/extcon/wlf,arizona.yaml new file mode 100644 index 000000000000..f9845dc2f5ae --- /dev/null +++ b/Bindings/extcon/wlf,arizona.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/extcon/wlf,arizona.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic/Wolfson Microelectronics Arizona class audio SoCs + +maintainers: + - patches@opensource.cirrus.com + +description: | + These devices are audio SoCs with extensive digital capabilities and a + range of analogue I/O. + + This document lists Extcon specific bindings, see the primary binding + document ../mfd/arizona.yaml + +properties: + wlf,hpdet-channel: + description: + Headphone detection channel. ARIZONA_ACCDET_MODE_HPL/1 sets the + headphone detect mode to HPDETL, ARIZONA_ACCDET_MODE_HPR/2 sets it + to HPDETR. If this node is not included or if the value is unknown, + then headphone detection mode is set to HPDETL. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 1 + maximum: 2 + + wlf,use-jd2: + description: + Use the additional JD input along with JD1 for dual pin jack detection. + type: boolean + + wlf,use-jd2-nopull: + description: + Internal pull on JD2 is disabled when used for jack detection. + type: boolean + + wlf,jd-invert: + description: + Invert the polarity of the jack detection switch. + type: boolean + + wlf,micd-software-compare: + description: + Use a software comparison to determine mic presence. + type: boolean + + wlf,micd-detect-debounce: + description: + Additional software microphone detection debounce specified in + milliseconds. + $ref: "/schemas/types.yaml#/definitions/uint32" + + wlf,micd-pol-gpio: + description: + GPIO specifier for the GPIO controlling the headset polarity if one + exists. + maxItems: 1 + + wlf,micd-bias-start-time: + description: + Time allowed for MICBIAS to startup prior to performing microphone + detection, specified as per the ARIZONA_MICD_TIME_XXX defines. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 12 + + wlf,micd-rate: + description: + Delay between successive microphone detection measurements, specified + as per the ARIZONA_MICD_TIME_XXX defines. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 12 + + wlf,micd-dbtime: + description: + Microphone detection hardware debounces specified as the number of + measurements to take. + $ref: "/schemas/types.yaml#/definitions/uint32" + enum: [2, 4] + + wlf,micd-timeout-ms: + description: + Timeout for microphone detection, specified in milliseconds. + $ref: "/schemas/types.yaml#/definitions/uint32" + + wlf,micd-force-micbias: + description: + Force MICBIAS continuously on during microphone detection. + type: boolean + + wlf,micd-configs: + description: + Headset polarity configurations (generally used for detection of + CTIA / OMTP headsets), the field can be of variable length but + should always be a multiple of 3 cells long, each three cell group + represents one polarity configuration. + $ref: "/schemas/types.yaml#/definitions/uint32-matrix" + items: + items: + - description: + The first cell defines the accessory detection pin, zero + will use MICDET1 and 0x2000 will use MICDET2. + enum: [ 0, 0x2000 ] + - description: + The second cell represents the MICBIAS to be used. Zero + will use MICVDD, 1-3 will use MICBIASx. + minimum: 0 + maximum: 3 + - description: + The third cell represents the value of the micd-pol-gpio + pin. + minimum: 0 + maximum: 1 + + wlf,gpsw: + description: + Settings for the general purpose switch, set as one of the + ARIZONA_GPSW_XXX defines. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 3 diff --git a/Bindings/firmware/intel,stratix10-svc.txt b/Bindings/firmware/intel,stratix10-svc.txt index 1fa66065acc6..6eff1afd8daf 100644 --- a/Bindings/firmware/intel,stratix10-svc.txt +++ b/Bindings/firmware/intel,stratix10-svc.txt @@ -23,7 +23,7 @@ Required properties: The svc node has the following mandatory properties, must be located under the firmware node. -- compatible: "intel,stratix10-svc" +- compatible: "intel,stratix10-svc" or "intel,agilex-svc" - method: smc or hvc smc - Secure Monitor Call hvc - Hypervisor Call diff --git a/Bindings/fpga/intel-stratix10-soc-fpga-mgr.txt b/Bindings/fpga/intel-stratix10-soc-fpga-mgr.txt index 6e03f79287fb..0f874137ca46 100644 --- a/Bindings/fpga/intel-stratix10-soc-fpga-mgr.txt +++ b/Bindings/fpga/intel-stratix10-soc-fpga-mgr.txt @@ -4,7 +4,8 @@ Required properties: The fpga_mgr node has the following mandatory property, must be located under firmware/svc node. -- compatible : should contain "intel,stratix10-soc-fpga-mgr" +- compatible : should contain "intel,stratix10-soc-fpga-mgr" or + "intel,agilex-soc-fpga-mgr" Example: diff --git a/Bindings/gpio/brcm,xgs-iproc-gpio.yaml b/Bindings/gpio/brcm,xgs-iproc-gpio.yaml index 5f1ed20e43ee..4f2cbd8307a7 100644 --- a/Bindings/gpio/brcm,xgs-iproc-gpio.yaml +++ b/Bindings/gpio/brcm,xgs-iproc-gpio.yaml @@ -27,7 +27,7 @@ properties: gpio-controller: true '#gpio-cells': - const: 2 + const: 2 ngpios: minimum: 0 diff --git a/Bindings/gpio/fsl-imx-gpio.txt b/Bindings/gpio/fsl-imx-gpio.txt deleted file mode 100644 index b4cd9f906c24..000000000000 --- a/Bindings/gpio/fsl-imx-gpio.txt +++ /dev/null @@ -1,35 +0,0 @@ -* Freescale i.MX/MXC GPIO controller - -Required properties: -- compatible : Should be "fsl,-gpio" -- reg : Address and length of the register set for the device -- interrupts : Should be the port interrupt shared by all 32 pins, if - one number. If two numbers, the first one is the interrupt shared - by low 16 pins and the second one is for high 16 pins. -- gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells : Should be 2. The first cell is the GPIO number. - The second cell bits[3:0] is used to specify trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - -Optional properties: -- clocks: the clock for clocking the GPIO silicon - -Example: - -gpio0: gpio@73f84000 { - compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; - reg = <0x73f84000 0x4000>; - interrupts = <50 51>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/Bindings/gpio/fsl-imx-gpio.yaml b/Bindings/gpio/fsl-imx-gpio.yaml new file mode 100644 index 000000000000..0b223abe8cfb --- /dev/null +++ b/Bindings/gpio/fsl-imx-gpio.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/fsl-imx-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX/MXC GPIO controller + +maintainers: + - Anson Huang + +properties: + compatible: + enum: + - fsl,imx1-gpio + - fsl,imx21-gpio + - fsl,imx31-gpio + - fsl,imx35-gpio + - fsl,imx7d-gpio + + reg: + maxItems: 1 + + interrupts: + description: | + Should be the port interrupt shared by all 32 pins, if one number. + If two numbers, the first one is the interrupt shared by low 16 pins + and the second one is for high 16 pins. + minItems: 1 + maxItems: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + clocks: + maxItems: 1 + + "#gpio-cells": + const: 2 + + gpio-controller: true + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - "#gpio-cells" + - gpio-controller + +additionalProperties: false + +examples: + - | + gpio0: gpio@73f84000 { + compatible = "fsl,imx35-gpio"; + reg = <0x73f84000 0x4000>; + interrupts = <50 51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + +... diff --git a/Bindings/gpio/gpio-mxs.txt b/Bindings/gpio/gpio-mxs.txt deleted file mode 100644 index 1e677a47b836..000000000000 --- a/Bindings/gpio/gpio-mxs.txt +++ /dev/null @@ -1,88 +0,0 @@ -* Freescale MXS GPIO controller - -The Freescale MXS GPIO controller is part of MXS PIN controller. The -GPIOs are organized in port/bank. Each port consists of 32 GPIOs. - -As the GPIO controller is embedded in the PIN controller and all the -GPIO ports share the same IO space with PIN controller, the GPIO node -will be represented as sub-nodes of MXS pinctrl node. - -Required properties for GPIO node: -- compatible : Should be "fsl,-gpio". The supported SoCs include - imx23 and imx28. -- interrupts : Should be the port interrupt shared by all 32 pins. -- gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells : Should be 2. The first cell is the GPIO number. - The second cell bits[3:0] is used to specify trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - -Note: Each GPIO port should have an alias correctly numbered in "aliases" -node. - -Examples: - -aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - gpio4 = &gpio4; -}; - -pinctrl@80018000 { - compatible = "fsl,imx28-pinctrl", "simple-bus"; - reg = <0x80018000 2000>; - - gpio0: gpio@0 { - compatible = "fsl,imx28-gpio"; - interrupts = <127>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@1 { - compatible = "fsl,imx28-gpio"; - interrupts = <126>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@2 { - compatible = "fsl,imx28-gpio"; - interrupts = <125>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@3 { - compatible = "fsl,imx28-gpio"; - interrupts = <124>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@4 { - compatible = "fsl,imx28-gpio"; - interrupts = <123>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; -}; diff --git a/Bindings/gpio/gpio-mxs.yaml b/Bindings/gpio/gpio-mxs.yaml new file mode 100644 index 000000000000..ccf5b50e798b --- /dev/null +++ b/Bindings/gpio/gpio-mxs.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/gpio-mxs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MXS GPIO controller + +maintainers: + - Shawn Guo + - Anson Huang + +description: | + The Freescale MXS GPIO controller is part of MXS PIN controller. + The GPIOs are organized in port/bank, each port consists of 32 GPIOs. + As the GPIO controller is embedded in the PIN controller and all the + GPIO ports share the same IO space with PIN controller, the GPIO node + will be represented as sub-nodes of MXS pinctrl node. + +properties: + compatible: + enum: + - fsl,imx23-pinctrl + - fsl,imx28-pinctrl + + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + reg: + maxItems: 1 + +patternProperties: + "gpio@[0-9]+$": + type: object + properties: + compatible: + enum: + - fsl,imx23-gpio + - fsl,imx28-gpio + + reg: + maxItems: 1 + + interrupts: + description: Should be the port interrupt shared by all 32 pins. + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + "#gpio-cells": + const: 2 + + gpio-controller: true + + required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - "#gpio-cells" + - gpio-controller + + additionalProperties: false + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + pinctrl@80018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-pinctrl"; + reg = <0x80018000 0x2000>; + + gpio@0 { + compatible = "fsl,imx28-gpio"; + reg = <0>; + interrupts = <127>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio@1 { + compatible = "fsl,imx28-gpio"; + reg = <1>; + interrupts = <126>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio@2 { + compatible = "fsl,imx28-gpio"; + reg = <2>; + interrupts = <125>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio@3 { + compatible = "fsl,imx28-gpio"; + reg = <3>; + interrupts = <124>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio@4 { + compatible = "fsl,imx28-gpio"; + reg = <4>; + interrupts = <123>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; diff --git a/Bindings/gpio/mediatek,mt7621-gpio.txt b/Bindings/gpio/mediatek,mt7621-gpio.txt index ba455589f869..e1c49b660d3a 100644 --- a/Bindings/gpio/mediatek,mt7621-gpio.txt +++ b/Bindings/gpio/mediatek,mt7621-gpio.txt @@ -12,7 +12,7 @@ Required properties for the top level node: Only the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. - #interrupt-cells : Specifies the number of cells needed to encode an interrupt. Should be 2. The first cell defines the interrupt number, - the second encodes the triger flags encoded as described in + the second encodes the trigger flags encoded as described in Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - compatible: - "mediatek,mt7621-gpio" for Mediatek controllers diff --git a/Bindings/gpio/renesas,em-gio.yaml b/Bindings/gpio/renesas,em-gio.yaml new file mode 100644 index 000000000000..8bdef812c87c --- /dev/null +++ b/Bindings/gpio/renesas,em-gio.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/renesas,em-gio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas EMMA Mobile General Purpose I/O Interface + +maintainers: + - Magnus Damm + +properties: + compatible: + const: renesas,em-gio + + reg: + items: + - description: First set of contiguous registers + - description: Second set of contiguous registers + + interrupts: + items: + - description: Interrupt for the first set of 16 GPIO ports + - description: Interrupt for the second set of 16 GPIO ports + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + ngpios: + minimum: 1 + maximum: 32 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +required: + - compatible + - reg + - interrupts + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - ngpios + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + #include + gpio0: gpio@e0050000 { + compatible = "renesas,em-gio"; + reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 32>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Bindings/gpio/renesas,gpio-rcar.txt b/Bindings/gpio/renesas,gpio-rcar.txt deleted file mode 100644 index 10dce84b1545..000000000000 --- a/Bindings/gpio/renesas,gpio-rcar.txt +++ /dev/null @@ -1,94 +0,0 @@ -* Renesas R-Car GPIO Controller - -Required Properties: - - - compatible: should contain one or more of the following: - - "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller. - - "renesas,gpio-r8a7744": for R8A7744 (RZ/G1N) compatible GPIO controller. - - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller. - - "renesas,gpio-r8a77470": for R8A77470 (RZ/G1C) compatible GPIO controller. - - "renesas,gpio-r8a774a1": for R8A774A1 (RZ/G2M) compatible GPIO controller. - - "renesas,gpio-r8a774b1": for R8A774B1 (RZ/G2N) compatible GPIO controller. - - "renesas,gpio-r8a774c0": for R8A774C0 (RZ/G2E) compatible GPIO controller. - - "renesas,gpio-r8a7778": for R8A7778 (R-Car M1) compatible GPIO controller. - - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller. - - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller. - - "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller. - - "renesas,gpio-r8a7792": for R8A7792 (R-Car V2H) compatible GPIO controller. - - "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller. - - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller. - - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller. - - "renesas,gpio-r8a7796": for R8A77960 (R-Car M3-W) compatible GPIO controller. - - "renesas,gpio-r8a77961": for R8A77961 (R-Car M3-W+) compatible GPIO controller. - - "renesas,gpio-r8a77965": for R8A77965 (R-Car M3-N) compatible GPIO controller. - - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO controller. - - "renesas,gpio-r8a77980": for R8A77980 (R-Car V3H) compatible GPIO controller. - - "renesas,gpio-r8a77990": for R8A77990 (R-Car E3) compatible GPIO controller. - - "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO controller. - - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller. - - "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO controller. - - "renesas,rcar-gen3-gpio": for a generic R-Car Gen3 or RZ/G2 GPIO controller. - - "renesas,gpio-rcar": deprecated. - - When compatible with the generic version nodes must list the - SoC-specific version corresponding to the platform first followed by - the generic version. - - - reg: Base address and length of each memory resource used by the GPIO - controller hardware module. - - - interrupts: Interrupt specifier for the controllers interrupt. - - - gpio-controller: Marks the device node as a gpio controller. - - #gpio-cells: Should be 2. The first cell is the GPIO number and the second - cell specifies GPIO flags, as defined in . Only the - GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. - - gpio-ranges: See gpio.txt. - -Optional properties: - - - clocks: Must contain a reference to the functional clock. The property is - mandatory if the hardware implements a controllable functional clock for - the GPIO instance. - - - gpio-reserved-ranges: See gpio.txt. - -Please refer to gpio.txt in this directory for the common GPIO bindings used by -client devices. - -The GPIO controller also acts as an interrupt controller. It uses the default -two cells specifier as described in Documentation/devicetree/bindings/ -interrupt-controller/interrupts.txt. - -Example: R8A77470 (RZ/G1C) GPIO controller nodes - - gpio0: gpio@e6050000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6050000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 23>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 912>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 912>; - }; - ... - gpio3: gpio@e6053000 { - compatible = "renesas,gpio-r8a77470", - "renesas,rcar-gen2-gpio"; - reg = <0 0xe6053000 0 0x50>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 30>; - gpio-reserved-ranges = <17 10>; - #interrupt-cells = <2>; - interrupt-controller; - clocks = <&cpg CPG_MOD 909>; - power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; - resets = <&cpg 909>; - }; diff --git a/Bindings/gpio/renesas,rcar-gpio.yaml b/Bindings/gpio/renesas,rcar-gpio.yaml new file mode 100644 index 000000000000..397d9383d15a --- /dev/null +++ b/Bindings/gpio/renesas,rcar-gpio.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/renesas,rcar-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car General-Purpose Input/Output Ports (GPIO) + +maintainers: + - Geert Uytterhoeven + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,gpio-r8a7778 # R-Car M1 + - renesas,gpio-r8a7779 # R-Car H1 + - const: renesas,rcar-gen1-gpio # R-Car Gen1 + + - items: + - enum: + - renesas,gpio-r8a7742 # RZ/G1H + - renesas,gpio-r8a7743 # RZ/G1M + - renesas,gpio-r8a7744 # RZ/G1N + - renesas,gpio-r8a7745 # RZ/G1E + - renesas,gpio-r8a77470 # RZ/G1C + - renesas,gpio-r8a7790 # R-Car H2 + - renesas,gpio-r8a7791 # R-Car M2-W + - renesas,gpio-r8a7792 # R-Car V2H + - renesas,gpio-r8a7793 # R-Car M2-N + - renesas,gpio-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-gpio # R-Car Gen2 or RZ/G1 + + - items: + - enum: + - renesas,gpio-r8a774a1 # RZ/G2M + - renesas,gpio-r8a774b1 # RZ/G2N + - renesas,gpio-r8a774c0 # RZ/G2E + - renesas,gpio-r8a7795 # R-Car H3 + - renesas,gpio-r8a7796 # R-Car M3-W + - renesas,gpio-r8a77961 # R-Car M3-W+ + - renesas,gpio-r8a77965 # R-Car M3-N + - renesas,gpio-r8a77970 # R-Car V3M + - renesas,gpio-r8a77980 # R-Car V3H + - renesas,gpio-r8a77990 # R-Car E3 + - renesas,gpio-r8a77995 # R-Car D3 + - const: renesas,rcar-gen3-gpio # R-Car Gen3 or RZ/G2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 8 + +patternProperties: + "^.*$": + if: + type: object + then: + properties: + gpio-hog: true + gpios: true + input: true + output-high: true + output-low: true + line-name: true + + required: + - gpio-hog + - gpios + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - interrupt-controller + - '#interrupt-cells' + +if: + not: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen1-gpio +then: + required: + - clocks + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a77470", "renesas,rcar-gen2-gpio"; + reg = <0xe6053000 0x50>; + interrupts = ; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; + resets = <&cpg 909>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 96 30>; + gpio-reserved-ranges = <17 10>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Bindings/gpio/sifive,gpio.yaml b/Bindings/gpio/sifive,gpio.yaml index 418e8381e07c..a0efd8dc2538 100644 --- a/Bindings/gpio/sifive,gpio.yaml +++ b/Bindings/gpio/sifive,gpio.yaml @@ -57,7 +57,7 @@ examples: compatible = "sifive,fu540-c000-gpio", "sifive,gpio0"; interrupt-parent = <&plic>; interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; - reg = <0x0 0x10060000 0x0 0x1000>; + reg = <0x10060000 0x1000>; clocks = <&tlclk PRCI_CLK_TLCLK>; gpio-controller; #gpio-cells = <2>; diff --git a/Bindings/gpio/snps,dw-apb-gpio.yaml b/Bindings/gpio/snps,dw-apb-gpio.yaml new file mode 100644 index 000000000000..1240f6289249 --- /dev/null +++ b/Bindings/gpio/snps,dw-apb-gpio.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare APB GPIO controller + +description: | + Synopsys DesignWare GPIO controllers have a configurable number of ports, + each of which are intended to be represented as child nodes with the generic + GPIO-controller properties as desribed in this bindings file. + +maintainers: + - Hoan Tran + - Serge Semin + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + const: snps,dw-apb-gpio + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: APB interface clock source + - description: DW GPIO debounce reference clock source + + clock-names: + minItems: 1 + items: + - const: bus + - const: db + + resets: + maxItems: 1 + +patternProperties: + "^gpio-(port|controller)@[0-9a-f]+$": + type: object + properties: + compatible: + const: snps,dw-apb-gpio-port + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + snps,nr-gpios: + description: The number of GPIO pins exported by the port. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 32 + minimum: 1 + maximum: 32 + + interrupts: + description: | + The interrupts to the parent controller raised when GPIOs generate + the interrupts. If the controller provides one combined interrupt + for all GPIOs, specify a single interrupt. If the controller provides + one interrupt for each GPIO, provide a list of interrupts that + correspond to each of the GPIO pins. + minItems: 1 + maxItems: 32 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + + dependencies: + interrupt-controller: [ interrupts ] + + additionalProperties: false + +additionalProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +examples: + - | + gpio: gpio@20000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x20000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&vic1>; + interrupts = <0>; + }; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <8>; + }; + }; +... diff --git a/Bindings/gpio/snps-dwapb-gpio.txt b/Bindings/gpio/snps-dwapb-gpio.txt deleted file mode 100644 index 839dd32ffe11..000000000000 --- a/Bindings/gpio/snps-dwapb-gpio.txt +++ /dev/null @@ -1,65 +0,0 @@ -* Synopsys DesignWare APB GPIO controller - -Required properties: -- compatible : Should contain "snps,dw-apb-gpio" -- reg : Address and length of the register set for the device. -- #address-cells : should be 1 (for addressing port subnodes). -- #size-cells : should be 0 (port subnodes). - -The GPIO controller has a configurable number of ports, each of which are -represented as child nodes with the following properties: - -Required properties: -- compatible : "snps,dw-apb-gpio-port" -- gpio-controller : Marks the device node as a gpio controller. -- #gpio-cells : Should be two. The first cell is the pin number and - the second cell is used to specify the gpio polarity: - 0 = active high - 1 = active low -- reg : The integer port index of the port, a single cell. - -Optional properties: -- interrupt-controller : The first port may be configured to be an interrupt -controller. -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt. Shall be set to 2. The first cell defines the interrupt number, - the second encodes the triger flags encoded as described in - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -- interrupts : The interrupts to the parent controller raised when GPIOs - generate the interrupts. If the controller provides one combined interrupt - for all GPIOs, specify a single interrupt. If the controller provides one - interrupt for each GPIO, provide a list of interrupts that correspond to each - of the GPIO pins. When specifying multiple interrupts, if any are unconnected, - use the interrupts-extended property to specify the interrupts and set the - interrupt controller handle for unused interrupts to 0. -- snps,nr-gpios : The number of pins in the port, a single cell. -- resets : Reset line for the controller. - -Example: - -gpio: gpio@20000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x20000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&vic1>; - interrupts = <0>; - }; - - portb: gpio@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <8>; - reg = <1>; - }; -}; diff --git a/Bindings/gpu/arm,mali-bifrost.yaml b/Bindings/gpu/arm,mali-bifrost.yaml index 0b229a7d4a98..b1844b9c295d 100644 --- a/Bindings/gpu/arm,mali-bifrost.yaml +++ b/Bindings/gpu/arm,mali-bifrost.yaml @@ -43,9 +43,15 @@ properties: operating-points-v2: true + power-domains: + maxItems: 1 + resets: maxItems: 2 + "#cooling-cells": + const: 2 + required: - compatible - reg diff --git a/Bindings/gpu/arm,mali-midgard.yaml b/Bindings/gpu/arm,mali-midgard.yaml index 0407e45eb8c4..80d519a76db2 100644 --- a/Bindings/gpu/arm,mali-midgard.yaml +++ b/Bindings/gpu/arm,mali-midgard.yaml @@ -16,33 +16,33 @@ properties: oneOf: - items: - enum: - - samsung,exynos5250-mali + - samsung,exynos5250-mali - const: arm,mali-t604 - items: - enum: - - samsung,exynos5420-mali + - samsung,exynos5420-mali - const: arm,mali-t628 - items: - enum: - - allwinner,sun50i-h6-mali + - allwinner,sun50i-h6-mali - const: arm,mali-t720 - items: - enum: - - amlogic,meson-gxm-mali - - realtek,rtd1295-mali + - amlogic,meson-gxm-mali + - realtek,rtd1295-mali - const: arm,mali-t820 - items: - enum: - - arm,juno-mali + - arm,juno-mali - const: arm,mali-t624 - items: - enum: - - rockchip,rk3288-mali - - samsung,exynos5433-mali + - rockchip,rk3288-mali + - samsung,exynos5433-mali - const: arm,mali-t760 - items: - enum: - - rockchip,rk3399-mali + - rockchip,rk3399-mali - const: arm,mali-t860 # "arm,mali-t830" @@ -87,6 +87,8 @@ properties: "#cooling-cells": const: 2 + dma-coherent: true + required: - compatible - reg diff --git a/Bindings/gpu/arm,mali-utgard.yaml b/Bindings/gpu/arm,mali-utgard.yaml index f5401cc8de4a..6226d31ec4b7 100644 --- a/Bindings/gpu/arm,mali-utgard.yaml +++ b/Bindings/gpu/arm,mali-utgard.yaml @@ -41,6 +41,7 @@ properties: - amlogic,meson-gxbb-mali - amlogic,meson-gxl-mali - hisilicon,hi6220-mali + - mediatek,mt7623-mali - rockchip,rk3328-mali - const: arm,mali-450 @@ -107,6 +108,9 @@ properties: operating-points-v2: true + "#cooling-cells": + const: 2 + required: - compatible - reg @@ -130,6 +134,7 @@ allOf: - amlogic,meson8-mali - amlogic,meson8b-mali - hisilicon,hi6220-mali + - mediatek,mt7623-mali - rockchip,rk3036-mali - rockchip,rk3066-mali - rockchip,rk3188-mali @@ -164,6 +169,7 @@ examples: clocks = <&ccu 1>, <&ccu 2>; clock-names = "bus", "core"; resets = <&ccu 1>; + #cooling-cells = <2>; }; ... diff --git a/Bindings/gpu/vivante,gc.yaml b/Bindings/gpu/vivante,gc.yaml index 0bc4b38d5cbb..e1ac6ff5a230 100644 --- a/Bindings/gpu/vivante,gc.yaml +++ b/Bindings/gpu/vivante,gc.yaml @@ -9,7 +9,7 @@ title: Vivante GPU Bindings description: Vivante GPU core devices maintainers: - - Lucas Stach + - Lucas Stach properties: compatible: diff --git a/Bindings/hwmon/adi,axi-fan-control.yaml b/Bindings/hwmon/adi,axi-fan-control.yaml index 7db78767c02d..af35b77053df 100644 --- a/Bindings/hwmon/adi,axi-fan-control.yaml +++ b/Bindings/hwmon/adi,axi-fan-control.yaml @@ -34,8 +34,7 @@ properties: description: Value specifying the number of pulses per revolution of the controlled FAN. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 2, 4] required: diff --git a/Bindings/hwmon/adi,ltc2947.yaml b/Bindings/hwmon/adi,ltc2947.yaml index 44a63fffb4be..eef614962b10 100644 --- a/Bindings/hwmon/adi,ltc2947.yaml +++ b/Bindings/hwmon/adi,ltc2947.yaml @@ -38,20 +38,18 @@ properties: the accumulated values, this entry can also have two items which sets energy1/charge1 and energy2/charger2 respectively. Check table 12 of the datasheet for more information on the supported options. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 2 - maxItems: 2 - items: - enum: [0, 1, 2, 3] - default: 0 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + items: + enum: [0, 1, 2, 3] + default: 0 adi,accumulation-deadband-microamp: description: This property controls the Accumulation Dead band which allows to set the level of current below which no accumulation takes place. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 maximum: 255 default: 0 @@ -61,8 +59,7 @@ properties: active high, setting it to zero makets it active low. When this property is present, the GPIO is automatically configured as output and set to control a fan as a function of measured temperature. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1] default: 0 @@ -74,13 +71,12 @@ properties: registers. Check table 13 of the datasheet for more information on the supported options. This property cannot be used together with adi,gpio-out-pol. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 2 - maxItems: 2 - items: - enum: [0, 1, 2] - default: 0 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + items: + enum: [0, 1, 2] + default: 0 required: - compatible diff --git a/Bindings/hwmon/adt7475.yaml b/Bindings/hwmon/adt7475.yaml index 46c441574f98..dfa821c0aacc 100644 --- a/Bindings/hwmon/adt7475.yaml +++ b/Bindings/hwmon/adt7475.yaml @@ -46,22 +46,20 @@ patternProperties: set to 1 the attenuator is bypassed if set to 0 the attenuator is not bypassed. If the property is absent then the attenuator retains it's configuration from the bios/bootloader. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [0, 1] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] "^adi,pwm-active-state$": description: | Integer array, represents the active state of the pwm outputs If set to 0 the pwm uses a logic low output for 100% duty cycle. If set to 1 the pwm uses a logic high output for 100% duty cycle. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 3 - maxItems: 3 - items: - enum: [0, 1] - default: 1 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + items: + enum: [0, 1] + default: 1 required: - compatible diff --git a/Bindings/hwmon/baikal,bt1-pvt.yaml b/Bindings/hwmon/baikal,bt1-pvt.yaml new file mode 100644 index 000000000000..84ae4cdd08ed --- /dev/null +++ b/Bindings/hwmon/baikal,bt1-pvt.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/baikal,bt1-pvt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 PVT Sensor + +maintainers: + - Serge Semin + +description: | + Baikal-T1 SoC provides an embedded process, voltage and temperature + sensor to monitor an internal SoC environment (chip temperature, supply + voltage and process monitor) and on time detect critical situations, + which may cause the system instability and even damages. The IP-block + is based on the Analog Bits PVT sensor, but is equipped with a dedicated + control wrapper, which provides a MMIO registers-based access to the + sensor core functionality (APB3-bus based) and exposes an additional + functions like thresholds/data ready interrupts, its status and masks, + measurements timeout. Its internal structure is depicted on the next + diagram: + + Analog Bits core Bakal-T1 PVT control block + +--------------------+ +------------------------+ + | Temperature sensor |-+ +------| Sensors control | + |--------------------| |<---En---| |------------------------| + | Voltage sensor |-|<--Mode--| +--->| Sampled data | + |--------------------| |<--Trim--+ | |------------------------| + | Low-Vt sensor |-| | +--| Thresholds comparator | + |--------------------| |---Data----| | |------------------------| + | High-Vt sensor |-| | +->| Interrupts status | + |--------------------| |--Valid--+-+ | |------------------------| + | Standard-Vt sensor |-+ +---+--| Interrupts mask | + +--------------------+ |------------------------| + ^ | Interrupts timeout | + | +------------------------+ + | ^ ^ + Rclk-----+----------------------------------------+ | + APB3-------------------------------------------------+ + + This bindings describes the external Baikal-T1 PVT control interfaces + like MMIO registers space, interrupt request number and clocks source. + These are then used by the corresponding hwmon device driver to + implement the sysfs files-based access to the sensors functionality. + +properties: + compatible: + const: baikal,bt1-pvt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PVT reference clock + - description: APB3 interface clock + + clock-names: + items: + - const: ref + - const: pclk + + "#thermal-sensor-cells": + description: Baikal-T1 can be referenced as the CPU thermal-sensor + const: 0 + + baikal,pvt-temp-offset-millicelsius: + description: | + Temperature sensor trimming factor. It can be used to manually adjust the + temperature measurements within 7.130 degrees Celsius. + maxItems: 1 + items: + default: 0 + minimum: 0 + maximum: 7130 + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + #include + + pvt@1f200000 { + compatible = "baikal,bt1-pvt"; + reg = <0x1f200000 0x1000>; + #thermal-sensor-cells = <0>; + + interrupts = ; + + baikal,pvt-temp-trim-millicelsius = <1000>; + + clocks = <&ccu_sys>, <&ccu_sys>; + clock-names = "ref", "pclk"; + }; +... diff --git a/Bindings/hwmon/cirrus,lochnagar.txt b/Bindings/hwmon/cirrus,lochnagar.txt deleted file mode 100644 index ffb79ccf51ee..000000000000 --- a/Bindings/hwmon/cirrus,lochnagar.txt +++ /dev/null @@ -1,26 +0,0 @@ -Cirrus Logic Lochnagar Audio Development Board - -Lochnagar is an evaluation and development board for Cirrus Logic -Smart CODEC and Amp devices. It allows the connection of most Cirrus -Logic devices on mini-cards, as well as allowing connection of -various application processor systems to provide a full evaluation -platform. Audio system topology, clocking and power can all be -controlled through the Lochnagar, allowing the device under test -to be used in a variety of possible use cases. - -This binding document describes the binding for the hardware monitor -portion of the driver. - -This binding must be part of the Lochnagar MFD binding: - [4] ../mfd/cirrus,lochnagar.txt - -Required properties: - - - compatible : One of the following strings: - "cirrus,lochnagar2-hwmon" - -Example: - -lochnagar-hwmon { - compatible = "cirrus,lochnagar2-hwmon"; -}; diff --git a/Bindings/hwmon/cirrus,lochnagar.yaml b/Bindings/hwmon/cirrus,lochnagar.yaml new file mode 100644 index 000000000000..cc00b97a7dac --- /dev/null +++ b/Bindings/hwmon/cirrus,lochnagar.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/cirrus,lochnagar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic Lochnagar Audio Development Board + +maintainers: + - patches@opensource.cirrus.com + +description: | + Lochnagar is an evaluation and development board for Cirrus Logic + Smart CODEC and Amp devices. It allows the connection of most Cirrus + Logic devices on mini-cards, as well as allowing connection of various + application processor systems to provide a full evaluation platform. + Audio system topology, clocking and power can all be controlled through + the Lochnagar, allowing the device under test to be used in a variety of + possible use cases. + + This binding document describes the binding for the hardware monitor + portion of the driver. + + This binding must be part of the Lochnagar MFD binding: + [1] ../mfd/cirrus,lochnagar.yaml + +properties: + compatible: + enum: + - cirrus,lochnagar2-hwmon + +required: + - compatible + +additionalProperties: false diff --git a/Bindings/hwmon/ti,tmp513.yaml b/Bindings/hwmon/ti,tmp513.yaml index 3f043e943668..90b2fa3f7752 100644 --- a/Bindings/hwmon/ti,tmp513.yaml +++ b/Bindings/hwmon/ti,tmp513.yaml @@ -45,16 +45,14 @@ properties: The gain value for the PGA function. This is 8, 4, 2 or 1. The PGA gain affect the shunt voltage range. The range will be equal to: pga-gain * 40mV - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 2, 4, 8] default: 8 ti,bus-range-microvolt: description: | This is the operating range of the bus voltage in microvolt - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 enum: [16000000, 32000000] default: 32000000 @@ -63,14 +61,13 @@ properties: Array of three(TMP513) or two(TMP512) n-Factor value for each remote temperature channel. See datasheet Table 11 for n-Factor range list and value interpretation. - allOf: - - $ref: /schemas/types.yaml#definitions/uint32-array - - minItems: 2 - maxItems: 3 - items: - default: 0x00 - minimum: 0x00 - maximum: 0xFF + $ref: /schemas/types.yaml#definitions/uint32-array + minItems: 2 + maxItems: 3 + items: + default: 0x00 + minimum: 0x00 + maximum: 0xFF required: - compatible diff --git a/Bindings/i2c/brcm,bcm2835-i2c.txt b/Bindings/i2c/brcm,bcm2835-i2c.txt index c9a6587fe4bb..a8a35df41951 100644 --- a/Bindings/i2c/brcm,bcm2835-i2c.txt +++ b/Bindings/i2c/brcm,bcm2835-i2c.txt @@ -13,7 +13,7 @@ Recommended properties: Example: -i2c@20205000 { +i2c@7e205000 { compatible = "brcm,bcm2835-i2c"; reg = <0x7e205000 0x1000>; interrupts = <2 21>; diff --git a/Bindings/i2c/cdns,i2c-r1p10.yaml b/Bindings/i2c/cdns,i2c-r1p10.yaml new file mode 100644 index 000000000000..dc0952f3780f --- /dev/null +++ b/Bindings/i2c/cdns,i2c-r1p10.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence I2C controller Device Tree Bindings + +maintainers: + - Michal Simek + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + enum: + - cdns,i2c-r1p10 # cadence i2c controller version 1.0 + - cdns,i2c-r1p14 # cadence i2c controller version 1.4 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: + minimum: 1 + maximum: 400000 + description: | + Desired operating frequency, in Hz, of the bus. + + clock-name: + const: pclk + description: | + Input clock name. + +required: + - compatible + - reg + - clocks + - interrupts + +examples: + - | + #include + i2c@e0004000 { + compatible = "cdns,i2c-r1p10"; + clocks = <&clkc 38>; + interrupts = ; + reg = <0xe0004000 0x1000>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Bindings/i2c/i2c-cadence.txt b/Bindings/i2c/i2c-cadence.txt deleted file mode 100644 index ebaa90c58c8e..000000000000 --- a/Bindings/i2c/i2c-cadence.txt +++ /dev/null @@ -1,28 +0,0 @@ -Binding for the Cadence I2C controller - -Required properties: - - reg: Physical base address and size of the controller's register area. - - compatible: Should contain one of: - * "cdns,i2c-r1p10" - Note: Use this when cadence i2c controller version 1.0 is used. - * "cdns,i2c-r1p14" - Note: Use this when cadence i2c controller version 1.4 is used. - - clocks: Input clock specifier. Refer to common clock bindings. - - interrupts: Interrupt specifier. Refer to interrupt bindings. - - #address-cells: Should be 1. - - #size-cells: Should be 0. - -Optional properties: - - clock-frequency: Desired operating frequency, in Hz, of the bus. - - clock-names: Input clock name, should be 'pclk'. - -Example: - i2c@e0004000 { - compatible = "cdns,i2c-r1p10"; - clocks = <&clkc 38>; - interrupts = ; - reg = <0xe0004000 0x1000>; - clock-frequency = <400000>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Bindings/i2c/i2c-designware.txt b/Bindings/i2c/i2c-designware.txt deleted file mode 100644 index 08be4d3846e5..000000000000 --- a/Bindings/i2c/i2c-designware.txt +++ /dev/null @@ -1,73 +0,0 @@ -* Synopsys DesignWare I2C - -Required properties : - - - compatible : should be "snps,designware-i2c" - or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback - - reg : Offset and length of the register set for the device - - interrupts : where IRQ is the interrupt number. - - clocks : phandles for the clocks, see the description of clock-names below. - The phandle for the "ic_clk" clock is required. The phandle for the "pclk" - clock is optional. If a single clock is specified but no clock-name, it is - the "ic_clk" clock. If both clocks are listed, the "ic_clk" must be first. - -Recommended properties : - - - clock-frequency : desired I2C bus clock frequency in Hz. - -Optional properties : - - - clock-names : Contains the names of the clocks: - "ic_clk", for the core clock used to generate the external I2C clock. - "pclk", the interface clock, required for register access. - - - reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold - time, named ICPU_CFG:TWI_DELAY in the datasheet. - - - i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds. - This option is only supported in hardware blocks version 1.11a or newer and - on Microsemi SoCs ("mscc,ocelot-i2c" compatible). - - - i2c-scl-falling-time-ns : should contain the SCL falling time in nanoseconds. - This value which is by default 300ns is used to compute the tLOW period. - - - i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds. - This value which is by default 300ns is used to compute the tHIGH period. - -Examples : - - i2c@f0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xf0000 0x1000>; - interrupts = <11>; - clock-frequency = <400000>; - }; - - i2c@1120000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0x1120000 0x1000>; - interrupt-parent = <&ictl>; - interrupts = <12 1>; - clock-frequency = <400000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <300>; - i2c-scl-falling-time-ns = <300>; - }; - - i2c@1120000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2000 0x100>; - clock-frequency = <400000>; - clocks = <&i2cclk>; - interrupts = <0>; - - eeprom@64 { - compatible = "linux,slave-24c02"; - reg = <0x40000064>; - }; - }; diff --git a/Bindings/i2c/i2c-jz4780.txt b/Bindings/i2c/i2c-jz4780.txt deleted file mode 100644 index d229eff5ca1b..000000000000 --- a/Bindings/i2c/i2c-jz4780.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Ingenic JZ4780 I2C Bus controller - -Required properties: -- compatible: should be one of the following: - - "ingenic,jz4780-i2c" for the JZ4780 - - "ingenic,x1000-i2c" for the X1000 -- reg: Should contain the address & size of the I2C controller registers. -- interrupts: Should specify the interrupt provided by parent. -- clocks: Should contain a single clock specifier for the JZ4780 I2C clock. -- clock-frequency: desired I2C bus clock frequency in Hz. - -Recommended properties: -- pinctrl-names: should be "default"; -- pinctrl-0: phandle to pinctrl function - -Example - -/ { - i2c4: i2c4@10054000 { - compatible = "ingenic,jz4780-i2c"; - reg = <0x10054000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <56>; - - clocks = <&cgu JZ4780_CLK_SMB4>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pins_i2c4_data>; - - }; -}; - diff --git a/Bindings/i2c/i2c-mt65xx.txt b/Bindings/i2c/i2c-mt65xx.txt index 68f6d73a8b73..88b71c1b32c9 100644 --- a/Bindings/i2c/i2c-mt65xx.txt +++ b/Bindings/i2c/i2c-mt65xx.txt @@ -8,6 +8,7 @@ Required properties: "mediatek,mt2712-i2c": for MediaTek MT2712 "mediatek,mt6577-i2c": for MediaTek MT6577 "mediatek,mt6589-i2c": for MediaTek MT6589 + "mediatek,mt6797-i2c", "mediatek,mt6577-i2c": for MediaTek MT6797 "mediatek,mt7622-i2c": for MediaTek MT7622 "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623 "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629 diff --git a/Bindings/i2c/i2c-qcom-cci.txt b/Bindings/i2c/i2c-qcom-cci.txt new file mode 100644 index 000000000000..c6668b7c66e6 --- /dev/null +++ b/Bindings/i2c/i2c-qcom-cci.txt @@ -0,0 +1,92 @@ +Qualcomm Camera Control Interface (CCI) I2C controller + +PROPERTIES: + +- compatible: + Usage: required + Value type: + Definition: must be one of: + "qcom,msm8916-cci" + "qcom,msm8996-cci" + "qcom,sdm845-cci" + +- reg + Usage: required + Value type: + Definition: base address CCI I2C controller and length of memory + mapped region. + +- interrupts: + Usage: required + Value type: + Definition: specifies the CCI I2C interrupt. The format of the + specifier is defined by the binding document describing + the node's interrupt parent. + +- clocks: + Usage: required + Value type: + Definition: a list of phandle, should contain an entry for each + entries in clock-names. + +- clock-names + Usage: required + Value type: + Definition: a list of clock names, must include "cci" clock. + +- power-domains + Usage: required for "qcom,msm8996-cci" + Value type: + Definition: + +SUBNODES: + +The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996 and +sdm845), described as subdevices named "i2c-bus@0" and "i2c-bus@1". + +PROPERTIES: + +- reg: + Usage: required + Value type: + Definition: Index of the CCI bus/master + +- clock-frequency: + Usage: optional + Value type: + Definition: Desired I2C bus clock frequency in Hz, defaults to 100 + kHz if omitted. + +Example: + + cci@a0c000 { + compatible = "qcom,msm8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa0c000 0x1000>; + interrupts = ; + clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>, + <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CLK>, + <&mmcc CAMSS_AHB_CLK>; + clock-names = "mmss_mmagic_ahb", + "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + + i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; diff --git a/Bindings/i2c/i2c-rk3x.yaml b/Bindings/i2c/i2c-rk3x.yaml index 61eac76c84c4..790aa7218ee0 100644 --- a/Bindings/i2c/i2c-rk3x.yaml +++ b/Bindings/i2c/i2c-rk3x.yaml @@ -28,14 +28,14 @@ properties: - const: rockchip,rk3399-i2c - items: - enum: - - rockchip,rk3036-i2c - - rockchip,rk3368-i2c + - rockchip,rk3036-i2c + - rockchip,rk3368-i2c - const: rockchip,rk3288-i2c - items: - enum: - - rockchip,px30-i2c - - rockchip,rk3308-i2c - - rockchip,rk3328-i2c + - rockchip,px30-i2c + - rockchip,rk3308-i2c + - rockchip,rk3328-i2c - const: rockchip,rk3399-i2c reg: diff --git a/Bindings/i2c/i2c-xiic.txt b/Bindings/i2c/i2c-xiic.txt deleted file mode 100644 index caf42e989462..000000000000 --- a/Bindings/i2c/i2c-xiic.txt +++ /dev/null @@ -1,25 +0,0 @@ -Xilinx IIC controller: - -Required properties: -- compatible : Must be "xlnx,xps-iic-2.00.a" -- reg : IIC register location and length -- interrupts : IIC controller unterrupt -- #address-cells = <1> -- #size-cells = <0> -- clocks: Input clock specifier. Refer to common clock bindings. - -Optional properties: -- Child nodes conforming to i2c bus binding -- clock-names: Input clock name, should be 'pclk'. - -Example: - - axi_iic_0: i2c@40800000 { - compatible = "xlnx,xps-iic-2.00.a"; - clocks = <&clkc 15>; - interrupts = < 1 2 >; - reg = < 0x40800000 0x10000 >; - - #size-cells = <0>; - #address-cells = <1>; - }; diff --git a/Bindings/i2c/i2c.txt b/Bindings/i2c/i2c.txt index 9a53df4243c6..438ae123107e 100644 --- a/Bindings/i2c/i2c.txt +++ b/Bindings/i2c/i2c.txt @@ -2,32 +2,26 @@ Generic device tree bindings for I2C busses =========================================== This document describes generic bindings which can be used to describe I2C -busses in a device tree. +busses and their child devices in a device tree. -Required properties -------------------- +Required properties (per bus) +----------------------------- - #address-cells - should be <1>. Read more about addresses below. - #size-cells - should be <0>. -- compatible - name of I2C bus controller following generic names - recommended practice. +- compatible - name of I2C bus controller For other required properties e.g. to describe register sets, clocks, etc. check the binding documentation of the specific driver. The cells properties above define that an address of children of an I2C bus -are described by a single value. This is usually a 7 bit address. However, -flags can be attached to the address. I2C_TEN_BIT_ADDRESS is used to mark a 10 -bit address. It is needed to avoid the ambiguity between e.g. a 7 bit address -of 0x50 and a 10 bit address of 0x050 which, in theory, can be on the same bus. -Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we listen to -be devices ourselves. +are described by a single value. -Optional properties -------------------- +Optional properties (per bus) +----------------------------- These properties may not be supported by all drivers. However, if a driver -wants to support one of the below features, it should adapt the bindings below. +wants to support one of the below features, it should adapt these bindings. - clock-frequency frequency of bus clock in Hz. @@ -73,6 +67,40 @@ wants to support one of the below features, it should adapt the bindings below. i2c bus clock frequency (clock-frequency). Specified in Hz. +- multi-master + states that there is another master active on this bus. The OS can use + this information to adapt power management to keep the arbitration awake + all the time, for example. Can not be combined with 'single-master'. + +- single-master + states that there is no other master active on this bus. The OS can use + this information to detect a stalled bus more reliably, for example. + Can not be combined with 'multi-master'. + +Required properties (per child device) +-------------------------------------- + +- compatible + name of I2C slave device + +- reg + One or many I2C slave addresses. These are usually a 7 bit addresses. + However, flags can be attached to an address. I2C_TEN_BIT_ADDRESS is + used to mark a 10 bit address. It is needed to avoid the ambiguity + between e.g. a 7 bit address of 0x50 and a 10 bit address of 0x050 + which, in theory, can be on the same bus. + Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we + listen to be devices ourselves. + +Optional properties (per child device) +-------------------------------------- + +These properties may not be supported by all drivers. However, if a driver +wants to support one of the below features, it should adapt these bindings. + +- host-notify + device uses SMBus host notify protocol instead of interrupt line. + - interrupts interrupts used by the device. @@ -80,24 +108,13 @@ wants to support one of the below features, it should adapt the bindings below. "irq", "wakeup" and "smbus_alert" names are recognized by I2C core, other names are left to individual drivers. -- host-notify - device uses SMBus host notify protocol instead of interrupt line. - -- multi-master - states that there is another master active on this bus. The OS can use - this information to adapt power management to keep the arbitration awake - all the time, for example. - -- wakeup-source - device can be used as a wakeup source. - -- reg - I2C slave addresses - - reg-names Names of map programmable addresses. It can contain any map needing another address than default one. +- wakeup-source + device can be used as a wakeup source. + Binding may contain optional "interrupts" property, describing interrupts used by the device. I2C core will assign "irq" interrupt (or the very first interrupt if not using interrupt names) as primary interrupt for the slave. diff --git a/Bindings/i2c/ingenic,i2c.yaml b/Bindings/i2c/ingenic,i2c.yaml new file mode 100644 index 000000000000..682ed1bbf5c6 --- /dev/null +++ b/Bindings/i2c/ingenic,i2c.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/ingenic,i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs I2C controller devicetree bindings + +maintainers: + - Paul Cercueil + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + $nodename: + pattern: "^i2c@[0-9a-f]+$" + + compatible: + enum: + - ingenic,jz4780-i2c + - ingenic,x1000-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + enum: [ 100000, 400000 ] + + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + + dma-names: + items: + - const: rx + - const: tx + +required: + - compatible + - reg + - interrupts + - clocks + - clock-frequency + - dmas + - dma-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + i2c@10054000 { + compatible = "ingenic,jz4780-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10054000 0x1000>; + + interrupt-parent = <&intc>; + interrupts = <56>; + + clocks = <&cgu JZ4780_CLK_SMB4>; + pinctrl-names = "default"; + pinctrl-0 = <&pins_i2c4_data>; + + dmas = <&dma JZ4780_DMA_SMB4_RX 0xffffffff>, + <&dma JZ4780_DMA_SMB4_TX 0xffffffff>; + dma-names = "rx", "tx"; + + clock-frequency = <400000>; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + + interrupt-parent = <&gpf>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + }; + }; diff --git a/Bindings/i2c/nuvoton,npcm7xx-i2c.yaml b/Bindings/i2c/nuvoton,npcm7xx-i2c.yaml new file mode 100644 index 000000000000..e3ef2d36f372 --- /dev/null +++ b/Bindings/i2c/nuvoton,npcm7xx-i2c.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: nuvoton NPCM7XX I2C Controller Device Tree Bindings + +description: | + The NPCM750x includes sixteen I2C bus controllers. All Controllers support + both master and slave mode. Each controller can switch between master and slave + at run time (i.e. IPMB mode). Each controller has two 16 byte HW FIFO for TX and + RX. + +maintainers: + - Tali Perry + +properties: + compatible: + const: nuvoton,npcm7xx-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: Reference clock for the I2C bus + + clock-frequency: + description: Desired I2C bus clock frequency in Hz. If not specified, + the default 100 kHz frequency will be used. + possible values are 100000, 400000 and 1000000. + default: 100000 + enum: [100000, 400000, 1000000] + +required: + - compatible + - reg + - interrupts + - clocks + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + i2c0: i2c@80000 { + reg = <0x80000 0x1000>; + clocks = <&clk NPCM7XX_CLK_APB2>; + clock-frequency = <100000>; + interrupts = ; + compatible = "nuvoton,npcm750-i2c"; + }; + +... diff --git a/Bindings/i2c/nvidia,tegra20-i2c.txt b/Bindings/i2c/nvidia,tegra20-i2c.txt index f64064f8bdc2..18c0de362451 100644 --- a/Bindings/i2c/nvidia,tegra20-i2c.txt +++ b/Bindings/i2c/nvidia,tegra20-i2c.txt @@ -35,6 +35,12 @@ Required properties: Due to above changes, Tegra114 I2C driver makes incompatible with previous hardware driver. Hence, tegra114 I2C controller is compatible with "nvidia,tegra114-i2c". + nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is part of the + host1x domain and typically used for camera use-cases. This VI I2C + controller is mostly compatible with the programming model of the + regular I2C controllers with a few exceptions. The I2C registers start + at an offset of 0xc00 (instead of 0), registers are 16 bytes apart + (rather than 4) and the controller does not support slave mode. - reg: Should contain I2C controller registers physical address and length. - interrupts: Should contain I2C controller interrupts. - address-cells: Address cells for I2C device address. diff --git a/Bindings/i2c/renesas,i2c.txt b/Bindings/i2c/renesas,i2c.txt index c359965d0724..a03f9f5cb378 100644 --- a/Bindings/i2c/renesas,i2c.txt +++ b/Bindings/i2c/renesas,i2c.txt @@ -2,6 +2,7 @@ I2C for R-Car platforms Required properties: - compatible: + "renesas,i2c-r8a7742" if the device is a part of a R8A7742 SoC. "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC. "renesas,i2c-r8a7744" if the device is a part of a R8A7744 SoC. "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC. diff --git a/Bindings/i2c/renesas,iic.txt b/Bindings/i2c/renesas,iic.txt index ffe085c9947e..89facb09337a 100644 --- a/Bindings/i2c/renesas,iic.txt +++ b/Bindings/i2c/renesas,iic.txt @@ -4,6 +4,7 @@ Required properties: - compatible : - "renesas,iic-r8a73a4" (R-Mobile APE6) - "renesas,iic-r8a7740" (R-Mobile A1) + - "renesas,iic-r8a7742" (RZ/G1H) - "renesas,iic-r8a7743" (RZ/G1M) - "renesas,iic-r8a7744" (RZ/G1N) - "renesas,iic-r8a7745" (RZ/G1E) diff --git a/Bindings/i2c/snps,designware-i2c.yaml b/Bindings/i2c/snps,designware-i2c.yaml new file mode 100644 index 000000000000..4f746bef2374 --- /dev/null +++ b/Bindings/i2c/snps,designware-i2c.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare APB I2C Controller + +maintainers: + - Jarkko Nikula + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + - if: + properties: + compatible: + not: + contains: + const: mscc,ocelot-i2c + then: + properties: + reg: + maxItems: 1 + +properties: + compatible: + oneOf: + - description: Generic Synopsys DesignWare I2C controller + const: snps,designware-i2c + - description: Microsemi Ocelot SoCs I2C controller + items: + - const: mscc,ocelot-i2c + - const: snps,designware-i2c + - description: Baikal-T1 SoC System I2C controller + const: baikal,bt1-sys-i2c + + reg: + minItems: 1 + items: + - description: DW APB I2C controller memory mapped registers + - description: | + ICPU_CFG:TWI_DELAY registers to setup the SDA hold time. + This registers are specific to the Ocelot I2C-controller. + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: I2C controller reference clock source + - description: APB interface clock source + + clock-names: + minItems: 1 + items: + - const: ref + - const: pclk + + resets: + maxItems: 1 + + clock-frequency: + description: Desired I2C bus clock frequency in Hz + enum: [100000, 400000, 1000000, 3400000] + default: 400000 + + i2c-sda-hold-time-ns: + maxItems: 1 + description: | + The property should contain the SDA hold time in nanoseconds. This option + is only supported in hardware blocks version 1.11a or newer or on + Microsemi SoCs. + + i2c-scl-falling-time-ns: + maxItems: 1 + description: | + The property should contain the SCL falling time in nanoseconds. + This value is used to compute the tLOW period. + default: 300 + + i2c-sda-falling-time-ns: + maxItems: 1 + description: | + The property should contain the SDA falling time in nanoseconds. + This value is used to compute the tHIGH period. + default: 300 + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + +unevaluatedProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - interrupts + +examples: + - | + i2c@f0000 { + compatible = "snps,designware-i2c"; + reg = <0xf0000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <11>; + clock-frequency = <400000>; + }; + - | + i2c@1120000 { + compatible = "snps,designware-i2c"; + reg = <0x1120000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <12 1>; + clock-frequency = <400000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <300>; + i2c-scl-falling-time-ns = <300>; + }; + - | + i2c@2000 { + compatible = "snps,designware-i2c"; + reg = <0x2000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&i2cclk>; + interrupts = <0>; + + eeprom@64 { + compatible = "atmel,24c02"; + reg = <0x64>; + }; + }; + - | + i2c@100400 { + compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; + reg = <0x100400 0x100>, <0x198 0x8>; + pinctrl-0 = <&i2c_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <8>; + clocks = <&ahb_clk>; + }; +... diff --git a/Bindings/i2c/st,stm32-i2c.yaml b/Bindings/i2c/st,stm32-i2c.yaml index 900ec1ab6a47..f2fcbb361180 100644 --- a/Bindings/i2c/st,stm32-i2c.yaml +++ b/Bindings/i2c/st,stm32-i2c.yaml @@ -17,6 +17,7 @@ allOf: contains: enum: - st,stm32f7-i2c + - st,stm32mp15-i2c then: properties: i2c-scl-rising-time-ns: @@ -30,11 +31,10 @@ allOf: Fast Mode Plus speed is selected by slave. Format is phandle to syscfg / register offset within syscfg / register bitmask for FMP bit. - allOf: - - $ref: "/schemas/types.yaml#/definitions/phandle-array" - - items: - minItems: 3 - maxItems: 3 + $ref: "/schemas/types.yaml#/definitions/phandle-array" + items: + minItems: 3 + maxItems: 3 - if: properties: @@ -52,6 +52,7 @@ properties: enum: - st,stm32f4-i2c - st,stm32f7-i2c + - st,stm32mp15-i2c reg: maxItems: 1 @@ -80,11 +81,11 @@ properties: clock-frequency: description: Desired I2C bus clock frequency in Hz. If not specified, the default 100 kHz frequency will be used. - For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode, - Fast-mode and Fast-mode Plus are supported, possible - values are 100000, 400000 and 1000000. + For STM32F7, STM32H7 and STM32MP1 SoCs, if timing parameters + match, the bus clock frequency can be from 1Hz to 1MHz. default: 100000 - enum: [100000, 400000, 1000000] + minimum: 1 + maximum: 1000000 required: - compatible @@ -121,12 +122,12 @@ examples: clocks = <&rcc 1 CLK_I2C1>; }; - //Example 3 (with st,stm32f7-i2c compatible on stm32mp) + //Example 3 (with st,stm32mp15-i2c compatible on stm32mp) #include #include #include i2c@40013000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x40013000 0x400>; diff --git a/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml b/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml new file mode 100644 index 000000000000..67c1c84ba3dc --- /dev/null +++ b/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/i2c/xlnx,xps-iic-2.00.a.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ilinx IIC controller Device Tree Bindings + +maintainers: + - info@mocean-labs.com + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: xlnx,xps-iic-2.00.a + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + + clock-name: + const: pclk + description: | + Input clock name. + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + axi_iic_0: i2c@40800000 { + compatible = "xlnx,xps-iic-2.00.a"; + clocks = <&clkc 15>; + interrupts = < 1 2 >; + reg = < 0x40800000 0x10000 >; + + #size-cells = <0>; + #address-cells = <1>; + }; diff --git a/Bindings/iio/accel/bma180.txt b/Bindings/iio/accel/bma180.txt index f53237270b32..33da4a6fdb39 100644 --- a/Bindings/iio/accel/bma180.txt +++ b/Bindings/iio/accel/bma180.txt @@ -1,15 +1,21 @@ -* Bosch BMA180 / BMA25x triaxial acceleration sensor +* Bosch BMA023 / BMA150/ BMA180 / BMA25x / SMB380 triaxial acceleration sensor +https://media.digikey.com/pdf/Data%20Sheets/Bosch/BMA150.pdf http://omapworld.com/BMA180_111_1002839.pdf http://ae-bst.resource.bosch.com/media/products/dokumente/bma250/bst-bma250-ds002-05.pdf Required properties: - compatible : should be one of: + "bosch,bma023" + "bosch,bma150" "bosch,bma180" "bosch,bma250" "bosch,bma254" + "bosch,smb380" - reg : the I2C address of the sensor + - vdd-supply : regulator phandle connected to the VDD pin + - vddio-supply : regulator phandle connected to the VDDIO pin Optional properties: diff --git a/Bindings/iio/adc/adi,ad7124.yaml b/Bindings/iio/adc/adi,ad7124.yaml index f0934b295edc..deb34deff0e8 100644 --- a/Bindings/iio/adc/adi,ad7124.yaml +++ b/Bindings/iio/adc/adi,ad7124.yaml @@ -72,8 +72,8 @@ patternProperties: The channel number. It can have up to 8 channels on ad7124-4 and 16 channels on ad7124-8, numbered from 0 to 15. items: - minimum: 0 - maximum: 15 + minimum: 0 + maximum: 15 adi,reference-select: description: | @@ -83,9 +83,8 @@ patternProperties: 1: REFIN2(+)/REFIN2(−). 3: AVDD If this field is left empty, internal reference is selected. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [0, 1, 3] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 3] diff-channels: description: see Documentation/devicetree/bindings/iio/adc/adc.txt diff --git a/Bindings/iio/adc/adi,ad9467.yaml b/Bindings/iio/adc/adi,ad9467.yaml new file mode 100644 index 000000000000..c4f57fa6aad1 --- /dev/null +++ b/Bindings/iio/adc/adi,ad9467.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad9467.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD9467 High-Speed ADC + +maintainers: + - Michael Hennerich + - Alexandru Ardelean + +description: | + The AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital + converter (ADC). + + https://www.analog.com/media/en/technical-documentation/data-sheets/AD9467.pdf + +properties: + compatible: + enum: + - adi,ad9467 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: adc-clk + + powerdown-gpios: + description: + Pin that controls the powerdown mode of the device. + maxItems: 1 + + reset-gpios: + description: + Reset pin for the device. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad9467"; + reg = <0>; + clocks = <&adc_clk>; + clock-names = "adc-clk"; + }; + }; +... diff --git a/Bindings/iio/adc/adi,axi-adc.yaml b/Bindings/iio/adc/adi,axi-adc.yaml new file mode 100644 index 000000000000..0924b2b4972b --- /dev/null +++ b/Bindings/iio/adc/adi,axi-adc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AXI ADC IP core + +maintainers: + - Michael Hennerich + - Alexandru Ardelean + +description: | + Analog Devices Generic AXI ADC IP core for interfacing an ADC device + with a high speed serial (JESD204B/C) or source synchronous parallel + interface (LVDS/CMOS). + Usually, some other interface type (i.e SPI) is used as a control + interface for the actual ADC, while this IP core will interface + to the data-lines of the ADC and handle the streaming of data into + memory via DMA. + + https://wiki.analog.com/resources/fpga/docs/axi_adc_ip + +properties: + compatible: + enum: + - adi,axi-adc-10.0.a + + reg: + maxItems: 1 + + dmas: + maxItems: 1 + + dma-names: + items: + - const: rx + + adi,adc-dev: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A reference to a the actual ADC to which this FPGA ADC interfaces to. + +required: + - compatible + - dmas + - reg + - adi,adc-dev + +additionalProperties: false + +examples: + - | + axi-adc@44a00000 { + compatible = "adi,axi-adc-10.0.a"; + reg = <0x44a00000 0x10000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + + adi,adc-dev = <&spi_adc>; + }; +... diff --git a/Bindings/iio/adc/lltc,ltc2496.yaml b/Bindings/iio/adc/lltc,ltc2496.yaml index 118809a03279..6a991e9f78e2 100644 --- a/Bindings/iio/adc/lltc,ltc2496.yaml +++ b/Bindings/iio/adc/lltc,ltc2496.yaml @@ -7,9 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Linear Technology / Analog Devices LTC2496 ADC maintainers: - - Lars-Peter Clausen - - Michael Hennerich - - Stefan Popa + - Lars-Peter Clausen + - Michael Hennerich + - Stefan Popa properties: compatible: @@ -18,8 +18,7 @@ properties: vref-supply: description: phandle to an external regulator providing the reference voltage - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle reg: description: spi chipselect number according to the usual spi bindings diff --git a/Bindings/iio/adc/maxim,max1241.yaml b/Bindings/iio/adc/maxim,max1241.yaml new file mode 100644 index 000000000000..f562505f5ecd --- /dev/null +++ b/Bindings/iio/adc/maxim,max1241.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2020 Alexandru Lazar +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/maxim,max1241.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX1241 12-bit, single-channel analog to digital converter + +maintainers: + - Alexandru Lazar + +description: | + Bindings for the max1241 12-bit, single-channel ADC device. Datasheet + can be found at: + https://datasheets.maximintegrated.com/en/ds/MAX1240-MAX1241.pdf + +properties: + compatible: + enum: + - maxim,max1241 + + reg: + maxItems: 1 + + vdd-supply: + description: + Device tree identifier of the regulator that powers the ADC. + + vref-supply: + description: + Device tree identifier of the regulator that provides the external + reference voltage. + + shutdown-gpios: + description: + GPIO spec for the GPIO pin connected to the ADC's /SHDN pin. If + specified, the /SHDN pin will be asserted between conversions, + thus enabling power-down mode. + maxItems: 1 + +required: + - compatible + - reg + - vdd-supply + - vref-supply + +examples: + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "maxim,max1241"; + reg = <0>; + vdd-supply = <&adc_vdd>; + vref-supply = <&adc_vref>; + spi-max-frequency = <1000000>; + shutdown-gpios = <&gpio 26 1>; + }; + }; diff --git a/Bindings/iio/adc/microchip,mcp3911.yaml b/Bindings/iio/adc/microchip,mcp3911.yaml index 8ffeceb6abae..95ab285f4eba 100644 --- a/Bindings/iio/adc/microchip,mcp3911.yaml +++ b/Bindings/iio/adc/microchip,mcp3911.yaml @@ -38,10 +38,9 @@ properties: microchip,device-addr: description: Device address when multiple MCP3911 chips are present on the same SPI bus. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [0, 1, 2, 3] - - default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 vref-supply: description: | diff --git a/Bindings/iio/adc/rockchip-saradc.txt b/Bindings/iio/adc/rockchip-saradc.txt deleted file mode 100644 index c2c50b59873d..000000000000 --- a/Bindings/iio/adc/rockchip-saradc.txt +++ /dev/null @@ -1,37 +0,0 @@ -Rockchip Successive Approximation Register (SAR) A/D Converter bindings - -Required properties: -- compatible: should be "rockchip,-saradc" or "rockchip,rk3066-tsadc" - - "rockchip,saradc": for rk3188, rk3288 - - "rockchip,rk3066-tsadc": for rk3036 - - "rockchip,rk3328-saradc", "rockchip,rk3399-saradc": for rk3328 - - "rockchip,rk3399-saradc": for rk3399 - - "rockchip,rv1108-saradc", "rockchip,rk3399-saradc": for rv1108 - -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. -- clocks: Must contain an entry for each entry in clock-names. -- clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk" for - the peripheral clock. -- vref-supply: The regulator supply ADC reference voltage. -- #io-channel-cells: Should be 1, see ../iio-bindings.txt - -Optional properties: -- resets: Must contain an entry for each entry in reset-names if need support - this option. See ../reset/reset.txt for details. -- reset-names: Must include the name "saradc-apb". - -Example: - saradc: saradc@2006c000 { - compatible = "rockchip,saradc"; - reg = <0x2006c000 0x100>; - interrupts = ; - clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; - clock-names = "saradc", "apb_pclk"; - resets = <&cru SRST_SARADC>; - reset-names = "saradc-apb"; - #io-channel-cells = <1>; - vref-supply = <&vcc18>; - }; diff --git a/Bindings/iio/adc/rockchip-saradc.yaml b/Bindings/iio/adc/rockchip-saradc.yaml new file mode 100644 index 000000000000..bcff82a423bc --- /dev/null +++ b/Bindings/iio/adc/rockchip-saradc.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/rockchip-saradc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Successive Approximation Register (SAR) A/D Converter + +maintainers: + - Heiko Stuebner + +properties: + compatible: + oneOf: + - const: rockchip,saradc + - const: rockchip,rk3066-tsadc + - const: rockchip,rk3399-saradc + - items: + - enum: + - rockchip,px30-saradc + - rockchip,rk3308-saradc + - rockchip,rk3328-saradc + - rockchip,rv1108-saradc + - const: rockchip,rk3399-saradc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: converter clock + - description: peripheral clock + + clock-names: + items: + - const: saradc + - const: apb_pclk + + resets: + maxItems: 1 + + reset-names: + const: saradc-apb + + vref-supply: + description: + The regulator supply for the ADC reference voltage. + + "#io-channel-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - vref-supply + - "#io-channel-cells" + +additionalProperties: false + +examples: + - | + #include + #include + saradc: saradc@2006c000 { + compatible = "rockchip,saradc"; + reg = <0x2006c000 0x100>; + interrupts = ; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; + vref-supply = <&vcc18>; + #io-channel-cells = <1>; + }; diff --git a/Bindings/iio/adc/st,stm32-adc.yaml b/Bindings/iio/adc/st,stm32-adc.yaml index dd8eb15aeb63..28417b31b558 100644 --- a/Bindings/iio/adc/st,stm32-adc.yaml +++ b/Bindings/iio/adc/st,stm32-adc.yaml @@ -76,8 +76,7 @@ properties: description: Phandle to system configuration controller. It can be used to control the analog circuitry on stm32mp1. - allOf: - - $ref: "/schemas/types.yaml#/definitions/phandle-array" + $ref: "/schemas/types.yaml#/definitions/phandle-array" interrupt-controller: true @@ -247,8 +246,7 @@ patternProperties: Resolution (bits) to use for conversions: - can be 6, 8, 10 or 12 on stm32f4 - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1 - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 st,adc-channels: description: | @@ -256,8 +254,7 @@ patternProperties: - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4 - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and stm32mp1. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array st,adc-diff-channels: description: | @@ -270,18 +267,17 @@ patternProperties: required. Both properties can be used together. Some channels can be used as single-ended and some other ones as differential (mixed). But channels can't be configured both as single-ended and differential. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-matrix - - items: - items: - - description: | - "vinp" indicates positive input number - minimum: 0 - maximum: 19 - - description: | - "vinn" indicates negative input number - minimum: 0 - maximum: 19 + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "vinp" indicates positive input number + minimum: 0 + maximum: 19 + - description: | + "vinn" indicates negative input number + minimum: 0 + maximum: 19 st,min-sample-time-nsecs: description: @@ -291,8 +287,7 @@ patternProperties: array that matches "st,adc-channels" and/or "st,adc-diff-channels" list, to set sample time resp. for all channels, or independently for each channel. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array allOf: - if: diff --git a/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml index b1627441a0b2..d61bc011e820 100644 --- a/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -95,16 +95,14 @@ patternProperties: On stm32h7 and stm32mp1: - For st,stm32-dfsdm-adc: up to 8 channels numbered from 0 to 7. - For st,stm32-dfsdm-dmic: 1 channel numbered from 0 to 7. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - items: - minimum: 0 - maximum: 7 + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + minimum: 0 + maximum: 7 st,adc-channel-names: description: List of single-ended channel names. - allOf: - - $ref: /schemas/types.yaml#/definitions/string-array + $ref: /schemas/types.yaml#/definitions/string-array st,filter-order: description: | @@ -112,11 +110,10 @@ patternProperties: - 0: FastSinC - [1-5]: order 1 to 5. For audio purpose it is recommended to use order 3 to 5. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - items: - minimum: 0 - maximum: 5 + $ref: /schemas/types.yaml#/definitions/uint32 + items: + minimum: 0 + maximum: 5 "#io-channel-cells": const: 1 @@ -130,8 +127,7 @@ patternProperties: - "MANCH_F": manchester codec, rising edge = logic 1, falling edge = logic 0 items: enum: [ SPI_R, SPI_F, MANCH_R, MANCH_F ] - allOf: - - $ref: /schemas/types.yaml#/definitions/non-unique-string-array + $ref: /schemas/types.yaml#/definitions/non-unique-string-array st,adc-channel-clk-src: description: | @@ -142,8 +138,7 @@ patternProperties: - "CLKOUT_R": internal SPI clock divided by 2 (rising edge). items: enum: [ CLKIN, CLKOUT, CLKOUT_F, CLKOUT_R ] - allOf: - - $ref: /schemas/types.yaml#/definitions/non-unique-string-array + $ref: /schemas/types.yaml#/definitions/non-unique-string-array st,adc-alt-channel: description: diff --git a/Bindings/iio/chemical/ams,ccs811.yaml b/Bindings/iio/chemical/ams,ccs811.yaml new file mode 100644 index 000000000000..52341c8bacd9 --- /dev/null +++ b/Bindings/iio/chemical/ams,ccs811.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/chemical/ams,ccs811.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMS CCS811 VOC Sensor + +maintainers: + - Narcisa Vasile + +description: | + Ultra-Low Power Digital Gas Sensor for Monitoring Indoor Air Quality. + +properties: + compatible: + enum: + - ams,ccs811 + reg: + maxItems: 1 + + reset-gpios: + description: GPIO connected to the nRESET line. This is an active low + input to CCS811. + maxItems: 1 + + wakeup-gpios: + description: GPIO connected to the nWAKE line. This is an active low + input to CCS811. + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + voc@5b { + compatible = "ams,ccs811"; + reg = <0x5b>; + reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; + wakeup-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; + }; + }; + +... diff --git a/Bindings/iio/chemical/atlas,sensor.yaml b/Bindings/iio/chemical/atlas,sensor.yaml index edcd2904d50e..69e8931e0ae8 100644 --- a/Bindings/iio/chemical/atlas,sensor.yaml +++ b/Bindings/iio/chemical/atlas,sensor.yaml @@ -4,19 +4,21 @@ $id: http://devicetree.org/schemas/iio/chemical/atlas,sensor.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Atlas Scientific OEM sensors +title: Atlas Scientific OEM + EZO sensors maintainers: - Matt Ranostay description: | - Atlas Scientific OEM sensors connected via I2C + Atlas Scientific OEM + EZO sensors connected via I2C Datasheets: http://www.atlas-scientific.com/_files/_datasheets/_oem/DO_oem_datasheet.pdf http://www.atlas-scientific.com/_files/_datasheets/_oem/EC_oem_datasheet.pdf http://www.atlas-scientific.com/_files/_datasheets/_oem/ORP_oem_datasheet.pdf http://www.atlas-scientific.com/_files/_datasheets/_oem/pH_oem_datasheet.pdf + http://www.atlas-scientific.com/_files/_datasheets/_oem/RTD_oem_datasheet.pdf + http://www.atlas-scientific.com/_files/_datasheets/_probe/EZO_CO2_Datasheet.pdf properties: compatible: @@ -25,6 +27,8 @@ properties: - atlas,ec-sm - atlas,orp-sm - atlas,ph-sm + - atlas,rtd-sm + - atlas,co2-ezo reg: maxItems: 1 diff --git a/Bindings/iio/common.yaml b/Bindings/iio/common.yaml new file mode 100644 index 000000000000..97ffcb77043d --- /dev/null +++ b/Bindings/iio/common.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common properties for iio sensors + +maintainers: + - Jonathan Cameron + - Guido Günther + +description: | + This document defines device tree properties common to several iio + sensors. It doesn't constitue a device tree binding specification by itself but + is meant to be referenced by device tree bindings. + + When referenced from sensor tree bindings the properties defined in this + document are defined as follows. The sensor tree bindings are responsible for + defining whether each property is required or optional. + +properties: + proximity-near-level: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + For proximity sensors whether an object can be considered near to the + device depends on parameters like sensor position, covering glass and + aperture. This value gives an indication to userspace for which + sensor readings this is the case. + + Raw proximity values equal or above this level should be + considered 'near' to the device (an object is near to the + sensor). + +... diff --git a/Bindings/iio/dac/ltc2632.txt b/Bindings/iio/dac/ltc2632.txt index 338c3220f01a..1ab9570cf219 100644 --- a/Bindings/iio/dac/ltc2632.txt +++ b/Bindings/iio/dac/ltc2632.txt @@ -1,4 +1,4 @@ -Linear Technology LTC2632/2636 DAC +Linear Technology LTC2632/2634/2636 DAC Required properties: - compatible: Has to contain one of the following: @@ -8,6 +8,12 @@ Required properties: lltc,ltc2632-h12 lltc,ltc2632-h10 lltc,ltc2632-h8 + lltc,ltc2634-l12 + lltc,ltc2634-l10 + lltc,ltc2634-l8 + lltc,ltc2634-h12 + lltc,ltc2634-h10 + lltc,ltc2634-h8 lltc,ltc2636-l12 lltc,ltc2636-l10 lltc,ltc2636-l8 diff --git a/Bindings/iio/dac/st,stm32-dac.txt b/Bindings/iio/dac/st,stm32-dac.txt deleted file mode 100644 index bf2925c671c6..000000000000 --- a/Bindings/iio/dac/st,stm32-dac.txt +++ /dev/null @@ -1,63 +0,0 @@ -STMicroelectronics STM32 DAC - -The STM32 DAC is a 12-bit voltage output digital-to-analog converter. The DAC -may be configured in 8 or 12-bit mode. It has two output channels, each with -its own converter. -It has built-in noise and triangle waveform generator and supports external -triggers for conversions. The DAC's output buffer allows a high drive output -current. - -Contents of a stm32 dac root node: ------------------------------------ -Required properties: -- compatible: Should be one of: - "st,stm32f4-dac-core" - "st,stm32h7-dac-core" -- reg: Offset and length of the device's register set. -- clocks: Must contain an entry for pclk (which feeds the peripheral bus - interface) -- clock-names: Must be "pclk". -- vref-supply: Phandle to the vref+ input analog reference supply. -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties: -- resets: Must contain the phandle to the reset controller. -- A pinctrl state named "default" for each DAC channel may be defined to set - DAC_OUTx pin in mode of operation for analog output on external pin. - -Contents of a stm32 dac child node: ------------------------------------ -DAC core node should contain at least one subnode, representing a -DAC instance/channel available on the machine. - -Required properties: -- compatible: Must be "st,stm32-dac". -- reg: Must be either 1 or 2, to define (single) channel in use -- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in - Documentation/devicetree/bindings/iio/iio-bindings.txt - -Example: - dac: dac@40007400 { - compatible = "st,stm32h7-dac-core"; - reg = <0x40007400 0x400>; - clocks = <&clk>; - clock-names = "pclk"; - vref-supply = <®_vref>; - pinctrl-names = "default"; - pinctrl-0 = <&dac_out1 &dac_out2>; - #address-cells = <1>; - #size-cells = <0>; - - dac1: dac@1 { - compatible = "st,stm32-dac"; - #io-channels-cells = <1>; - reg = <1>; - }; - - dac2: dac@2 { - compatible = "st,stm32-dac"; - #io-channels-cells = <1>; - reg = <2>; - }; - }; diff --git a/Bindings/iio/dac/st,stm32-dac.yaml b/Bindings/iio/dac/st,stm32-dac.yaml new file mode 100644 index 000000000000..393f7005941a --- /dev/null +++ b/Bindings/iio/dac/st,stm32-dac.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/iio/dac/st,stm32-dac.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STMicroelectronics STM32 DAC bindings + +description: | + The STM32 DAC is a 12-bit voltage output digital-to-analog converter. The DAC + may be configured in 8 or 12-bit mode. It has two output channels, each with + its own converter. + It has built-in noise and triangle waveform generator and supports external + triggers for conversions. The DAC's output buffer allows a high drive output + current. + +maintainers: + - Fabrice Gasnier + +properties: + compatible: + enum: + - st,stm32f4-dac-core + - st,stm32h7-dac-core + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pclk + + vref-supply: + description: Phandle to the vref input analog reference voltage. + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - vref-supply + - '#address-cells' + - '#size-cells' + +patternProperties: + "^dac@[1-2]+$": + type: object + description: + A DAC block node should contain at least one subnode, representing an + DAC instance/channel available on the machine. + + properties: + compatible: + const: st,stm32-dac + + reg: + description: Must be either 1 or 2, to define (single) channel in use + enum: [1, 2] + + '#io-channel-cells': + const: 1 + + additionalProperties: false + + required: + - compatible + - reg + - '#io-channel-cells' + +examples: + - | + // Example on stm32mp157c + #include + dac: dac@40017000 { + compatible = "st,stm32h7-dac-core"; + reg = <0x40017000 0x400>; + clocks = <&rcc DAC12>; + clock-names = "pclk"; + vref-supply = <&vref>; + #address-cells = <1>; + #size-cells = <0>; + + dac@1 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <1>; + }; + + dac@2 { + compatible = "st,stm32-dac"; + #io-channel-cells = <1>; + reg = <2>; + }; + }; + +... diff --git a/Bindings/iio/gyroscope/bmg160.txt b/Bindings/iio/gyroscope/bmg160.txt index 78e18a1e9c1d..bb43d1ad9c9f 100644 --- a/Bindings/iio/gyroscope/bmg160.txt +++ b/Bindings/iio/gyroscope/bmg160.txt @@ -2,7 +2,7 @@ Required properties: - - compatible : should be "bosch,bmg160" or "bosch,bmi055_gyro" + - compatible : should be "bosch,bmg160", "bosch,bmi055_gyro" or "bosch,bmi088_gyro" - reg : the I2C address of the sensor (0x69) Optional properties: diff --git a/Bindings/iio/imu/adi,adis16475.yaml b/Bindings/iio/imu/adi,adis16475.yaml new file mode 100644 index 000000000000..208faaffa58d --- /dev/null +++ b/Bindings/iio/imu/adi,adis16475.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/imu/adi,adis16475.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADIS16475 and similar IMUs + +maintainers: + - Nuno Sá + +description: | + Analog Devices ADIS16475 and similar IMUs + https://www.analog.com/media/en/technical-documentation/data-sheets/ADIS16475.pdf + +properties: + compatible: + enum: + - adi,adis16475-1 + - adi,adis16475-2 + - adi,adis16475-3 + - adi,adis16477-1 + - adi,adis16477-2 + - adi,adis16477-3 + - adi,adis16470 + - adi,adis16465-1 + - adi,adis16465-2 + - adi,adis16465-3 + - adi,adis16467-1 + - adi,adis16467-2 + - adi,adis16467-3 + - adi,adis16500 + - adi,adis16505-1 + - adi,adis16505-2 + - adi,adis16505-3 + - adi,adis16507-1 + - adi,adis16507-2 + - adi,adis16507-3 + + reg: + maxItems: 1 + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 2000000 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + reset-gpios: + description: + Must be the device tree identifier of the RESET pin. If specified, + it will be asserted during driver probe. As the line is active low, + it should be marked GPIO_ACTIVE_LOW. + maxItems: 1 + + adi,sync-mode: + description: + Configures the device SYNC pin. The following modes are supported + 0 - output_sync + 1 - direct_sync + 2 - scaled_sync + 3 - pulse_sync + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + + adi,scaled-output-hz: + description: + This property must be present if the clock mode is scaled-sync through + clock-names property. In this mode, the input clock can have a range + of 1Hz to 128HZ which must be scaled to originate an allowable sample + rate. This property specifies that rate. + minimum: 1900 + maximum: 2100 + +required: + - compatible + - reg + - interrupts + - spi-cpha + - spi-cpol + +allOf: + - if: + properties: + compatible: + contains: + enum: + - adi,adis16500 + - adi,adis16505-1 + - adi,adis16505-2 + - adi,adis16505-3 + - adi,adis16507-1 + - adi,adis16507-2 + - adi,adis16507-3 + + then: + properties: + adi,sync-mode: + minimum: 0 + maximum: 2 + + - if: + properties: + adi,sync-mode: + enum: [1, 2, 3] + + then: + dependencies: + adi,sync-mode: [ clocks ] + +examples: + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + adis16475: adis16475-3@0 { + compatible = "adi,adis16475-3"; + reg = <0>; + spi-cpha; + spi-cpol; + spi-max-frequency = <2000000>; + interrupts = <4 IRQ_TYPE_EDGE_RISING>; + interrupt-parent = <&gpio>; + }; + }; +... diff --git a/Bindings/iio/imu/bmi160.txt b/Bindings/iio/imu/bmi160.txt deleted file mode 100644 index 900c169de00f..000000000000 --- a/Bindings/iio/imu/bmi160.txt +++ /dev/null @@ -1,37 +0,0 @@ -Bosch BMI160 - Inertial Measurement Unit with Accelerometer, Gyroscope -and externally connectable Magnetometer - -https://www.bosch-sensortec.com/bst/products/all_products/bmi160 - -Required properties: - - compatible : should be "bosch,bmi160" - - reg : the I2C address or SPI chip select number of the sensor - - spi-max-frequency : set maximum clock frequency (only for SPI) - -Optional properties: - - interrupts : interrupt mapping for IRQ - - interrupt-names : set to "INT1" if INT1 pin should be used as interrupt - input, set to "INT2" if INT2 pin should be used instead - - drive-open-drain : set if the specified interrupt pin should be configured as - open drain. If not set, defaults to push-pull. - -Examples: - -bmi160@68 { - compatible = "bosch,bmi160"; - reg = <0x68>; - - interrupt-parent = <&gpio4>; - interrupts = <12 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "INT1"; -}; - -bmi160@0 { - compatible = "bosch,bmi160"; - reg = <0>; - spi-max-frequency = <10000000>; - - interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT2"; -}; diff --git a/Bindings/iio/imu/bosch,bmi160.yaml b/Bindings/iio/imu/bosch,bmi160.yaml new file mode 100644 index 000000000000..0d0ef84e22b9 --- /dev/null +++ b/Bindings/iio/imu/bosch,bmi160.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/imu/bosch,bmi160.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bosch BMI160 + +maintainers: + - Jonathan Cameron + +description: | + Inertial Measurement Unit with Accelerometer, Gyroscope and externally + connectable Magnetometer + https://www.bosch-sensortec.com/bst/products/all_products/bmi160 + +properties: + compatible: + const: bosch,bmi160 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + enum: + - INT1 + - INT2 + description: | + set to "INT1" if INT1 pin should be used as interrupt input, set + to "INT2" if INT2 pin should be used instead + + drive-open-drain: + description: | + set if the specified interrupt pin should be configured as + open drain. If not set, defaults to push-pull. + +required: + - compatible + - reg + +examples: + - | + // Example for I2C + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bmi160@68 { + compatible = "bosch,bmi160"; + reg = <0x68>; + interrupt-parent = <&gpio4>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT1"; + }; + }; + - | + // Example for SPI + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + bmi160@0 { + compatible = "bosch,bmi160"; + reg = <0>; + spi-max-frequency = <10000000>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "INT2"; + }; + }; diff --git a/Bindings/iio/light/amstaos,tsl2563.yaml b/Bindings/iio/light/amstaos,tsl2563.yaml new file mode 100644 index 000000000000..e201a06d8fdc --- /dev/null +++ b/Bindings/iio/light/amstaos,tsl2563.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/light/amstaos,tsl2563.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMS TAOS TSL2563 ambient light sensor + +maintainers: + - Sebastian Reichel + +description: | + Ambient light sensor with an i2c interface. + +properties: + compatible: + enum: + - amstaos,tsl2560 + - amstaos,tsl2561 + - amstaos,tsl2562 + - amstaos,tsl2563 + + reg: + maxItems: 1 + + amstaos,cover-comp-gain: + description: Multiplier for gain compensation + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 16] + +required: + - compatible + - reg + +examples: + - | + i2c { + + #address-cells = <1>; + #size-cells = <0>; + + light-sensor@29 { + compatible = "amstaos,tsl2563"; + reg = <0x29>; + amstaos,cover-comp-gain = <16>; + }; + }; +... diff --git a/Bindings/iio/light/tsl2563.txt b/Bindings/iio/light/tsl2563.txt deleted file mode 100644 index f91e809e736e..000000000000 --- a/Bindings/iio/light/tsl2563.txt +++ /dev/null @@ -1,19 +0,0 @@ -* AMS TAOS TSL2563 ambient light sensor - -Required properties: - - - compatible : should be "amstaos,tsl2563" - - reg : the I2C address of the sensor - -Optional properties: - - - amstaos,cover-comp-gain : integer used as multiplier for gain - compensation (default = 1) - -Example: - -tsl2563@29 { - compatible = "amstaos,tsl2563"; - reg = <0x29>; - amstaos,cover-comp-gain = <16>; -}; diff --git a/Bindings/iio/light/tsl2772.yaml b/Bindings/iio/light/tsl2772.yaml index e8f7d1ada57b..d81229857944 100644 --- a/Bindings/iio/light/tsl2772.yaml +++ b/Bindings/iio/light/tsl2772.yaml @@ -33,13 +33,12 @@ properties: amstaos,proximity-diodes: description: Proximity diodes to enable - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 1 - maxItems: 2 - items: - minimum: 0 - maximum: 1 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 1 interrupts: maxItems: 1 diff --git a/Bindings/iio/light/vcnl4000.txt b/Bindings/iio/light/vcnl4000.txt deleted file mode 100644 index 955af4555c90..000000000000 --- a/Bindings/iio/light/vcnl4000.txt +++ /dev/null @@ -1,24 +0,0 @@ -VISHAY VCNL4000 - Ambient Light and proximity sensor - -This driver supports the VCNL4000/10/20/40 and VCNL4200 chips - -Required properties: - - -compatible: must be one of : - vishay,vcnl4000 - vishay,vcnl4010 - vishay,vcnl4020 - vishay,vcnl4040 - vishay,vcnl4200 - - -reg: I2C address of the sensor, should be one from below based on the model: - 0x13 - 0x51 - 0x60 - -Example: - -light-sensor@51 { - compatible = "vishay,vcnl4200"; - reg = <0x51>; -}; diff --git a/Bindings/iio/light/vishay,vcnl4000.yaml b/Bindings/iio/light/vishay,vcnl4000.yaml new file mode 100644 index 000000000000..da8f2e872535 --- /dev/null +++ b/Bindings/iio/light/vishay,vcnl4000.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/light/vishay,vcnl4000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: VISHAY VCNL4000 ambient light and proximity sensor + +maintainers: + - Peter Meerwald + +description: | + Ambient light sensing with proximity detection over an i2c + interface. + +allOf: + - $ref: ../common.yaml# + +properties: + compatible: + enum: + - vishay,vcnl4000 + - vishay,vcnl4010 + - vishay,vcnl4020 + - vishay,vcnl4040 + - vishay,vcnl4200 + reg: + maxItems: 1 + + proximity-near-level: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: +- | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + light-sensor@51 { + compatible = "vishay,vcnl4200"; + reg = <0x51>; + proximity-near-level = <220>; + }; + }; +... diff --git a/Bindings/iio/magnetometer/ak8974.txt b/Bindings/iio/magnetometer/ak8974.txt index baecc4a85197..7f06eff3b504 100644 --- a/Bindings/iio/magnetometer/ak8974.txt +++ b/Bindings/iio/magnetometer/ak8974.txt @@ -2,7 +2,9 @@ Required properties: -- compatible : should be "asahi-kasei,ak8974" +- compatible: + * "asahi-kasei,ak8974" + * "alps,hscdtd008a" - reg : the I2C address of the magnetometer Optional properties: diff --git a/Bindings/iio/proximity/vishay,vcnl3020.yaml b/Bindings/iio/proximity/vishay,vcnl3020.yaml new file mode 100644 index 000000000000..4190253336ec --- /dev/null +++ b/Bindings/iio/proximity/vishay,vcnl3020.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/proximity/vishay,vcnl3020.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Integrated Proximity Sensor With Infrared Emitter + +maintainers: + - Ivan Mikhaylov + +description: | + The VCNL3020 is a fully integrated proximity sensor. Fully integrated means + that the infrared emitter is included in the package. It has 16-bit + resolution. It includes a signal processing IC and features standard I2C + communication interface. It features an interrupt function. + + Specifications about the devices can be found at: + https://www.vishay.com/docs/84150/vcnl3020.pdf + +properties: + compatible: + enum: + - vishay,vcnl3020 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: + description: Regulator that provides power to the sensor + + vddio-supply: + description: Regulator that provides power to the bus + + vishay,led-current-microamp: + description: + The driver current for the LED used in proximity sensing. + enum: [0, 10000, 20000, 30000, 40000, 50000, 60000, 70000, 80000, 90000, + 100000, 110000, 120000, 130000, 140000, 150000, 160000, 170000, + 180000, 190000, 200000] + default: 20000 + +required: + - compatible + - reg + +examples: + - | + i2c { + + #address-cells = <1>; + #size-cells = <0>; + + proximity@13 { + compatible = "vishay,vcnl3020"; + reg = <0x13>; + vishay,led-current-microamp = <200000>; + }; + }; diff --git a/Bindings/iio/st-sensors.txt b/Bindings/iio/st-sensors.txt index 0ef64a444479..3213599c5071 100644 --- a/Bindings/iio/st-sensors.txt +++ b/Bindings/iio/st-sensors.txt @@ -50,6 +50,7 @@ Accelerometers: - st,lis3dhh - st,lis3de - st,lis2de12 +- st,lis2hh12 Gyroscopes: - st,l3g4200d-gyro diff --git a/Bindings/iio/temperature/adi,ltc2983.yaml b/Bindings/iio/temperature/adi,ltc2983.yaml index 8fb46de6641d..40ccbe7b5c13 100644 --- a/Bindings/iio/temperature/adi,ltc2983.yaml +++ b/Bindings/iio/temperature/adi,ltc2983.yaml @@ -42,10 +42,9 @@ properties: 0 - 50/60Hz rejection 1 - 60Hz rejection 2 - 50Hz rejection - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - maximum: 2 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 2 '#address-cells': const: 1 @@ -91,8 +90,7 @@ patternProperties: 7 - Type T Thermocouple 8 - Type B Thermocouple 9 - Custom Thermocouple - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 9 @@ -121,8 +119,7 @@ patternProperties: more details look at table 69 and 70. Note should be signed, but dtc doesn't currently maintain the sign. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint64-matrix + $ref: /schemas/types.yaml#/definitions/uint64-matrix minItems: 3 maxItems: 64 items: @@ -138,8 +135,7 @@ patternProperties: properties: adi,sensor-type: description: Identifies the sensor as a diode. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 const: 28 adi,single-ended: @@ -196,8 +192,7 @@ patternProperties: 16 - RTD PT-1000 (0.00375) 17 - RTD NI-120 18 - RTD Custom - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 10 maximum: 18 @@ -210,9 +205,8 @@ patternProperties: description: Identifies the number of wires used by the RTD. Setting this property to 5 means 4 wires with Kelvin Rsense. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [2, 3, 4, 5] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 3, 4, 5] adi,rsense-share: description: @@ -237,18 +231,16 @@ patternProperties: description: This property set the RTD curve used and the corresponding Callendar-VanDusen constants. Look at table 30 of the datasheet. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - maximum: 3 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 adi,custom-rtd: description: This is a table, where each entry should be a pair of resistance(ohm)-temperature(K). The entries added here are in uohm and uK. For more details values look at table 74 and 75. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint64-matrix + $ref: /schemas/types.yaml#/definitions/uint64-matrix items: minItems: 3 maxItems: 64 @@ -260,7 +252,7 @@ patternProperties: - adi,rsense-handle dependencies: - adi,current-rotate: [ adi,rsense-share ] + adi,current-rotate: [ "adi,rsense-share" ] "^thermistor@": type: object @@ -280,8 +272,7 @@ patternProperties: 25 - Thermistor Spectrum 1003k 1kohm 26 - Thermistor Custom Steinhart-Hart 27 - Custom Thermistor - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 19 maximum: 27 @@ -314,10 +305,9 @@ patternProperties: This property controls the magnitude of the excitation current applied to the thermistor. Value 0 set's the sensor in auto-range mode. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [0, 250, 500, 1000, 5000, 10000, 25000, 50000, 100000, - 250000, 500000, 1000000] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 250, 500, 1000, 5000, 10000, 25000, 50000, 100000, 250000, + 500000, 1000000] adi,custom-thermistor: description: @@ -325,8 +315,7 @@ patternProperties: resistance(ohm)-temperature(K). The entries added here are in uohm and uK only for custom thermistors. For more details look at table 78 and 79. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint64-matrix + $ref: /schemas/types.yaml#/definitions/uint64-matrix minItems: 3 maxItems: 64 items: @@ -339,8 +328,7 @@ patternProperties: be programmed into the device memory using this property. For Steinhart sensors the coefficients are given in the raw format. Look at table 82 for more information. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array items: minItems: 6 maxItems: 6 @@ -349,7 +337,7 @@ patternProperties: - adi,rsense-handle dependencies: - adi,current-rotate: [ adi,rsense-share ] + adi,current-rotate: [ "adi,rsense-share" ] "^adc@": type: object @@ -358,8 +346,7 @@ patternProperties: properties: adi,sensor-type: description: Identifies the sensor as a direct adc. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 const: 30 adi,single-ended: @@ -379,8 +366,7 @@ patternProperties: adi,sensor-type: description: Identifies the sensor as a rsense. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 const: 29 adi,rsense-val-milli-ohms: diff --git a/Bindings/index.rst b/Bindings/index.rst new file mode 100644 index 000000000000..3837b17c234f --- /dev/null +++ b/Bindings/index.rst @@ -0,0 +1,12 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=========== +Device Tree +=========== + +.. toctree:: + :maxdepth: 1 + + ABI + submitting-patches + writing-bindings diff --git a/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml index 5b3b71c9c018..cffd02028d02 100644 --- a/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml +++ b/Bindings/input/allwinner,sun4i-a10-lradc-keys.yaml @@ -16,8 +16,8 @@ properties: - const: allwinner,sun4i-a10-lradc-keys - const: allwinner,sun8i-a83t-r-lradc - items: - - const: allwinner,sun50i-a64-lradc - - const: allwinner,sun8i-a83t-r-lradc + - const: allwinner,sun50i-a64-lradc + - const: allwinner,sun8i-a83t-r-lradc reg: maxItems: 1 @@ -42,9 +42,8 @@ patternProperties: description: Keycode to emit channel: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [0, 1] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] description: ADC Channel this key is attached to voltage: diff --git a/Bindings/input/elants_i2c.txt b/Bindings/input/elants_i2c.txt deleted file mode 100644 index 5edac8be0802..000000000000 --- a/Bindings/input/elants_i2c.txt +++ /dev/null @@ -1,34 +0,0 @@ -Elantech I2C Touchscreen - -Required properties: -- compatible: must be "elan,ekth3500". -- reg: I2C address of the chip. -- interrupts: interrupt to which the chip is connected (see interrupt - binding[0]). - -Optional properties: -- wakeup-source: touchscreen can be used as a wakeup source. -- pinctrl-names: should be "default" (see pinctrl binding [1]). -- pinctrl-0: a phandle pointing to the pin settings for the device (see - pinctrl binding [1]). -- reset-gpios: reset gpio the chip is connected to. -- vcc33-supply: a phandle for the regulator supplying 3.3V power. -- vccio-supply: a phandle for the regulator supplying IO power. - -[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt -[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example: - &i2c1 { - /* ... */ - - touchscreen@10 { - compatible = "elan,ekth3500"; - reg = <0x10>; - interrupt-parent = <&gpio4>; - interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - /* ... */ - }; diff --git a/Bindings/input/gpio-keys-polled.txt b/Bindings/input/gpio-keys-polled.txt deleted file mode 100644 index 4d9a3717eaaf..000000000000 --- a/Bindings/input/gpio-keys-polled.txt +++ /dev/null @@ -1,45 +0,0 @@ -Device-Tree bindings for input/gpio_keys_polled.c keyboard driver - -Required properties: - - compatible = "gpio-keys-polled"; - - poll-interval: Poll interval time in milliseconds - -Optional properties: - - autorepeat: Boolean, Enable auto repeat feature of Linux input - subsystem. - -Each button (key) is represented as a sub-node of "gpio-keys-polled": -Subnode properties: - - - gpios: OF device-tree gpio specification. - - label: Descriptive name of the key. - - linux,code: Key / Axis code to emit. - -Optional subnode-properties: - - linux,input-type: Specify event type this button/key generates. - If not specified defaults to <1> == EV_KEY. - - linux,input-value: If linux,input-type is EV_ABS or EV_REL then this - value is sent for events this button generates when pressed. - EV_ABS/EV_REL axis will generate an event with a value of 0 when - all buttons with linux,input-type == type and linux,code == axis - are released. This value is interpreted as a signed 32 bit value, - e.g. to make a button generate a value of -1 use: - linux,input-value = <0xffffffff>; /* -1 */ - - debounce-interval: Debouncing interval time in milliseconds. - If not specified defaults to 5. - - wakeup-source: Boolean, button can wake-up the system. - (Legacy property supported: "gpio-key,wakeup") - -Example nodes: - - gpio_keys_polled { - compatible = "gpio-keys-polled"; - poll-interval = <100>; - autorepeat; - - button21 { - label = "GPIO Key UP"; - linux,code = <103>; - gpios = <&gpio1 0 1>; - }; - ... diff --git a/Bindings/input/gpio-keys.txt b/Bindings/input/gpio-keys.txt deleted file mode 100644 index 7cccc49b6bea..000000000000 --- a/Bindings/input/gpio-keys.txt +++ /dev/null @@ -1,58 +0,0 @@ -Device-Tree bindings for input/keyboard/gpio_keys.c keyboard driver - -Required properties: - - compatible = "gpio-keys"; - -Optional properties: - - autorepeat: Boolean, Enable auto repeat feature of Linux input - subsystem. - - label: String, name of the input device. - -Each button (key) is represented as a sub-node of "gpio-keys": -Subnode properties: - - - gpios: OF device-tree gpio specification. - - interrupts: the interrupt line for that input. - - label: Descriptive name of the key. - - linux,code: Keycode to emit. - -Note that either "interrupts" or "gpios" properties can be omitted, but not -both at the same time. Specifying both properties is allowed. - -Optional subnode-properties: - - linux,input-type: Specify event type this button/key generates. - If not specified defaults to <1> == EV_KEY. - - debounce-interval: Debouncing interval time in milliseconds. - If not specified defaults to 5. - - wakeup-source: Boolean, button can wake-up the system. - (Legacy property supported: "gpio-key,wakeup") - - wakeup-event-action: Specifies whether the key should wake the - system when asserted, when deasserted, or both. This property is - only valid for keys that wake up the system (e.g., when the - "wakeup-source" property is also provided). - Supported values are defined in linux-event-codes.h: - EV_ACT_ASSERTED - asserted - EV_ACT_DEASSERTED - deasserted - EV_ACT_ANY - both asserted and deasserted - - linux,can-disable: Boolean, indicates that button is connected - to dedicated (not shared) interrupt which can be disabled to - suppress events from the button. - -Example nodes: - - gpio-keys { - compatible = "gpio-keys"; - autorepeat; - - up { - label = "GPIO Key UP"; - linux,code = <103>; - gpios = <&gpio1 0 1>; - }; - - down { - label = "GPIO Key DOWN"; - linux,code = <108>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - }; - ... diff --git a/Bindings/input/gpio-keys.yaml b/Bindings/input/gpio-keys.yaml new file mode 100644 index 000000000000..6966ab009fa3 --- /dev/null +++ b/Bindings/input/gpio-keys.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/gpio-keys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device-Tree bindings for GPIO attached keys + +maintainers: + - Rob Herring + +properties: + compatible: + enum: + - gpio-keys + - gpio-keys-polled + +patternProperties: + ".*": + if: + type: object + then: + $ref: input.yaml# + + properties: + gpios: + maxItems: 1 + + interrupts: + maxItems: 1 + + label: + description: Descriptive name of the key. + + linux,code: + description: Key / Axis code to emit. + $ref: /schemas/types.yaml#definitions/uint32 + + linux,input-type: + description: + Specify event type this button/key generates. If not specified defaults to + <1> == EV_KEY. + $ref: /schemas/types.yaml#definitions/uint32 + + default: 1 + + linux,input-value: + description: | + If linux,input-type is EV_ABS or EV_REL then this + value is sent for events this button generates when pressed. + EV_ABS/EV_REL axis will generate an event with a value of 0 + when all buttons with linux,input-type == type and + linux,code == axis are released. This value is interpreted + as a signed 32 bit value, e.g. to make a button generate a + value of -1 use: + + linux,input-value = <0xffffffff>; /* -1 */ + + $ref: /schemas/types.yaml#definitions/uint32 + + debounce-interval: + description: + Debouncing interval time in milliseconds. If not specified defaults to 5. + $ref: /schemas/types.yaml#definitions/uint32 + + default: 5 + + wakeup-source: + description: Button can wake-up the system. + + wakeup-event-action: + description: | + Specifies whether the key should wake the system when asserted, when + deasserted, or both. This property is only valid for keys that wake up the + system (e.g., when the "wakeup-source" property is also provided). + + Supported values are defined in linux-event-codes.h: + + EV_ACT_ANY - both asserted and deasserted + EV_ACT_ASSERTED - asserted + EV_ACT_DEASSERTED - deasserted + $ref: /schemas/types.yaml#definitions/uint32 + enum: [0, 1, 2] + + linux,can-disable: + description: + Indicates that button is connected to dedicated (not shared) interrupt + which can be disabled to suppress events from the button. + type: boolean + + pinctrl-0: + maxItems: 1 + + pinctrl-names: + maxItems: 1 + + required: + - linux,code + + anyOf: + - required: + - interrupts + - required: + - gpios + + dependencies: + wakeup-event-action: [ wakeup-source ] + linux,input-value: [ gpios ] + + unevaluatedProperties: false + +if: + properties: + compatible: + const: gpio-keys-polled +then: + properties: + poll-interval: + description: + Poll interval time in milliseconds + $ref: /schemas/types.yaml#definitions/uint32 + + required: + - poll-interval + +additionalProperties: false + +examples: + - | + #include + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + up { + label = "GPIO Key UP"; + linux,code = <103>; + gpios = <&gpio1 0 1>; + }; + + down { + label = "GPIO Key DOWN"; + linux,code = <108>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + }; + }; + +... diff --git a/Bindings/input/input.yaml b/Bindings/input/input.yaml index 6d519046b3af..8edcb3c31270 100644 --- a/Bindings/input/input.yaml +++ b/Bindings/input/input.yaml @@ -18,11 +18,10 @@ properties: description: Specifies an array of numeric keycode values to be used for reporting button presses. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - items: - minimum: 0 - maximum: 0xff + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + minimum: 0 + maximum: 0xff poll-interval: description: Poll interval time in milliseconds. diff --git a/Bindings/input/iqs269a.yaml b/Bindings/input/iqs269a.yaml new file mode 100644 index 000000000000..9c154e5e1a91 --- /dev/null +++ b/Bindings/input/iqs269a.yaml @@ -0,0 +1,555 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/iqs269a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Azoteq IQS269A Capacitive Touch Controller + +maintainers: + - Jeff LaBundy + +description: | + The Azoteq IQS269A is an 8-channel capacitive touch controller that features + additional Hall-effect and inductive sensing capabilities. + + Link to datasheet: https://www.azoteq.com/ + +properties: + compatible: + const: azoteq,iqs269a + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + azoteq,hall-enable: + type: boolean + description: + Enables Hall-effect sensing on channels 6 and 7. In this case, keycodes + assigned to channel 6 are ignored and keycodes assigned to channel 7 are + interpreted as switch codes. Refer to the datasheet for requirements im- + posed on channels 6 and 7 by Hall-effect sensing. + + azoteq,suspend-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + description: | + Specifies the power mode during suspend as follows: + 0: Automatic (same as normal runtime, i.e. suspend/resume disabled) + 1: Low power (all sensing at a reduced reporting rate) + 2: Ultra-low power (channel 0 proximity sensing) + 3: Halt (no sensing) + + azoteq,clk-div: + type: boolean + description: Divides the device's core clock by a factor of 4. + + azoteq,ulp-update: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + default: 3 + description: Specifies the ultra-low-power mode update rate. + + azoteq,reseed-offset: + type: boolean + description: + Applies an 8-count offset to all long-term averages upon either ATI or + reseed events. + + azoteq,filt-str-lp-lta: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + description: + Specifies the long-term average filter strength during low-power mode. + + azoteq,filt-str-lp-cnt: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + description: + Specifies the raw count filter strength during low-power mode. + + azoteq,filt-str-np-lta: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + description: + Specifies the long-term average filter strength during normal-power mode. + + azoteq,filt-str-np-cnt: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + description: + Specifies the raw count filter strength during normal-power mode. + + azoteq,rate-np-ms: + minimum: 0 + maximum: 255 + default: 16 + description: Specifies the report rate (in ms) during normal-power mode. + + azoteq,rate-lp-ms: + minimum: 0 + maximum: 255 + default: 160 + description: Specifies the report rate (in ms) during low-power mode. + + azoteq,rate-ulp-ms: + multipleOf: 16 + minimum: 0 + maximum: 4080 + default: 160 + description: Specifies the report rate (in ms) during ultra-low-power mode. + + azoteq,timeout-pwr-ms: + multipleOf: 512 + minimum: 0 + maximum: 130560 + default: 2560 + description: + Specifies the length of time (in ms) to wait for an event during normal- + power mode before transitioning to low-power mode. + + azoteq,timeout-lta-ms: + multipleOf: 512 + minimum: 0 + maximum: 130560 + default: 32768 + description: + Specifies the length of time (in ms) to wait before resetting the long- + term average of all channels. Specify the maximum timeout to disable it + altogether. + + azoteq,ati-band-disable: + type: boolean + description: Disables the ATI band check. + + azoteq,ati-lp-only: + type: boolean + description: Limits automatic ATI to low-power mode. + + azoteq,ati-band-tighten: + type: boolean + description: Tightens the ATI band from 1/8 to 1/16 of the desired target. + + azoteq,filt-disable: + type: boolean + description: Disables all raw count filtering. + + azoteq,gpio3-select: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + default: 0 + description: + Selects the channel for which the GPIO3 pin represents touch state. + + azoteq,dual-direction: + type: boolean + description: + Specifies that long-term averages are to freeze in the presence of either + increasing or decreasing counts, thereby permitting events to be reported + in either direction. + + azoteq,tx-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + description: | + Specifies the inductive sensing excitation frequency as follows (paren- + thesized numbers represent the frequency if 'azoteq,clk-div' is present): + 0: 16 MHz (4 MHz) + 1: 8 MHz (2 MHz) + 2: 4 MHz (1 MHz) + 3: 2 MHz (500 kHz) + + azoteq,global-cap-increase: + type: boolean + description: Increases the global capacitance adder from 0.5 pF to 1.5 pF. + + azoteq,reseed-select: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + description: | + Specifies the event(s) that prompt the device to reseed (i.e. reset the + long-term average) of an associated channel as follows: + 0: None + 1: Proximity + 2: Proximity or touch + 3: Proximity, touch or deep touch + + azoteq,tracking-enable: + type: boolean + description: + Enables all associated channels to track their respective reference + channels. + + azoteq,filt-str-slider: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 1 + description: Specifies the slider coordinate filter strength. + +patternProperties: + "^channel@[0-7]$": + type: object + description: + Represents a single sensing channel. A channel is active if defined and + inactive otherwise. + + properties: + reg: + minimum: 0 + maximum: 7 + description: Index of the channel. + + azoteq,reseed-disable: + type: boolean + description: + Prevents the channel from being reseeded if the long-term average + timeout (defined in 'azoteq,timeout-lta') expires. + + azoteq,blocking-enable: + type: boolean + description: Specifies that the channel is a blocking channel. + + azoteq,slider0-select: + type: boolean + description: Specifies that the channel participates in slider 0. + + azoteq,slider1-select: + type: boolean + description: Specifies that the channel participates in slider 1. + + azoteq,rx-enable: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + items: + minimum: 0 + maximum: 7 + description: + Specifies the CRX pin(s) associated with the channel. By default, only + the CRX pin corresponding to the channel's index is enabled (e.g. CRX0 + for channel 0). + + azoteq,tx-enable: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + items: + minimum: 0 + maximum: 7 + default: [0, 1, 2, 3, 4, 5, 6, 7] + description: Specifies the TX pin(s) associated with the channel. + + azoteq,meas-cap-decrease: + type: boolean + description: + Decreases the internal measurement capacitance from 60 pF to 15 pF. + + azoteq,rx-float-inactive: + type: boolean + description: Floats any inactive CRX pins instead of grounding them. + + azoteq,local-cap-size: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + default: 0 + description: | + Specifies the capacitance to be added to the channel as follows: + 0: None + 1: Global adder (based on 'azoteq,global-cap-increase') + 2: Global adder + 0.5 pF + + azoteq,invert-enable: + type: boolean + description: + Inverts the polarity of the states reported for proximity, touch and + deep-touch events relative to their respective thresholds. + + azoteq,proj-bias: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 2 + description: | + Specifies the bias current applied during projected-capacitance + sensing as follows: + 0: 2.5 uA + 1: 5 uA + 2: 10 uA + 3: 20 uA + + azoteq,sense-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 9, 14, 15] + default: 0 + description: | + Specifies the channel's sensing mode as follows: + 0: Self capacitance + 1: Projected capacitance + 9: Self or mutual inductance + 14: Hall effect + 15: Temperature + + azoteq,sense-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 1 + description: | + Specifies the channel's sensing frequency as follows (parenthesized + numbers represent the frequency if 'azoteq,clk-div' is present): + 0: 4 MHz (1 MHz) + 1: 2 MHz (500 kHz) + 2: 1 MHz (250 kHz) + 3: 500 kHz (125 kHz) + + azoteq,static-enable: + type: boolean + description: Enables the static front-end for the channel. + + azoteq,ati-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 3 + description: | + Specifies the channel's ATI mode as follows: + 0: Disabled + 1: Semi-partial + 2: Partial + 3: Full + + azoteq,ati-base: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [75, 100, 150, 200] + default: 100 + description: Specifies the channel's ATI base. + + azoteq,ati-target: + $ref: /schemas/types.yaml#/definitions/uint32 + multipleOf: 32 + minimum: 0 + maximum: 2016 + default: 512 + description: Specifies the channel's ATI target. + + azoteq,assoc-select: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + items: + minimum: 0 + maximum: 7 + description: + Specifies the associated channels for which the channel serves as a + reference channel. By default, no channels are selected. + + azoteq,assoc-weight: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + default: 0 + description: + Specifies the channel's impact weight if it acts as an associated + channel (0 = 0% impact, 255 = 200% impact). + + patternProperties: + "^event-prox(-alt)?$": + type: object + description: + Represents a proximity event reported by the channel in response to + a decrease in counts. Node names suffixed with '-alt' instead corre- + spond to an increase in counts. + + By default, the long-term average tracks an increase in counts such + that only events corresponding to a decrease in counts are reported + (refer to the datasheet for more information). + + Specify 'azoteq,dual-direction' to freeze the long-term average when + the counts increase or decrease such that events of either direction + can be reported. Alternatively, specify 'azoteq,invert-enable' to in- + vert the polarity of the states reported by the channel. + + Complementary events (e.g. event-touch and event-touch-alt) can both + be present and specify different key or switch codes, but not differ- + ent thresholds or hysteresis (if applicable). + + properties: + azoteq,thresh: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + default: 10 + description: Specifies the threshold for the event. + + linux,code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Numeric key or switch code associated with the event. + + additionalProperties: false + + "^event-touch(-alt)?$": + type: object + description: Represents a touch event reported by the channel. + + properties: + azoteq,thresh: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + default: 8 + description: Specifies the threshold for the event. + + azoteq,hyst: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + default: 4 + description: Specifies the hysteresis for the event. + + linux,code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Numeric key or switch code associated with the event. + + additionalProperties: false + + "^event-deep(-alt)?$": + type: object + description: Represents a deep-touch event reported by the channel. + + properties: + azoteq,thresh: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + default: 26 + description: Specifies the threshold for the event. + + azoteq,hyst: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + default: 0 + description: Specifies the hysteresis for the event. + + linux,code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Numeric key or switch code associated with the event. + + additionalProperties: false + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + iqs269a@44 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "azoteq,iqs269a"; + reg = <0x44>; + interrupt-parent = <&gpio>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + + azoteq,hall-enable; + azoteq,suspend-mode = <2>; + + channel@0 { + reg = <0x0>; + + event-prox { + linux,code = ; + }; + }; + + channel@1 { + reg = <0x1>; + azoteq,slider0-select; + }; + + channel@2 { + reg = <0x2>; + azoteq,slider0-select; + }; + + channel@3 { + reg = <0x3>; + azoteq,slider0-select; + }; + + channel@4 { + reg = <0x4>; + azoteq,slider0-select; + }; + + channel@5 { + reg = <0x5>; + azoteq,slider0-select; + }; + + channel@6 { + reg = <0x6>; + azoteq,invert-enable; + azoteq,static-enable; + azoteq,reseed-disable; + azoteq,rx-enable = <0>; + azoteq,sense-freq = <0x0>; + azoteq,sense-mode = <0xE>; + azoteq,ati-mode = <0x0>; + azoteq,ati-base = <200>; + azoteq,ati-target = <320>; + }; + + channel@7 { + reg = <0x7>; + azoteq,invert-enable; + azoteq,static-enable; + azoteq,reseed-disable; + azoteq,rx-enable = <0>, <6>; + azoteq,sense-freq = <0x0>; + azoteq,sense-mode = <0xE>; + azoteq,ati-mode = <0x3>; + azoteq,ati-base = <200>; + azoteq,ati-target = <320>; + + event-touch { + linux,code = ; + }; + }; + }; + }; + +... diff --git a/Bindings/input/iqs62x-keys.yaml b/Bindings/input/iqs62x-keys.yaml index 5625c222903a..77fe3b545b35 100644 --- a/Bindings/input/iqs62x-keys.yaml +++ b/Bindings/input/iqs62x-keys.yaml @@ -30,10 +30,9 @@ properties: - azoteq,iqs625-keys linux,keycodes: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 1 - maxItems: 16 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16 description: | Specifies the numeric keycodes associated with each available touch or proximity event according to the following table. An 'x' indicates the diff --git a/Bindings/input/msm-vibrator.txt b/Bindings/input/msm-vibrator.txt deleted file mode 100644 index 8dcf014ef2e5..000000000000 --- a/Bindings/input/msm-vibrator.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Device tree bindings for the Qualcomm MSM vibrator - -Required properties: - - - compatible: Should be one of - "qcom,msm8226-vibrator" - "qcom,msm8974-vibrator" - - reg: the base address and length of the IO memory for the registers. - - pinctrl-names: set to default. - - pinctrl-0: phandles pointing to pin configuration nodes. See - Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - - clock-names: set to pwm - - clocks: phandle of the clock. See - Documentation/devicetree/bindings/clock/clock-bindings.txt - - enable-gpios: GPIO that enables the vibrator. - -Optional properties: - - - vcc-supply: phandle to the regulator that provides power to the sensor. - -Example from a LG Nexus 5 (hammerhead) phone: - -vibrator@fd8c3450 { - reg = <0xfd8c3450 0x400>; - compatible = "qcom,msm8974-vibrator"; - - vcc-supply = <&pm8941_l19>; - - clocks = <&mmcc CAMSS_GP1_CLK>; - clock-names = "pwm"; - - enable-gpios = <&msmgpio 60 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&vibrator_pin>; -}; diff --git a/Bindings/input/touchscreen/cypress,cy8ctma140.yaml b/Bindings/input/touchscreen/cypress,cy8ctma140.yaml new file mode 100644 index 000000000000..8c73e5264312 --- /dev/null +++ b/Bindings/input/touchscreen/cypress,cy8ctma140.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/cypress,cy8ctma140.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cypress CY8CTMA140 series touchscreen controller bindings + +maintainers: + - Linus Walleij + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + const: cypress,cy8ctma140 + + reg: + const: 0x20 + + clock-frequency: + description: I2C client clock frequency, defined for host + minimum: 100000 + maximum: 400000 + + interrupts: + maxItems: 1 + + vcpin-supply: + description: Analog power supply regulator on VCPIN pin + + vdd-supply: + description: Digital power supply regulator on VDD pin + + touchscreen-inverted-x: true + touchscreen-inverted-y: true + touchscreen-size-x: true + touchscreen-size-y: true + touchscreen-swapped-x-y: true + touchscreen-max-pressure: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - touchscreen-size-x + - touchscreen-size-y + - touchscreen-max-pressure + +examples: +- | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + touchscreen@20 { + compatible = "cypress,cy8ctma140"; + reg = <0x20>; + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + touchscreen-max-pressure = <255>; + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&ab8500_ldo_aux2_reg>; + vcpin-supply = <&ab8500_ldo_aux2_reg>; + }; + }; + +... diff --git a/Bindings/input/touchscreen/edt-ft5x06.yaml b/Bindings/input/touchscreen/edt-ft5x06.yaml index 383d64a91854..024b262a2ef7 100644 --- a/Bindings/input/touchscreen/edt-ft5x06.yaml +++ b/Bindings/input/touchscreen/edt-ft5x06.yaml @@ -42,7 +42,7 @@ properties: - focaltech,ft6236 reg: - const: 0x38 + maxItems: 1 interrupts: maxItems: 1 @@ -61,33 +61,29 @@ properties: gain: description: Allows setting the sensitivity in the range from 0 to 31. Note that lower values indicate higher sensitivity. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - - maximum: 31 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 offset: description: Allows setting the edge compensation in the range from 0 to 31. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - - maximum: 31 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 offset-x: description: Same as offset, but applies only to the horizontal position. Range from 0 to 80, only supported by evervision,ev-ft5726 devices. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - - maximum: 80 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 80 offset-y: description: Same as offset, but applies only to the vertical position. Range from 0 to 80, only supported by evervision,ev-ft5726 devices. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - - maximum: 80 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 80 touchscreen-size-x: true touchscreen-size-y: true diff --git a/Bindings/input/touchscreen/elan,elants_i2c.yaml b/Bindings/input/touchscreen/elan,elants_i2c.yaml new file mode 100644 index 000000000000..a792d6377b1d --- /dev/null +++ b/Bindings/input/touchscreen/elan,elants_i2c.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/input/touchscreen/elan,elants_i2c.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Elantech I2C Touchscreen + +maintainers: + - David Heidelberg + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - elan,ektf3624 + - elan,ekth3500 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + wakeup-source: + type: boolean + description: touchscreen can be used as a wakeup source. + + reset-gpios: + description: reset gpio the chip is connected to. + + vcc33-supply: + description: a phandle for the regulator supplying 3.3V power. + + vccio-supply: + description: a phandle for the regulator supplying IO power. + + touchscreen-inverted-x: true + touchscreen-inverted-y: true + touchscreen-size-x: true + touchscreen-size-y: true + touchscreen-swapped-x-y: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + + interrupt-parent = <&gpio4>; + interrupts = <0x0 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + }; diff --git a/Bindings/input/touchscreen/goodix.yaml b/Bindings/input/touchscreen/goodix.yaml index c8ea9434c9cc..e81cfa56f25a 100644 --- a/Bindings/input/touchscreen/goodix.yaml +++ b/Bindings/input/touchscreen/goodix.yaml @@ -63,7 +63,7 @@ required: - interrupts examples: -- | + - | i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/Bindings/input/touchscreen/mms114.txt b/Bindings/input/touchscreen/mms114.txt index 2cd954051d29..707234cfd7e6 100644 --- a/Bindings/input/touchscreen/mms114.txt +++ b/Bindings/input/touchscreen/mms114.txt @@ -1,9 +1,10 @@ -* MELFAS MMS114/MMS152 touchscreen controller +* MELFAS MMS114/MMS152/MMS345L touchscreen controller Required properties: - compatible: should be one of: - "melfas,mms114" - "melfas,mms152" + - "melfas,mms345l" - reg: I2C address of the chip - interrupts: interrupt to which the chip is connected - touchscreen-size-x: See [1] diff --git a/Bindings/interconnect/fsl,imx8m-noc.yaml b/Bindings/interconnect/fsl,imx8m-noc.yaml new file mode 100644 index 000000000000..ff09550ad959 --- /dev/null +++ b/Bindings/interconnect/fsl,imx8m-noc.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic i.MX bus frequency device + +maintainers: + - Leonard Crestez + +description: | + The i.MX SoC family has multiple buses for which clock frequency (and + sometimes voltage) can be adjusted. + + Some of those buses expose register areas mentioned in the memory maps as GPV + ("Global Programmers View") but not all. Access to this area might be denied + for normal (non-secure) world. + + The buses are based on externally licensed IPs such as ARM NIC-301 and + Arteris FlexNOC but DT bindings are specific to the integration of these bus + interconnect IPs into imx SOCs. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,imx8mn-nic + - fsl,imx8mm-nic + - fsl,imx8mq-nic + - const: fsl,imx8m-nic + - items: + - enum: + - fsl,imx8mn-noc + - fsl,imx8mm-noc + - fsl,imx8mq-noc + - const: fsl,imx8m-noc + - const: fsl,imx8m-nic + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + operating-points-v2: true + opp-table: true + + fsl,ddrc: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: + Phandle to DDR Controller. + + '#interconnect-cells': + description: + If specified then also act as an interconnect provider. Should only be + set once per soc on the main noc. + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + #include + + noc: interconnect@32700000 { + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MM_CLK_NOC>; + #interconnect-cells = <1>; + fsl,ddrc = <&ddrc>; + + operating-points-v2 = <&noc_opp_table>; + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133M { + opp-hz = /bits/ 64 <133333333>; + }; + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; + }; + + ddrc: memory-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, + <&clk IMX8MM_DRAM_PLL>, + <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>; + }; diff --git a/Bindings/interconnect/qcom,msm8916.yaml b/Bindings/interconnect/qcom,msm8916.yaml index 4107e60cab12..e1009ae4e8f7 100644 --- a/Bindings/interconnect/qcom,msm8916.yaml +++ b/Bindings/interconnect/qcom,msm8916.yaml @@ -10,8 +10,8 @@ maintainers: - Georgi Djakov description: | - The Qualcomm MSM8916 interconnect providers support adjusting the - bandwidth requirements between the various NoC fabrics. + The Qualcomm MSM8916 interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. properties: compatible: diff --git a/Bindings/interconnect/qcom,msm8974.yaml b/Bindings/interconnect/qcom,msm8974.yaml index 9af3c6e59cff..8004c4baf397 100644 --- a/Bindings/interconnect/qcom,msm8974.yaml +++ b/Bindings/interconnect/qcom,msm8974.yaml @@ -10,8 +10,8 @@ maintainers: - Brian Masney description: | - The Qualcomm MSM8974 interconnect providers support setting system - bandwidth requirements between various network-on-chip fabrics. + The Qualcomm MSM8974 interconnect providers support setting system + bandwidth requirements between various network-on-chip fabrics. properties: reg: diff --git a/Bindings/interconnect/qcom,qcs404.yaml b/Bindings/interconnect/qcom,qcs404.yaml index 8d65c5f80679..3fbb8785fbc9 100644 --- a/Bindings/interconnect/qcom,qcs404.yaml +++ b/Bindings/interconnect/qcom,qcs404.yaml @@ -10,8 +10,8 @@ maintainers: - Georgi Djakov description: | - The Qualcomm QCS404 interconnect providers support adjusting the - bandwidth requirements between the various NoC fabrics. + The Qualcomm QCS404 interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. properties: reg: diff --git a/Bindings/interconnect/qcom,sc7180.yaml b/Bindings/interconnect/qcom,sc7180.yaml index 50f78f87f3fb..d01bac80d416 100644 --- a/Bindings/interconnect/qcom,sc7180.yaml +++ b/Bindings/interconnect/qcom,sc7180.yaml @@ -65,21 +65,21 @@ examples: config_noc: interconnect@1500000 { compatible = "qcom,sc7180-config-noc"; - reg = <0 0x01500000 0 0x28000>; + reg = <0x01500000 0x28000>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; system_noc: interconnect@1620000 { compatible = "qcom,sc7180-system-noc"; - reg = <0 0x01620000 0 0x17080>; + reg = <0x01620000 0x17080>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sc7180-mmss-noc"; - reg = <0 0x01740000 0 0x1c100>; + reg = <0x01740000 0x1c100>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; diff --git a/Bindings/interconnect/qcom,sdm845.yaml b/Bindings/interconnect/qcom,sdm845.yaml index 8b087e0b0b81..74536747b51d 100644 --- a/Bindings/interconnect/qcom,sdm845.yaml +++ b/Bindings/interconnect/qcom,sdm845.yaml @@ -60,14 +60,14 @@ examples: mem_noc: interconnect@1380000 { compatible = "qcom,sdm845-mem-noc"; - reg = <0 0x01380000 0 0x27200>; + reg = <0x01380000 0x27200>; #interconnect-cells = <1>; qcom,bcm-voters = <&apps_bcm_voter>; }; mmss_noc: interconnect@1740000 { compatible = "qcom,sdm845-mmss-noc"; - reg = <0 0x01740000 0 0x1c1000>; + reg = <0x01740000 0x1c1000>; #interconnect-cells = <1>; qcom,bcm-voter-names = "apps", "disp"; qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>; diff --git a/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index cf09055da78b..7cd6b8bacfa0 100644 --- a/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -27,15 +27,15 @@ properties: deprecated: true - const: allwinner,sun7i-a20-sc-nmi - items: - - const: allwinner,sun8i-a83t-r-intc - - const: allwinner,sun6i-a31-r-intc + - const: allwinner,sun8i-a83t-r-intc + - const: allwinner,sun6i-a31-r-intc - const: allwinner,sun9i-a80-sc-nmi - items: - - const: allwinner,sun50i-a64-r-intc - - const: allwinner,sun6i-a31-r-intc + - const: allwinner,sun50i-a64-r-intc + - const: allwinner,sun6i-a31-r-intc - items: - - const: allwinner,sun50i-h6-r-intc - - const: allwinner,sun6i-a31-r-intc + - const: allwinner,sun50i-h6-r-intc + - const: allwinner,sun6i-a31-r-intc reg: maxItems: 1 diff --git a/Bindings/interrupt-controller/arm,gic-v3.yaml b/Bindings/interrupt-controller/arm,gic-v3.yaml index 66aacd106503..1ecd1831cf02 100644 --- a/Bindings/interrupt-controller/arm,gic-v3.yaml +++ b/Bindings/interrupt-controller/arm,gic-v3.yaml @@ -91,18 +91,16 @@ properties: description: If using padding pages, specifies the stride of consecutive redistributors. Must be a multiple of 64kB. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint64 - - multipleOf: 0x10000 - exclusiveMinimum: 0 + $ref: /schemas/types.yaml#/definitions/uint64 + multipleOf: 0x10000 + exclusiveMinimum: 0 "#redistributor-regions": description: The number of independent contiguous regions occupied by the redistributors. Required if more than one such region is present. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - maximum: 4096 # Should be enough? + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 4096 msi-controller: description: @@ -114,22 +112,20 @@ properties: A list of pairs , where "intid" is the first SPI of a range that can be used an MBI, and "span" the size of that range. Multiple ranges can be provided. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-matrix - - items: - minItems: 2 - maxItems: 2 + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + minItems: 2 + maxItems: 2 mbi-alias: description: Address property. Base address of an alias of the GICD region containing only the {SET,CLR}SPI registers to be used if isolation is required, and if supported by the HW. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - items: - minItems: 1 - maxItems: 2 + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + minItems: 1 + maxItems: 2 ppi-partitions: type: object @@ -188,11 +184,10 @@ patternProperties: description: (u32, u32) tuple describing the untranslated address and size of the pre-ITS window. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - items: - minItems: 2 - maxItems: 2 + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + minItems: 2 + maxItems: 2 required: - compatible diff --git a/Bindings/interrupt-controller/arm,gic.yaml b/Bindings/interrupt-controller/arm,gic.yaml index 9a47820ef346..96f8803ff4e6 100644 --- a/Bindings/interrupt-controller/arm,gic.yaml +++ b/Bindings/interrupt-controller/arm,gic.yaml @@ -39,6 +39,12 @@ properties: - qcom,msm-8660-qgic - qcom,msm-qgic2 + - items: + - const: arm,gic-400 + - enum: + - arm,cortex-a15-gic + - arm,cortex-a7-gic + - items: - const: arm,arm1176jzf-devchip-gic - const: arm,arm11mp-gic @@ -125,6 +131,9 @@ properties: power-domains: maxItems: 1 + resets: + maxItems: 1 + required: - compatible - reg diff --git a/Bindings/interrupt-controller/csky,mpintc.txt b/Bindings/interrupt-controller/csky,mpintc.txt index e13405355166..e6bbcae4d07f 100644 --- a/Bindings/interrupt-controller/csky,mpintc.txt +++ b/Bindings/interrupt-controller/csky,mpintc.txt @@ -10,7 +10,7 @@ Interrupt number definition: 16-31 : private irq, and we use 16 as the co-processor timer. 31-1024: common irq for soc ip. -Interrupt triger mode: (Defined in dt-bindings/interrupt-controller/irq.h) +Interrupt trigger mode: (Defined in dt-bindings/interrupt-controller/irq.h) IRQ_TYPE_LEVEL_HIGH (default) IRQ_TYPE_LEVEL_LOW IRQ_TYPE_EDGE_RISING diff --git a/Bindings/interrupt-controller/fsl,irqsteer.txt b/Bindings/interrupt-controller/fsl,irqsteer.txt deleted file mode 100644 index 582991c426ee..000000000000 --- a/Bindings/interrupt-controller/fsl,irqsteer.txt +++ /dev/null @@ -1,35 +0,0 @@ -Freescale IRQSTEER Interrupt multiplexer - -Required properties: - -- compatible: should be: - - "fsl,imx8m-irqsteer" - - "fsl,imx-irqsteer" -- reg: Physical base address and size of registers. -- interrupts: Should contain the up to 8 parent interrupt lines used to - multiplex the input interrupts. They should be specified sequentially - from output 0 to 7. -- clocks: Should contain one clock for entry in clock-names - see Documentation/devicetree/bindings/clock/clock-bindings.txt -- clock-names: - - "ipg": main logic clock -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: Specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- fsl,channel: The output channel that all input IRQs should be steered into. -- fsl,num-irqs: Number of input interrupts of this channel. - Should be multiple of 32 input interrupts and up to 512 interrupts. - -Example: - - interrupt-controller@32e2d000 { - compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; - reg = <0x32e2d000 0x1000>; - interrupts = ; - clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; - clock-names = "ipg"; - fsl,channel = <0>; - fsl,num-irqs = <64>; - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Bindings/interrupt-controller/fsl,irqsteer.yaml b/Bindings/interrupt-controller/fsl,irqsteer.yaml new file mode 100644 index 000000000000..360a575ef8b0 --- /dev/null +++ b/Bindings/interrupt-controller/fsl,irqsteer.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IRQSTEER Interrupt Multiplexer + +maintainers: + - Lucas Stach + +properties: + compatible: + enum: + - fsl,imx8m-irqsteer + - fsl,imx-irqsteer + + reg: + maxItems: 1 + + interrupts: + description: | + should contain the up to 8 parent interrupt lines used to multiplex + the input interrupts. They should be specified sequentially from + output 0 to 7. + items: + - description: output interrupt 0 + - description: output interrupt 1 + - description: output interrupt 2 + - description: output interrupt 3 + - description: output interrupt 4 + - description: output interrupt 5 + - description: output interrupt 6 + - description: output interrupt 7 + minItems: 1 + maxItems: 8 + + clocks: + maxItems: 1 + + clock-names: + const: ipg + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + fsl,channel: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + u32 value representing the output channel that all input IRQs should be + steered into. + + fsl,num-irqs: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + u32 value representing the number of input interrupts of this channel, + should be multiple of 32 input interrupts and up to 512 interrupts. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - interrupt-controller + - "#interrupt-cells" + - fsl,channel + - fsl,num-irqs + +additionalProperties: false + +examples: + - | + #include + #include + + interrupt-controller@32e2d000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x32e2d000 0x1000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; + clock-names = "ipg"; + fsl,channel = <0>; + fsl,num-irqs = <64>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Bindings/interrupt-controller/ingenic,intc.txt b/Bindings/interrupt-controller/ingenic,intc.txt deleted file mode 100644 index d4373d0f7121..000000000000 --- a/Bindings/interrupt-controller/ingenic,intc.txt +++ /dev/null @@ -1,28 +0,0 @@ -Ingenic SoC Interrupt Controller - -Required properties: - -- compatible : should be "ingenic,-intc". Valid strings are: - ingenic,jz4740-intc - ingenic,jz4725b-intc - ingenic,jz4770-intc - ingenic,jz4775-intc - ingenic,jz4780-intc -- reg : Specifies base physical address and size of the registers. -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 1. -- interrupts : Specifies the CPU interrupt the controller is connected to. - -Example: - -intc: interrupt-controller@10001000 { - compatible = "ingenic,jz4740-intc"; - reg = <0x10001000 0x14>; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&cpuintc>; - interrupts = <2>; -}; diff --git a/Bindings/interrupt-controller/ingenic,intc.yaml b/Bindings/interrupt-controller/ingenic,intc.yaml new file mode 100644 index 000000000000..28b27e1a6e9d --- /dev/null +++ b/Bindings/interrupt-controller/ingenic,intc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/ingenic,intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs interrupt controller devicetree bindings + +maintainers: + - Paul Cercueil + +properties: + $nodename: + pattern: "^interrupt-controller@[0-9a-f]+$" + + compatible: + oneOf: + - enum: + - ingenic,jz4740-intc + - ingenic,jz4760-intc + - ingenic,jz4780-intc + - items: + - enum: + - ingenic,jz4775-intc + - ingenic,jz4770-intc + - const: ingenic,jz4760-intc + - items: + - const: ingenic,x1000-intc + - const: ingenic,jz4780-intc + - items: + - const: ingenic,jz4725b-intc + - const: ingenic,jz4740-intc + + "#interrupt-cells": + const: 1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + +required: + - compatible + - reg + - interrupts + - "#interrupt-cells" + - interrupt-controller + +examples: + - | + intc: interrupt-controller@10001000 { + compatible = "ingenic,jz4770-intc", "ingenic,jz4760-intc"; + reg = <0x10001000 0x40>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; diff --git a/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml b/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml index ccc507f384d2..14dced11877b 100644 --- a/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml +++ b/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml @@ -25,10 +25,10 @@ properties: compatible: items: - enum: - - intel,ixp42x-interrupt - - intel,ixp43x-interrupt - - intel,ixp45x-interrupt - - intel,ixp46x-interrupt + - intel,ixp42x-interrupt + - intel,ixp43x-interrupt + - intel,ixp45x-interrupt + - intel,ixp46x-interrupt reg: maxItems: 1 diff --git a/Bindings/interrupt-controller/loongson,htvec.yaml b/Bindings/interrupt-controller/loongson,htvec.yaml new file mode 100644 index 000000000000..e865cd8f96a9 --- /dev/null +++ b/Bindings/interrupt-controller/loongson,htvec.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson-3 HyperTransport Interrupt Vector Controller + +maintainers: + - Jiaxun Yang + +description: + This interrupt controller is found in the Loongson-3 family of chips for + receiving vectorized interrupts from PCH's interrupt controller. + +properties: + compatible: + const: loongson,htvec-1.0 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 4 + description: Four parent interrupts that receive chained interrupts. + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + #include + htvec: interrupt-controller@fb000080 { + compatible = "loongson,htvec-1.0"; + reg = <0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&liointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +... diff --git a/Bindings/interrupt-controller/loongson,liointc.yaml b/Bindings/interrupt-controller/loongson,liointc.yaml index 26f1fcf0857a..b1db21ed44e9 100644 --- a/Bindings/interrupt-controller/loongson,liointc.yaml +++ b/Bindings/interrupt-controller/loongson,liointc.yaml @@ -54,11 +54,9 @@ properties: and each bit in the cell refers to a children interrupt fron 0 to 31. If a CPU interrupt line didn't connected with liointc, then keep it's cell with zero. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 4 - maxItems: 4 - + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 4 + maxItems: 4 required: - compatible diff --git a/Bindings/interrupt-controller/loongson,pch-msi.yaml b/Bindings/interrupt-controller/loongson,pch-msi.yaml new file mode 100644 index 000000000000..1b256d9dd92a --- /dev/null +++ b/Bindings/interrupt-controller/loongson,pch-msi.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson PCH MSI Controller + +maintainers: + - Jiaxun Yang + +description: + This interrupt controller is found in the Loongson LS7A family of PCH for + transforming interrupts from PCIe MSI into HyperTransport vectorized + interrupts. + +properties: + compatible: + const: loongson,pch-msi-1.0 + + reg: + maxItems: 1 + + loongson,msi-base-vec: + description: + u32 value of the base of parent HyperTransport vector allocated + to PCH MSI. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 255 + + loongson,msi-num-vecs: + description: + u32 value of the number of parent HyperTransport vectors allocated + to PCH MSI. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 1 + maximum: 256 + + msi-controller: true + +required: + - compatible + - reg + - msi-controller + - loongson,msi-base-vec + - loongson,msi-num-vecs + +examples: + - | + #include + msi: msi-controller@2ff00000 { + compatible = "loongson,pch-msi-1.0"; + reg = <0x2ff00000 0x4>; + msi-controller; + loongson,msi-base-vec = <64>; + loongson,msi-num-vecs = <64>; + interrupt-parent = <&htvec>; + }; +... diff --git a/Bindings/interrupt-controller/loongson,pch-pic.yaml b/Bindings/interrupt-controller/loongson,pch-pic.yaml new file mode 100644 index 000000000000..a6dcbb2971a9 --- /dev/null +++ b/Bindings/interrupt-controller/loongson,pch-pic.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson PCH PIC Controller + +maintainers: + - Jiaxun Yang + +description: + This interrupt controller is found in the Loongson LS7A family of PCH for + transforming interrupts from on-chip devices into HyperTransport vectorized + interrupts. + +properties: + compatible: + const: loongson,pch-pic-1.0 + + reg: + maxItems: 1 + + loongson,pic-base-vec: + description: + u32 value of the base of parent HyperTransport vector allocated + to PCH PIC. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 192 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +required: + - compatible + - reg + - loongson,pic-base-vec + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + #include + pic: interrupt-controller@10000000 { + compatible = "loongson,pch-pic-1.0"; + reg = <0x10000000 0x400>; + interrupt-controller; + #interrupt-cells = <2>; + loongson,pic-base-vec = <64>; + interrupt-parent = <&htvec>; + }; +... diff --git a/Bindings/interrupt-controller/renesas,intc-irqpin.txt b/Bindings/interrupt-controller/renesas,intc-irqpin.txt deleted file mode 100644 index 772c550d3b4b..000000000000 --- a/Bindings/interrupt-controller/renesas,intc-irqpin.txt +++ /dev/null @@ -1,62 +0,0 @@ -DT bindings for the R-/SH-Mobile irqpin controller - -Required properties: - -- compatible: has to be "renesas,intc-irqpin-", "renesas,intc-irqpin" - as fallback. - Examples with soctypes are: - - "renesas,intc-irqpin-r8a7740" (R-Mobile A1) - - "renesas,intc-irqpin-r8a7778" (R-Car M1A) - - "renesas,intc-irqpin-r8a7779" (R-Car H1) - - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5) - -- reg: Base address and length of each register bank used by the external - IRQ pins driven by the interrupt controller hardware module. The base - addresses, length and number of required register banks varies with soctype. -- interrupt-controller: Identifies the node as an interrupt controller. -- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in - interrupts.txt in this directory. -- interrupts: Must contain a list of interrupt specifiers. For each interrupt - provided by this irqpin controller instance, there must be one entry, - referring to the corresponding parent interrupt. - -Optional properties: - -- any properties, listed in interrupts.txt, and any standard resource allocation - properties -- sense-bitfield-width: width of a single sense bitfield in the SENSE register, - if different from the default 4 bits -- control-parent: disable and enable interrupts on the parent interrupt - controller, needed for some broken implementations -- clocks: Must contain a reference to the functional clock. This property is - mandatory if the hardware implements a controllable functional clock for - the irqpin controller instance. -- power-domains: Must contain a reference to the power domain. This property is - mandatory if the irqpin controller instance is part of a controllable power - domain. - - -Example -------- - - irqpin1: interrupt-controller@e6900004 { - compatible = "renesas,intc-irqpin-r8a7740", - "renesas,intc-irqpin"; - #interrupt-cells = <2>; - interrupt-controller; - reg = <0xe6900004 4>, - <0xe6900014 4>, - <0xe6900024 1>, - <0xe6900044 1>, - <0xe6900064 1>; - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH - 0 149 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp2_clks R8A7740_CLK_INTCA>; - power-domains = <&pd_a4s>; - }; diff --git a/Bindings/interrupt-controller/renesas,intc-irqpin.yaml b/Bindings/interrupt-controller/renesas,intc-irqpin.yaml new file mode 100644 index 000000000000..f4aae56c6469 --- /dev/null +++ b/Bindings/interrupt-controller/renesas,intc-irqpin.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Interrupt Controller (INTC) for external pins + +maintainers: + - Geert Uytterhoeven + +properties: + compatible: + items: + - enum: + - renesas,intc-irqpin-r8a7740 # R-Mobile A1 + - renesas,intc-irqpin-r8a7778 # R-Car M1A + - renesas,intc-irqpin-r8a7779 # R-Car H1 + - renesas,intc-irqpin-sh73a0 # SH-Mobile AG5 + - const: renesas,intc-irqpin + + reg: + minItems: 5 + items: + - description: Interrupt control register + - description: Interrupt priority register + - description: Interrupt source register + - description: Interrupt mask register + - description: Interrupt mask clear register + - description: Interrupt control register for ICR0 with IRLM0 bit + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + minItems: 1 + maxItems: 8 + + sense-bitfield-width: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 4] + default: 4 + description: + Width of a single sense bitfield in the SENSE register, if different from the + default. + + control-parent: + type: boolean + description: + Disable and enable interrupts on the parent interrupt controller, needed for some + broken implementations. + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +if: + properties: + compatible: + contains: + enum: + - renesas,intc-irqpin-r8a7740 + - renesas,intc-irqpin-sh73a0 +then: + required: + - clocks + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + + irqpin1: interrupt-controller@e6900004 { + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; + reg = <0xe6900004 4>, + <0xe6900014 4>, + <0xe6900024 1>, + <0xe6900044 1>, + <0xe6900064 1>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; + power-domains = <&pd_a4s>; + }; diff --git a/Bindings/interrupt-controller/renesas,irqc.yaml b/Bindings/interrupt-controller/renesas,irqc.yaml index ee5273b6c5a3..b67b8cbd33fc 100644 --- a/Bindings/interrupt-controller/renesas,irqc.yaml +++ b/Bindings/interrupt-controller/renesas,irqc.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - renesas,irqc-r8a73a4 # R-Mobile APE6 + - renesas,irqc-r8a7742 # RZ/G1H - renesas,irqc-r8a7743 # RZ/G1M - renesas,irqc-r8a7744 # RZ/G1N - renesas,irqc-r8a7745 # RZ/G1E @@ -78,7 +79,7 @@ examples: compatible = "renesas,irqc-r8a7790", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; - reg = <0 0xe61c0000 0 0x200>; + reg = <0xe61c0000 0x200>; interrupts = , , , diff --git a/Bindings/interrupt-controller/st,stm32-exti.yaml b/Bindings/interrupt-controller/st,stm32-exti.yaml index 9e5c6608b4e3..2a5b29567926 100644 --- a/Bindings/interrupt-controller/st,stm32-exti.yaml +++ b/Bindings/interrupt-controller/st,stm32-exti.yaml @@ -14,13 +14,13 @@ properties: compatible: oneOf: - items: - - enum: - - st,stm32-exti - - st,stm32h7-exti + - enum: + - st,stm32-exti + - st,stm32h7-exti - items: - - enum: - - st,stm32mp1-exti - - const: syscon + - enum: + - st,stm32mp1-exti + - const: syscon "#interrupt-cells": const: 2 diff --git a/Bindings/iommu/allwinner,sun50i-h6-iommu.yaml b/Bindings/iommu/allwinner,sun50i-h6-iommu.yaml new file mode 100644 index 000000000000..5e125cf2a88b --- /dev/null +++ b/Bindings/iommu/allwinner,sun50i-h6-iommu.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/allwinner,sun50i-h6-iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner H6 IOMMU Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + - Maxime Ripard + +properties: + "#iommu-cells": + const: 1 + description: + The content of the cell is the master ID. + + compatible: + const: allwinner,sun50i-h6-iommu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - "#iommu-cells" + - compatible + - reg + - interrupts + - clocks + - resets + +additionalProperties: false + +examples: + - | + #include + #include + + #include + #include + + iommu: iommu@30f0000 { + compatible = "allwinner,sun50i-h6-iommu"; + reg = <0x030f0000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_IOMMU>; + resets = <&ccu RST_BUS_IOMMU>; + #iommu-cells = <1>; + }; + +... diff --git a/Bindings/iommu/arm,smmu.yaml b/Bindings/iommu/arm,smmu.yaml index 6515dbe47508..d7ceb4c34423 100644 --- a/Bindings/iommu/arm,smmu.yaml +++ b/Bindings/iommu/arm,smmu.yaml @@ -28,6 +28,7 @@ properties: - enum: - qcom,msm8996-smmu-v2 - qcom,msm8998-smmu-v2 + - qcom,sc7180-smmu-v2 - qcom,sdm845-smmu-v2 - const: qcom,smmu-v2 @@ -41,7 +42,9 @@ properties: - const: arm,mmu-500 - const: arm,smmu-v2 - items: - - const: arm,mmu-401 + - enum: + - arm,mmu-400 + - arm,mmu-401 - const: arm,smmu-v1 - enum: - arm,smmu-v1 @@ -56,8 +59,7 @@ properties: '#global-interrupts': description: The number of global interrupts exposed by the device. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters diff --git a/Bindings/iommu/renesas,ipmmu-vmsa.txt b/Bindings/iommu/renesas,ipmmu-vmsa.txt deleted file mode 100644 index 020d6f226efb..000000000000 --- a/Bindings/iommu/renesas,ipmmu-vmsa.txt +++ /dev/null @@ -1,73 +0,0 @@ -* Renesas VMSA-Compatible IOMMU - -The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables. -It provides address translation for bus masters outside of the CPU, each -connected to the IPMMU through a port called micro-TLB. - - -Required Properties: - - - compatible: Must contain SoC-specific and generic entry below in case - the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU. - - - "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU. - - "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU. - - "renesas,ipmmu-r8a7744" for the R8A7744 (RZ/G1N) IPMMU. - - "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU. - - "renesas,ipmmu-r8a774a1" for the R8A774A1 (RZ/G2M) IPMMU. - - "renesas,ipmmu-r8a774b1" for the R8A774B1 (RZ/G2N) IPMMU. - - "renesas,ipmmu-r8a774c0" for the R8A774C0 (RZ/G2E) IPMMU. - - "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU. - - "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU. - - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU. - - "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU. - - "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU. - - "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU. - - "renesas,ipmmu-r8a77965" for the R8A77965 (R-Car M3-N) IPMMU. - - "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU. - - "renesas,ipmmu-r8a77980" for the R8A77980 (R-Car V3H) IPMMU. - - "renesas,ipmmu-r8a77990" for the R8A77990 (R-Car E3) IPMMU. - - "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU. - - "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible - IPMMU. - - - reg: Base address and size of the IPMMU registers. - - interrupts: Specifiers for the MMU fault interrupts. For instances that - support secure mode two interrupts must be specified, for non-secure and - secure mode, in that order. For instances that don't support secure mode a - single interrupt must be specified. Not required for cache IPMMUs. - - - #iommu-cells: Must be 1. - -Optional properties: - - - renesas,ipmmu-main: reference to the main IPMMU instance in two cells. - The first cell is a phandle to the main IPMMU and the second cell is - the interrupt bit number associated with the particular cache IPMMU device. - The interrupt bit number needs to match the main IPMMU IMSSTR register. - Only used by cache IPMMU instances. - - -Each bus master connected to an IPMMU must reference the IPMMU in its device -node with the following property: - - - iommus: A reference to the IPMMU in two cells. The first cell is a phandle - to the IPMMU and the second cell the number of the micro-TLB that the - device is connected to. - - -Example: R8A7791 IPMMU-MX and VSP1-D0 bus master - - ipmmu_mx: mmu@fe951000 { - compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa"; - reg = <0 0xfe951000 0 0x1000>; - interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, - <0 221 IRQ_TYPE_LEVEL_HIGH>; - #iommu-cells = <1>; - }; - - vsp@fe928000 { - ... - iommus = <&ipmmu_mx 13>; - ... - }; diff --git a/Bindings/iommu/renesas,ipmmu-vmsa.yaml b/Bindings/iommu/renesas,ipmmu-vmsa.yaml new file mode 100644 index 000000000000..39675cf4ed71 --- /dev/null +++ b/Bindings/iommu/renesas,ipmmu-vmsa.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas VMSA-Compatible IOMMU + +maintainers: + - Yoshihiro Shimoda + +description: + The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables. + It provides address translation for bus masters outside of the CPU, each + connected to the IPMMU through a port called micro-TLB. + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,ipmmu-r8a73a4 # R-Mobile APE6 + - renesas,ipmmu-r8a7743 # RZ/G1M + - renesas,ipmmu-r8a7744 # RZ/G1N + - renesas,ipmmu-r8a7745 # RZ/G1E + - renesas,ipmmu-r8a7790 # R-Car H2 + - renesas,ipmmu-r8a7791 # R-Car M2-W + - renesas,ipmmu-r8a7793 # R-Car M2-N + - renesas,ipmmu-r8a7794 # R-Car E2 + - const: renesas,ipmmu-vmsa # R-Mobile APE6 or R-Car Gen2 or RZ/G1 + - items: + - enum: + - renesas,ipmmu-r8a774a1 # RZ/G2M + - renesas,ipmmu-r8a774b1 # RZ/G2N + - renesas,ipmmu-r8a774c0 # RZ/G2E + - renesas,ipmmu-r8a7795 # R-Car H3 + - renesas,ipmmu-r8a7796 # R-Car M3-W + - renesas,ipmmu-r8a77965 # R-Car M3-N + - renesas,ipmmu-r8a77970 # R-Car V3M + - renesas,ipmmu-r8a77980 # R-Car V3H + - renesas,ipmmu-r8a77990 # R-Car E3 + - renesas,ipmmu-r8a77995 # R-Car D3 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + description: + Specifiers for the MMU fault interrupts. Not required for cache IPMMUs. + items: + - description: non-secure mode + - description: secure mode if supported + + '#iommu-cells': + const: 1 + description: + The number of the micro-TLB that the device is connected to. + + power-domains: + maxItems: 1 + + renesas,ipmmu-main: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Reference to the main IPMMU phandle plus 1 cell. The cell is + the interrupt bit number associated with the particular cache IPMMU + device. The interrupt bit number needs to match the main IPMMU IMSSTR + register. Only used by cache IPMMU instances. + +required: + - compatible + - reg + - '#iommu-cells' + - power-domains + +oneOf: + - required: + - interrupts + - required: + - renesas,ipmmu-main + +additionalProperties: false + +examples: + - | + #include + #include + #include + + ipmmu_mx: iommu@fe951000 { + compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa"; + reg = <0xfe951000 0x1000>; + interrupts = , + ; + #iommu-cells = <1>; + }; diff --git a/Bindings/iommu/samsung,sysmmu.yaml b/Bindings/iommu/samsung,sysmmu.yaml index 0e33cd9e010e..af51b91c893e 100644 --- a/Bindings/iommu/samsung,sysmmu.yaml +++ b/Bindings/iommu/samsung,sysmmu.yaml @@ -54,13 +54,13 @@ properties: clock-names: oneOf: - items: - - const: sysmmu + - const: sysmmu - items: - - const: sysmmu - - const: master + - const: sysmmu + - const: master - items: - - const: aclk - - const: pclk + - const: aclk + - const: pclk "#iommu-cells": const: 0 diff --git a/Bindings/ipmi/ipmi-smic.txt b/Bindings/ipmi/ipmi-smic.txt deleted file mode 100644 index d5f1a877ed3e..000000000000 --- a/Bindings/ipmi/ipmi-smic.txt +++ /dev/null @@ -1,25 +0,0 @@ -IPMI device - -Required properties: -- compatible: should be one of ipmi-kcs, ipmi-smic, or ipmi-bt -- device_type: should be ipmi -- reg: Address and length of the register set for the device - -Optional properties: -- interrupts: The interrupt for the device. Without this the interface - is polled. -- reg-size - The size of the register. Defaults to 1 -- reg-spacing - The number of bytes between register starts. Defaults to 1 -- reg-shift - The amount to shift the registers to the right to get the data - into bit zero. - -Example: - -smic@fff3a000 { - compatible = "ipmi-smic"; - device_type = "ipmi"; - reg = <0xfff3a000 0x1000>; - interrupts = <0 24 4>; - reg-size = <4>; - reg-spacing = <4>; -}; diff --git a/Bindings/ipmi/ipmi-smic.yaml b/Bindings/ipmi/ipmi-smic.yaml new file mode 100644 index 000000000000..58fa76ee6176 --- /dev/null +++ b/Bindings/ipmi/ipmi-smic.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ipmi/ipmi-smic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: IPMI device bindings + +description: IPMI device bindings + +maintainers: + - Corey Minyard + +properties: + compatible: + enum: + - ipmi-kcs + - ipmi-smic + - ipmi-bt + + device_type: + items: + - const: "ipmi" + + reg: + maxItems: 1 + + interrupts: + description: Interface is polled if this property is omitted. + maxItems: 1 + + reg-size: + description: The access width of the register in bytes. Defaults to 1. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8] + + reg-spacing: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of bytes between register starts. Defaults to 1. + + reg-shift: + description: | + The amount of bits to shift the register content to the right to get + the data into bit zero. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 56 + +required: + - compatible + - reg + +examples: + - | + smic@fff3a000 { + compatible = "ipmi-smic"; + device_type = "ipmi"; + reg = <0xfff3a000 0x1000>; + interrupts = <0 24 4>; + reg-size = <4>; + reg-spacing = <4>; + }; diff --git a/Bindings/leds/backlight/qcom-wled.txt b/Bindings/leds/backlight/qcom-wled.txt deleted file mode 100644 index c06863badfbd..000000000000 --- a/Bindings/leds/backlight/qcom-wled.txt +++ /dev/null @@ -1,154 +0,0 @@ -Binding for Qualcomm Technologies, Inc. WLED driver - -WLED (White Light Emitting Diode) driver is used for controlling display -backlight that is part of PMIC on Qualcomm Technologies, Inc. reference -platforms. The PMIC is connected to the host processor via SPMI bus. - -- compatible - Usage: required - Value type: - Definition: should be one of: - "qcom,pm8941-wled" - "qcom,pmi8998-wled" - "qcom,pm660l-wled" - -- reg - Usage: required - Value type: - Definition: Base address of the WLED modules. - -- default-brightness - Usage: optional - Value type: - Definition: brightness value on boot, value from: 0-4095. - Default: 2048 - -- label - Usage: required - Value type: - Definition: The name of the backlight device - -- qcom,cs-out - Usage: optional - Value type: - Definition: enable current sink output. - This property is supported only for PM8941. - -- qcom,cabc - Usage: optional - Value type: - Definition: enable content adaptive backlight control. - -- qcom,ext-gen - Usage: optional - Value type: - Definition: use externally generated modulator signal to dim. - This property is supported only for PM8941. - -- qcom,current-limit - Usage: optional - Value type: - Definition: mA; per-string current limit; value from 0 to 25 with - 1 mA step. Default 20 mA. - This property is supported only for pm8941. - -- qcom,current-limit-microamp - Usage: optional - Value type: - Definition: uA; per-string current limit; value from 0 to 30000 with - 2500 uA step. Default 25 mA. - -- qcom,current-boost-limit - Usage: optional - Value type: - Definition: mA; boost current limit. - For pm8941: one of: 105, 385, 525, 805, 980, 1260, 1400, - 1680. Default: 805 mA. - For pmi8998: one of: 105, 280, 450, 620, 970, 1150, 1300, - 1500. Default: 970 mA. - -- qcom,switching-freq - Usage: optional - Value type: - Definition: kHz; switching frequency; one of: 600, 640, 685, 738, - 800, 872, 960, 1066, 1200, 1371, 1600, 1920, 2400, 3200, - 4800, 9600. - Default: for pm8941: 1600 kHz - for pmi8998: 800 kHz - -- qcom,ovp - Usage: optional - Value type: - Definition: V; Over-voltage protection limit; one of: - 27, 29, 32, 35. Default: 29V - This property is supported only for PM8941. - -- qcom,ovp-millivolt - Usage: optional - Value type: - Definition: mV; Over-voltage protection limit; - For pmi8998: one of 18100, 19600, 29600, 31100. - Default 29600 mV. - If this property is not specified for PM8941, it - falls back to "qcom,ovp" property. - -- qcom,num-strings - Usage: optional - Value type: - Definition: #; number of led strings attached; - value: For PM8941 from 1 to 3. Default: 2 - For PMI8998 from 1 to 4. - -- interrupts - Usage: optional - Value type: - Definition: Interrupts associated with WLED. This should be - "short" and "ovp" interrupts. Interrupts can be - specified as per the encoding listed under - Documentation/devicetree/bindings/spmi/ - qcom,spmi-pmic-arb.txt. - -- interrupt-names - Usage: optional - Value type: - Definition: Interrupt names associated with the interrupts. - Must be "short" and "ovp". The short circuit detection - is not supported for PM8941. - -- qcom,enabled-strings - Usage: optional - Value tyoe: - Definition: Array of the WLED strings numbered from 0 to 3. Each - string of leds are operated individually. Specify the - list of strings used by the device. Any combination of - led strings can be used. - -- qcom,external-pfet - Usage: optional - Value type: - Definition: Specify if external PFET control for short circuit - protection is used. This property is supported only - for PMI8998. - -- qcom,auto-string-detection - Usage: optional - Value type: - Definition: Enables auto-detection of the WLED string configuration. - This feature is not supported for PM8941. - - -Example: - -pm8941-wled@d800 { - compatible = "qcom,pm8941-wled"; - reg = <0xd800>; - label = "backlight"; - - qcom,cs-out; - qcom,current-limit = <20>; - qcom,current-boost-limit = <805>; - qcom,switching-freq = <1600>; - qcom,ovp = <29>; - qcom,num-strings = <2>; - qcom,enabled-strings = <0 1>; -}; diff --git a/Bindings/leds/backlight/qcom-wled.yaml b/Bindings/leds/backlight/qcom-wled.yaml new file mode 100644 index 000000000000..32e0896c6bc1 --- /dev/null +++ b/Bindings/leds/backlight/qcom-wled.yaml @@ -0,0 +1,252 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/qcom-wled.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Binding for Qualcomm Technologies, Inc. WLED driver + +maintainers: + - Bjorn Andersson + - Kiran Gunda + +description: | + WLED (White Light Emitting Diode) driver is used for controlling display + backlight that is part of PMIC on Qualcomm Technologies, Inc. reference + platforms. The PMIC is connected to the host processor via SPMI bus. + +properties: + compatible: + enum: + - qcom,pm8941-wled + - qcom,pmi8998-wled + - qcom,pm660l-wled + - qcom,pm8150l-wled + + reg: + maxItems: 1 + + default-brightness: + description: | + brightness value on boot. + + label: true + + max-brightness: + description: | + Maximum brightness level. + + qcom,cs-out: + description: | + enable current sink output. + This property is supported only for WLED3. + type: boolean + + qcom,cabc: + description: | + enable content adaptive backlight control. + type: boolean + + qcom,ext-gen: + description: | + use externally generated modulator signal to dim. + This property is supported only for WLED3. + type: boolean + + qcom,current-limit: + description: | + mA; per-string current limit. + This property is supported only for WLED3. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 20 + minimum: 0 + maximum: 25 + + qcom,current-limit-microamp: + description: | + uA; per-string current limit. + default: 25 + minimum: 0 + maximum: 30000 + multipleOf: 25 + + qcom,current-boost-limit: + description: | + mA; boost current limit. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,switching-freq: + description: | + kHz; switching frequency. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371, 1600, 1920, 2400, 3200, 4800, 9600 ] + + qcom,ovp: + description: | + V; Over-voltage protection limit. + This property is supported only for WLED3. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 27, 29, 32, 35 ] + default: 29 + + qcom,ovp-millivolt: + description: | + Over-voltage protection limit. This property is for WLED4 only. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 18100, 19600, 29600, 31100 ] + default: 29600 + + qcom,num-strings: + description: | + number of led strings attached. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,enabled-strings: + description: | + Array of the WLED strings numbered from 0 to 3. Each + string of leds are operated individually. Specify the + list of strings used by the device. Any combination of + led strings can be used. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + + qcom,external-pfet: + description: | + Specify if external PFET control for short circuit + protection is used. This property is supported only + for WLED4. + type: boolean + + qcom,auto-string-detection: + description: | + Enables auto-detection of the WLED string configuration. + This feature is not supported for WLED3. + type: boolean + + interrupts: + minItems: 1 + items: + - description: over voltage protection interrupt. + - description: short circuit interrupt. + + interrupt-names: + minItems: 1 + items: + - const: ovp + - const: short + + qcom,modulator-sel: + description: | + Selects the modulator used for brightness modulation. + Allowed values are, + 0 - Modulator A + 1 - Modulator B + This property is applicable only to WLED5 peripheral. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + default: 0 + + qcom,cabc-sel: + description: | + Selects the CABC pin signal used for brightness modulation. + Allowed values are, + 0 - CABC disabled + 1 - CABC 1 + 2 - CABC 2 + 3 - External signal (e.g. LPG) is used for dimming + This property is applicable only to WLED5 peripheral. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,pm8941-wled + + then: + properties: + qcom,current-boost-limit: + enum: [ 105, 385, 525, 805, 980, 1260, 1400, 1680 ] + default: 805 + + qcom,switching-freq: + default: 1600 + + qcom,num-strings: + enum: [ 1, 2, 3 ] + + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + + else: + properties: + qcom,current-boost-limit: + enum: [ 105, 280, 450, 620, 970, 1150, 1300, 1500 ] + default: 970 + + qcom,switching-freq: + default: 800 + + qcom,num-strings: + enum: [ 1, 2, 3, 4 ] + + interrupts: + minItems: 2 + + interrupt-names: + minItems: 2 + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8150l-wled + + then: + properties: + default-brightness: + minimum: 0 + maximum: 32767 + + max-brightness: + minimum: 0 + maximum: 32767 + + else: + properties: + default-brightness: + minimum: 0 + maximum: 4095 + + max-brightness: + minimum: 0 + maximum: 4095 + +required: + - compatible + - reg + - label + +additionalProperties: false + +examples: + - | + backlight@d800 { + compatible = "qcom,pm8941-wled"; + reg = <0xd800 0x100>; + label = "backlight"; + + qcom,cs-out; + qcom,current-limit = <20>; + qcom,current-boost-limit = <805>; + qcom,switching-freq = <1600>; + qcom,ovp = <29>; + qcom,num-strings = <2>; + qcom,enabled-strings = <0 1>; + }; diff --git a/Bindings/leds/common.yaml b/Bindings/leds/common.yaml index 4c270fde4567..a2a541bca73c 100644 --- a/Bindings/leds/common.yaml +++ b/Bindings/leds/common.yaml @@ -41,8 +41,7 @@ properties: Color of the LED. Use one of the LED_COLOR_ID_* prefixed definitions from the header include/dt-bindings/leds/common.h. If there is no matching LED_COLOR_ID available, add a new one. - allOf: - - $ref: /schemas/types.yaml#definitions/uint32 + $ref: /schemas/types.yaml#definitions/uint32 minimum: 0 maximum: 8 @@ -67,8 +66,7 @@ properties: produced where the LED momentarily turns off (or on). The "keep" setting will keep the LED at whatever its current state is, without producing a glitch. - allOf: - - $ref: /schemas/types.yaml#definitions/string + $ref: /schemas/types.yaml#definitions/string enum: - on - off @@ -79,8 +77,8 @@ properties: description: This parameter, if present, is a string defining the trigger assigned to the LED. - allOf: - - $ref: /schemas/types.yaml#definitions/string + $ref: /schemas/types.yaml#definitions/string + enum: # LED will act as a back-light, controlled by the framebuffer system - backlight @@ -111,8 +109,7 @@ properties: brightness and duration (in ms). The exact format is described in: Documentation/devicetree/bindings/leds/leds-trigger-pattern.txt - allOf: - - $ref: /schemas/types.yaml#definitions/uint32-matrix + $ref: /schemas/types.yaml#definitions/uint32-matrix items: minItems: 2 maxItems: 2 diff --git a/Bindings/leds/leds-aw2013.yaml b/Bindings/leds/leds-aw2013.yaml new file mode 100644 index 000000000000..e24b0d15ef01 --- /dev/null +++ b/Bindings/leds/leds-aw2013.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/leds-aw2013.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AWINIC AW2013 3-channel LED Driver + +maintainers: + - Nikita Travkin + +description: | + The AW2013 is a 3-channel LED driver with I2C interface. It can control + LED brightness with PWM output. + +properties: + compatible: + const: awinic,aw2013 + + reg: + maxItems: 1 + + vcc-supply: + description: Regulator providing power to the "VCC" pin. + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^led@[0-2]$": + type: object + $ref: common.yaml# + + properties: + reg: + description: Index of the LED. + minimum: 0 + maximum: 2 + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@45 { + compatible = "awinic,aw2013"; + reg = <0x45>; + #address-cells = <1>; + #size-cells = <0>; + + vcc-supply = <&pm8916_l17>; + + led@0 { + reg = <0>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + + led@1 { + reg = <1>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + + led@2 { + reg = <2>; + led-max-microamp = <5000>; + function = LED_FUNCTION_INDICATOR; + color = ; + }; + }; + }; +... diff --git a/Bindings/leds/leds-gpio.yaml b/Bindings/leds/leds-gpio.yaml index 0e75b185dd19..7ad2baeda0b0 100644 --- a/Bindings/leds/leds-gpio.yaml +++ b/Bindings/leds/leds-gpio.yaml @@ -24,8 +24,7 @@ patternProperties: "(^led-[0-9a-f]$|led)": type: object - allOf: - - $ref: common.yaml# + $ref: common.yaml# properties: gpios: diff --git a/Bindings/leds/leds-sgm3140.yaml b/Bindings/leds/leds-sgm3140.yaml new file mode 100644 index 000000000000..f68259619488 --- /dev/null +++ b/Bindings/leds/leds-sgm3140.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/leds-sgm3140.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SGMICRO SGM3140 500mA Buck/Boost Charge Pump LED Driver + +maintainers: + - Luca Weiss + +description: | + The SGM3140 is a current-regulated charge pump which can regulate two current + levels for Flash and Torch modes. + + The data sheet can be found at: + http://www.sg-micro.com/uploads/soft/20190626/1561535688.pdf + +properties: + compatible: + const: sgmicro,sgm3140 + + enable-gpios: + maxItems: 1 + description: A connection to the 'EN' pin. + + flash-gpios: + maxItems: 1 + description: A connection to the 'FLASH' pin. + + vin-supply: + description: Regulator providing power to the 'VIN' pin. + + led: + type: object + $ref: common.yaml# + +required: + - compatible + - flash-gpios + - enable-gpios + +additionalProperties: false + +examples: + - | + #include + #include + + led-controller { + compatible = "sgmicro,sgm3140"; + flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */ + enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */ + vin-supply = <®_dcdc1>; + + sgm3140_flash: led { + function = LED_FUNCTION_FLASH; + color = ; + flash-max-timeout-us = <250000>; + }; + }; diff --git a/Bindings/leds/rohm,bd71828-leds.yaml b/Bindings/leds/rohm,bd71828-leds.yaml index 90edf9d33b33..86a37c92b834 100644 --- a/Bindings/leds/rohm,bd71828-leds.yaml +++ b/Bindings/leds/rohm,bd71828-leds.yaml @@ -34,11 +34,10 @@ patternProperties: #- $ref: "common.yaml#" rohm,led-compatible: description: LED identification string - allOf: - - $ref: "/schemas/types.yaml#/definitions/string" - - enum: - - bd71828-ambled - - bd71828-grnled + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - bd71828-ambled + - bd71828-grnled function: description: Purpose of LED as defined in dt-bindings/leds/common.h diff --git a/Bindings/mailbox/fsl,mu.txt b/Bindings/mailbox/fsl,mu.txt deleted file mode 100644 index 31486c9f6443..000000000000 --- a/Bindings/mailbox/fsl,mu.txt +++ /dev/null @@ -1,58 +0,0 @@ -NXP i.MX Messaging Unit (MU) --------------------------------------------------------------------- - -The Messaging Unit module enables two processors within the SoC to -communicate and coordinate by passing messages (e.g. data, status -and control) through the MU interface. The MU also provides the ability -for one processor to signal the other processor using interrupts. - -Because the MU manages the messaging between processors, the MU uses -different clocks (from each side of the different peripheral buses). -Therefore, the MU must synchronize the accesses from one side to the -other. The MU accomplishes synchronization using two sets of matching -registers (Processor A-facing, Processor B-facing). - -Messaging Unit Device Node: -============================= - -Required properties: -------------------- -- compatible : should be "fsl,-mu", the supported chips include - imx6sx, imx7s, imx8qxp, imx8qm. - The "fsl,imx6sx-mu" compatible is seen as generic and should - be included together with SoC specific compatible. - There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu" - compatible to support it. - To communicate with i.MX8 SCU, "fsl,imx8-mu-scu" could be - used for fast IPC -- reg : Should contain the registers location and length -- interrupts : Interrupt number. The interrupt specifier format depends - on the interrupt controller parent. -- #mbox-cells: Must be 2. - <&phandle type channel> - phandle : Label name of controller - type : Channel type - channel : Channel number - - This MU support 4 type of unidirectional channels, each type - has 4 channels. A total of 16 channels. Following types are - supported: - 0 - TX channel with 32bit transmit register and IRQ transmit - acknowledgment support. - 1 - RX channel with 32bit receive register and IRQ support - 2 - TX doorbell channel. Without own register and no ACK support. - 3 - RX doorbell channel. - -Optional properties: -------------------- -- clocks : phandle to the input clock. -- fsl,mu-side-b : Should be set for side B MU. - -Examples: --------- -lsio_mu0: mailbox@5d1b0000 { - compatible = "fsl,imx8qxp-mu"; - reg = <0x0 0x5d1b0000 0x0 0x10000>; - interrupts = ; - #mbox-cells = <2>; -}; diff --git a/Bindings/mailbox/fsl,mu.yaml b/Bindings/mailbox/fsl,mu.yaml new file mode 100644 index 000000000000..3b35eb5ac3f9 --- /dev/null +++ b/Bindings/mailbox/fsl,mu.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX Messaging Unit (MU) + +maintainers: + - Dong Aisheng + +description: | + The Messaging Unit module enables two processors within the SoC to + communicate and coordinate by passing messages (e.g. data, status + and control) through the MU interface. The MU also provides the ability + for one processor to signal the other processor using interrupts. + + Because the MU manages the messaging between processors, the MU uses + different clocks (from each side of the different peripheral buses). + Therefore, the MU must synchronize the accesses from one side to the + other. The MU accomplishes synchronization using two sets of matching + registers (Processor A-facing, Processor B-facing). + +properties: + compatible: + oneOf: + - const: fsl,imx6sx-mu + - const: fsl,imx7ulp-mu + - const: fsl,imx8-mu-scu + - items: + - enum: + - fsl,imx7s-mu + - fsl,imx8mq-mu + - fsl,imx8mm-mu + - fsl,imx8mn-mu + - fsl,imx8mp-mu + - fsl,imx8qxp-mu + - const: fsl,imx6sx-mu + - description: To communicate with i.MX8 SCU with fast IPC + items: + - const: fsl,imx8qxp-mu + - const: fsl,imx8-mu-scu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#mbox-cells": + description: | + <&phandle type channel> + phandle : Label name of controller + type : Channel type + channel : Channel number + + This MU support 4 type of unidirectional channels, each type + has 4 channels. A total of 16 channels. Following types are + supported: + 0 - TX channel with 32bit transmit register and IRQ transmit + acknowledgment support. + 1 - RX channel with 32bit receive register and IRQ support + 2 - TX doorbell channel. Without own register and no ACK support. + 3 - RX doorbell channel. + const: 2 + + clocks: + maxItems: 1 + + fsl,mu-side-b: + description: boolean, if present, means it is for side B MU. + type: boolean + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + + mailbox@5d1b0000 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + reg = <0x5d1b0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; diff --git a/Bindings/mailbox/qcom,apcs-kpss-global.txt b/Bindings/mailbox/qcom,apcs-kpss-global.txt deleted file mode 100644 index beec612dbe6a..000000000000 --- a/Bindings/mailbox/qcom,apcs-kpss-global.txt +++ /dev/null @@ -1,88 +0,0 @@ -Binding for the Qualcomm APCS global block -========================================== - -This binding describes the APCS "global" block found in various Qualcomm -platforms. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,msm8916-apcs-kpss-global", - "qcom,msm8996-apcs-hmss-global" - "qcom,msm8998-apcs-hmss-global" - "qcom,qcs404-apcs-apps-global" - "qcom,sc7180-apss-shared" - "qcom,sdm845-apss-shared" - "qcom,sm8150-apss-shared" - "qcom,ipq8074-apcs-apps-global" - -- reg: - Usage: required - Value type: - Definition: must specify the base address and size of the global block - -- clocks: - Usage: required if #clock-names property is present - Value type: - Definition: phandles to the two parent clocks of the clock driver. - -- #mbox-cells: - Usage: required - Value type: - Definition: as described in mailbox.txt, must be 1 - -- #clock-cells: - Usage: optional - Value type: - Definition: as described in clock.txt, must be 0 - -- clock-names: - Usage: required if the platform data based clock driver needs to - retrieve the parent clock names from device tree. - This will requires two mandatory clocks to be defined. - Value type: - Definition: must be "pll" and "aux" - -= EXAMPLE -The following example describes the APCS HMSS found in MSM8996 and part of the -GLINK RPM referencing the "rpm_hlos" doorbell therein. - - apcs_glb: mailbox@9820000 { - compatible = "qcom,msm8996-apcs-hmss-global"; - reg = <0x9820000 0x1000>; - - #mbox-cells = <1>; - }; - - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - mboxes = <&apcs_glb 0>; - mbox-names = "rpm_hlos"; - }; - -Below is another example of the APCS binding on MSM8916 platforms: - - apcs: mailbox@b011000 { - compatible = "qcom,msm8916-apcs-kpss-global"; - reg = <0xb011000 0x1000>; - #mbox-cells = <1>; - clocks = <&a53pll>; - #clock-cells = <0>; - }; - -Below is another example of the APCS binding on QCS404 platforms: - - apcs_glb: mailbox@b011000 { - compatible = "qcom,qcs404-apcs-apps-global", "syscon"; - reg = <0x0b011000 0x1000>; - #mbox-cells = <1>; - clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; - clock-names = "pll", "aux"; - #clock-cells = <0>; - }; diff --git a/Bindings/mailbox/qcom,apcs-kpss-global.yaml b/Bindings/mailbox/qcom,apcs-kpss-global.yaml new file mode 100644 index 000000000000..12eff942708d --- /dev/null +++ b/Bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm APCS global block bindings + +description: + This binding describes the APCS "global" block found in various Qualcomm + platforms. + +maintainers: + - Sivaprakash Murugesan + +properties: + compatible: + enum: + - qcom,ipq8074-apcs-apps-global + - qcom,msm8916-apcs-kpss-global + - qcom,msm8996-apcs-hmss-global + - qcom,msm8998-apcs-hmss-global + - qcom,qcs404-apcs-apps-global + - qcom,sc7180-apss-shared + - qcom,sdm845-apss-shared + - qcom,sm8150-apss-shared + + reg: + maxItems: 1 + + clocks: + description: phandles to the parent clocks of the clock driver + items: + - description: primary pll parent of the clock driver + - description: auxiliary parent + + '#mbox-cells': + const: 1 + + '#clock-cells': + const: 0 + + clock-names: + items: + - const: pll + - const: aux + +required: + - compatible + - reg + - '#mbox-cells' + +additionalProperties: false + +examples: + + # Example apcs with msm8996 + - | + #include + apcs_glb: mailbox@9820000 { + compatible = "qcom,msm8996-apcs-hmss-global"; + reg = <0x9820000 0x1000>; + + #mbox-cells = <1>; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + mbox-names = "rpm_hlos"; + }; + + # Example apcs with qcs404 + - | + #define GCC_APSS_AHB_CLK_SRC 1 + #define GCC_GPLL0_AO_OUT_MAIN 123 + apcs: mailbox@b011000 { + compatible = "qcom,qcs404-apcs-apps-global"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; + clock-names = "pll", "aux"; + #clock-cells = <0>; + }; diff --git a/Bindings/mailbox/qcom-ipcc.yaml b/Bindings/mailbox/qcom-ipcc.yaml new file mode 100644 index 000000000000..4ac2123d9193 --- /dev/null +++ b/Bindings/mailbox/qcom-ipcc.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller + +maintainers: + - Manivannan Sadhasivam + +description: + The Inter-Processor Communication Controller (IPCC) is a centralized hardware + to route interrupts across various subsystems. It involves a three-level + addressing scheme called protocol, client and signal. For example, consider an + entity on the Application Processor Subsystem (APSS) that wants to listen to + Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such + a case, the client would be Modem (client-id is 2) and the signal would be + SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC) + protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h + for the list of such IDs. + +properties: + compatible: + items: + - enum: + - qcom,sm8250-ipcc + - const: qcom,ipcc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 3 + description: + The first cell is the client-id, the second cell is the signal-id and the + third cell is the interrupt type. + + "#mbox-cells": + const: 2 + description: + The first cell is the client-id, and the second cell is the signal-id. + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + mailbox@408000 { + compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; + reg = <0x408000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + interrupts-extended = <&ipcc_mproc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; + + /* Other SMP2P fields */ + }; diff --git a/Bindings/mailbox/sprd-mailbox.yaml b/Bindings/mailbox/sprd-mailbox.yaml new file mode 100644 index 000000000000..26a5cca3f838 --- /dev/null +++ b/Bindings/mailbox/sprd-mailbox.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mailbox/sprd-mailbox.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Spreadtrum mailbox controller bindings + +maintainers: + - Orson Zhai + - Baolin Wang + - Chunyan Zhang + +properties: + compatible: + enum: + - sprd,sc9860-mailbox + + reg: + items: + - description: inbox registers' base address + - description: outbox registers' base address + + interrupts: + items: + - description: inbox interrupt + - description: outbox interrupt + + clocks: + maxItems: 1 + + clock-names: + items: + - const: enable + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + mailbox: mailbox@400a0000 { + compatible = "sprd,sc9860-mailbox"; + reg = <0x400a0000 0x8000>, <0x400a8000 0x8000>; + #mbox-cells = <1>; + clock-names = "enable"; + clocks = <&aon_gate 53>; + interrupts = , ; + }; +... diff --git a/Bindings/mailbox/st,stm32-ipcc.yaml b/Bindings/mailbox/st,stm32-ipcc.yaml index 5b13d6672996..3b7ab61a144f 100644 --- a/Bindings/mailbox/st,stm32-ipcc.yaml +++ b/Bindings/mailbox/st,stm32-ipcc.yaml @@ -24,7 +24,7 @@ properties: maxItems: 1 clocks: - maxItems: 1 + maxItems: 1 interrupts: items: @@ -49,9 +49,8 @@ properties: st,proc-id: description: Processor id using the mailbox (0 or 1) - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 0, 1 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] required: - compatible diff --git a/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt b/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt index 4438432bfe9b..ad76edccf881 100644 --- a/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt +++ b/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt @@ -87,7 +87,7 @@ Example: ranges; /* APU<->RPU0 IPI mailbox controller */ - ipi_mailbox_rpu0: mailbox@ff90400 { + ipi_mailbox_rpu0: mailbox@ff990400 { reg = <0xff990400 0x20>, <0xff990420 0x20>, <0xff990080 0x20>, diff --git a/Bindings/media/allwinner,sun4i-a10-csi.yaml b/Bindings/media/allwinner,sun4i-a10-csi.yaml index 8453ee340b9f..09318830db47 100644 --- a/Bindings/media/allwinner,sun4i-a10-csi.yaml +++ b/Bindings/media/allwinner,sun4i-a10-csi.yaml @@ -20,11 +20,11 @@ properties: - const: allwinner,sun4i-a10-csi1 - const: allwinner,sun7i-a20-csi0 - items: - - const: allwinner,sun7i-a20-csi1 - - const: allwinner,sun4i-a10-csi1 + - const: allwinner,sun7i-a20-csi1 + - const: allwinner,sun4i-a10-csi1 - items: - - const: allwinner,sun8i-r40-csi0 - - const: allwinner,sun7i-a20-csi0 + - const: allwinner,sun8i-r40-csi0 + - const: allwinner,sun7i-a20-csi0 reg: maxItems: 1 @@ -35,24 +35,24 @@ properties: clocks: oneOf: - items: - - description: The CSI interface clock - - description: The CSI DRAM clock + - description: The CSI interface clock + - description: The CSI DRAM clock - items: - - description: The CSI interface clock - - description: The CSI ISP clock - - description: The CSI DRAM clock + - description: The CSI interface clock + - description: The CSI ISP clock + - description: The CSI DRAM clock clock-names: oneOf: - items: - - const: bus - - const: ram + - const: bus + - const: ram - items: - - const: bus - - const: isp - - const: ram + - const: bus + - const: isp + - const: ram resets: maxItems: 1 diff --git a/Bindings/media/allwinner,sun4i-a10-video-engine.yaml b/Bindings/media/allwinner,sun4i-a10-video-engine.yaml index 526593c8c614..4cc1a670c986 100644 --- a/Bindings/media/allwinner,sun4i-a10-video-engine.yaml +++ b/Bindings/media/allwinner,sun4i-a10-video-engine.yaml @@ -47,6 +47,9 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array description: Phandle to the device SRAM + iommus: + maxItems: 1 + memory-region: description: CMA pool to use for buffers allocation instead of the default diff --git a/Bindings/media/amlogic,gx-vdec.yaml b/Bindings/media/amlogic,gx-vdec.yaml index 37d77e065491..b902495d278b 100644 --- a/Bindings/media/amlogic,gx-vdec.yaml +++ b/Bindings/media/amlogic,gx-vdec.yaml @@ -29,14 +29,14 @@ properties: compatible: oneOf: - items: - - enum: - - amlogic,gxbb-vdec # GXBB (S905) - - amlogic,gxl-vdec # GXL (S905X, S905D) - - amlogic,gxm-vdec # GXM (S912) - - const: amlogic,gx-vdec + - enum: + - amlogic,gxbb-vdec # GXBB (S905) + - amlogic,gxl-vdec # GXL (S905X, S905D) + - amlogic,gxm-vdec # GXM (S912) + - const: amlogic,gx-vdec - enum: - - amlogic,g12a-vdec # G12A (S905X2, S905D2) - - amlogic,sm1-vdec # SM1 (S905X3, S905D3) + - amlogic,g12a-vdec # G12A (S905X2, S905D2) + - amlogic,sm1-vdec # SM1 (S905X3, S905D3) interrupts: minItems: 2 @@ -77,13 +77,11 @@ properties: amlogic,ao-sysctrl: description: should point to the AOBUS sysctrl node - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle amlogic,canvas: description: should point to a canvas provider node - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle allOf: - if: diff --git a/Bindings/media/amlogic,meson-gx-ao-cec.yaml b/Bindings/media/amlogic,meson-gx-ao-cec.yaml index 95ffa8bc0533..d93aea6a0258 100644 --- a/Bindings/media/amlogic,meson-gx-ao-cec.yaml +++ b/Bindings/media/amlogic,meson-gx-ao-cec.yaml @@ -35,8 +35,7 @@ properties: hdmi-phandle: description: phandle to the HDMI controller - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle allOf: - if: @@ -88,7 +87,7 @@ examples: - | cec_AO: cec@100 { compatible = "amlogic,meson-gx-ao-cec"; - reg = <0x0 0x00100 0x0 0x14>; + reg = <0x00100 0x14>; interrupts = <199>; clocks = <&clkc_cec>; clock-names = "core"; diff --git a/Bindings/media/i2c/imx219.yaml b/Bindings/media/i2c/imx219.yaml index 32d6b693274f..dfc4d29a4f04 100644 --- a/Bindings/media/i2c/imx219.yaml +++ b/Bindings/media/i2c/imx219.yaml @@ -67,8 +67,7 @@ properties: otherwise it's continuous. link-frequencies: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint64-array + $ref: /schemas/types.yaml#/definitions/uint64-array description: Allowed data bus frequencies. diff --git a/Bindings/media/i2c/ov8856.yaml b/Bindings/media/i2c/ov8856.yaml new file mode 100644 index 000000000000..1956b2a32bf4 --- /dev/null +++ b/Bindings/media/i2c/ov8856.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2019 MediaTek Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ov8856.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Omnivision OV8856 CMOS Sensor Device Tree Bindings + +maintainers: + - Dongchun Zhu + +description: |- + The Omnivision OV8856 is a high performance, 1/4-inch, 8 megapixel, CMOS + image sensor that delivers 3264x2448 at 30fps. It provides full-frame, + sub-sampled, and windowed 10-bit MIPI images in various formats via the + Serial Camera Control Bus (SCCB) interface. This chip is programmable + through I2C and two-wire SCCB. The sensor output is available via CSI-2 + serial data output (up to 4-lane). + +properties: + compatible: + const: ovti,ov8856 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + description: + Input clock for the sensor. + items: + - const: xvclk + + clock-frequency: + description: + Frequency of the xvclk clock in Hertz. + + dovdd-supply: + description: + Definition of the regulator used as interface power supply. + + avdd-supply: + description: + Definition of the regulator used as analog power supply. + + dvdd-supply: + description: + Definition of the regulator used as digital power supply. + + reset-gpios: + description: + The phandle and specifier for the GPIO that controls sensor reset. + This corresponds to the hardware pin XSHUTDOWN which is physically + active low. + + port: + type: object + additionalProperties: false + description: + A node containing an output port node with an endpoint definition + as documented in + Documentation/devicetree/bindings/media/video-interfaces.txt + + properties: + endpoint: + type: object + + properties: + data-lanes: + description: |- + The driver only supports four-lane operation. + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + link-frequencies: + $ref: /schemas/types.yaml#/definitions/uint64-array + description: + Allowed data bus frequencies. 360000000, 180000000 Hz or both + are supported by the driver. + + + required: + - link-frequencies + + required: + - endpoint + +required: + - compatible + - reg + - clocks + - clock-names + - clock-frequency + - dovdd-supply + - avdd-supply + - dvdd-supply + - reset-gpios + - port + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ov8856: camera@10 { + compatible = "ovti,ov8856"; + reg = <0x10>; + + reset-gpios = <&pio 111 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&clk_24m_cam>; + + clocks = <&cam_osc>; + clock-names = "xvclk"; + clock-frequency = <19200000>; + + avdd-supply = <&mt6358_vcama2_reg>; + dvdd-supply = <&mt6358_vcamd_reg>; + dovdd-supply = <&mt6358_vcamio_reg>; + + port { + wcam_out: endpoint { + remote-endpoint = <&mipi_in_wcam>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <360000000>; + }; + }; + }; + }; +... \ No newline at end of file diff --git a/Bindings/media/marvell,mmp2-ccic.txt b/Bindings/media/marvell,mmp2-ccic.txt deleted file mode 100644 index 7ec2c8c8a3b9..000000000000 --- a/Bindings/media/marvell,mmp2-ccic.txt +++ /dev/null @@ -1,50 +0,0 @@ -Marvell MMP2 camera host interface - -Required properties: - - compatible: Should be "marvell,mmp2-ccic". - - reg: Register base and size. - - interrupts: The interrupt number. - - #clock-cells: Must be 0. - -Optional properties: - - clocks: Reference to the input clock as specified by - Documentation/devicetree/bindings/clock/clock-bindings.txt. - - clock-names: Names of the clocks used; "axi" for the AXI bus interface, - "func" for the peripheral clock and "phy" for the parallel - video bus interface. - - clock-output-names: Optional clock source for sensors. Shall be "mclk". - -Required subnodes: - - port: The parallel bus interface port with a single endpoint linked to - the sensor's endpoint as described in - Documentation/devicetree/bindings/media/video-interfaces.txt. - -Required endpoint properties: - - bus-type: data bus type, <5> or <6> for Parallel or Bt.656 respectively - - pclk-sample: pixel clock polarity - - hsync-active: horizontal synchronization polarity (only required for - parallel bus) - - vsync-active: vertical synchronization polarity (only required for - parallel bus) - -Example: - - camera0: camera@d420a000 { - compatible = "marvell,mmp2-ccic"; - reg = <0xd420a000 0x800>; - interrupts = <42>; - clocks = <&soc_clocks MMP2_CLK_CCIC0>; - clock-names = "axi"; - #clock-cells = <0>; - clock-output-names = "mclk"; - - port { - camera0_0: endpoint { - remote-endpoint = <&ov7670_0>; - bus-type = <5>; /* Parallel */ - hsync-active = <1>; /* Active high */ - vsync-active = <1>; /* Active high */ - pclk-sample = <0>; /* Falling */ - }; - }; - }; diff --git a/Bindings/media/marvell,mmp2-ccic.yaml b/Bindings/media/marvell,mmp2-ccic.yaml new file mode 100644 index 000000000000..49bff738aca5 --- /dev/null +++ b/Bindings/media/marvell,mmp2-ccic.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2019,2020 Lubomir Rintel +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MMP2 camera host interface bindings + +maintainers: + - Lubomir Rintel + +properties: + $nodename: + pattern: '^camera@[a-f0-9]+$' + + compatible: + const: marvell,mmp2-ccic + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + port: + type: object + additionalProperties: false + + properties: + endpoint: + type: object + additionalProperties: false + + # Properties described in + # Documentation/devicetree/bindings/media/video-interfaces.txt + properties: + remote-endpoint: true + hsync-active: true + vsync-active: true + pclk-sample: true + bus-type: true + + required: + - remote-endpoint + + required: + - endpoint + + clocks: + minItems: 1 + maxItems: 3 + items: + - description: AXI bus interface clock + - description: Peripheral clock + - description: Parallel video bus interface clock + + clock-names: + const: axi + + '#clock-cells': + const: 0 + + clock-output-names: + const: mclk + +required: + - compatible + - reg + - interrupts + - port + +additionalProperties: false + +examples: + - | + #include + + camera@d420a000 { + compatible = "marvell,mmp2-ccic"; + reg = <0xd420a000 0x800>; + interrupts = <42>; + clocks = <&soc_clocks MMP2_CLK_CCIC0>; + clock-names = "axi"; + #clock-cells = <0>; + clock-output-names = "mclk"; + + port { + camera0_0: endpoint { + remote-endpoint = <&ov7670_0>; + bus-type = <5>; /* Parallel */ + hsync-active = <1>; /* Active high */ + vsync-active = <1>; /* Active high */ + pclk-sample = <0>; /* Falling */ + }; + }; + }; + +... diff --git a/Bindings/media/qcom,sc7180-venus.yaml b/Bindings/media/qcom,sc7180-venus.yaml index 764affa4877e..55f2d67ae34e 100644 --- a/Bindings/media/qcom,sc7180-venus.yaml +++ b/Bindings/media/qcom,sc7180-venus.yaml @@ -115,7 +115,7 @@ examples: venus: video-codec@aa00000 { compatible = "qcom,sc7180-venus"; - reg = <0 0x0aa00000 0 0xff000>; + reg = <0x0aa00000 0xff000>; interrupts = ; power-domains = <&videocc VENUS_GDSC>, <&videocc VCODEC0_GDSC>; diff --git a/Bindings/media/qcom,sdm845-venus-v2.yaml b/Bindings/media/qcom,sdm845-venus-v2.yaml index 8552f4ab907e..157dff8057e9 100644 --- a/Bindings/media/qcom,sdm845-venus-v2.yaml +++ b/Bindings/media/qcom,sdm845-venus-v2.yaml @@ -110,7 +110,7 @@ examples: video-codec@aa00000 { compatible = "qcom,sdm845-venus-v2"; - reg = <0 0x0aa00000 0 0xff000>; + reg = <0x0aa00000 0xff000>; interrupts = ; clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, <&videocc VIDEO_CC_VENUS_AHB_CLK>, diff --git a/Bindings/media/qcom,sdm845-venus.yaml b/Bindings/media/qcom,sdm845-venus.yaml index 05cabe4e893a..084e45e2df62 100644 --- a/Bindings/media/qcom,sdm845-venus.yaml +++ b/Bindings/media/qcom,sdm845-venus.yaml @@ -127,7 +127,7 @@ examples: video-codec@aa00000 { compatible = "qcom,sdm845-venus"; - reg = <0 0x0aa00000 0 0xff000>; + reg = <0x0aa00000 0xff000>; interrupts = ; clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, <&videocc VIDEO_CC_VENUS_AHB_CLK>, diff --git a/Bindings/media/rc.yaml b/Bindings/media/rc.yaml index b27c9385d490..ded2ac43237d 100644 --- a/Bindings/media/rc.yaml +++ b/Bindings/media/rc.yaml @@ -18,136 +18,135 @@ properties: description: Specifies the scancode/key mapping table defined in-kernel for the remote controller. - allOf: - - $ref: '/schemas/types.yaml#/definitions/string' - - enum: - - rc-adstech-dvb-t-pci - - rc-alink-dtu-m - - rc-anysee - - rc-apac-viewcomp - - rc-astrometa-t2hybrid - - rc-asus-pc39 - - rc-asus-ps3-100 - - rc-ati-tv-wonder-hd-600 - - rc-ati-x10 - - rc-avermedia - - rc-avermedia-a16d - - rc-avermedia-cardbus - - rc-avermedia-dvbt - - rc-avermedia-m135a - - rc-avermedia-m733a-rm-k6 - - rc-avermedia-rm-ks - - rc-avertv-303 - - rc-azurewave-ad-tu700 - - rc-beelink-gs1 - - rc-behold - - rc-behold-columbus - - rc-budget-ci-old - - rc-cec - - rc-cinergy - - rc-cinergy-1400 - - rc-d680-dmb - - rc-delock-61959 - - rc-dib0700-nec - - rc-dib0700-rc5 - - rc-digitalnow-tinytwin - - rc-digittrade - - rc-dm1105-nec - - rc-dntv-live-dvb-t - - rc-dntv-live-dvbt-pro - - rc-dtt200u - - rc-dvbsky - - rc-dvico-mce - - rc-dvico-portable - - rc-em-terratec - - rc-empty - - rc-encore-enltv - - rc-encore-enltv-fm53 - - rc-encore-enltv2 - - rc-evga-indtube - - rc-eztv - - rc-flydvb - - rc-flyvideo - - rc-fusionhdtv-mce - - rc-gadmei-rm008z - - rc-geekbox - - rc-genius-tvgo-a11mce - - rc-gotview7135 - - rc-hauppauge - - rc-hisi-poplar - - rc-hisi-tv-demo - - rc-imon-mce - - rc-imon-pad - - rc-imon-rsc - - rc-iodata-bctv7e - - rc-it913x-v1 - - rc-it913x-v2 - - rc-kaiomy - - rc-khadas - - rc-kworld-315u - - rc-kworld-pc150u - - rc-kworld-plus-tv-analog - - rc-leadtek-y04g0051 - - rc-lme2510 - - rc-manli - - rc-medion-x10 - - rc-medion-x10-digitainer - - rc-medion-x10-or2x - - rc-msi-digivox-ii - - rc-msi-digivox-iii - - rc-msi-tvanywhere - - rc-msi-tvanywhere-plus - - rc-nebula - - rc-nec-terratec-cinergy-xs - - rc-norwood - - rc-npgtech - - rc-odroid - - rc-pctv-sedna - - rc-pinnacle-color - - rc-pinnacle-grey - - rc-pinnacle-pctv-hd - - rc-pixelview - - rc-pixelview-002t - - rc-pixelview-mk12 - - rc-pixelview-new - - rc-powercolor-real-angel - - rc-proteus-2309 - - rc-purpletv - - rc-pv951 - - rc-rc5-tv - - rc-rc6-mce - - rc-real-audio-220-32-keys - - rc-reddo - - rc-snapstream-firefly - - rc-streamzap - - rc-su3000 - - rc-tango - - rc-tanix-tx3mini - - rc-tanix-tx5max - - rc-tbs-nec - - rc-technisat-ts35 - - rc-technisat-usb2 - - rc-terratec-cinergy-c-pci - - rc-terratec-cinergy-s2-hd - - rc-terratec-cinergy-xs - - rc-terratec-slim - - rc-terratec-slim-2 - - rc-tevii-nec - - rc-tivo - - rc-total-media-in-hand - - rc-total-media-in-hand-02 - - rc-trekstor - - rc-tt-1500 - - rc-twinhan-dtv-cab-ci - - rc-twinhan1027 - - rc-videomate-k100 - - rc-videomate-s350 - - rc-videomate-tv-pvr - - rc-videostrong-kii-pro - - rc-wetek-hub - - rc-wetek-play2 - - rc-winfast - - rc-winfast-usbii-deluxe - - rc-x96max - - rc-xbox-dvd - - rc-zx-irdec + $ref: '/schemas/types.yaml#/definitions/string' + enum: + - rc-adstech-dvb-t-pci + - rc-alink-dtu-m + - rc-anysee + - rc-apac-viewcomp + - rc-astrometa-t2hybrid + - rc-asus-pc39 + - rc-asus-ps3-100 + - rc-ati-tv-wonder-hd-600 + - rc-ati-x10 + - rc-avermedia + - rc-avermedia-a16d + - rc-avermedia-cardbus + - rc-avermedia-dvbt + - rc-avermedia-m135a + - rc-avermedia-m733a-rm-k6 + - rc-avermedia-rm-ks + - rc-avertv-303 + - rc-azurewave-ad-tu700 + - rc-beelink-gs1 + - rc-behold + - rc-behold-columbus + - rc-budget-ci-old + - rc-cec + - rc-cinergy + - rc-cinergy-1400 + - rc-d680-dmb + - rc-delock-61959 + - rc-dib0700-nec + - rc-dib0700-rc5 + - rc-digitalnow-tinytwin + - rc-digittrade + - rc-dm1105-nec + - rc-dntv-live-dvb-t + - rc-dntv-live-dvbt-pro + - rc-dtt200u + - rc-dvbsky + - rc-dvico-mce + - rc-dvico-portable + - rc-em-terratec + - rc-empty + - rc-encore-enltv + - rc-encore-enltv-fm53 + - rc-encore-enltv2 + - rc-evga-indtube + - rc-eztv + - rc-flydvb + - rc-flyvideo + - rc-fusionhdtv-mce + - rc-gadmei-rm008z + - rc-geekbox + - rc-genius-tvgo-a11mce + - rc-gotview7135 + - rc-hauppauge + - rc-hisi-poplar + - rc-hisi-tv-demo + - rc-imon-mce + - rc-imon-pad + - rc-imon-rsc + - rc-iodata-bctv7e + - rc-it913x-v1 + - rc-it913x-v2 + - rc-kaiomy + - rc-khadas + - rc-kworld-315u + - rc-kworld-pc150u + - rc-kworld-plus-tv-analog + - rc-leadtek-y04g0051 + - rc-lme2510 + - rc-manli + - rc-medion-x10 + - rc-medion-x10-digitainer + - rc-medion-x10-or2x + - rc-msi-digivox-ii + - rc-msi-digivox-iii + - rc-msi-tvanywhere + - rc-msi-tvanywhere-plus + - rc-nebula + - rc-nec-terratec-cinergy-xs + - rc-norwood + - rc-npgtech + - rc-odroid + - rc-pctv-sedna + - rc-pinnacle-color + - rc-pinnacle-grey + - rc-pinnacle-pctv-hd + - rc-pixelview + - rc-pixelview-002t + - rc-pixelview-mk12 + - rc-pixelview-new + - rc-powercolor-real-angel + - rc-proteus-2309 + - rc-purpletv + - rc-pv951 + - rc-rc5-tv + - rc-rc6-mce + - rc-real-audio-220-32-keys + - rc-reddo + - rc-snapstream-firefly + - rc-streamzap + - rc-su3000 + - rc-tango + - rc-tanix-tx3mini + - rc-tanix-tx5max + - rc-tbs-nec + - rc-technisat-ts35 + - rc-technisat-usb2 + - rc-terratec-cinergy-c-pci + - rc-terratec-cinergy-s2-hd + - rc-terratec-cinergy-xs + - rc-terratec-slim + - rc-terratec-slim-2 + - rc-tevii-nec + - rc-tivo + - rc-total-media-in-hand + - rc-total-media-in-hand-02 + - rc-trekstor + - rc-tt-1500 + - rc-twinhan-dtv-cab-ci + - rc-twinhan1027 + - rc-videomate-k100 + - rc-videomate-s350 + - rc-videomate-tv-pvr + - rc-videostrong-kii-pro + - rc-wetek-hub + - rc-wetek-play2 + - rc-winfast + - rc-winfast-usbii-deluxe + - rc-x96max + - rc-xbox-dvd + - rc-zx-irdec diff --git a/Bindings/media/renesas,ceu.yaml b/Bindings/media/renesas,ceu.yaml index fcb5f13704a5..c7e1e4fe67e6 100644 --- a/Bindings/media/renesas,ceu.yaml +++ b/Bindings/media/renesas,ceu.yaml @@ -27,28 +27,34 @@ properties: interrupts: maxItems: 1 + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + port: type: object additionalProperties: false properties: - endpoint: - type: object - additionalProperties: false + endpoint: + type: object + additionalProperties: false # Properties described in # Documentation/devicetree/bindings/media/video-interfaces.txt - properties: - remote-endpoint: true - hsync-active: true - vsync-active: true - field-even-active: false - bus-width: - enum: [8, 16] - default: 8 + properties: + remote-endpoint: true + hsync-active: true + vsync-active: true + field-even-active: false + bus-width: + enum: [8, 16] + default: 8 - required: - - remote-endpoint + required: + - remote-endpoint required: - endpoint @@ -57,6 +63,8 @@ required: - compatible - reg - interrupts + - clocks + - power-domains - port additionalProperties: false @@ -64,11 +72,14 @@ additionalProperties: false examples: - | #include + #include ceu: ceu@e8210000 { reg = <0xe8210000 0x209c>; compatible = "renesas,r7s72100-ceu"; interrupts = ; + clocks = <&mstp6_clks R7S72100_CLK_CEU>; + power-domains = <&cpg_clocks>; port { ceu_in: endpoint { diff --git a/Bindings/media/renesas,csi2.yaml b/Bindings/media/renesas,csi2.yaml index 408442a0c389..c9e068231d4b 100644 --- a/Bindings/media/renesas,csi2.yaml +++ b/Bindings/media/renesas,csi2.yaml @@ -135,7 +135,7 @@ examples: csi20: csi2@fea80000 { compatible = "renesas,r8a7796-csi2"; - reg = <0 0xfea80000 0 0x10000>; + reg = <0xfea80000 0x10000>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 714>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; diff --git a/Bindings/media/renesas,vin.yaml b/Bindings/media/renesas,vin.yaml index 1ec947b4781f..53c0a7238bac 100644 --- a/Bindings/media/renesas,vin.yaml +++ b/Bindings/media/renesas,vin.yaml @@ -116,10 +116,9 @@ properties: #The per-board settings for Gen3 and RZ/G2 platforms: renesas,id: description: VIN channel number - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - - maximum: 15 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 ports: type: object @@ -261,13 +260,13 @@ properties: anyOf: - required: - - endpoint@0 + - endpoint@0 - required: - - endpoint@1 + - endpoint@1 - required: - - endpoint@2 + - endpoint@2 - required: - - endpoint@3 + - endpoint@3 additionalProperties: false @@ -307,7 +306,7 @@ examples: vin1: vin@e6ef1000 { compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; - reg = <0 0xe6ef1000 0 0x1000>; + reg = <0xe6ef1000 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; @@ -329,7 +328,7 @@ examples: vin0: video@e6ef0000 { compatible = "renesas,vin-r8a7795"; - reg = <0 0xe6ef0000 0 0x1000>; + reg = <0xe6ef0000 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -366,7 +365,7 @@ examples: vin2: video@e6ef2000 { compatible = "renesas,vin-r8a77970"; - reg = <0 0xe6ef2000 0 0x1000>; + reg = <0xe6ef2000 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; diff --git a/Bindings/media/rockchip,vdec.yaml b/Bindings/media/rockchip,vdec.yaml new file mode 100644 index 000000000000..8d35c327018b --- /dev/null +++ b/Bindings/media/rockchip,vdec.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip,vdec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Video Decoder (VDec) Device Tree Bindings + +maintainers: + - Heiko Stuebner + +description: |- + The Rockchip rk3399 has a stateless Video Decoder that can decodes H.264, + HEVC an VP9 streams. + +properties: + compatible: + const: rockchip,rk3399-vdec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: The Video Decoder AXI interface clock + - description: The Video Decoder AHB interface clock + - description: The Video Decoded CABAC clock + - description: The Video Decoder core clock + + clock-names: + items: + - const: axi + - const: ahb + - const: cabac + - const: core + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + + vdec: video-codec@ff660000 { + compatible = "rockchip,rk3399-vdec"; + reg = <0xff660000 0x400>; + interrupts = ; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, + <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + power-domains = <&power RK3399_PD_VDU>; + iommus = <&vdec_mmu>; + }; + +... diff --git a/Bindings/media/rockchip-rga.txt b/Bindings/media/rockchip-rga.txt deleted file mode 100644 index c53a8e5133f6..000000000000 --- a/Bindings/media/rockchip-rga.txt +++ /dev/null @@ -1,34 +0,0 @@ -device-tree bindings for rockchip 2D raster graphic acceleration controller (RGA) - -RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D -graphics operations, such as point/line drawing, image scaling, rotation, -BitBLT, alpha blending and image blur/sharpness. - -Required properties: -- compatible: value should be one of the following - "rockchip,rk3228-rga", "rockchip,rk3288-rga": for Rockchip RK3228 - "rockchip,rk3288-rga": for Rockchip RK3288 - "rockchip,rk3399-rga": for Rockchip RK3399 - -- interrupts: RGA interrupt specifier. - -- clocks: phandle to RGA sclk/hclk/aclk clocks - -- clock-names: should be "aclk", "hclk" and "sclk" - -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: should be "core", "axi" and "ahb" - -Example: -SoC-specific DT entry: - rga: rga@ff680000 { - compatible = "rockchip,rk3399-rga"; - reg = <0xff680000 0x10000>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; - clock-names = "aclk", "hclk", "sclk"; - - resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; - reset-names = "core, "axi", "ahb"; - }; diff --git a/Bindings/media/rockchip-rga.yaml b/Bindings/media/rockchip-rga.yaml new file mode 100644 index 000000000000..dd645ddccb07 --- /dev/null +++ b/Bindings/media/rockchip-rga.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/rockchip-rga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip 2D raster graphic acceleration controller (RGA) + +description: + RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D + graphics operations, such as point/line drawing, image scaling, rotation, + BitBLT, alpha blending and image blur/sharpness. + +maintainers: + - Jacob Chen + - Ezequiel Garcia + +properties: + compatible: + oneOf: + - const: rockchip,rk3288-rga + - const: rockchip,rk3399-rga + - items: + - const: rockchip,rk3228-rga + - const: rockchip,rk3288-rga + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: aclk + - const: hclk + - const: sclk + + power-domains: + maxItems: 1 + + resets: + maxItems: 3 + + reset-names: + items: + - const: core + - const: axi + - const: ahb + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + rga: rga@ff680000 { + compatible = "rockchip,rk3399-rga"; + reg = <0xff680000 0x10000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru SCLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + power-domains = <&power RK3399_PD_RGA>; + resets = <&cru SRST_RGA_CORE>, + <&cru SRST_A_RGA>, + <&cru SRST_H_RGA>; + reset-names = "core", "axi", "ahb"; + }; diff --git a/Bindings/media/rockchip-vpu.txt b/Bindings/media/rockchip-vpu.txt deleted file mode 100644 index 339252d9c515..000000000000 --- a/Bindings/media/rockchip-vpu.txt +++ /dev/null @@ -1,43 +0,0 @@ -device-tree bindings for rockchip VPU codec - -Rockchip (Video Processing Unit) present in various Rockchip platforms, -such as RK3288, RK3328 and RK3399. - -Required properties: -- compatible: value should be one of the following - "rockchip,rk3288-vpu"; - "rockchip,rk3328-vpu"; - "rockchip,rk3399-vpu"; -- interrupts: encoding and decoding interrupt specifiers -- interrupt-names: should be - "vepu", "vdpu" on RK3288 and RK3399, - "vdpu" on RK3328. -- clocks: phandle to VPU aclk, hclk clocks -- clock-names: should be "aclk" and "hclk" -- power-domains: phandle to power domain node -- iommus: phandle to a iommu node - -Example: -SoC-specific DT entry: - vpu: video-codec@ff9a0000 { - compatible = "rockchip,rk3288-vpu"; - reg = <0x0 0xff9a0000 0x0 0x800>; - interrupts = , - ; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "hclk"; - power-domains = <&power RK3288_PD_VIDEO>; - iommus = <&vpu_mmu>; - }; - - vpu: video-codec@ff350000 { - compatible = "rockchip,rk3328-vpu"; - reg = <0x0 0xff350000 0x0 0x800>; - interrupts = ; - interrupt-names = "vdpu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "hclk"; - power-domains = <&power RK3328_PD_VPU>; - iommus = <&vpu_mmu>; - }; diff --git a/Bindings/media/rockchip-vpu.yaml b/Bindings/media/rockchip-vpu.yaml new file mode 100644 index 000000000000..2b629456d75f --- /dev/null +++ b/Bindings/media/rockchip-vpu.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/media/rockchip-vpu.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Hantro G1 VPU codecs implemented on Rockchip SoCs + +maintainers: + - Ezequiel Garcia + +description: + Hantro G1 video encode and decode accelerators present on Rockchip SoCs. + +properties: + compatible: + enum: + - rockchip,rk3288-vpu + - rockchip,rk3328-vpu + - rockchip,rk3399-vpu + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + oneOf: + - const: vdpu + - items: + - const: vepu + - const: vdpu + + clocks: + maxItems: 2 + + clock-names: + items: + - const: aclk + - const: hclk + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + vpu: video-codec@ff9a0000 { + compatible = "rockchip,rk3288-vpu"; + reg = <0xff9a0000 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3288_PD_VIDEO>; + iommus = <&vpu_mmu>; + }; diff --git a/Bindings/media/ti,vpe.yaml b/Bindings/media/ti,vpe.yaml index f3a8a350e85f..ef473f287399 100644 --- a/Bindings/media/ti,vpe.yaml +++ b/Bindings/media/ti,vpe.yaml @@ -17,7 +17,7 @@ description: |- properties: compatible: - const: ti,dra7-vpe + const: ti,dra7-vpe reg: items: diff --git a/Bindings/media/video-interfaces.txt b/Bindings/media/video-interfaces.txt index f884ada0bffc..3920f25a9123 100644 --- a/Bindings/media/video-interfaces.txt +++ b/Bindings/media/video-interfaces.txt @@ -85,10 +85,374 @@ Optional properties - lens-focus: A phandle to the node of the focus lens controller. -- rotation: The device, typically an image sensor, is not mounted upright, - but a number of degrees counter clockwise. Typical values are 0 and 180 - (upside down). +- rotation: The camera rotation is expressed as the angular difference in + degrees between two reference systems, one relative to the camera module, and + one defined on the external world scene to be captured when projected on the + image sensor pixel array. + A camera sensor has a 2-dimensional reference system 'Rc' defined by + its pixel array read-out order. The origin is set to the first pixel + being read out, the X-axis points along the column read-out direction + towards the last columns, and the Y-axis along the row read-out + direction towards the last row. + + A typical example for a sensor with a 2592x1944 pixel array matrix + observed from the front is: + + 2591 X-axis 0 + <------------------------+ 0 + .......... ... ..........! + .......... ... ..........! Y-axis + ... ! + .......... ... ..........! + .......... ... ..........! 1943 + V + + The external world scene reference system 'Rs' is a 2-dimensional + reference system on the focal plane of the camera module. The origin is + placed on the top-left corner of the visible scene, the X-axis points + towards the right, and the Y-axis points towards the bottom of the + scene. The top, bottom, left and right directions are intentionally not + defined and depend on the environment in which the camera is used. + + A typical example of a (very common) picture of a shark swimming from + left to right, as seen from the camera, is: + + 0 X-axis + 0 +-------------------------------------> + ! + ! + ! + ! |\____)\___ + ! ) _____ __`< + ! |/ )/ + ! + ! + ! + V + Y-axis + + with the reference system 'Rs' placed on the camera focal plane: + + ¸.·˙! + ¸.·˙ ! + _ ¸.·˙ ! + +-/ \-+¸.·˙ ! + | (o) | ! Camera focal plane + +-----+˙·.¸ ! + ˙·.¸ ! + ˙·.¸ ! + ˙·.¸! + + When projected on the sensor's pixel array, the image and the associated + reference system 'Rs' are typically (but not always) inverted, due to + the camera module's lens optical inversion effect. + + Assuming the above represented scene of the swimming shark, the lens + inversion projects the scene and its reference system onto the sensor + pixel array, seen from the front of the camera sensor, as follows: + + Y-axis + ^ + ! + ! + ! + ! |\_____)\__ + ! ) ____ ___.< + ! |/ )/ + ! + ! + ! + 0 +-------------------------------------> + 0 X-axis + + Note the shark being upside-down. + + The resulting projected reference system is named 'Rp'. + + The camera rotation property is then defined as the angular difference + in the counter-clockwise direction between the camera reference system + 'Rc' and the projected scene reference system 'Rp'. It is expressed in + degrees as a number in the range [0, 360[. + + Examples + + 0 degrees camera rotation: + + + Y-Rp + ^ + Y-Rc ! + ^ ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! 0 +-------------------------------------> + ! 0 X-Rp + 0 +-------------------------------------> + 0 X-Rc + + + X-Rc 0 + <------------------------------------+ 0 + X-Rp 0 ! + <------------------------------------+ 0 ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! V + ! Y-Rc + V + Y-Rp + + 90 degrees camera rotation: + + 0 Y-Rc + 0 +--------------------> + ! Y-Rp + ! ^ + ! ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! 0 +-------------------------------------> + ! 0 X-Rp + ! + ! + ! + ! + V + X-Rc + + 180 degrees camera rotation: + + 0 + <------------------------------------+ 0 + X-Rc ! + Y-Rp ! + ^ ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! V + ! Y-Rc + 0 +-------------------------------------> + 0 X-Rp + + 270 degrees camera rotation: + + 0 Y-Rc + 0 +--------------------> + ! 0 + ! <-----------------------------------+ 0 + ! X-Rp ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! ! + ! V + ! Y-Rp + ! + ! + ! + ! + V + X-Rc + + + Example one - Webcam + + A camera module installed on the user facing part of a laptop screen + casing used for video calls. The captured images are meant to be + displayed in landscape mode (width > height) on the laptop screen. + + The camera is typically mounted upside-down to compensate the lens + optical inversion effect: + + Y-Rp + Y-Rc ^ + ^ ! + ! ! + ! ! |\_____)\__ + ! ! ) ____ ___.< + ! ! |/ )/ + ! ! + ! ! + ! ! + ! 0 +-------------------------------------> + ! 0 X-Rp + 0 +-------------------------------------> + 0 X-Rc + + The two reference systems are aligned, the resulting camera rotation is + 0 degrees, no rotation correction needs to be applied to the resulting + image once captured to memory buffers to correctly display it to users: + + +--------------------------------------+ + ! ! + ! ! + ! ! + ! |\____)\___ ! + ! ) _____ __`< ! + ! |/ )/ ! + ! ! + ! ! + ! ! + +--------------------------------------+ + + If the camera sensor is not mounted upside-down to compensate for the + lens optical inversion, the two reference systems will not be aligned, + with 'Rp' being rotated 180 degrees relatively to 'Rc': + + + X-Rc 0 + <------------------------------------+ 0 + ! + Y-Rp ! + ^ ! + ! ! + ! |\_____)\__ ! + ! ) ____ ___.< ! + ! |/ )/ ! + ! ! + ! ! + ! V + ! Y-Rc + 0 +-------------------------------------> + 0 X-Rp + + The image once captured to memory will then be rotated by 180 degrees: + + +--------------------------------------+ + ! ! + ! ! + ! ! + ! __/(_____/| ! + ! >.___ ____ ( ! + ! \( \| ! + ! ! + ! ! + ! ! + +--------------------------------------+ + + A software rotation correction of 180 degrees should be applied to + correctly display the image: + + +--------------------------------------+ + ! ! + ! ! + ! ! + ! |\____)\___ ! + ! ) _____ __`< ! + ! |/ )/ ! + ! ! + ! ! + ! ! + +--------------------------------------+ + + Example two - Phone camera + + A camera installed on the back side of a mobile device facing away from + the user. The captured images are meant to be displayed in portrait mode + (height > width) to match the device screen orientation and the device + usage orientation used when taking the picture. + + The camera sensor is typically mounted with its pixel array longer side + aligned to the device longer side, upside-down mounted to compensate for + the lens optical inversion effect: + + 0 Y-Rc + 0 +--------------------> + ! Y-Rp + ! ^ + ! ! + ! ! + ! ! + ! ! |\_____)\__ + ! ! ) ____ ___.< + ! ! |/ )/ + ! ! + ! ! + ! ! + ! 0 +-------------------------------------> + ! 0 X-Rp + ! + ! + ! + ! + V + X-Rc + + The two reference systems are not aligned and the 'Rp' reference + system is rotated by 90 degrees in the counter-clockwise direction + relatively to the 'Rc' reference system. + + The image once captured to memory will be rotated: + + +-------------------------------------+ + | _ _ | + | \ / | + | | | | + | | | | + | | > | + | < | | + | | | | + | . | + | V | + +-------------------------------------+ + + A correction of 90 degrees in counter-clockwise direction has to be + applied to correctly display the image in portrait mode on the device + screen: + + +--------------------+ + | | + | | + | | + | | + | | + | | + | |\____)\___ | + | ) _____ __`< | + | |/ )/ | + | | + | | + | | + | | + | | + +--------------------+ + +- orientation: The orientation of a device (typically an image sensor or a flash + LED) describing its mounting position relative to the usage orientation of the + system where the device is installed on. + Possible values are: + 0 - Front. The device is mounted on the front facing side of the system. + For mobile devices such as smartphones, tablets and laptops the front side is + the user facing side. + 1 - Back. The device is mounted on the back side of the system, which is + defined as the opposite side of the front facing one. + 2 - External. The device is not attached directly to the system but is + attached in a way that allows it to move freely. Optional endpoint properties ---------------------------- diff --git a/Bindings/memory-controllers/baikal,bt1-l2-ctl.yaml b/Bindings/memory-controllers/baikal,bt1-l2-ctl.yaml new file mode 100644 index 000000000000..1fca282f64a2 --- /dev/null +++ b/Bindings/memory-controllers/baikal,bt1-l2-ctl.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 L2-cache Control Block + +maintainers: + - Serge Semin + +description: | + By means of the System Controller Baikal-T1 SoC exposes a few settings to + tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible + to change the Tag, Data and Way-select RAM access latencies. Baikal-T1 + L2-cache controller block is responsible for the tuning. Its DT node is + supposed to be a child of the system controller. + +properties: + compatible: + const: baikal,bt1-l2-ctl + + reg: + maxItems: 1 + + baikal,l2-ws-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Way-select RAM accesses + default: 0 + minimum: 0 + maximum: 3 + + baikal,l2-tag-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Tag RAM accesses + default: 0 + minimum: 0 + maximum: 3 + + baikal,l2-data-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Data RAM accesses + default: 1 + minimum: 0 + maximum: 3 + +additionalProperties: false + +required: + - compatible + +examples: + - | + l2@1f04d028 { + compatible = "baikal,bt1-l2-ctl"; + reg = <0x1f04d028 0x004>; + + baikal,l2-ws-latency = <1>; + baikal,l2-tag-latency = <1>; + baikal,l2-data-latency = <2>; + }; +... diff --git a/Bindings/memory-controllers/calxeda-ddr-ctrlr.txt b/Bindings/memory-controllers/calxeda-ddr-ctrlr.txt deleted file mode 100644 index 049675944b78..000000000000 --- a/Bindings/memory-controllers/calxeda-ddr-ctrlr.txt +++ /dev/null @@ -1,16 +0,0 @@ -Calxeda DDR memory controller - -Properties: -- compatible : Should be: - - "calxeda,hb-ddr-ctrl" for ECX-1000 - - "calxeda,ecx-2000-ddr-ctrl" for ECX-2000 -- reg : Address and size for DDR controller registers. -- interrupts : Interrupt for DDR controller. - -Example: - - memory-controller@fff00000 { - compatible = "calxeda,hb-ddr-ctrl"; - reg = <0xfff00000 0x1000>; - interrupts = <0 91 4>; - }; diff --git a/Bindings/memory-controllers/calxeda-ddr-ctrlr.yaml b/Bindings/memory-controllers/calxeda-ddr-ctrlr.yaml new file mode 100644 index 000000000000..96d563fd61f5 --- /dev/null +++ b/Bindings/memory-controllers/calxeda-ddr-ctrlr.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda DDR memory controller binding + +description: | + The Calxeda DDR memory controller is initialised and programmed by the + firmware, but an OS might want to read its registers for error reporting + purposes and to learn about the DRAM topology. + +maintainers: + - Andre Przywara + +properties: + compatible: + enum: + - calxeda,hb-ddr-ctrl + - calxeda,ecx-2000-ddr-ctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + memory-controller@fff00000 { + compatible = "calxeda,hb-ddr-ctrl"; + reg = <0xfff00000 0x1000>; + interrupts = <0 91 4>; + }; diff --git a/Bindings/memory-controllers/exynos-srom.yaml b/Bindings/memory-controllers/exynos-srom.yaml index cdfe3f7f0ea9..637e24f0f73b 100644 --- a/Bindings/memory-controllers/exynos-srom.yaml +++ b/Bindings/memory-controllers/exynos-srom.yaml @@ -51,9 +51,7 @@ patternProperties: maxItems: 1 reg-io-width: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [1, 2] + enum: [1, 2] description: Data width in bytes (1 or 2). If omitted, default of 1 is used. @@ -64,11 +62,10 @@ patternProperties: type: boolean samsung,srom-timing: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - items: - minItems: 6 - maxItems: 6 + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + minItems: 6 + maxItems: 6 description: | Array of 6 integers, specifying bank timings in the following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. diff --git a/Bindings/memory-controllers/fsl/imx8m-ddrc.yaml b/Bindings/memory-controllers/fsl/imx8m-ddrc.yaml index c9e6c22cb5be..445e46feda69 100644 --- a/Bindings/memory-controllers/fsl/imx8m-ddrc.yaml +++ b/Bindings/memory-controllers/fsl/imx8m-ddrc.yaml @@ -25,9 +25,9 @@ properties: compatible: items: - enum: - - fsl,imx8mn-ddrc - - fsl,imx8mm-ddrc - - fsl,imx8mq-ddrc + - fsl,imx8mn-ddrc + - fsl,imx8mm-ddrc + - fsl,imx8mq-ddrc - const: fsl,imx8m-ddrc reg: diff --git a/Bindings/memory-controllers/ingenic,jz4780-nemc.txt b/Bindings/memory-controllers/ingenic,jz4780-nemc.txt deleted file mode 100644 index 59b8dcc118ee..000000000000 --- a/Bindings/memory-controllers/ingenic,jz4780-nemc.txt +++ /dev/null @@ -1,76 +0,0 @@ -* Ingenic JZ4780 NAND/external memory controller (NEMC) - -This file documents the device tree bindings for the NEMC external memory -controller in Ingenic JZ4780 - -Required properties: -- compatible: Should be set to one of: - "ingenic,jz4740-nemc" (JZ4740) - "ingenic,jz4780-nemc" (JZ4780) -- reg: Should specify the NEMC controller registers location and length. -- clocks: Clock for the NEMC controller. -- #address-cells: Must be set to 2. -- #size-cells: Must be set to 1. -- ranges: A set of ranges for each bank describing the physical memory layout. - Each should specify the following 4 integer values: - - 0 - -Each child of the NEMC node describes a device connected to the NEMC. - -Required child node properties: -- reg: Should contain at least one register specifier, given in the following - format: - - - - Multiple registers can be specified across multiple banks. This is needed, - for example, for packaged NAND devices with multiple dies. Such devices - should be grouped into a single node. - -Optional child node properties: -- ingenic,nemc-bus-width: Specifies the bus width in bits. Defaults to 8 bits. -- ingenic,nemc-tAS: Address setup time in nanoseconds. -- ingenic,nemc-tAH: Address hold time in nanoseconds. -- ingenic,nemc-tBP: Burst pitch time in nanoseconds. -- ingenic,nemc-tAW: Access wait time in nanoseconds. -- ingenic,nemc-tSTRV: Static memory recovery time in nanoseconds. - -If a child node references multiple banks in its "reg" property, the same value -for all optional parameters will be configured for all banks. If any optional -parameters are omitted, they will be left unchanged from whatever they are -configured to when the NEMC device is probed (which may be the reset value as -given in the hardware reference manual, or a value configured by the boot -loader). - -Example (NEMC node with a NAND child device attached at CS1): - -nemc: nemc@13410000 { - compatible = "ingenic,jz4780-nemc"; - reg = <0x13410000 0x10000>; - - #address-cells = <2>; - #size-cells = <1>; - - ranges = <1 0 0x1b000000 0x1000000 - 2 0 0x1a000000 0x1000000 - 3 0 0x19000000 0x1000000 - 4 0 0x18000000 0x1000000 - 5 0 0x17000000 0x1000000 - 6 0 0x16000000 0x1000000>; - - clocks = <&cgu JZ4780_CLK_NEMC>; - - nand: nand@1 { - compatible = "ingenic,jz4780-nand"; - reg = <1 0 0x1000000>; - - ingenic,nemc-tAS = <10>; - ingenic,nemc-tAH = <5>; - ingenic,nemc-tBP = <10>; - ingenic,nemc-tAW = <15>; - ingenic,nemc-tSTRV = <100>; - - ... - }; -}; diff --git a/Bindings/memory-controllers/ingenic,nemc.yaml b/Bindings/memory-controllers/ingenic,nemc.yaml new file mode 100644 index 000000000000..17ba45a6c260 --- /dev/null +++ b/Bindings/memory-controllers/ingenic,nemc.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ingenic,nemc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs NAND / External Memory Controller (NEMC) devicetree bindings + +maintainers: + - Paul Cercueil + +properties: + $nodename: + pattern: "^memory-controller@[0-9a-f]+$" + + compatible: + oneOf: + - enum: + - ingenic,jz4740-nemc + - ingenic,jz4780-nemc + - items: + - const: ingenic,jz4725b-nemc + - const: ingenic,jz4740-nemc + + "#address-cells": + const: 2 + + "#size-cells": + const: 1 + + ranges: true + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +patternProperties: + ".*@[0-9]+$": + type: object + properties: + reg: + minItems: 1 + maxItems: 255 + + ingenic,nemc-bus-width: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16] + description: Specifies the bus width in bits. + + ingenic,nemc-tAS: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Address setup time in nanoseconds. + + ingenic,nemc-tAH: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Address hold time in nanoseconds. + + ingenic,nemc-tBP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Burst pitch time in nanoseconds. + + ingenic,nemc-tAW: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Address wait time in nanoseconds. + + ingenic,nemc-tSTRV: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Static memory recovery time in nanoseconds. + + required: + - reg + +required: + - compatible + - "#address-cells" + - "#size-cells" + - ranges + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + nemc: memory-controller@13410000 { + compatible = "ingenic,jz4780-nemc"; + reg = <0x13410000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0x1b000000 0x1000000>, + <2 0 0x1a000000 0x1000000>, + <3 0 0x19000000 0x1000000>, + <4 0 0x18000000 0x1000000>, + <5 0 0x17000000 0x1000000>, + <6 0 0x16000000 0x1000000>; + + clocks = <&cgu JZ4780_CLK_NEMC>; + + ethernet@6 { + compatible = "davicom,dm9000"; + davicom,no-eeprom; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_nemc_cs6>; + + reg = <6 0 1>, /* addr */ + <6 2 1>; /* data */ + + ingenic,nemc-tAS = <15>; + ingenic,nemc-tAH = <10>; + ingenic,nemc-tBP = <20>; + ingenic,nemc-tAW = <50>; + ingenic,nemc-tSTRV = <100>; + + reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>; + vcc-supply = <ð0_power>; + + interrupt-parent = <&gpe>; + interrupts = <19 4>; + }; + }; diff --git a/Bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Bindings/memory-controllers/nvidia,tegra124-emc.yaml index 3e0a8a92d652..278549f9e051 100644 --- a/Bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -73,10 +73,9 @@ patternProperties: timings nvidia,emc-auto-cal-interval: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 description: pad calibration interval in microseconds + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 2097151 @@ -136,11 +135,10 @@ patternProperties: value of the EMC_XM2DQSPADCTRL2 register for this set of timings nvidia,emc-zcal-cnt-long: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 description: number of EMC clocks to wait before issuing any commands after clock change + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 1023 @@ -150,12 +148,11 @@ patternProperties: value of the EMC_ZCAL_INTERVAL register for this set of timings nvidia,emc-configuration: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array description: EMC timing characterization data. These are the registers (see section "15.6.2 EMC Registers" in the TRM) whose values need to be specified, according to the board documentation. + $ref: /schemas/types.yaml#/definitions/uint32-array items: - description: EMC_RC - description: EMC_RFC @@ -340,7 +337,7 @@ examples: mc: memory-controller@70019000 { compatible = "nvidia,tegra124-mc"; - reg = <0x0 0x70019000 0x0 0x1000>; + reg = <0x70019000 0x1000>; clocks = <&tegra_car TEGRA124_CLK_MC>; clock-names = "mc"; @@ -352,7 +349,7 @@ examples: external-memory-controller@7001b000 { compatible = "nvidia,tegra124-emc"; - reg = <0x0 0x7001b000 0x0 0x1000>; + reg = <0x7001b000 0x1000>; clocks = <&car TEGRA124_CLK_EMC>; clock-names = "emc"; diff --git a/Bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Bindings/memory-controllers/nvidia,tegra124-mc.yaml index 22a94b6fdbde..84d0339505b1 100644 --- a/Bindings/memory-controllers/nvidia,tegra124-mc.yaml +++ b/Bindings/memory-controllers/nvidia,tegra124-mc.yaml @@ -60,8 +60,7 @@ patternProperties: maximum: 1066000000 nvidia,emem-configuration: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array description: | Values to be written to the EMEM register block. See section "15.6.1 MC Registers" in the TRM. @@ -112,7 +111,7 @@ examples: - | memory-controller@70019000 { compatible = "nvidia,tegra124-mc"; - reg = <0x0 0x70019000 0x0 0x1000>; + reg = <0x70019000 0x1000>; clocks = <&tegra_car 32>; clock-names = "mc"; diff --git a/Bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Bindings/memory-controllers/nvidia,tegra210-emc.yaml new file mode 100644 index 000000000000..49ab09252e52 --- /dev/null +++ b/Bindings/memory-controllers/nvidia,tegra210-emc.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra210 SoC External Memory Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +description: | + The EMC interfaces with the off-chip SDRAM to service the request stream + sent from the memory controller. + +properties: + compatible: + const: nvidia,tegra210-emc + + reg: + maxItems: 3 + + clocks: + items: + - description: external memory clock + + clock-names: + items: + - const: emc + + interrupts: + items: + - description: EMC general interrupt + + memory-region: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to a reserved memory region describing the table of EMC + frequencies trained by the firmware + + nvidia,memory-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of the memory controller node + +required: + - compatible + - reg + - clocks + - clock-names + - nvidia,memory-controller + +additionalProperties: false + +examples: + - | + #include + #include + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + emc_table: emc-table@83400000 { + compatible = "nvidia,tegra210-emc-table"; + reg = <0x83400000 0x10000>; + }; + }; + + external-memory-controller@7001b000 { + compatible = "nvidia,tegra210-emc"; + reg = <0x7001b000 0x1000>, + <0x7001e000 0x1000>, + <0x7001f000 0x1000>; + clocks = <&tegra_car TEGRA210_CLK_EMC>; + clock-names = "emc"; + interrupts = ; + memory-region = <&emc_table>; + nvidia,memory-controller = <&mc>; + }; diff --git a/Bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Bindings/memory-controllers/nvidia,tegra30-emc.yaml index e4135bac6957..112bae2fcbbd 100644 --- a/Bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -56,10 +56,9 @@ patternProperties: maximum: 900000000 nvidia,emc-auto-cal-interval: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 description: Pad calibration interval in microseconds. + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 2097151 @@ -79,11 +78,10 @@ patternProperties: Mode Register 0. nvidia,emc-zcal-cnt-long: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 description: Number of EMC clocks to wait before issuing any commands after sending ZCAL_MRW_CMD. + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 1023 @@ -98,12 +96,11 @@ patternProperties: FBIO "read" FIFO periodic resetting enabled. nvidia,emc-configuration: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array description: EMC timing characterization data. These are the registers (see section "18.13.2 EMC Registers" in the TRM) whose values need to be specified, according to the board documentation. + $ref: /schemas/types.yaml#/definitions/uint32-array items: - description: EMC_RC - description: EMC_RFC diff --git a/Bindings/memory-controllers/nvidia,tegra30-mc.yaml b/Bindings/memory-controllers/nvidia,tegra30-mc.yaml index 4b9196c83291..84fd57bcf0dc 100644 --- a/Bindings/memory-controllers/nvidia,tegra30-mc.yaml +++ b/Bindings/memory-controllers/nvidia,tegra30-mc.yaml @@ -77,8 +77,7 @@ patternProperties: maximum: 900000000 nvidia,emem-configuration: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array description: | Values to be written to the EMEM register block. See section "18.13.1 MC Registers" in the TRM. diff --git a/Bindings/memory-controllers/renesas,dbsc.txt b/Bindings/memory-controllers/renesas,dbsc.txt deleted file mode 100644 index 9f78e6c82740..000000000000 --- a/Bindings/memory-controllers/renesas,dbsc.txt +++ /dev/null @@ -1,44 +0,0 @@ -DT bindings for Renesas R-Mobile and SH-Mobile memory controllers -================================================================= - -Renesas R-Mobile and SH-Mobile SoCs contain one or more memory controllers. -These memory controllers differ from one SoC variant to another, and are called -by different names ("DDR Bus Controller (DBSC)", "DDR3 Bus State Controller -(DBSC3)", "SDRAM Bus State Controller (SBSC)"). - -Currently memory controller device nodes are used only to reference PM -domains, and prevent these PM domains from being powered down, which would -crash the system. - -As there exist no actual drivers for these controllers yet, these bindings -should be considered EXPERIMENTAL for now. - -Required properties: - - compatible: Must be one of the following SoC-specific values: - - "renesas,dbsc-r8a73a4" (R-Mobile APE6) - - "renesas,dbsc3-r8a7740" (R-Mobile A1) - - "renesas,sbsc-sh73a0" (SH-Mobile AG5) - - reg: Must contain the base address and length of the memory controller's - registers. - -Optional properties: - - interrupts: Must contain a list of interrupt specifiers for memory - controller interrupts, if available. - - interrupt-names: Must contain a list of interrupt names corresponding to - the interrupts in the interrupts property, if available. - Valid interrupt names are: - - "sec" (secure interrupt) - - "temp" (normal (temperature) interrupt) - - power-domains: Must contain a reference to the PM domain that the memory - controller belongs to, if available. - -Example: - - sbsc1: memory-controller@fe400000 { - compatible = "renesas,sbsc-sh73a0"; - reg = <0xfe400000 0x400>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, - <0 36 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "sec", "temp"; - power-domains = <&pd_a4bc0>; - }; diff --git a/Bindings/memory-controllers/renesas,dbsc.yaml b/Bindings/memory-controllers/renesas,dbsc.yaml new file mode 100644 index 000000000000..7056ccb7eb30 --- /dev/null +++ b/Bindings/memory-controllers/renesas,dbsc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas DDR Bus Controllers + +maintainers: + - Geert Uytterhoeven + +description: | + Renesas SoCs contain one or more memory controllers. These memory + controllers differ from one SoC variant to another, and are called by + different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller + (DBSC3)", or "SDRAM Bus State Controller (SBSC)"). + +properties: + compatible: + enum: + - renesas,dbsc-r8a73a4 # R-Mobile APE6 + - renesas,dbsc3-r8a7740 # R-Mobile A1 + - renesas,sbsc-sh73a0 # SH-Mobile AG5 + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: sec # secure interrupt + - const: temp # normal (temperature) interrupt + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - power-domains + +additionalProperties: false + +examples: + - | + #include + sbsc1: memory-controller@fe400000 { + compatible = "renesas,sbsc-sh73a0"; + reg = <0xfe400000 0x400>; + interrupts = , + ; + interrupt-names = "sec", "temp"; + power-domains = <&pd_a4bc0>; + }; diff --git a/Bindings/mfd/allwinner,sun4i-a10-ts.yaml b/Bindings/mfd/allwinner,sun4i-a10-ts.yaml index 39afacc447b2..f591332fc462 100644 --- a/Bindings/mfd/allwinner,sun4i-a10-ts.yaml +++ b/Bindings/mfd/allwinner,sun4i-a10-ts.yaml @@ -31,19 +31,19 @@ properties: description: A touchscreen is attached to the controller allwinner,tp-sensitive-adjust: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - maximum: 15 - default: 15 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + default: 15 + description: Sensitivity of pen down detection allwinner,filter-type: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - maximum: 3 - default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 1 + description: | Select median and averaging filter. Sample used for median / averaging filter: diff --git a/Bindings/mfd/arizona.txt b/Bindings/mfd/arizona.txt deleted file mode 100644 index 148ef621a5e5..000000000000 --- a/Bindings/mfd/arizona.txt +++ /dev/null @@ -1,101 +0,0 @@ -Cirrus Logic/Wolfson Microelectronics Arizona class audio SoCs - -These devices are audio SoCs with extensive digital capabilities and a range -of analogue I/O. - -Required properties: - - - compatible : One of the following chip-specific strings: - "cirrus,cs47l24" - "wlf,wm5102" - "wlf,wm5110" - "wlf,wm8280" - "wlf,wm8997" - "wlf,wm8998" - "wlf,wm1814" - "wlf,wm1831" - - - reg : I2C slave address when connected using I2C, chip select number when - using SPI. - - - interrupts : The interrupt line the /IRQ signal for the device is - connected to. - - interrupt-controller : Arizona class devices contain interrupt controllers - and may provide interrupt services to other devices. - - #interrupt-cells: the number of cells to describe an IRQ, this should be 2. - The first cell is the IRQ number. - The second cell is the flags, encoded as the trigger masks from - Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - - - gpio-controller : Indicates this device is a GPIO controller. - - #gpio-cells : Must be 2. The first cell is the pin number and the - second cell is used to specify optional parameters, see ../gpio/gpio.txt - for details. - - - AVDD-supply, DBVDD1-supply, CPVDD-supply : Power supplies for the device, - as covered in Documentation/devicetree/bindings/regulator/regulator.txt - - - DBVDD2-supply, DBVDD3-supply : Additional databus power supplies (wm5102, - wm5110, wm8280, wm8998, wm1814) - - - SPKVDDL-supply, SPKVDDR-supply : Speaker driver power supplies (wm5102, - wm5110, wm8280, wm8998, wm1814) - - - SPKVDD-supply : Speaker driver power supply (wm8997) - - - DCVDD-supply : Main power supply (cs47l24, wm1831) - - - MICVDD-supply : Microphone power supply (cs47l24, wm1831) - -Optional properties: - - - reset-gpios : GPIO specifier for the GPIO controlling /RESET - - - clocks: Should reference the clocks supplied on MCLK1 and MCLK2 - - clock-names: Should contains two strings: - "mclk1" for the clock supplied on MCLK1, recommended to be a high - quality audio reference clock - "mclk2" for the clock supplied on MCLK2, recommended to be an always on - 32k clock - - - wlf,gpio-defaults : A list of GPIO configuration register values. Defines - for the appropriate values can found in . If - absent, no configuration of these registers is performed. If any entry has - a value that is out of range for a 16 bit register then the chip default - will be used. If present exactly five values must be specified. - - - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if - they are being externally supplied. As covered in - Documentation/devicetree/bindings/regulator/regulator.txt - (wm5102, wm5110, wm8280, wm8997, wm8998, wm1814) - -Deprecated properties: - - - wlf,reset : GPIO specifier for the GPIO controlling /RESET - -Also see child specific device properties: - Regulator - ../regulator/arizona-regulator.txt - Extcon - ../extcon/extcon-arizona.txt - Sound - ../sound/wlf,arizona.txt - -Example: - -codec: wm5102@1a { - compatible = "wlf,wm5102"; - reg = <0x1a>; - interrupts = <347>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gic>; - - gpio-controller; - #gpio-cells = <2>; - - wlf,gpio-defaults = < - ARIZONA_GP_FN_TXLRCLK - ARIZONA_GP_DEFAULT - ARIZONA_GP_DEFAULT - ARIZONA_GP_DEFAULT - ARIZONA_GP_DEFAULT - >; -}; diff --git a/Bindings/mfd/cirrus,lochnagar.txt b/Bindings/mfd/cirrus,lochnagar.txt deleted file mode 100644 index 3bf92ad37fa1..000000000000 --- a/Bindings/mfd/cirrus,lochnagar.txt +++ /dev/null @@ -1,85 +0,0 @@ -Cirrus Logic Lochnagar Audio Development Board - -Lochnagar is an evaluation and development board for Cirrus Logic -Smart CODEC and Amp devices. It allows the connection of most Cirrus -Logic devices on mini-cards, as well as allowing connection of -various application processor systems to provide a full evaluation -platform. Audio system topology, clocking and power can all be -controlled through the Lochnagar, allowing the device under test -to be used in a variety of possible use cases. - -Also see these documents for generic binding information: - [1] GPIO : ../gpio/gpio.txt - -And these for relevant defines: - [2] include/dt-bindings/pinctrl/lochnagar.h - [3] include/dt-bindings/clock/lochnagar.h - -And these documents for the required sub-node binding details: - [4] Clock: ../clock/cirrus,lochnagar.txt - [5] Pinctrl: ../pinctrl/cirrus,lochnagar.txt - [6] Regulator: ../regulator/cirrus,lochnagar.txt - [7] Sound: ../sound/cirrus,lochnagar.txt - [8] Hardware Monitor: ../hwmon/cirrus,lochnagar.txt - -Required properties: - - - compatible : One of the following strings: - "cirrus,lochnagar1" - "cirrus,lochnagar2" - - - reg : I2C slave address - - - reset-gpios : Reset line to the Lochnagar, see [1]. - -Required sub-nodes: - - - lochnagar-clk : Binding for the clocking components, see [4]. - - - lochnagar-pinctrl : Binding for the pin control components, see [5]. - -Optional sub-nodes: - - - Bindings for the regulator components, see [6]. Only available on - Lochnagar 2. - - - lochnagar-sc : Binding for the sound card components, see [7]. - Only available on Lochnagar 2. - - lochnagar-hwmon : Binding for the hardware monitor components, see [8]. - Only available on Lochnagar 2. - -Optional properties: - - - present-gpios : Host present line, indicating the presence of a - host system, see [1]. This can be omitted if the present line is - tied in hardware. - -Example: - -lochnagar: lochnagar@22 { - compatible = "cirrus,lochnagar2"; - reg = <0x22>; - - reset-gpios = <&gpio0 55 0>; - present-gpios = <&gpio0 60 0>; - - lochnagar-clk { - compatible = "cirrus,lochnagar2-clk"; - ... - }; - - lochnagar-pinctrl { - compatible = "cirrus,lochnagar-pinctrl"; - ... - }; - - lochnagar-sc { - compatible = "cirrus,lochnagar2-soundcard"; - ... - }; - - lochnagar-hwmon { - compatible = "cirrus,lochnagar2-hwmon"; - ... - }; -}; diff --git a/Bindings/mfd/cirrus,lochnagar.yaml b/Bindings/mfd/cirrus,lochnagar.yaml new file mode 100644 index 000000000000..7a616577ac63 --- /dev/null +++ b/Bindings/mfd/cirrus,lochnagar.yaml @@ -0,0 +1,352 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/cirrus,lochnagar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic Lochnagar Audio Development Board + +maintainers: + - patches@opensource.cirrus.com + +description: | + Lochnagar is an evaluation and development board for Cirrus Logic + Smart CODEC and Amp devices. It allows the connection of most Cirrus + Logic devices on mini-cards, as well as allowing connection of + various application processor systems to provide a full evaluation + platform. Audio system topology, clocking and power can all be + controlled through the Lochnagar, allowing the device under test + to be used in a variety of possible use cases. + + Also see these documents for generic binding information: + [1] GPIO : ../gpio/gpio.txt + + And these for relevant defines: + [2] include/dt-bindings/pinctrl/lochnagar.h + [3] include/dt-bindings/clock/lochnagar.h + + And these documents for the required sub-node binding details: + [4] Clock: ../clock/cirrus,lochnagar.yaml + [5] Pinctrl: ../pinctrl/cirrus,lochnagar.yaml + [6] Sound: ../sound/cirrus,lochnagar.yaml + [7] Hardware Monitor: ../hwmon/cirrus,lochnagar.yaml + +allOf: + - if: + properties: + compatible: + enum: + - cirrus,lochnagar2 + then: + properties: + lochnagar-hwmon: + type: object + $ref: /schemas/hwmon/cirrus,lochnagar.yaml# + + lochnagar-sc: + type: object + $ref: /schemas/sound/cirrus,lochnagar.yaml# + +properties: + compatible: + enum: + - cirrus,lochnagar1 + - cirrus,lochnagar2 + + reg: + const: 0x22 + + reset-gpios: + maxItems: 1 + + present-gpios: + description: | + Host present line, indicating the presence of a + host system, see [1]. This can be omitted if the present line is + tied in hardware. + maxItems: 1 + + lochnagar-clk: + type: object + $ref: /schemas/clock/cirrus,lochnagar.yaml# + + lochnagar-pmic32k: + type: object + $ref: /schemas/clock/fixed-clock.yaml# + properties: + clock-frequency: + const: 32768 + + lochnagar-clk12m: + type: object + $ref: /schemas/clock/fixed-clock.yaml# + properties: + clock-frequency: + const: 12288000 + + lochnagar-clk11m: + type: object + $ref: /schemas/clock/fixed-clock.yaml# + properties: + clock-frequency: + const: 11298600 + + lochnagar-clk24m: + type: object + $ref: /schemas/clock/fixed-clock.yaml# + properties: + clock-frequency: + const: 24576000 + + lochnagar-clk22m: + type: object + $ref: /schemas/clock/fixed-clock.yaml# + properties: + clock-frequency: + const: 22579200 + + lochnagar-clk8m: + type: object + $ref: /schemas/clock/fixed-clock.yaml# + properties: + clock-frequency: + const: 8192000 + + lochnagar-usb24m: + type: object + $ref: /schemas/clock/fixed-clock.yaml# + properties: + clock-frequency: + const: 24576000 + + lochnagar-usb12m: + type: object + $ref: /schemas/clock/fixed-clock.yaml# + properties: + clock-frequency: + const: 12288000 + + lochnagar-pinctrl: + type: object + $ref: /schemas/pinctrl/cirrus,lochnagar.yaml# + + VDDCORE: + description: + Initialisation data for the VDDCORE regulator, which supplies the + CODECs digital core if not being provided by an internal regulator. + type: object + $ref: /schemas/regulator/regulator.yaml# + properties: + compatible: + enum: + - cirrus,lochnagar2-vddcore + + SYSVDD-supply: + description: + Primary power supply for the Lochnagar. + required: + - compatible + + MICVDD: + description: + Initialisation data for the MICVDD regulator, which supplies the + CODECs MICVDD. + type: object + $ref: /schemas/regulator/regulator.yaml# + properties: + compatible: + enum: + - cirrus,lochnagar2-micvdd + + SYSVDD-supply: + description: + Primary power supply for the Lochnagar. + required: + - compatible + + MIC1VDD: + description: + Initialisation data for the MIC1VDD supplies. + type: object + $ref: /schemas/regulator/regulator.yaml# + properties: + compatible: + enum: + - cirrus,lochnagar2-mic1vdd + + cirrus,micbias-input: + description: + A property selecting which of the CODEC minicard micbias outputs + should be used. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 4 + + MICBIAS1-supply: + description: + Regulator supplies for the MIC1VDD outputs, supplying the digital + microphones, normally supplied from the attached CODEC. + required: + - compatible + + MIC2VDD: + description: + Initialisation data for the MIC2VDD supplies. + type: object + $ref: /schemas/regulator/regulator.yaml# + properties: + compatible: + enum: + - cirrus,lochnagar2-mic2vdd + + cirrus,micbias-input: + description: + A property selecting which of the CODEC minicard micbias outputs + should be used. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 4 + + MICBIAS2-supply: + description: + Regulator supplies for the MIC2VDD outputs, supplying the digital + microphones, normally supplied from the attached CODEC. + required: + - compatible + + VDD1V8: + description: + Recommended fixed regulator for the VDD1V8 regulator, which supplies + the CODECs analog and 1.8V digital supplies. + type: object + $ref: /schemas/regulator/regulator.yaml# + properties: + compatible: + enum: + - regulator-fixed + + regulator-min-microvolt: + const: 1800000 + + regulator-max-microvolt: + const: 1800000 + + vin-supply: + description: + Should be set to same supply as SYSVDD + required: + - compatible + - regulator-min-microvolt + - regulator-max-microvolt + - regulator-boot-on + - regulator-always-on + - vin-supply + +required: + - compatible + - reg + - reset-gpios + - lochnagar-clk + - lochnagar-pinctrl + +unevaluatedProperties: false + +examples: + - | + #include + #include + i2c@e0004000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe0004000 0x1000>; + + lochnagar: lochnagar@22 { + compatible = "cirrus,lochnagar2"; + reg = <0x22>; + + reset-gpios = <&gpio0 55 0>; + present-gpios = <&gpio0 60 0>; + + lochnagarclk: lochnagar-clk { + compatible = "cirrus,lochnagar2-clk"; + + #clock-cells = <1>; + clocks = <&clkaudio>, <&clkpmic>; + clock-names = "ln-gf-mclk2", "ln-pmic-32k"; + + assigned-clocks = <&lochnagarclk LOCHNAGAR_CDC_MCLK1>, + <&lochnagarclk LOCHNAGAR_CDC_MCLK2>; + assigned-clock-parents = <&clkaudio>, <&clkpmic>; + }; + + clkpmic: lochnagar-pmic32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + lochnagar-pinctrl { + compatible = "cirrus,lochnagar-pinctrl"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lochnagar 0 0 LOCHNAGAR2_PIN_NUM_GPIOS>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinsettings>; + + pinsettings: pin-settings { + ap2aif-pins { + input-enable; + groups = "gf-aif1"; + function = "codec-aif3"; + }; + codec2aif-pins { + output-enable; + groups = "codec-aif3"; + function = "gf-aif1"; + }; + }; + }; + + lochnagar-sc { + compatible = "cirrus,lochnagar2-soundcard"; + + #sound-dai-cells = <1>; + + clocks = <&lochnagarclk LOCHNAGAR_SOUNDCARD_MCLK>; + clock-names = "mclk"; + }; + + lochnagar-hwmon { + compatible = "cirrus,lochnagar2-hwmon"; + }; + + MIC1VDD { + compatible = "cirrus,lochnagar2-mic1vdd"; + + cirrus,micbias-input = <3>; + }; + + MICVDD { + compatible = "cirrus,lochnagar2-micvdd"; + + SYSVDD-supply = <&wallvdd>; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + VDD1V8 { + compatible = "regulator-fixed"; + + regulator-name = "VDD1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + + vin-supply = <&wallvdd>; + }; + }; + }; diff --git a/Bindings/mfd/cirrus,madera.yaml b/Bindings/mfd/cirrus,madera.yaml new file mode 100644 index 000000000000..a5531f6caf12 --- /dev/null +++ b/Bindings/mfd/cirrus,madera.yaml @@ -0,0 +1,299 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/cirrus,madera.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic Madera class audio CODECs Multi-Functional Device + +maintainers: + - patches@opensource.cirrus.com + +description: | + These devices are audio SoCs with extensive digital capabilities and a range + of analogue I/O. + + See also the child driver bindings in: + + bindings/pinctrl/cirrus,madera.yaml + bindings/regulator/wlf,arizona.yaml + bindings/sound/cirrus,madera.yaml + +allOf: + - $ref: /schemas/pinctrl/cirrus,madera.yaml# + - $ref: /schemas/regulator/wlf,arizona.yaml# + - $ref: /schemas/sound/cirrus,madera.yaml# + - if: + properties: + compatible: + contains: + enum: + - cirrus,cs47l85 + - wlf,wm1840 + then: + properties: + SPKVDDL-supply: + description: + Left speaker driver power supply. + + SPKVDDR-supply: + description: + Right speaker driver power supply. + + required: + - SPKVDDL-supply + - SPKVDDR-supply + else: + required: + - DCVDD-supply + - if: + properties: + compatible: + contains: + enum: + - cirrus,cs47l15 + - cirrus,cs47l35 + then: + properties: + SPKVDD-supply: + description: + Mono speaker driver power supply. + + required: + - SPKVDD-supply + - if: + properties: + compatible: + contains: + enum: + - cirrus,cs47l35 + - cirrus,cs47l85 + - cirrus,cs47l90 + - cirrus,cs47l91 + - wlf,wm1840 + then: + properties: + DBVDD2-supply: + description: + Databus power supply. + + required: + - DBVDD2-supply + - if: + properties: + compatible: + contains: + enum: + - cirrus,cs47l85 + - cirrus,cs47l90 + - cirrus,cs47l91 + - wlf,wm1840 + then: + properties: + DBVDD3-supply: + description: + Databus power supply. + + DBVDD4-supply: + description: + Databus power supply. + - if: + properties: + compatible: + contains: + enum: + - cirrus,cs47l15 + then: + required: + - MICVDD-supply + else: + properties: + CPVDD2-supply: + description: + Secondary charge pump power supply. + + required: + - CPVDD2-supply + +properties: + compatible: + enum: + - cirrus,cs47l15 + - cirrus,cs47l35 + - cirrus,cs47l85 + - cirrus,cs47l90 + - cirrus,cs47l91 + - cirrus,cs42l92 + - cirrus,cs47l92 + - cirrus,cs47l93 + - cirrus,wm1840 + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + description: + The first cell is the pin number. The second cell is reserved for + future use and must be zero + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + description: + The first cell is the IRQ number. + The second cell is the flags, encoded as the trigger masks from + bindings/interrupt-controller/interrupts.txt + const: 2 + + interrupts: + maxItems: 1 + + reset-gpios: + description: + One entry specifying the GPIO controlling /RESET. As defined in + bindings/gpio.txt. Although optional, it is strongly recommended + to use a hardware reset. + maxItems: 1 + + clocks: + description: + Should reference the clocks supplied on MCLK1, MCLK2 and MCLK3. + minItems: 1 + maxItems: 3 + + clock-names: + description: | + May contain up to three strings: + "mclk1" For the clock supplied on MCLK1, recommended to be a + high quality audio reference clock. + "mclk2" For the clock supplied on MCLK2, required to be an + always on 32k clock. + "mclk3" For the clock supplied on MCLK3. + oneOf: + - items: + - const: mclk1 + - items: + - const: mclk2 + - items: + - const: mclk3 + - items: + - const: mclk1 + - const: mclk2 + - items: + - const: mclk1 + - const: mclk3 + - items: + - const: mclk2 + - const: mclk3 + - items: + - const: mclk1 + - const: mclk2 + - const: mclk3 + + AVDD-supply: + description: + Analogue power supply. + + DBVDD1-supply: + description: + Databus power supply. + + CPVDD1-supply: + description: + Charge pump power supply. + + DCVDD-supply: + description: + Digital power supply, optional on CS47L85, WM1840 where it can + be supplied internally. + + MICVDD-supply: + description: + Microphone power supply, normally supplied internally except on + cs47l24, wm1831 where it is mandatory. + +required: + - compatible + - gpio-controller + - '#gpio-cells' + - interrupt-controller + - '#interrupt-cells' + - interrupt-parent + - interrupts + - AVDD-supply + - DBVDD1-supply + - CPVDD1-supply + +unevaluatedProperties: false + +examples: + - | + #include + i2c@e0004000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe0004000 0x1000>; + + cs47l85: codec@1a { + compatible = "cirrus,cs47l85"; + reg = <0x1a>; + + reset-gpios = <&gpio 0>; + wlf,ldoena = <&gpio 1>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <&host_irq1>; + interrupt-parent = <&gic>; + + gpio-controller; + #gpio-cells = <2>; + + AVDD-supply = <&vdd1v8>; + DBVDD1-supply = <&vdd1v8>; + DBVDD2-supply = <&vdd1v8>; + DBVDD3-supply = <&vdd1v8>; + DBVDD4-supply = <&vdd1v8>; + CPVDD1-supply = <&vdd1v8>; + CPVDD2-supply = <&vdd1v2>; + SPKVDDL-supply = <&vdd5v>; + SPKVDDR-supply = <&vdd5v>; + + clocks = <&clks 0>, <&clks 1>, <&clks 2>; + clock-names = "mclk1", "mclk2", "mclk3"; + + cirrus,dmic-ref = <0 0 MADERA_DMIC_REF_MICBIAS1>; + cirrus,inmode = < + MADERA_INMODE_SE MADERA_INMODE_SE + MADERA_INMODE_SE MADERA_INMODE_SE + MADERA_INMODE_DIFF MADERA_INMODE_DIFF + >; + cirrus,max-channels-clocked = <2 0 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinsettings>; + + pinsettings: pin-settings { + aif1-pins { + groups = "aif1"; + function = "aif1"; + bias-bus-hold; + }; + + aif2-pins { + groups = "aif2"; + function = "aif2"; + bias-bus-hold; + }; + + aif3-pins { + groups = "aif3"; + function = "aif3"; + bias-bus-hold; + }; + }; + }; + }; diff --git a/Bindings/mfd/gateworks-gsc.yaml b/Bindings/mfd/gateworks-gsc.yaml new file mode 100644 index 000000000000..487a8445722e --- /dev/null +++ b/Bindings/mfd/gateworks-gsc.yaml @@ -0,0 +1,196 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Gateworks System Controller + +description: | + The Gateworks System Controller (GSC) is a device present across various + Gateworks product families that provides a set of system related features + such as the following (refer to the board hardware user manuals to see what + features are present) + - Watchdog Timer + - GPIO + - Pushbutton controller + - Hardware monitor with ADC's for temperature and voltage rails and + fan controller + +maintainers: + - Tim Harvey + - Robert Jones + +properties: + $nodename: + pattern: "gsc@[0-9a-f]{1,2}" + compatible: + const: gw,gsc + + reg: + description: I2C device address + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + adc: + type: object + description: Optional hardware monitoring module + + properties: + compatible: + const: gw,gsc-adc + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^channel@[0-9]+$": + type: object + description: | + Properties for a single ADC which can report cooked values + (i.e. temperature sensor based on thermister), raw values + (i.e. voltage rail with a pre-scaling resistor divider). + + properties: + reg: + description: Register of the ADC + maxItems: 1 + + label: + description: Name of the ADC input + + gw,mode: + description: | + conversion mode: + 0 - temperature, in C*10 + 1 - pre-scaled voltage value + 2 - scaled voltage based on an optional resistor divider + and optional offset + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + gw,voltage-divider-ohms: + description: Values of resistors for divider on raw ADC input + maxItems: 2 + items: + minimum: 1000 + maximum: 1000000 + + gw,voltage-offset-microvolt: + description: | + A positive voltage offset to apply to a raw ADC + (i.e. to compensate for a diode drop). + minimum: 0 + maximum: 1000000 + + required: + - gw,mode + - reg + - label + + required: + - compatible + - "#address-cells" + - "#size-cells" + +patternProperties: + "^fan-controller@[0-9a-f]+$": + type: object + description: Optional fan controller + + properties: + compatible: + const: gw,gsc-fan + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + description: The fan controller base address + maxItems: 1 + + required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - "#address-cells" + - "#size-cells" + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <4 GPIO_ACTIVE_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* A0: Board Temperature */ + reg = <0x00>; + label = "temp"; + gw,mode = <0>; + }; + + channel@2 { /* A1: Input Voltage (raw ADC) */ + reg = <0x02>; + label = "vdd_vin"; + gw,mode = <1>; + gw,voltage-divider-ohms = <22100 1000>; + gw,voltage-offset-microvolt = <800000>; + }; + + channel@b { /* A2: Battery voltage */ + reg = <0x0b>; + label = "vdd_bat"; + gw,mode = <1>; + }; + }; + + fan-controller@2c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "gw,gsc-fan"; + reg = <0x2c>; + }; + }; + }; diff --git a/Bindings/mfd/madera.txt b/Bindings/mfd/madera.txt deleted file mode 100644 index 47e2b8bc6051..000000000000 --- a/Bindings/mfd/madera.txt +++ /dev/null @@ -1,114 +0,0 @@ -Cirrus Logic Madera class audio codecs Multi-Functional Device - -These devices are audio SoCs with extensive digital capabilities and a range -of analogue I/O. - -See also the child driver bindings in: -bindings/pinctrl/cirrus,madera-pinctrl.txt -bindings/regulator/arizona-regulator.txt -bindings/sound/madera.txt - -Required properties: - - - compatible : One of the following chip-specific strings: - "cirrus,cs47l15" - "cirrus,cs47l35" - "cirrus,cs47l85" - "cirrus,cs47l90" - "cirrus,cs47l91" - "cirrus,cs42l92" - "cirrus,cs47l92" - "cirrus,cs47l93" - "cirrus,wm1840" - - - reg : I2C slave address when connected using I2C, chip select number when - using SPI. - - - DCVDD-supply : Power supply for the device as defined in - bindings/regulator/regulator.txt - Mandatory on CS47L15, CS47L35, CS47L90, CS47L91, CS42L92, CS47L92, CS47L93 - Optional on CS47L85, WM1840 - - - AVDD-supply, DBVDD1-supply, DBVDD2-supply, CPVDD1-supply, CPVDD2-supply : - Power supplies for the device - - - DBVDD3-supply, DBVDD4-supply : Power supplies for the device - (CS47L85, CS47L90, CS47L91, WM1840) - - - SPKVDDL-supply, SPKVDDR-supply : Power supplies for the device - (CS47L85, WM1840) - - - SPKVDD-supply : Power supply for the device - (CS47L15, CS47L35) - - - interrupt-controller : Indicates that this device is an interrupt controller - - - #interrupt-cells: the number of cells to describe an IRQ, must be 2. - The first cell is the IRQ number. - The second cell is the flags, encoded as the trigger masks from - bindings/interrupt-controller/interrupts.txt - - - gpio-controller : Indicates this device is a GPIO controller. - - - #gpio-cells : Must be 2. The first cell is the pin number. The second cell - is reserved for future use and must be zero - - - interrupt-parent : The parent interrupt controller. - - - interrupts : The interrupt line the /IRQ signal for the device is - connected to. - -Optional properties: - - - MICVDD-supply : Power supply, only need to be specified if - powered externally - - - reset-gpios : One entry specifying the GPIO controlling /RESET. - As defined in bindings/gpio.txt. - Although optional, it is strongly recommended to use a hardware reset - - - clocks: Should reference the clocks supplied on MCLK1, MCLK2 and MCLK3 - - clock-names: May contain up to three strings: - "mclk1" for the clock supplied on MCLK1, recommended to be a high - quality audio reference clock - "mclk2" for the clock supplied on MCLK2, required to be an always on - 32k clock - "mclk3" for the clock supplied on MCLK3 - - - MICBIASx : Initial data for the MICBIAS regulators, as covered in - Documentation/devicetree/bindings/regulator/regulator.txt. - One for each MICBIAS generator (MICBIAS1, MICBIAS2, ...) - (all codecs) - - One for each output pin (MICBIAS1A, MIBCIAS1B, MICBIAS2A, ...) - (all except CS47L85, WM1840) - - The following following additional property is supported for the generator - nodes: - - cirrus,ext-cap : Set to 1 if the MICBIAS has external decoupling - capacitors attached. - -Optional child nodes: - micvdd : Node containing initialization data for the micvdd regulator - See bindings/regulator/arizona-regulator.txt - - ldo1 : Node containing initialization data for the LDO1 regulator - See bindings/regulator/arizona-regulator.txt - (cs47l85, wm1840) - -Example: - -cs47l85@0 { - compatible = "cirrus,cs47l85"; - reg = <0>; - - reset-gpios = <&gpio 0>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <&host_irq1>; - interrupt-parent = <&gic>; - - gpio-controller; - #gpio-cells = <2>; -}; diff --git a/Bindings/mfd/max8998.txt b/Bindings/mfd/max8998.txt index 5f2f07c09c90..4ed52184d081 100644 --- a/Bindings/mfd/max8998.txt +++ b/Bindings/mfd/max8998.txt @@ -73,6 +73,8 @@ number as described in MAX8998 datasheet. - ESAFEOUT1: (ldo19) - ESAFEOUT2: (ld020) + - CHARGER: main battery charger current control + Standard regulator bindings are used inside regulator subnodes. Check Documentation/devicetree/bindings/regulator/regulator.txt for more details. @@ -113,5 +115,11 @@ Example: regulator-always-on; regulator-boot-on; }; + + charger_reg: CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <90000>; + regulator-max-microamp = <800000>; + }; }; }; diff --git a/Bindings/mfd/mps,mp2629.yaml b/Bindings/mfd/mps,mp2629.yaml new file mode 100644 index 000000000000..f91acc42d652 --- /dev/null +++ b/Bindings/mfd/mps,mp2629.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/mps,mp2629.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MP2629 Battery Charger PMIC from Monolithic Power System. + +maintainers: + - Saravanan Sekar + +description: | + MP2629 is a PMIC providing battery charging and power supply for smartphones, + wireless camera and portable devices. Chip is controlled over I2C. + + The battery charge management device handles battery charger controller and + ADC IIO device for battery, system voltage + +properties: + compatible: + const: mps,mp2629 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + description: + The first cell is the IRQ number, the second cell is the trigger type. + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@4b { + compatible = "mps,mp2629"; + reg = <0x4b>; + + interrupt-controller; + interrupt-parent = <&gpio2>; + #interrupt-cells = <2>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + }; + }; diff --git a/Bindings/mfd/mt6397.txt b/Bindings/mfd/mt6397.txt index a9b105ac00a8..2661775a3825 100644 --- a/Bindings/mfd/mt6397.txt +++ b/Bindings/mfd/mt6397.txt @@ -18,24 +18,30 @@ See the following for pwarp node definitions: This document describes the binding for MFD device and its sub module. Required properties: -compatible: "mediatek,mt6397" or "mediatek,mt6323" +compatible: + "mediatek,mt6323" for PMIC MT6323 + "mediatek,mt6358" for PMIC MT6358 + "mediatek,mt6397" for PMIC MT6397 Optional subnodes: - rtc Required properties: Should be one of follows - compatible: "mediatek,mt6323-rtc" + - compatible: "mediatek,mt6358-rtc" - compatible: "mediatek,mt6397-rtc" For details, see ../rtc/rtc-mt6397.txt - regulators Required properties: - - compatible: "mediatek,mt6397-regulator" - see ../regulator/mt6397-regulator.txt - compatible: "mediatek,mt6323-regulator" see ../regulator/mt6323-regulator.txt + - compatible: "mediatek,mt6358-regulator" + see ../regulator/mt6358-regulator.txt + - compatible: "mediatek,mt6397-regulator" + see ../regulator/mt6397-regulator.txt - codec Required properties: - - compatible: "mediatek,mt6397-codec" + - compatible: "mediatek,mt6397-codec" or "mediatek,mt6358-sound" - clk Required properties: - compatible: "mediatek,mt6397-clk" @@ -54,6 +60,11 @@ Optional subnodes: - compatible: "mediatek,mt6323-pwrc" For details, see ../power/reset/mt6323-poweroff.txt +- pin-controller + Required properties: + - compatible: "mediatek,mt6397-pinctrl" + For details, see ../pinctrl/pinctrl-mt65xx.txt + Example: pwrap: pwrap@1000f000 { compatible = "mediatek,mt8135-pwrap"; diff --git a/Bindings/mfd/st,stm32-lptimer.yaml b/Bindings/mfd/st,stm32-lptimer.yaml index ddf190cb800b..e675611f80d0 100644 --- a/Bindings/mfd/st,stm32-lptimer.yaml +++ b/Bindings/mfd/st,stm32-lptimer.yaml @@ -66,8 +66,8 @@ patternProperties: reg: description: Identify trigger hardware block. items: - minimum: 0 - maximum: 2 + minimum: 0 + maximum: 2 required: - compatible diff --git a/Bindings/mfd/st,stm32-timers.yaml b/Bindings/mfd/st,stm32-timers.yaml index 590849ee9f32..f212fc6e1661 100644 --- a/Bindings/mfd/st,stm32-timers.yaml +++ b/Bindings/mfd/st,stm32-timers.yaml @@ -67,23 +67,22 @@ properties: description: One or two to describe break input configurations. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-matrix - - items: - items: - - description: | - "index" indicates on which break input (0 or 1) the - configuration should be applied. - enum: [ 0 , 1] - - description: | - "level" gives the active level (0=low or 1=high) of the - input signal for this configuration - enum: [ 0, 1 ] - - description: | - "filter" gives the filtering value (up to 15) to be applied. - maximum: 15 - minItems: 1 - maxItems: 2 + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "index" indicates on which break input (0 or 1) the + configuration should be applied. + enum: [0, 1] + - description: | + "level" gives the active level (0=low or 1=high) of the + input signal for this configuration + enum: [0, 1] + - description: | + "filter" gives the filtering value (up to 15) to be applied. + maximum: 15 + minItems: 1 + maxItems: 2 required: - "#pwm-cells" @@ -102,8 +101,8 @@ patternProperties: reg: description: Identify trigger hardware block. items: - minimum: 0 - maximum: 16 + minimum: 0 + maximum: 16 required: - compatible diff --git a/Bindings/mfd/st,stpmic1.yaml b/Bindings/mfd/st,stpmic1.yaml index be7faa6dc055..dd995d7dc1a6 100644 --- a/Bindings/mfd/st,stpmic1.yaml +++ b/Bindings/mfd/st,stpmic1.yaml @@ -29,8 +29,7 @@ properties: onkey: type: object - allOf: - - $ref: ../input/input.yaml + $ref: ../input/input.yaml properties: compatible: @@ -68,8 +67,7 @@ properties: watchdog: type: object - allOf: - - $ref: ../watchdog/watchdog.yaml + $ref: ../watchdog/watchdog.yaml properties: compatible: @@ -190,8 +188,7 @@ properties: description: STPMIC1 voltage regulators supplies "^(buck[1-4]|ldo[1-6]|boost|vref_ddr|pwr_sw[1-2])$": - allOf: - - $ref: ../regulator/regulator.yaml + $ref: ../regulator/regulator.yaml "^ldo[1-2,5-6]$": type: object diff --git a/Bindings/mfd/syscon.yaml b/Bindings/mfd/syscon.yaml index 39375e4313d2..19bdaf781853 100644 --- a/Bindings/mfd/syscon.yaml +++ b/Bindings/mfd/syscon.yaml @@ -33,13 +33,13 @@ properties: compatible: anyOf: - items: - - enum: - - allwinner,sun8i-a83t-system-controller - - allwinner,sun8i-h3-system-controller - - allwinner,sun8i-v3s-system-controller - - allwinner,sun50i-a64-system-controller + - enum: + - allwinner,sun8i-a83t-system-controller + - allwinner,sun8i-h3-system-controller + - allwinner,sun8i-v3s-system-controller + - allwinner,sun50i-a64-system-controller - - const: syscon + - const: syscon - contains: const: syscon @@ -52,9 +52,8 @@ properties: description: | The size (in bytes) of the IO accesses that should be performed on the device. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 1, 2, 4, 8 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8] hwlocks: maxItems: 1 diff --git a/Bindings/mfd/wlf,arizona.yaml b/Bindings/mfd/wlf,arizona.yaml new file mode 100644 index 000000000000..4c0106cea36d --- /dev/null +++ b/Bindings/mfd/wlf,arizona.yaml @@ -0,0 +1,280 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/wlf,arizona.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic/Wolfson Microelectronics Arizona class audio SoCs + +maintainers: + - patches@opensource.cirrus.com + +description: | + These devices are audio SoCs with extensive digital capabilities and a + range of analogue I/O. + +allOf: + - $ref: /schemas/sound/wlf,arizona.yaml# + - $ref: /schemas/regulator/wlf,arizona.yaml# + - $ref: /schemas/extcon/wlf,arizona.yaml# + - if: + properties: + compatible: + contains: + enum: + - cirrus,cs47l24 + - wlf,wm1831 + then: + required: + - DCVDD-supply + - MICVDD-supply + else: + properties: + LDOVDD-supply: + description: + Digital power supply, used internally to generate DCVDD when + internally supplied. + + - if: + properties: + compatible: + contains: + enum: + - wlf,wm1814 + - wlf,wm5102 + - wlf,wm5110 + - wlf,wm8280 + - wlf,wm8997 + - wlf,wm8998 + then: + properties: + DBVDD2-supply: + description: + Databus power supply. + + required: + - DBVDD2-supply + - if: + properties: + compatible: + contains: + enum: + - wlf,wm1814 + - wlf,wm5102 + - wlf,wm5110 + - wlf,wm8280 + - wlf,wm8998 + then: + properties: + DBVDD3-supply: + description: + Databus power supply. + + required: + - DBVDD3-supply + - if: + properties: + compatible: + contains: + enum: + - cirrus,cs47l24 + - wlf,wm1831 + - wlf,wm8997 + then: + properties: + SPKVDD-supply: + description: + Mono speaker driver power supply. + + required: + - SPKVDD-supply + else: + properties: + SPKVDDL-supply: + description: + Left speaker driver power supply. + + SPKVDDR-supply: + description: + Right speaker driver power supply. + + required: + - SPKVDDL-supply + - SPKVDDR-supply + +properties: + compatible: + enum: + - cirrus,cs47l24 + - wlf,wm1814 + - wlf,wm1831 + - wlf,wm5102 + - wlf,wm5110 + - wlf,wm8280 + - wlf,wm8997 + - wlf,wm8998 + + reg: + maxItems: 1 + + AVDD-supply: + description: + Analogue power supply. + + CPVDD-supply: + description: + Charge pump power supply. + + DBVDD1-supply: + description: + Databus power supply. + + DCVDD-supply: + description: + Digital power supply, normally supplied internally except on cs47l24, + wm1831 where it is mandatory. + + MICVDD-supply: + description: + Microphone power supply, normally supplied internally except on + cs47l24, wm1831 where it is mandatory. + + gpio-controller: true + + '#gpio-cells': + description: + The first cell is the pin number and the second cell is used to + specify optional parameters. + const: 2 + + wlf,gpio-defaults: + description: + A list of GPIO configuration register values. Defines for the + appropriate values can found in dt-bindings/mfd/arizona.h. If + absent, no configuration of these registers is performed. If any + entry has a value that is out of range for a 16 bit register then the + chip default will be used. If present exactly five values must be + specified. + $ref: "/schemas/types.yaml#/definitions/uint32-array" + minItems: 1 + maxItems: 5 + + interrupt-controller: true + + '#interrupt-cells': + description: + The first cell is the IRQ number. The second cell is the flags, + encoded as trigger masks. + const: 2 + + interrupts: + maxItems: 1 + + clocks: + description: + Should reference the clocks supplied on MCLK1 and MCLK2. + minItems: 1 + maxItems: 2 + + clock-names: + description: + Should contains two strings mclk1 for the clock supplied on MCLK1, + recommended to be a high quality audio reference clock mclk2 for the + clock supplied on MCLK2, recommended to be an always on 32k clock. + oneOf: + - items: + - const: mclk1 + - items: + - const: mclk2 + - items: + - const: mclk1 + - const: mclk2 + + reset-gpios: + maxItems: 1 + + wlf,reset: + description: + GPIO specifier for the GPIO controlling RESET + deprecated: true + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + +required: + - compatible + - AVDD-supply + - CPVDD-supply + - DBVDD1-supply + - gpio-controller + - '#gpio-cells' + - interrupt-controller + - '#interrupt-cells' + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + i2c@e0004000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe0004000 0x1000>; + + wm5102: codec@1a { + compatible = "wlf,wm5102"; + reg = <0x1a>; + + reset-gpios = <&gpio 0>; + wlf,ldoena = <&gpio 1>; + + AVDD-supply = <&vdd1v8>; + DBVDD1-supply = <&vdd1v8>; + DBVDD2-supply = <&vdd1v8>; + DBVDD3-supply = <&vdd1v8>; + CPVDD-supply = <&vdd1v8>; + LDOVDD-supply = <&vdd1v8>; + SPKVDDL-supply = <&vdd5v>; + SPKVDDR-supply = <&vdd5v>; + + interrupts = <347>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + + gpio-controller; + #gpio-cells = <2>; + + #sound-dai-cells = <1>; + + wlf,gpio-defaults = < + ARIZONA_GP_FN_TXLRCLK + ARIZONA_GP_DEFAULT + ARIZONA_GP_DEFAULT + ARIZONA_GP_DEFAULT + ARIZONA_GP_DEFAULT + >; + + clocks = <&clks 0>, <&clks 1>; + clock-names = "mclk1", "mclk2"; + + wlf,inmode = ; + wlf,dmic-ref = ; + + wlf,use-jd2; + wlf,use-jd2-nopull; + wlf,jd-invert; + + wlf,micd-software-compare; + wlf,micd-detect-debounce = <0>; + wlf,micd-pol-gpio = <&codec 2 0>; + wlf,micd-rate = ; + wlf,micd-dbtime = <4>; + wlf,micd-timeout-ms = <100>; + wlf,micd-force-micbias; + wlf,micd-configs = <0 ARIZONA_DMIC_MICBIAS1 0>, + <0x2000 ARIZONA_DMIC_MICBIAS2 1>; + + wlf,gpsw = ; + }; + }; diff --git a/Bindings/mips/ingenic/devices.yaml b/Bindings/mips/ingenic/devices.yaml index 78dcf6ef3883..d1175030781a 100644 --- a/Bindings/mips/ingenic/devices.yaml +++ b/Bindings/mips/ingenic/devices.yaml @@ -20,16 +20,20 @@ properties: - description: Qi Hardware Ben NanoNote items: - const: qi,lb60 + - const: ingenic,jz4740 - description: Game Consoles Worldwide GCW Zero items: - const: gcw,zero + - const: ingenic,jz4770 - description: MIPS Creator CI20 items: - const: img,ci20 + - const: ingenic,jz4780 - description: YSH & ATIL General Board CU Neo items: - const: yna,cu1000-neo + - const: ingenic,x1000 ... diff --git a/Bindings/mips/loongson/rs780e-acpi.yaml b/Bindings/mips/loongson/rs780e-acpi.yaml new file mode 100644 index 000000000000..d317897e1115 --- /dev/null +++ b/Bindings/mips/loongson/rs780e-acpi.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mips/loongson/rs780e-acpi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Loongson RS780E PCH ACPI Controller + +maintainers: + - Jiaxun Yang + +description: | + This controller can be found in Loongson-3 systems with RS780E PCH. + +properties: + compatible: + const: loongson,rs780e-acpi + + reg: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + isa@0 { + compatible = "isa"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0 0x1000>; + + acpi@800 { + compatible = "loongson,rs780e-acpi"; + reg = <1 0x800 0x100>; + }; + }; + +... diff --git a/Bindings/misc/olpc,xo1.75-ec.txt b/Bindings/misc/olpc,xo1.75-ec.txt index 8c4d649cdd8f..2d7cdf19a0d0 100644 --- a/Bindings/misc/olpc,xo1.75-ec.txt +++ b/Bindings/misc/olpc,xo1.75-ec.txt @@ -8,7 +8,7 @@ The embedded controller requires the SPI controller driver to signal readiness to receive a transfer (that is, when TX FIFO contains the response data) by strobing the ACK pin with the ready signal. See the "ready-gpios" property of the SSP binding as documented in: -. +. Example: &ssp3 { diff --git a/Bindings/mmc/amlogic,meson-mx-sdhc.yaml b/Bindings/mmc/amlogic,meson-mx-sdhc.yaml new file mode 100644 index 000000000000..7a386a5b8fcb --- /dev/null +++ b/Bindings/mmc/amlogic,meson-mx-sdhc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdhc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson SDHC controller Device Tree Bindings + +allOf: + - $ref: "mmc-controller.yaml" + +maintainers: + - Martin Blumenstingl + +description: | + The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC + card interface with 1/4/8-bit bus width. + It supports eMMC spec 4.4x/4.5x including HS200 (up to 100MHz clock). + +properties: + compatible: + items: + - enum: + - amlogic,meson8-sdhc + - amlogic,meson8b-sdhc + - amlogic,meson8m2-sdhc + - const: amlogic,meson-mx-sdhc + + reg: + minItems: 1 + + interrupts: + minItems: 1 + + clocks: + minItems: 5 + + clock-names: + items: + - const: clkin0 + - const: clkin1 + - const: clkin2 + - const: clkin3 + - const: pclk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + #include + #include + + sdhc: mmc@8e00 { + compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; + reg = <0x8e00 0x42>; + interrupts = ; + clocks = <&xtal>, + <&fclk_div4>, + <&fclk_div3>, + <&fclk_div5>, + <&sdhc_pclk>; + clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; + }; diff --git a/Bindings/mmc/arasan,sdhci.txt b/Bindings/mmc/arasan,sdhci.txt index 428685eb2ded..f29bf7dd2ece 100644 --- a/Bindings/mmc/arasan,sdhci.txt +++ b/Bindings/mmc/arasan,sdhci.txt @@ -18,12 +18,21 @@ Required Properties: - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY For this device it is strongly suggested to include clock-output-names and #clock-cells. + - "xlnx,versal-8.9a": Versal SDHCI 8.9a PHY + For this device it is strongly suggested to include clock-output-names and + #clock-cells. - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY Note: This binding has been deprecated and moved to [5]. - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY For this device it is strongly suggested to include arasan,soc-ctl-syscon. - "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY For this device it is strongly suggested to include arasan,soc-ctl-syscon. + - "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel Keem Bay eMMC + For this device it is strongly suggested to include arasan,soc-ctl-syscon. + - "intel,keembay-sdhci-5.1-sd": Intel Keem Bay SD controller + For this device it is strongly suggested to include arasan,soc-ctl-syscon. + - "intel,keembay-sdhci-5.1-sdio": Intel Keem Bay SDIO controller + For this device it is strongly suggested to include arasan,soc-ctl-syscon. [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt @@ -104,6 +113,18 @@ Example: clk-phase-sd-hs = <63>, <72>; }; + sdhci: mmc@f1040000 { + compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; + interrupt-parent = <&gic>; + interrupts = <0 126 4>; + reg = <0x0 0xf1040000 0x0 0x10000>; + clocks = <&clk200>, <&clk200>; + clock-names = "clk_xin", "clk_ahb"; + clock-output-names = "clk_out_sd0", "clk_in_sd0"; + #clock-cells = <1>; + clk-phase-sd-hs = <132>, <60>; + }; + emmc: sdhci@ec700000 { compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1"; reg = <0xec700000 0x300>; @@ -133,3 +154,39 @@ Example: phy-names = "phy_arasan"; arasan,soc-ctl-syscon = <&sysconf>; }; + + mmc: mmc@33000000 { + compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1"; + interrupts = ; + reg = <0x0 0x33000000 0x0 0x300>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>, + <&scmi_clk KEEM_BAY_PSS_EMMC>; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>; + assigned-clock-rates = <200000000>; + clock-output-names = "emmc_cardclock"; + #clock-cells = <0>; + arasan,soc-ctl-syscon = <&mmc_phy_syscon>; + }; + + sd0: mmc@31000000 { + compatible = "intel,keembay-sdhci-5.1-sd"; + interrupts = ; + reg = <0x0 0x31000000 0x0 0x300>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>, + <&scmi_clk KEEM_BAY_PSS_SD0>; + arasan,soc-ctl-syscon = <&sd0_phy_syscon>; + }; + + sd1: mmc@32000000 { + compatible = "intel,keembay-sdhci-5.1-sdio"; + interrupts = ; + reg = <0x0 0x32000000 0x0 0x300>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>, + <&scmi_clk KEEM_BAY_PSS_SD1>; + arasan,soc-ctl-syscon = <&sd1_phy_syscon>; + }; diff --git a/Bindings/mmc/aspeed,sdhci.yaml b/Bindings/mmc/aspeed,sdhci.yaml index 200de9396036..987b287f3bff 100644 --- a/Bindings/mmc/aspeed,sdhci.yaml +++ b/Bindings/mmc/aspeed,sdhci.yaml @@ -41,8 +41,8 @@ properties: patternProperties: "^sdhci@[0-9a-f]+$": type: object - allOf: - - $ref: mmc-controller.yaml + $ref: mmc-controller.yaml + properties: compatible: enum: diff --git a/Bindings/mmc/cdns,sdhci.yaml b/Bindings/mmc/cdns,sdhci.yaml index 2f45dd0d04db..d93f7794a85f 100644 --- a/Bindings/mmc/cdns,sdhci.yaml +++ b/Bindings/mmc/cdns,sdhci.yaml @@ -17,7 +17,7 @@ properties: compatible: items: - enum: - - socionext,uniphier-sd4hc + - socionext,uniphier-sd4hc - const: cdns,sd4hc reg: @@ -36,91 +36,80 @@ properties: cdns,phy-input-delay-sd-highspeed: description: Value of the delay in the input path for SD high-speed timing - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - - maximum: 0x1f + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 0x1f cdns,phy-input-delay-legacy: description: Value of the delay in the input path for legacy timing - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - - maximum: 0x1f + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 0x1f cdns,phy-input-delay-sd-uhs-sdr12: description: Value of the delay in the input path for SD UHS SDR12 timing - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - - maximum: 0x1f + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 0x1f cdns,phy-input-delay-sd-uhs-sdr25: description: Value of the delay in the input path for SD UHS SDR25 timing - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - - maximum: 0x1f + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 0x1f cdns,phy-input-delay-sd-uhs-sdr50: description: Value of the delay in the input path for SD UHS SDR50 timing - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - - maximum: 0x1f + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 0x1f cdns,phy-input-delay-sd-uhs-ddr50: description: Value of the delay in the input path for SD UHS DDR50 timing - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - - maximum: 0x1f + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 0x1f cdns,phy-input-delay-mmc-highspeed: description: Value of the delay in the input path for MMC high-speed timing - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - - maximum: 0x1f + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 0x1f cdns,phy-input-delay-mmc-ddr: description: Value of the delay in the input path for eMMC high-speed DDR timing - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - - maximum: 0x1f # PHY DLL clock delays: # Each delay property represents the fraction of the clock period. # The approximate delay value will be # (/128)*sdmclk_clock_period. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 0x1f cdns,phy-dll-delay-sdclk: description: | Value of the delay introduced on the sdclk output for all modes except HS200, HS400 and HS400_ES. - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - - maximum: 0x7f + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 0x7f cdns,phy-dll-delay-sdclk-hsmmc: description: | Value of the delay introduced on the sdclk output for HS200, HS400 and HS400_ES speed modes. - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - - maximum: 0x7f + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 0x7f cdns,phy-dll-delay-strobe: description: | Value of the delay introduced on the dat_strobe input used in HS400 / HS400_ES speed modes. - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - - maximum: 0x7f + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 0x7f required: - compatible diff --git a/Bindings/mmc/ingenic,mmc.yaml b/Bindings/mmc/ingenic,mmc.yaml new file mode 100644 index 000000000000..e60bfe980ab3 --- /dev/null +++ b/Bindings/mmc/ingenic,mmc.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/ingenic,mmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs MMC Controller DT bindings + +maintainers: + - Paul Cercueil + +allOf: + - $ref: mmc-controller.yaml# + +properties: + compatible: + oneOf: + - enum: + - ingenic,jz4740-mmc + - ingenic,jz4725b-mmc + - ingenic,jz4760-mmc + - ingenic,jz4780-mmc + - ingenic,x1000-mmc + - items: + - const: ingenic,jz4770-mmc + - const: ingenic,jz4760-mmc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: mmc + + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + + dma-names: + items: + - const: rx + - const: tx + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + +examples: + - | + #include + #include + mmc0: mmc@13450000 { + compatible = "ingenic,jz4780-mmc"; + reg = <0x13450000 0x1000>; + + interrupt-parent = <&intc>; + interrupts = <37>; + + clocks = <&cgu JZ4780_CLK_MSC0>; + clock-names = "mmc"; + + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>, + <&dma JZ4780_DMA_MSC0_TX 0xffffffff>; + dma-names = "rx", "tx"; + }; diff --git a/Bindings/mmc/jz4740.txt b/Bindings/mmc/jz4740.txt deleted file mode 100644 index 453d3b9d145d..000000000000 --- a/Bindings/mmc/jz4740.txt +++ /dev/null @@ -1,41 +0,0 @@ -* Ingenic XBurst MMC controllers - -This file documents the device tree properties used for the MMC controller in -Ingenic JZ4740/JZ4760/JZ4780/X1000 SoCs. These are in addition to the core MMC -properties described in mmc.txt. - -Required properties: -- compatible: Should be one of the following: - - "ingenic,jz4740-mmc" for the JZ4740 - - "ingenic,jz4725b-mmc" for the JZ4725B - - "ingenic,jz4760-mmc" for the JZ4760 - - "ingenic,jz4780-mmc" for the JZ4780 - - "ingenic,x1000-mmc" for the X1000 -- reg: Should contain the MMC controller registers location and length. -- interrupts: Should contain the interrupt specifier of the MMC controller. -- clocks: Clock for the MMC controller. - -Optional properties: -- dmas: List of DMA specifiers with the controller specific format - as described in the generic DMA client binding. A tx and rx - specifier is required. -- dma-names: RX and TX DMA request names. - Should be "rx" and "tx", in that order. - -For additional details on DMA client bindings see ../dma/dma.txt. - -Example: - -mmc0: mmc@13450000 { - compatible = "ingenic,jz4780-mmc"; - reg = <0x13450000 0x1000>; - - interrupt-parent = <&intc>; - interrupts = <37>; - - clocks = <&cgu JZ4780_CLK_MSC0>; - clock-names = "mmc"; - - dmas = <&dma JZ4780_DMA_MSC0_RX 0xffffffff>, <&dma JZ4780_DMA_MSC0_TX 0xffffffff>; - dma-names = "rx", "tx"; -}; diff --git a/Bindings/mmc/mmc-controller.yaml b/Bindings/mmc/mmc-controller.yaml index acc9f10871d4..4931fab34d81 100644 --- a/Bindings/mmc/mmc-controller.yaml +++ b/Bindings/mmc/mmc-controller.yaml @@ -76,20 +76,18 @@ properties: # Other properties bus-width: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [1, 4, 8] - default: 1 description: Number of data lines. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 4, 8] + default: 1 max-frequency: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 400000 - - maximum: 200000000 description: Maximum operating frequency of the bus. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 400000 + maximum: 200000000 disable-wp: $ref: /schemas/types.yaml#/definitions/flag @@ -212,13 +210,12 @@ properties: eMMC HS400 enhanced strobe mode is supported dsr: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - - maximum: 0xffff description: Value the card Driver Stage Register (DSR) should be programmed with. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 0xffff no-sdio: $ref: /schemas/types.yaml#/definitions/flag @@ -238,25 +235,23 @@ properties: initialization. fixed-emmc-driver-type: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - - maximum: 4 description: For non-removable eMMC, enforce this driver type. The value is the driver type as specified in the eMMC specification (table 206 in spec version 5.1) + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 4 post-power-on-delay-ms: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - default: 10 description: It was invented for MMC pwrseq-simple which could be referred to mmc-pwrseq-simple.txt. But now it\'s reused as a tunable delay waiting for I/O signalling and card power supply to be stable, regardless of whether pwrseq-simple is used. Default to 10ms if no available. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 10 supports-cqe: $ref: /schemas/types.yaml#/definitions/flag @@ -333,8 +328,8 @@ patternProperties: - reg "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$": - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 maxItems: 2 items: diff --git a/Bindings/mmc/owl-mmc.yaml b/Bindings/mmc/owl-mmc.yaml index 12b40213426d..1380501fb8f0 100644 --- a/Bindings/mmc/owl-mmc.yaml +++ b/Bindings/mmc/owl-mmc.yaml @@ -47,7 +47,7 @@ examples: - | mmc0: mmc@e0330000 { compatible = "actions,owl-mmc"; - reg = <0x0 0xe0330000 0x0 0x4000>; + reg = <0xe0330000 0x4000>; interrupts = <0 42 4>; clocks = <&cmu 56>; resets = <&cmu 23>; diff --git a/Bindings/mmc/renesas,mmcif.txt b/Bindings/mmc/renesas,mmcif.txt index c064af5838aa..291532ac0446 100644 --- a/Bindings/mmc/renesas,mmcif.txt +++ b/Bindings/mmc/renesas,mmcif.txt @@ -11,6 +11,7 @@ Required properties: - "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs - "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs - "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs + - "renesas,mmcif-r8a7742" for the MMCIF found in r8a7742 SoCs - "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs - "renesas,mmcif-r8a7744" for the MMCIF found in r8a7744 SoCs - "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs @@ -24,8 +25,8 @@ Required properties: - interrupts: Some SoCs have only 1 shared interrupt, while others have either 2 or 3 individual interrupts (error, int, card detect). Below is the number of interrupts for each SoC: - 1: r8a73a4, r8a7743, r8a7744, r8a7745, r8a7778, r8a7790, r8a7791, r8a7793, - r8a7794 + 1: r8a73a4, r8a7742, r8a7743, r8a7744, r8a7745, r8a7778, r8a7790, r8a7791, + r8a7793, r8a7794 2: r8a7740, sh73a0 3: r7s72100 diff --git a/Bindings/mmc/renesas,sdhi.txt b/Bindings/mmc/renesas,sdhi.txt index e6cc47844207..0ca9a622cce0 100644 --- a/Bindings/mmc/renesas,sdhi.txt +++ b/Bindings/mmc/renesas,sdhi.txt @@ -7,6 +7,7 @@ Required properties: "renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC + "renesas,sdhi-r8a7742" - SDHI IP on R8A7742 SoC "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC "renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC diff --git a/Bindings/mmc/rockchip-dw-mshc.yaml b/Bindings/mmc/rockchip-dw-mshc.yaml index 89c3edd6a728..01316185e771 100644 --- a/Bindings/mmc/rockchip-dw-mshc.yaml +++ b/Bindings/mmc/rockchip-dw-mshc.yaml @@ -30,21 +30,21 @@ properties: - items: - enum: # for Rockchip PX30 - - rockchip,px30-dw-mshc + - rockchip,px30-dw-mshc # for Rockchip RK3036 - - rockchip,rk3036-dw-mshc + - rockchip,rk3036-dw-mshc # for Rockchip RK322x - - rockchip,rk3228-dw-mshc + - rockchip,rk3228-dw-mshc # for Rockchip RK3308 - - rockchip,rk3308-dw-mshc + - rockchip,rk3308-dw-mshc # for Rockchip RK3328 - - rockchip,rk3328-dw-mshc + - rockchip,rk3328-dw-mshc # for Rockchip RK3368 - - rockchip,rk3368-dw-mshc + - rockchip,rk3368-dw-mshc # for Rockchip RK3399 - - rockchip,rk3399-dw-mshc + - rockchip,rk3399-dw-mshc # for Rockchip RV1108 - - rockchip,rv1108-dw-mshc + - rockchip,rv1108-dw-mshc - const: rockchip,rk3288-dw-mshc reg: @@ -76,8 +76,7 @@ properties: high speed modes. rockchip,default-sample-phase: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 360 default: 0 @@ -87,8 +86,7 @@ properties: If not specified 0 deg will be used. rockchip,desired-num-phases: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 360 default: 360 @@ -111,7 +109,7 @@ examples: #include sdmmc: mmc@ff0c0000 { compatible = "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xff0c0000 0x0 0x4000>; + reg = <0xff0c0000 0x4000>; interrupts = ; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; diff --git a/Bindings/mmc/sdhci-msm.txt b/Bindings/mmc/sdhci-msm.txt index 5445931c5ab9..b8e1d2b7aea9 100644 --- a/Bindings/mmc/sdhci-msm.txt +++ b/Bindings/mmc/sdhci-msm.txt @@ -17,6 +17,7 @@ Required properties: "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4" "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4" "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4" + "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5" "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5" "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5" "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; @@ -46,6 +47,13 @@ Required properties: "cal" - reference clock for RCLK delay calibration (optional) "sleep" - sleep clock for RCLK delay calibration (optional) +- qcom,ddr-config: Certain chipsets and platforms require particular settings + for the DDR_CONFIG register. Use this field to specify the register + value as per the Hardware Programming Guide. + +- qcom,dll-config: Chipset and Platform specific value. Use this field to + specify the DLL_CONFIG register value as per Hardware Programming Guide. + Example: sdhc_1: sdhci@f9824900 { @@ -63,6 +71,9 @@ Example: clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; clock-names = "core", "iface"; + + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040868>; }; sdhc_2: sdhci@f98a4900 { @@ -80,4 +91,7 @@ Example: clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; clock-names = "core", "iface"; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; }; diff --git a/Bindings/mmc/sdhci-pxa.txt b/Bindings/mmc/sdhci-pxa.txt deleted file mode 100644 index 3d1b449d6097..000000000000 --- a/Bindings/mmc/sdhci-pxa.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Marvell sdhci-pxa v2/v3 controller - -This file documents differences between the core properties in mmc.txt -and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers. - -Required properties: -- compatible: Should be "mrvl,pxav2-mmc", "mrvl,pxav3-mmc" or - "marvell,armada-380-sdhci". -- reg: - * for "mrvl,pxav2-mmc" and "mrvl,pxav3-mmc", one register area for - the SDHCI registers. - - * for "marvell,armada-380-sdhci", three register areas. The first - one for the SDHCI registers themselves, the second one for the - AXI/Mbus bridge registers of the SDHCI unit, the third one for the - SDIO3 Configuration register -- reg names: should be "sdhci", "mbus", "conf-sdio3". only mandatory - for "marvell,armada-380-sdhci" -- clocks: Array of clocks required for SDHCI; requires at least one for - I/O clock. -- clock-names: Array of names corresponding to clocks property; shall be - "io" for I/O clock and "core" for optional core clock. - -Optional properties: -- mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning. - -Example: - -sdhci@d4280800 { - compatible = "mrvl,pxav3-mmc"; - reg = <0xd4280800 0x800>; - bus-width = <8>; - interrupts = <27>; - clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; - clock-names = "io", "core"; - non-removable; - mrvl,clk-delay-cycles = <31>; -}; - -sdhci@d8000 { - compatible = "marvell,armada-380-sdhci"; - reg-names = "sdhci", "mbus", "conf-sdio3"; - reg = <0xd8000 0x1000>, - <0xdc000 0x100>; - <0x18454 0x4>; - interrupts = <0 25 0x4>; - clocks = <&gateclk 17>; - clock-names = "io"; - mrvl,clk-delay-cycles = <0x1F>; -}; diff --git a/Bindings/mmc/sdhci-pxa.yaml b/Bindings/mmc/sdhci-pxa.yaml new file mode 100644 index 000000000000..a58715c860b7 --- /dev/null +++ b/Bindings/mmc/sdhci-pxa.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA SDHCI v2/v3 bindings + +maintainers: + - Ulf Hansson + +allOf: + - $ref: mmc-controller.yaml# + - if: + properties: + compatible: + contains: + const: marvell,armada-380-sdhci + then: + properties: + regs: + minItems: 3 + reg-names: + minItems: 3 + required: + - reg-names + else: + properties: + regs: + maxItems: 1 + reg-names: + maxItems: 1 + +properties: + compatible: + enum: + - mrvl,pxav2-mmc + - mrvl,pxav3-mmc + - marvell,armada-380-sdhci + + reg: + minItems: 1 + maxItems: 3 + + reg-names: + items: + - const: sdhci + - const: mbus + - const: conf-sdio3 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: io + - const: core + + mrvl,clk-delay-cycles: + description: Specify a number of cycles to delay for tuning. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + #include + mmc@d4280800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4280800 0x800>; + bus-width = <8>; + interrupts = <27>; + clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; + clock-names = "io", "core"; + non-removable; + mrvl,clk-delay-cycles = <31>; + }; + - | + mmc@d8000 { + compatible = "marvell,armada-380-sdhci"; + reg-names = "sdhci", "mbus", "conf-sdio3"; + reg = <0xd8000 0x1000>, + <0xdc000 0x100>, + <0x18454 0x4>; + interrupts = <0 25 0x4>; + clocks = <&gateclk 17>; + clock-names = "io"; + mrvl,clk-delay-cycles = <0x1F>; + }; + +... diff --git a/Bindings/mmc/socionext,uniphier-sd.yaml b/Bindings/mmc/socionext,uniphier-sd.yaml index cdfac9b4411b..8d6413f48823 100644 --- a/Bindings/mmc/socionext,uniphier-sd.yaml +++ b/Bindings/mmc/socionext,uniphier-sd.yaml @@ -35,15 +35,15 @@ properties: oneOf: - const: host - items: - - const: host - - const: bridge + - const: host + - const: bridge - items: - - const: host - - const: hw + - const: host + - const: hw - items: - - const: host - - const: bridge - - const: hw + - const: host + - const: bridge + - const: hw resets: minItems: 1 diff --git a/Bindings/mmc/synopsys-dw-mshc-common.yaml b/Bindings/mmc/synopsys-dw-mshc-common.yaml index 890d47a87ac5..85bd528e9a14 100644 --- a/Bindings/mmc/synopsys-dw-mshc-common.yaml +++ b/Bindings/mmc/synopsys-dw-mshc-common.yaml @@ -27,39 +27,35 @@ properties: clock to this at probe time. fifo-depth: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 description: The maximum size of the tx/rx fifo's. If this property is not specified, the default value of the fifo size is determined from the controller registers. + $ref: /schemas/types.yaml#/definitions/uint32 card-detect-delay: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - default: 0 description: Delay in milli-seconds before detecting card after card insert event. The default value is 0. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 data-addr: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 description: Override fifo address with value provided by DT. The default FIFO reg offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A) by driver. If the controller does not follow this rule, please use this property to set fifo address in device tree. + $ref: /schemas/types.yaml#/definitions/uint32 fifo-watermark-aligned: - allOf: - - $ref: /schemas/types.yaml#/definitions/flag description: Data done irq is expected if data length is less than watermark in PIO mode. But fifo watermark is requested to be aligned with data length in some SoC so that TX/RX irq can be generated with data done irq. Add this watermark quirk to mark this requirement and force fifo watermark setting accordingly. + $ref: /schemas/types.yaml#/definitions/flag dmas: maxItems: 1 diff --git a/Bindings/mtd/allwinner,sun4i-a10-nand.yaml b/Bindings/mtd/allwinner,sun4i-a10-nand.yaml index 5d3fa412aabd..c033ac3f147d 100644 --- a/Bindings/mtd/allwinner,sun4i-a10-nand.yaml +++ b/Bindings/mtd/allwinner,sun4i-a10-nand.yaml @@ -75,13 +75,12 @@ patternProperties: allwinner,rb: description: Contains the native Ready/Busy IDs. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 1 - maxItems: 2 - items: - minimum: 0 - maximum: 1 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 1 additionalProperties: false diff --git a/Bindings/mtd/arasan,nand-controller.yaml b/Bindings/mtd/arasan,nand-controller.yaml new file mode 100644 index 000000000000..cb9794edff24 --- /dev/null +++ b/Bindings/mtd/arasan,nand-controller.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/arasan,nand-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arasan NAND Flash Controller with ONFI 3.1 support device tree bindings + +allOf: + - $ref: "nand-controller.yaml" + +maintainers: + - Naga Sureshkumar Relli + +properties: + compatible: + oneOf: + - items: + - enum: + - xlnx,zynqmp-nand-controller + - enum: + - arasan,nfc-v3p10 + + reg: + maxItems: 1 + + clocks: + items: + - description: Controller clock + - description: NAND bus clock + + clock-names: + items: + - const: controller + - const: bus + + interrupts: + maxItems: 1 + + "#address-cells": true + "#size-cells": true + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: true + +examples: + - | + nfc: nand-controller@ff100000 { + compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; + reg = <0xff100000 0x1000>; + clock-names = "controller", "bus"; + clocks = <&clk200>, <&clk100>; + interrupt-parent = <&gic>; + interrupts = <0 14 4>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Bindings/mtd/brcm,brcmnand.txt b/Bindings/mtd/brcm,brcmnand.txt index 05651a654c66..44335a4f8bfb 100644 --- a/Bindings/mtd/brcm,brcmnand.txt +++ b/Bindings/mtd/brcm,brcmnand.txt @@ -20,6 +20,8 @@ Required properties: "brcm,brcmnand" and an appropriate version compatibility string, like "brcm,brcmnand-v7.0" Possible values: + brcm,brcmnand-v2.1 + brcm,brcmnand-v2.2 brcm,brcmnand-v4.0 brcm,brcmnand-v5.0 brcm,brcmnand-v6.0 diff --git a/Bindings/mtd/denali,nand.yaml b/Bindings/mtd/denali,nand.yaml index 46e6b6726bc0..c07b91592cbd 100644 --- a/Bindings/mtd/denali,nand.yaml +++ b/Bindings/mtd/denali,nand.yaml @@ -54,8 +54,8 @@ properties: reg: register reset oneOf: - items: - - const: nand - - const: reg + - const: nand + - const: reg - const: nand - const: reg diff --git a/Bindings/mtd/ingenic,jz4780-nand.txt b/Bindings/mtd/ingenic,jz4780-nand.txt deleted file mode 100644 index c02259353327..000000000000 --- a/Bindings/mtd/ingenic,jz4780-nand.txt +++ /dev/null @@ -1,92 +0,0 @@ -* Ingenic JZ4780 NAND/ECC - -This file documents the device tree bindings for NAND flash devices on the -JZ4780. NAND devices are connected to the NEMC controller (described in -memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must -be children of the NEMC node. - -Required NAND controller device properties: -- compatible: Should be one of: - * ingenic,jz4740-nand - * ingenic,jz4725b-nand - * ingenic,jz4780-nand -- reg: For each bank with a NAND chip attached, should specify a bank number, - an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank). - -Optional NAND controller device properties: -- ecc-engine: To make use of the hardware ECC controller, this - property must contain a phandle for the ECC controller node. The required - properties for this node are described below. If this is not specified, - software ECC will be used instead. - -Optional children nodes: -- Individual NAND chips are children of the NAND controller node. - -Required children node properties: -- reg: An integer ranging from 1 to 6 representing the CS line to use. - -Optional children node properties: -- nand-ecc-step-size: ECC block size in bytes. -- nand-ecc-strength: ECC strength (max number of correctable bits). -- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default -- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present false -- rb-gpios: GPIO specifier for the busy pin. -- wp-gpios: GPIO specifier for the write protect pin. - -Optional child node of NAND chip nodes: -- partitions: see Documentation/devicetree/bindings/mtd/partition.txt - -Example: - -nemc: nemc@13410000 { - ... - - nandc: nand-controller@1 { - compatible = "ingenic,jz4780-nand"; - reg = <1 0 0x1000000>; /* Bank 1 */ - - #address-cells = <1>; - #size-cells = <0>; - - ecc-engine = <&bch>; - - nand@1 { - reg = <1>; - - nand-ecc-step-size = <1024>; - nand-ecc-strength = <24>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - - rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>; - - partitions { - #address-cells = <2>; - #size-cells = <2>; - ... - } - }; - }; -}; - -The ECC controller is a separate SoC component used for error correction on -NAND devices. The following is a description of the device properties for a -ECC controller. - -Required ECC properties: -- compatible: Should be one of: - * ingenic,jz4740-ecc - * ingenic,jz4725b-bch - * ingenic,jz4780-bch -- reg: Should specify the ECC controller registers location and length. -- clocks: Clock for the ECC controller. - -Example: - -bch: bch@134d0000 { - compatible = "ingenic,jz4780-bch"; - reg = <0x134d0000 0x10000>; - - clocks = <&cgu JZ4780_CLK_BCH>; -}; diff --git a/Bindings/mtd/ingenic,nand.yaml b/Bindings/mtd/ingenic,nand.yaml new file mode 100644 index 000000000000..8abb6d463cb6 --- /dev/null +++ b/Bindings/mtd/ingenic,nand.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs NAND controller devicetree bindings + +maintainers: + - Paul Cercueil + +allOf: + - $ref: nand-controller.yaml# + +properties: + compatible: + enum: + - ingenic,jz4740-nand + - ingenic,jz4725b-nand + - ingenic,jz4780-nand + + reg: + items: + - description: Bank number, offset and size of first attached NAND chip + - description: Bank number, offset and size of second attached NAND chip + - description: Bank number, offset and size of third attached NAND chip + - description: Bank number, offset and size of fourth attached NAND chip + minItems: 1 + + ecc-engine: true + + partitions: + type: object + description: + Node containing description of fixed partitions. + See Documentation/devicetree/bindings/mtd/partition.txt + +patternProperties: + "^nand@[a-f0-9]$": + type: object + properties: + rb-gpios: + description: GPIO specifier for the busy pin. + maxItems: 1 + + wp-gpios: + description: GPIO specifier for the write-protect pin. + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + #include + memory-controller@13410000 { + compatible = "ingenic,jz4780-nemc"; + reg = <0x13410000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0x1b000000 0x1000000>, + <2 0 0x1a000000 0x1000000>, + <3 0 0x19000000 0x1000000>, + <4 0 0x18000000 0x1000000>, + <5 0 0x17000000 0x1000000>, + <6 0 0x16000000 0x1000000>; + + clocks = <&cgu JZ4780_CLK_NEMC>; + + nand-controller@1 { + compatible = "ingenic,jz4780-nand"; + reg = <1 0 0x1000000>; + + #address-cells = <1>; + #size-cells = <0>; + + ecc-engine = <&bch>; + + ingenic,nemc-tAS = <10>; + ingenic,nemc-tAH = <5>; + ingenic,nemc-tBP = <10>; + ingenic,nemc-tAW = <15>; + ingenic,nemc-tSTRV = <100>; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_nemc>; + + nand@1 { + reg = <1>; + + nand-ecc-step-size = <1024>; + nand-ecc-strength = <24>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_nemc_cs1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x0 0x0 0x800000>; + }; + + partition@800000 { + label = "u-boot"; + reg = <0x0 0x800000 0x0 0x200000>; + }; + + partition@a00000 { + label = "u-boot-env"; + reg = <0x0 0xa00000 0x0 0x200000>; + }; + + partition@c00000 { + label = "boot"; + reg = <0x0 0xc00000 0x0 0x4000000>; + }; + + partition@4c00000 { + label = "system"; + reg = <0x0 0x4c00000 0x1 0xfb400000>; + }; + }; + }; + }; + }; diff --git a/Bindings/mtd/nand-controller.yaml b/Bindings/mtd/nand-controller.yaml index d261b7096c69..cde7c4d79efe 100644 --- a/Bindings/mtd/nand-controller.yaml +++ b/Bindings/mtd/nand-controller.yaml @@ -47,29 +47,26 @@ patternProperties: Contains the native Ready/Busy IDs. nand-ecc-mode: - allOf: - - $ref: /schemas/types.yaml#/definitions/string - - enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ] description: Desired ECC engine, either hardware (most of the time embedded in the NAND controller) or software correction (Linux will handle the calculations). soft_bch is deprecated and should be replaced by soft and nand-ecc-algo. + $ref: /schemas/types.yaml#/definitions/string + enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die] nand-ecc-algo: - allOf: - - $ref: /schemas/types.yaml#/definitions/string - - enum: [ hamming, bch, rs ] description: Desired ECC algorithm. + $ref: /schemas/types.yaml#/definitions/string + enum: [hamming, bch, rs] nand-bus-width: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 8, 16 ] - - default: 8 description: Bus width to the NAND chip + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16] + default: 8 nand-on-flash-bbt: $ref: /schemas/types.yaml#/definitions/flag @@ -83,18 +80,16 @@ patternProperties: build a volatile BBT in RAM. nand-ecc-strength: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 1 description: Maximum number of bits that can be corrected per ECC step. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 nand-ecc-step-size: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 1 description: Number of data bytes covered by a single ECC step. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 nand-ecc-maximize: $ref: /schemas/types.yaml#/definitions/flag diff --git a/Bindings/mtd/partition.txt b/Bindings/mtd/partition.txt index afbbd870496d..4a39698221a2 100644 --- a/Bindings/mtd/partition.txt +++ b/Bindings/mtd/partition.txt @@ -61,6 +61,9 @@ Optional properties: clobbered. - lock : Do not unlock the partition at initialization time (not supported on all devices) +- slc-mode: This parameter, if present, allows one to emulate SLC mode on a + partition attached to an MLC NAND thus making this partition immune to + paired-pages corruptions Examples: diff --git a/Bindings/net/allwinner,sun8i-a83t-emac.yaml b/Bindings/net/allwinner,sun8i-a83t-emac.yaml index db36b4d86484..c7c9ad4e3f9f 100644 --- a/Bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -19,8 +19,8 @@ properties: - const: allwinner,sun8i-v3s-emac - const: allwinner,sun50i-a64-emac - items: - - const: allwinner,sun50i-h6-emac - - const: allwinner,sun50i-a64-emac + - const: allwinner,sun50i-h6-emac + - const: allwinner,sun50i-a64-emac reg: maxItems: 1 diff --git a/Bindings/net/amlogic,meson-dwmac.yaml b/Bindings/net/amlogic,meson-dwmac.yaml index ae91aa9d8616..64c20c92c07d 100644 --- a/Bindings/net/amlogic,meson-dwmac.yaml +++ b/Bindings/net/amlogic,meson-dwmac.yaml @@ -40,18 +40,22 @@ allOf: then: properties: clocks: + minItems: 3 + maxItems: 4 items: - description: GMAC main clock - description: First parent clock of the internal mux - description: Second parent clock of the internal mux + - description: The clock which drives the timing adjustment logic clock-names: minItems: 3 - maxItems: 3 + maxItems: 4 items: - const: stmmaceth - const: clkin0 - const: clkin1 + - const: timing-adjustment amlogic,tx-delay-ns: $ref: /schemas/types.yaml#definitions/uint32 @@ -67,6 +71,19 @@ allOf: PHY and MAC are adding a delay). Any configuration is ignored when the phy-mode is set to "rmii". + amlogic,rx-delay-ns: + enum: + - 0 + - 2 + default: 0 + description: + The internal RGMII RX clock delay (provided by this IP block) in + nanoseconds. When phy-mode is set to "rgmii" then the RX delay + should be explicitly configured. When the phy-mode is set to + either "rgmii-id" or "rgmii-rxid" the RX clock delay is already + provided by the PHY. Any configuration is ignored when the + phy-mode is set to "rmii". + properties: compatible: additionalItems: true @@ -107,7 +124,7 @@ examples: reg = <0xc9410000 0x10000>, <0xc8834540 0x8>; interrupts = <8>; interrupt-names = "macirq"; - clocks = <&clk_eth>, <&clkc_fclk_div2>, <&clk_mpll2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; phy-mode = "rgmii"; }; diff --git a/Bindings/net/calxeda-xgmac.txt b/Bindings/net/calxeda-xgmac.txt deleted file mode 100644 index c8ae996bd8f2..000000000000 --- a/Bindings/net/calxeda-xgmac.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Calxeda Highbank 10Gb XGMAC Ethernet - -Required properties: -- compatible : Should be "calxeda,hb-xgmac" -- reg : Address and length of the register set for the device -- interrupts : Should contain 3 xgmac interrupts. The 1st is main interrupt. - The 2nd is pwr mgt interrupt. The 3rd is low power state interrupt. - -Optional properties: -- dma-coherent : Present if dma operations are coherent - -Example: - -ethernet@fff50000 { - compatible = "calxeda,hb-xgmac"; - reg = <0xfff50000 0x1000>; - interrupts = <0 77 4 0 78 4 0 79 4>; -}; diff --git a/Bindings/net/calxeda-xgmac.yaml b/Bindings/net/calxeda-xgmac.yaml new file mode 100644 index 000000000000..c3ca26666ede --- /dev/null +++ b/Bindings/net/calxeda-xgmac.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/calxeda-xgmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank 10Gb XGMAC Ethernet controller + +description: | + The Calxeda XGMAC Ethernet controllers are directly connected to the + internal machine "network fabric", which is set up, initialised and + managed by the firmware. So there are no PHY properties in this + binding. Switches in the fabric take care of routing and mapping the + traffic to external network ports. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: calxeda,hb-xgmac + + reg: + maxItems: 1 + + interrupts: + description: | + Can point to at most 3 xgmac interrupts. The 1st one is the main + interrupt, the 2nd one is used for power management. The optional + 3rd one is the low power state interrupt. + minItems: 2 + maxItems: 3 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + ethernet@fff50000 { + compatible = "calxeda,hb-xgmac"; + reg = <0xfff50000 0x1000>; + interrupts = <0 77 4>, <0 78 4>, <0 79 4>; + }; diff --git a/Bindings/net/can/bosch,m_can.yaml b/Bindings/net/can/bosch,m_can.yaml index cccf8202c8f7..798fa5fb7bb2 100644 --- a/Bindings/net/can/bosch,m_can.yaml +++ b/Bindings/net/can/bosch,m_can.yaml @@ -9,7 +9,7 @@ title: Bosch MCAN controller Bindings description: Bosch MCAN controller for CAN bus maintainers: - - Sriram Dash + - Sriram Dash properties: compatible: @@ -51,61 +51,60 @@ properties: bosch,mram-cfg: description: | - Message RAM configuration data. - Multiple M_CAN instances can share the same Message RAM - and each element(e.g Rx FIFO or Tx Buffer and etc) number - in Message RAM is also configurable, so this property is - telling driver how the shared or private Message RAM are - used by this M_CAN controller. + Message RAM configuration data. + Multiple M_CAN instances can share the same Message RAM + and each element(e.g Rx FIFO or Tx Buffer and etc) number + in Message RAM is also configurable, so this property is + telling driver how the shared or private Message RAM are + used by this M_CAN controller. - The format should be as follows: - - The 'offset' is an address offset of the Message RAM where - the following elements start from. This is usually set to - 0x0 if you're using a private Message RAM. The remain cells - are used to specify how many elements are used for each FIFO/Buffer. + The format should be as follows: + + The 'offset' is an address offset of the Message RAM where + the following elements start from. This is usually set to + 0x0 if you're using a private Message RAM. The remain cells + are used to specify how many elements are used for each FIFO/Buffer. - M_CAN includes the following elements according to user manual: - 11-bit Filter 0-128 elements / 0-128 words - 29-bit Filter 0-64 elements / 0-128 words - Rx FIFO 0 0-64 elements / 0-1152 words - Rx FIFO 1 0-64 elements / 0-1152 words - Rx Buffers 0-64 elements / 0-1152 words - Tx Event FIFO 0-32 elements / 0-64 words - Tx Buffers 0-32 elements / 0-576 words + M_CAN includes the following elements according to user manual: + 11-bit Filter 0-128 elements / 0-128 words + 29-bit Filter 0-64 elements / 0-128 words + Rx FIFO 0 0-64 elements / 0-1152 words + Rx FIFO 1 0-64 elements / 0-1152 words + Rx Buffers 0-64 elements / 0-1152 words + Tx Event FIFO 0-32 elements / 0-64 words + Tx Buffers 0-32 elements / 0-576 words - Please refer to 2.4.1 Message RAM Configuration in Bosch - M_CAN user manual for details. - allOf: - - $ref: /schemas/types.yaml#/definitions/int32-array - - items: - items: - - description: The 'offset' is an address offset of the Message RAM - where the following elements start from. This is usually - set to 0x0 if you're using a private Message RAM. - default: 0 - - description: 11-bit Filter 0-128 elements / 0-128 words - minimum: 0 - maximum: 128 - - description: 29-bit Filter 0-64 elements / 0-128 words - minimum: 0 - maximum: 64 - - description: Rx FIFO 0 0-64 elements / 0-1152 words - minimum: 0 - maximum: 64 - - description: Rx FIFO 1 0-64 elements / 0-1152 words - minimum: 0 - maximum: 64 - - description: Rx Buffers 0-64 elements / 0-1152 words - minimum: 0 - maximum: 64 - - description: Tx Event FIFO 0-32 elements / 0-64 words - minimum: 0 - maximum: 32 - - description: Tx Buffers 0-32 elements / 0-576 words - minimum: 0 - maximum: 32 - maxItems: 1 + Please refer to 2.4.1 Message RAM Configuration in Bosch + M_CAN user manual for details. + $ref: /schemas/types.yaml#/definitions/int32-array + items: + items: + - description: The 'offset' is an address offset of the Message RAM where + the following elements start from. This is usually set to 0x0 if + you're using a private Message RAM. + default: 0 + - description: 11-bit Filter 0-128 elements / 0-128 words + minimum: 0 + maximum: 128 + - description: 29-bit Filter 0-64 elements / 0-128 words + minimum: 0 + maximum: 64 + - description: Rx FIFO 0 0-64 elements / 0-1152 words + minimum: 0 + maximum: 64 + - description: Rx FIFO 1 0-64 elements / 0-1152 words + minimum: 0 + maximum: 64 + - description: Rx Buffers 0-64 elements / 0-1152 words + minimum: 0 + maximum: 64 + - description: Tx Event FIFO 0-32 elements / 0-64 words + minimum: 0 + maximum: 32 + - description: Tx Buffers 0-32 elements / 0-576 words + minimum: 0 + maximum: 32 + maxItems: 1 can-transceiver: $ref: can-transceiver.yaml# diff --git a/Bindings/net/ethernet-controller.yaml b/Bindings/net/ethernet-controller.yaml index ac471b60ed6a..1c4474036d46 100644 --- a/Bindings/net/ethernet-controller.yaml +++ b/Bindings/net/ethernet-controller.yaml @@ -14,25 +14,23 @@ properties: pattern: "^ethernet(@.*)?$" local-mac-address: - allOf: - - $ref: /schemas/types.yaml#definitions/uint8-array - - items: - - minItems: 6 - maxItems: 6 description: Specifies the MAC address that was assigned to the network device. + $ref: /schemas/types.yaml#definitions/uint8-array + items: + - minItems: 6 + maxItems: 6 mac-address: - allOf: - - $ref: /schemas/types.yaml#definitions/uint8-array - - items: - - minItems: 6 - maxItems: 6 description: Specifies the MAC address that was last used by the boot program; should be used in cases where the MAC address assigned to the device by the boot program is different from the local-mac-address property. + $ref: /schemas/types.yaml#definitions/uint8-array + items: + - minItems: 6 + maxItems: 6 max-frame-size: $ref: /schemas/types.yaml#definitions/uint32 @@ -133,15 +131,14 @@ properties: is used for components that can have configurable fifo sizes. managed: - allOf: - - $ref: /schemas/types.yaml#definitions/string - - default: auto - enum: - - auto - - in-band-status description: Specifies the PHY management type. If auto is set and fixed-link is not specified, it uses MDIO for management. + $ref: /schemas/types.yaml#definitions/string + default: auto + enum: + - auto + - in-band-status fixed-link: allOf: @@ -183,11 +180,10 @@ properties: then: properties: speed: - allOf: - - $ref: /schemas/types.yaml#definitions/uint32 - - enum: [10, 100, 1000] description: Link speed. + $ref: /schemas/types.yaml#definitions/uint32 + enum: [10, 100, 1000] full-duplex: $ref: /schemas/types.yaml#definitions/flag diff --git a/Bindings/net/ethernet-phy.yaml b/Bindings/net/ethernet-phy.yaml index 5aa141ccc113..9b1f1147ca36 100644 --- a/Bindings/net/ethernet-phy.yaml +++ b/Bindings/net/ethernet-phy.yaml @@ -81,7 +81,8 @@ properties: $ref: /schemas/types.yaml#definitions/flag description: If set, indicates the PHY device does not correctly release - the turn around line low at the end of a MDIO transaction. + the turn around line low at end of the control phase of the + MDIO transaction. enet-phy-lane-swap: $ref: /schemas/types.yaml#definitions/flag diff --git a/Bindings/net/fsl-fec.txt b/Bindings/net/fsl-fec.txt index ff8b0f211aa1..9b543789cd52 100644 --- a/Bindings/net/fsl-fec.txt +++ b/Bindings/net/fsl-fec.txt @@ -22,8 +22,11 @@ Optional properties: - fsl,err006687-workaround-present: If present indicates that the system has the hardware workaround for ERR006687 applied and does not need a software workaround. -- gpr: phandle of SoC general purpose register mode. Required for wake on LAN - on some SoCs +- fsl,stop-mode: register bits of stop mode control, the format is + <&gpr req_gpr req_bit>. + gpr is the phandle to general purpose register node. + req_gpr is the gpr register offset for ENET stop request. + req_bit is the gpr bit offset for ENET stop request. -interrupt-names: names of the interrupts listed in interrupts property in the same order. The defaults if not specified are __Number of interrupts__ __Default__ @@ -82,6 +85,7 @@ ethernet@83fec000 { phy-supply = <®_fec_supply>; phy-handle = <ðphy>; mdio { + clock-frequency = <5000000>; ethphy: ethernet-phy@6 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <6>; diff --git a/Bindings/net/imx-dwmac.txt b/Bindings/net/imx-dwmac.txt new file mode 100644 index 000000000000..921d522fe8d7 --- /dev/null +++ b/Bindings/net/imx-dwmac.txt @@ -0,0 +1,56 @@ +IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP. + +This file documents platform glue layer for IMX. +Please see stmmac.txt for the other unchanged properties. + +The device node has following properties. + +Required properties: +- compatible: Should be "nxp,imx8mp-dwmac-eqos" to select glue layer + and "snps,dwmac-5.10a" to select IP version. +- clocks: Must contain a phandle for each entry in clock-names. +- clock-names: Should be "stmmaceth" for the host clock. + Should be "pclk" for the MAC apb clock. + Should be "ptp_ref" for the MAC timer clock. + Should be "tx" for the MAC RGMII TX clock: + Should be "mem" for EQOS MEM clock. + - "mem" clock is required for imx8dxl platform. + - "mem" clock is not required for imx8mp platform. +- interrupt-names: Should contain a list of interrupt names corresponding to + the interrupts in the interrupts property, if available. + Should be "macirq" for the main MAC IRQ + Should be "eth_wake_irq" for the IT which wake up system +- intf_mode: Should be phandle/offset pair. The phandle to the syscon node which + encompases the GPR register, and the offset of the GPR register. + - required for imx8mp platform. + - is optional for imx8dxl platform. + +Optional properties: +- intf_mode: is optional for imx8dxl platform. +- snps,rmii_refclk_ext: to select RMII reference clock from external. + +Example: + eqos: ethernet@30bf0000 { + compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x30bf0000 0x10000>; + interrupts = , + ; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, + <&clk IMX8MP_CLK_QOS_ENET_ROOT>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; + assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <100000000>, <125000000>; + nvmem-cells = <ð_mac0>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + intf_mode = <&gpr 0x4>; + status = "disabled"; + }; diff --git a/Bindings/net/mdio.yaml b/Bindings/net/mdio.yaml index 50c3397a82bc..d6a3bf8550eb 100644 --- a/Bindings/net/mdio.yaml +++ b/Bindings/net/mdio.yaml @@ -31,13 +31,25 @@ properties: maxItems: 1 description: The phandle and specifier for the GPIO that controls the RESET - lines of all PHYs on that MDIO bus. + lines of all devices on that MDIO bus. reset-delay-us: description: - RESET pulse width in microseconds. It applies to all PHY devices - and must therefore be appropriately determined based on all PHY - requirements (maximum value of all per-PHY RESET pulse widths). + RESET pulse width in microseconds. It applies to all MDIO devices + and must therefore be appropriately determined based on all devices + requirements (maximum value of all per-device RESET pulse widths). + + clock-frequency: + description: + Desired MDIO bus clock frequency in Hz. Values greater than IEEE 802.3 + defined 2.5MHz should only be used when all devices on the bus support + the given clock speed. + + suppress-preamble: + description: + The 32 bit preamble should be suppressed. In order for this to + work, all devices on the bus must support suppressed preamble. + type: boolean patternProperties: "^ethernet-phy@[0-9a-f]+$": @@ -48,7 +60,35 @@ patternProperties: minimum: 0 maximum: 31 description: - The ID number for the PHY. + The ID number for the device. + + broken-turn-around: + $ref: /schemas/types.yaml#definitions/flag + description: + If set, indicates the MDIO device does not correctly release + the turn around line low at end of the control phase of the + MDIO transaction. + + resets: + maxItems: 1 + + reset-names: + const: phy + + reset-gpios: + maxItems: 1 + description: + The GPIO phandle and specifier for the MDIO reset signal. + + reset-assert-us: + description: + Delay after the reset was asserted in microseconds. If this + property is missing the delay will be skipped. + + reset-deassert-us: + description: + Delay after the reset was deasserted in microseconds. If + this property is missing the delay will be skipped. required: - reg diff --git a/Bindings/net/mediatek,star-emac.yaml b/Bindings/net/mediatek,star-emac.yaml new file mode 100644 index 000000000000..aea88e621792 --- /dev/null +++ b/Bindings/net/mediatek,star-emac.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek STAR Ethernet MAC Controller + +maintainers: + - Bartosz Golaszewski + +description: + This Ethernet MAC is used on the MT8* family of SoCs from MediaTek. + It's compliant with 802.3 standards and supports half- and full-duplex + modes with flow-control as well as CRC offloading and VLAN tags. + +allOf: + - $ref: "ethernet-controller.yaml#" + +properties: + compatible: + enum: + - mediatek,mt8516-eth + - mediatek,mt8518-eth + - mediatek,mt8175-eth + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + additionalItems: false + items: + - const: core + - const: reg + - const: trans + + mediatek,pericfg: + $ref: /schemas/types.yaml#definitions/phandle + description: + Phandle to the device containing the PERICFG register range. This is used + to control the MII mode. + + mdio: + type: object + description: + Creates and registers an MDIO bus. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - mediatek,pericfg + - phy-handle + +examples: + - | + #include + #include + + ethernet: ethernet@11180000 { + compatible = "mediatek,mt8516-eth"; + reg = <0x11180000 0x1000>; + mediatek,pericfg = <&pericfg>; + interrupts = ; + clocks = <&topckgen CLK_TOP_RG_ETH>, + <&topckgen CLK_TOP_66M_ETH>, + <&topckgen CLK_TOP_133M_ETH>; + clock-names = "core", "reg", "trans"; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; + }; diff --git a/Bindings/net/mediatek-bluetooth.txt b/Bindings/net/mediatek-bluetooth.txt index 219bcbd0d344..9ef5bacda8c1 100644 --- a/Bindings/net/mediatek-bluetooth.txt +++ b/Bindings/net/mediatek-bluetooth.txt @@ -3,7 +3,7 @@ MediaTek SoC built-in Bluetooth Devices This device is a serial attached device to BTIF device and thus it must be a child node of the serial node with BTIF. The dt-bindings details for BTIF -device can be known via Documentation/devicetree/bindings/serial/8250.txt. +device can be known via Documentation/devicetree/bindings/serial/8250.yaml. Required properties: diff --git a/Bindings/net/nxp,tja11xx.yaml b/Bindings/net/nxp,tja11xx.yaml new file mode 100644 index 000000000000..42be0255512b --- /dev/null +++ b/Bindings/net/nxp,tja11xx.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/nxp,tja11xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP TJA11xx PHY + +maintainers: + - Andrew Lunn + - Florian Fainelli + - Heiner Kallweit + +description: + Bindings for NXP TJA11xx automotive PHYs + +allOf: + - $ref: ethernet-phy.yaml# + +patternProperties: + "^ethernet-phy@[0-9a-f]+$": + type: object + description: | + Some packages have multiple PHYs. Secondary PHY should be defines as + subnode of the first (parent) PHY. + + properties: + reg: + minimum: 0 + maximum: 31 + description: + The ID number for the child PHY. Should be +1 of parent PHY. + + required: + - reg + +examples: + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + + tja1101_phy0: ethernet-phy@4 { + reg = <0x4>; + }; + }; + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + + tja1102_phy0: ethernet-phy@4 { + reg = <0x4>; + #address-cells = <1>; + #size-cells = <0>; + + tja1102_phy1: ethernet-phy@5 { + reg = <0x5>; + }; + }; + }; diff --git a/Bindings/net/qca,ar71xx.txt b/Bindings/net/qca,ar71xx.txt deleted file mode 100644 index 2a33e71ba72b..000000000000 --- a/Bindings/net/qca,ar71xx.txt +++ /dev/null @@ -1,45 +0,0 @@ -Required properties: -- compatible: Should be "qca,-eth". Currently support compatibles are: - qca,ar7100-eth - Atheros AR7100 - qca,ar7240-eth - Atheros AR7240 - qca,ar7241-eth - Atheros AR7241 - qca,ar7242-eth - Atheros AR7242 - qca,ar9130-eth - Atheros AR9130 - qca,ar9330-eth - Atheros AR9330 - qca,ar9340-eth - Atheros AR9340 - qca,qca9530-eth - Qualcomm Atheros QCA9530 - qca,qca9550-eth - Qualcomm Atheros QCA9550 - qca,qca9560-eth - Qualcomm Atheros QCA9560 - -- reg : Address and length of the register set for the device -- interrupts : Should contain eth interrupt -- phy-mode : See ethernet.txt file in the same directory -- clocks: the clock used by the core -- clock-names: the names of the clock listed in the clocks property. These are - "eth" and "mdio". -- resets: Should contain phandles to the reset signals -- reset-names: Should contain the names of reset signal listed in the resets - property. These are "mac" and "mdio" - -Optional properties: -- phy-handle : phandle to the PHY device connected to this device. -- fixed-link : Assume a fixed link. See fixed-link.txt in the same directory. - Use instead of phy-handle. - -Optional subnodes: -- mdio : specifies the mdio bus, used as a container for phy nodes - according to phy.txt in the same directory - -Example: - -ethernet@1a000000 { - compatible = "qca,ar9330-eth"; - reg = <0x1a000000 0x200>; - interrupts = <5>; - resets = <&rst 13>, <&rst 23>; - reset-names = "mac", "mdio"; - clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_MDIO>; - clock-names = "eth", "mdio"; - - phy-mode = "gmii"; -}; diff --git a/Bindings/net/qca,ar71xx.yaml b/Bindings/net/qca,ar71xx.yaml new file mode 100644 index 000000000000..f99a5aabe923 --- /dev/null +++ b/Bindings/net/qca,ar71xx.yaml @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qca,ar71xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QCA AR71XX MAC + +allOf: + - $ref: ethernet-controller.yaml# + +maintainers: + - Oleksij Rempel + +properties: + compatible: + oneOf: + - items: + - enum: + - qca,ar7100-eth # Atheros AR7100 + - qca,ar7240-eth # Atheros AR7240 + - qca,ar7241-eth # Atheros AR7241 + - qca,ar7242-eth # Atheros AR7242 + - qca,ar9130-eth # Atheros AR9130 + - qca,ar9330-eth # Atheros AR9330 + - qca,ar9340-eth # Atheros AR9340 + - qca,qca9530-eth # Qualcomm Atheros QCA9530 + - qca,qca9550-eth # Qualcomm Atheros QCA9550 + - qca,qca9560-eth # Qualcomm Atheros QCA9560 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#address-cells': + description: number of address cells for the MDIO bus + const: 1 + + '#size-cells': + description: number of size cells on the MDIO bus + const: 0 + + clocks: + items: + - description: MAC main clock + - description: MDIO clock + + clock-names: + items: + - const: eth + - const: mdio + + resets: + items: + - description: MAC reset + - description: MDIO reset + + reset-names: + items: + - const: mac + - const: mdio + +required: + - compatible + - reg + - interrupts + - phy-mode + - clocks + - clock-names + - resets + - reset-names + +examples: + # Lager board + - | + eth0: ethernet@19000000 { + compatible = "qca,ar9330-eth"; + reg = <0x19000000 0x200>; + interrupts = <4>; + resets = <&rst 9>, <&rst 22>; + reset-names = "mac", "mdio"; + clocks = <&pll 1>, <&pll 2>; + clock-names = "eth", "mdio"; + qca,ethcfg = <ðcfg>; + phy-mode = "mii"; + phy-handle = <&phy_port4>; + }; + + eth1: ethernet@1a000000 { + compatible = "qca,ar9330-eth"; + reg = <0x1a000000 0x200>; + interrupts = <5>; + resets = <&rst 13>, <&rst 23>; + reset-names = "mac", "mdio"; + clocks = <&pll 1>, <&pll 2>; + clock-names = "eth", "mdio"; + + phy-mode = "gmii"; + + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch10: switch@10 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qca,ar9331-switch"; + reg = <0x10>; + resets = <&rst 8>; + reset-names = "switch"; + + interrupt-parent = <&miscintc>; + interrupts = <12>; + + interrupt-controller; + #interrupt-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + switch_port0: port@0 { + reg = <0x0>; + label = "cpu"; + ethernet = <ð1>; + + phy-mode = "gmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + switch_port1: port@1 { + reg = <0x1>; + phy-handle = <&phy_port0>; + phy-mode = "internal"; + + status = "disabled"; + }; + + switch_port2: port@2 { + reg = <0x2>; + phy-handle = <&phy_port1>; + phy-mode = "internal"; + + status = "disabled"; + }; + + switch_port3: port@3 { + reg = <0x3>; + phy-handle = <&phy_port2>; + phy-mode = "internal"; + + status = "disabled"; + }; + + switch_port4: port@4 { + reg = <0x4>; + phy-handle = <&phy_port3>; + phy-mode = "internal"; + + status = "disabled"; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + interrupt-parent = <&switch10>; + + phy_port0: phy@0 { + reg = <0x0>; + interrupts = <0>; + status = "disabled"; + }; + + phy_port1: phy@1 { + reg = <0x1>; + interrupts = <0>; + status = "disabled"; + }; + + phy_port2: phy@2 { + reg = <0x2>; + interrupts = <0>; + status = "disabled"; + }; + + phy_port3: phy@3 { + reg = <0x3>; + interrupts = <0>; + status = "disabled"; + }; + + phy_port4: phy@4 { + reg = <0x4>; + interrupts = <0>; + status = "disabled"; + }; + }; + }; + }; + }; diff --git a/Bindings/net/qca,ar803x.yaml b/Bindings/net/qca,ar803x.yaml index 5a6c9d20c0ba..1788884b8c28 100644 --- a/Bindings/net/qca,ar803x.yaml +++ b/Bindings/net/qca,ar803x.yaml @@ -20,15 +20,13 @@ allOf: properties: qca,clk-out-frequency: description: Clock output frequency in Hertz. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 25000000, 50000000, 62500000, 125000000 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [25000000, 50000000, 62500000, 125000000] qca,clk-out-strength: description: Clock output driver strength. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 0, 1, 2 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] qca,keep-pll-enabled: description: | @@ -52,17 +50,14 @@ properties: type: object description: Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V. - allOf: - - $ref: /schemas/regulator/regulator.yaml + $ref: /schemas/regulator/regulator.yaml vddh-regulator: type: object description: Dummy subnode to model the external connection of the PHY VDDH regulator to VDDIO. - allOf: - - $ref: /schemas/regulator/regulator.yaml - + $ref: /schemas/regulator/regulator.yaml examples: - | diff --git a/Bindings/net/qcom,ipa.yaml b/Bindings/net/qcom,ipa.yaml index 140f15245654..a3561276e609 100644 --- a/Bindings/net/qcom,ipa.yaml +++ b/Bindings/net/qcom,ipa.yaml @@ -20,7 +20,10 @@ description: The GSI is an integral part of the IPA, but it is logically isolated and has a distinct interrupt and a separately-defined address space. - See also soc/qcom/qcom,smp2p.txt and interconnect/interconnect.txt. + See also soc/qcom/qcom,smp2p.txt and interconnect/interconnect.txt. See + iommu/iommu.txt and iommu/arm,smmu.yaml for more information about SMMU + bindings. + - | -------- --------- @@ -54,6 +57,9 @@ properties: - const: ipa-shared - const: gsi + iommus: + maxItems: 1 + clocks: maxItems: 1 @@ -87,16 +93,14 @@ properties: - const: config qcom,smem-states: - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle-array + $ref: /schemas/types.yaml#/definitions/phandle-array description: State bits used in by the AP to signal the modem. items: - description: Whether the "ipa-clock-enabled" state bit is valid - description: Whether the IPA clock is enabled (if valid) qcom,smem-state-names: - allOf: - - $ref: /schemas/types.yaml#/definitions/string-array + $ref: /schemas/types.yaml#/definitions/string-array description: The names of the state bits used for SMP2P output items: - const: ipa-clock-enabled-valid @@ -126,6 +130,7 @@ properties: required: - compatible + - iommus - reg - clocks - interrupts @@ -164,9 +169,10 @@ examples: modem-init; modem-remoteproc = <&mss_pil>; - reg = <0 0x1e40000 0 0x7000>, - <0 0x1e47000 0 0x2000>, - <0 0x1e04000 0 0x2c000>; + iommus = <&apps_smmu 0x720 0x3>; + reg = <0x1e40000 0x7000>, + <0x1e47000 0x2000>, + <0x1e04000 0x2c000>; reg-names = "ipa-reg", "ipa-shared", "gsi"; diff --git a/Bindings/net/qcom,ipq4019-mdio.yaml b/Bindings/net/qcom,ipq4019-mdio.yaml new file mode 100644 index 000000000000..13555a89975f --- /dev/null +++ b/Bindings/net/qcom,ipq4019-mdio.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ40xx MDIO Controller Device Tree Bindings + +maintainers: + - Robert Marko + +allOf: + - $ref: "mdio.yaml#" + +properties: + compatible: + const: qcom,ipq4019-mdio + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +examples: + - | + mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq4019-mdio"; + reg = <0x90000 0x64>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + }; + + ethphy4: ethernet-phy@4 { + reg = <4>; + }; + }; diff --git a/Bindings/net/qualcomm-bluetooth.txt b/Bindings/net/qualcomm-bluetooth.txt index d2202791c1d4..709ca6d51650 100644 --- a/Bindings/net/qualcomm-bluetooth.txt +++ b/Bindings/net/qualcomm-bluetooth.txt @@ -10,9 +10,11 @@ device the slave device is attached to. Required properties: - compatible: should contain one of the following: * "qcom,qca6174-bt" + * "qcom,qca9377-bt" * "qcom,wcn3990-bt" * "qcom,wcn3991-bt" * "qcom,wcn3998-bt" + * "qcom,qca6390-bt" Optional properties for compatible string qcom,qca6174-bt: @@ -20,6 +22,10 @@ Optional properties for compatible string qcom,qca6174-bt: - clocks: clock provided to the controller (SUSCLK_32KHZ) - firmware-name: specify the name of nvm firmware to load +Optional properties for compatible string qcom,qca9377-bt: + + - max-speed: see Documentation/devicetree/bindings/serial/serial.yaml + Required properties for compatible string qcom,wcn399x-bt: - vddio-supply: VDD_IO supply regulator handle. diff --git a/Bindings/net/realtek-bluetooth.yaml b/Bindings/net/realtek-bluetooth.yaml new file mode 100644 index 000000000000..f15a5e5e4859 --- /dev/null +++ b/Bindings/net/realtek-bluetooth.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/realtek-bluetooth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RTL8723BS/RTL8723CS/RTL8822CS Bluetooth Device Tree Bindings + +maintainers: + - Vasily Khoruzhick + - Alistair Francis + +description: + RTL8723CS/RTL8723CS/RTL8822CS is WiFi + BT chip. WiFi part is connected over + SDIO, while BT is connected over serial. It speaks H5 protocol with few + extra commands to upload firmware and change module speed. + +properties: + compatible: + oneOf: + - const: "realtek,rtl8723bs-bt" + - const: "realtek,rtl8723cs-bt" + - const: "realtek,rtl8822cs-bt" + + device-wake-gpios: + maxItems: 1 + description: GPIO specifier, used to wakeup the BT module + + enable-gpios: + maxItems: 1 + description: GPIO specifier, used to enable the BT module + + host-wake-gpios: + maxItems: 1 + description: GPIO specifier, used to wakeup the host processor + +required: + - compatible + +examples: + - | + #include + + uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts = <1>; + + bluetooth { + compatible = "realtek,rtl8723bs-bt"; + device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + host-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + }; + }; diff --git a/Bindings/net/renesas,ether.yaml b/Bindings/net/renesas,ether.yaml index 7f84df9790e2..08678af5ed93 100644 --- a/Bindings/net/renesas,ether.yaml +++ b/Bindings/net/renesas,ether.yaml @@ -29,8 +29,9 @@ properties: - renesas,rcar-gen1-ether # a generic R-Car Gen1 device - items: - enum: - - renesas,ether-r8a7745 # device is a part of R8A7745 SoC + - renesas,ether-r8a7742 # device is a part of R8A7742 SoC - renesas,ether-r8a7743 # device is a part of R8A7743 SoC + - renesas,ether-r8a7745 # device is a part of R8A7745 SoC - renesas,ether-r8a7790 # device is a part of R8A7790 SoC - renesas,ether-r8a7791 # device is a part of R8A7791 SoC - renesas,ether-r8a7793 # device is a part of R8A7793 SoC @@ -40,8 +41,8 @@ properties: reg: items: - - description: E-DMAC/feLic registers - - description: TSU registers + - description: E-DMAC/feLic registers + - description: TSU registers minItems: 1 interrupts: @@ -92,7 +93,7 @@ examples: ethernet@ee700000 { compatible = "renesas,ether-r8a7790", "renesas,rcar-gen2-ether"; - reg = <0 0xee700000 0 0x400>; + reg = <0xee700000 0x400>; interrupt-parent = <&gic>; interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp8_clks R8A7790_CLK_ETHER>; diff --git a/Bindings/net/renesas,ravb.txt b/Bindings/net/renesas,ravb.txt index 87dad2dd8ca0..032b76f14f4f 100644 --- a/Bindings/net/renesas,ravb.txt +++ b/Bindings/net/renesas,ravb.txt @@ -5,6 +5,7 @@ interface contains. Required properties: - compatible: Must contain one or more of the following: + - "renesas,etheravb-r8a7742" for the R8A7742 SoC. - "renesas,etheravb-r8a7743" for the R8A7743 SoC. - "renesas,etheravb-r8a7744" for the R8A7744 SoC. - "renesas,etheravb-r8a7745" for the R8A7745 SoC. diff --git a/Bindings/net/snps,dwmac.yaml b/Bindings/net/snps,dwmac.yaml index e08cd4c4d568..30a1efd26626 100644 --- a/Bindings/net/snps,dwmac.yaml +++ b/Bindings/net/snps,dwmac.yaml @@ -27,6 +27,7 @@ select: - snps,dwmac-3.710 - snps,dwmac-4.00 - snps,dwmac-4.10a + - snps,dwmac-4.20a - snps,dwxgmac - snps,dwxgmac-2.10 @@ -62,6 +63,7 @@ properties: - snps,dwmac-3.710 - snps,dwmac-4.00 - snps,dwmac-4.10a + - snps,dwmac-4.20a - snps,dwxgmac - snps,dwxgmac-2.10 @@ -87,7 +89,8 @@ properties: clocks: minItems: 1 - maxItems: 3 + maxItems: 5 + additionalItems: true items: - description: GMAC main clock - description: Peripheral registers interface clock @@ -97,6 +100,8 @@ properties: clock will be used and this is fine on some platforms. clock-names: + minItems: 1 + maxItems: 5 additionalItems: true contains: enum: @@ -199,14 +204,13 @@ properties: snps,reset-delays-us: deprecated: true - allOf: - - $ref: /schemas/types.yaml#definitions/uint32-array - - minItems: 3 - maxItems: 3 description: Triplet of delays. The 1st cell is reset pre-delay in micro seconds. The 2nd cell is reset pulse in micro seconds. The 3rd cell is reset post-delay in micro seconds. + $ref: /schemas/types.yaml#definitions/uint32-array + minItems: 3 + maxItems: 3 snps,aal: $ref: /schemas/types.yaml#definitions/flag @@ -301,27 +305,24 @@ allOf: then: properties: snps,pbl: - allOf: - - $ref: /schemas/types.yaml#definitions/uint32 - - enum: [2, 4, 8] description: Programmable Burst Length (tx and rx) + $ref: /schemas/types.yaml#definitions/uint32 + enum: [2, 4, 8] snps,txpbl: - allOf: - - $ref: /schemas/types.yaml#definitions/uint32 - - enum: [2, 4, 8] description: Tx Programmable Burst Length. If set, DMA tx will use this value rather than snps,pbl. + $ref: /schemas/types.yaml#definitions/uint32 + enum: [2, 4, 8] snps,rxpbl: - allOf: - - $ref: /schemas/types.yaml#definitions/uint32 - - enum: [2, 4, 8] description: Rx Programmable Burst Length. If set, DMA rx will use this value rather than snps,pbl. + $ref: /schemas/types.yaml#definitions/uint32 + enum: [2, 4, 8] snps,no-pbl-x8: $ref: /schemas/types.yaml#definitions/flag @@ -342,6 +343,7 @@ allOf: - allwinner,sun50i-a64-emac - snps,dwmac-4.00 - snps,dwmac-4.10a + - snps,dwmac-4.20a - snps,dwxgmac - snps,dwxgmac-2.10 - st,spear600-gmac diff --git a/Bindings/net/socionext,uniphier-ave4.txt b/Bindings/net/socionext,uniphier-ave4.txt deleted file mode 100644 index 4e85fc495e87..000000000000 --- a/Bindings/net/socionext,uniphier-ave4.txt +++ /dev/null @@ -1,64 +0,0 @@ -* Socionext AVE ethernet controller - -This describes the devicetree bindings for AVE ethernet controller -implemented on Socionext UniPhier SoCs. - -Required properties: - - compatible: Should be - - "socionext,uniphier-pro4-ave4" : for Pro4 SoC - - "socionext,uniphier-pxs2-ave4" : for PXs2 SoC - - "socionext,uniphier-ld11-ave4" : for LD11 SoC - - "socionext,uniphier-ld20-ave4" : for LD20 SoC - - "socionext,uniphier-pxs3-ave4" : for PXs3 SoC - - reg: Address where registers are mapped and size of region. - - interrupts: Should contain the MAC interrupt. - - phy-mode: See ethernet.txt in the same directory. Allow to choose - "rgmii", "rmii", "mii", or "internal" according to the PHY. - The acceptable mode is SoC-dependent. - - phy-handle: Should point to the external phy device. - See ethernet.txt file in the same directory. - - clocks: A phandle to the clock for the MAC. - For Pro4 SoC, that is "socionext,uniphier-pro4-ave4", - another MAC clock, GIO bus clock and PHY clock are also required. - - clock-names: Should contain - - "ether", "ether-gb", "gio", "ether-phy" for Pro4 SoC - - "ether" for others - - resets: A phandle to the reset control for the MAC. For Pro4 SoC, - GIO bus reset is also required. - - reset-names: Should contain - - "ether", "gio" for Pro4 SoC - - "ether" for others - - socionext,syscon-phy-mode: A phandle to syscon with one argument - that configures phy mode. The argument is the ID of MAC instance. - -The MAC address will be determined using the optional properties -defined in ethernet.txt. - -Required subnode: - - mdio: A container for child nodes representing phy nodes. - See phy.txt in the same directory. - -Example: - - ether: ethernet@65000000 { - compatible = "socionext,uniphier-ld20-ave4"; - reg = <0x65000000 0x8500>; - interrupts = <0 66 4>; - phy-mode = "rgmii"; - phy-handle = <ðphy>; - clock-names = "ether"; - clocks = <&sys_clk 6>; - reset-names = "ether"; - resets = <&sys_rst 6>; - socionext,syscon-phy-mode = <&soc_glue 0>; - local-mac-address = [00 00 00 00 00 00]; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethphy@1 { - reg = <1>; - }; - }; - }; diff --git a/Bindings/net/socionext,uniphier-ave4.yaml b/Bindings/net/socionext,uniphier-ave4.yaml new file mode 100644 index 000000000000..7d84a863b9b9 --- /dev/null +++ b/Bindings/net/socionext,uniphier-ave4.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/socionext,uniphier-ave4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext AVE ethernet controller + +maintainers: + - Kunihiko Hayashi + +description: | + This describes the devicetree bindings for AVE ethernet controller + implemented on Socionext UniPhier SoCs. + +allOf: + - $ref: ethernet-controller.yaml# + +properties: + compatible: + enum: + - socionext,uniphier-pro4-ave4 + - socionext,uniphier-pxs2-ave4 + - socionext,uniphier-ld11-ave4 + - socionext,uniphier-ld20-ave4 + - socionext,uniphier-pxs3-ave4 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + phy-mode: true + + phy-handle: true + + mac-address: true + + local-mac-address: true + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + oneOf: + - items: # for Pro4 + - const: gio + - const: ether + - const: ether-gb + - const: ether-phy + - const: ether # for others + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + oneOf: + - items: # for Pro4 + - const: gio + - const: ether + - const: ether # for others + + socionext,syscon-phy-mode: + $ref: /schemas/types.yaml#definitions/phandle-array + description: + A phandle to syscon with one argument that configures phy mode. + The argument is the ID of MAC instance. + + mdio: + $ref: mdio.yaml# + +required: + - compatible + - reg + - interrupts + - phy-mode + - phy-handle + - clocks + - clock-names + - resets + - reset-names + - mdio + +additionalProperties: false + +examples: + - | + ether: ethernet@65000000 { + compatible = "socionext,uniphier-ld20-ave4"; + reg = <0x65000000 0x8500>; + interrupts = <0 66 4>; + phy-mode = "rgmii"; + phy-handle = <ðphy>; + clock-names = "ether"; + clocks = <&sys_clk 6>; + reset-names = "ether"; + resets = <&sys_rst 6>; + socionext,syscon-phy-mode = <&soc_glue 0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@1 { + reg = <1>; + }; + }; + }; diff --git a/Bindings/net/stm32-dwmac.txt b/Bindings/net/stm32-dwmac.txt deleted file mode 100644 index a90eef11dc46..000000000000 --- a/Bindings/net/stm32-dwmac.txt +++ /dev/null @@ -1,44 +0,0 @@ -STMicroelectronics STM32 / MCU DWMAC glue layer controller - -This file documents platform glue layer for stmmac. -Please see stmmac.txt for the other unchanged properties. - -The device node has following properties. - -Required properties: -- compatible: For MCU family should be "st,stm32-dwmac" to select glue, and - "snps,dwmac-3.50a" to select IP version. - For MPU family should be "st,stm32mp1-dwmac" to select - glue, and "snps,dwmac-4.20a" to select IP version. -- clocks: Must contain a phandle for each entry in clock-names. -- clock-names: Should be "stmmaceth" for the host clock. - Should be "mac-clk-tx" for the MAC TX clock. - Should be "mac-clk-rx" for the MAC RX clock. - For MPU family need to add also "ethstp" for power mode clock -- interrupt-names: Should contain a list of interrupt names corresponding to - the interrupts in the interrupts property, if available. - Should be "macirq" for the main MAC IRQ - Should be "eth_wake_irq" for the IT which wake up system -- st,syscon : Should be phandle/offset pair. The phandle to the syscon node which - encompases the glue register, and the offset of the control register. - -Optional properties: -- clock-names: For MPU family "eth-ck" for PHY without quartz -- st,eth-clk-sel (boolean) : set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125. -- st,eth-ref-clk-sel (boolean) : set this property in RMII mode when you have PHY without crystal 50MHz and want to select RCC clock instead of ETH_REF_CLK. - -Example: - - ethernet@40028000 { - compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; - reg = <0x40028000 0x8000>; - reg-names = "stmmaceth"; - interrupts = <0 61 0>, <0 62 0>; - interrupt-names = "macirq", "eth_wake_irq"; - clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; - clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>; - st,syscon = <&syscfg 0x4>; - snps,pbl = <8>; - snps,mixed-burst; - dma-ranges; - }; diff --git a/Bindings/net/stm32-dwmac.yaml b/Bindings/net/stm32-dwmac.yaml new file mode 100644 index 000000000000..fafa34cebdb1 --- /dev/null +++ b/Bindings/net/stm32-dwmac.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 BayLibre, SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/stm32-dwmac.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: STMicroelectronics STM32 / MCU DWMAC glue layer controller + +maintainers: + - Alexandre Torgue + - Christophe Roullier + +description: + This file documents platform glue layer for stmmac. + +# We need a select here so we don't match all nodes with 'snps,dwmac' +select: + properties: + compatible: + contains: + enum: + - st,stm32-dwmac + - st,stm32mp1-dwmac + required: + - compatible + +allOf: + - $ref: "snps,dwmac.yaml#" + +properties: + compatible: + oneOf: + - items: + - enum: + - st,stm32mp1-dwmac + - const: snps,dwmac-4.20a + - items: + - enum: + - st,stm32-dwmac + - const: snps,dwmac-4.10a + - items: + - enum: + - st,stm32-dwmac + - const: snps,dwmac-3.50a + + clocks: + minItems: 3 + maxItems: 5 + items: + - description: GMAC main clock + - description: MAC TX clock + - description: MAC RX clock + - description: For MPU family, used for power mode + - description: For MPU family, used for PHY without quartz + + clock-names: + minItems: 3 + maxItems: 5 + contains: + enum: + - stmmaceth + - mac-clk-tx + - mac-clk-rx + - ethstp + - eth-ck + + st,syscon: + $ref: "/schemas/types.yaml#/definitions/phandle-array" + description: + Should be phandle/offset pair. The phandle to the syscon node which + encompases the glue register, and the offset of the control register + + st,eth-clk-sel: + description: + set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125. + type: boolean + + st,eth-ref-clk-sel: + description: + set this property in RMII mode when you have PHY without crystal 50MHz and want to + select RCC clock instead of ETH_REF_CLK. + type: boolean + +required: + - compatible + - clocks + - clock-names + - st,syscon + +examples: + - | + #include + #include + #include + #include + //Example 1 + ethernet0: ethernet@5800a000 { + compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHSTP>, + <&rcc ETHCK_K>; + st,syscon = <&syscfg 0x4>; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_0>; + snps,tso; + phy-mode = "rgmii"; + }; + + //Example 2 (MCU example) + ethernet1: ethernet@40028000 { + compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; + reg = <0x40028000 0x8000>; + reg-names = "stmmaceth"; + interrupts = <0 61 0>, <0 62 0>; + interrupt-names = "macirq", "eth_wake_irq"; + clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; + clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>; + st,syscon = <&syscfg 0x4>; + snps,pbl = <8>; + snps,mixed-burst; + phy-mode = "mii"; + }; + + //Example 3 + ethernet2: ethernet@40027000 { + compatible = "st,stm32-dwmac", "snps,dwmac-4.10a"; + reg = <0x40028000 0x8000>; + reg-names = "stmmaceth"; + interrupts = <61>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; + clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>; + st,syscon = <&syscfg 0x4>; + snps,pbl = <8>; + phy-mode = "mii"; + }; diff --git a/Bindings/net/ti,cpsw-switch.yaml b/Bindings/net/ti,cpsw-switch.yaml index 976f139bb66e..3ea0e1290dbb 100644 --- a/Bindings/net/ti,cpsw-switch.yaml +++ b/Bindings/net/ti,cpsw-switch.yaml @@ -23,14 +23,14 @@ properties: oneOf: - const: ti,cpsw-switch - items: - - const: ti,am335x-cpsw-switch - - const: ti,cpsw-switch + - const: ti,am335x-cpsw-switch + - const: ti,cpsw-switch - items: - - const: ti,am4372-cpsw-switch - - const: ti,cpsw-switch + - const: ti,am4372-cpsw-switch + - const: ti,cpsw-switch - items: - - const: ti,dra7-cpsw-switch - - const: ti,cpsw-switch + - const: ti,dra7-cpsw-switch + - const: ti,cpsw-switch reg: maxItems: 1 @@ -105,8 +105,7 @@ properties: description: label associated with this port ti,dual-emac-pvid: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 1024 description: @@ -150,10 +149,9 @@ properties: patternProperties: "^mdio@": type: object - allOf: - - $ref: "ti,davinci-mdio.yaml#" description: CPSW MDIO bus. + $ref: "ti,davinci-mdio.yaml#" required: diff --git a/Bindings/net/ti,davinci-mdio.yaml b/Bindings/net/ti,davinci-mdio.yaml index 242ac4935a4b..d454c1fab930 100644 --- a/Bindings/net/ti,davinci-mdio.yaml +++ b/Bindings/net/ti,davinci-mdio.yaml @@ -18,33 +18,31 @@ allOf: properties: compatible: oneOf: - - const: ti,davinci_mdio - - items: - - const: ti,keystone_mdio - - const: ti,davinci_mdio - - items: - - const: ti,cpsw-mdio - - const: ti,davinci_mdio - - items: - - const: ti,am4372-mdio - - const: ti,cpsw-mdio - - const: ti,davinci_mdio + - const: ti,davinci_mdio + - items: + - const: ti,keystone_mdio + - const: ti,davinci_mdio + - items: + - const: ti,cpsw-mdio + - const: ti,davinci_mdio + - items: + - const: ti,am4372-mdio + - const: ti,cpsw-mdio + - const: ti,davinci_mdio reg: maxItems: 1 bus_freq: - maximum: 2500000 - description: - MDIO Bus frequency + maximum: 2500000 + description: MDIO Bus frequency ti,hwmods: description: TI hwmod name deprecated: true - allOf: - - $ref: /schemas/types.yaml#/definitions/string-array - - items: - const: davinci_mdio + $ref: /schemas/types.yaml#/definitions/string-array + items: + const: davinci_mdio if: properties: diff --git a/Bindings/net/ti,dp83867.txt b/Bindings/net/ti,dp83867.txt deleted file mode 100644 index 44e2a4fab29e..000000000000 --- a/Bindings/net/ti,dp83867.txt +++ /dev/null @@ -1,68 +0,0 @@ -* Texas Instruments - dp83867 Giga bit ethernet phy - -Required properties: - - reg - The ID number for the phy, usually a small integer - - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h - for applicable values. Required only if interface type is - PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID - - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h - for applicable values. Required only if interface type is - PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID - -Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock delays - will be left at their default values, as set by the PHY's pin strapping. - The default strapping will use a delay of 2.00 ns. Thus - PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no - internal delay, but as PHY_INTERFACE_MODE_RGMII_ID. The device tree - should use "rgmii-id" if internal delays are desired as this may be - changed in future to cause "rgmii" mode to disable delays. - -Optional property: - - ti,min-output-impedance - MAC Interface Impedance control to set - the programmable output impedance to - minimum value (35 ohms). - - ti,max-output-impedance - MAC Interface Impedance control to set - the programmable output impedance to - maximum value (70 ohms). - - ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the - board has RX_DV/RX_CTRL pin strapped in - mode 1 or 2. To ensure PHY operation, - there are specific actions that - software needs to take when this pin is - strapped in these modes. See data manual - for details. - - ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h - for applicable values. The CLK_OUT pin can also - be disabled by this property. When omitted, the - PHY's default will be left as is. - - ti,sgmii-ref-clock-output-enable - This denotes which - SGMII configuration is used (4 or 6-wire modes). - Some MACs work with differential SGMII clock. - See data manual for details. - - - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h - for applicable values (deprecated) - - -tx-fifo-depth - As defined in the ethernet-controller.yaml. Values for - the depth can be found in dt-bindings/net/ti-dp83867.h - -rx-fifo-depth - As defined in the ethernet-controller.yaml. Values for - the depth can be found in dt-bindings/net/ti-dp83867.h - -Note: ti,min-output-impedance and ti,max-output-impedance are mutually - exclusive. When both properties are present ti,max-output-impedance - takes precedence. - -Default child nodes are standard Ethernet PHY device -nodes as described in Documentation/devicetree/bindings/net/phy.txt - -Example: - - ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,tx-internal-delay = ; - tx-fifo-depth = ; - }; - -Datasheet can be found: -http://www.ti.com/product/DP83867IR/datasheet diff --git a/Bindings/net/ti,dp83867.yaml b/Bindings/net/ti,dp83867.yaml new file mode 100644 index 000000000000..554dcd7a40a9 --- /dev/null +++ b/Bindings/net/ti,dp83867.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +# Copyright (C) 2019 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/ti,dp83867.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI DP83867 ethernet PHY + +allOf: + - $ref: "ethernet-controller.yaml#" + +maintainers: + - Dan Murphy + +description: | + The DP83867 device is a robust, low power, fully featured Physical Layer + transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX + and 1000BASE-T Ethernet protocols. + + The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet + LANs. It interfaces directly to twisted pair media via an external + transformer. This device interfaces directly to the MAC layer through the + IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit + Media Independent Interface (GMII) or Reduced GMII (RGMII). + + Specifications about the charger can be found at: + https://www.ti.com/lit/gpn/dp83867ir + +properties: + reg: + maxItems: 1 + + ti,min-output-impedance: + type: boolean + description: | + MAC Interface Impedance control to set the programmable output impedance + to a minimum value (35 ohms). + + ti,max-output-impedance: + type: boolean + description: | + MAC Interface Impedance control to set the programmable output impedance + to a maximum value (70 ohms). + Note: ti,min-output-impedance and ti,max-output-impedance are mutually + exclusive. When both properties are present ti,max-output-impedance + takes precedence. + + tx-fifo-depth: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + Transmitt FIFO depth see dt-bindings/net/ti-dp83867.h for values + + rx-fifo-depth: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + Receive FIFO depth see dt-bindings/net/ti-dp83867.h for values + + ti,clk-output-sel: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h + for applicable values. The CLK_OUT pin can also be disabled by this + property. When omitted, the PHY's default will be left as is. + + ti,rx-internal-delay: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values. Required only if interface type is + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID. + + ti,tx-internal-delay: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h + for applicable values. Required only if interface type is + PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID. + + Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock + delays will be left at their default values, as set by the PHY's pin + strapping. The default strapping will use a delay of 2.00 ns. Thus + PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no + internal delay, but as PHY_INTERFACE_MODE_RGMII_ID. The device tree + should use "rgmii-id" if internal delays are desired as this may be + changed in future to cause "rgmii" mode to disable delays. + + ti,dp83867-rxctrl-strap-quirk: + type: boolean + description: | + This denotes the fact that the board has RX_DV/RX_CTRL pin strapped in + mode 1 or 2. To ensure PHY operation, there are specific actions that + software needs to take when this pin is strapped in these modes. + See data manual for details. + + ti,sgmii-ref-clock-output-enable: + type: boolean + description: | + This denotes which SGMII configuration is used (4 or 6-wire modes). + Some MACs work with differential SGMII clock. See data manual for details. + + ti,fifo-depth: + deprecated: true + $ref: /schemas/types.yaml#definitions/uint32 + description: | + Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable + values. + +required: + - reg + +examples: + - | + #include + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + ethphy0: ethernet-phy@0 { + reg = <0>; + tx-fifo-depth = ; + rx-fifo-depth = ; + ti,max-output-impedance; + ti,clk-output-sel = ; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + }; + }; diff --git a/Bindings/net/ti,dp83869.yaml b/Bindings/net/ti,dp83869.yaml index 6fe3e451da8a..5b69ef03bbf7 100644 --- a/Bindings/net/ti,dp83869.yaml +++ b/Bindings/net/ti,dp83869.yaml @@ -1,4 +1,4 @@ -# SPDX-License-Identifier: GPL-2.0 +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) # Copyright (C) 2019 Texas Instruments Incorporated %YAML 1.2 --- diff --git a/Bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Bindings/net/ti,k3-am654-cpsw-nuss.yaml index 78bf511e2892..174579370a22 100644 --- a/Bindings/net/ti,k3-am654-cpsw-nuss.yaml +++ b/Bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -103,8 +103,7 @@ properties: type: object description: CPSW2G NUSS external ports - allOf: - - $ref: ethernet-controller.yaml# + $ref: ethernet-controller.yaml# properties: reg: @@ -139,11 +138,17 @@ properties: patternProperties: "^mdio@[0-9a-f]+$": type: object - allOf: - - $ref: "ti,davinci-mdio.yaml#" + $ref: "ti,davinci-mdio.yaml#" + description: CPSW MDIO bus. + "^cpts@[0-9a-f]+": + type: object + $ref: "ti,k3-am654-cpts.yaml#" + description: + CPSW Common Platform Time Sync (CPTS) module. + required: - compatible - reg @@ -164,38 +169,44 @@ examples: #include #include #include + #include + #include - mcu_cpsw: ethernet@46000000 { - compatible = "ti,am654-cpsw-nuss"; + bus { #address-cells = <2>; #size-cells = <2>; - reg = <0x0 0x46000000 0x0 0x200000>; - reg-names = "cpsw_nuss"; - ranges = <0x0 0x0 0x46000000 0x0 0x200000>; - dma-coherent; - clocks = <&k3_clks 5 10>; - clock-names = "fck"; - power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; - pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; - dmas = <&mcu_udmap 0xf000>, - <&mcu_udmap 0xf001>, - <&mcu_udmap 0xf002>, - <&mcu_udmap 0xf003>, - <&mcu_udmap 0xf004>, - <&mcu_udmap 0xf005>, - <&mcu_udmap 0xf006>, - <&mcu_udmap 0xf007>, - <&mcu_udmap 0x7000>; - dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "rx"; + mcu_cpsw: ethernet@46000000 { + compatible = "ti,am654-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0x46000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; + dma-coherent; + clocks = <&k3_clks 5 10>; + clock-names = "fck"; + power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; + dmas = <&mcu_udmap 0xf000>, + <&mcu_udmap 0xf001>, + <&mcu_udmap 0xf002>, + <&mcu_udmap 0xf003>, + <&mcu_udmap 0xf004>, + <&mcu_udmap 0xf005>, + <&mcu_udmap 0xf006>, + <&mcu_udmap 0xf007>, + <&mcu_udmap 0x7000>; + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", + "rx"; - cpsw_port1: port@1 { + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { reg = <1>; ti,mac-only; label = "port1"; @@ -204,22 +215,34 @@ examples: phy-mode = "rgmii-rxid"; phy-handle = <&phy0>; - }; - }; + }; + }; - davinci_mdio: mdio@f00 { - compatible = "ti,cpsw-mdio","ti,davinci_mdio"; - reg = <0x0 0xf00 0x0 0x100>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&k3_clks 5 10>; - clock-names = "fck"; - bus_freq = <1000000>; + davinci_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 5 10>; + clock-names = "fck"; + bus_freq = <1000000>; - phy0: ethernet-phy@0 { + phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; ti,fifo-depth = ; - }; + }; + }; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&k3_clks 18 2>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; }; }; diff --git a/Bindings/net/ti,k3-am654-cpts.yaml b/Bindings/net/ti,k3-am654-cpts.yaml new file mode 100644 index 000000000000..9b7117920d90 --- /dev/null +++ b/Bindings/net/ti,k3-am654-cpts.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,k3-am654-cpts.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module Device Tree Bindings + +maintainers: + - Grygorii Strashko + - Sekhar Nori + +description: |+ + The TI AM654x/J721E CPTS module is used to facilitate host control of time + sync operations. + Main features of CPTS module are + - selection of multiple external clock sources + - Software control of time sync events via interrupt or polling + - 64-bit timestamp mode in ns with PPM and nudge adjustment. + - hardware timestamp push inputs (HWx_TS_PUSH) + - timestamp counter compare output (TS_COMP) + - timestamp counter bit output (TS_SYNC) + - periodic Generator function outputs (TS_GENFx) + - Ethernet Enhanced Scheduled Traffic Operations (CPTS_ESTFn) (TSN) + - external hardware timestamp push inputs (HWx_TS_PUSH) timestamping + + Depending on integration it enables compliance with the IEEE 1588-2008 + standard for a precision clock synchronization protocol, Ethernet Enhanced + Scheduled Traffic Operations (CPTS_ESTFn) and PCIe Subsystem Precision Time + Measurement (PTM). + + TI AM654x/J721E SoCs has several similar CPTS modules integrated into the + different parts of the system which could be synchronized with each other + - Main CPTS + - MCU CPSW CPTS with IEEE 1588-2008 support + - PCIe subsystem CPTS for PTM support + + Depending on CPTS module integration and when CPTS is integral part of + another module (MCU CPSW for example) "compatible" and "reg" can + be omitted - parent module is fully responsible for CPTS enabling and + configuration. + +properties: + $nodename: + pattern: "^cpts@[0-9a-f]+$" + + compatible: + oneOf: + - const: ti,am65-cpts + - const: ti,j721e-cpts + + reg: + maxItems: 1 + description: + The physical base address and size of CPTS IO range + + reg-names: + items: + - const: cpts + + clocks: + description: CPTS reference clock + + clock-names: + items: + - const: cpts + + interrupts: + items: + - description: CPTS events interrupt + + interrupt-names: + items: + - const: cpts + + ti,cpts-ext-ts-inputs: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 8 + description: + Number of hardware timestamp push inputs (HWx_TS_PUSH) + + ti,cpts-periodic-outputs: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 8 + description: + Number of timestamp Generator function outputs (TS_GENFx) + + refclk-mux: + type: object + description: CPTS reference clock multiplexer clock + properties: + '#clock-cells': + const: 0 + + clocks: + maxItems: 8 + + assigned-clocks: + maxItems: 1 + + assigned-clocks-parents: + maxItems: 1 + + required: + - clocks + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include + #include + + cpts@310d0000 { + compatible = "ti,am65-cpts"; + reg = <0x310d0000 0x400>; + reg-names = "cpts"; + clocks = <&main_cpts_mux>; + clock-names = "cpts"; + interrupts-extended = <&k3_irq 163 0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-periodic-outputs = <6>; + ti,cpts-ext-ts-inputs = <8>; + + main_cpts_mux: refclk-mux { + #clock-cells = <0>; + clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, + <&k3_clks 157 91>, <&k3_clks 157 77>, + <&k3_clks 157 102>, <&k3_clks 157 80>, + <&k3_clks 120 3>, <&k3_clks 121 3>; + assigned-clocks = <&main_cpts_mux>; + assigned-clock-parents = <&k3_clks 118 11>; + }; + }; + diff --git a/Bindings/net/wireless/mediatek,mt76.txt b/Bindings/net/wireless/mediatek,mt76.txt index 3a76d8faaaed..ab7e7a00e534 100644 --- a/Bindings/net/wireless/mediatek,mt76.txt +++ b/Bindings/net/wireless/mediatek,mt76.txt @@ -25,6 +25,9 @@ Optional properties: - mediatek,mtd-eeprom: Specify a MTD partition + offset containing EEPROM data - big-endian: if the radio eeprom partition is written in big-endian, specify this property +- mediatek,eeprom-merge-otp: Merge EEPROM data with OTP data. Can be used on + boards where the flash calibration data is generic and specific calibration + data should be pulled from the OTP ROM The MAC address can as well be set with corresponding optional properties defined in net/ethernet.txt. diff --git a/Bindings/net/wireless/qcom,ath10k.txt b/Bindings/net/wireless/qcom,ath10k.txt index 71bf91f97386..65ee68efd574 100644 --- a/Bindings/net/wireless/qcom,ath10k.txt +++ b/Bindings/net/wireless/qcom,ath10k.txt @@ -96,6 +96,17 @@ Optional properties: - qcom,coexist-gpio-pin : gpio pin number information to support coex which will be used by wifi firmware. +* Subnodes +The ath10k wifi node can contain one optional firmware subnode. +Firmware subnode is needed when the platform does not have TustZone. +The firmware subnode must have: + +- iommus: + Usage: required + Value type: + Definition: A list of phandle and IOMMU specifier pairs. + + Example (to supply PCI based wifi block details): In this example, the node is defined as child node of the PCI controller. @@ -196,4 +207,7 @@ wifi@18000000 { memory-region = <&wifi_msa_mem>; iommus = <&apps_smmu 0x0040 0x1>; qcom,msa-fixed-perm; + wifi-firmware { + iommus = <&apps_iommu 0xc22 0x1>; + }; }; diff --git a/Bindings/nvmem/imx-iim.txt b/Bindings/nvmem/imx-iim.txt deleted file mode 100644 index 1978c5bcd96d..000000000000 --- a/Bindings/nvmem/imx-iim.txt +++ /dev/null @@ -1,22 +0,0 @@ -Freescale i.MX IC Identification Module (IIM) device tree bindings - -This binding represents the IC Identification Module (IIM) found on -i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 and i.MX53 SoCs. - -Required properties: -- compatible: should be one of - "fsl,imx25-iim", "fsl,imx27-iim", - "fsl,imx31-iim", "fsl,imx35-iim", - "fsl,imx51-iim", "fsl,imx53-iim", -- reg: Should contain the register base and length. -- interrupts: Should contain the interrupt for the IIM -- clocks: Should contain a phandle pointing to the gated peripheral clock. - -Example: - - iim: iim@63f98000 { - compatible = "fsl,imx53-iim", "fsl,imx27-iim"; - reg = <0x63f98000 0x4000>; - interrupts = <69>; - clocks = <&clks IMX5_CLK_IIM_GATE>; - }; diff --git a/Bindings/nvmem/imx-iim.yaml b/Bindings/nvmem/imx-iim.yaml new file mode 100644 index 000000000000..9cc43e7a4b38 --- /dev/null +++ b/Bindings/nvmem/imx-iim.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/imx-iim.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX IC Identification Module (IIM) device tree bindings + +maintainers: + - Anson Huang + +description: | + This binding represents the IC Identification Module (IIM) found on + i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 and i.MX53 SoCs. + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + enum: + - fsl,imx25-iim + - fsl,imx27-iim + - fsl,imx31-iim + - fsl,imx35-iim + - fsl,imx51-iim + - fsl,imx53-iim + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + + iim: efuse@63f98000 { + compatible = "fsl,imx53-iim"; + reg = <0x63f98000 0x4000>; + interrupts = <69>; + clocks = <&clks IMX5_CLK_IIM_GATE>; + }; + +... diff --git a/Bindings/nvmem/imx-ocotp.txt b/Bindings/nvmem/imx-ocotp.txt deleted file mode 100644 index 6e346d5cddcf..000000000000 --- a/Bindings/nvmem/imx-ocotp.txt +++ /dev/null @@ -1,50 +0,0 @@ -Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings - -This binding represents the on-chip eFuse OTP controller found on -i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL, -i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN and i.MX8MP SoCs. - -Required properties: -- compatible: should be one of - "fsl,imx6q-ocotp" (i.MX6Q/D/DL/S), - "fsl,imx6sl-ocotp" (i.MX6SL), or - "fsl,imx6sx-ocotp" (i.MX6SX), - "fsl,imx6ul-ocotp" (i.MX6UL), - "fsl,imx6ull-ocotp" (i.MX6ULL/ULZ), - "fsl,imx7d-ocotp" (i.MX7D/S), - "fsl,imx6sll-ocotp" (i.MX6SLL), - "fsl,imx7ulp-ocotp" (i.MX7ULP), - "fsl,imx8mq-ocotp" (i.MX8MQ), - "fsl,imx8mm-ocotp" (i.MX8MM), - "fsl,imx8mn-ocotp" (i.MX8MN), - "fsl,imx8mp-ocotp" (i.MX8MP), - followed by "syscon". -- #address-cells : Should be 1 -- #size-cells : Should be 1 -- reg: Should contain the register base and length. -- clocks: Should contain a phandle pointing to the gated peripheral clock. - -Optional properties: -- read-only: disable write access - -Optional Child nodes: - -- Data cells of ocotp: - Detailed bindings are described in bindings/nvmem/nvmem.txt - -Example: - ocotp: ocotp@21bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx6sx-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SX_CLK_OCOTP>; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; - }; diff --git a/Bindings/nvmem/imx-ocotp.yaml b/Bindings/nvmem/imx-ocotp.yaml new file mode 100644 index 000000000000..fe9c7df78ea1 --- /dev/null +++ b/Bindings/nvmem/imx-ocotp.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/imx-ocotp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings + +maintainers: + - Anson Huang + +description: | + This binding represents the on-chip eFuse OTP controller found on + i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL, + i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN and i.MX8MP SoCs. + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + items: + - enum: + - fsl,imx6q-ocotp + - fsl,imx6sl-ocotp + - fsl,imx6sx-ocotp + - fsl,imx6ul-ocotp + - fsl,imx6ull-ocotp + - fsl,imx7d-ocotp + - fsl,imx6sll-ocotp + - fsl,imx7ulp-ocotp + - fsl,imx8mq-ocotp + - fsl,imx8mm-ocotp + - fsl,imx8mn-ocotp + - fsl,imx8mp-ocotp + - const: syscon + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + clocks: + maxItems: 1 + +required: + - "#address-cells" + - "#size-cells" + - compatible + - reg + +patternProperties: + "^.*@[0-9a-f]+$": + type: object + + properties: + reg: + maxItems: 1 + description: + Offset and size in bytes within the storage device. + + required: + - reg + + additionalProperties: false + +examples: + - | + #include + + ocotp: efuse@21bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx6sx-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SX_CLK_OCOTP>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; + }; + +... diff --git a/Bindings/nvmem/mxs-ocotp.txt b/Bindings/nvmem/mxs-ocotp.txt deleted file mode 100644 index 372c72fd64dc..000000000000 --- a/Bindings/nvmem/mxs-ocotp.txt +++ /dev/null @@ -1,24 +0,0 @@ -On-Chip OTP Memory for Freescale i.MX23/i.MX28 - -Required properties : -- compatible : - - "fsl,imx23-ocotp" for i.MX23 - - "fsl,imx28-ocotp" for i.MX28 -- #address-cells : Should be 1 -- #size-cells : Should be 1 -- reg : Address and length of OTP controller registers -- clocks : Should contain a reference to the hbus clock - -= Data cells = -Are child nodes of mxs-ocotp, bindings of which as described in -bindings/nvmem/nvmem.txt - -Example for i.MX28: - - ocotp: ocotp@8002c000 { - compatible = "fsl,imx28-ocotp", "fsl,ocotp"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x8002c000 0x2000>; - clocks = <&clks 25>; - }; diff --git a/Bindings/nvmem/mxs-ocotp.yaml b/Bindings/nvmem/mxs-ocotp.yaml new file mode 100644 index 000000000000..ff317fd7c15b --- /dev/null +++ b/Bindings/nvmem/mxs-ocotp.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/mxs-ocotp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: On-Chip OTP Memory for Freescale i.MX23/i.MX28 + +maintainers: + - Anson Huang + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + enum: + - fsl,imx23-ocotp + - fsl,imx28-ocotp + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + ocotp: efuse@8002c000 { + compatible = "fsl,imx28-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x8002c000 0x2000>; + clocks = <&clks 25>; + }; + +... diff --git a/Bindings/nvmem/nvmem.yaml b/Bindings/nvmem/nvmem.yaml index 65980224d550..b459f9dba6c9 100644 --- a/Bindings/nvmem/nvmem.yaml +++ b/Bindings/nvmem/nvmem.yaml @@ -67,8 +67,6 @@ patternProperties: required: - reg - additionalProperties: false - examples: - | #include diff --git a/Bindings/nvmem/rockchip-efuse.txt b/Bindings/nvmem/rockchip-efuse.txt deleted file mode 100644 index 265bdb7dc8aa..000000000000 --- a/Bindings/nvmem/rockchip-efuse.txt +++ /dev/null @@ -1,54 +0,0 @@ -= Rockchip eFuse device tree bindings = - -Required properties: -- compatible: Should be one of the following. - - "rockchip,rk3066a-efuse" - for RK3066a SoCs. - - "rockchip,rk3188-efuse" - for RK3188 SoCs. - - "rockchip,rk3228-efuse" - for RK3228 SoCs. - - "rockchip,rk3288-efuse" - for RK3288 SoCs. - - "rockchip,rk3328-efuse" - for RK3328 SoCs. - - "rockchip,rk3368-efuse" - for RK3368 SoCs. - - "rockchip,rk3399-efuse" - for RK3399 SoCs. -- reg: Should contain the registers location and exact eFuse size -- clocks: Should be the clock id of eFuse -- clock-names: Should be "pclk_efuse" - -Optional properties: -- rockchip,efuse-size: Should be exact eFuse size in byte, the eFuse - size in property will be invalid if define this property. - -Deprecated properties: -- compatible: "rockchip,rockchip-efuse" - Old efuse compatible value compatible to rk3066a, rk3188 and rk3288 - efuses - -= Data cells = -Are child nodes of eFuse, bindings of which as described in -bindings/nvmem/nvmem.txt - -Example: - - efuse: efuse@ffb40000 { - compatible = "rockchip,rk3288-efuse"; - reg = <0xffb40000 0x20>; - #address-cells = <1>; - #size-cells = <1>; - clocks = <&cru PCLK_EFUSE256>; - clock-names = "pclk_efuse"; - - /* Data cells */ - cpu_leakage: cpu_leakage { - reg = <0x17 0x1>; - }; - }; - -= Data consumers = -Are device nodes which consume nvmem data cells. - -Example: - - cpu_leakage { - ... - nvmem-cells = <&cpu_leakage>; - nvmem-cell-names = "cpu_leakage"; - }; diff --git a/Bindings/nvmem/rockchip-efuse.yaml b/Bindings/nvmem/rockchip-efuse.yaml new file mode 100644 index 000000000000..3ae00b0b23bc --- /dev/null +++ b/Bindings/nvmem/rockchip-efuse.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/rockchip-efuse.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip eFuse device tree bindings + +maintainers: + - Heiko Stuebner + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + enum: + - rockchip,rk3066a-efuse + - rockchip,rk3188-efuse + - rockchip,rk3228-efuse + - rockchip,rk3288-efuse + - rockchip,rk3328-efuse + - rockchip,rk3368-efuse + - rockchip,rk3399-efuse + + # Deprecated: old compatible value for rk3066a, rk3188 and rk3288 + - rockchip,rockchip-efuse + + reg: + description: + Registers location and eFuse size. + maxItems: 1 + + clocks: + description: + eFuse clock id. + maxItems: 1 + + clock-names: + const: pclk_efuse + + rockchip,efuse-size: + description: + eFuse size in bytes. The eFuse size in property will be invalid if + this property is defined. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - clocks + - clock-names + +examples: + - | + #include + efuse: efuse@ffb40000 { + compatible = "rockchip,rk3288-efuse"; + reg = <0xffb40000 0x20>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE256>; + clock-names = "pclk_efuse"; + + /* Data cells */ + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; + }; +... diff --git a/Bindings/nvmem/st,stm32-romem.yaml b/Bindings/nvmem/st,stm32-romem.yaml index d84deb4774a4..c11c99f085d7 100644 --- a/Bindings/nvmem/st,stm32-romem.yaml +++ b/Bindings/nvmem/st,stm32-romem.yaml @@ -24,6 +24,18 @@ properties: - st,stm32f4-otp - st,stm32mp15-bsec +patternProperties: + "^.*@[0-9a-f]+$": + type: object + + properties: + st,non-secure-otp: + description: | + This property explicits a factory programmed area that both secure + and non-secure worlds can access. It is needed when, by default, the + related area can only be reached by the secure world. + type: boolean + required: - "#address-cells" - "#size-cells" @@ -41,6 +53,11 @@ examples: calib@22c { reg = <0x22c 0x2>; }; + + mac_addr@e4 { + reg = <0xe4 0x8>; + st,non-secure-otp; + }; }; ... diff --git a/Bindings/opp/opp.txt b/Bindings/opp/opp.txt index 68592271461f..9d16d417e9be 100644 --- a/Bindings/opp/opp.txt +++ b/Bindings/opp/opp.txt @@ -83,9 +83,14 @@ properties. Required properties: - opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer. This is a - required property for all device nodes but devices like power domains. The - power domain nodes must have another (implementation dependent) property which - uniquely identifies the OPP nodes. + required property for all device nodes, unless another "required" property to + uniquely identify the OPP nodes exists. Devices like power domains must have + another (implementation dependent) property. + +- opp-peak-kBps: Peak bandwidth in kilobytes per second, expressed as an array + of 32-bit big-endian integers. Each element of the array represents the + peak bandwidth value of each interconnect path. The number of elements should + match the number of interconnect paths. Optional properties: - opp-microvolt: voltage in micro Volts. @@ -132,6 +137,12 @@ Optional properties: - opp-level: A value representing the performance level of the device, expressed as a 32-bit integer. +- opp-avg-kBps: Average bandwidth in kilobytes per second, expressed as an array + of 32-bit big-endian integers. Each element of the array represents the + average bandwidth value of each interconnect path. The number of elements + should match the number of interconnect paths. This property is only + meaningful in OPP tables where opp-peak-kBps is present. + - clock-latency-ns: Specifies the maximum possible transition latency (in nanoseconds) for switching to this OPP from any other OPP. diff --git a/Bindings/pci/aardvark-pci.txt b/Bindings/pci/aardvark-pci.txt index 310ef7145c47..2b8ca920a7fa 100644 --- a/Bindings/pci/aardvark-pci.txt +++ b/Bindings/pci/aardvark-pci.txt @@ -19,6 +19,9 @@ contain the following properties: - interrupt-map-mask and interrupt-map: standard PCI properties to define the mapping of the PCIe interface to interrupt numbers. - bus-range: PCI bus numbers covered + - phys: the PCIe PHY handle + - max-link-speed: see pci.txt + - reset-gpios: see pci.txt In addition, the Device Tree describing an Aardvark PCIe controller must include a sub-node that describes the legacy interrupt controller @@ -48,6 +51,7 @@ Example: <0 0 0 2 &pcie_intc 1>, <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; + phys = <&comphy1 0>; pcie_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; diff --git a/Bindings/pci/brcm,stb-pcie.yaml b/Bindings/pci/brcm,stb-pcie.yaml index 77d3e81a437b..8680a0f86c5a 100644 --- a/Bindings/pci/brcm,stb-pcie.yaml +++ b/Bindings/pci/brcm,stb-pcie.yaml @@ -56,6 +56,8 @@ properties: description: Indicates usage of spread-spectrum clocking. type: boolean + aspm-no-l0s: true + required: - reg - dma-ranges diff --git a/Bindings/pci/cdns,cdns-pcie-ep.yaml b/Bindings/pci/cdns,cdns-pcie-ep.yaml index 2996f8d4777c..50ce5d79d2c7 100644 --- a/Bindings/pci/cdns,cdns-pcie-ep.yaml +++ b/Bindings/pci/cdns,cdns-pcie-ep.yaml @@ -10,7 +10,7 @@ maintainers: - Tom Joseph allOf: - - $ref: "cdns-pcie.yaml#" + - $ref: "cdns-pcie-ep.yaml#" - $ref: "pci-ep.yaml#" properties: diff --git a/Bindings/pci/cdns,cdns-pcie-host.yaml b/Bindings/pci/cdns,cdns-pcie-host.yaml index cabbe46ff578..84a8f095d031 100644 --- a/Bindings/pci/cdns,cdns-pcie-host.yaml +++ b/Bindings/pci/cdns,cdns-pcie-host.yaml @@ -45,8 +45,6 @@ examples: #size-cells = <2>; bus-range = <0x0 0xff>; linux,pci-domain = <0>; - cdns,max-outbound-regions = <16>; - cdns,no-bar-match-nbits = <32>; vendor-id = <0x17cd>; device-id = <0x0200>; @@ -57,6 +55,7 @@ examples: ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; #interrupt-cells = <0x1>; diff --git a/Bindings/pci/cdns-pcie-ep.yaml b/Bindings/pci/cdns-pcie-ep.yaml new file mode 100644 index 000000000000..016a5f61592d --- /dev/null +++ b/Bindings/pci/cdns-pcie-ep.yaml @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence PCIe Device + +maintainers: + - Tom Joseph + +allOf: + - $ref: "cdns-pcie.yaml#" + +properties: + cdns,max-outbound-regions: + description: maximum number of outbound regions + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 32 + +required: + - cdns,max-outbound-regions diff --git a/Bindings/pci/cdns-pcie-host.yaml b/Bindings/pci/cdns-pcie-host.yaml index ab6e43b636ec..303078a7b7a8 100644 --- a/Bindings/pci/cdns-pcie-host.yaml +++ b/Bindings/pci/cdns-pcie-host.yaml @@ -14,14 +14,22 @@ allOf: - $ref: "cdns-pcie.yaml#" properties: + cdns,max-outbound-regions: + description: maximum number of outbound regions + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 32 + deprecated: true + cdns,no-bar-match-nbits: description: Set into the no BAR match register to configure the number of least significant bits kept during inbound (PCIe -> AXI) address translations - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 64 default: 32 + deprecated: true msi-parent: true diff --git a/Bindings/pci/cdns-pcie.yaml b/Bindings/pci/cdns-pcie.yaml index 6887ccc339cc..02553d5e6c51 100644 --- a/Bindings/pci/cdns-pcie.yaml +++ b/Bindings/pci/cdns-pcie.yaml @@ -10,14 +10,6 @@ maintainers: - Tom Joseph properties: - cdns,max-outbound-regions: - description: maximum number of outbound regions - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 1 - maximum: 32 - default: 32 - phys: description: One per lane if more than one in the list. If only one PHY listed it must diff --git a/Bindings/pci/intel-gw-pcie.yaml b/Bindings/pci/intel-gw-pcie.yaml index 48a98dae00de..64b2c64ca806 100644 --- a/Bindings/pci/intel-gw-pcie.yaml +++ b/Bindings/pci/intel-gw-pcie.yaml @@ -71,10 +71,9 @@ properties: max-link-speed: description: Specify PCI Gen for link capability. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 1, 2, 3, 4 ] - - default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4] + default: 1 bus-range: description: Range of bus numbers associated with this controller. diff --git a/Bindings/pci/loongson.yaml b/Bindings/pci/loongson.yaml new file mode 100644 index 000000000000..30e7cf1aeb87 --- /dev/null +++ b/Bindings/pci/loongson.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/loongson.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson PCI Host Controller + +maintainers: + - Jiaxun Yang + +description: |+ + PCI host controller found on Loongson PCHs and SoCs. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + oneOf: + - const: loongson,ls2k-pci + - const: loongson,ls7a-pci + - const: loongson,rs780e-pci + + reg: + minItems: 1 + maxItems: 2 + items: + - description: CFG0 standard config space register + - description: CFG1 extended config space register + + ranges: + minItems: 1 + maxItems: 3 + + +required: + - compatible + - reg + - ranges + +examples: + - | + + bus { + #address-cells = <2>; + #size-cells = <2>; + pcie@1a000000 { + compatible = "loongson,rs780e-pci"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + // CPU_PHYSICAL(2) SIZE(2) + reg = <0x0 0x1a000000 0x0 0x2000000>; + + // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2) + ranges = <0x01000000 0x0 0x00004000 0x0 0x00004000 0x0 0x00004000>, + <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; + }; + }; +... diff --git a/Bindings/pci/pci-ep.yaml b/Bindings/pci/pci-ep.yaml index b3df100705b0..0f8e575ac01a 100644 --- a/Bindings/pci/pci-ep.yaml +++ b/Bindings/pci/pci-ep.yaml @@ -18,21 +18,18 @@ properties: max-functions: description: Maximum number of functions that can be configured - allOf: - - $ref: /schemas/types.yaml#/definitions/uint8 + $ref: /schemas/types.yaml#/definitions/uint8 minimum: 1 default: 1 maximum: 255 max-link-speed: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 1, 2, 3, 4 ] num-lanes: description: maximum number of lanes - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 default: 1 maximum: 16 diff --git a/Bindings/pci/pci-rcar-gen2.txt b/Bindings/pci/pci-rcar-gen2.txt index b94078f58d8e..aeba38f0a387 100644 --- a/Bindings/pci/pci-rcar-gen2.txt +++ b/Bindings/pci/pci-rcar-gen2.txt @@ -6,7 +6,8 @@ AHB. There is one bridge instance per USB port connected to the internal OHCI and EHCI controllers. Required properties: -- compatible: "renesas,pci-r8a7743" for the R8A7743 SoC; +- compatible: "renesas,pci-r8a7742" for the R8A7742 SoC; + "renesas,pci-r8a7743" for the R8A7743 SoC; "renesas,pci-r8a7744" for the R8A7744 SoC; "renesas,pci-r8a7745" for the R8A7745 SoC; "renesas,pci-r8a7790" for the R8A7790 SoC; diff --git a/Bindings/pci/rcar-pci-ep.yaml b/Bindings/pci/rcar-pci-ep.yaml new file mode 100644 index 000000000000..aa483c7f27fd --- /dev/null +++ b/Bindings/pci/rcar-pci-ep.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car PCIe Endpoint + +maintainers: + - Lad Prabhakar + - Yoshihiro Shimoda + +properties: + compatible: + items: + - const: renesas,r8a774c0-pcie-ep + - const: renesas,rcar-gen3-pcie-ep + + reg: + maxItems: 5 + + reg-names: + items: + - const: apb-base + - const: memory0 + - const: memory1 + - const: memory2 + - const: memory3 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pcie + + max-functions: + minimum: 1 + maximum: 1 + +required: + - compatible + - reg + - reg-names + - resets + - power-domains + - clocks + - clock-names + - max-functions + +examples: + - | + #include + #include + + pcie0_ep: pcie-ep@fe000000 { + compatible = "renesas,r8a774c0-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0xfe000000 0x80000>, + <0xfe100000 0x100000>, + <0xfe200000 0x200000>, + <0x30000000 0x8000000>, + <0x38000000 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + max-functions = /bits/ 8 <1>; + }; diff --git a/Bindings/pci/rcar-pci.txt b/Bindings/pci/rcar-pci.txt index 12702c8c46ce..1041c44a614f 100644 --- a/Bindings/pci/rcar-pci.txt +++ b/Bindings/pci/rcar-pci.txt @@ -11,7 +11,8 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC; "renesas,pcie-r8a7791" for the R8A7791 SoC; "renesas,pcie-r8a7793" for the R8A7793 SoC; "renesas,pcie-r8a7795" for the R8A7795 SoC; - "renesas,pcie-r8a7796" for the R8A7796 SoC; + "renesas,pcie-r8a7796" for the R8A77960 SoC; + "renesas,pcie-r8a77961" for the R8A77961 SoC; "renesas,pcie-r8a77980" for the R8A77980 SoC; "renesas,pcie-r8a77990" for the R8A77990 SoC; "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or diff --git a/Bindings/pci/socionext,uniphier-pcie-ep.yaml b/Bindings/pci/socionext,uniphier-pcie-ep.yaml new file mode 100644 index 000000000000..f0558b9cf9e9 --- /dev/null +++ b/Bindings/pci/socionext,uniphier-pcie-ep.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier PCIe endpoint controller + +description: | + UniPhier PCIe endpoint controller is based on the Synopsys DesignWare + PCI core. It shares common features with the PCIe DesignWare core and + inherits common properties defined in + Documentation/devicetree/bindings/pci/designware-pcie.txt. + +maintainers: + - Kunihiko Hayashi + +allOf: + - $ref: "pci-ep.yaml#" + +properties: + compatible: + const: socionext,uniphier-pro5-pcie-ep + + reg: + maxItems: 4 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: link + - const: addr_space + + clocks: + maxItems: 2 + + clock-names: + items: + - const: gio + - const: link + + resets: + maxItems: 2 + + reset-names: + items: + - const: gio + - const: link + + num-ib-windows: + const: 16 + + num-ob-windows: + const: 16 + + num-lanes: true + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + pcie_ep: pcie-ep@66000000 { + compatible = "socionext,uniphier-pro5-pcie-ep"; + reg-names = "dbi", "dbi2", "link", "addr_space"; + reg = <0x66000000 0x1000>, <0x66001000 0x1000>, + <0x66010000 0x10000>, <0x67000000 0x400000>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 24>; + reset-names = "gio", "link"; + resets = <&sys_rst 12>, <&sys_rst 24>; + num-ib-windows = <16>; + num-ob-windows = <16>; + num-lanes = <4>; + phy-names = "pcie-phy"; + phys = <&pcie_phy>; + }; diff --git a/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml b/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml index 88683db6cf81..18c1ec5e19ad 100644 --- a/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml +++ b/Bindings/phy/amlogic,meson-axg-mipi-pcie-analog.yaml @@ -30,6 +30,6 @@ examples: - | mpphy: phy@0 { compatible = "amlogic,axg-mipi-pcie-analog-phy"; - reg = <0x0 0x0 0x0 0xc>; + reg = <0x0 0xc>; #phy-cells = <1>; }; diff --git a/Bindings/phy/amlogic,meson-axg-pcie.yaml b/Bindings/phy/amlogic,meson-axg-pcie.yaml index 086478aec946..45f3d72b1cca 100644 --- a/Bindings/phy/amlogic,meson-axg-pcie.yaml +++ b/Bindings/phy/amlogic,meson-axg-pcie.yaml @@ -44,7 +44,7 @@ examples: #include pcie_phy: pcie-phy@ff644000 { compatible = "amlogic,axg-pcie-phy"; - reg = <0x0 0xff644000 0x0 0x1c>; + reg = <0xff644000 0x1c>; resets = <&reset RESET_PCIE_PHY>; phys = <&mipi_analog_phy PHY_TYPE_PCIE>; phy-names = "analog"; diff --git a/Bindings/phy/amlogic,meson8b-usb2-phy.yaml b/Bindings/phy/amlogic,meson8b-usb2-phy.yaml new file mode 100644 index 000000000000..03c4809dbe8d --- /dev/null +++ b/Bindings/phy/amlogic,meson8b-usb2-phy.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/amlogic,meson8b-usb2-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY + +maintainers: + - Martin Blumenstingl + +properties: + compatible: + oneOf: + - items: + - enum: + - amlogic,meson8-usb2-phy + - amlogic,meson8b-usb2-phy + - amlogic,meson8m2-usb2-phy + - const: amlogic,meson-mx-usb2-phy + - const: amlogic,meson-gxbb-usb2-phy + + reg: + maxItems: 1 + + clocks: + minItems: 2 + + clock-names: + items: + - const: usb_general + - const: usb + + resets: + minItems: 1 + + "#phy-cells": + const: 0 + + phy-supply: + description: + Phandle to a regulator that provides power to the PHY. This + regulator will be managed during the PHY power on/off sequence. + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + usb-phy@c0000000 { + compatible = "amlogic,meson-gxbb-usb2-phy"; + reg = <0xc0000000 0x20>; + resets = <&reset_usb_phy>; + clocks = <&clk_usb_general>, <&reset_usb>; + clock-names = "usb_general", "usb"; + phy-supply = <&usb_vbus>; + #phy-cells = <0>; + }; diff --git a/Bindings/phy/calxeda-combophy.txt b/Bindings/phy/calxeda-combophy.txt deleted file mode 100644 index 6622bdb2e8bc..000000000000 --- a/Bindings/phy/calxeda-combophy.txt +++ /dev/null @@ -1,17 +0,0 @@ -Calxeda Highbank Combination Phys for SATA - -Properties: -- compatible : Should be "calxeda,hb-combophy" -- #phy-cells: Should be 1. -- reg : Address and size for Combination Phy registers. -- phydev: device ID for programming the combophy. - -Example: - - combophy5: combo-phy@fff5d000 { - compatible = "calxeda,hb-combophy"; - #phy-cells = <1>; - reg = <0xfff5d000 0x1000>; - phydev = <31>; - }; - diff --git a/Bindings/phy/calxeda-combophy.yaml b/Bindings/phy/calxeda-combophy.yaml new file mode 100644 index 000000000000..41ee16e21f8d --- /dev/null +++ b/Bindings/phy/calxeda-combophy.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Calxeda Highbank Combination PHYs binding for SATA + +description: | + The Calxeda Combination PHYs connect the SoC to the internal fabric + and to SATA connectors. The PHYs support multiple protocols (SATA, + SGMII, PCIe) and can be assigned to different devices (SATA or XGMAC + controller). + Programming the PHYs is typically handled by those device drivers, + not by a dedicated PHY driver. + +maintainers: + - Andre Przywara + +properties: + compatible: + const: calxeda,hb-combophy + + '#phy-cells': + const: 1 + + reg: + maxItems: 1 + + phydev: + description: device ID for programming the ComboPHY. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 31 + +required: + - compatible + - reg + - phydev + - '#phy-cells' + +additionalProperties: false + +examples: + - | + combophy5: combo-phy@fff5d000 { + compatible = "calxeda,hb-combophy"; + #phy-cells = <1>; + reg = <0xfff5d000 0x1000>; + phydev = <31>; + }; diff --git a/Bindings/phy/cdns,salvo-phy.yaml b/Bindings/phy/cdns,salvo-phy.yaml new file mode 100644 index 000000000000..3a07285b5470 --- /dev/null +++ b/Bindings/phy/cdns,salvo-phy.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2020 NXP +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence SALVO PHY + +maintainers: + - Peter Chen + +properties: + compatible: + enum: + - nxp,salvo-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: salvo_phy_clk + + power-domains: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + + usb3phy: usb3-phy@5b160000 { + compatible = "nxp,salvo-phy"; + reg = <0x5b160000 0x40000>; + clocks = <&usb3_lpcg 4>; + clock-names = "salvo_phy_clk"; + power-domains = <&pd IMX_SC_R_USB_2_PHY>; + #phy-cells = <0>; + }; diff --git a/Bindings/phy/intel,combo-phy.yaml b/Bindings/phy/intel,combo-phy.yaml new file mode 100644 index 000000000000..347d0cdfb80d --- /dev/null +++ b/Bindings/phy/intel,combo-phy.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel ComboPhy Subsystem + +maintainers: + - Dilip Kota + +description: | + Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA + controllers. A single Combophy provides two PHY instances. + +properties: + $nodename: + pattern: "combophy(@.*|-[0-9a-f])*$" + + compatible: + items: + - const: intel,combophy-lgm + - const: intel,combo-phy + + clocks: + maxItems: 1 + + reg: + items: + - description: ComboPhy core registers + - description: PCIe app core control registers + + reg-names: + items: + - const: core + - const: app + + resets: + maxItems: 4 + + reset-names: + items: + - const: phy + - const: core + - const: iphy0 + - const: iphy1 + + intel,syscfg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: Chip configuration registers handle and ComboPhy instance id + + intel,hsio: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: HSIO registers handle and ComboPhy instance id on NOC + + intel,aggregation: + type: boolean + description: | + Specify the flag to configure ComboPHY in dual lane mode. + + intel,phy-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Mode of the two phys in ComboPhy. + See dt-bindings/phy/phy.h for values. + + "#phy-cells": + const: 1 + +required: + - compatible + - clocks + - reg + - reg-names + - intel,syscfg + - intel,hsio + - intel,phy-mode + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + combophy@d0a00000 { + compatible = "intel,combophy-lgm", "intel,combo-phy"; + clocks = <&cgu0 1>; + #phy-cells = <1>; + reg = <0xd0a00000 0x40000>, + <0xd0a40000 0x1000>; + reg-names = "core", "app"; + resets = <&rcu0 0x50 6>, + <&rcu0 0x50 17>, + <&rcu0 0x50 23>, + <&rcu0 0x50 24>; + reset-names = "phy", "core", "iphy0", "iphy1"; + intel,syscfg = <&sysconf 0>; + intel,hsio = <&hsiol 0>; + intel,phy-mode = ; + intel,aggregation; + }; diff --git a/Bindings/phy/intel,lgm-emmc-phy.yaml b/Bindings/phy/intel,lgm-emmc-phy.yaml index 9a346d6290d9..77bb5309918e 100644 --- a/Bindings/phy/intel,lgm-emmc-phy.yaml +++ b/Bindings/phy/intel,lgm-emmc-phy.yaml @@ -23,7 +23,7 @@ description: |+ properties: compatible: - const: intel,lgm-emmc-phy + const: intel,lgm-emmc-phy "#phy-cells": const: 0 diff --git a/Bindings/phy/meson-gxl-usb3-phy.txt b/Bindings/phy/meson-gxl-usb3-phy.txt deleted file mode 100644 index 114947e1de3d..000000000000 --- a/Bindings/phy/meson-gxl-usb3-phy.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Amlogic Meson GXL and GXM USB3 PHY and OTG detection binding - -Required properties: -- compatible: Should be "amlogic,meson-gxl-usb3-phy" -- #phys-cells: must be 0 (see phy-bindings.txt in this directory) -- reg: The base address and length of the registers -- interrupts: the interrupt specifier for the OTG detection -- clocks: phandles to the clocks for - - the USB3 PHY - - and peripheral mode/OTG detection -- clock-names: must contain "phy" and "peripheral" -- resets: phandle to the reset lines for: - - the USB3 PHY and - - peripheral mode/OTG detection -- reset-names: must contain "phy" and "peripheral" - -Optional properties: -- phy-supply: see phy-bindings.txt in this directory - - -Example: - usb3_phy0: phy@78080 { - compatible = "amlogic,meson-gxl-usb3-phy"; - #phy-cells = <0>; - reg = <0x0 0x78080 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_USB_OTG>, <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "phy", "peripheral"; - resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>; - reset-names = "phy", "peripheral"; - }; diff --git a/Bindings/phy/meson8b-usb2-phy.txt b/Bindings/phy/meson8b-usb2-phy.txt deleted file mode 100644 index d81d73aea608..000000000000 --- a/Bindings/phy/meson8b-usb2-phy.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Amlogic Meson8, Meson8b and GXBB USB2 PHY - -Required properties: -- compatible: Depending on the platform this should be one of: - "amlogic,meson8-usb2-phy" - "amlogic,meson8b-usb2-phy" - "amlogic,meson-gxbb-usb2-phy" -- reg: The base address and length of the registers -- #phys-cells: should be 0 (see phy-bindings.txt in this directory) -- clocks: phandle and clock identifier for the phy clocks -- clock-names: "usb_general" and "usb" - -Optional properties: -- resets: reference to the reset controller -- phy-supply: see phy-bindings.txt in this directory - - -Example: - -usb0_phy: usb-phy@c0000000 { - compatible = "amlogic,meson-gxbb-usb2-phy"; - #phy-cells = <0>; - reg = <0x0 0xc0000000 0x0 0x20>; - resets = <&reset RESET_USB_OTG>; - clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; - clock-names = "usb_general", "usb"; - phy-supply = <&usb_vbus>; -}; diff --git a/Bindings/phy/phy-cadence-torrent.yaml b/Bindings/phy/phy-cadence-torrent.yaml index c779a3c7d87a..4071438be2ba 100644 --- a/Bindings/phy/phy-cadence-torrent.yaml +++ b/Bindings/phy/phy-cadence-torrent.yaml @@ -77,24 +77,21 @@ patternProperties: description: Specifies the type of PHY for which the group of PHY lanes is used. Refer include/dt-bindings/phy/phy.h. Constants from the header should be used. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [1, 2, 3, 4, 5, 6] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4, 5, 6] cdns,num-lanes: description: Number of DisplayPort lanes. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [1, 2, 4] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4] default: 4 cdns,max-bit-rate: description: Maximum DisplayPort link bit rate to use, in Mbps - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100] default: 8100 required: @@ -120,24 +117,30 @@ additionalProperties: false examples: - | #include - torrent_phy: torrent-phy@f0fb500000 { - compatible = "cdns,torrent-phy"; - reg = <0xf0 0xfb500000 0x0 0x00100000>, - <0xf0 0xfb030a00 0x0 0x00000040>; - reg-names = "torrent_phy", "dptx_phy"; - resets = <&phyrst 0>; - clocks = <&ref_clk>; - clock-names = "refclk"; - #address-cells = <1>; - #size-cells = <0>; - torrent_phy_dp: phy@0 { - reg = <0>; - resets = <&phyrst 1>, <&phyrst 2>, - <&phyrst 3>, <&phyrst 4>; - #phy-cells = <0>; - cdns,phy-type = ; - cdns,num-lanes = <4>; - cdns,max-bit-rate = <8100>; - }; + + bus { + #address-cells = <2>; + #size-cells = <2>; + + torrent-phy@f0fb500000 { + compatible = "cdns,torrent-phy"; + reg = <0xf0 0xfb500000 0x0 0x00100000>, + <0xf0 0xfb030a00 0x0 0x00000040>; + reg-names = "torrent_phy", "dptx_phy"; + resets = <&phyrst 0>; + clocks = <&ref_clk>; + clock-names = "refclk"; + #address-cells = <1>; + #size-cells = <0>; + phy@0 { + reg = <0>; + resets = <&phyrst 1>, <&phyrst 2>, + <&phyrst 3>, <&phyrst 4>; + #phy-cells = <0>; + cdns,phy-type = ; + cdns,num-lanes = <4>; + cdns,max-bit-rate = <8100>; + }; + }; }; ... diff --git a/Bindings/phy/qcom,qmp-phy.yaml b/Bindings/phy/qcom,qmp-phy.yaml new file mode 100644 index 000000000000..f80f8896d527 --- /dev/null +++ b/Bindings/phy/qcom,qmp-phy.yaml @@ -0,0 +1,317 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm QMP PHY controller + +maintainers: + - Manu Gautam + +description: + QMP phy controller supports physical layer functionality for a number of + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +properties: + compatible: + enum: + - qcom,ipq8074-qmp-pcie-phy + - qcom,msm8996-qmp-pcie-phy + - qcom,msm8996-qmp-ufs-phy + - qcom,msm8996-qmp-usb3-phy + - qcom,msm8998-qmp-pcie-phy + - qcom,msm8998-qmp-ufs-phy + - qcom,msm8998-qmp-usb3-phy + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phy + - qcom,sdm845-qmp-ufs-phy + - qcom,sdm845-qmp-usb3-uni-phy + - qcom,sm8150-qmp-ufs-phy + - qcom,sm8250-qmp-ufs-phy + + reg: + items: + - description: Address and length of PHY's common serdes block. + + "#clock-cells": + enum: [ 1, 2 ] + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + ranges: true + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + resets: + minItems: 1 + maxItems: 3 + + reset-names: + minItems: 1 + maxItems: 3 + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + + vddp-ref-clk-supply: + description: + Phandle to a regulator supply to any specific refclk + pll block. + +#Required nodes: +patternProperties: + "^phy@[0-9a-f]+$": + type: object + description: + Each device node of QMP phy is required to have as many child nodes as + the number of lanes the PHY has. + +required: + - compatible + - reg + - "#clock-cells" + - "#address-cells" + - "#size-cells" + - ranges + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-qmp-usb3-uni-phy + then: + properties: + clocks: + items: + - description: Phy aux clock. + - description: Phy config clock. + - description: 19.2 MHz ref clk. + - description: Phy common block aux clock. + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: com_aux + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + reset-names: + items: + - const: phy + - const: common + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-qmp-pcie-phy + then: + properties: + clocks: + items: + - description: Phy aux clock. + - description: Phy config clock. + - description: 19.2 MHz ref clk. + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + - description: phy's ahb cfg block reset. + reset-names: + items: + - const: phy + - const: common + - const: cfg + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-qmp-usb3-phy + - qcom,msm8998-qmp-pcie-phy + - qcom,msm8998-qmp-usb3-phy + then: + properties: + clocks: + items: + - description: Phy aux clock. + - description: Phy config clock. + - description: 19.2 MHz ref clk. + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + reset-names: + items: + - const: phy + - const: common + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-qmp-ufs-phy + then: + properties: + clocks: + items: + - description: 19.2 MHz ref clk. + clock-names: + items: + - const: ref + resets: + items: + - description: PHY reset in the UFS controller. + reset-names: + items: + - const: ufsphy + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-qmp-ufs-phy + - qcom,sdm845-qmp-ufs-phy + - qcom,sm8150-qmp-ufs-phy + - qcom,sm8250-qmp-ufs-phy + then: + properties: + clocks: + items: + - description: 19.2 MHz ref clk. + - description: Phy reference aux clock. + clock-names: + items: + - const: ref + - const: ref_aux + resets: + items: + - description: PHY reset in the UFS controller. + reset-names: + items: + - const: ufsphy + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8074-qmp-pcie-phy + then: + properties: + clocks: + items: + - description: pipe clk. + clock-names: + items: + - const: pipe_clk + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + reset-names: + items: + - const: phy + - const: common + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phy + then: + properties: + clocks: + items: + - description: Phy aux clock. + - description: Phy config clock. + - description: 19.2 MHz ref clk. + - description: Phy refgen clk. + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: refgen + resets: + items: + - description: reset of phy block. + reset-names: + items: + - const: phy + +examples: + - | + #include + usb_2_qmpphy: phy-wrapper@88eb000 { + compatible = "qcom,sdm845-qmp-usb3-uni-phy"; + reg = <0x088eb000 0x18c>; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x088eb000 0x2000>; + + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_PHY_SEC_BCR>; + reset-names = "phy", "common"; + + vdda-phy-supply = <&vdda_usb2_ss_1p2>; + vdda-pll-supply = <&vdda_usb2_ss_core>; + + usb_2_ssphy: phy@200 { + reg = <0x200 0x128>, + <0x400 0x1fc>, + <0x800 0x218>, + <0x600 0x70>; + #clock-cells = <0>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; diff --git a/Bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Bindings/phy/qcom,qmp-usb3-dp-phy.yaml new file mode 100644 index 000000000000..6e2487501457 --- /dev/null +++ b/Bindings/phy/qcom,qmp-usb3-dp-phy.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm QMP USB3 DP PHY controller + +maintainers: + - Manu Gautam + +properties: + compatible: + enum: + - qcom,sc7180-qmp-usb3-phy + - qcom,sdm845-qmp-usb3-phy + reg: + items: + - description: Address and length of PHY's common serdes block. + - description: Address and length of the DP_COM control block. + + reg-names: + items: + - const: reg-base + - const: dp_com + + "#clock-cells": + enum: [ 1, 2 ] + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + ranges: true + + clocks: + items: + - description: Phy aux clock. + - description: Phy config clock. + - description: 19.2 MHz ref clk. + - description: Phy common block aux clock. + + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: com_aux + + resets: + items: + - description: reset of phy block. + - description: phy common block reset. + + reset-names: + items: + - const: phy + - const: common + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + + vddp-ref-clk-supply: + description: + Phandle to a regulator supply to any specific refclk + pll block. + +#Required nodes: +patternProperties: + "^phy@[0-9a-f]+$": + type: object + description: + Each device node of QMP phy is required to have as many child nodes as + the number of lanes the PHY has. + +required: + - compatible + - reg + - reg-names + - "#clock-cells" + - "#address-cells" + - "#size-cells" + - ranges + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include + usb_1_qmpphy: phy-wrapper@88e9000 { + compatible = "qcom,sdm845-qmp-usb3-phy"; + reg = <0x088e9000 0x18c>, + <0x088e8000 0x10>; + reg-names = "reg-base", "dp_com"; + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x088e9000 0x1000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "com_aux"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + vdda-phy-supply = <&vdda_usb2_ss_1p2>; + vdda-pll-supply = <&vdda_usb2_ss_core>; + + phy@200 { + reg = <0x200 0x128>, + <0x400 0x200>, + <0xc00 0x218>, + <0x600 0x128>, + <0x800 0x200>, + <0xa00 0x100>; + #clock-cells = <0>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; diff --git a/Bindings/phy/qcom,qusb2-phy.yaml b/Bindings/phy/qcom,qusb2-phy.yaml index f8bd28ff31c1..b5a6195de7ff 100644 --- a/Bindings/phy/qcom,qusb2-phy.yaml +++ b/Bindings/phy/qcom,qusb2-phy.yaml @@ -83,31 +83,28 @@ then: It is a 6 bit value that specifies offset to be added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY tuning parameter that may vary for different boards of same SOC. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - maximum: 63 - default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 63 + default: 0 qcom,bias-ctrl-value: description: It is a 6 bit value that specifies bias-ctrl-value. It is a PHY tuning parameter that may vary for different boards of same SOC. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - maximum: 63 - default: 32 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 63 + default: 32 qcom,charge-ctrl-value: - description: + description: It is a 2 bit value that specifies charge-ctrl-value. It is a PHY tuning parameter that may vary for different boards of same SOC. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - maximum: 3 - default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 0 qcom,hstx-trim-value: description: @@ -115,22 +112,20 @@ then: output current. Possible range is - 15mA to 24mA (stepsize of 600 uA). See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - maximum: 15 - default: 3 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + default: 3 qcom,preemphasis-level: description: It is a 2 bit value that specifies pre-emphasis level. Possible range is 0 to 15% (stepsize of 5%). See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - maximum: 3 - default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 2 qcom,preemphasis-width: description: @@ -138,21 +133,19 @@ then: pre-emphasis (specified using qcom,preemphasis-level) must be in effect. Duration could be half-bit of full-bit. See dt-bindings/phy/phy-qcom-qusb2.h for applicable values. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - maximum: 1 - default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 1 + default: 0 qcom,hsdisc-trim-value: description: It is a 2 bit value tuning parameter that control disconnect threshold and may vary for different boards of same SOC. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 0 - maximum: 3 - default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + default: 0 required: - compatible diff --git a/Bindings/phy/qcom,usb-snps-femto-v2.yaml b/Bindings/phy/qcom,usb-snps-femto-v2.yaml new file mode 100644 index 000000000000..4949a2851532 --- /dev/null +++ b/Bindings/phy/qcom,usb-snps-femto-v2.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Synopsys Femto High-Speed USB PHY V2 + +maintainers: + - Wesley Cheng + +description: | + Qualcomm High-Speed USB PHY + +properties: + compatible: + enum: + - qcom,usb-snps-hs-7nm-phy + - qcom,sm8150-usb-hs-phy + - qcom,usb-snps-femto-v2-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + items: + - description: rpmhcc ref clock + + clock-names: + items: + - const: ref + + resets: + items: + - description: PHY core reset + + vdda-pll-supply: + description: phandle to the regulator VDD supply node. + + vdda18-supply: + description: phandle to the regulator 1.8V supply node. + + vdda33-supply: + description: phandle to the regulator 3.3V supply node. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - resets + - vdda-pll-supply + - vdda18-supply + - vdda33-supply + +additionalProperties: false + +examples: + - | + #include + #include + phy@88e2000 { + compatible = "qcom,sm8150-usb-hs-phy"; + reg = <0x088e2000 0x400>; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + vdda-pll-supply = <&vdd_usb_hs_core>; + vdda33-supply = <&vdda_usb_hs_3p1>; + vdda18-supply = <&vdda_usb_hs_1p8>; + }; +... diff --git a/Bindings/phy/qcom-qmp-phy.txt b/Bindings/phy/qcom-qmp-phy.txt deleted file mode 100644 index 54d6f8d43508..000000000000 --- a/Bindings/phy/qcom-qmp-phy.txt +++ /dev/null @@ -1,242 +0,0 @@ -Qualcomm QMP PHY controller -=========================== - -QMP phy controller supports physical layer functionality for a number of -controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. - -Required properties: - - compatible: compatible list, contains: - "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 - "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, - "qcom,msm8996-qmp-ufs-phy" for 14nm UFS phy on msm8996, - "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996, - "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998, - "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998, - "qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998, - "qcom,sdm845-qhp-pcie-phy" for QHP PCIe phy on sdm845, - "qcom,sdm845-qmp-pcie-phy" for QMP PCIe phy on sdm845, - "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845, - "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845, - "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845, - "qcom,sm8150-qmp-ufs-phy" for UFS QMP phy on sm8150. - -- reg: - - index 0: address and length of register set for PHY's common - serdes block. - - index 1: address and length of the DP_COM control block (for - "qcom,sdm845-qmp-usb3-phy" only). - -- reg-names: - - For "qcom,sdm845-qmp-usb3-phy": - - Should be: "reg-base", "dp_com" - - For all others: - - The reg-names property shouldn't be defined. - - - #address-cells: must be 1 - - #size-cells: must be 1 - - ranges: must be present - - - clocks: a list of phandles and clock-specifier pairs, - one for each entry in clock-names. - - clock-names: "cfg_ahb" for phy config clock, - "aux" for phy aux clock, - "ref" for 19.2 MHz ref clk, - "com_aux" for phy common block aux clock, - "ref_aux" for phy reference aux clock, - - For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed. - For "qcom,msm8996-qmp-pcie-phy" must contain: - "aux", "cfg_ahb", "ref". - For "qcom,msm8996-qmp-ufs-phy" must contain: - "ref". - For "qcom,msm8996-qmp-usb3-phy" must contain: - "aux", "cfg_ahb", "ref". - For "qcom,msm8998-qmp-usb3-phy" must contain: - "aux", "cfg_ahb", "ref". - For "qcom,msm8998-qmp-ufs-phy" must contain: - "ref", "ref_aux". - For "qcom,msm8998-qmp-pcie-phy" must contain: - "aux", "cfg_ahb", "ref". - For "qcom,sdm845-qhp-pcie-phy" must contain: - "aux", "cfg_ahb", "ref", "refgen". - For "qcom,sdm845-qmp-pcie-phy" must contain: - "aux", "cfg_ahb", "ref", "refgen". - For "qcom,sdm845-qmp-usb3-phy" must contain: - "aux", "cfg_ahb", "ref", "com_aux". - For "qcom,sdm845-qmp-usb3-uni-phy" must contain: - "aux", "cfg_ahb", "ref", "com_aux". - For "qcom,sdm845-qmp-ufs-phy" must contain: - "ref", "ref_aux". - For "qcom,sm8150-qmp-ufs-phy" must contain: - "ref", "ref_aux". - - - resets: a list of phandles and reset controller specifier pairs, - one for each entry in reset-names. - - reset-names: "phy" for reset of phy block, - "common" for phy common block reset, - "cfg" for phy's ahb cfg block reset, - "ufsphy" for the PHY reset in the UFS controller. - - For "qcom,ipq8074-qmp-pcie-phy" must contain: - "phy", "common". - For "qcom,msm8996-qmp-pcie-phy" must contain: - "phy", "common", "cfg". - For "qcom,msm8996-qmp-ufs-phy": must contain: - "ufsphy". - For "qcom,msm8996-qmp-usb3-phy" must contain - "phy", "common". - For "qcom,msm8998-qmp-usb3-phy" must contain - "phy", "common". - For "qcom,msm8998-qmp-ufs-phy": must contain: - "ufsphy". - For "qcom,msm8998-qmp-pcie-phy" must contain: - "phy", "common". - For "qcom,sdm845-qhp-pcie-phy" must contain: - "phy". - For "qcom,sdm845-qmp-pcie-phy" must contain: - "phy". - For "qcom,sdm845-qmp-usb3-phy" must contain: - "phy", "common". - For "qcom,sdm845-qmp-usb3-uni-phy" must contain: - "phy", "common". - For "qcom,sdm845-qmp-ufs-phy": must contain: - "ufsphy". - For "qcom,sm8150-qmp-ufs-phy": must contain: - "ufsphy". - - - vdda-phy-supply: Phandle to a regulator supply to PHY core block. - - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. - -Optional properties: - - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk - pll block. - -Required nodes: - - Each device node of QMP phy is required to have as many child nodes as - the number of lanes the PHY has. - -Required properties for child nodes of PCIe PHYs (one child per lane): - - reg: list of offset and length pairs of register sets for PHY blocks - - tx, rx, pcs, and pcs_misc (optional). - - #phy-cells: must be 0 - -Required properties for a single "lanes" child node of non-PCIe PHYs: - - reg: list of offset and length pairs of register sets for PHY blocks - For 1-lane devices: - tx, rx, pcs, and (optionally) pcs_misc - For 2-lane devices: - tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc - - #phy-cells: must be 0 - -Required properties for child node of PCIe and USB3 qmp phys: - - clocks: a list of phandles and clock-specifier pairs, - one for each entry in clock-names. - - clock-names: Must contain following: - "pipe" for pipe clock specific to each lane. - - clock-output-names: Name of the PHY clock that will be the parent for - the above pipe clock. - For "qcom,ipq8074-qmp-pcie-phy": - - "pcie20_phy0_pipe_clk" Pipe Clock parent - (or) - "pcie20_phy1_pipe_clk" - - #clock-cells: must be 0 - - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then - gate-controlled by the gcc. - -Required properties for child node of PHYs with lane reset, AKA: - "qcom,msm8996-qmp-pcie-phy" - - resets: a list of phandles and reset controller specifier pairs, - one for each entry in reset-names. - - reset-names: Must contain following: - "lane" for reset specific to each lane. - -Example: - phy@34000 { - compatible = "qcom,msm8996-qmp-pcie-phy"; - reg = <0x34000 0x488>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; - - vdda-phy-supply = <&pm8994_l28>; - vdda-pll-supply = <&pm8994_l12>; - - resets = <&gcc GCC_PCIE_PHY_BCR>, - <&gcc GCC_PCIE_PHY_COM_BCR>, - <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; - reset-names = "phy", "common", "cfg"; - - pciephy_0: lane@35000 { - reg = <0x35000 0x130>, - <0x35200 0x200>, - <0x35400 0x1dc>; - #clock-cells = <0>; - #phy-cells = <0>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "pcie_0_pipe_clk_src"; - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "lane0"; - }; - - pciephy_1: lane@36000 { - ... - ... - }; - - phy@88eb000 { - compatible = "qcom,sdm845-qmp-usb3-uni-phy"; - reg = <0x88eb000 0x18c>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_USB3_SEC_CLKREF_CLK>, - <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "com_aux"; - - resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, - <&gcc GCC_USB3_PHY_SEC_BCR>; - reset-names = "phy", "common"; - - lane@88eb200 { - reg = <0x88eb200 0x128>, - <0x88eb400 0x1fc>, - <0x88eb800 0x218>, - <0x88eb600 0x70>; - #clock-cells = <0>; - #phy-cells = <0>; - clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_uni_phy_pipe_clk_src"; - }; - }; - - phy@1d87000 { - compatible = "qcom,sdm845-qmp-ufs-phy"; - reg = <0x1d87000 0x18c>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clock-names = "ref", - "ref_aux"; - clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; - - lanes@1d87400 { - reg = <0x1d87400 0x108>, - <0x1d87600 0x1e0>, - <0x1d87c00 0x1dc>, - <0x1d87800 0x108>, - <0x1d87a00 0x1e0>; - #phy-cells = <0>; - }; - }; diff --git a/Bindings/phy/qcom-usb-ipq4019-phy.yaml b/Bindings/phy/qcom-usb-ipq4019-phy.yaml new file mode 100644 index 000000000000..1118fe69b611 --- /dev/null +++ b/Bindings/phy/qcom-usb-ipq4019-phy.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcom IPQ40xx Dakota HS/SS USB PHY + +maintainers: + - Robert Marko + +properties: + compatible: + enum: + - qcom,usb-ss-ipq4019-phy + - qcom,usb-hs-ipq4019-phy + + reg: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: por_rst + - const: srif_rst + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - resets + - reset-names + - "#phy-cells" + +examples: + - | + #include + + hsphy@a8000 { + #phy-cells = <0>; + compatible = "qcom,usb-hs-ipq4019-phy"; + reg = <0xa8000 0x40>; + resets = <&gcc USB2_HSPHY_POR_ARES>, + <&gcc USB2_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + }; diff --git a/Bindings/phy/rcar-gen2-phy.txt b/Bindings/phy/rcar-gen2-phy.txt index ac96d6481bb8..a3bd1c4499b7 100644 --- a/Bindings/phy/rcar-gen2-phy.txt +++ b/Bindings/phy/rcar-gen2-phy.txt @@ -4,7 +4,8 @@ This file provides information on what the device node for the R-Car generation 2 USB PHY contains. Required properties: -- compatible: "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC. +- compatible: "renesas,usb-phy-r8a7742" if the device is a part of R8A7742 SoC. + "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC. "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC. "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC. "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC. diff --git a/Bindings/phy/rcar-gen3-phy-usb2.txt b/Bindings/phy/rcar-gen3-phy-usb2.txt deleted file mode 100644 index 7734b219d9aa..000000000000 --- a/Bindings/phy/rcar-gen3-phy-usb2.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Renesas R-Car generation 3 USB 2.0 PHY - -This file provides information on what the device node for the R-Car generation -3, RZ/G1C, RZ/G2 and RZ/A2 USB 2.0 PHY contain. - -Required properties: -- compatible: "renesas,usb2-phy-r7s9210" if the device is a part of an R7S9210 - SoC. - "renesas,usb2-phy-r8a77470" if the device is a part of an R8A77470 - SoC. - "renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1 - SoC. - "renesas,usb2-phy-r8a774b1" if the device is a part of an R8A774B1 - SoC. - "renesas,usb2-phy-r8a774c0" if the device is a part of an R8A774C0 - SoC. - "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795 - SoC. - "renesas,usb2-phy-r8a7796" if the device is a part of an R8A7796 - SoC. - "renesas,usb2-phy-r8a77965" if the device is a part of an - R8A77965 SoC. - "renesas,usb2-phy-r8a77990" if the device is a part of an - R8A77990 SoC. - "renesas,usb2-phy-r8a77995" if the device is a part of an - R8A77995 SoC. - "renesas,rcar-gen3-usb2-phy" for a generic R-Car Gen3, RZ/G2 or - RZ/A2 compatible device. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: offset and length of the partial USB 2.0 Host register block. -- clocks: clock phandle and specifier pair(s). -- #phy-cells: see phy-bindings.txt in the same directory, must be <1> (and - using <0> is deprecated). - -The phandle's argument in the PHY specifier is the INT_STATUS bit of controller: -- 1 = USBH_INTA (OHCI) -- 2 = USBH_INTB (EHCI) -- 3 = UCOM_INT (OTG and BC) - -Optional properties: -To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are -combined, the device tree node should set interrupt properties to use the -channel as USB OTG: -- interrupts: interrupt specifier for the PHY. -- vbus-supply: Phandle to a regulator that provides power to the VBUS. This - regulator will be managed during the PHY power on/off sequence. -- renesas,no-otg-pins: boolean, specify when a board does not provide proper - otg pins. -- dr_mode: string, indicates the working mode for the PHY. Can be "host", - "peripheral", or "otg". Should be set if otg controller is not used. - - -Example (R-Car H3): - - usb-phy@ee080200 { - compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee080200 0 0x700>; - interrupts = ; - clocks = <&cpg CPG_MOD 703>; - }; - - usb-phy@ee0a0200 { - compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy"; - reg = <0 0xee0a0200 0 0x700>; - clocks = <&cpg CPG_MOD 702>; - }; diff --git a/Bindings/phy/rcar-gen3-phy-usb3.txt b/Bindings/phy/rcar-gen3-phy-usb3.txt deleted file mode 100644 index 0fe433b9a592..000000000000 --- a/Bindings/phy/rcar-gen3-phy-usb3.txt +++ /dev/null @@ -1,52 +0,0 @@ -* Renesas R-Car generation 3 USB 3.0 PHY - -This file provides information on what the device node for the R-Car generation -3 and RZ/G2 USB 3.0 PHY contain. -If you want to enable spread spectrum clock (ssc), you should use USB_EXTAL -instead of USB3_CLK. However, if you don't want to these features, you don't -need this driver. - -Required properties: -- compatible: "renesas,r8a774a1-usb3-phy" if the device is a part of an R8A774A1 - SoC. - "renesas,r8a774b1-usb3-phy" if the device is a part of an R8A774B1 - SoC. - "renesas,r8a7795-usb3-phy" if the device is a part of an R8A7795 - SoC. - "renesas,r8a7796-usb3-phy" if the device is a part of an R8A7796 - SoC. - "renesas,r8a77965-usb3-phy" if the device is a part of an - R8A77965 SoC. - "renesas,rcar-gen3-usb3-phy" for a generic R-Car Gen3 or RZ/G2 - compatible device. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: offset and length of the USB 3.0 PHY register block. -- clocks: A list of phandles and clock-specifier pairs. -- clock-names: Name of the clocks. - - The funcional clock must be "usb3-if". - - The usb3's external clock must be "usb3s_clk". - - The usb2's external clock must be "usb_extal". If you want to use the ssc, - the clock-frequency must not be 0. -- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. - -Optional properties: -- renesas,ssc-range: Enable/disable spread spectrum clock (ssc) by using - the following values as u32: - - 0 (or the property doesn't exist): disable the ssc - - 4980: enable the ssc as -4980 ppm - - 4492: enable the ssc as -4492 ppm - - 4003: enable the ssc as -4003 ppm - -Example (R-Car H3): - - usb-phy@e65ee000 { - compatible = "renesas,r8a7795-usb3-phy", - "renesas,rcar-gen3-usb3-phy"; - reg = <0 0xe65ee000 0 0x90>; - clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, <&usb_extal>; - clock-names = "usb3-if", "usb3s_clk", "usb_extal"; - }; diff --git a/Bindings/phy/renesas,usb2-phy.yaml b/Bindings/phy/renesas,usb2-phy.yaml new file mode 100644 index 000000000000..440f09fddf93 --- /dev/null +++ b/Bindings/phy/renesas,usb2-phy.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car generation 3 USB 2.0 PHY + +maintainers: + - Yoshihiro Shimoda + +properties: + compatible: + oneOf: + - items: + - const: renesas,usb2-phy-r8a77470 # RZ/G1C + + - items: + - enum: + - renesas,usb2-phy-r7s9210 # RZ/A2 + - renesas,usb2-phy-r8a774a1 # RZ/G2M + - renesas,usb2-phy-r8a774b1 # RZ/G2N + - renesas,usb2-phy-r8a774c0 # RZ/G2E + - renesas,usb2-phy-r8a7795 # R-Car H3 + - renesas,usb2-phy-r8a7796 # R-Car M3-W + - renesas,usb2-phy-r8a77961 # R-Car M3-W+ + - renesas,usb2-phy-r8a77965 # R-Car M3-N + - renesas,usb2-phy-r8a77990 # R-Car E3 + - renesas,usb2-phy-r8a77995 # R-Car D3 + - const: renesas,rcar-gen3-usb2-phy + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: fck + - const: usb_x1 + + '#phy-cells': + enum: [0, 1] # and 0 is deprecated. + description: | + The phandle's argument in the PHY specifier is the INT_STATUS bit of + controller. + - 1 = USBH_INTA (OHCI) + - 2 = USBH_INTB (EHCI) + - 3 = UCOM_INT (OTG and BC) + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 2 + items: + - description: reset of USB 2.0 host side + - description: reset of USB 2.0 peripheral side + + vbus-supply: + description: | + Phandle to a regulator that provides power to the VBUS. This regulator + will be managed during the PHY power on/off sequence. + + renesas,no-otg-pins: + $ref: /schemas/types.yaml#/definitions/flag + description: | + specify when a board does not provide proper otg pins. + + dr_mode: true + +if: + properties: + compatible: + items: + enum: + - renesas,usb2-phy-r7s9210 +then: + required: + - clock-names + +required: + - compatible + - reg + - clocks + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + + usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy"; + reg = <0xee080200 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + #phy-cells = <1>; + }; + + usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy"; + reg = <0xee0a0200 0x700>; + clocks = <&cpg CPG_MOD 702>; + #phy-cells = <1>; + }; diff --git a/Bindings/phy/renesas,usb3-phy.yaml b/Bindings/phy/renesas,usb3-phy.yaml new file mode 100644 index 000000000000..68cf9dd0390d --- /dev/null +++ b/Bindings/phy/renesas,usb3-phy.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car generation 3 USB 3.0 PHY + +maintainers: + - Yoshihiro Shimoda + +properties: + compatible: + items: + - enum: + - renesas,r8a774a1-usb3-phy # RZ/G2M + - renesas,r8a774b1-usb3-phy # RZ/G2N + - renesas,r8a7795-usb3-phy # R-Car H3 + - renesas,r8a7796-usb3-phy # R-Car M3-W + - renesas,r8a77961-usb3-phy # R-Car M3-W+ + - renesas,r8a77965-usb3-phy # R-Car M3-N + - const: renesas,rcar-gen3-usb3-phy + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + # If you want to use the ssc, the clock-frequency of usb_extal + # must not be 0. + minItems: 2 + maxItems: 3 + items: + - const: usb3-if # The funcional clock + - const: usb3s_clk # The usb3's external clock + - const: usb_extal # The usb2's external clock + + '#phy-cells': + # see phy-bindings.txt in the same directory + const: 0 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + renesas,ssc-range: + description: | + Enable/disable spread spectrum clock (ssc). 0 or the property doesn't + exist means disabling the ssc. The actual value will be - ppm. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 4003, 4492, 4980 ] + +required: + - compatible + - reg + - clocks + - clock-names + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + usb-phy@e65ee000 { + compatible = "renesas,r8a7795-usb3-phy", "renesas,rcar-gen3-usb3-phy"; + reg = <0xe65ee000 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, <&usb_extal>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + #phy-cells = <0>; + }; diff --git a/Bindings/phy/rockchip,px30-dsi-dphy.yaml b/Bindings/phy/rockchip,px30-dsi-dphy.yaml index 72aca81e8959..8a3032a3bd73 100644 --- a/Bindings/phy/rockchip,px30-dsi-dphy.yaml +++ b/Bindings/phy/rockchip,px30-dsi-dphy.yaml @@ -59,7 +59,7 @@ examples: - | dsi_dphy: phy@ff2e0000 { compatible = "rockchip,px30-dsi-dphy"; - reg = <0x0 0xff2e0000 0x0 0x10000>; + reg = <0xff2e0000 0x10000>; clocks = <&pmucru 13>, <&cru 12>; clock-names = "ref", "pclk"; resets = <&cru 12>; diff --git a/Bindings/phy/rockchip-mipi-dphy-rx0.yaml b/Bindings/phy/rockchip-mipi-dphy-rx0.yaml new file mode 100644 index 000000000000..7d888d358823 --- /dev/null +++ b/Bindings/phy/rockchip-mipi-dphy-rx0.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings + +maintainers: + - Helen Koike + - Ezequiel Garcia + +description: | + The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to + the ISP1 (Image Signal Processing unit v1.0) for CSI cameras. + +properties: + compatible: + const: rockchip,rk3399-mipi-dphy-rx0 + + clocks: + items: + - description: MIPI D-PHY ref clock + - description: MIPI D-PHY RX0 cfg clock + - description: Video in/out general register file clock + + clock-names: + items: + - const: dphy-ref + - const: dphy-cfg + - const: grf + + '#phy-cells': + const: 0 + + power-domains: + description: Video in/out power domain. + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - '#phy-cells' + - power-domains + +additionalProperties: false + +examples: + - | + + /* + * MIPI D-PHY RX0 use registers in "general register files", it + * should be a child of the GRF. + * + * grf: syscon@ff770000 { + * compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; + * ... + * }; + */ + + #include + #include + + mipi_dphy_rx0: mipi-dphy-rx0 { + compatible = "rockchip,rk3399-mipi-dphy-rx0"; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_RX0_CFG>, + <&cru PCLK_VIO_GRF>; + clock-names = "dphy-ref", "dphy-cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + #phy-cells = <0>; + }; diff --git a/Bindings/phy/socionext,uniphier-pcie-phy.yaml b/Bindings/phy/socionext,uniphier-pcie-phy.yaml new file mode 100644 index 000000000000..86f49093b65f --- /dev/null +++ b/Bindings/phy/socionext,uniphier-pcie-phy.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier PCIe PHY + +description: | + This describes the devicetree bindings for PHY interface built into + PCIe controller implemented on Socionext UniPhier SoCs. + +maintainers: + - Kunihiko Hayashi + +properties: + compatible: + enum: + - socionext,uniphier-pro5-pcie-phy + - socionext,uniphier-ld20-pcie-phy + - socionext,uniphier-pxs3-pcie-phy + + reg: + description: PHY register region (offset and length) + + "#phy-cells": + const: 0 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + oneOf: + - items: # for Pro5 + - const: gio + - const: link + - const: link # for others + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + oneOf: + - items: # for Pro5 + - const: gio + - const: link + - const: link # for others + + socionext,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: A phandle to system control to set configurations for phy + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + pcie_phy: phy@66038000 { + compatible = "socionext,uniphier-ld20-pcie-phy"; + reg = <0x66038000 0x4000>; + #phy-cells = <0>; + clock-names = "link"; + clocks = <&sys_clk 24>; + reset-names = "link"; + resets = <&sys_rst 24>; + socionext,syscon = <&soc_glue>; + }; diff --git a/Bindings/phy/socionext,uniphier-usb2-phy.yaml b/Bindings/phy/socionext,uniphier-usb2-phy.yaml new file mode 100644 index 000000000000..479b203f7aa6 --- /dev/null +++ b/Bindings/phy/socionext,uniphier-usb2-phy.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier USB2 PHY + +description: | + This describes the devicetree bindings for PHY interface built into + USB2 controller implemented on Socionext UniPhier SoCs. + Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3 + controller doesn't include its own High-Speed PHY. This needs to specify + USB2 PHY instead of USB3 HS-PHY. + +maintainers: + - Kunihiko Hayashi + +properties: + compatible: + enum: + - socionext,uniphier-pro4-usb2-phy + - socionext,uniphier-ld11-usb2-phy + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^phy@[0-9]+$": + type: object + additionalProperties: false + + properties: + reg: + minimum: 0 + maximum: 3 + description: + The ID number for the PHY + + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + +required: + - compatible + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + // The UniPhier usb2-phy should be a subnode of a "syscon" compatible node. + + soc-glue@5f800000 { + compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + usb-controller { + compatible = "socionext,uniphier-ld11-usb2-phy"; + #address-cells = <1>; + #size-cells = <0>; + + usb_phy0: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + usb_phy1: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + usb_phy2: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + }; + }; diff --git a/Bindings/phy/socionext,uniphier-usb3hs-phy.yaml b/Bindings/phy/socionext,uniphier-usb3hs-phy.yaml new file mode 100644 index 000000000000..f88d36207b87 --- /dev/null +++ b/Bindings/phy/socionext,uniphier-usb3hs-phy.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier USB3 High-Speed (HS) PHY + +description: | + This describes the devicetree bindings for PHY interfaces built into + USB3 controller implemented on Socionext UniPhier SoCs. + Although the controller includes High-Speed PHY and Super-Speed PHY, + this describes about High-Speed PHY. + +maintainers: + - Kunihiko Hayashi + +properties: + compatible: + enum: + - socionext,uniphier-pro5-usb3-hsphy + - socionext,uniphier-pxs2-usb3-hsphy + - socionext,uniphier-ld20-usb3-hsphy + - socionext,uniphier-pxs3-usb3-hsphy + + reg: + description: PHY register region (offset and length) + + "#phy-cells": + const: 0 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + oneOf: + - const: link # for PXs2 + - items: # for PXs3 + - const: link + - const: phy + + resets: + maxItems: 2 + + reset-names: + items: + - const: link + - const: phy + + vbus-supply: + description: A phandle to the regulator for USB VBUS + + nvmem-cells: + maxItems: 3 + description: + Phandles to nvmem cell that contains the trimming data. + Available only for HS-PHY implemented on LD20 and PXs3, and + if unspecified, default value is used. + + nvmem-cell-names: + items: + - const: rterm + - const: sel_t + - const: hs_i + description: + Should be the following names, which correspond to each nvmem-cells. + All of the 3 parameters associated with the above names are + required for each port, if any one is omitted, the trimming data + of the port will not be set at all. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + usb-glue@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>; + }; + }; diff --git a/Bindings/phy/socionext,uniphier-usb3ss-phy.yaml b/Bindings/phy/socionext,uniphier-usb3ss-phy.yaml new file mode 100644 index 000000000000..edff2c95c9ae --- /dev/null +++ b/Bindings/phy/socionext,uniphier-usb3ss-phy.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier USB3 Super-Speed (SS) PHY + +description: | + This describes the devicetree bindings for PHY interfaces built into + USB3 controller implemented on Socionext UniPhier SoCs. + Although the controller includes High-Speed PHY and Super-Speed PHY, + this describes about Super-Speed PHY. + +maintainers: + - Kunihiko Hayashi + +properties: + compatible: + enum: + - socionext,uniphier-pro4-usb3-ssphy + - socionext,uniphier-pro5-usb3-ssphy + - socionext,uniphier-pxs2-usb3-ssphy + - socionext,uniphier-ld20-usb3-ssphy + - socionext,uniphier-pxs3-usb3-ssphy + + reg: + description: PHY register region (offset and length) + + "#phy-cells": + const: 0 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + oneOf: + - items: # for Pro4, Pro5 + - const: gio + - const: link + - items: # for PXs3 with phy-ext + - const: link + - const: phy + - const: phy-ext + - items: # for others + - const: link + - const: phy + + resets: + maxItems: 2 + + reset-names: + oneOf: + - items: # for Pro4,Pro5 + - const: gio + - const: link + - items: # for others + - const: link + - const: phy + + vbus-supply: + description: A phandle to the regulator for USB VBUS + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + - vbus-supply + +additionalProperties: false + +examples: + - | + usb-glue@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-ld20-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb_vbus0>; + }; + }; diff --git a/Bindings/phy/uniphier-pcie-phy.txt b/Bindings/phy/uniphier-pcie-phy.txt deleted file mode 100644 index 3cee372c5742..000000000000 --- a/Bindings/phy/uniphier-pcie-phy.txt +++ /dev/null @@ -1,36 +0,0 @@ -Socionext UniPhier PCIe PHY bindings - -This describes the devicetree bindings for PHY interface built into -PCIe controller implemented on Socionext UniPhier SoCs. - -Required properties: -- compatible: Should contain one of the following: - "socionext,uniphier-pro5-pcie-phy" - for Pro5 PHY - "socionext,uniphier-ld20-pcie-phy" - for LD20 PHY - "socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY -- reg: Specifies offset and length of the register set for the device. -- #phy-cells: Must be zero. -- clocks: A list of phandles to the clock gate for PCIe glue layer - including this phy. -- clock-names: For Pro5 only, should contain the following: - "gio", "link" - for Pro5 SoC -- resets: A list of phandles to the reset line for PCIe glue layer - including this phy. -- reset-names: For Pro5 only, should contain the following: - "gio", "link" - for Pro5 SoC - -Optional properties: -- socionext,syscon: A phandle to system control to set configurations - for phy. - -Refer to phy/phy-bindings.txt for the generic PHY binding properties. - -Example: - pcie_phy: phy@66038000 { - compatible = "socionext,uniphier-ld20-pcie-phy"; - reg = <0x66038000 0x4000>; - #phy-cells = <0>; - clocks = <&sys_clk 24>; - resets = <&sys_rst 24>; - socionext,syscon = <&soc_glue>; - }; diff --git a/Bindings/phy/uniphier-usb2-phy.txt b/Bindings/phy/uniphier-usb2-phy.txt deleted file mode 100644 index b43b28250cc0..000000000000 --- a/Bindings/phy/uniphier-usb2-phy.txt +++ /dev/null @@ -1,45 +0,0 @@ -Socionext UniPhier USB2 PHY - -This describes the devicetree bindings for PHY interface built into -USB2 controller implemented on Socionext UniPhier SoCs. - -Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3 -controller doesn't include its own High-Speed PHY. This needs to specify -USB2 PHY instead of USB3 HS-PHY. - -Required properties: -- compatible: Should contain one of the following: - "socionext,uniphier-pro4-usb2-phy" - for Pro4 SoC - "socionext,uniphier-ld11-usb2-phy" - for LD11 SoC - -Sub-nodes: -Each PHY should be represented as a sub-node. - -Sub-nodes required properties: -- #phy-cells: Should be 0. -- reg: The number of the PHY. - -Sub-nodes optional properties: -- vbus-supply: A phandle to the regulator for USB VBUS. - -Refer to phy/phy-bindings.txt for the generic PHY binding properties. - -Example: - soc-glue@5f800000 { - ... - usb-phy { - compatible = "socionext,uniphier-ld11-usb2-phy"; - usb_phy0: phy@0 { - reg = <0>; - #phy-cells = <0>; - }; - ... - }; - }; - - usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - ... - phy-names = "usb"; - phys = <&usb_phy0>; - }; diff --git a/Bindings/phy/uniphier-usb3-hsphy.txt b/Bindings/phy/uniphier-usb3-hsphy.txt deleted file mode 100644 index 093d4f08705f..000000000000 --- a/Bindings/phy/uniphier-usb3-hsphy.txt +++ /dev/null @@ -1,69 +0,0 @@ -Socionext UniPhier USB3 High-Speed (HS) PHY - -This describes the devicetree bindings for PHY interfaces built into -USB3 controller implemented on Socionext UniPhier SoCs. -Although the controller includes High-Speed PHY and Super-Speed PHY, -this describes about High-Speed PHY. - -Required properties: -- compatible: Should contain one of the following: - "socionext,uniphier-pro5-usb3-hsphy" - for Pro5 SoC - "socionext,uniphier-pxs2-usb3-hsphy" - for PXs2 SoC - "socionext,uniphier-ld20-usb3-hsphy" - for LD20 SoC - "socionext,uniphier-pxs3-usb3-hsphy" - for PXs3 SoC -- reg: Specifies offset and length of the register set for the device. -- #phy-cells: Should be 0. -- clocks: A list of phandles to the clock gate for USB3 glue layer. - According to the clock-names, appropriate clocks are required. -- clock-names: Should contain the following: - "gio", "link" - for Pro5 SoC - "phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional. - "phy", "link" - for others -- resets: A list of phandles to the reset control for USB3 glue layer. - According to the reset-names, appropriate resets are required. -- reset-names: Should contain the following: - "gio", "link" - for Pro5 SoC - "phy", "link" - for others - -Optional properties: -- vbus-supply: A phandle to the regulator for USB VBUS. -- nvmem-cells: Phandles to nvmem cell that contains the trimming data. - Available only for HS-PHY implemented on LD20 and PXs3, and - if unspecified, default value is used. -- nvmem-cell-names: Should be the following names, which correspond to - each nvmem-cells. - All of the 3 parameters associated with the following names are - required for each port, if any one is omitted, the trimming data - of the port will not be set at all. - "rterm", "sel_t", "hs_i" - Each cell name for phy parameters - -Refer to phy/phy-bindings.txt for the generic PHY binding properties. - -Example: - - usb-glue@65b00000 { - compatible = "socionext,uniphier-ld20-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb_vbus0: regulator { - ... - }; - - usb_hsphy0: hs-phy@200 { - compatible = "socionext,uniphier-ld20-usb3-hsphy"; - reg = <0x200 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 16>; - vbus-supply = <&usb_vbus0>; - nvmem-cell-names = "rterm", "sel_t", "hs_i"; - nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, - <&usb_hs_i0>; - }; - ... - }; diff --git a/Bindings/phy/uniphier-usb3-ssphy.txt b/Bindings/phy/uniphier-usb3-ssphy.txt deleted file mode 100644 index 9df2bc2f5999..000000000000 --- a/Bindings/phy/uniphier-usb3-ssphy.txt +++ /dev/null @@ -1,58 +0,0 @@ -Socionext UniPhier USB3 Super-Speed (SS) PHY - -This describes the devicetree bindings for PHY interfaces built into -USB3 controller implemented on Socionext UniPhier SoCs. -Although the controller includes High-Speed PHY and Super-Speed PHY, -this describes about Super-Speed PHY. - -Required properties: -- compatible: Should contain one of the following: - "socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC - "socionext,uniphier-pro5-usb3-ssphy" - for Pro5 SoC - "socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC - "socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC - "socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC -- reg: Specifies offset and length of the register set for the device. -- #phy-cells: Should be 0. -- clocks: A list of phandles to the clock gate for USB3 glue layer. - According to the clock-names, appropriate clocks are required. -- clock-names: - "gio", "link" - for Pro4 and Pro5 SoC - "phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional. - "phy", "link" - for others -- resets: A list of phandles to the reset control for USB3 glue layer. - According to the reset-names, appropriate resets are required. -- reset-names: - "gio", "link" - for Pro4 and Pro5 SoC - "phy", "link" - for others - -Optional properties: -- vbus-supply: A phandle to the regulator for USB VBUS. - -Refer to phy/phy-bindings.txt for the generic PHY binding properties. - -Example: - - usb-glue@65b00000 { - compatible = "socionext,uniphier-ld20-dwc3-glue", - "simple-mfd"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x65b00000 0x400>; - - usb_vbus0: regulator { - ... - }; - - usb_ssphy0: ss-phy@300 { - compatible = "socionext,uniphier-ld20-usb3-ssphy"; - reg = <0x300 0x10>; - #phy-cells = <0>; - clock-names = "link", "phy"; - clocks = <&sys_clk 14>, <&sys_clk 16>; - reset-names = "link", "phy"; - resets = <&sys_rst 14>, <&sys_rst 16>; - vbus-supply = <&usb_vbus0>; - }; - ... - }; diff --git a/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index bfefd09d8c1e..7556be6e2754 100644 --- a/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -84,13 +84,12 @@ properties: gpio-line-names: true input-debounce: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 1 - maxItems: 5 description: Debouncing periods in microseconds, one period per interrupt bank found in the controller + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 5 patternProperties: # It's pretty scary, but the basic idea is that: @@ -115,9 +114,8 @@ patternProperties: bias-pull-down: true drive-strength: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 10, 20, 30, 40 ] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [10, 20, 30, 40] required: - pins diff --git a/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml b/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml index 7651a675ab2d..017d9593573b 100644 --- a/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml +++ b/Bindings/pinctrl/aspeed,ast2400-pinctrl.yaml @@ -33,26 +33,23 @@ patternProperties: then: patternProperties: "^function|groups$": - allOf: - - $ref: "/schemas/types.yaml#/definitions/string" - - enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, - ADC15, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, - DDCCLK, DDCDAT, EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, - GPID4, GPID6, GPIE0, GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, - I2C13, I2C14, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, - LPCPME, LPCRST, LPCSMI, MAC1LINK, MAC2LINK, MDIO1, MDIO2, NCTS1, - NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, - NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NDTS4, NRI1, NRI2, - NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0, PWM1, PWM2, PWM3, - PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, RMII2, ROM16, - ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3, RXD4, - SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD, - SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO, - SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, - SPI1PASSTHRU, SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, - TIMER8, TXD1, TXD2, TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, - USB2H1, USBCKI, VGABIOS_ROM, VGAHS, VGAVS, VPI18, VPI24, VPI30, - VPO12, VPO24, WDTRST1, WDTRST2 ] + $ref: "/schemas/types.yaml#/definitions/string" + enum: [ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, + ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT, + EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0, + GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, + I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK, + MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, + NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, + NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0, + PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, + RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3, + RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD, + SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO, + SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU, + SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, + TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM, + VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2] required: - compatible diff --git a/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml index 36feaf5e2dff..c643d6d44415 100644 --- a/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml +++ b/Bindings/pinctrl/aspeed,ast2500-pinctrl.yaml @@ -29,8 +29,7 @@ properties: aspeed,external-nodes: minItems: 2 maxItems: 2 - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle-array + $ref: /schemas/types.yaml#/definitions/phandle-array description: | A cell of phandles to external controller nodes: 0: compatible with "aspeed,ast2500-gfx", "syscon" @@ -43,28 +42,25 @@ patternProperties: then: patternProperties: "^function|groups$": - allOf: - - $ref: "/schemas/types.yaml#/definitions/string" - - enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, - ADC15, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, - DDCCLK, DDCDAT, ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, - GPID6, GPIE0, GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, - I2C14, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, - LAD2, LAD3, LCLK, LFRAME, LPCHC, LPCPD, LPCPLUS, LPCPME, LPCRST, - LPCSMI, LSIRQ, MAC1LINK, MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, - NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, - NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, - NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0, PWM1, PWM2, - PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, RMII2, RXD1, - RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14, - SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1, - SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, - SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, - SPI1DEBUG, SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, - SPI2MOSI, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, - TXD2, TXD3, TXD4, UART6, USB11BHID, USB2AD, USB2AH, USB2BD, - USB2BH, USBCKI, VGABIOSROM, VGAHS, VGAVS, VPI24, VPO, WDTRST1, - WDTRST2, ] + $ref: "/schemas/types.yaml#/definitions/string" + enum: [ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, + ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT, + ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2, + GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5, + I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, LAD2, LAD3, LCLK, LFRAME, LPCHC, + LPCPD, LPCPLUS, LPCPME, LPCRST, LPCSMI, LSIRQ, MAC1LINK, MAC2LINK, + MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, + NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, + NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0, + PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, + RMII2, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, + SALT14, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1, + SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO, + SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, SPI1DEBUG, + SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, SPI2MOSI, TIMER3, + TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, TXD3, TXD4, UART6, + USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS, + VGAVS, VPI24, VPO, WDTRST1, WDTRST2] required: - compatible @@ -125,7 +121,7 @@ examples: lhc: lhc@20 { compatible = "aspeed,ast2500-lhc"; - reg = <0x20 0x24 0x48 0x8>; + reg = <0x20 0x24>, <0x48 0x8>; }; }; }; diff --git a/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml index 45af29bc3202..1506726c7fea 100644 --- a/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -30,64 +30,58 @@ patternProperties: then: properties: function: - allOf: - - $ref: "/schemas/types.yaml#/definitions/string" - - enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, - ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, - ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, - GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, - GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11, - I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, - I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, - LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, - MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, - NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, - NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, - NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11, - PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, - PWM8, PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, - RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, - SALT13, SALT14, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, - SALT6, SALT7, SALT8, SALT9, SD1, SD2, SGPM1, SGPS1, SIOONCTRL, - SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, - SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, - TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, - TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, - THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13, - UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP, - USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, - WDTRST4, ] + $ref: "/schemas/types.yaml#/definitions/string" + enum: [ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2, + ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT, + FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3, + GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5, + GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, + I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, + I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, + MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, + NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, + NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, + NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11, + PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8, + PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4, + RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14, + SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, + SALT9, SD1, SD2, SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, + SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2, + SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14, + TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, + THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, + UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP, + USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4] + groups: - allOf: - - $ref: "/schemas/types.yaml#/definitions/string" - - enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, - ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, - EMMCG4, EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, - FWQSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, - GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, - GPIU7, HVI3C3, HVI3C4, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, - I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, - I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, - LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3, MACLINK4, - MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, - NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, - NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, - OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, - PWM12G0, PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, - PWM15G1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, - PWM9G0, PWM9G1, QSPI1, QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, - RMII1, RMII2, RMII3, RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, - SALT10G0, SALT10G1, SALT11G0, SALT11G1, SALT12G0, SALT12G1, - SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, SALT15G1, - SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, - SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPS1, SIOONCTRL, - SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, - SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, - TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, - TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, - THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0, - UART12G1, UART13G0, UART13G1, UART6, UART7, UART8, UART9, USBA, - USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4, ] + $ref: "/schemas/types.yaml#/definitions/string" + enum: [ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2, + ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4, + EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWQSPID, FWSPIWP, + GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, + GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10, + I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, + I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, + LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3, + MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, + NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, + NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, + OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0, + PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2, + PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1, + QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4, + RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1, + SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, + SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, + SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPS1, SIOONCTRL, + SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, + SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, + TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, + TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, + TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6, + UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, + WDTRST3, WDTRST4] required: - compatible diff --git a/Bindings/pinctrl/brcm,bcm2835-gpio.txt b/Bindings/pinctrl/brcm,bcm2835-gpio.txt index 3cab7336a326..5682b2010e50 100644 --- a/Bindings/pinctrl/brcm,bcm2835-gpio.txt +++ b/Bindings/pinctrl/brcm,bcm2835-gpio.txt @@ -9,13 +9,16 @@ Required properties: "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl + "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl - reg: Should contain the physical address of the GPIO module's registers. - gpio-controller: Marks the device node as a GPIO controller. - #gpio-cells : Should be two. The first cell is the pin number and the second cell is used to specify optional parameters: - bit 0 specifies polarity (0 for normal, 1 for inverted) - interrupts : The interrupt outputs from the controller. One interrupt per - individual bank followed by the "all banks" interrupt. + individual bank followed by the "all banks" interrupt. For BCM7211, an + additional set of per-bank interrupt line and an "all banks" wake-up + interrupt may be specified. - interrupt-controller: Marks the device node as an interrupt controller. - #interrupt-cells : Should be 2. The first cell is the GPIO number. diff --git a/Bindings/pinctrl/cirrus,lochnagar.txt b/Bindings/pinctrl/cirrus,lochnagar.txt deleted file mode 100644 index a87447180e83..000000000000 --- a/Bindings/pinctrl/cirrus,lochnagar.txt +++ /dev/null @@ -1,141 +0,0 @@ -Cirrus Logic Lochnagar Audio Development Board - -Lochnagar is an evaluation and development board for Cirrus Logic -Smart CODEC and Amp devices. It allows the connection of most Cirrus -Logic devices on mini-cards, as well as allowing connection of -various application processor systems to provide a full evaluation -platform. Audio system topology, clocking and power can all be -controlled through the Lochnagar, allowing the device under test -to be used in a variety of possible use cases. - -This binding document describes the binding for the pinctrl portion -of the driver. - -Also see these documents for generic binding information: - [1] GPIO : ../gpio/gpio.txt - [2] Pinctrl: ../pinctrl/pinctrl-bindings.txt - -And these for relevant defines: - [3] include/dt-bindings/pinctrl/lochnagar.h - -This binding must be part of the Lochnagar MFD binding: - [4] ../mfd/cirrus,lochnagar.txt - -Required properties: - - - compatible : One of the following strings: - "cirrus,lochnagar-pinctrl" - - - gpio-controller : Indicates this device is a GPIO controller. - - #gpio-cells : Must be 2. The first cell is the pin number, see - [3] for available pins and the second cell is used to specify - optional parameters, see [1]. - - gpio-ranges : Range of pins managed by the GPIO controller, see - [1]. Both the GPIO and Pinctrl base should be set to zero and the - count to the appropriate of the LOCHNAGARx_PIN_NUM_GPIOS define, - see [3]. - - - pinctrl-names : A pinctrl state named "default" must be defined. - - pinctrl-0 : A phandle to the default pinctrl state. - -Required sub-nodes: - -The pin configurations are defined as a child of the pinctrl states -node, see [2]. Each sub-node can have the following properties: - - groups : A list of groups to select (either this or "pins" must be - specified), available groups: - codec-aif1, codec-aif2, codec-aif3, dsp-aif1, dsp-aif2, psia1, - psia2, gf-aif1, gf-aif2, gf-aif3, gf-aif4, spdif-aif, usb-aif1, - usb-aif2, adat-aif, soundcard-aif - - pins : A list of pin names to select (either this or "groups" must - be specified), available pins: - fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4, fpga-gpio5, - fpga-gpio6, codec-gpio1, codec-gpio2, codec-gpio3, codec-gpio4, - codec-gpio5, codec-gpio6, codec-gpio7, codec-gpio8, dsp-gpio1, - dsp-gpio2, dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6, gf-gpio2, - gf-gpio3, gf-gpio7, codec-aif1-bclk, codec-aif1-rxdat, - codec-aif1-lrclk, codec-aif1-txdat, codec-aif2-bclk, - codec-aif2-rxdat, codec-aif2-lrclk, codec-aif2-txdat, - codec-aif3-bclk, codec-aif3-rxdat, codec-aif3-lrclk, - codec-aif3-txdat, dsp-aif1-bclk, dsp-aif1-rxdat, dsp-aif1-lrclk, - dsp-aif1-txdat, dsp-aif2-bclk, dsp-aif2-rxdat, - dsp-aif2-lrclk, dsp-aif2-txdat, psia1-bclk, psia1-rxdat, - psia1-lrclk, psia1-txdat, psia2-bclk, psia2-rxdat, psia2-lrclk, - psia2-txdat, gf-aif3-bclk, gf-aif3-rxdat, gf-aif3-lrclk, - gf-aif3-txdat, gf-aif4-bclk, gf-aif4-rxdat, gf-aif4-lrclk, - gf-aif4-txdat, gf-aif1-bclk, gf-aif1-rxdat, gf-aif1-lrclk, - gf-aif1-txdat, gf-aif2-bclk, gf-aif2-rxdat, gf-aif2-lrclk, - gf-aif2-txdat, dsp-uart1-rx, dsp-uart1-tx, dsp-uart2-rx, - dsp-uart2-tx, gf-uart2-rx, gf-uart2-tx, usb-uart-rx, - codec-pdmclk1, codec-pdmdat1, codec-pdmclk2, codec-pdmdat2, - codec-dmicclk1, codec-dmicdat1, codec-dmicclk2, codec-dmicdat2, - codec-dmicclk3, codec-dmicdat3, codec-dmicclk4, codec-dmicdat4, - dsp-dmicclk1, dsp-dmicdat1, dsp-dmicclk2, dsp-dmicdat2, i2c2-scl, - i2c2-sda, i2c3-scl, i2c3-sda, i2c4-scl, i2c4-sda, dsp-standby, - codec-mclk1, codec-mclk2, dsp-clkin, psia1-mclk, psia2-mclk, - gf-gpio1, gf-gpio5, dsp-gpio20, led1, led2 - - function : The mux function to select, available functions: - aif, fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4, fpga-gpio5, - fpga-gpio6, codec-gpio1, codec-gpio2, codec-gpio3, codec-gpio4, - codec-gpio5, codec-gpio6, codec-gpio7, codec-gpio8, dsp-gpio1, - dsp-gpio2, dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6, gf-gpio2, - gf-gpio3, gf-gpio7, gf-gpio1, gf-gpio5, dsp-gpio20, codec-clkout, - dsp-clkout, pmic-32k, spdif-clkout, clk-12m288, clk-11m2986, - clk-24m576, clk-22m5792, xmos-mclk, gf-clkout1, gf-mclk1, - gf-mclk3, gf-mclk2, gf-clkout2, codec-mclk1, codec-mclk2, - dsp-clkin, psia1-mclk, psia2-mclk, spdif-mclk, codec-irq, - codec-reset, dsp-reset, dsp-irq, dsp-standby, codec-pdmclk1, - codec-pdmdat1, codec-pdmclk2, codec-pdmdat2, codec-dmicclk1, - codec-dmicdat1, codec-dmicclk2, codec-dmicdat2, codec-dmicclk3, - codec-dmicdat3, codec-dmicclk4, codec-dmicdat4, dsp-dmicclk1, - dsp-dmicdat1, dsp-dmicclk2, dsp-dmicdat2, dsp-uart1-rx, - dsp-uart1-tx, dsp-uart2-rx, dsp-uart2-tx, gf-uart2-rx, - gf-uart2-tx, usb-uart-rx, usb-uart-tx, i2c2-scl, i2c2-sda, - i2c3-scl, i2c3-sda, i2c4-scl, i2c4-sda, spdif-aif, psia1, - psia1-bclk, psia1-lrclk, psia1-rxdat, psia1-txdat, psia2, - psia2-bclk, psia2-lrclk, psia2-rxdat, psia2-txdat, codec-aif1, - codec-aif1-bclk, codec-aif1-lrclk, codec-aif1-rxdat, - codec-aif1-txdat, codec-aif2, codec-aif2-bclk, codec-aif2-lrclk, - codec-aif2-rxdat, codec-aif2-txdat, codec-aif3, codec-aif3-bclk, - codec-aif3-lrclk, codec-aif3-rxdat, codec-aif3-txdat, dsp-aif1, - dsp-aif1-bclk, dsp-aif1-lrclk, dsp-aif1-rxdat, dsp-aif1-txdat, - dsp-aif2, dsp-aif2-bclk, dsp-aif2-lrclk, dsp-aif2-rxdat, - dsp-aif2-txdat, gf-aif3, gf-aif3-bclk, gf-aif3-lrclk, - gf-aif3-rxdat, gf-aif3-txdat, gf-aif4, gf-aif4-bclk, - gf-aif4-lrclk, gf-aif4-rxdat, gf-aif4-txdat, gf-aif1, - gf-aif1-bclk, gf-aif1-lrclk, gf-aif1-rxdat, gf-aif1-txdat, - gf-aif2, gf-aif2-bclk, gf-aif2-lrclk, gf-aif2-rxdat, - gf-aif2-txdat, usb-aif1, usb-aif2, adat-aif, soundcard-aif, - - - output-enable : Specifies that an AIF group will be used as a master - interface (either this or input-enable is required if a group is - being muxed to an AIF) - - input-enable : Specifies that an AIF group will be used as a slave - interface (either this or output-enable is required if a group is - being muxed to an AIF) - -Example: - -lochnagar-pinctrl { - compatible = "cirrus,lochnagar-pinctrl"; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&lochnagar 0 0 LOCHNAGAR2_PIN_NUM_GPIOS>; - - pinctrl-names = "default"; - pinctrl-0 = <&pin-settings>; - - pin-settings: pin-settings { - ap-aif { - input-enable; - groups = "gf-aif1"; - function = "codec-aif3"; - }; - codec-aif { - output-enable; - groups = "codec-aif3"; - function = "gf-aif1"; - }; - }; -}; diff --git a/Bindings/pinctrl/cirrus,lochnagar.yaml b/Bindings/pinctrl/cirrus,lochnagar.yaml new file mode 100644 index 000000000000..420d74856032 --- /dev/null +++ b/Bindings/pinctrl/cirrus,lochnagar.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cirrus,lochnagar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic Lochnagar Audio Development Board + +maintainers: + - patches@opensource.cirrus.com + +description: | + Lochnagar is an evaluation and development board for Cirrus Logic + Smart CODEC and Amp devices. It allows the connection of most Cirrus + Logic devices on mini-cards, as well as allowing connection of various + application processor systems to provide a full evaluation platform. + Audio system topology, clocking and power can all be controlled through + the Lochnagar, allowing the device under test to be used in a variety of + possible use cases. + + This binding document describes the binding for the pinctrl portion of + the driver. + + Also see these documents for generic binding information: + [1] GPIO : ../gpio/gpio.txt + [2] Pinctrl: ../pinctrl/pinctrl-bindings.txt + + And these for relevant defines: + [3] include/dt-bindings/pinctrl/lochnagar.h + + This binding must be part of the Lochnagar MFD binding: + [4] ../mfd/cirrus,lochnagar.yaml + +properties: + compatible: + enum: + - cirrus,lochnagar-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: + The first cell is the pin number and the second cell is used + to specify optional parameters. + const: 2 + + gpio-ranges: + description: + Range of pins managed by the GPIO controller, see [1]. Both the + GPIO and Pinctrl base should be set to zero and the count to the + appropriate of the LOCHNAGARx_PIN_NUM_GPIOS define, see [3]. + maxItems: 1 + + pinctrl-0: + description: + A phandle to the default pinctrl state. + + pinctrl-names: + description: + A pinctrl state named "default" must be defined. + const: default + + pin-settings: + type: object + patternProperties: + '-pins$': + description: + The pin configurations are defined as a child of the pinctrl + states node, see [2]. Each sub-node can have the following + properties. + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + groups: + description: + A list of groups to select (either this or "pins" must be + specified), available groups. + enum: [ codec-aif1, codec-aif2, codec-aif3, dsp-aif1, + dsp-aif2, psia1, psia2, gf-aif1, gf-aif2, gf-aif3, + gf-aif4, spdif-aif, usb-aif1, usb-aif2, adat-aif, + soundcard-aif ] + + pins: + description: + A list of pin names to select (either this or "groups" must + be specified), available pins. + enum: [ fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4, + fpga-gpio5, fpga-gpio6, codec-gpio1, codec-gpio2, + codec-gpio3, codec-gpio4, codec-gpio5, codec-gpio6, + codec-gpio7, codec-gpio8, dsp-gpio1, dsp-gpio2, + dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6, + gf-gpio2, gf-gpio3, gf-gpio7, codec-aif1-bclk, + codec-aif1-rxdat, codec-aif1-lrclk, codec-aif1-txdat, + codec-aif2-bclk, codec-aif2-rxdat, codec-aif2-lrclk, + codec-aif2-txdat, codec-aif3-bclk, codec-aif3-rxdat, + codec-aif3-lrclk, codec-aif3-txdat, dsp-aif1-bclk, + dsp-aif1-rxdat, dsp-aif1-lrclk, dsp-aif1-txdat, + dsp-aif2-bclk, dsp-aif2-rxdat, dsp-aif2-lrclk, + dsp-aif2-txdat, psia1-bclk, psia1-rxdat, psia1-lrclk, + psia1-txdat, psia2-bclk, psia2-rxdat, psia2-lrclk, + psia2-txdat, gf-aif3-bclk, gf-aif3-rxdat, + gf-aif3-lrclk, gf-aif3-txdat, gf-aif4-bclk, + gf-aif4-rxdat, gf-aif4-lrclk, gf-aif4-txdat, + gf-aif1-bclk, gf-aif1-rxdat, gf-aif1-lrclk, + gf-aif1-txdat, gf-aif2-bclk, gf-aif2-rxdat, + gf-aif2-lrclk, gf-aif2-txdat, dsp-uart1-rx, + dsp-uart1-tx, dsp-uart2-rx, dsp-uart2-tx, + gf-uart2-rx, gf-uart2-tx, usb-uart-rx, codec-pdmclk1, + codec-pdmdat1, codec-pdmclk2, codec-pdmdat2, + codec-dmicclk1, codec-dmicdat1, codec-dmicclk2, + codec-dmicdat2, codec-dmicclk3, codec-dmicdat3, + codec-dmicclk4, codec-dmicdat4, dsp-dmicclk1, + dsp-dmicdat1, dsp-dmicclk2, dsp-dmicdat2, i2c2-scl, + i2c2-sda, i2c3-scl, i2c3-sda, i2c4-scl, i2c4-sda, + dsp-standby, codec-mclk1, codec-mclk2, dsp-clkin, + psia1-mclk, psia2-mclk, gf-gpio1, gf-gpio5, + dsp-gpio20, led1, led2 ] + + function: + description: + The mux function to select, available functions. + enum: [ aif, fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4, + fpga-gpio5, fpga-gpio6, codec-gpio1, codec-gpio2, + codec-gpio3, codec-gpio4, codec-gpio5, codec-gpio6, + codec-gpio7, codec-gpio8, dsp-gpio1, dsp-gpio2, + dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6, + gf-gpio2, gf-gpio3, gf-gpio7, gf-gpio1, gf-gpio5, + dsp-gpio20, codec-clkout, dsp-clkout, pmic-32k, + spdif-clkout, clk-12m288, clk-11m2986, clk-24m576, + clk-22m5792, xmos-mclk, gf-clkout1, gf-mclk1, + gf-mclk3, gf-mclk2, gf-clkout2, codec-mclk1, + codec-mclk2, dsp-clkin, psia1-mclk, psia2-mclk, + spdif-mclk, codec-irq, codec-reset, dsp-reset, + dsp-irq, dsp-standby, codec-pdmclk1, codec-pdmdat1, + codec-pdmclk2, codec-pdmdat2, codec-dmicclk1, + codec-dmicdat1, codec-dmicclk2, codec-dmicdat2, + codec-dmicclk3, codec-dmicdat3, codec-dmicclk4, + codec-dmicdat4, dsp-dmicclk1, dsp-dmicdat1, + dsp-dmicclk2, dsp-dmicdat2, dsp-uart1-rx, + dsp-uart1-tx, dsp-uart2-rx, dsp-uart2-tx, + gf-uart2-rx, gf-uart2-tx, usb-uart-rx, usb-uart-tx, + i2c2-scl, i2c2-sda, i2c3-scl, i2c3-sda, i2c4-scl, + i2c4-sda, spdif-aif, psia1, psia1-bclk, psia1-lrclk, + psia1-rxdat, psia1-txdat, psia2, psia2-bclk, + psia2-lrclk, psia2-rxdat, psia2-txdat, codec-aif1, + codec-aif1-bclk, codec-aif1-lrclk, codec-aif1-rxdat, + codec-aif1-txdat, codec-aif2, codec-aif2-bclk, + codec-aif2-lrclk, codec-aif2-rxdat, codec-aif2-txdat, + codec-aif3, codec-aif3-bclk, codec-aif3-lrclk, + codec-aif3-rxdat, codec-aif3-txdat, dsp-aif1, + dsp-aif1-bclk, dsp-aif1-lrclk, dsp-aif1-rxdat, + dsp-aif1-txdat, dsp-aif2, dsp-aif2-bclk, + dsp-aif2-lrclk, dsp-aif2-rxdat, dsp-aif2-txdat, + gf-aif3, gf-aif3-bclk, gf-aif3-lrclk, gf-aif3-rxdat, + gf-aif3-txdat, gf-aif4, gf-aif4-bclk, gf-aif4-lrclk, + gf-aif4-rxdat, gf-aif4-txdat, gf-aif1, gf-aif1-bclk, + gf-aif1-lrclk, gf-aif1-rxdat, gf-aif1-txdat, gf-aif2, + gf-aif2-bclk, gf-aif2-lrclk, gf-aif2-rxdat, + gf-aif2-txdat, usb-aif1, usb-aif2, adat-aif, + soundcard-aif ] + + output-enable: + description: + Specifies that an AIF group will be used as a master + interface (either this or input-enable is required if a + group is being muxed to an AIF) + + input-enable: + description: + Specifies that an AIF group will be used as a slave + interface (either this or output-enable is required if a + group is being muxed to an AIF) + + additionalProperties: false + + required: + - function + + additionalProperties: false + +required: + - compatible + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - pinctrl-0 + - pinctrl-names diff --git a/Bindings/pinctrl/cirrus,madera-pinctrl.txt b/Bindings/pinctrl/cirrus,madera-pinctrl.txt deleted file mode 100644 index b0e36cf0d289..000000000000 --- a/Bindings/pinctrl/cirrus,madera-pinctrl.txt +++ /dev/null @@ -1,99 +0,0 @@ -Cirrus Logic Madera class audio codecs pinctrl driver - -The Cirrus Logic Madera codecs provide a number of GPIO functions for -interfacing to external hardware and to provide logic outputs to other devices. -Certain groups of GPIO pins also have an alternate function, normally as an -audio interface. - -The set of available GPIOs, functions and alternate function groups differs -between codecs so refer to the datasheet for the codec for further information -on what is supported on that device. - -The properties for this driver exist within the parent MFD driver node. - -See also - the core bindings for the parent MFD driver: - Documentation/devicetree/bindings/mfd/madera.txt - - the generic pinmix bindings: - Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Required properties of parent mfd node: - - pinctrl-names : must be "default" - - pinctrl-0 : a phandle to the node containing the subnodes containing default - configurations - -Required subnodes: - One subnode is required to contain the default settings. It contains an - arbitrary number of configuration subnodes, one for each group or pin - configuration you want to apply as a default. - -Required properties of configuration subnodes: - - groups : name of one pin group to configure. One of: - aif1, aif2, aif3, aif4, mif1, mif2, mif3, pdmspk1, pdmspk2, - dmic4, dmic5, dmic6, - gpio1, gpio2, ..., gpio40 - The gpioN groups select the single pin of this name for configuration - -Optional properties of configuration subnodes: - Any configuration option not explicitly listed in the dts will be left at - chip default setting. - - - function : name of function to assign to this group. One of: - aif1, aif2, aif3, aif4, mif1, mif2, mif3, pdmspk1, pdmspk2, - dmic3, dmic4, dmic5, dmic6, - io, dsp-gpio, irq1, irq2, - fll1-clk, fll1-lock, fll2-clk, fll2-lock, fll3-clk, fll3-lock, - fllao-clk, fllao-lock, - opclk, opclk-async, pwm1, pwm2, spdif, - asrc1-in1-lock, asrc1-in2-lock, asrc2-in1-lock, asrc2-in2-lock, - spkl-short-circuit, spkr-short-circuit, spk-shutdown, - spk-overheat-shutdown, spk-overheat-warn, - timer1-sts, timer2-sts, timer3-sts, timer4-sts, timer5-sts, timer6-sts, - timer7-sts, timer8-sts, - log1-fifo-ne, log2-fifo-ne, log3-fifo-ne, log4-fifo-ne, log5-fifo-ne, - log6-fifo-ne, log7-fifo-ne, log8-fifo-ne, - - - bias-disable : disable pull-up and pull-down - - bias-bus-hold : enable buskeeper - - bias-pull-up : output is pulled-up - - bias-pull-down : output is pulled-down - - drive-push-pull : CMOS output - - drive-open-drain : open-drain output - - drive-strength : drive strength in mA. Valid values are 4 or 8 - - input-schmitt-enable : enable schmitt-trigger mode - - input-schmitt-disable : disable schmitt-trigger mode - - input-debounce : A value of 0 disables debounce, a value !=0 enables - debounce - - output-low : set the pin to output mode with low level - - output-high : set the pin to output mode with high level - -Example: - -cs47l85@0 { - compatible = "cirrus,cs47l85"; - - pinctrl-names = "default"; - pinctrl-0 = <&cs47l85_defaults>; - - cs47l85_defaults: cs47l85-gpio-defaults { - aif1 { - groups = "aif1"; - function = "aif1"; - bias-bus-hold; - }; - - aif2 { - groups = "aif2"; - function = "aif2"; - bias-bus-hold; - }; - - opclk { - groups = "gpio1"; - function = "opclk"; - bias-pull-up; - drive-strength = <8>; - }; - }; -}; diff --git a/Bindings/pinctrl/cirrus,madera.yaml b/Bindings/pinctrl/cirrus,madera.yaml new file mode 100644 index 000000000000..6bfc25d0e1b3 --- /dev/null +++ b/Bindings/pinctrl/cirrus,madera.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cirrus,madera.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic Madera class audio CODECs pinctrl driver + +maintainers: + - patches@opensource.cirrus.com + +description: | + The Cirrus Logic Madera codecs provide a number of GPIO functions for + interfacing to external hardware and to provide logic outputs to other devices. + Certain groups of GPIO pins also have an alternate function, normally as an + audio interface. + + The set of available GPIOs, functions and alternate function groups differs + between CODECs so refer to the datasheet for the CODEC for further information + on what is supported on that device. + + The properties for this driver exist within the parent MFD driver node. + + See also the core bindings for the parent MFD driver: + + Documentation/devicetree/bindings/mfd/cirrus,madera.yaml + + And the generic pinmix bindings: + + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +properties: + pinctrl-0: + description: + A phandle to the node containing the subnodes containing default + configurations. + + pinctrl-names: + description: + A pinctrl state named "default" must be defined. + const: default + + pin-settings: + description: + One subnode is required to contain the default settings. It + contains an arbitrary number of configuration subnodes, one for + each group or pin configuration you want to apply as a default. + type: object + patternProperties: + '-pins$': + type: object + allOf: + - $ref: "pincfg-node.yaml#" + - $ref: "pinmux-node.yaml#" + properties: + groups: + description: + Name of one pin group to configure. + enum: [ aif1, aif2, aif3, aif4, mif1, mif2, mif3, pdmspk1, + pdmspk2, dmic4, dmic5, dmic6, gpio1, gpio2, gpio3, + gpio4, gpio5, gpio6, gpio7, gpio7, gpio8, gpio9, + gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, + gpio16, gpio17, gpio17, gpio18, gpio19, gpio20, + gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, + gpio27, gpio27, gpio28, gpio29, gpio30, gpio31, + gpio32, gpio33, gpio34, gpio35, gpio36, gpio37, + gpio37, gpio38, gpio39 ] + + function: + description: + Name of function to assign to this group. + enum: [ aif1, aif2, aif3, aif4, mif1, mif2, mif3, + pdmspk1, pdmspk2, dmic3, dmic4, dmic5, + dmic6, io, dsp-gpio, irq1, irq2, fll1-clk, + fll1-lock, fll2-clk, fll2-lock, fll3-clk, + fll3-lock, fllao-clk, fllao-lock, opclk, + opclk-async, pwm1, pwm2, spdif, asrc1-in1-lock, + asrc1-in2-lock, asrc2-in1-lock, asrc2-in2-lock, + spkl-short-circuit, spkr-short-circuit, + spk-shutdown, spk-overheat-shutdown, + spk-overheat-warn, timer1-sts, timer2-sts, + timer3-sts, timer4-sts, timer5-sts, timer6-sts, + timer7-sts, timer8-sts, log1-fifo-ne, + log2-fifo-ne, log3-fifo-ne, log4-fifo-ne, + log5-fifo-ne, log6-fifo-ne, log7-fifo-ne, + log8-fifo-ne ] + + bias-disable: true + + bias-bus-hold: true + + bias-pull-up: true + + bias-pull-down: true + + drive-push-pull: true + + drive-open-drain: true + + drive-strength: + enum: [ 4, 8 ] + + input-schmitt-enable: true + + input-schmitt-disable: true + + input-debounce: true + + output-low: true + + output-high: true + + additionalProperties: false + + required: + - groups + + additionalProperties: false + +required: + - pinctrl-0 + - pinctrl-names diff --git a/Bindings/pinctrl/fsl,imx8mm-pinctrl.yaml b/Bindings/pinctrl/fsl,imx8mm-pinctrl.yaml index d98a3866add8..6d7d162e6171 100644 --- a/Bindings/pinctrl/fsl,imx8mm-pinctrl.yaml +++ b/Bindings/pinctrl/fsl,imx8mm-pinctrl.yaml @@ -37,22 +37,21 @@ patternProperties: be found in . The last integer CONFIG is the pad setting value like pull-up on this pin. Please refer to i.MX8M Mini Reference Manual for detailed CONFIG settings. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-matrix - - items: - items: - - description: | - "mux_reg" indicates the offset of mux register. - - description: | - "conf_reg" indicates the offset of pad configuration register. - - description: | - "input_reg" indicates the offset of select input register. - - description: | - "mux_val" indicates the mux value to be applied. - - description: | - "input_val" indicates the select input value to be applied. - - description: | - "pad_setting" indicates the pad configuration value to be applied. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. required: - fsl,pins diff --git a/Bindings/pinctrl/fsl,imx8mn-pinctrl.yaml b/Bindings/pinctrl/fsl,imx8mn-pinctrl.yaml index b9aa180e07e4..7131cfd1fc45 100644 --- a/Bindings/pinctrl/fsl,imx8mn-pinctrl.yaml +++ b/Bindings/pinctrl/fsl,imx8mn-pinctrl.yaml @@ -37,22 +37,21 @@ patternProperties: be found in . The last integer CONFIG is the pad setting value like pull-up on this pin. Please refer to i.MX8M Nano Reference Manual for detailed CONFIG settings. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-matrix - - items: - items: - - description: | - "mux_reg" indicates the offset of mux register. - - description: | - "conf_reg" indicates the offset of pad configuration register. - - description: | - "input_reg" indicates the offset of select input register. - - description: | - "mux_val" indicates the mux value to be applied. - - description: | - "input_val" indicates the select input value to be applied. - - description: | - "pad_setting" indicates the pad configuration value to be applied. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. required: - fsl,pins diff --git a/Bindings/pinctrl/fsl,imx8mp-pinctrl.yaml b/Bindings/pinctrl/fsl,imx8mp-pinctrl.yaml index 6297e78418cf..d474bc1f393b 100644 --- a/Bindings/pinctrl/fsl,imx8mp-pinctrl.yaml +++ b/Bindings/pinctrl/fsl,imx8mp-pinctrl.yaml @@ -37,22 +37,21 @@ patternProperties: be found in . The last integer CONFIG is the pad setting value like pull-up on this pin. Please refer to i.MX8M Plus Reference Manual for detailed CONFIG settings. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-matrix - - items: - items: - - description: | - "mux_reg" indicates the offset of mux register. - - description: | - "conf_reg" indicates the offset of pad configuration register. - - description: | - "input_reg" indicates the offset of select input register. - - description: | - "mux_val" indicates the mux value to be applied. - - description: | - "input_val" indicates the select input value to be applied. - - description: | - "pad_setting" indicates the pad configuration value to be applied. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. required: - fsl,pins diff --git a/Bindings/pinctrl/fsl,imx8mq-pinctrl.yaml b/Bindings/pinctrl/fsl,imx8mq-pinctrl.yaml index b30c704fcfa1..0af2b6c95c17 100644 --- a/Bindings/pinctrl/fsl,imx8mq-pinctrl.yaml +++ b/Bindings/pinctrl/fsl,imx8mq-pinctrl.yaml @@ -37,22 +37,21 @@ patternProperties: be found in . The last integer CONFIG is the pad setting value like pull-up on this pin. Please refer to i.MX8M Quad Reference Manual for detailed CONFIG settings. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-matrix - - items: - items: - - description: | - "mux_reg" indicates the offset of mux register. - - description: | - "conf_reg" indicates the offset of pad configuration register. - - description: | - "input_reg" indicates the offset of select input register. - - description: | - "mux_val" indicates the mux value to be applied. - - description: | - "input_val" indicates the select input value to be applied. - - description: | - "pad_setting" indicates the pad configuration value to be applied. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. required: - fsl,pins diff --git a/Bindings/pinctrl/intel,lgm-io.yaml b/Bindings/pinctrl/intel,lgm-io.yaml index cd2b436350ef..2c0acb405e6c 100644 --- a/Bindings/pinctrl/intel,lgm-io.yaml +++ b/Bindings/pinctrl/intel,lgm-io.yaml @@ -24,12 +24,10 @@ properties: patternProperties: '-pins$': type: object - allOf: - - $ref: pincfg-node.yaml# - - $ref: pinmux-node.yaml# description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. + $ref: pinmux-node.yaml# properties: function: true diff --git a/Bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Bindings/pinctrl/mscc,ocelot-pinctrl.txt index 32a8a8fa7805..00912449237b 100644 --- a/Bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -2,8 +2,8 @@ Microsemi Ocelot pin controller Device Tree Bindings ---------------------------------------------------- Required properties: - - compatible : Should be "mscc,ocelot-pinctrl" or - "mscc,jaguar2-pinctrl" + - compatible : Should be "mscc,ocelot-pinctrl", + "mscc,jaguar2-pinctrl" or "microchip,sparx5-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. diff --git a/Bindings/pinctrl/pinmux-node.yaml b/Bindings/pinctrl/pinmux-node.yaml index 732d9075560b..ef8877ddb1eb 100644 --- a/Bindings/pinctrl/pinmux-node.yaml +++ b/Bindings/pinctrl/pinmux-node.yaml @@ -122,11 +122,10 @@ properties: this, "pins" or "pinmux" has to be specified) pinmux: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array description: The list of numeric pin ids and their mux settings that properties in the node apply to (either this, "pins" or "groups" have to be specified) + $ref: /schemas/types.yaml#/definitions/uint32-array pinctrl-pin-array: $ref: /schemas/types.yaml#/definitions/uint32-array diff --git a/Bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/Bindings/pinctrl/qcom,ipq6018-pinctrl.yaml index 63d1cfe86c6e..b2de3992d484 100644 --- a/Bindings/pinctrl/qcom,ipq6018-pinctrl.yaml +++ b/Bindings/pinctrl/qcom,ipq6018-pinctrl.yaml @@ -49,8 +49,7 @@ patternProperties: description: Pinctrl node's client devices use subnodes for desired pin configuration. Client device subnodes use below standard properties. - allOf: - - $ref: "/schemas/pinctrl/pincfg-node.yaml" + $ref: "/schemas/pinctrl/pincfg-node.yaml" properties: pins: diff --git a/Bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Bindings/pinctrl/qcom,sm8250-pinctrl.yaml new file mode 100644 index 000000000000..6dc3b52f47cd --- /dev/null +++ b/Bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8250 TLMM block + +maintainers: + - Bjorn Andersson + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SM8250 platform. + +properties: + compatible: + const: qcom,sm8250-pinctrl + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + items: + - const: "west" + - const: "south" + - const: "north" + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + wakeup-parent: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '^.*$': + if: + type: object + then: + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio, + ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, + mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, + mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, + mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1, + pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset, + pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, + qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6, + qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, + sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1, + tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data, + tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en, + tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + pinctrl@1f00000 { + compatible = "qcom,sm8250-pinctrl"; + reg = <0x0f100000 0x300000>, + <0x0f500000 0x300000>, + <0x0f900000 0x300000>; + reg-names = "west", "south", "north"; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 180>; + wakeup-parent = <&pdc>; + }; diff --git a/Bindings/pinctrl/renesas,pfc-pinctrl.txt b/Bindings/pinctrl/renesas,pfc-pinctrl.txt index 6eada23eaa31..1b8e8b4a6379 100644 --- a/Bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -13,6 +13,7 @@ Required Properties: - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller. - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. + - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller. - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. - "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller. - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. @@ -113,7 +114,7 @@ with values derived from the SoC user manual. [flags]> On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver. -Please refer to Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +Please refer to Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml for documentation of the GPIO device tree bindings on those platforms. diff --git a/Bindings/pinctrl/rockchip,pinctrl.txt b/Bindings/pinctrl/rockchip,pinctrl.txt index 2113cfaa26e6..d3eae61a340d 100644 --- a/Bindings/pinctrl/rockchip,pinctrl.txt +++ b/Bindings/pinctrl/rockchip,pinctrl.txt @@ -110,8 +110,8 @@ pinctrl@20008000 { uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, + <1 RK_PB1 1 &pcfg_pull_default>; }; }; }; diff --git a/Bindings/pinctrl/st,stm32-pinctrl.yaml b/Bindings/pinctrl/st,stm32-pinctrl.yaml index 46a0478cb924..0857cbeeb43c 100644 --- a/Bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Bindings/pinctrl/st,stm32-pinctrl.yaml @@ -36,22 +36,22 @@ properties: pins-are-numbered: true hwlocks: true + interrupts: + maxItems: 1 + st,syscfg: - allOf: - - $ref: "/schemas/types.yaml#/definitions/phandle-array" description: Should be phandle/offset/mask - Phandle to the syscon node which includes IRQ mux selection. - The offset of the IRQ mux selection register. - The field mask of IRQ mux, needed if different of 0xf. + $ref: "/schemas/types.yaml#/definitions/phandle-array" st,package: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [1, 2, 4, 8] description: Indicates the SOC package used. More details in include/dt-bindings/pinctrl/stm32-pinfunc.h - + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8] patternProperties: '^gpio@[0-9a-f]*$': @@ -78,33 +78,30 @@ patternProperties: maximum: 16 st,bank-name: - allOf: - - $ref: "/schemas/types.yaml#/definitions/string" - - enum: - - GPIOA - - GPIOB - - GPIOC - - GPIOD - - GPIOE - - GPIOF - - GPIOG - - GPIOH - - GPIOI - - GPIOJ - - GPIOK - - GPIOZ description: Should be a name string for this bank as specified in the datasheet. + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - GPIOA + - GPIOB + - GPIOC + - GPIOD + - GPIOE + - GPIOF + - GPIOG + - GPIOH + - GPIOI + - GPIOJ + - GPIOK + - GPIOZ st,bank-ioport: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - - maximum: 11 - description: Should correspond to the EXTI IOport selection (EXTI line used to select GPIOs as interrupts). + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 11 required: - gpio-controller @@ -125,8 +122,7 @@ patternProperties: configuration, pullups, drive, output high/low and output speed. properties: pinmux: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32-array" + $ref: "/schemas/types.yaml#/definitions/uint32-array" description: | Integer array, represents gpio pin number and mux setting. Supported pin number and mux varies for different SoCs, and are @@ -180,9 +176,8 @@ patternProperties: 1: Medium speed 2: Fast speed 3: High speed - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [0, 1, 2, 3] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] required: - pinmux diff --git a/Bindings/power/amlogic,meson-ee-pwrc.yaml b/Bindings/power/amlogic,meson-ee-pwrc.yaml index 6c6079fe1351..4f524f822e84 100644 --- a/Bindings/power/amlogic,meson-ee-pwrc.yaml +++ b/Bindings/power/amlogic,meson-ee-pwrc.yaml @@ -23,48 +23,119 @@ description: |+ properties: compatible: enum: + - amlogic,meson8-pwrc + - amlogic,meson8b-pwrc + - amlogic,meson8m2-pwrc + - amlogic,meson-gxbb-pwrc - amlogic,meson-g12a-pwrc - amlogic,meson-sm1-pwrc clocks: - minItems: 2 + minItems: 1 + maxItems: 2 clock-names: + minItems: 1 + maxItems: 2 items: - const: vpu - const: vapb resets: minItems: 11 + maxItems: 12 reset-names: - items: - - const: viu - - const: venc - - const: vcbus - - const: bt656 - - const: rdma - - const: venci - - const: vencp - - const: vdac - - const: vdi6 - - const: vencl - - const: vid_lock + minItems: 11 + maxItems: 12 "#power-domain-cells": const: 1 amlogic,ao-sysctrl: description: phandle to the AO sysctrl node - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle + +allOf: + - if: + properties: + compatible: + enum: + - amlogic,meson8b-pwrc + - amlogic,meson8m2-pwrc + then: + properties: + reset-names: + items: + - const: dblk + - const: pic_dc + - const: hdmi_apb + - const: hdmi_system + - const: venci + - const: vencp + - const: vdac + - const: vencl + - const: viu + - const: venc + - const: rdma + required: + - resets + - reset-names + + - if: + properties: + compatible: + enum: + - amlogic,meson-gxbb-pwrc + then: + properties: + reset-names: + items: + - const: viu + - const: venc + - const: vcbus + - const: bt656 + - const: dvin + - const: rdma + - const: venci + - const: vencp + - const: vdac + - const: vdi6 + - const: vencl + - const: vid_lock + required: + - resets + - reset-names + + - if: + properties: + compatible: + enum: + - amlogic,meson-g12a-pwrc + - amlogic,meson-sm1-pwrc + then: + properties: + reset-names: + items: + - const: viu + - const: venc + - const: vcbus + - const: bt656 + - const: rdma + - const: venci + - const: vencp + - const: vdac + - const: vdi6 + - const: vencl + - const: vid_lock + required: + - resets + - reset-names required: - compatible - clocks - clock-names - - resets - - reset-names - "#power-domain-cells" - amlogic,ao-sysctrl diff --git a/Bindings/power/fsl,imx-gpc.txt b/Bindings/power/fsl,imx-gpc.txt deleted file mode 100644 index f0f5553a9e74..000000000000 --- a/Bindings/power/fsl,imx-gpc.txt +++ /dev/null @@ -1,91 +0,0 @@ -Freescale i.MX General Power Controller -======================================= - -The i.MX6 General Power Control (GPC) block contains DVFS load tracking -counters and Power Gating Control (PGC). - -Required properties: -- compatible: Should be one of the following: - - fsl,imx6q-gpc - - fsl,imx6qp-gpc - - fsl,imx6sl-gpc - - fsl,imx6sx-gpc -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain one interrupt specifier for the GPC interrupt -- clocks: Must contain an entry for each entry in clock-names. - See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - ipg - -The power domains are generic power domain providers as documented in -Documentation/devicetree/bindings/power/power-domain.yaml. They are described as -subnodes of the power gating controller 'pgc' node of the GPC and should -contain the following: - -Required properties: -- reg: Must contain the DOMAIN_INDEX of this power domain - The following DOMAIN_INDEX values are valid for i.MX6Q: - ARM_DOMAIN 0 - PU_DOMAIN 1 - The following additional DOMAIN_INDEX value is valid for i.MX6SL: - DISPLAY_DOMAIN 2 - The following additional DOMAIN_INDEX value is valid for i.MX6SX: - PCI_DOMAIN 3 - -- #power-domain-cells: Should be 0 - -Optional properties: -- clocks: a number of phandles to clocks that need to be enabled during domain - power-up sequencing to ensure reset propagation into devices located inside - this power domain -- power-supply: a phandle to the regulator powering this domain - -Example: - - gpc: gpc@20dc000 { - compatible = "fsl,imx6q-gpc"; - reg = <0x020dc000 0x4000>; - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPG>; - clock-names = "ipg"; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - power-domain@0 { - reg = <0>; - #power-domain-cells = <0>; - }; - - pd_pu: power-domain@1 { - reg = <1>; - #power-domain-cells = <0>; - power-supply = <®_pu>; - clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>, - <&clks IMX6QDL_CLK_GPU2D_CORE>, - <&clks IMX6QDL_CLK_GPU2D_AXI>, - <&clks IMX6QDL_CLK_OPENVG_AXI>, - <&clks IMX6QDL_CLK_VPU_AXI>; - }; - }; - }; - - -Specifying power domain for IP modules -====================================== - -IP cores belonging to a power domain should contain a 'power-domains' property -that is a phandle pointing to the power domain the device belongs to. - -Example of a device that is part of the PU power domain: - - vpu: vpu@2040000 { - reg = <0x02040000 0x3c000>; - /* ... */ - power-domains = <&pd_pu>; - /* ... */ - }; diff --git a/Bindings/power/fsl,imx-gpc.yaml b/Bindings/power/fsl,imx-gpc.yaml new file mode 100644 index 000000000000..a055b3e819d8 --- /dev/null +++ b/Bindings/power/fsl,imx-gpc.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX General Power Controller + +maintainers: + - Philipp Zabel + +description: | + The i.MX6 General Power Control (GPC) block contains DVFS load tracking + counters and Power Gating Control (PGC). + + The power domains are generic power domain providers as documented in + Documentation/devicetree/bindings/power/power-domain.yaml. They are + described as subnodes of the power gating controller 'pgc' node of the GPC. + + IP cores belonging to a power domain should contain a 'power-domains' + property that is a phandle pointing to the power domain the device belongs + to. + +properties: + compatible: + enum: + - fsl,imx6q-gpc + - fsl,imx6qp-gpc + - fsl,imx6sl-gpc + - fsl,imx6sx-gpc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: ipg + + pgc: + type: object + description: list of power domains provided by this controller. + + patternProperties: + "power-domain@[0-9]$": + type: object + properties: + + '#power-domain-cells': + const: 0 + + reg: + description: | + The following DOMAIN_INDEX values are valid for i.MX6Q: + ARM_DOMAIN 0 + PU_DOMAIN 1 + The following additional DOMAIN_INDEX value is valid for i.MX6SL: + DISPLAY_DOMAIN 2 + The following additional DOMAIN_INDEX value is valid for i.MX6SX: + PCI_DOMAIN 3 + maxItems: 1 + + clocks: + description: | + A number of phandles to clocks that need to be enabled during domain + power-up sequencing to ensure reset propagation into devices located + inside this power domain. + minItems: 1 + maxItems: 7 + + power-supply: true + + required: + - '#power-domain-cells' + - reg + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - pgc + +additionalProperties: false + +examples: + - | + #include + #include + + gpc@20dc000 { + compatible = "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + + pd_pu: power-domain@1 { + reg = <1>; + #power-domain-cells = <0>; + power-supply = <®_pu>; + clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_SHADER>, + <&clks IMX6QDL_CLK_GPU2D_CORE>, + <&clks IMX6QDL_CLK_GPU2D_AXI>, + <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_VPU_AXI>; + }; + }; + }; diff --git a/Bindings/power/fsl,imx-gpcv2.txt b/Bindings/power/fsl,imx-gpcv2.txt deleted file mode 100644 index 61649202f6f5..000000000000 --- a/Bindings/power/fsl,imx-gpcv2.txt +++ /dev/null @@ -1,77 +0,0 @@ -Freescale i.MX General Power Controller v2 -========================================== - -The i.MX7S/D General Power Control (GPC) block contains Power Gating -Control (PGC) for various power domains. - -Required properties: - -- compatible: Should be one of: - - "fsl,imx7d-gpc" - - "fsl,imx8mq-gpc" - -- reg: should be register base and length as documented in the - datasheet - -- interrupts: Should contain GPC interrupt request 1 - -Power domains contained within GPC node are generic power domain -providers, documented in -Documentation/devicetree/bindings/power/power-domain.yaml, which are -described as subnodes of the power gating controller 'pgc' node, -which, in turn, is expected to contain the following: - -Required properties: - -- reg: Power domain index. Valid values are defined in - include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and - include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc - -- #power-domain-cells: Should be 0 - -Optional properties: - -- power-supply: Power supply used to power the domain -- clocks: a number of phandles to clocks that need to be enabled during - domain power-up sequencing to ensure reset propagation into devices - located inside this power domain - -Example: - - gpc: gpc@303a0000 { - compatible = "fsl,imx7d-gpc"; - reg = <0x303a0000 0x1000>; - interrupt-controller; - interrupts = ; - #interrupt-cells = <3>; - interrupt-parent = <&intc>; - - pgc { - #address-cells = <1>; - #size-cells = <0>; - - pgc_pcie_phy: power-domain@1 { - #power-domain-cells = <0>; - - reg = <1>; - power-supply = <®_1p0d>; - }; - }; - }; - - -Specifying power domain for IP modules -====================================== - -IP cores belonging to a power domain should contain a 'power-domains' -property that is a phandle for PGC node representing the domain. - -Example of a device that is part of the PCIE_PHY power domain: - - pcie: pcie@33800000 { - reg = <0x33800000 0x4000>, - <0x4ff00000 0x80000>; - /* ... */ - power-domains = <&pgc_pcie_phy>; - /* ... */ - }; diff --git a/Bindings/power/fsl,imx-gpcv2.yaml b/Bindings/power/fsl,imx-gpcv2.yaml new file mode 100644 index 000000000000..bde09a0b2da3 --- /dev/null +++ b/Bindings/power/fsl,imx-gpcv2.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/fsl,imx-gpcv2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX General Power Controller v2 + +maintainers: + - Andrey Smirnov + +description: | + The i.MX7S/D General Power Control (GPC) block contains Power Gating + Control (PGC) for various power domains. + + Power domains contained within GPC node are generic power domain + providers, documented in + Documentation/devicetree/bindings/power/power-domain.yaml, which are + described as subnodes of the power gating controller 'pgc' node. + + IP cores belonging to a power domain should contain a 'power-domains' + property that is a phandle for PGC node representing the domain. + +properties: + compatible: + enum: + - fsl,imx7d-gpc + - fsl,imx8mq-gpc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + pgc: + type: object + description: list of power domains provided by this controller. + + patternProperties: + "power-domain@[0-9]$": + type: object + properties: + + '#power-domain-cells': + const: 0 + + reg: + description: | + Power domain index. Valid values are defined in + include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and + include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc + maxItems: 1 + + clocks: + description: | + A number of phandles to clocks that need to be enabled during domain + power-up sequencing to ensure reset propagation into devices located + inside this power domain. + minItems: 1 + maxItems: 5 + + power-supply: true + + required: + - '#power-domain-cells' + - reg + +required: + - compatible + - reg + - interrupts + - pgc + +additionalProperties: false + +examples: + - | + #include + + gpc@303a0000 { + compatible = "fsl,imx7d-gpc"; + reg = <0x303a0000 0x1000>; + interrupts = ; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_mipi_phy: power-domain@0 { + #power-domain-cells = <0>; + reg = <0>; + power-supply = <®_1p0d>; + }; + + pgc_pcie_phy: power-domain@1 { + #power-domain-cells = <0>; + reg = <1>; + power-supply = <®_1p0d>; + }; + + pgc_hsic_phy: power-domain@2 { + #power-domain-cells = <0>; + reg = <2>; + power-supply = <®_1p2>; + }; + }; + }; diff --git a/Bindings/power/qcom,rpmpd.yaml b/Bindings/power/qcom,rpmpd.yaml index ba605310abeb..8058955fb3b9 100644 --- a/Bindings/power/qcom,rpmpd.yaml +++ b/Bindings/power/qcom,rpmpd.yaml @@ -23,6 +23,7 @@ properties: - qcom,sc7180-rpmhpd - qcom,sdm845-rpmhpd - qcom,sm8150-rpmhpd + - qcom,sm8250-rpmhpd '#power-domain-cells': const: 1 diff --git a/Bindings/power/renesas,apmu.yaml b/Bindings/power/renesas,apmu.yaml index 078b2cb40fe3..60a23b3beb40 100644 --- a/Bindings/power/renesas,apmu.yaml +++ b/Bindings/power/renesas,apmu.yaml @@ -18,6 +18,7 @@ properties: compatible: items: - enum: + - renesas,r8a7742-apmu # RZ/G1H - renesas,r8a7743-apmu # RZ/G1M - renesas,r8a7744-apmu # RZ/G1N - renesas,r8a7745-apmu # RZ/G1E diff --git a/Bindings/power/renesas,rcar-sysc.yaml b/Bindings/power/renesas,rcar-sysc.yaml index e59331e1d944..55b6ab2d8784 100644 --- a/Bindings/power/renesas,rcar-sysc.yaml +++ b/Bindings/power/renesas,rcar-sysc.yaml @@ -17,6 +17,7 @@ description: properties: compatible: enum: + - renesas,r8a7742-sysc # RZ/G1H - renesas,r8a7743-sysc # RZ/G1M - renesas,r8a7744-sysc # RZ/G1N - renesas,r8a7745-sysc # RZ/G1E diff --git a/Bindings/power/reset/syscon-reboot-mode.txt b/Bindings/power/reset/syscon-reboot-mode.txt deleted file mode 100644 index f7ce1d8af04a..000000000000 --- a/Bindings/power/reset/syscon-reboot-mode.txt +++ /dev/null @@ -1,35 +0,0 @@ -SYSCON reboot mode driver - -This driver gets reboot mode magic value form reboot-mode driver -and stores it in a SYSCON mapped register. Then the bootloader -can read it and take different action according to the magic -value stored. - -This DT node should be represented as a sub-node of a "syscon", "simple-mfd" -node. - -Required properties: -- compatible: should be "syscon-reboot-mode" -- offset: offset in the register map for the storage register (in bytes) - -Optional property: -- mask: bits mask of the bits in the register to store the reboot mode magic value, - default set to 0xffffffff if missing. - -The rest of the properties should follow the generic reboot-mode description -found in reboot-mode.txt - -Example: - pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; - reg = <0x20004000 0x100>; - - reboot-mode { - compatible = "syscon-reboot-mode"; - offset = <0x40>; - mode-normal = ; - mode-recovery = ; - mode-bootloader = ; - mode-loader = ; - }; - }; diff --git a/Bindings/power/reset/syscon-reboot-mode.yaml b/Bindings/power/reset/syscon-reboot-mode.yaml new file mode 100644 index 000000000000..9b1ffceefe3d --- /dev/null +++ b/Bindings/power/reset/syscon-reboot-mode.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/syscon-reboot-mode.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic SYSCON reboot mode driver + +maintainers: + - Sebastian Reichel + +description: | + This driver gets reboot mode magic value from reboot-mode driver + and stores it in a SYSCON mapped register. Then the bootloader + can read it and take different action according to the magic + value stored. The SYSCON mapped register is retrieved from the + parental dt-node plus the offset. So the SYSCON reboot-mode node + should be represented as a sub-node of a "syscon", "simple-mfd" node. + +properties: + compatible: + const: syscon-reboot-mode + + mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Update only the register bits defined by the mask (32 bit) + + offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset in the register map for the mode register (in bytes) + +patternProperties: + "^mode-.+": + $ref: /schemas/types.yaml#/definitions/uint32 + description: Vendor-specific mode value written to the mode register + +additionalProperties: false + +required: + - compatible + - offset + +examples: + - | + #include + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x40>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; +... diff --git a/Bindings/power/reset/syscon-reboot.yaml b/Bindings/power/reset/syscon-reboot.yaml index b80772cb9f06..da2509724812 100644 --- a/Bindings/power/reset/syscon-reboot.yaml +++ b/Bindings/power/reset/syscon-reboot.yaml @@ -12,9 +12,12 @@ maintainers: description: |+ This is a generic reset driver using syscon to map the reset register. The reset is generally performed with a write to the reset register - defined by the register map pointed by syscon reference plus the offset - with the value and mask defined in the reboot node. - Default will be little endian mode, 32 bit access only. + defined by the SYSCON register map base plus the offset with the value and + mask defined in the reboot node. Default will be little endian mode, 32 bit + access only. The SYSCON registers map is normally retrieved from the + parental dt-node. So the SYSCON reboot node should be represented as a + sub-node of a "syscon", "simple-mfd" node. Though the regmap property + pointing to the system controller node is also supported. properties: compatible: @@ -30,7 +33,10 @@ properties: regmap: $ref: /schemas/types.yaml#/definitions/phandle - description: Phandle to the register map node. + deprecated: true + description: | + Phandle to the register map node. This property is deprecated in favor of + the syscon-reboot node been a child of a system controller node. value: $ref: /schemas/types.yaml#/definitions/uint32 @@ -38,7 +44,6 @@ properties: required: - compatible - - regmap - offset additionalProperties: false diff --git a/Bindings/power/supply/battery.txt b/Bindings/power/supply/battery.txt index 3049cf88bdcf..5e29595edd74 100644 --- a/Bindings/power/supply/battery.txt +++ b/Bindings/power/supply/battery.txt @@ -11,15 +11,21 @@ different type. This prevents unpredictable, potentially harmful, behavior should a replacement that changes the battery type occur without a corresponding update to the dtb. +Please note that not all charger drivers respect all of the properties. + Required Properties: - compatible: Must be "simple-battery" Optional Properties: + - over-voltage-threshold-microvolt: battery over-voltage limit + - re-charge-voltage-microvolt: limit to automatically start charging again - voltage-min-design-microvolt: drained battery voltage - voltage-max-design-microvolt: fully charged battery voltage - energy-full-design-microwatt-hours: battery design energy - charge-full-design-microamp-hours: battery design capacity + - trickle-charge-current-microamp: current for trickle-charge phase - precharge-current-microamp: current for pre-charge phase + - precharge-upper-limit-microvolt: limit when to change to constant charging - charge-term-current-microamp: current for charge termination phase - constant-charge-current-max-microamp: maximum constant input current - constant-charge-voltage-max-microvolt: maximum constant input voltage diff --git a/Bindings/power/supply/bq27xxx.txt b/Bindings/power/supply/bq27xxx.txt deleted file mode 100644 index 4fa8e08df2b6..000000000000 --- a/Bindings/power/supply/bq27xxx.txt +++ /dev/null @@ -1,56 +0,0 @@ -TI BQ27XXX fuel gauge family - -Required properties: -- compatible: contains one of the following: - * "ti,bq27200" - BQ27200 - * "ti,bq27210" - BQ27210 - * "ti,bq27500" - deprecated, use revision specific property below - * "ti,bq27510" - deprecated, use revision specific property below - * "ti,bq27520" - deprecated, use revision specific property below - * "ti,bq27500-1" - BQ27500/1 - * "ti,bq27510g1" - BQ27510-g1 - * "ti,bq27510g2" - BQ27510-g2 - * "ti,bq27510g3" - BQ27510-g3 - * "ti,bq27520g1" - BQ27520-g1 - * "ti,bq27520g2" - BQ27520-g2 - * "ti,bq27520g3" - BQ27520-g3 - * "ti,bq27520g4" - BQ27520-g4 - * "ti,bq27521" - BQ27521 - * "ti,bq27530" - BQ27530 - * "ti,bq27531" - BQ27531 - * "ti,bq27541" - BQ27541 - * "ti,bq27542" - BQ27542 - * "ti,bq27546" - BQ27546 - * "ti,bq27742" - BQ27742 - * "ti,bq27545" - BQ27545 - * "ti,bq27411" - BQ27411 - * "ti,bq27421" - BQ27421 - * "ti,bq27425" - BQ27425 - * "ti,bq27426" - BQ27426 - * "ti,bq27441" - BQ27441 - * "ti,bq27621" - BQ27621 -- reg: integer, I2C address of the fuel gauge. - -Optional properties: -- monitored-battery: phandle of battery characteristics node - The fuel gauge uses the following battery properties: - + energy-full-design-microwatt-hours - + charge-full-design-microamp-hours - + voltage-min-design-microvolt - Both or neither of the *-full-design-*-hours properties must be set. - See Documentation/devicetree/bindings/power/supply/battery.txt - -Example: - - bat: battery { - compatible = "simple-battery"; - voltage-min-design-microvolt = <3200000>; - energy-full-design-microwatt-hours = <5290000>; - charge-full-design-microamp-hours = <1430000>; - }; - - bq27510g3: fuel-gauge@55 { - compatible = "ti,bq27510g3"; - reg = <0x55>; - monitored-battery = <&bat>; - }; diff --git a/Bindings/power/supply/bq27xxx.yaml b/Bindings/power/supply/bq27xxx.yaml new file mode 100644 index 000000000000..03d1020a2e47 --- /dev/null +++ b/Bindings/power/supply/bq27xxx.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2020 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/supply/bq27xxx.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI BQ27XXX fuel gauge family + +maintainers: + - Pali Rohár + - Andrew F. Davis + - Sebastian Reichel + +description: | + Support various Texas Instruments fuel gauge devices that share similar + register maps and power supply properties + +allOf: + - $ref: power-supply.yaml# + +properties: + compatible: + enum: + - ti,bq27200 + - ti,bq27210 + - ti,bq27500 # deprecated, use revision specific property below + - ti,bq27510 # deprecated, use revision specific property below + - ti,bq27520 # deprecated, use revision specific property below + - ti,bq27500-1 + - ti,bq27510g1 + - ti,bq27510g2 + - ti,bq27510g3 + - ti,bq27520g1 + - ti,bq27520g2 + - ti,bq27520g3 + - ti,bq27520g4 + - ti,bq27521 + - ti,bq27530 + - ti,bq27531 + - ti,bq27541 + - ti,bq27542 + - ti,bq27546 + - ti,bq27742 + - ti,bq27545 + - ti,bq27411 + - ti,bq27421 + - ti,bq27425 + - ti,bq27426 + - ti,bq27441 + - ti,bq27621 + + reg: + maxItems: 1 + description: integer, I2C address of the fuel gauge. + + monitored-battery: + description: | + phandle of battery characteristics node. + The fuel gauge uses the following battery properties: + - energy-full-design-microwatt-hours + - charge-full-design-microamp-hours + - voltage-min-design-microvolt + Both or neither of the *-full-design-*-hours properties must be set. + See Documentation/devicetree/bindings/power/supply/battery.txt + + power-supplies: true + +required: + - compatible + - reg +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + bat: battery { + compatible = "simple-battery"; + voltage-min-design-microvolt = <3200000>; + energy-full-design-microwatt-hours = <5290000>; + charge-full-design-microamp-hours = <1430000>; + }; + + bq27510g3: fuel-gauge@55 { + compatible = "ti,bq27510g3"; + reg = <0x55>; + monitored-battery = <&bat>; + }; + }; diff --git a/Bindings/power/supply/cw2015_battery.yaml b/Bindings/power/supply/cw2015_battery.yaml new file mode 100644 index 000000000000..2036977ecc2f --- /dev/null +++ b/Bindings/power/supply/cw2015_battery.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/cw2015_battery.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Battery driver for CW2015 shuntless fuel gauge by CellWise. + +maintainers: + - Tobias Schramm + +description: | + The driver can utilize information from a simple-battery linked via a + phandle in monitored-battery. If specified the driver uses the + charge-full-design-microamp-hours property of the battery. + +properties: + compatible: + const: cellwise,cw2015 + + reg: + maxItems: 1 + + cellwise,battery-profile: + description: | + This property specifies characteristics of the battery used. The format + of this binary blob is kept secret by CellWise. The only way to obtain + it is to mail two batteries to a test facility of CellWise and receive + back a test report with the binary blob. + $ref: /schemas/types.yaml#definitions/uint8-array + minItems: 64 + maxItems: 64 + + cellwise,monitor-interval-ms: + description: + Specifies the interval in milliseconds gauge values are polled at + minimum: 250 + + power-supplies: + description: + Specifies supplies used for charging the battery connected to this gauge + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 8 # Should be enough + + monitored-battery: + description: + Specifies the phandle of a simple-battery connected to this gauge + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + cw2015@62 { + compatible = "cellwise,cw201x"; + reg = <0x62>; + cellwise,battery-profile = /bits/ 8 < + 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63 + 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36 + 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69 + 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59 + 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17 + 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D + 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB + 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11 + >; + cellwise,monitor-interval-ms = <5000>; + monitored-battery = <&bat>; + power-supplies = <&mains_charger>, <&usb_charger>; + }; + }; + diff --git a/Bindings/power/supply/power-supply.yaml b/Bindings/power/supply/power-supply.yaml new file mode 100644 index 000000000000..3bb02bb3a2d8 --- /dev/null +++ b/Bindings/power/supply/power-supply.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/power/supply/power-supply.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Power Supply Core Support + +maintainers: + - Sebastian Reichel + +properties: + power-supplies: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + This property is added to a supply in order to list the devices which + supply it power, referenced by their phandles. + +examples: + - | + power { + #address-cells = <1>; + #size-cells = <0>; + + usb_charger:charger@e { + compatible = "some,usb-charger"; + reg = <0xe>; + }; + + ac_charger:charger@c { + compatible = "some,ac-charger"; + reg = <0xc>; + }; + + battery:battery@b { + compatible = "some,battery"; + reg = <0xb>; + power-supplies = <&usb_charger>, <&ac_charger>; + }; + }; diff --git a/Bindings/power/supply/power_supply.txt b/Bindings/power/supply/power_supply.txt index 8391bfa0edac..d9693e054509 100644 --- a/Bindings/power/supply/power_supply.txt +++ b/Bindings/power/supply/power_supply.txt @@ -1,23 +1,2 @@ -Power Supply Core Support - -Optional Properties: - - power-supplies : This property is added to a supply in order to list the - devices which supply it power, referenced by their phandles. - -Example: - - usb-charger: power@e { - compatible = "some,usb-charger"; - ... - }; - - ac-charger: power@c { - compatible = "some,ac-charger"; - ... - }; - - battery@b { - compatible = "some,battery"; - ... - power-supplies = <&usb-charger>, <&ac-charger>; - }; +This binding has been converted to yaml please see power-supply.yaml in this +directory. diff --git a/Bindings/power/supply/rohm,bd99954.yaml b/Bindings/power/supply/rohm,bd99954.yaml new file mode 100644 index 000000000000..7e0f73a898c7 --- /dev/null +++ b/Bindings/power/supply/rohm,bd99954.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/rohm,bd99954.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD99954 Battery charger + +maintainers: + - Matti Vaittinen + - Markus Laine + - Mikko Mutanen + +description: | + The ROHM BD99954 is a Battery Management LSI for 1-4 cell Lithium-Ion + secondary battery intended to be used in space-constraint equipment such + as Low profile Notebook PC, Tablets and other applications. BD99954 + provides a Dual-source Battery Charger, two port BC1.2 detection and a + Battery Monitor. + + +properties: + compatible: + const: rohm,bd99954 +# +# The battery charging profile of BD99954. +# +# Curve (1) represents charging current. +# Curve (2) represents battery voltage. +# +# The BD99954 data sheet divides charging to three phases. +# a) Trickle-charge with constant current (8). +# b) pre-charge with constant current (6) +# c) fast-charge with: +# First a constant current (5) phase (CC) +# Then constant voltage (CV) phase (after the battery voltage has reached +# target level - until charging current has dropped to termination +# level (7) +# +# V ^ ^ I +# . . +# . . +# (4)- -.- - - - - - - - - - - - - - +++++++++++++++++++++++++++. +# . / . +# . ++++++/++ - - - - - - - - - - - - -.- - (5) +# . + / + . +# . + - -- . +# . + - + . +# . +.- -: . +# . .+ +` . +# . .- + | `/ . +# . .." + .: . +# . -" + -- . +# . (2) ..." + | :- . +# . ..."" + -: . +# (3)- -.-.""- - - - -+++++++++ - - - - - - -.:- - - - - - - - - .- - (6) +# . + `:. . +# . + | -: . +# . + -: . +# . + .. . +# . (1) + | "+++- - - -.- - (7) +# -++++++++++++++- - - - - - - - - - - - - - - - - + - - - .- - (8) +# . + - +# -------------------------------------------------+++++++++--> +# | | | CC | CV | +# | --trickle-- | -pre- | ---------fast----------- | +# +# The charger uses the following battery properties +# - trickle-charge-current-microamp: +# Current used at trickle-charge phase (8 in above chart) +# minimum: 64000 +# maximum: 1024000 +# multipleOf: 64000 +# - precharge-current-microamp: +# Current used at pre-charge phase (6 in above chart) +# minimum: 64000 +# maximum: 1024000 +# multipleOf: 64000 +# - constant-charge-current-max-microamp +# Current used at fast charge constant current phase (5 in above chart) +# minimum: 64000 +# maximum: 1024000 +# multipleOf: 64000 +# - constant-charge-voltage-max-microvolt +# The constant voltage used in fast charging phase (4 in above chart) +# minimum: 2560000 +# maximum: 19200000 +# multipleOf: 16000 +# - precharge-upper-limit-microvolt +# charging mode is changed from trickle charging to pre-charging +# when battery voltage exceeds this limit voltage (3 in above chart) +# minimum: 2048000 +# maximum: 19200000 +# multipleOf: 64000 +# - re-charge-voltage-microvolt +# minimum: 2560000 +# maximum: 19200000 +# multipleOf: 16000 +# re-charging is automatically started when battry has been discharging +# to the point where the battery voltage drops below this limit +# - over-voltage-threshold-microvolt +# battery is expected to be faulty if battery voltage exceeds this limit. +# Charger will then enter to a "battery faulty" -state +# minimum: 2560000 +# maximum: 19200000 +# multipleOf: 16000 +# - charge-term-current-microamp +# minimum: 0 +# maximum: 1024000 +# multipleOf: 64000 +# a charge cycle terminates when the battery voltage is above recharge +# threshold, and the current is below this setting (7 in above chart) +# See also Documentation/devicetree/bindings/power/supply/battery.txt + + monitored-battery: + description: + phandle of battery characteristics devicetree node + + rohm,vsys-regulation-microvolt: + description: system specific lower limit for system voltage. + minimum: 2560000 + maximum: 19200000 + multipleOf: 64000 + + rohm,vbus-input-current-limit-microamp: + description: system specific VBUS input current limit (in microamps). + minimum: 32000 + maximum: 16352000 + multipleOf: 32000 + + rohm,vcc-input-current-limit-microamp: + description: system specific VCC/VACP input current limit (in microamps). + minimum: 32000 + maximum: 16352000 + multipleOf: 32000 + +required: + - compatible + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + charger@9 { + compatible = "rohm,bd99954"; + monitored-battery = <&battery>; + reg = <0x9>; + interrupt-parent = <&gpio1>; + interrupts = <29 8>; + rohm,vsys-regulation-microvolt = <8960000>; + rohm,vbus-input-current-limit-microamp = <1472000>; + rohm,vcc-input-current-limit-microamp = <1472000>; + }; + }; diff --git a/Bindings/power/supply/sbs,sbs-battery.yaml b/Bindings/power/supply/sbs,sbs-battery.yaml new file mode 100644 index 000000000000..a90b3601e695 --- /dev/null +++ b/Bindings/power/supply/sbs,sbs-battery.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/sbs,sbs-battery.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SBS compliant battery + +maintainers: + - Sebastian Reichel + +description: | + Battery compatible with the smart battery system specifications + +properties: + + compatible: + oneOf: + - items: + - enum: + - ti,bq20z65 + - ti,bq20z75 + - enum: + - sbs,sbs-battery + - items: + - const: sbs,sbs-battery + + reg: + maxItems: 1 + + sbs,i2c-retry-count: + description: + The number of times to retry I2C transactions on I2C IO failure. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + sbs,poll-retry-count: + description: + The number of times to try looking for new status after an external + change notification. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + sbs,battery-detect-gpios: + description: + GPIO which signals battery detection. If this is not supplied, the bus + needs to be polled to detect the battery. + maxItems: 1 + + sbs,disable-charger-broadcasts: + description: + SBS batteries by default send broadcast messages to SBS compliant chargers to + configure max. charge current/voltage. If your hardware does not have an SBS + compliant charger it should be disabled via this property to avoid blocking + the bus. Also some SBS battery fuel gauges are known to have a buggy multi- + master implementation. + type: boolean + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + battery@b { + compatible = "ti,bq20z75", "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + sbs,battery-detect-gpios = <&gpio 122 GPIO_ACTIVE_HIGH>; + sbs,disable-charger-broadcasts; + }; + }; diff --git a/Bindings/power/supply/sbs_sbs-battery.txt b/Bindings/power/supply/sbs_sbs-battery.txt deleted file mode 100644 index 4e78e51018eb..000000000000 --- a/Bindings/power/supply/sbs_sbs-battery.txt +++ /dev/null @@ -1,27 +0,0 @@ -SBS sbs-battery -~~~~~~~~~~ - -Required properties : - - compatible: ",", "sbs,sbs-battery" as fallback. The - part number compatible string might be used in order to take care of - vendor specific registers. - Known ,: - ti,bq20z75 - -Optional properties : - - sbs,i2c-retry-count : The number of times to retry i2c transactions on i2c - IO failure. - - sbs,poll-retry-count : The number of times to try looking for new status - after an external change notification. - - sbs,battery-detect-gpios : The gpio which signals battery detection and - a flag specifying its polarity. - -Example: - - battery@b { - compatible = "ti,bq20z75", "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - sbs,battery-detect-gpios = <&gpio-controller 122 1>; - } diff --git a/Bindings/property-units.txt b/Bindings/property-units.txt index e9b8360b3288..c80a110c1e26 100644 --- a/Bindings/property-units.txt +++ b/Bindings/property-units.txt @@ -41,3 +41,7 @@ Temperature Pressure ---------------------------------------- -kpascal : kilopascal + +Throughput +---------------------------------------- +-kBps : kilobytes per second diff --git a/Bindings/pwm/imx-pwm.txt b/Bindings/pwm/imx-pwm.txt deleted file mode 100644 index 22f1c3d8b773..000000000000 --- a/Bindings/pwm/imx-pwm.txt +++ /dev/null @@ -1,27 +0,0 @@ -Freescale i.MX PWM controller - -Required properties: -- compatible : should be "fsl,-pwm" and one of the following - compatible strings: - - "fsl,imx1-pwm" for PWM compatible with the one integrated on i.MX1 - - "fsl,imx27-pwm" for PWM compatible with the one integrated on i.MX27 -- reg: physical base address and length of the controller's registers -- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml - in this directory for a description of the cells format. -- clocks : Clock specifiers for both ipg and per clocks. -- clock-names : Clock names should include both "ipg" and "per" -See the clock consumer binding, - Documentation/devicetree/bindings/clock/clock-bindings.txt -- interrupts: The interrupt for the pwm controller - -Example: - -pwm1: pwm@53fb4000 { - #pwm-cells = <3>; - compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; - reg = <0x53fb4000 0x4000>; - clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, - <&clks IMX5_CLK_PWM1_HF_GATE>; - clock-names = "ipg", "per"; - interrupts = <61>; -}; diff --git a/Bindings/pwm/imx-pwm.yaml b/Bindings/pwm/imx-pwm.yaml new file mode 100644 index 000000000000..01df06777cba --- /dev/null +++ b/Bindings/pwm/imx-pwm.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/imx-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX PWM controller + +maintainers: + - Philipp Zabel + +properties: + "#pwm-cells": + description: | + Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml + in this directory for a description of the cells format. + enum: + - 2 + - 3 + + compatible: + enum: + - fsl,imx1-pwm + - fsl,imx27-pwm + + reg: + maxItems: 1 + + clocks: + items: + - description: SoC PWM ipg clock + - description: SoC PWM per clock + + clock-names: + items: + - const: ipg + - const: per + + interrupts: + maxItems: 1 + +required: + - "#pwm-cells" + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + + pwm@53fb4000 { + #pwm-cells = <3>; + compatible = "fsl,imx27-pwm"; + reg = <0x53fb4000 0x4000>; + clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, + <&clks IMX5_CLK_PWM1_HF_GATE>; + clock-names = "ipg", "per"; + interrupts = <61>; + }; diff --git a/Bindings/pwm/imx-tpm-pwm.txt b/Bindings/pwm/imx-tpm-pwm.txt deleted file mode 100644 index 5bf20950a24e..000000000000 --- a/Bindings/pwm/imx-tpm-pwm.txt +++ /dev/null @@ -1,22 +0,0 @@ -Freescale i.MX TPM PWM controller - -Required properties: -- compatible : Should be "fsl,imx7ulp-pwm". -- reg: Physical base address and length of the controller's registers. -- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format. -- clocks : The clock provided by the SoC to drive the PWM. -- interrupts: The interrupt for the PWM controller. - -Note: The TPM counter and period counter are shared between multiple channels, so all channels -should use same period setting. - -Example: - -tpm4: pwm@40250000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x40250000 0x1000>; - assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; - clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; - #pwm-cells = <3>; -}; diff --git a/Bindings/pwm/imx-tpm-pwm.yaml b/Bindings/pwm/imx-tpm-pwm.yaml new file mode 100644 index 000000000000..fe9ef42544f1 --- /dev/null +++ b/Bindings/pwm/imx-tpm-pwm.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX TPM PWM controller + +maintainers: + - Anson Huang + +description: | + The TPM counter and period counter are shared between multiple + channels, so all channels should use same period setting. + +properties: + "#pwm-cells": + const: 3 + + compatible: + enum: + - fsl,imx7ulp-pwm + + reg: + maxItems: 1 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - "#pwm-cells" + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + + pwm@40250000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x40250000 0x1000>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; + clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>; + #pwm-cells = <3>; + }; diff --git a/Bindings/pwm/mxs-pwm.txt b/Bindings/pwm/mxs-pwm.txt deleted file mode 100644 index a1b8a482f873..000000000000 --- a/Bindings/pwm/mxs-pwm.txt +++ /dev/null @@ -1,17 +0,0 @@ -Freescale MXS PWM controller - -Required properties: -- compatible: should be "fsl,imx23-pwm" -- reg: physical base address and length of the controller's registers -- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of - the cells format. -- fsl,pwm-number: the number of PWM devices - -Example: - -pwm: pwm@80064000 { - compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; - reg = <0x80064000 0x2000>; - #pwm-cells = <3>; - fsl,pwm-number = <8>; -}; diff --git a/Bindings/pwm/mxs-pwm.yaml b/Bindings/pwm/mxs-pwm.yaml new file mode 100644 index 000000000000..da68f4a25dd9 --- /dev/null +++ b/Bindings/pwm/mxs-pwm.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/mxs-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MXS PWM controller + +maintainers: + - Shawn Guo + - Anson Huang + +properties: + compatible: + enum: + - fsl,imx23-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + fsl,pwm-number: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: u32 value representing the number of PWM devices + +required: + - compatible + - reg + - "#pwm-cells" + - fsl,pwm-number + +additionalProperties: false + +examples: + - | + pwm@80064000 { + compatible = "fsl,imx23-pwm"; + reg = <0x80064000 0x2000>; + #pwm-cells = <3>; + fsl,pwm-number = <8>; + }; diff --git a/Bindings/pwm/pwm-samsung.yaml b/Bindings/pwm/pwm-samsung.yaml index ea7f32905172..fc799b0577d4 100644 --- a/Bindings/pwm/pwm-samsung.yaml +++ b/Bindings/pwm/pwm-samsung.yaml @@ -49,17 +49,17 @@ properties: are available. oneOf: - items: - - const: timers + - const: timers - items: - - const: timers - - const: pwm-tclk0 + - const: timers + - const: pwm-tclk0 - items: - - const: timers - - const: pwm-tclk1 + - const: timers + - const: pwm-tclk1 - items: - - const: timers - - const: pwm-tclk0 - - const: pwm-tclk1 + - const: timers + - const: pwm-tclk0 + - const: pwm-tclk1 interrupts: description: @@ -78,12 +78,11 @@ properties: A list of PWM channels used as PWM outputs on particular platform. It is an array of up to 5 elements being indices of PWM channels (from 0 to 4), the order does not matter. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - uniqueItems: true - - items: - minimum: 0 - maximum: 4 + $ref: /schemas/types.yaml#/definitions/uint32-array + uniqueItems: true + items: + minimum: 0 + maximum: 4 required: - clocks diff --git a/Bindings/pwm/renesas,pwm-rcar.yaml b/Bindings/pwm/renesas,pwm-rcar.yaml index 945c14e1be35..daadde9ff9c4 100644 --- a/Bindings/pwm/renesas,pwm-rcar.yaml +++ b/Bindings/pwm/renesas,pwm-rcar.yaml @@ -27,6 +27,7 @@ properties: - renesas,pwm-r8a7794 # R-Car E2 - renesas,pwm-r8a7795 # R-Car H3 - renesas,pwm-r8a7796 # R-Car M3-W + - renesas,pwm-r8a77961 # R-Car M3-W+ - renesas,pwm-r8a77965 # R-Car M3-N - renesas,pwm-r8a77970 # R-Car V3M - renesas,pwm-r8a77980 # R-Car V3H @@ -68,7 +69,7 @@ examples: pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; - reg = <0 0xe6e30000 0 0x8>; + reg = <0xe6e30000 0x8>; clocks = <&cpg CPG_MOD 523>; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; resets = <&cpg 523>; diff --git a/Bindings/regulator/anatop-regulator.txt b/Bindings/regulator/anatop-regulator.txt deleted file mode 100644 index a3106c72fbea..000000000000 --- a/Bindings/regulator/anatop-regulator.txt +++ /dev/null @@ -1,40 +0,0 @@ -Anatop Voltage regulators - -Required properties: -- compatible: Must be "fsl,anatop-regulator" -- regulator-name: A string used as a descriptive name for regulator outputs -- anatop-reg-offset: Anatop MFD register offset -- anatop-vol-bit-shift: Bit shift for the register -- anatop-vol-bit-width: Number of bits used in the register -- anatop-min-bit-val: Minimum value of this register -- anatop-min-voltage: Minimum voltage of this regulator -- anatop-max-voltage: Maximum voltage of this regulator - -Optional properties: -- anatop-delay-reg-offset: Anatop MFD step time register offset -- anatop-delay-bit-shift: Bit shift for the step time register -- anatop-delay-bit-width: Number of bits used in the step time register -- vin-supply: The supply for this regulator -- anatop-enable-bit: Regulator enable bit offset - -Any property defined as part of the core regulator -binding, defined in regulator.txt, can also be used. - -Example: - - regulator-vddpu { - compatible = "fsl,anatop-regulator"; - regulator-name = "vddpu"; - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - anatop-reg-offset = <0x140>; - anatop-vol-bit-shift = <9>; - anatop-vol-bit-width = <5>; - anatop-delay-reg-offset = <0x170>; - anatop-delay-bit-shift = <24>; - anatop-delay-bit-width = <2>; - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1300000>; - }; diff --git a/Bindings/regulator/anatop-regulator.yaml b/Bindings/regulator/anatop-regulator.yaml new file mode 100644 index 000000000000..e7b3abe30363 --- /dev/null +++ b/Bindings/regulator/anatop-regulator.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Anatop Voltage Regulators + +maintainers: + - Ying-Chun Liu (PaulLiu) + +allOf: + - $ref: "regulator.yaml#" + +properties: + compatible: + const: fsl,anatop-regulator + + regulator-name: true + + anatop-reg-offset: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: u32 value representing the anatop MFD register offset. + + anatop-vol-bit-shift: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: u32 value representing the bit shift for the register. + + anatop-vol-bit-width: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: u32 value representing the number of bits used in the register. + + anatop-min-bit-val: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: u32 value representing the minimum value of this register. + + anatop-min-voltage: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: u32 value representing the minimum voltage of this regulator. + + anatop-max-voltage: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: u32 value representing the maximum voltage of this regulator. + + anatop-delay-reg-offset: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: u32 value representing the anatop MFD step time register offset. + + anatop-delay-bit-shift: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: u32 value representing the bit shift for the step time register. + + anatop-delay-bit-width: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: u32 value representing the number of bits used in the step time register. + + anatop-enable-bit: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: u32 value representing regulator enable bit offset. + + vin-supply: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: input supply phandle. + +required: + - compatible + - regulator-name + - anatop-reg-offset + - anatop-vol-bit-shift + - anatop-vol-bit-width + - anatop-min-bit-val + - anatop-min-voltage + - anatop-max-voltage + +unevaluatedProperties: false + +examples: + - | + regulator-vddpu { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <9>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1300000>; + }; diff --git a/Bindings/regulator/arizona-regulator.txt b/Bindings/regulator/arizona-regulator.txt deleted file mode 100644 index 69bf41949b01..000000000000 --- a/Bindings/regulator/arizona-regulator.txt +++ /dev/null @@ -1,18 +0,0 @@ -Cirrus Logic Arizona class audio SoCs - -These devices are audio SoCs with extensive digital capabilities and a range -of analogue I/O. - -This document lists regulator specific bindings, see the primary binding -document: - For Wolfson Microelectronic Arizona codecs: ../mfd/arizona.txt - For Cirrus Logic Madera codecs: ../mfd/madera.txt - -Optional properties: - - wlf,ldoena : GPIO specifier for the GPIO controlling LDOENA - -Optional subnodes: - - ldo1 : Initial data for the LDO1 regulator, as covered in - Documentation/devicetree/bindings/regulator/regulator.txt - - micvdd : Initial data for the MICVDD regulator, as covered in - Documentation/devicetree/bindings/regulator/regulator.txt diff --git a/Bindings/regulator/cirrus,lochnagar.txt b/Bindings/regulator/cirrus,lochnagar.txt deleted file mode 100644 index 91974e6ee251..000000000000 --- a/Bindings/regulator/cirrus,lochnagar.txt +++ /dev/null @@ -1,82 +0,0 @@ -Cirrus Logic Lochnagar Audio Development Board - -Lochnagar is an evaluation and development board for Cirrus Logic -Smart CODEC and Amp devices. It allows the connection of most Cirrus -Logic devices on mini-cards, as well as allowing connection of -various application processor systems to provide a full evaluation -platform. Audio system topology, clocking and power can all be -controlled through the Lochnagar, allowing the device under test -to be used in a variety of possible use cases. - -This binding document describes the binding for the regulator portion -of the driver. - -Also see these documents for generic binding information: - [1] Regulator: ../regulator/regulator.txt - -This binding must be part of the Lochnagar MFD binding: - [2] ../mfd/cirrus,lochnagar.txt - -Optional sub-nodes: - - - VDDCORE : Initialisation data for the VDDCORE regulator, which - supplies the CODECs digital core if it has no build regulator for that - purpose. - Required Properties: - - compatible : One of the following strings: - "cirrus,lochnagar2-vddcore" - - SYSVDD-supply: Primary power supply for the Lochnagar. - - - MICVDD : Initialisation data for the MICVDD regulator, which - supplies the CODECs MICVDD. - Required Properties: - - compatible : One of the following strings: - "cirrus,lochnagar2-micvdd" - - SYSVDD-supply: Primary power supply for the Lochnagar. - - - MIC1VDD, MIC2VDD : Initialisation data for the MICxVDD supplies. - Required Properties: - - compatible : One of the following strings: - "cirrus,lochnagar2-mic1vdd", "cirrus,lochnagar2-mic2vdd" - Optional Properties: - - cirrus,micbias-input : A property selecting which of the CODEC - minicard micbias outputs should be used, valid values are 1 - 4. - - MICBIAS1-supply, MICBIAS2-supply: Regulator supplies for the - MICxVDD outputs, supplying the digital microphones, normally - supplied from the attached CODEC. - - - VDD1V8 : Recommended fixed regulator for the VDD1V8 regulator, which supplies the - CODECs analog and 1.8V digital supplies. - Required Properties: - - compatible : Should be set to "regulator-fixed" - - regulator-min-microvolt : Should be set to 1.8V - - regulator-max-microvolt : Should be set to 1.8V - - regulator-boot-on - - regulator-always-on - - vin-supply : Should be set to same supply as SYSVDD - -Example: - -lochnagar { - lochnagar-micvdd: MICVDD { - compatible = "cirrus,lochnagar2-micvdd"; - - SYSVDD-supply = <&wallvdd>; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - lochnagar-vdd1v8: VDD1V8 { - compatible = "regulator-fixed"; - - regulator-name = "VDD1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - - vin-supply = <&wallvdd>; - }; -}; - diff --git a/Bindings/regulator/gpio-regulator.yaml b/Bindings/regulator/gpio-regulator.yaml index 9d3b28417fb6..605590384b48 100644 --- a/Bindings/regulator/gpio-regulator.yaml +++ b/Bindings/regulator/gpio-regulator.yaml @@ -46,24 +46,22 @@ properties: 0: LOW 1: HIGH Default is LOW if nothing else is specified. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - maxItems: 8 - items: - enum: [ 0, 1 ] - default: 0 + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 8 + items: + enum: [0, 1] + default: 0 states: description: Selection of available voltages/currents provided by this regulator and matching GPIO configurations to achieve them. If there are no states in the "states" array, use a fixed regulator instead. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-matrix - - maxItems: 8 - items: - items: - - description: Voltage in microvolts - - description: GPIO group state value + $ref: /schemas/types.yaml#/definitions/uint32-matrix + maxItems: 8 + items: + items: + - description: Voltage in microvolts + - description: GPIO group state value startup-delay-us: description: startup time in microseconds @@ -81,12 +79,11 @@ properties: regulator-type: description: Specifies what is being regulated. - allOf: - - $ref: /schemas/types.yaml#/definitions/string - - enum: - - voltage - - current - default: voltage + $ref: /schemas/types.yaml#/definitions/string + enum: + - voltage + - current + default: voltage required: - compatible diff --git a/Bindings/regulator/maxim,max77826.yaml b/Bindings/regulator/maxim,max77826.yaml new file mode 100644 index 000000000000..78c0b63243f7 --- /dev/null +++ b/Bindings/regulator/maxim,max77826.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/maxim,max77826.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX77826 PMIC + +maintainers: + - Iskren Chernev + +properties: + $nodename: + pattern: "pmic@[0-9a-f]{1,2}" + compatible: + enum: + - maxim,max77826 + + reg: + maxItems: 1 + + regulators: + type: object + $ref: regulator.yaml# + description: | + list of regulators provided by this controller, must be named + after their hardware counterparts LDO[1-15], BUCK and BUCKBOOST + + patternProperties: + "^LDO([1-9]|1[0-5])$": + type: object + $ref: regulator.yaml# + + "^BUCK|BUCKBOOST$": + type: object + $ref: regulator.yaml# + + additionalProperties: false + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@69 { + compatible = "maxim,max77826"; + reg = <0x69>; + + regulators { + LDO2 { + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <3587500>; + }; + }; + }; + }; +... diff --git a/Bindings/regulator/mps,mp5416.yaml b/Bindings/regulator/mps,mp5416.yaml index 3b019fa6db31..90727fdc1283 100644 --- a/Bindings/regulator/mps,mp5416.yaml +++ b/Bindings/regulator/mps,mp5416.yaml @@ -27,13 +27,11 @@ properties: patternProperties: "^buck[1-4]$": - allOf: - - $ref: "regulator.yaml#" + $ref: "regulator.yaml#" type: object "^ldo[1-4]$": - allOf: - - $ref: "regulator.yaml#" + $ref: "regulator.yaml#" type: object additionalProperties: false diff --git a/Bindings/regulator/mps,mpq7920.yaml b/Bindings/regulator/mps,mpq7920.yaml index ae6e7ab36c58..12b8963615c3 100644 --- a/Bindings/regulator/mps,mpq7920.yaml +++ b/Bindings/regulator/mps,mpq7920.yaml @@ -21,17 +21,16 @@ properties: regulators: type: object - allOf: - - $ref: regulator.yaml# + $ref: regulator.yaml# + description: | list of regulators provided by this controller, must be named after their hardware counterparts BUCK[1-4], one LDORTC, and LDO[2-5] properties: mps,switch-freq: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint8" - enum: [ 0, 1, 2, 3 ] + $ref: "/schemas/types.yaml#/definitions/uint8" + enum: [0, 1, 2, 3] default: 2 description: | switching frequency must be one of following corresponding value @@ -40,32 +39,27 @@ properties: patternProperties: "^ldo[1-4]$": type: object - allOf: - - $ref: regulator.yaml# + $ref: regulator.yaml# "^ldortc$": type: object - allOf: - - $ref: regulator.yaml# + $ref: regulator.yaml# "^buck[1-4]$": type: object - allOf: - - $ref: regulator.yaml# + $ref: regulator.yaml# properties: mps,buck-softstart: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint8" - enum: [ 0, 1, 2, 3 ] + $ref: "/schemas/types.yaml#/definitions/uint8" + enum: [0, 1, 2, 3] description: | defines the soft start time of this buck, must be one of the following corresponding values 150us, 300us, 610us, 920us mps,buck-phase-delay: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint8" - enum: [ 0, 1, 2, 3 ] + $ref: "/schemas/types.yaml#/definitions/uint8" + enum: [0, 1, 2, 3] description: | defines the phase delay of this buck, must be one of the following corresponding values 0deg, 90deg, 180deg, 270deg diff --git a/Bindings/regulator/regulator.yaml b/Bindings/regulator/regulator.yaml index 91a39a33000b..ec505dbbf87c 100644 --- a/Bindings/regulator/regulator.yaml +++ b/Bindings/regulator/regulator.yaml @@ -123,9 +123,8 @@ properties: 0: Disable active discharge. 1: Enable active discharge. Absence of this property will leave configuration to default. - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - enum: [ 0, 1 ] + $ref: "/schemas/types.yaml#/definitions/uint32" + enum: [0, 1] regulator-coupled-with: description: Regulators with which the regulator is coupled. The linkage diff --git a/Bindings/regulator/rohm,bd71828-regulator.yaml b/Bindings/regulator/rohm,bd71828-regulator.yaml index 1e52dafcb5c9..5ce587fff961 100644 --- a/Bindings/regulator/rohm,bd71828-regulator.yaml +++ b/Bindings/regulator/rohm,bd71828-regulator.yaml @@ -24,10 +24,9 @@ description: | patternProperties: "^LDO[1-7]$": type: object - allOf: - - $ref: regulator.yaml# description: Properties for single LDO regulator. + $ref: regulator.yaml# properties: regulator-name: @@ -39,10 +38,9 @@ patternProperties: "^BUCK[1-7]$": type: object - allOf: - - $ref: regulator.yaml# description: Properties for single BUCK regulator. + $ref: regulator.yaml# properties: regulator-name: @@ -51,40 +49,36 @@ patternProperties: should be "buck1", ..., "buck7" rohm,dvs-run-voltage: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - maximum: 3300000 description: PMIC default "RUN" state voltage in uV. See below table for bucks which support this. 0 means disabled. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 3300000 rohm,dvs-idle-voltage: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - maximum: 3300000 description: PMIC default "IDLE" state voltage in uV. See below table for bucks which support this. 0 means disabled. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 3300000 rohm,dvs-suspend-voltage: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - maximum: 3300000 description: PMIC default "SUSPEND" state voltage in uV. See below table for bucks which support this. 0 means disabled. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 3300000 rohm,dvs-lpsr-voltage: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - maximum: 3300000 description: PMIC default "LPSR" state voltage in uV. See below table for bucks which support this. 0 means disabled. + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 3300000 # Supported default DVS states: # buck | run | idle | suspend | lpsr diff --git a/Bindings/regulator/rohm,bd71837-regulator.yaml b/Bindings/regulator/rohm,bd71837-regulator.yaml index 543d4b52397e..19d9408d9c3b 100644 --- a/Bindings/regulator/rohm,bd71837-regulator.yaml +++ b/Bindings/regulator/rohm,bd71837-regulator.yaml @@ -30,8 +30,7 @@ description: | patternProperties: "^LDO[1-7]$": type: object - allOf: - - $ref: regulator.yaml# + $ref: regulator.yaml# description: Properties for single LDO regulator. @@ -45,8 +44,7 @@ patternProperties: "^BUCK[1-8]$": type: object - allOf: - - $ref: regulator.yaml# + $ref: regulator.yaml# description: Properties for single BUCK regulator. @@ -57,28 +55,25 @@ patternProperties: should be "buck1", ..., "buck8" rohm,dvs-run-voltage: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - maximum: 1300000 + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 1300000 description: PMIC default "RUN" state voltage in uV. See below table for bucks which support this. 0 means disabled. rohm,dvs-idle-voltage: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - maximum: 1300000 + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 1300000 description: PMIC default "IDLE" state voltage in uV. See below table for bucks which support this. 0 means disabled. rohm,dvs-suspend-voltage: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - maximum: 1300000 + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 1300000 description: PMIC default "SUSPEND" state voltage in uV. See below table for bucks which support this. 0 means disabled. diff --git a/Bindings/regulator/rohm,bd71847-regulator.yaml b/Bindings/regulator/rohm,bd71847-regulator.yaml index d797cc23406f..07256a4b50b9 100644 --- a/Bindings/regulator/rohm,bd71847-regulator.yaml +++ b/Bindings/regulator/rohm,bd71847-regulator.yaml @@ -29,8 +29,7 @@ description: | patternProperties: "^LDO[1-6]$": type: object - allOf: - - $ref: regulator.yaml# + $ref: regulator.yaml# description: Properties for single LDO regulator. @@ -44,8 +43,7 @@ patternProperties: "^BUCK[1-6]$": type: object - allOf: - - $ref: regulator.yaml# + $ref: regulator.yaml# description: Properties for single BUCK regulator. @@ -56,28 +54,25 @@ patternProperties: should be "buck1", ..., "buck6" rohm,dvs-run-voltage: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - maximum: 1300000 + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 1300000 description: PMIC default "RUN" state voltage in uV. See below table for bucks which support this. 0 means disabled. rohm,dvs-idle-voltage: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - maximum: 1300000 + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 1300000 description: PMIC default "IDLE" state voltage in uV. See below table for bucks which support this. 0 means disabled. rohm,dvs-suspend-voltage: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - maximum: 1300000 + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 1300000 description: PMIC default "SUSPEND" state voltage in uV. See below table for bucks which support this. 0 means disabled. diff --git a/Bindings/regulator/st,stm32-booster.yaml b/Bindings/regulator/st,stm32-booster.yaml index 64f1183ce841..cb336b2c16af 100644 --- a/Bindings/regulator/st,stm32-booster.yaml +++ b/Bindings/regulator/st,stm32-booster.yaml @@ -23,8 +23,7 @@ properties: - st,stm32mp1-booster st,syscfg: - allOf: - - $ref: "/schemas/types.yaml#/definitions/phandle-array" + $ref: "/schemas/types.yaml#/definitions/phandle-array" description: phandle to system configuration controller. vdda-supply: diff --git a/Bindings/regulator/st,stm32mp1-pwr-reg.yaml b/Bindings/regulator/st,stm32mp1-pwr-reg.yaml index 8d8f38fe85dc..e6322bc3e447 100644 --- a/Bindings/regulator/st,stm32mp1-pwr-reg.yaml +++ b/Bindings/regulator/st,stm32mp1-pwr-reg.yaml @@ -26,8 +26,7 @@ patternProperties: "^(reg11|reg18|usb33)$": type: object - allOf: - - $ref: "regulator.yaml#" + $ref: "regulator.yaml#" required: - compatible diff --git a/Bindings/regulator/wlf,arizona.yaml b/Bindings/regulator/wlf,arizona.yaml new file mode 100644 index 000000000000..a0aea73bf412 --- /dev/null +++ b/Bindings/regulator/wlf,arizona.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/wlf,arizona.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic/Wolfson Microelectronics Arizona/Madera class audio SoCs + +maintainers: + - patches@opensource.cirrus.com + +description: | + These devices are audio SoCs with extensive digital capabilities and a + range of analogue I/O. + + This document lists regulator specific bindings, see the primary binding + document. For Wolfson Microelectronic Arizona codecs ../mfd/wlf,arizona.yaml + and for Cirrus Logic Madera codecs ../mfd/madera.txt + +properties: + wlf,ldoena: + description: + GPIO specifier for the GPIO controlling LDOENA. + $ref: "/schemas/types.yaml#/definitions/phandle-array" + maxItems: 1 + + ldo1: + description: + Initial data for the LDO1 regulator. + $ref: "regulator.yaml#" + type: object + + micvdd: + description: + Initial data for the MICVDD regulator. + $ref: "regulator.yaml#" + type: object diff --git a/Bindings/remoteproc/ingenic,vpu.yaml b/Bindings/remoteproc/ingenic,vpu.yaml new file mode 100644 index 000000000000..c019f9fbe916 --- /dev/null +++ b/Bindings/remoteproc/ingenic,vpu.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/remoteproc/ingenic,vpu.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Ingenic Video Processing Unit bindings + +description: + Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from + Ingenic is a second Xburst MIPS CPU very similar to the main core. + This document describes the devicetree bindings for this auxiliary + processor. + +maintainers: + - Paul Cercueil + +properties: + compatible: + const: ingenic,jz4770-vpu-rproc + + reg: + items: + - description: aux registers + - description: tcsm0 registers + - description: tcsm1 registers + - description: sram registers + + reg-names: + items: + - const: aux + - const: tcsm0 + - const: tcsm1 + - const: sram + + clocks: + items: + - description: aux clock + - description: vpu clock + + clock-names: + items: + - const: aux + - const: vpu + + interrupts: + description: VPU hardware interrupt + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + + vpu: video-decoder@132a0000 { + compatible = "ingenic,jz4770-vpu-rproc"; + + reg = <0x132a0000 0x20>, /* AUX */ + <0x132b0000 0x4000>, /* TCSM0 */ + <0x132c0000 0xc000>, /* TCSM1 */ + <0x132f0000 0x7000>; /* SRAM */ + reg-names = "aux", "tcsm0", "tcsm1", "sram"; + + clocks = <&cgu JZ4770_CLK_AUX>, <&cgu JZ4770_CLK_VPU>; + clock-names = "aux", "vpu"; + + interrupt-parent = <&cpuintc>; + interrupts = <3>; + }; diff --git a/Bindings/remoteproc/qcom,adsp.txt b/Bindings/remoteproc/qcom,adsp.txt index 9938918b2fea..54737024da20 100644 --- a/Bindings/remoteproc/qcom,adsp.txt +++ b/Bindings/remoteproc/qcom,adsp.txt @@ -15,12 +15,16 @@ on the Qualcomm ADSP Hexagon core. "qcom,qcs404-adsp-pas" "qcom,qcs404-cdsp-pas" "qcom,qcs404-wcss-pas" + "qcom,sc7180-mpss-pas" "qcom,sdm845-adsp-pas" "qcom,sdm845-cdsp-pas" "qcom,sm8150-adsp-pas" "qcom,sm8150-cdsp-pas" "qcom,sm8150-mpss-pas" "qcom,sm8150-slpi-pas" + "qcom,sm8250-adsp-pas" + "qcom,sm8250-cdsp-pas" + "qcom,sm8250-slpi-pas" - interrupts-extended: Usage: required @@ -44,8 +48,12 @@ on the Qualcomm ADSP Hexagon core. qcom,sm8150-adsp-pas: qcom,sm8150-cdsp-pas: qcom,sm8150-slpi-pas: + qcom,sm8250-adsp-pas: + qcom,sm8250-cdsp-pas: + qcom,sm8250-slpi-pas: must be "wdog", "fatal", "ready", "handover", "stop-ack" qcom,qcs404-wcss-pas: + qcom,sc7180-mpss-pas: qcom,sm8150-mpss-pas: must be "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack" @@ -105,10 +113,14 @@ on the Qualcomm ADSP Hexagon core. qcom,sdm845-cdsp-pas: qcom,sm8150-adsp-pas: qcom,sm8150-cdsp-pas: + qcom,sm8250-cdsp-pas: must be "cx", "load_state" + qcom,sc7180-mpss-pas: qcom,sm8150-mpss-pas: must be "cx", "load_state", "mss" + qcom,sm8250-adsp-pas: qcom,sm8150-slpi-pas: + qcom,sm8250-slpi-pas: must be "lcx", "lmx", "load_state" - memory-region: diff --git a/Bindings/remoteproc/qcom,q6v5.txt b/Bindings/remoteproc/qcom,q6v5.txt index 88dfa3fc15f7..1f9a62e13ebe 100644 --- a/Bindings/remoteproc/qcom,q6v5.txt +++ b/Bindings/remoteproc/qcom,q6v5.txt @@ -79,7 +79,7 @@ on the Qualcomm Hexagon core. "snoc_axi", "mnoc_axi", "qdss" qcom,sc7180-mss-pil: must be "iface", "bus", "xo", "snoc_axi", "mnoc_axi", - "mss_crypto", "mss_nav", "nav" + "nav" qcom,sdm845-mss-pil: must be "iface", "bus", "mem", "xo", "gpll0_mss", "snoc_axi", "mnoc_axi", "prng" @@ -102,6 +102,14 @@ on the Qualcomm Hexagon core. must be "mss_restart", "pdc_reset" for the modem sub-system on SC7180, SDM845 SoCs +For devices where the mba and mpss sub-nodes are not specified, mba/mpss region +should be referenced as follows: +- memory-region: + Usage: required + Value type: + Definition: reference to the reserved-memory for the mba region followed + by the mpss region + For the compatible strings below the following supplies are required: "qcom,q6v5-pil" "qcom,msm8916-mss-pil", @@ -173,16 +181,15 @@ For the compatible string below the following supplies are required: For the compatible strings below the following phandle references are required: "qcom,sc7180-mss-pil" -- qcom,halt-nav-regs: +- qcom,spare-regs: Usage: required Value type: - Definition: reference to a list of 2 phandles with one offset each for - the modem sub-system running on SC7180 SoC. The first - phandle reference is to the mss clock node followed by the - offset within register space for nav halt register. The - second phandle reference is to a syscon representing TCSR - followed by the offset within syscon for conn_box_spare0 - register. + Definition: a phandle reference to a syscon representing TCSR followed + by the offset within syscon for conn_box_spare0 register + used by the modem sub-system running on SC7180 SoC. + +The Hexagon node must contain iommus property as described in ../iommu/iommu.txt +on platforms which do not have TrustZone. = SUBNODES: The Hexagon node must contain two subnodes, named "mba" and "mpss" representing diff --git a/Bindings/remoteproc/st,stm32-rproc.yaml b/Bindings/remoteproc/st,stm32-rproc.yaml index c0d83865e933..4ffa25268fcc 100644 --- a/Bindings/remoteproc/st,stm32-rproc.yaml +++ b/Bindings/remoteproc/st,stm32-rproc.yaml @@ -25,25 +25,23 @@ properties: maxItems: 3 resets: - maxItems: 1 + maxItems: 1 st,syscfg-holdboot: - allOf: - - $ref: "/schemas/types.yaml#/definitions/phandle-array" description: remote processor reset hold boot - Phandle of syscon block. - The offset of the hold boot setting register. - The field mask of the hold boot. + $ref: "/schemas/types.yaml#/definitions/phandle-array" maxItems: 1 st,syscfg-tz: - allOf: - - $ref: "/schemas/types.yaml#/definitions/phandle-array" description: Reference to the system configuration which holds the RCC trust zone mode - Phandle of syscon block. - The offset of the RCC trust zone mode register. - The field mask of the RCC trust zone mode. + $ref: "/schemas/types.yaml#/definitions/phandle-array" maxItems: 1 interrupts: @@ -90,8 +88,7 @@ properties: (see ../reserved-memory/reserved-memory.txt) st,syscfg-pdds: - allOf: - - $ref: "/schemas/types.yaml#/definitions/phandle-array" + $ref: "/schemas/types.yaml#/definitions/phandle-array" description: | Reference to the system configuration which holds the remote 1st cell: phandle to syscon block diff --git a/Bindings/reserved-memory/ramoops.txt b/Bindings/reserved-memory/ramoops.txt index 0eba562fe5c6..b7886fea368c 100644 --- a/Bindings/reserved-memory/ramoops.txt +++ b/Bindings/reserved-memory/ramoops.txt @@ -30,7 +30,7 @@ Optional properties: - ecc-size: enables ECC support and specifies ECC buffer size in bytes (defaults to 0: no ECC) -- record-size: maximum size in bytes of each dump done on oops/panic +- record-size: maximum size in bytes of each kmsg dump. (defaults to 0: disabled) - console-size: size in bytes of log buffer reserved for kernel messages @@ -45,7 +45,16 @@ Optional properties: - unbuffered: if present, use unbuffered mappings to map the reserved region (defaults to buffered mappings) -- no-dump-oops: if present, only dump panics (defaults to panics and oops) +- max-reason: if present, sets maximum type of kmsg dump reasons to store + (defaults to 2: log Oopses and Panics). This can be set to INT_MAX to + store all kmsg dumps. See include/linux/kmsg_dump.h KMSG_DUMP_* for other + kmsg dump reason values. Setting this to 0 (KMSG_DUMP_UNDEF), means the + reason filtering will be controlled by the printk.always_kmsg_dump boot + param: if unset, it will be KMSG_DUMP_OOPS, otherwise KMSG_DUMP_MAX. + +- no-dump-oops: deprecated, use max_reason instead. If present, and + max_reason is not specified, it is equivalent to max_reason = 1 + (KMSG_DUMP_PANIC). - flags: if present, pass ramoops behavioral flags (defaults to 0, see include/linux/pstore_ram.h RAMOOPS_FLAG_* for flag values). diff --git a/Bindings/reserved-memory/reserved-memory.txt b/Bindings/reserved-memory/reserved-memory.txt index bac4afa3b197..4dd20de6977f 100644 --- a/Bindings/reserved-memory/reserved-memory.txt +++ b/Bindings/reserved-memory/reserved-memory.txt @@ -77,6 +77,8 @@ Regions in the /reserved-memory node may be referenced by other device nodes by adding a memory-region property to the device node. memory-region (optional) - phandle, specifier pairs to children of /reserved-memory +memory-region-names (optional) - a list of names, one for each corresponding + entry in the memory-region property Example ------- diff --git a/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml b/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml index 512a33bdb208..dfce6738b033 100644 --- a/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml +++ b/Bindings/reset/brcm,bcm7216-pcie-sata-rescal.yaml @@ -7,7 +7,9 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: BCM7216 RESCAL reset controller -description: This document describes the BCM7216 RESCAL reset controller which is responsible for controlling the reset of the SATA and PCIe0/1 instances on BCM7216. +description: This document describes the BCM7216 RESCAL reset controller + which is responsible for controlling the reset of the SATA and PCIe0/1 + instances on BCM7216. maintainers: - Florian Fainelli diff --git a/Bindings/reset/fsl,imx7-src.txt b/Bindings/reset/fsl,imx7-src.txt index c2489e41a801..e10502d9153e 100644 --- a/Bindings/reset/fsl,imx7-src.txt +++ b/Bindings/reset/fsl,imx7-src.txt @@ -9,6 +9,8 @@ Required properties: - For i.MX7 SoCs should be "fsl,imx7d-src", "syscon" - For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon" - For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon" + - For i.MX8MN SoCs should be "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon" + - For i.MX8MP SoCs should be "fsl,imx8mp-src", "syscon" - reg: should be register base and length as documented in the datasheet - interrupts: Should contain SRC interrupt @@ -49,4 +51,6 @@ Example: For list of all valid reset indices see for i.MX7, for i.MX8MQ and - for i.MX8MM + for i.MX8MM and + for i.MX8MN and + for i.MX8MP diff --git a/Bindings/reset/intel,rcu-gw.yaml b/Bindings/reset/intel,rcu-gw.yaml index 8ac437282659..6b2d56cc3f38 100644 --- a/Bindings/reset/intel,rcu-gw.yaml +++ b/Bindings/reset/intel,rcu-gw.yaml @@ -21,8 +21,7 @@ properties: intel,global-reset: description: Global reset register offset and bit offset. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-array items: - description: Register offset - description: Register bit offset diff --git a/Bindings/reset/renesas,rst.yaml b/Bindings/reset/renesas,rst.yaml index b5de1d196a13..4c2b429ac702 100644 --- a/Bindings/reset/renesas,rst.yaml +++ b/Bindings/reset/renesas,rst.yaml @@ -23,6 +23,7 @@ description: | properties: compatible: enum: + - renesas,r8a7742-rst # RZ/G1H - renesas,r8a7743-rst # RZ/G1M - renesas,r8a7744-rst # RZ/G1N - renesas,r8a7745-rst # RZ/G1E diff --git a/Bindings/riscv/cpus.yaml b/Bindings/riscv/cpus.yaml index 04819ad379c2..f80ba2c66f71 100644 --- a/Bindings/riscv/cpus.yaml +++ b/Bindings/riscv/cpus.yaml @@ -40,24 +40,18 @@ properties: and identifies the type of the hart. mmu-type: - allOf: - - $ref: "/schemas/types.yaml#/definitions/string" - - enum: - - riscv,sv32 - - riscv,sv39 - - riscv,sv48 description: Identifies the MMU address translation mode used on this hart. These values originate from the RISC-V Privileged Specification document, available from https://riscv.org/specifications/ + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - riscv,sv32 + - riscv,sv39 + - riscv,sv48 riscv,isa: - allOf: - - $ref: "/schemas/types.yaml#/definitions/string" - - enum: - - rv64imac - - rv64imafdc description: Identifies the specific RISC-V instruction set architecture supported by the hart. These are documented in the RISC-V @@ -67,6 +61,10 @@ properties: While the isa strings in ISA specification are case insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - rv64imac + - rv64imafdc # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false diff --git a/Bindings/rng/arm-cctrng.yaml b/Bindings/rng/arm-cctrng.yaml new file mode 100644 index 000000000000..c471e4c10558 --- /dev/null +++ b/Bindings/rng/arm-cctrng.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/arm-cctrng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm TrustZone CryptoCell TRNG engine + +maintainers: + - Hadar Gat + +description: |+ + Arm TrustZone CryptoCell TRNG (True Random Number Generator) engine. + +properties: + compatible: + enum: + - arm,cryptocell-713-trng + - arm,cryptocell-703-trng + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + arm,rosc-ratio: + description: + Arm TrustZone CryptoCell TRNG engine has 4 ring oscillators. + Sampling ratio values for these 4 ring oscillators. (from calibration) + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 4 + + clocks: + maxItems: 1 + +required: + - compatible + - interrupts + - reg + - arm,rosc-ratio + +additionalProperties: false + +examples: + - | + arm_cctrng: rng@60000000 { + compatible = "arm,cryptocell-713-trng"; + interrupts = <0 29 4>; + reg = <0x60000000 0x10000>; + arm,rosc-ratio = <5000 1000 500 0>; + }; diff --git a/Bindings/rtc/dw-apb.txt b/Bindings/rtc/dw-apb.txt deleted file mode 100644 index c703d51abb6c..000000000000 --- a/Bindings/rtc/dw-apb.txt +++ /dev/null @@ -1,32 +0,0 @@ -* Designware APB timer - -Required properties: -- compatible: One of: - "snps,dw-apb-timer" - "snps,dw-apb-timer-sp" - "snps,dw-apb-timer-osc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: IRQ line for the timer. -- either clocks+clock-names or clock-frequency properties - -Optional properties: -- clocks : list of clock specifiers, corresponding to entries in - the clock-names property; -- clock-names : should contain "timer" and "pclk" entries, matching entries - in the clocks property. -- clock-frequency: The frequency in HZ of the timer. -- clock-freq: For backwards compatibility with picoxcell - -If using the clock specifiers, the pclk clock is optional, as not all -systems may use one. - - -Example: - timer@ffe00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 170 4>; - reg = <0xffe00000 0x1000>; - clocks = <&timer_clk>, <&timer_pclk>; - clock-names = "timer", "pclk"; - }; diff --git a/Bindings/rtc/renesas,sh-rtc.yaml b/Bindings/rtc/renesas,sh-rtc.yaml index b95cb017f469..eff9df4b856a 100644 --- a/Bindings/rtc/renesas,sh-rtc.yaml +++ b/Bindings/rtc/renesas,sh-rtc.yaml @@ -43,6 +43,9 @@ properties: items: enum: [ fck, rtc_x1, rtc_x3, extal ] + power-domains: + maxItems: 1 + required: - compatible - reg @@ -50,6 +53,7 @@ required: - interrupt-names - clocks - clock-names + - power-domains additionalProperties: false @@ -68,5 +72,6 @@ examples: interrupt-names = "alarm", "period", "carry"; clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>, <&rtc_x3_clk>, <&extal_clk>; + power-domains = <&cpg_clocks>; clock-names = "fck", "rtc_x1", "rtc_x3", "extal"; }; diff --git a/Bindings/rtc/rtc-mxc.txt b/Bindings/rtc/rtc-mxc.txt deleted file mode 100644 index 5bcd31d995b0..000000000000 --- a/Bindings/rtc/rtc-mxc.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Real Time Clock of the i.MX SoCs - -RTC controller for the i.MX SoCs - -Required properties: -- compatible: Should be "fsl,imx1-rtc" or "fsl,imx21-rtc". -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: IRQ line for the RTC. -- clocks: should contain two entries: - * one for the input reference - * one for the the SoC RTC -- clock-names: should contain: - * "ref" for the input reference clock - * "ipg" for the SoC RTC clock - -Example: - -rtc@10007000 { - compatible = "fsl,imx21-rtc"; - reg = <0x10007000 0x1000>; - interrupts = <22>; - clocks = <&clks IMX27_CLK_CKIL>, - <&clks IMX27_CLK_RTC_IPG_GATE>; - clock-names = "ref", "ipg"; -}; diff --git a/Bindings/rtc/rtc-mxc.yaml b/Bindings/rtc/rtc-mxc.yaml new file mode 100644 index 000000000000..4f263fa6fd0d --- /dev/null +++ b/Bindings/rtc/rtc-mxc.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/rtc-mxc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Real Time Clock of the i.MX SoCs + +allOf: + - $ref: "rtc.yaml#" + +maintainers: + - Philippe Reynes + +properties: + compatible: + enum: + - fsl,imx1-rtc + - fsl,imx21-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: input reference + - description: the SoC RTC clock + + clock-names: + items: + - const: ref + - const: ipg + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + rtc@10007000 { + compatible = "fsl,imx21-rtc"; + reg = <0x10007000 0x1000>; + interrupts = <22>; + clocks = <&clks IMX27_CLK_CKIL>, + <&clks IMX27_CLK_RTC_IPG_GATE>; + clock-names = "ref", "ipg"; + }; diff --git a/Bindings/rtc/rtc-mxc_v2.txt b/Bindings/rtc/rtc-mxc_v2.txt deleted file mode 100644 index 79d7e87b0d91..000000000000 --- a/Bindings/rtc/rtc-mxc_v2.txt +++ /dev/null @@ -1,17 +0,0 @@ -* i.MX53 Secure Real Time Clock (SRTC) - -Required properties: -- compatible: should be: "fsl,imx53-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: should contain the phandle for the rtc clock -- interrupts: rtc alarm interrupt - -Example: - -rtc@53fa4000 { - compatible = "fsl,imx53-rtc"; - reg = <0x53fa4000 0x4000>; - interrupts = <24>; - clocks = <&clks IMX5_CLK_SRTC_GATE>; -}; diff --git a/Bindings/rtc/rtc-mxc_v2.yaml b/Bindings/rtc/rtc-mxc_v2.yaml new file mode 100644 index 000000000000..2d1a30663d72 --- /dev/null +++ b/Bindings/rtc/rtc-mxc_v2.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/rtc-mxc_v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX53 Secure Real Time Clock (SRTC) + +allOf: + - $ref: "rtc.yaml#" + +maintainers: + - Patrick Bruenn + +properties: + compatible: + enum: + - fsl,imx53-rtc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + #include + + rtc@53fa4000 { + compatible = "fsl,imx53-rtc"; + reg = <0x53fa4000 0x4000>; + interrupts = <24>; + clocks = <&clks IMX5_CLK_SRTC_GATE>; + }; diff --git a/Bindings/rtc/st,stm32-rtc.yaml b/Bindings/rtc/st,stm32-rtc.yaml index 48c6cafca90c..5456604b1c14 100644 --- a/Bindings/rtc/st,stm32-rtc.yaml +++ b/Bindings/rtc/st,stm32-rtc.yaml @@ -32,16 +32,15 @@ properties: maxItems: 1 st,syscfg: - allOf: - - $ref: "/schemas/types.yaml#/definitions/phandle-array" - - items: - minItems: 3 - maxItems: 3 + $ref: "/schemas/types.yaml#/definitions/phandle-array" + items: + minItems: 3 + maxItems: 3 description: | - Phandle/offset/mask triplet. The phandle to pwrcfg used to - access control register at offset, and change the dbp (Disable Backup - Protection) bit represented by the mask, mandatory to disable/enable backup - domain (RTC registers) write protection. + Phandle/offset/mask triplet. The phandle to pwrcfg used to + access control register at offset, and change the dbp (Disable Backup + Protection) bit represented by the mask, mandatory to disable/enable backup + domain (RTC registers) write protection. assigned-clocks: description: | @@ -78,14 +77,14 @@ allOf: const: st,stm32h7-rtc then: - properties: - clocks: - minItems: 2 - maxItems: 2 + properties: + clocks: + minItems: 2 + maxItems: 2 - required: - - clock-names - - st,syscfg + required: + - clock-names + - st,syscfg - if: properties: @@ -94,16 +93,16 @@ allOf: const: st,stm32mp1-rtc then: - properties: - clocks: - minItems: 2 - maxItems: 2 + properties: + clocks: + minItems: 2 + maxItems: 2 - assigned-clocks: false - assigned-clock-parents: false + assigned-clocks: false + assigned-clock-parents: false - required: - - clock-names + required: + - clock-names required: - compatible diff --git a/Bindings/serial/8250.txt b/Bindings/serial/8250.txt deleted file mode 100644 index 55700f20f6ee..000000000000 --- a/Bindings/serial/8250.txt +++ /dev/null @@ -1,100 +0,0 @@ -* UART (Universal Asynchronous Receiver/Transmitter) - -Required properties: -- compatible : one of: - - "ns8250" - - "ns16450" - - "ns16550a" - - "ns16550" - - "ns16750" - - "ns16850" - - For Tegra20, must contain "nvidia,tegra20-uart" - - For other Tegra, must contain '"nvidia,-uart", - "nvidia,tegra20-uart"' where is tegra30, tegra114, tegra124, - tegra132, or tegra210. - - "nxp,lpc3220-uart" - - "ralink,rt2880-uart" - - For MediaTek BTIF, must contain '"mediatek,-btif", - "mediatek,mtk-btif"' where is mt7622, mt7623. - - "altr,16550-FIFO32" - - "altr,16550-FIFO64" - - "altr,16550-FIFO128" - - "fsl,16550-FIFO64" - - "fsl,ns16550" - - "intel,xscale-uart" - - "ti,da830-uart" - - "aspeed,ast2400-vuart" - - "aspeed,ast2500-vuart" - - "nuvoton,npcm750-uart" - - "serial" if the port type is unknown. -- reg : offset and length of the register set for the device. -- interrupts : should contain uart interrupt. -- clock-frequency : the input clock frequency for the UART - or - clocks phandle to refer to the clk used as per Documentation/devicetree - /bindings/clock/clock-bindings.txt - -Optional properties: -- current-speed : the current active speed of the UART. -- reg-offset : offset to apply to the mapbase from the start of the registers. -- reg-shift : quantity to shift the register offsets by. -- reg-io-width : the size (in bytes) of the IO accesses that should be - performed on the device. There are some systems that require 32-bit - accesses to the UART (e.g. TI davinci). -- used-by-rtas : set to indicate that the port is in use by the OpenFirmware - RTAS and should not be registered. -- no-loopback-test: set to indicate that the port does not implements loopback - test mode -- fifo-size: the fifo size of the UART. -- auto-flow-control: one way to enable automatic flow control support. The - driver is allowed to detect support for the capability even without this - property. -- tx-threshold: Specify the TX FIFO low water indication for parts with - programmable TX FIFO thresholds. -- resets : phandle + reset specifier pairs -- overrun-throttle-ms : how long to pause uart rx when input overrun is encountered. -- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD - line respectively. It will use specified GPIO instead of the peripheral - function pin for the UART feature. If unsure, don't specify this property. -- aspeed,sirq-polarity-sense: Only applicable to aspeed,ast2500-vuart. - phandle to aspeed,ast2500-scu compatible syscon alongside register offset - and bit number to identify how the SIRQ polarity should be configured. - One possible data source is the LPC/eSPI mode bit. - Example: aspeed,sirq-polarity-sense = <&syscon 0x70 25> - -Note: -* fsl,ns16550: - ------------ - Freescale DUART is very similar to the PC16552D (and to a - pair of NS16550A), albeit with some nonstandard behavior such as - erratum A-004737 (relating to incorrect BRK handling). - - Represents a single port that is compatible with the DUART found - on many Freescale chips (examples include mpc8349, mpc8548, - mpc8641d, p4080 and ls2085a). - -Example: - - uart@80230000 { - compatible = "ns8250"; - reg = <0x80230000 0x100>; - clock-frequency = <3686400>; - interrupts = <10>; - reg-shift = <2>; - }; - -Example for OMAP UART using GPIO-based modem control signals: - - uart4: serial@49042000 { - compatible = "ti,omap3-uart"; - reg = <0x49042000 0x400>; - interrupts = <80>; - ti,hwmods = "uart4"; - clock-frequency = <48000000>; - cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; - dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - }; diff --git a/Bindings/serial/8250.yaml b/Bindings/serial/8250.yaml new file mode 100644 index 000000000000..c1d4c196f005 --- /dev/null +++ b/Bindings/serial/8250.yaml @@ -0,0 +1,233 @@ +# Copyright 2020 Lubomir Rintel +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/8250.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UART (Universal Asynchronous Receiver/Transmitter) bindings + +maintainers: + - devicetree@vger.kernel.org + +allOf: + - $ref: /schemas/serial.yaml# + - if: + required: + - aspeed,sirq-polarity-sense + then: + properties: + compatible: + const: aspeed,ast2500-vuart + - if: + properties: + compatible: + const: mrvl,mmp-uart + then: + properties: + reg-shift: + const: 2 + required: + - reg-shift + - if: + not: + properties: + compatible: + items: + - enum: + - ns8250 + - ns16450 + - ns16550 + - ns16550a + then: + anyOf: + - required: [ clock-frequency ] + - required: [ clocks ] + +properties: + compatible: + oneOf: + - const: ns8250 + - const: ns16450 + - const: ns16550 + - const: ns16550a + - const: ns16850 + - const: aspeed,ast2400-vuart + - const: aspeed,ast2500-vuart + - const: intel,xscale-uart + - const: mrvl,pxa-uart + - const: nuvoton,npcm750-uart + - const: nvidia,tegra20-uart + - const: nxp,lpc3220-uart + - items: + - enum: + - altr,16550-FIFO32 + - altr,16550-FIFO64 + - altr,16550-FIFO128 + - fsl,16550-FIFO64 + - fsl,ns16550 + - andestech,uart16550 + - nxp,lpc1850-uart + - opencores,uart16550-rtlsvn105 + - ti,da830-uart + - const: ns16550a + - items: + - enum: + - ns16750 + - cavium,octeon-3860-uart + - xlnx,xps-uart16550-2.00.b + - ralink,rt2880-uart + - enum: + - ns16550 # Deprecated, unless the FIFO really is broken + - ns16550a + - items: + - enum: + - ralink,mt7620a-uart + - ralink,rt3052-uart + - ralink,rt3883-uart + - const: ralink,rt2880-uart + - enum: + - ns16550 # Deprecated, unless the FIFO really is broken + - ns16550a + - items: + - enum: + - mediatek,mt7622-btif + - mediatek,mt7623-btif + - const: mediatek,mtk-btif + - items: + - enum: + - mediatek,mt7622-btif + - mediatek,mt7623-btif + - const: mediatek,mtk-btif + - items: + - const: mrvl,mmp-uart + - const: intel,xscale-uart + - items: + - enum: + - nvidia,tegra30-uart + - nvidia,tegra114-uart + - nvidia,tegra124-uart + - nvidia,tegra186-uart + - nvidia,tegra194-uart + - nvidia,tegra210-uart + - const: nvidia,tegra20-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-frequency: true + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + current-speed: + $ref: /schemas/types.yaml#definitions/uint32 + description: The current active speed of the UART. + + reg-offset: + description: | + Offset to apply to the mapbase from the start of the registers. + + reg-shift: + description: Quantity to shift the register offsets by. + + reg-io-width: + description: | + The size (in bytes) of the IO accesses that should be performed on the + device. There are some systems that require 32-bit accesses to the + UART (e.g. TI davinci). + + used-by-rtas: + type: boolean + description: | + Set to indicate that the port is in use by the OpenFirmware RTAS and + should not be registered. + + no-loopback-test: + type: boolean + description: | + Set to indicate that the port does not implement loopback test mode. + + fifo-size: + $ref: /schemas/types.yaml#definitions/uint32 + description: The fifo size of the UART. + + auto-flow-control: + type: boolean + description: | + One way to enable automatic flow control support. The driver is + allowed to detect support for the capability even without this + property. + + tx-threshold: + $ref: /schemas/types.yaml#definitions/uint32 + description: | + Specify the TX FIFO low water indication for parts with programmable + TX FIFO thresholds. + + overrun-throttle-ms: + description: | + How long to pause uart rx when input overrun is encountered. + + rts-gpios: true + cts-gpios: true + dtr-gpios: true + dsr-gpios: true + rng-gpios: true + dcd-gpios: true + + aspeed,sirq-polarity-sense: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + Phandle to aspeed,ast2500-scu compatible syscon alongside register + offset and bit number to identify how the SIRQ polarity should be + configured. One possible data source is the LPC/eSPI mode bit. Only + applicable to aspeed,ast2500-vuart. + +required: + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + serial@80230000 { + compatible = "ns8250"; + reg = <0x80230000 0x100>; + interrupts = <10>; + reg-shift = <2>; + clock-frequency = <48000000>; + }; + - | + #include + serial@49042000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0x49042000 0x400>; + interrupts = <80>; + clock-frequency = <48000000>; + cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + - | + #include + serial@1e787000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e787000 0x40>; + reg-shift = <2>; + interrupts = <8>; + clocks = <&syscon ASPEED_CLK_APB>; + no-loopback-test; + aspeed,sirq-polarity-sense = <&syscon 0x70 25>; + }; + +... diff --git a/Bindings/serial/amlogic,meson-uart.yaml b/Bindings/serial/amlogic,meson-uart.yaml index d4178ab0d675..75ebc9952a99 100644 --- a/Bindings/serial/amlogic,meson-uart.yaml +++ b/Bindings/serial/amlogic,meson-uart.yaml @@ -24,18 +24,18 @@ properties: oneOf: - description: Always-on power domain UART controller items: - - enum: + - enum: + - amlogic,meson6-uart + - amlogic,meson8-uart + - amlogic,meson8b-uart + - amlogic,meson-gx-uart + - const: amlogic,meson-ao-uart + - description: Everything-Else power domain UART controller + enum: - amlogic,meson6-uart - amlogic,meson8-uart - amlogic,meson8b-uart - amlogic,meson-gx-uart - - const: amlogic,meson-ao-uart - - description: Everything-Else power domain UART controller - enum: - - amlogic,meson6-uart - - amlogic,meson8-uart - - amlogic,meson8b-uart - - amlogic,meson-gx-uart reg: maxItems: 1 diff --git a/Bindings/serial/ingenic,uart.txt b/Bindings/serial/ingenic,uart.txt deleted file mode 100644 index 24ed8769f4af..000000000000 --- a/Bindings/serial/ingenic,uart.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Ingenic SoC UART - -Required properties: -- compatible : One of: - - "ingenic,jz4740-uart", - - "ingenic,jz4760-uart", - - "ingenic,jz4770-uart", - - "ingenic,jz4775-uart", - - "ingenic,jz4780-uart", - - "ingenic,x1000-uart". -- reg : offset and length of the register set for the device. -- interrupts : should contain uart interrupt. -- clocks : phandles to the module & baud clocks. -- clock-names: tuple listing input clock names. - Required elements: "baud", "module" - -Example: - -uart0: serial@10030000 { - compatible = "ingenic,jz4740-uart"; - reg = <0x10030000 0x100>; - - interrupt-parent = <&intc>; - interrupts = <9>; - - clocks = <&ext>, <&cgu JZ4740_CLK_UART0>; - clock-names = "baud", "module"; -}; diff --git a/Bindings/serial/ingenic,uart.yaml b/Bindings/serial/ingenic,uart.yaml new file mode 100644 index 000000000000..c023d650e9c1 --- /dev/null +++ b/Bindings/serial/ingenic,uart.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/ingenic,uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs UART controller devicetree bindings + +maintainers: + - Paul Cercueil + +properties: + $nodename: + pattern: "^serial@[0-9a-f]+$" + + compatible: + oneOf: + - enum: + - ingenic,jz4740-uart + - ingenic,jz4760-uart + - ingenic,jz4780-uart + - ingenic,x1000-uart + - items: + - enum: + - ingenic,jz4770-uart + - ingenic,jz4775-uart + - const: ingenic,jz4760-uart + - items: + - const: ingenic,jz4725b-uart + - const: ingenic,jz4740-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Baud clock + - description: UART module clock + + clock-names: + items: + - const: baud + - const: module + + dmas: + items: + - description: DMA controller phandle and request line for RX + - description: DMA controller phandle and request line for TX + + dma-names: + items: + - const: rx + - const: tx + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + +examples: + - | + #include + #include + #include + serial@10032000 { + compatible = "ingenic,jz4780-uart"; + reg = <0x10032000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <49>; + + clocks = <&ext>, <&cgu JZ4780_CLK_UART2>; + clock-names = "baud", "module"; + + dmas = <&dma JZ4780_DMA_UART2_RX 0xffffffff>, + <&dma JZ4780_DMA_UART2_TX 0xffffffff>; + dma-names = "rx", "tx"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + reset-gpios = <&gpf 8 GPIO_ACTIVE_HIGH>; + vcc-supply = <&wlan0_power>; + device-wakeup-gpios = <&gpf 5 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpf 6 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpf 4 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Bindings/serial/mrvl-serial.txt b/Bindings/serial/mrvl-serial.txt deleted file mode 100644 index d744340de887..000000000000 --- a/Bindings/serial/mrvl-serial.txt +++ /dev/null @@ -1,4 +0,0 @@ -PXA UART controller - -Required properties: -- compatible : should be "mrvl,mmp-uart" or "mrvl,pxa-uart". diff --git a/Bindings/serial/nxp,sc16is7xx.txt b/Bindings/serial/nxp,sc16is7xx.txt index c1091a923a89..0fa8e3e43bf8 100644 --- a/Bindings/serial/nxp,sc16is7xx.txt +++ b/Bindings/serial/nxp,sc16is7xx.txt @@ -21,6 +21,8 @@ Optional properties: the second cell is used to specify the GPIO polarity: 0 = active high, 1 = active low. +- irda-mode-ports: An array that lists the indices of the port that + should operate in IrDA mode. Example: sc16is750: sc16is750@51 { @@ -55,6 +57,8 @@ Optional properties: the second cell is used to specify the GPIO polarity: 0 = active high, 1 = active low. +- irda-mode-ports: An array that lists the indices of the port that + should operate in IrDA mode. Example: sc16is750: sc16is750@0 { diff --git a/Bindings/serial/pl011.yaml b/Bindings/serial/pl011.yaml index 1a64d59152aa..c23c93b400f0 100644 --- a/Bindings/serial/pl011.yaml +++ b/Bindings/serial/pl011.yaml @@ -88,17 +88,15 @@ properties: description: Rate at which poll occurs when auto-poll is set. default 100ms. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - default: 100 + $ref: /schemas/types.yaml#/definitions/uint32 + default: 100 poll-timeout-ms: description: Poll timeout when auto-poll is set, default 3000ms. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - default: 3000 + $ref: /schemas/types.yaml#/definitions/uint32 + default: 3000 required: - compatible diff --git a/Bindings/serial/qca,ar9330-uart.txt b/Bindings/serial/qca,ar9330-uart.txt deleted file mode 100644 index 7d65126bd1d7..000000000000 --- a/Bindings/serial/qca,ar9330-uart.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Qualcomm Atheros AR9330 High-Speed UART - -Required properties: - -- compatible: Must be "qca,ar9330-uart" - -- reg: Specifies the physical base address of the controller and - the length of the memory mapped region. - -- interrupts: Specifies the interrupt source of the parent interrupt - controller. The format of the interrupt specifier depends on the - parent interrupt controller. - -Additional requirements: - - Each UART port must have an alias correctly numbered in "aliases" - node. - -Example: - - aliases { - serial0 = &uart0; - }; - - uart0: uart@18020000 { - compatible = "qca,ar9330-uart"; - reg = <0x18020000 0x14>; - - interrupt-parent = <&intc>; - interrupts = <3>; - }; diff --git a/Bindings/serial/qca,ar9330-uart.yaml b/Bindings/serial/qca,ar9330-uart.yaml new file mode 100644 index 000000000000..a344369285b6 --- /dev/null +++ b/Bindings/serial/qca,ar9330-uart.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/qca,ar9330-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros AR9330 High-Speed UART + +maintainers: + - Oleksij Rempel + +allOf: + - $ref: /schemas/serial.yaml# + +properties: + compatible: + const: qca,ar9330-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: uart + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + serial@18020000 { + compatible = "qca,ar9330-uart"; + reg = <0x18020000 0x14>; + clocks = <&ref>; + clock-names = "uart"; + interrupt-parent = <&intc>; + interrupts = <3>; + }; +... diff --git a/Bindings/serial/renesas,em-uart.yaml b/Bindings/serial/renesas,em-uart.yaml new file mode 100644 index 000000000000..82aefdb0d45e --- /dev/null +++ b/Bindings/serial/renesas,em-uart.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/serial/renesas,em-uart.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas EMMA Mobile UART Interface + +maintainers: + - Magnus Damm + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: renesas,em-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: sclk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + uart0: serial@e1020000 { + compatible = "renesas,em-uart"; + reg = <0xe1020000 0x38>; + interrupts = ; + clocks = <&usia_u0_sclk>; + clock-names = "sclk"; + }; diff --git a/Bindings/serial/renesas,hscif.yaml b/Bindings/serial/renesas,hscif.yaml index 91101521ef07..6b04c0451d41 100644 --- a/Bindings/serial/renesas,hscif.yaml +++ b/Bindings/serial/renesas,hscif.yaml @@ -24,6 +24,7 @@ properties: - items: - enum: + - renesas,hscif-r8a7742 # RZ/G1H - renesas,hscif-r8a7743 # RZ/G1M - renesas,hscif-r8a7744 # RZ/G1N - renesas,hscif-r8a7745 # RZ/G1E diff --git a/Bindings/serial/renesas,scif.yaml b/Bindings/serial/renesas,scif.yaml index 70392b9bd977..570b379f9f19 100644 --- a/Bindings/serial/renesas,scif.yaml +++ b/Bindings/serial/renesas,scif.yaml @@ -33,6 +33,7 @@ properties: - items: - enum: + - renesas,scif-r8a7742 # RZ/G1H - renesas,scif-r8a7743 # RZ/G1M - renesas,scif-r8a7744 # RZ/G1N - renesas,scif-r8a7745 # RZ/G1E diff --git a/Bindings/serial/renesas,scifa.yaml b/Bindings/serial/renesas,scifa.yaml index b28bcb268854..78b8e20dd34d 100644 --- a/Bindings/serial/renesas,scifa.yaml +++ b/Bindings/serial/renesas,scifa.yaml @@ -24,13 +24,14 @@ properties: - items: - enum: - - renesas,scifa-r8a7743 # R8A7743 RZ/G1M - - renesas,scifa-r8a7744 # R8A7744 RZ/G1N - - renesas,scifa-r8a7745 # R8A7745 RZ/G1E - - renesas,scifa-r8a7790 # R8A7790 R-Car H2 - - renesas,scifa-r8a7791 # R8A7791 R-Car M2-W - - renesas,scifa-r8a7793 # R8A7793 R-Car M2-N - - renesas,scifa-r8a7794 # R8A7794 R-Car E2 + - renesas,scifa-r8a7742 # RZ/G1H + - renesas,scifa-r8a7743 # RZ/G1M + - renesas,scifa-r8a7744 # RZ/G1N + - renesas,scifa-r8a7745 # RZ/G1E + - renesas,scifa-r8a7790 # R-Car H2 + - renesas,scifa-r8a7791 # R-Car M2-W + - renesas,scifa-r8a7793 # R-Car M2-N + - renesas,scifa-r8a7794 # R-Car E2 - const: renesas,rcar-gen2-scifa # R-Car Gen2 and RZ/G1 - const: renesas,scifa # generic SCIFA compatible UART diff --git a/Bindings/serial/renesas,scifb.yaml b/Bindings/serial/renesas,scifb.yaml index 57205cb1dcd4..b083970c16a9 100644 --- a/Bindings/serial/renesas,scifb.yaml +++ b/Bindings/serial/renesas,scifb.yaml @@ -24,6 +24,7 @@ properties: - items: - enum: + - renesas,scifb-r8a7742 # RZ/G1H - renesas,scifb-r8a7743 # RZ/G1M - renesas,scifb-r8a7744 # RZ/G1N - renesas,scifb-r8a7745 # RZ/G1E diff --git a/Bindings/serial/rs485.yaml b/Bindings/serial/rs485.yaml index d4beaf11222d..fe90569475e1 100644 --- a/Bindings/serial/rs485.yaml +++ b/Bindings/serial/rs485.yaml @@ -6,40 +6,43 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: RS485 serial communications Bindings -description: The RTS signal is capable of automatically controlling - line direction for the built-in half-duplex mode. - The properties described hereafter shall be given to a - half-duplex capable UART node. +description: The RTS signal is capable of automatically controlling line + direction for the built-in half-duplex mode. The properties described + hereafter shall be given to a half-duplex capable UART node. maintainers: - - Rob Herring + - Rob Herring properties: rs485-rts-delay: description: prop-encoded-array - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - items: - items: - - description: - Delay between rts signal and beginning of data sent in milliseconds. - It corresponds to the delay before sending data. - default: 0 - maximum: 1000 - - description: - Delay between end of data sent and rts signal in milliseconds. - It corresponds to the delay after sending data and actual release of the line. - default: 0 - maximum: 1000 + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + items: + - description: Delay between rts signal and beginning of data sent in + milliseconds. It corresponds to the delay before sending data. + default: 0 + maximum: 1000 + - description: Delay between end of data sent and rts signal in milliseconds. + It corresponds to the delay after sending data and actual release + of the line. + default: 0 + maximum: 1000 rs485-rts-active-low: description: drive RTS low when sending (default is high). $ref: /schemas/types.yaml#/definitions/flag linux,rs485-enabled-at-boot-time: - description: enables the rs485 feature at boot time. It can be disabled later with proper ioctl. + description: enables the rs485 feature at boot time. It can be disabled + later with proper ioctl. $ref: /schemas/types.yaml#/definitions/flag rs485-rx-during-tx: - description: enables the receiving of data even while sending data. - $ref: /schemas/types.yaml#/definitions/flag + description: enables the receiving of data even while sending data. + $ref: /schemas/types.yaml#/definitions/flag + + rs485-term-gpios: + description: GPIO pin to enable RS485 bus termination. + maxItems: 1 +... diff --git a/Bindings/serial/samsung_uart.yaml b/Bindings/serial/samsung_uart.yaml index 9d2ce347875b..96414ac65d06 100644 --- a/Bindings/serial/samsung_uart.yaml +++ b/Bindings/serial/samsung_uart.yaml @@ -29,6 +29,13 @@ properties: reg: maxItems: 1 + reg-io-width: + description: | + The size (in bytes) of the IO accesses that should be performed + on the device. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 4 ] + clocks: minItems: 2 maxItems: 5 @@ -51,9 +58,8 @@ properties: samsung,uart-fifosize: description: The fifo size supported by the UART channel. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [16, 64, 256] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [16, 64, 256] required: - compatible diff --git a/Bindings/serial/serial.yaml b/Bindings/serial/serial.yaml index 53204d90d0c7..8645d0e526b4 100644 --- a/Bindings/serial/serial.yaml +++ b/Bindings/serial/serial.yaml @@ -67,6 +67,14 @@ properties: (wired and enabled by pinmux configuration). This depends on both the UART hardware and the board wiring. + rx-tx-swap: + type: boolean + description: RX and TX pins are swapped. + + cts-rts-swap: + type: boolean + description: CTS and RTS pins are swapped. + if: required: - uart-has-rtscts diff --git a/Bindings/serial/sifive-serial.yaml b/Bindings/serial/sifive-serial.yaml index e8d3aeda1202..92283f693de0 100644 --- a/Bindings/serial/sifive-serial.yaml +++ b/Bindings/serial/sifive-serial.yaml @@ -55,7 +55,7 @@ examples: compatible = "sifive,fu540-c000-uart", "sifive,uart0"; interrupt-parent = <&plic0>; interrupts = <80>; - reg = <0x0 0x10010000 0x0 0x1000>; + reg = <0x10010000 0x1000>; clocks = <&prci PRCI_CLK_TLCLK>; }; diff --git a/Bindings/serial/st,stm32-uart.yaml b/Bindings/serial/st,stm32-uart.yaml index 238c44192d31..75b8521eb7cb 100644 --- a/Bindings/serial/st,stm32-uart.yaml +++ b/Bindings/serial/st,stm32-uart.yaml @@ -48,6 +48,12 @@ properties: minItems: 1 maxItems: 2 + cts-gpios: + maxItems: 1 + + rts-gpios: + maxItems: 1 + wakeup-source: true rs485-rts-delay: true @@ -55,6 +61,14 @@ properties: linux,rs485-enabled-at-boot-time: true rs485-rx-during-tx: true +if: + required: + - st,hw-flow-ctrl +then: + properties: + cts-gpios: false + rts-gpios: false + required: - compatible - reg diff --git a/Bindings/soc/amlogic/amlogic,canvas.yaml b/Bindings/soc/amlogic/amlogic,canvas.yaml index cb008fd188d8..02b2d5ba01d6 100644 --- a/Bindings/soc/amlogic/amlogic,canvas.yaml +++ b/Bindings/soc/amlogic/amlogic,canvas.yaml @@ -26,11 +26,11 @@ properties: compatible: oneOf: - items: - - enum: - - amlogic,meson8-canvas - - amlogic,meson8b-canvas - - amlogic,meson8m2-canvas - - const: amlogic,canvas + - enum: + - amlogic,meson8-canvas + - amlogic,meson8b-canvas + - amlogic,meson8m2-canvas + - const: amlogic,canvas - const: amlogic,canvas # GXBB and newer SoCs reg: diff --git a/Bindings/soc/qcom/qcom,aoss-qmp.txt b/Bindings/soc/qcom/qcom,aoss-qmp.txt index 4fc571e78f01..953add19e937 100644 --- a/Bindings/soc/qcom/qcom,aoss-qmp.txt +++ b/Bindings/soc/qcom/qcom,aoss-qmp.txt @@ -19,6 +19,7 @@ power-domains. "qcom,sc7180-aoss-qmp" "qcom,sdm845-aoss-qmp" "qcom,sm8150-aoss-qmp" + "qcom,sm8250-aoss-qmp" - reg: Usage: required diff --git a/Bindings/soc/qcom/qcom,apr.txt b/Bindings/soc/qcom/qcom,apr.txt index f8fa71f5d84b..2e2f6dc351c0 100644 --- a/Bindings/soc/qcom/qcom,apr.txt +++ b/Bindings/soc/qcom/qcom,apr.txt @@ -65,30 +65,30 @@ which uses apr as communication between Apps and QDSP. compatible = "qcom,apr-v2"; qcom,apr-domain = ; - q6core@3 { + apr-service@3 { compatible = "qcom,q6core"; reg = ; }; - q6afe@4 { + apr-service@4 { compatible = "qcom,q6afe"; reg = ; dais { #sound-dai-cells = <1>; - hdmi@1 { - reg = <1>; + dai@1 { + reg = ; }; }; }; - q6asm@7 { + apr-service@7 { compatible = "qcom,q6asm"; reg = ; ... }; - q6adm@8 { + apr-service@8 { compatible = "qcom,q6adm"; reg = ; ... @@ -106,26 +106,26 @@ have no such dependency. qcom,glink-channels = "apr_audio_svc"; qcom,apr-domain = ; - q6core { + apr-service@3 { compatible = "qcom,q6core"; reg = ; }; - q6afe: q6afe { + q6afe: apr-service@4 { compatible = "qcom,q6afe"; reg = ; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; ... }; - q6asm: q6asm { + q6asm: apr-service@7 { compatible = "qcom,q6asm"; reg = ; qcom,protection-domain = "tms/servreg", "msm/slpi/sensor_pd"; ... }; - q6adm: q6adm { + q6adm: apr-service@8 { compatible = "qcom,q6adm"; reg = ; qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; diff --git a/Bindings/soc/qcom/qcom,geni-se.txt b/Bindings/soc/qcom/qcom,geni-se.txt deleted file mode 100644 index dab7ca9f250c..000000000000 --- a/Bindings/soc/qcom/qcom,geni-se.txt +++ /dev/null @@ -1,94 +0,0 @@ -Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller - -Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper -is a programmable module for supporting a wide range of serial interfaces -like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial -Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP -Wrapper controller is modeled as a node with zero or more child nodes each -representing a serial engine. - -Required properties: -- compatible: Must be "qcom,geni-se-qup". -- reg: Must contain QUP register address and length. -- clock-names: Must contain "m-ahb" and "s-ahb". -- clocks: AHB clocks needed by the device. - -Required properties if child node exists: -- #address-cells: Must be <1> for Serial Engine Address -- #size-cells: Must be <1> for Serial Engine Address Size -- ranges: Must be present - -Properties for children: - -A GENI based QUP wrapper controller node can contain 0 or more child nodes -representing serial devices. These serial devices can be a QCOM UART, I2C -controller, SPI controller, or some combination of aforementioned devices. -Please refer below the child node definitions for the supported serial -interface protocols. - -Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller - -Required properties: -- compatible: Must be "qcom,geni-i2c". -- reg: Must contain QUP register address and length. -- interrupts: Must contain I2C interrupt. -- clock-names: Must contain "se". -- clocks: Serial engine core clock needed by the device. -- #address-cells: Must be <1> for I2C device address. -- #size-cells: Must be <0> as I2C addresses have no size component. - -Optional property: -- clock-frequency: Desired I2C bus clock frequency in Hz. - When missing default to 100000Hz. - -Child nodes should conform to I2C bus binding as described in i2c.txt. - -Qualcomm Technologies Inc. GENI Serial Engine based UART Controller - -Required properties: -- compatible: Must be "qcom,geni-debug-uart" or "qcom,geni-uart". -- reg: Must contain UART register location and length. -- interrupts: Must contain UART core interrupts. -- clock-names: Must contain "se". -- clocks: Serial engine core clock needed by the device. - -Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller -node binding is described in -Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt. - -Example: - geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x8c0000 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - i2c0: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0xa94000 0x4000>; - interrupts = ; - clock-names = "se"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_i2c_5_active>; - pinctrl-1 = <&qup_1_i2c_5_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; - - uart0: serial@a88000 { - compatible = "qcom,geni-debug-uart"; - reg = <0xa88000 0x7000>; - interrupts = ; - clock-names = "se"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_uart_3_active>; - pinctrl-1 = <&qup_1_uart_3_sleep>; - }; - - } diff --git a/Bindings/soc/qcom/qcom,geni-se.yaml b/Bindings/soc/qcom/qcom,geni-se.yaml new file mode 100644 index 000000000000..a2b29cc3e93b --- /dev/null +++ b/Bindings/soc/qcom/qcom,geni-se.yaml @@ -0,0 +1,222 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: GENI Serial Engine QUP Wrapper Controller + +maintainers: + - Mukesh Savaliya + - Akash Asthana + +description: | + Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper + is a programmable module for supporting a wide range of serial interfaces + like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial + Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP + Wrapper controller is modeled as a node with zero or more child nodes each + representing a serial engine. + +properties: + compatible: + enum: + - qcom,geni-se-qup + + reg: + description: QUP wrapper common register address and length. + maxItems: 1 + + clock-names: + items: + - const: m-ahb + - const: s-ahb + + clocks: + items: + - description: Master AHB Clock + - description: Slave AHB Clock + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + interconnects: + maxItems: 1 + + interconnect-names: + const: qup-core + +required: + - compatible + - reg + - clock-names + - clocks + - "#address-cells" + - "#size-cells" + - ranges + +patternProperties: + "^.*@[0-9a-f]+$": + type: object + description: Common properties for GENI Serial Engine based I2C, SPI and + UART controller. + + properties: + reg: + description: GENI Serial Engine register address and length. + maxItems: 1 + + clock-names: + const: se + + clocks: + description: Serial engine core clock needed by the device. + maxItems: 1 + + interconnects: + minItems: 2 + maxItems: 3 + + interconnect-names: + minItems: 2 + items: + - const: qup-core + - const: qup-config + - const: qup-memory + + required: + - reg + - clock-names + - clocks + + "spi@[0-9a-f]+$": + type: object + description: GENI serial engine based SPI controller. SPI in master mode + supports up to 50MHz, up to four chip selects, programmable + data path from 4 bits to 32 bits and numerous protocol + variants. + $ref: /spi/spi-controller.yaml# + + properties: + compatible: + enum: + - qcom,geni-spi + + interrupts: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + required: + - compatible + - interrupts + - "#address-cells" + - "#size-cells" + + "i2c@[0-9a-f]+$": + type: object + description: GENI serial engine based I2C controller. + $ref: /schemas/i2c/i2c-controller.yaml# + + properties: + compatible: + enum: + - qcom,geni-i2c + + interrupts: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clock-frequency: + description: Desired I2C bus clock frequency in Hz. + default: 100000 + + required: + - compatible + - interrupts + - "#address-cells" + - "#size-cells" + + "serial@[0-9a-f]+$": + type: object + description: GENI Serial Engine based UART Controller. + $ref: /schemas/serial.yaml# + + properties: + compatible: + enum: + - qcom,geni-uart + - qcom,geni-debug-uart + + interrupts: + minItems: 1 + maxItems: 2 + items: + - description: UART core irq + - description: Wakeup irq (RX GPIO) + + required: + - compatible + - interrupts + + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x008c0000 0 0x6000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0xa94000 0 0x4000>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_i2c_5_active>; + pinctrl-1 = <&qup_1_i2c_5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart0: serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0 0xa88000 0 0x7000>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_1_uart_3_active>; + pinctrl-1 = <&qup_1_uart_3_sleep>; + }; + }; + }; + +... diff --git a/Bindings/soc/ti/k3-socinfo.yaml b/Bindings/soc/ti/k3-socinfo.yaml new file mode 100644 index 000000000000..a1a8423b2e2e --- /dev/null +++ b/Bindings/soc/ti/k3-socinfo.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/ti/k3-socinfo.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 Multicore SoC platforms chipid module + +maintainers: + - Tero Kristo + - Nishanth Menon + +description: | + Texas Instruments (ARM64) K3 Multicore SoC platforms chipid module is + represented by CTRLMMR_xxx_JTAGID register which contains information about + SoC id and revision. + +properties: + $nodename: + pattern: "^chipid@[0-9a-f]+$" + + compatible: + items: + - const: ti,am654-chipid + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + chipid@43000014 { + compatible = "ti,am654-chipid"; + reg = <0x43000014 0x4>; + }; diff --git a/Bindings/sound/adi,adau7118.yaml b/Bindings/sound/adi,adau7118.yaml index 76ee695097bf..fb78967ee17b 100644 --- a/Bindings/sound/adi,adau7118.yaml +++ b/Bindings/sound/adi,adau7118.yaml @@ -35,23 +35,21 @@ properties: adi,decimation-ratio: description: | This property set's the decimation ratio of PDM to PCM audio data. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [64, 32, 16] - default: 64 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [64, 32, 16] + default: 64 adi,pdm-clk-map: description: | The ADAU7118 has two PDM clocks for the four Inputs. Each input must be assigned to one of these two clocks. This property set's the mapping between the clocks and the inputs. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32-array - - minItems: 4 - maxItems: 4 - items: - maximum: 1 - default: [0, 0, 1, 1] + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 4 + maxItems: 4 + items: + maximum: 1 + default: [0, 0, 1, 1] required: - "#sound-dai-cells" diff --git a/Bindings/sound/allwinner,sun4i-a10-codec.yaml b/Bindings/sound/allwinner,sun4i-a10-codec.yaml index ea1d2efb2aaa..be390accdd07 100644 --- a/Bindings/sound/allwinner,sun4i-a10-codec.yaml +++ b/Bindings/sound/allwinner,sun4i-a10-codec.yaml @@ -57,32 +57,31 @@ properties: A list of the connections between audio components. Each entry is a pair of strings, the first being the connection's sink, the second being the connection's source. - allOf: - - $ref: /schemas/types.yaml#definitions/non-unique-string-array - - minItems: 2 - maxItems: 18 - items: - enum: - # Audio Pins on the SoC - - HP - - HPCOM - - LINEIN - - LINEOUT - - MIC1 - - MIC2 - - MIC3 + $ref: /schemas/types.yaml#definitions/non-unique-string-array + minItems: 2 + maxItems: 18 + items: + enum: + # Audio Pins on the SoC + - HP + - HPCOM + - LINEIN + - LINEOUT + - MIC1 + - MIC2 + - MIC3 - # Microphone Biases from the SoC - - HBIAS - - MBIAS + # Microphone Biases from the SoC + - HBIAS + - MBIAS - # Board Connectors - - Headphone - - Headset Mic - - Line In - - Line Out - - Mic - - Speaker + # Board Connectors + - Headphone + - Headset Mic + - Line In + - Line Out + - Mic + - Speaker allwinner,codec-analog-controls: $ref: /schemas/types.yaml#/definitions/phandle diff --git a/Bindings/sound/amlogic,aiu.yaml b/Bindings/sound/amlogic,aiu.yaml index a61bccf915d8..f9344adaf6c2 100644 --- a/Bindings/sound/amlogic,aiu.yaml +++ b/Bindings/sound/amlogic,aiu.yaml @@ -86,7 +86,7 @@ examples: aiu: audio-controller@5400 { compatible = "amlogic,aiu-gxl", "amlogic,aiu"; #sound-dai-cells = <2>; - reg = <0x0 0x5400 0x0 0x2ac>; + reg = <0x5400 0x2ac>; interrupts = , ; interrupt-names = "i2s", "spdif"; @@ -110,4 +110,3 @@ examples: "spdif_mclk_sel"; resets = <&reset RESET_AIU>; }; - diff --git a/Bindings/sound/amlogic,g12a-toacodec.yaml b/Bindings/sound/amlogic,g12a-toacodec.yaml index f778d3371fde..51a0c30e10f9 100644 --- a/Bindings/sound/amlogic,g12a-toacodec.yaml +++ b/Bindings/sound/amlogic,g12a-toacodec.yaml @@ -45,7 +45,7 @@ examples: toacodec: audio-controller@740 { compatible = "amlogic,g12a-toacodec"; - reg = <0x0 0x740 0x0 0x4>; + reg = <0x740 0x4>; #sound-dai-cells = <1>; resets = <&clkc_audio AUD_RESET_TOACODEC>; }; diff --git a/Bindings/sound/amlogic,t9015.yaml b/Bindings/sound/amlogic,t9015.yaml index b7c38c2b5b54..04014e658c90 100644 --- a/Bindings/sound/amlogic,t9015.yaml +++ b/Bindings/sound/amlogic,t9015.yaml @@ -49,10 +49,9 @@ examples: acodec: audio-controller@32000 { compatible = "amlogic,t9015"; - reg = <0x0 0x32000 0x0 0x14>; + reg = <0x32000 0x14>; #sound-dai-cells = <0>; clocks = <&clkc CLKID_AUDIO_CODEC>; clock-names = "pclk"; resets = <&reset RESET_AUDIO_CODEC>; }; - diff --git a/Bindings/sound/audio-graph-card.txt b/Bindings/sound/audio-graph-card.txt index 269682619a70..d5f6919a2d69 100644 --- a/Bindings/sound/audio-graph-card.txt +++ b/Bindings/sound/audio-graph-card.txt @@ -5,7 +5,7 @@ It is based on common bindings for device graphs. see ${LINUX}/Documentation/devicetree/bindings/graph.txt Basically, Audio Graph Card property is same as Simple Card. -see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt +see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.yaml Below are same as Simple-Card. diff --git a/Bindings/sound/cirrus,lochnagar.txt b/Bindings/sound/cirrus,lochnagar.txt deleted file mode 100644 index 41ae2699f07a..000000000000 --- a/Bindings/sound/cirrus,lochnagar.txt +++ /dev/null @@ -1,39 +0,0 @@ -Cirrus Logic Lochnagar Audio Development Board - -Lochnagar is an evaluation and development board for Cirrus Logic -Smart CODEC and Amp devices. It allows the connection of most Cirrus -Logic devices on mini-cards, as well as allowing connection of -various application processor systems to provide a full evaluation -platform. Audio system topology, clocking and power can all be -controlled through the Lochnagar, allowing the device under test -to be used in a variety of possible use cases. - -This binding document describes the binding for the audio portion -of the driver. - -This binding must be part of the Lochnagar MFD binding: - [4] ../mfd/cirrus,lochnagar.txt - -Required properties: - - - compatible : One of the following strings: - "cirrus,lochnagar2-soundcard" - - - #sound-dai-cells : Must be set to 1. - - - clocks : Contains an entry for each entry in clock-names. - - clock-names : Must include the following clocks: - "mclk" Master clock source for the sound card, should normally - be set to LOCHNAGAR_SOUNDCARD_MCLK provided by the Lochnagar - clock driver. - -Example: - -lochnagar-sc { - compatible = "cirrus,lochnagar2-soundcard"; - - #sound-dai-cells = <1>; - - clocks = <&lochnagar_clk LOCHNAGAR_SOUNDCARD_MCLK>; - clock-names = "mclk"; -}; diff --git a/Bindings/sound/cirrus,lochnagar.yaml b/Bindings/sound/cirrus,lochnagar.yaml new file mode 100644 index 000000000000..cea612d3d4a7 --- /dev/null +++ b/Bindings/sound/cirrus,lochnagar.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cirrus,lochnagar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic Lochnagar Audio Development Board + +maintainers: + - patches@opensource.cirrus.com + +description: | + Lochnagar is an evaluation and development board for Cirrus Logic + Smart CODEC and Amp devices. It allows the connection of most Cirrus + Logic devices on mini-cards, as well as allowing connection of various + application processor systems to provide a full evaluation platform. + Audio system topology, clocking and power can all be controlled through + the Lochnagar, allowing the device under test to be used in a variety of + possible use cases. + + This binding document describes the binding for the audio portion of the + driver. + + This binding must be part of the Lochnagar MFD binding: + [1] ../mfd/cirrus,lochnagar.yaml + +properties: + compatible: + enum: + - cirrus,lochnagar2-soundcard + + '#sound-dai-cells': + description: + The first cell indicating the audio interface. + const: 1 + + clocks: + description: + Master clock source for the sound card, should normally be set to + LOCHNAGAR_SOUNDCARD_MCLK provided by the Lochnagar clock driver. + maxItems: 1 + + clock-names: + const: mclk + +required: + - compatible + - '#sound-dai-cells' + - clocks + - clock-names + +additionalProperties: false diff --git a/Bindings/sound/cirrus,madera.yaml b/Bindings/sound/cirrus,madera.yaml new file mode 100644 index 000000000000..c4cd58b5acd4 --- /dev/null +++ b/Bindings/sound/cirrus,madera.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cirrus,madera.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic Madera class audio CODECs + +maintainers: + - patches@opensource.cirrus.com + +description: | + This describes audio configuration bindings for these codecs. + + See also the core bindings for the parent MFD driver: + + Documentation/devicetree/bindings/mfd/cirrus,madera.yaml + + and defines for values used in these bindings: + + include/dt-bindings/sound/madera.h + + The properties are all contained in the parent MFD node. + +properties: + '#sound-dai-cells': + description: + The first cell indicating the audio interface. + const: 1 + + cirrus,inmode: + description: + A list of input mode settings for each input. A maximum + of 24 cells, with four cells per input in the order INnAL, + INnAR INnBL INnBR. For non-muxed inputs the first two cells + for that input set the mode for the left and right channel + and the second two cells must be 0. For muxed inputs the + first two cells for that input set the mode of the left and + right A inputs and the second two cells set the mode of the + left and right B inputs. Valid mode values are one of the + MADERA_INMODE_xxx. If the array is shorter than the number + of inputs the unspecified inputs default to MADERA_INMODE_DIFF. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 24 + items: + minimum: 0 + maximum: 1 + default: 0 + + cirrus,out-mono: + description: + Mono bit for each output, maximum of six cells if the array + is shorter outputs will be set to stereo. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 6 + items: + minimum: 0 + maximum: 1 + default: 0 + + cirrus,dmic-ref: + description: | + Indicates how the MICBIAS pins have been externally connected + to DMICs on each input, one cell per input. + + + + A value of 0 indicates MICVDD and is the default, + other values depend on the codec: For CS47L35 one of the + CS47L35_DMIC_REF_xxx values For all other codecs one of + the MADERA_DMIC_REF_xxx values Also see the datasheet for a + description of the INn_DMIC_SUP field. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 6 + items: + minimum: 0 + maximum: 3 + default: 0 + + cirrus,max-channels-clocked: + description: + Maximum number of channels that I2S clocks will be generated + for. Useful when clock master for systems where the I2S bus + has multiple data lines. One cell for each AIF, use a value + of zero for AIFs that should be handled normally. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + default: 0 + + cirrus,pdm-fmt: + description: + PDM speaker data format, must contain 2 cells (OUT5 and + OUT6). See the PDM_SPKn_FMT field in the datasheet for a + description of this value. The second cell is ignored for + codecs that do not have OUT6. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + + cirrus,pdm-mute: + description: | + PDM mute format, must contain 2 cells (OUT5 and OUT6). See the + PDM_SPKn_CTRL_1 register in the datasheet for a description + of this value. The second cell is ignored for codecs that + do not have OUT6. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 diff --git a/Bindings/sound/da7213.txt b/Bindings/sound/da7213.txt index 58902802d56c..94584c96c4ae 100644 --- a/Bindings/sound/da7213.txt +++ b/Bindings/sound/da7213.txt @@ -1,9 +1,9 @@ -Dialog Semiconductor DA7213 Audio Codec bindings +Dialog Semiconductor DA7212/DA7213 Audio Codec bindings ====== Required properties: -- compatible : Should be "dlg,da7213" +- compatible : Should be "dlg,da7212" or "dlg,da7213" - reg: Specifies the I2C slave address Optional properties: @@ -21,6 +21,10 @@ Optional properties: - dlg,dmic-clkrate : DMIC clock frequency (Hz). [<1500000>, <3000000>] + - VDDA-supply : Regulator phandle for Analogue power supply + - VDDMIC-supply : Regulator phandle for Mic Bias + - VDDIO-supply : Regulator phandle for I/O power supply + ====== Example: diff --git a/Bindings/sound/fsl,asrc.txt b/Bindings/sound/fsl,asrc.txt index cb9a25165503..998b4c8a7f78 100644 --- a/Bindings/sound/fsl,asrc.txt +++ b/Bindings/sound/fsl,asrc.txt @@ -51,6 +51,10 @@ Optional properties: will be in use as default. Otherwise, the big endian mode will be in use for all the device registers. + - fsl,asrc-format : Defines a mutual sample format used by DPCM Back + Ends, which can replace the fsl,asrc-width. + The value is 2 (S16_LE), or 6 (S24_LE). + Example: asrc: asrc@2034000 { diff --git a/Bindings/sound/fsl,easrc.yaml b/Bindings/sound/fsl,easrc.yaml new file mode 100644 index 000000000000..32d547af9ce7 --- /dev/null +++ b/Bindings/sound/fsl,easrc.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/fsl,easrc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Asynchronous Sample Rate Converter (ASRC) Controller + +maintainers: + - Shengjiu Wang + +properties: + $nodename: + pattern: "^easrc@.*" + + compatible: + const: fsl,imx8mn-easrc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Peripheral clock + + clock-names: + items: + - const: mem + + dmas: + maxItems: 8 + + dma-names: + items: + - const: ctx0_rx + - const: ctx0_tx + - const: ctx1_rx + - const: ctx1_tx + - const: ctx2_rx + - const: ctx2_tx + - const: ctx3_rx + - const: ctx3_tx + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + const: imx/easrc/easrc-imx8mn.bin + description: The coefficient table for the filters + + fsl,asrc-rate: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 8000 + maximum: 192000 + description: Defines a mutual sample rate used by DPCM Back Ends + + fsl,asrc-format: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 6, 10, 32, 36] + default: 2 + description: + Defines a mutual sample format used by DPCM Back Ends + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + - firmware-name + - fsl,asrc-rate + - fsl,asrc-format + +examples: + - | + #include + + easrc: easrc@300c0000 { + compatible = "fsl,imx8mn-easrc"; + reg = <0x300c0000 0x10000>; + interrupts = <0x0 122 0x4>; + clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + firmware-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-format = <2>; + }; diff --git a/Bindings/sound/fsl,esai.txt b/Bindings/sound/fsl,esai.txt index 0e6e2166f76c..0a2480aeecf0 100644 --- a/Bindings/sound/fsl,esai.txt +++ b/Bindings/sound/fsl,esai.txt @@ -12,6 +12,7 @@ Required properties: "fsl,imx35-esai", "fsl,vf610-esai", "fsl,imx6ull-esai", + "fsl,imx8qm-esai", - reg : Offset and length of the register set for the device. diff --git a/Bindings/sound/madera.txt b/Bindings/sound/madera.txt deleted file mode 100644 index 5e669ce552f4..000000000000 --- a/Bindings/sound/madera.txt +++ /dev/null @@ -1,67 +0,0 @@ -Cirrus Logic Madera class audio codecs - -This describes audio configuration bindings for these codecs. - -See also the core bindings for the parent MFD driver: -See Documentation/devicetree/bindings/mfd/madera.txt - -and defines for values used in these bindings: -include/dt-bindings/sound/madera.h - -These properties are all contained in the parent MFD node. - -Optional properties: - - cirrus,dmic-ref : Indicates how the MICBIAS pins have been externally - connected to DMICs on each input, one cell per input. - - A value of 0 indicates MICVDD and is the default, other values depend on the - codec: - For CS47L35 one of the CS47L35_DMIC_REF_xxx values - For all other codecs one of the MADERA_DMIC_REF_xxx values - Also see the datasheet for a description of the INn_DMIC_SUP field. - - - cirrus,inmode : A list of input mode settings for each input. A maximum of - 16 cells, with four cells per input in the order INnAL, INnAR INnBL INnBR. - For non-muxed inputs the first two cells for that input set the mode for - the left and right channel and the second two cells must be 0. - For muxed inputs the first two cells for that input set the mode of the - left and right A inputs and the second two cells set the mode of the left - and right B inputs. - Valid mode values are one of the MADERA_INMODE_xxx. If the array is shorter - than the number of inputs the unspecified inputs default to - MADERA_INMODE_DIFF. - - - cirrus,out-mono : Mono bit for each output, maximum of six cells if the - array is shorter outputs will be set to stereo. - - - cirrus,max-channels-clocked : Maximum number of channels that I2S clocks - will be generated for. Useful when clock master for systems where the I2S - bus has multiple data lines. - One cell for each AIF, use a value of zero for AIFs that should be handled - normally. - - - cirrus,pdm-fmt : PDM speaker data format, must contain 2 cells - (OUT5 and OUT6). See the PDM_SPKn_FMT field in the datasheet for a - description of this value. - The second cell is ignored for codecs that do not have OUT6. - - - cirrus,pdm-mute : PDM mute format, must contain 2 cells - (OUT5 and OUT6). See the PDM_SPKn_CTRL_1 register in the datasheet for a - description of this value. - The second cell is ignored for codecs that do not have OUT6. - -Example: - -cs47l35@0 { - compatible = "cirrus,cs47l35"; - - cirrus,dmic-ref = <0 0 CS47L35_DMIC_REF_MICBIAS1B 0>; - cirrus,inmode = < - MADERA_INMODE_DMIC MADERA_INMODE_DMIC /* IN1A digital */ - MADERA_INMODE_SE MADERA_INMODE_SE /* IN1B single-ended */ - MADERA_INMODE_DIFF MADERA_INMODE_DIFF /* IN2 differential */ - 0 0 /* not used on this codec */ - >; - cirrus,out-mono = <0 0 0 0 0 0>; - cirrus,max-channels-clocked = <2 0 0>; -}; diff --git a/Bindings/sound/marvell,mmp-sspa.yaml b/Bindings/sound/marvell,mmp-sspa.yaml new file mode 100644 index 000000000000..6d20a24a2ae9 --- /dev/null +++ b/Bindings/sound/marvell,mmp-sspa.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/marvell,mmp-sspa.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvel SSPA Digital Audio Interface Bindings + +maintainers: + - Lubomir Rintel + +properties: + $nodename: + pattern: "^audio-controller(@.*)?$" + + compatible: + const: marvell,mmp-sspa + + reg: + items: + - description: RX block + - description: TX block + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Clock for the Audio block + - description: I2S bit clock + + clock-names: + items: + - const: audio + - const: bitclk + + power-domains: + maxItems: 1 + + '#sound-dai-cells': + const: 0 + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + + port: + type: object + + properties: + endpoint: + type: object + + properties: + remote-endpoint: true + + frame-master: + type: boolean + description: SoC generates the frame clock + + bitclock-master: + type: boolean + description: SoC generates the bit clock + + dai-format: + $ref: /schemas/types.yaml#/definitions/string + description: The digital audio format + const: i2s + + required: + - remote-endpoint + + required: + - endpoint + + additionalProperties: false + +required: + - "#sound-dai-cells" + - compatible + - reg + - interrupts + - clocks + - clock-names + - dmas + - dma-names + - port + +additionalProperties: false + +examples: + - | + #include + + audio-controller@d42a0c00 { + compatible = "marvell,mmp-sspa"; + reg = <0xd42a0c00 0x30>, + <0xd42a0c80 0x30>; + interrupts = <2>; + clock-names = "audio", "bitclk"; + clocks = <&soc_clocks 127>, + <&audio_clk 1>; + #sound-dai-cells = <0>; + dmas = <&adma0 0>, <&adma0 1>; + dma-names = "tx", "rx"; + port { + endpoint { + remote-endpoint = <&rt5631_0>; + frame-master; + bitclock-master; + dai-format = "i2s"; + }; + }; + }; + +... diff --git a/Bindings/sound/nau8810.txt b/Bindings/sound/nau8810.txt index 05830e477acd..7deaa452b200 100644 --- a/Bindings/sound/nau8810.txt +++ b/Bindings/sound/nau8810.txt @@ -1,10 +1,11 @@ -NAU8810 audio CODEC +NAU8810/NAU8812/NAU8814 audio CODEC This device supports I2C only. Required properties: - - compatible : "nuvoton,nau8810" + - compatible : One of "nuvoton,nau8810" or "nuvoton,nau8812" or + "nuvoton,nau8814" - reg : the I2C address of the device. diff --git a/Bindings/sound/nau8825.txt b/Bindings/sound/nau8825.txt index d16d96839bcb..388a7bc60b1f 100644 --- a/Bindings/sound/nau8825.txt +++ b/Bindings/sound/nau8825.txt @@ -101,5 +101,5 @@ Example: nuvoton,crosstalk-enable; clock-names = "mclk"; - clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>; + clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_2>; }; diff --git a/Bindings/sound/nvidia,tegra-audio-wm8903.txt b/Bindings/sound/nvidia,tegra-audio-wm8903.txt index a8f2b0c56c79..bbd581a8c5bc 100644 --- a/Bindings/sound/nvidia,tegra-audio-wm8903.txt +++ b/Bindings/sound/nvidia,tegra-audio-wm8903.txt @@ -29,6 +29,7 @@ Optional properties: - nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in - nvidia,int-mic-en-gpios : The GPIO that enables the internal microphone - nvidia,ext-mic-en-gpios : The GPIO that enables the external microphone +- nvidia,headset : The Mic Jack represents state of the headset microphone pin Example: diff --git a/Bindings/sound/qcom,lpass-cpu.txt b/Bindings/sound/qcom,lpass-cpu.txt index 21c648328be9..32c2cdb3d32f 100644 --- a/Bindings/sound/qcom,lpass-cpu.txt +++ b/Bindings/sound/qcom,lpass-cpu.txt @@ -30,6 +30,8 @@ Required properties: - reg : Must contain an address for each entry in reg-names. - reg-names : A list which must include the following entries: * "lpass-lpaif" +- #address-cells : Must be 1 +- #size-cells : Must be 0 @@ -37,6 +39,20 @@ Optional properties: - qcom,adsp : Phandle for the audio DSP node +By default, the driver uses up to 4 MI2S SD lines, for a total of 8 channels. +The SD lines to use can be configured by adding subnodes for each of the DAIs. + +Required properties for each DAI (represented by a subnode): +- reg : Must be one of the DAI IDs + (usually part of dt-bindings header) +- qcom,playback-sd-lines: List of serial data lines to use for playback + Each SD line should be represented by a number from 0-3. +- qcom,capture-sd-lines : List of serial data lines to use for capture + Each SD line should be represented by a number from 0-3. + +Note that adding a subnode changes the default to "no lines configured", +so both playback and capture lines should be configured when a subnode is added. + Example: lpass@28100000 { @@ -51,4 +67,13 @@ lpass@28100000 { reg = <0x28100000 0x10000>; reg-names = "lpass-lpaif"; qcom,adsp = <&adsp>; + + #address-cells = <1>; + #size-cells = <0>; + + /* Optional to set different MI2S SD lines */ + dai@3 { + reg = ; + qcom,playback-sd-lines = <0 1>; + }; }; diff --git a/Bindings/sound/qcom,q6adm.txt b/Bindings/sound/qcom,q6adm.txt index bbae426cdfb1..15c353a20de8 100644 --- a/Bindings/sound/qcom,q6adm.txt +++ b/Bindings/sound/qcom,q6adm.txt @@ -29,7 +29,7 @@ used by the apr service device. Definition: Must be 0 = EXAMPLE -q6adm@8 { +apr-service@8 { compatible = "qcom,q6adm"; reg = ; q6routing: routing { diff --git a/Bindings/sound/qcom,q6afe.txt b/Bindings/sound/qcom,q6afe.txt index d74888b9f1bb..4916dd6a0896 100644 --- a/Bindings/sound/qcom,q6afe.txt +++ b/Bindings/sound/qcom,q6afe.txt @@ -100,7 +100,7 @@ configuration of each dai. Must contain the following properties. = EXAMPLE -q6afe@4 { +apr-service@4 { compatible = "qcom,q6afe"; reg = ; @@ -110,12 +110,12 @@ q6afe@4 { #address-cells = <1>; #size-cells = <0>; - hdmi@1 { - reg = <1>; + dai@1 { + reg = ; }; - tdm@24 { - reg = <24>; + dai@24 { + reg = ; qcom,tdm-sync-mode = <1>: qcom,tdm-sync-src = <1>; qcom,tdm-data-out = <0>; @@ -125,8 +125,8 @@ q6afe@4 { }; - tdm@25 { - reg = <25>; + dai@25 { + reg = ; qcom,tdm-sync-mode = <1>: qcom,tdm-sync-src = <1>; qcom,tdm-data-out = <0>; @@ -135,43 +135,43 @@ q6afe@4 { qcom,tdm-data-align = <0>; }; - prim-mi2s-rx@16 { - reg = <16>; + dai@16 { + reg = ; qcom,sd-lines = <0 2>; }; - prim-mi2s-tx@17 { - reg = <17>; + dai@17 { + reg = ; qcom,sd-lines = <1>; }; - sec-mi2s-rx@18 { - reg = <18>; + dai@18 { + reg = ; qcom,sd-lines = <0 3>; }; - sec-mi2s-tx@19 { - reg = <19>; + dai@19 { + reg = ; qcom,sd-lines = <1>; }; - tert-mi2s-rx@20 { - reg = <20>; + dai@20 { + reg = ; qcom,sd-lines = <1 3>; }; - tert-mi2s-tx@21 { - reg = <21>; + dai@21 { + reg = ; qcom,sd-lines = <0>; }; - quat-mi2s-rx@22 { - reg = <22>; + dai@22 { + reg = ; qcom,sd-lines = <0>; }; - quat-mi2s-tx@23 { - reg = <23>; + dai@23 { + reg = ; qcom,sd-lines = <1>; }; }; diff --git a/Bindings/sound/qcom,q6asm.txt b/Bindings/sound/qcom,q6asm.txt index 9f5378c51686..6b9a88d0ea3f 100644 --- a/Bindings/sound/qcom,q6asm.txt +++ b/Bindings/sound/qcom,q6asm.txt @@ -51,13 +51,16 @@ configuration of each dai. Must contain the following properties. = EXAMPLE -q6asm@7 { +apr-service@7 { compatible = "qcom,q6asm"; reg = ; q6asmdai: dais { compatible = "qcom,q6asm-dais"; + #address-cells = <1>; + #size-cells = <0>; #sound-dai-cells = <1>; - mm@0 { + + dai@0 { reg = <0>; direction = <2>; is-compress-dai; diff --git a/Bindings/sound/qcom,q6core.txt b/Bindings/sound/qcom,q6core.txt index 7f36ff8bec18..5cd4cc9b1fde 100644 --- a/Bindings/sound/qcom,q6core.txt +++ b/Bindings/sound/qcom,q6core.txt @@ -15,7 +15,7 @@ used by the apr service device. example "qcom,q6core-v2.0" = EXAMPLE -q6core@3 { +apr-service@3 { compatible = "qcom,q6core"; reg = ; }; diff --git a/Bindings/sound/qcom,wcd934x.yaml b/Bindings/sound/qcom,wcd934x.yaml index a495d5fc0d23..e8f716b5f875 100644 --- a/Bindings/sound/qcom,wcd934x.yaml +++ b/Bindings/sound/qcom,wcd934x.yaml @@ -102,8 +102,7 @@ properties: gpio@42: type: object - allOf: - - $ref: ../gpio/qcom,wcd934x-gpio.yaml# + $ref: ../gpio/qcom,wcd934x-gpio.yaml# patternProperties: "^.*@[0-9a-f]+$": diff --git a/Bindings/sound/renesas,fsi.yaml b/Bindings/sound/renesas,fsi.yaml index d1b65554e681..8a4406be387a 100644 --- a/Bindings/sound/renesas,fsi.yaml +++ b/Bindings/sound/renesas,fsi.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/renesas,fsi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas FSI Sound Driver Device Tree Bindings +title: Renesas FIFO-buffered Serial Interface (FSI) maintainers: - Kuninori Morimoto @@ -17,16 +17,16 @@ properties: oneOf: # for FSI2 SoC - items: - - enum: - - renesas,fsi2-sh73a0 - - renesas,fsi2-r8a7740 - - enum: - - renesas,sh_fsi2 + - enum: + - renesas,fsi2-sh73a0 # SH-Mobile AG5 + - renesas,fsi2-r8a7740 # R-Mobile A1 + - enum: + - renesas,sh_fsi2 # for Generic - items: - - enum: - - renesas,sh_fsi - - renesas,sh_fsi2 + - enum: + - renesas,sh_fsi + - renesas,sh_fsi2 reg: maxItems: 1 @@ -34,6 +34,15 @@ properties: interrupts: maxItems: 1 + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#sound-dai-cells': + const: 1 + fsia,spdif-connection: $ref: /schemas/types.yaml#/definitions/flag description: FSI is connected by S/PDIF @@ -62,16 +71,24 @@ required: - compatible - reg - interrupts + - clocks + - power-domains + - '#sound-dai-cells' additionalProperties: false examples: - | - sh_fsi2: sound@ec230000 { + #include + #include + sh_fsi2: sound@fe1f0000 { compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; - reg = <0xec230000 0x400>; - interrupts = <0 146 0x4>; + reg = <0xfe1f0000 0x400>; + interrupts = ; + clocks = <&mstp3_clks R8A7740_CLK_FSI>; + power-domains = <&pd_a4mp>; + #sound-dai-cells = <1>; fsia,spdif-connection; fsia,stream-mode-support; fsia,use-internal-clock; diff --git a/Bindings/sound/renesas,rsnd.txt b/Bindings/sound/renesas,rsnd.txt index 797fd035434c..1596f0d1e2fe 100644 --- a/Bindings/sound/renesas,rsnd.txt +++ b/Bindings/sound/renesas,rsnd.txt @@ -263,6 +263,7 @@ Required properties: "renesas,rcar_sound-gen2" if generation2 (or RZ/G1) "renesas,rcar_sound-gen3" if generation3 (or RZ/G2) Examples with soctypes are: + - "renesas,rcar_sound-r8a7742" (RZ/G1H) - "renesas,rcar_sound-r8a7743" (RZ/G1M) - "renesas,rcar_sound-r8a7744" (RZ/G1N) - "renesas,rcar_sound-r8a7745" (RZ/G1E) diff --git a/Bindings/sound/rockchip-i2s.yaml b/Bindings/sound/rockchip-i2s.yaml index a3ba2186d6a1..acb2b888dbfc 100644 --- a/Bindings/sound/rockchip-i2s.yaml +++ b/Bindings/sound/rockchip-i2s.yaml @@ -24,6 +24,7 @@ properties: - rockchip,rk3188-i2s - rockchip,rk3228-i2s - rockchip,rk3288-i2s + - rockchip,rk3308-i2s - rockchip,rk3328-i2s - rockchip,rk3366-i2s - rockchip,rk3368-i2s @@ -47,28 +48,27 @@ properties: - const: i2s_hclk dmas: - items: - - description: TX DMA Channel - - description: RX DMA Channel + minItems: 1 + maxItems: 2 dma-names: - items: - - const: tx + oneOf: - const: rx + - items: + - const: tx + - const: rx power-domains: maxItems: 1 rockchip,capture-channels: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 default: 2 description: Max capture channels, if not set, 2 channels default. rockchip,playback-channels: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32 default: 8 description: Max playback channels, if not set, 8 channels default. diff --git a/Bindings/sound/rt1016.txt b/Bindings/sound/rt1016.txt new file mode 100644 index 000000000000..2310f8ff259b --- /dev/null +++ b/Bindings/sound/rt1016.txt @@ -0,0 +1,17 @@ +RT1016 Stereo Class D Audio Amplifier + +This device supports I2C only. + +Required properties: + +- compatible : "realtek,rt1016". + +- reg : The I2C address of the device. + + +Example: + +rt1016: codec@1a { + compatible = "realtek,rt1016"; + reg = <0x1a>; +}; diff --git a/Bindings/sound/simple-card.txt b/Bindings/sound/simple-card.txt deleted file mode 100644 index 79954cd6e37b..000000000000 --- a/Bindings/sound/simple-card.txt +++ /dev/null @@ -1,351 +0,0 @@ -Simple-Card: - -Simple-Card specifies audio DAI connections of SoC <-> codec. - -Required properties: - -- compatible : "simple-audio-card" - -Optional properties: - -- simple-audio-card,name : User specified audio sound card name, one string - property. -- simple-audio-card,widgets : Please refer to widgets.txt. -- simple-audio-card,routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. -- simple-audio-card,mclk-fs : Multiplication factor between stream rate and codec - mclk. When defined, mclk-fs property defined in - dai-link sub nodes are ignored. -- simple-audio-card,hp-det-gpio : Reference to GPIO that signals when - headphones are attached. -- simple-audio-card,mic-det-gpio : Reference to GPIO that signals when - a microphone is attached. -- simple-audio-card,aux-devs : List of phandles pointing to auxiliary devices, such - as amplifiers, to be added to the sound card. -- simple-audio-card,pin-switches : List of strings containing the widget names for - which pin switches must be created. - -Optional subnodes: - -- simple-audio-card,dai-link : Container for dai-link level - properties and the CPU and CODEC - sub-nodes. This container may be - omitted when the card has only one - DAI link. See the examples and the - section below. - -Dai-link subnode properties and subnodes: - -If dai-link subnode is omitted and the subnode properties are directly -under "sound"-node the subnode property and subnode names have to be -prefixed with "simple-audio-card,"-prefix. - -Required dai-link subnodes: - -- cpu : CPU sub-node -- codec : CODEC sub-node - -Optional dai-link subnode properties: - -- format : CPU/CODEC common audio format. - "i2s", "right_j", "left_j" , "dsp_a" - "dsp_b", "ac97", "pdm", "msb", "lsb" -- frame-master : Indicates dai-link frame master. - phandle to a cpu or codec subnode. -- bitclock-master : Indicates dai-link bit clock master. - phandle to a cpu or codec subnode. -- bitclock-inversion : bool property. Add this if the - dai-link uses bit clock inversion. -- frame-inversion : bool property. Add this if the - dai-link uses frame clock inversion. -- mclk-fs : Multiplication factor between stream - rate and codec mclk, applied only for - the dai-link. - -For backward compatibility the frame-master and bitclock-master -properties can be used as booleans in codec subnode to indicate if the -codec is the dai-link frame or bit clock master. In this case there -should be no dai-link node, the same properties should not be present -at sound-node level, and the bitclock-inversion and frame-inversion -properties should also be placed in the codec node if needed. - -Required CPU/CODEC subnodes properties: - -- sound-dai : phandle and port of CPU/CODEC - -Optional CPU/CODEC subnodes properties: - -- dai-tdm-slot-num : Please refer to tdm-slot.txt. -- dai-tdm-slot-width : Please refer to tdm-slot.txt. -- clocks / system-clock-frequency : specify subnode's clock if needed. - it can be specified via "clocks" if system has - clock node (= common clock), or "system-clock-frequency" - (if system doens't support common clock) - If a clock is specified, it is - enabled with clk_prepare_enable() - in dai startup() and disabled with - clk_disable_unprepare() in dai - shutdown(). - If a clock is specified and a - multiplication factor is given with - mclk-fs, the clock will be set to the - calculated mclk frequency when the - stream starts. -- system-clock-direction-out : specifies clock direction as 'out' on - initialization. It is useful for some aCPUs with - fixed clocks. - -------------------------------------------- -Example 1 - single DAI link: -------------------------------------------- - -sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "VF610-Tower-Sound-Card"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&dailink0_master>; - simple-audio-card,frame-master = <&dailink0_master>; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Headphone", "Headphone Jack", - "Speaker", "External Speaker"; - simple-audio-card,routing = - "MIC_IN", "Microphone Jack", - "Headphone Jack", "HP_OUT", - "External Speaker", "LINE_OUT"; - - simple-audio-card,cpu { - sound-dai = <&sh_fsi2 0>; - }; - - dailink0_master: simple-audio-card,codec { - sound-dai = <&ak4648>; - clocks = <&osc>; - }; -}; - -&i2c0 { - ak4648: ak4648@12 { - #sound-dai-cells = <0>; - compatible = "asahi-kasei,ak4648"; - reg = <0x12>; - }; -}; - -sh_fsi2: sh_fsi2@ec230000 { - #sound-dai-cells = <1>; - compatible = "renesas,sh_fsi2"; - reg = <0xec230000 0x400>; - interrupt-parent = <&gic>; - interrupts = <0 146 0x4>; -}; - -------------------------------------------- -Example 2 - many DAI links: -------------------------------------------- - -sound { - compatible = "simple-audio-card"; - simple-audio-card,name = "Cubox Audio"; - - simple-audio-card,dai-link@0 { /* I2S - HDMI */ - reg = <0>; - format = "i2s"; - cpu { - sound-dai = <&audio1 0>; - }; - codec { - sound-dai = <&tda998x 0>; - }; - }; - - simple-audio-card,dai-link@1 { /* S/PDIF - HDMI */ - reg = <1>; - cpu { - sound-dai = <&audio1 1>; - }; - codec { - sound-dai = <&tda998x 1>; - }; - }; - - simple-audio-card,dai-link@2 { /* S/PDIF - S/PDIF */ - reg = <2>; - cpu { - sound-dai = <&audio1 1>; - }; - codec { - sound-dai = <&spdif_codec>; - }; - }; -}; - -------------------------------------------- -Example 3 - route audio from IMX6 SSI2 through TLV320DAC3100 codec -through TPA6130A2 amplifier to headphones: -------------------------------------------- - -&i2c0 { - codec: tlv320dac3100@18 { - compatible = "ti,tlv320dac3100"; - ... - } - - amp: tpa6130a2@60 { - compatible = "ti,tpa6130a2"; - ... - } -} - -sound { - compatible = "simple-audio-card"; - ... - simple-audio-card,widgets = - "Headphone", "Headphone Jack"; - simple-audio-card,routing = - "Headphone Jack", "HPLEFT", - "Headphone Jack", "HPRIGHT", - "LEFTIN", "HPL", - "RIGHTIN", "HPR"; - simple-audio-card,aux-devs = <&>; - simple-audio-card,cpu { - sound-dai = <&ssi2>; - }; - simple-audio-card,codec { - sound-dai = <&codec>; - clocks = ... - }; -}; - -------------------------------------------- -Example 4. Sampling Rate Conversion -------------------------------------------- - -sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "rsnd-ak4643"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&sndcodec>; - simple-audio-card,frame-master = <&sndcodec>; - - simple-audio-card,convert-rate = <48000>; - - simple-audio-card,prefix = "ak4642"; - simple-audio-card,routing = "ak4642 Playback", "DAI0 Playback", - "DAI0 Capture", "ak4642 Capture"; - - sndcpu: simple-audio-card,cpu { - sound-dai = <&rcar_sound>; - }; - - sndcodec: simple-audio-card,codec { - sound-dai = <&ak4643>; - system-clock-frequency = <11289600>; - }; -}; - -------------------------------------------- -Example 5. 2 CPU 1 Codec (Mixing) -------------------------------------------- -sound { - compatible = "simple-audio-card"; - - simple-audio-card,name = "rsnd-ak4643"; - simple-audio-card,format = "left_j"; - simple-audio-card,bitclock-master = <&dpcmcpu>; - simple-audio-card,frame-master = <&dpcmcpu>; - - simple-audio-card,routing = "ak4642 Playback", "DAI0 Playback", - "ak4642 Playback", "DAI1 Playback"; - - dpcmcpu: cpu@0 { - sound-dai = <&rcar_sound 0>; - }; - - cpu@1 { - sound-dai = <&rcar_sound 1>; - }; - - codec { - prefix = "ak4642"; - sound-dai = <&ak4643>; - clocks = <&audio_clock>; - }; -}; - -------------------------------------------- -Example 6 - many DAI links with DPCM: -------------------------------------------- - -CPU0 ------ ak4613 -CPU1 ------ PCM3168A-p /* DPCM 1ch/2ch */ -CPU2 --/ /* DPCM 3ch/4ch */ -CPU3 --/ /* DPCM 5ch/6ch */ -CPU4 --/ /* DPCM 7ch/8ch */ -CPU5 ------ PCM3168A-c - -sound { - compatible = "simple-audio-card"; - - simple-audio-card,routing = - "pcm3168a Playback", "DAI1 Playback", - "pcm3168a Playback", "DAI2 Playback", - "pcm3168a Playback", "DAI3 Playback", - "pcm3168a Playback", "DAI4 Playback"; - - simple-audio-card,dai-link@0 { - format = "left_j"; - bitclock-master = <&sndcpu0>; - frame-master = <&sndcpu0>; - - sndcpu0: cpu { - sound-dai = <&rcar_sound 0>; - }; - codec { - sound-dai = <&ak4613>; - }; - }; - simple-audio-card,dai-link@1 { - format = "i2s"; - bitclock-master = <&sndcpu1>; - frame-master = <&sndcpu1>; - - convert-channels = <8>; /* TDM Split */ - - sndcpu1: cpu@0 { - sound-dai = <&rcar_sound 1>; - }; - cpu@1 { - sound-dai = <&rcar_sound 2>; - }; - cpu@2 { - sound-dai = <&rcar_sound 3>; - }; - cpu@3 { - sound-dai = <&rcar_sound 4>; - }; - codec { - mclk-fs = <512>; - prefix = "pcm3168a"; - dai-tdm-slot-num = <8>; - sound-dai = <&pcm3168a 0>; - }; - }; - simple-audio-card,dai-link@2 { - format = "i2s"; - bitclock-master = <&sndcpu2>; - frame-master = <&sndcpu2>; - - sndcpu2: cpu { - sound-dai = <&rcar_sound 5>; - }; - codec { - mclk-fs = <512>; - prefix = "pcm3168a"; - sound-dai = <&pcm3168a 1>; - }; - }; -}; diff --git a/Bindings/sound/simple-card.yaml b/Bindings/sound/simple-card.yaml new file mode 100644 index 000000000000..35e669020296 --- /dev/null +++ b/Bindings/sound/simple-card.yaml @@ -0,0 +1,491 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/simple-card.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple Audio Card Driver Device Tree Bindings + +maintainers: + - Kuninori Morimoto + +definitions: + + frame-master: + description: Indicates dai-link frame master. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + + bitclock-master: + description: Indicates dai-link bit clock master + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + + frame-inversion: + description: dai-link uses frame clock inversion + $ref: /schemas/types.yaml#/definitions/flag + + bitclock-inversion: + description: dai-link uses bit clock inversion + $ref: /schemas/types.yaml#/definitions/flag + + dai-tdm-slot-num: + description: see tdm-slot.txt. + $ref: /schemas/types.yaml#/definitions/uint32 + + dai-tdm-slot-width: + description: see tdm-slot.txt. + $ref: /schemas/types.yaml#/definitions/uint32 + + system-clock-frequency: + description: | + If a clock is specified and a multiplication factor is given with + mclk-fs, the clock will be set to the calculated mclk frequency + when the stream starts. + $ref: /schemas/types.yaml#/definitions/uint32 + + system-clock-direction-out: + description: | + specifies clock direction as 'out' on initialization. + It is useful for some aCPUs with fixed clocks. + $ref: /schemas/types.yaml#/definitions/flag + + mclk-fs: + description: | + Multiplication factor between stream rate and codec mclk. + When defined, mclk-fs property defined in dai-link sub nodes are ignored. + $ref: /schemas/types.yaml#/definitions/uint32 + + aux-devs: + description: | + List of phandles pointing to auxiliary devices, such + as amplifiers, to be added to the sound card. + $ref: /schemas/types.yaml#/definitions/phandle-array + + convert-rate: + description: CPU to Codec rate convert. + $ref: /schemas/types.yaml#/definitions/uint32 + + convert-channels: + description: CPU to Codec rate channels. + $ref: /schemas/types.yaml#/definitions/uint32 + + prefix: + description: "device name prefix" + $ref: /schemas/types.yaml#/definitions/string + + label: + maxItems: 1 + + routing: + description: | + A list of the connections between audio components. + Each entry is a pair of strings, the first being the + connection's sink, the second being the connection's source. + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + + widgets: + description: User specified audio sound widgets. + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + + pin-switches: + description: the widget names for which pin switches must be created. + $ref: /schemas/types.yaml#/definitions/string-array + + format: + description: audio format. + items: + enum: + - i2s + - right_j + - left_j + - dsp_a + - dsp_b + - ac97 + - pdm + - msb + - lsb + + dai: + type: object + properties: + sound-dai: + maxItems: 1 + + # common properties + mclk-fs: + $ref: "#/definitions/mclk-fs" + prefix: + $ref: "#/definitions/prefix" + frame-inversion: + $ref: "#/definitions/frame-inversion" + bitclock-inversion: + $ref: "#/definitions/bitclock-inversion" + frame-master: + $ref: /schemas/types.yaml#/definitions/flag + bitclock-master: + $ref: /schemas/types.yaml#/definitions/flag + + dai-tdm-slot-num: + $ref: "#/definitions/dai-tdm-slot-num" + dai-tdm-slot-width: + $ref: "#/definitions/dai-tdm-slot-width" + clocks: + maxItems: 1 + system-clock-frequency: + $ref: "#/definitions/system-clock-frequency" + system-clock-direction-out: + $ref: "#/definitions/system-clock-direction-out" + required: + - sound-dai + +properties: + compatible: + contains: + enum: + - simple-audio-card + - simple-scu-audio-card + + "#address-cells": + const: 1 + "#size-cells": + const: 0 + + label: + $ref: "#/definitions/label" + + simple-audio-card,name: + description: User specified audio sound card name. + $ref: /schemas/types.yaml#/definitions/string + +# use patternProperties to avoid naming "xxx,yyy" issue +patternProperties: + "^simple-audio-card,widgets$": + $ref: "#/definitions/widgets" + "^simple-audio-card,routing$": + $ref: "#/definitions/routing" + "^simple-audio-card,cpu(@[0-9a-f]+)?": + $ref: "#/definitions/dai" + "^simple-audio-card,codec(@[0-9a-f]+)?": + $ref: "#/definitions/dai" + + # common properties + "^simple-audio-card,frame-master$": + $ref: "#/definitions/frame-master" + "^simple-audio-card,bitclock-master$": + $ref: "#/definitions/bitclock-master" + "^simple-audio-card,frame-inversion$": + $ref: "#/definitions/frame-inversion" + "^simple-audio-card,bitclock-inversion$": + $ref: "#/definitions/bitclock-inversion" + "^simple-audio-card,format$": + $ref: "#/definitions/format" + "^simple-audio-card,mclk-fs$": + $ref: "#/definitions/mclk-fs" + "^simple-audio-card,aux-devs$": + $ref: "#/definitions/aux-devs" + "^simple-audio-card,convert-rate$": + $ref: "#/definitions/convert-rate" + "^simple-audio-card,convert-channels$": + $ref: "#/definitions/convert-channels" + "^simple-audio-card,prefix$": + $ref: "#/definitions/prefix" + "^simple-audio-card,pin-switches$": + $ref: "#/definitions/pin-switches" + "^simple-audio-card,hp-det-gpio$": + maxItems: 1 + "^simple-audio-card,mic-det-gpio$": + maxItems: 1 + + "^simple-audio-card,dai-link(@[0-9a-f]+)?$": + description: | + Container for dai-link level properties and the CPU and CODEC sub-nodes. + This container may be omitted when the card has only one DAI link. + type: object + properties: + reg: + maxItems: 1 + + # common properties + frame-master: + $ref: "#/definitions/frame-master" + bitclock-master: + $ref: "#/definitions/bitclock-master" + frame-inversion: + $ref: "#/definitions/frame-inversion" + bitclock-inversion: + $ref: "#/definitions/bitclock-inversion" + format: + $ref: "#/definitions/format" + mclk-fs: + $ref: "#/definitions/mclk-fs" + aux-devs: + $ref: "#/definitions/aux-devs" + convert-rate: + $ref: "#/definitions/convert-rate" + convert-channels: + $ref: "#/definitions/convert-channels" + prefix: + $ref: "#/definitions/prefix" + pin-switches: + $ref: "#/definitions/pin-switches" + hp-det-gpio: + maxItems: 1 + mic-det-gpio: + maxItems: 1 + + patternProperties: + "^cpu(@[0-9a-f]+)?": + $ref: "#/definitions/dai" + "^codec(@[0-9a-f]+)?": + $ref: "#/definitions/dai" + additionalProperties: false + +required: + - compatible + +additionalProperties: false + +examples: +#-------------------- +# single DAI link +#-------------------- + - | + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "VF610-Tower-Sound-Card"; + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Speaker", "External Speaker"; + simple-audio-card,routing = + "MIC_IN", "Microphone Jack", + "Headphone Jack", "HP_OUT", + "External Speaker", "LINE_OUT"; + + simple-audio-card,cpu { + sound-dai = <&sh_fsi2 0>; + }; + + dailink0_master: simple-audio-card,codec { + sound-dai = <&ak4648>; + clocks = <&osc>; + }; + }; + +#-------------------- +# Multi DAI links +#-------------------- + - | + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "Cubox Audio"; + + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { /* I2S - HDMI */ + reg = <0>; + format = "i2s"; + cpu { + sound-dai = <&audio0>; + }; + codec { + sound-dai = <&tda998x0>; + }; + }; + + simple-audio-card,dai-link@1 { /* S/PDIF - HDMI */ + reg = <1>; + cpu { + sound-dai = <&audio1>; + }; + codec { + sound-dai = <&tda998x1>; + }; + }; + + simple-audio-card,dai-link@2 { /* S/PDIF - S/PDIF */ + reg = <2>; + cpu { + sound-dai = <&audio2>; + }; + codec { + sound-dai = <&spdif_codec>; + }; + }; + }; + +#-------------------- +# route audio from IMX6 SSI2 through TLV320DAC3100 codec +# through TPA6130A2 amplifier to headphones: +#-------------------- + - | + sound { + compatible = "simple-audio-card"; + + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT", + "LEFTIN", "HPL", + "RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&>; + simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clocks>; + }; + }; + +#-------------------- +# Sampling Rate Conversion +#-------------------- + - | + sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "rsnd-ak4643"; + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + simple-audio-card,convert-rate = <48000>; + + simple-audio-card,prefix = "ak4642"; + simple-audio-card,routing = "ak4642 Playback", "DAI0 Playback", + "DAI0 Capture", "ak4642 Capture"; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + system-clock-frequency = <11289600>; + }; + }; + +#-------------------- +# 2 CPU 1 Codec (Mixing) +#-------------------- + - | + sound { + compatible = "simple-audio-card"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,name = "rsnd-ak4643"; + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&dpcmcpu>; + simple-audio-card,frame-master = <&dpcmcpu>; + + simple-audio-card,convert-rate = <48000>; + simple-audio-card,convert-channels = <2>; + + simple-audio-card,routing = "ak4642 Playback", "DAI0 Playback", + "ak4642 Playback", "DAI1 Playback"; + + dpcmcpu: simple-audio-card,cpu@0 { + reg = <0>; + sound-dai = <&rcar_sound 0>; + }; + + simple-audio-card,cpu@1 { + reg = <1>; + sound-dai = <&rcar_sound 1>; + }; + + simple-audio-card,codec { + prefix = "ak4642"; + sound-dai = <&ak4643>; + clocks = <&audio_clock>; + }; + }; + +#-------------------- +# Multi DAI links with DPCM: +# +# CPU0 ------ ak4613 +# CPU1 ------ PCM3168A-p /* DPCM 1ch/2ch */ +# CPU2 --/ /* DPCM 3ch/4ch */ +# CPU3 --/ /* DPCM 5ch/6ch */ +# CPU4 --/ /* DPCM 7ch/8ch */ +# CPU5 ------ PCM3168A-c +#-------------------- + - | + sound { + compatible = "simple-audio-card"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,routing = + "pcm3168a Playback", "DAI1 Playback", + "pcm3168a Playback", "DAI2 Playback", + "pcm3168a Playback", "DAI3 Playback", + "pcm3168a Playback", "DAI4 Playback"; + + simple-audio-card,dai-link@0 { + reg = <0>; + format = "left_j"; + bitclock-master = <&sndcpu0>; + frame-master = <&sndcpu0>; + + sndcpu0: cpu { + sound-dai = <&rcar_sound 0>; + }; + codec { + sound-dai = <&ak4613>; + }; + }; + + simple-audio-card,dai-link@1 { + reg = <1>; + format = "i2s"; + bitclock-master = <&sndcpu1>; + frame-master = <&sndcpu1>; + + convert-channels = <8>; /* TDM Split */ + + sndcpu1: cpu0 { + sound-dai = <&rcar_sound 1>; + }; + cpu1 { + sound-dai = <&rcar_sound 2>; + }; + cpu2 { + sound-dai = <&rcar_sound 3>; + }; + cpu3 { + sound-dai = <&rcar_sound 4>; + }; + codec { + mclk-fs = <512>; + prefix = "pcm3168a"; + dai-tdm-slot-num = <8>; + sound-dai = <&pcm3168a 0>; + }; + }; + + simple-audio-card,dai-link@2 { + reg = <2>; + format = "i2s"; + bitclock-master = <&sndcpu2>; + frame-master = <&sndcpu2>; + + sndcpu2: cpu { + sound-dai = <&rcar_sound 5>; + }; + codec { + mclk-fs = <512>; + prefix = "pcm3168a"; + sound-dai = <&pcm3168a 1>; + }; + }; + }; diff --git a/Bindings/sound/st,sti-asoc-card.txt b/Bindings/sound/st,sti-asoc-card.txt index 4d51f3f5ea98..a6ffcdec6f6a 100644 --- a/Bindings/sound/st,sti-asoc-card.txt +++ b/Bindings/sound/st,sti-asoc-card.txt @@ -5,7 +5,7 @@ codec or external codecs. sti sound drivers allows to expose sti SoC audio interface through the generic ASoC simple card. For details about sound card declaration please refer to -Documentation/devicetree/bindings/sound/simple-card.txt. +Documentation/devicetree/bindings/sound/simple-card.yaml. 1) sti-uniperiph-dai: audio dai device. --------------------------------------- diff --git a/Bindings/sound/tdm-slot.txt b/Bindings/sound/tdm-slot.txt index 34cf70e2cbc4..4bb513ae62fc 100644 --- a/Bindings/sound/tdm-slot.txt +++ b/Bindings/sound/tdm-slot.txt @@ -14,8 +14,8 @@ For instance: dai-tdm-slot-tx-mask = <0 1>; dai-tdm-slot-rx-mask = <1 0>; -And for each spcified driver, there could be one .of_xlate_tdm_slot_mask() -to specify a explicit mapping of the channels and the slots. If it's absent +And for each specified driver, there could be one .of_xlate_tdm_slot_mask() +to specify an explicit mapping of the channels and the slots. If it's absent the default snd_soc_of_xlate_tdm_slot_mask() will be used to generating the tx and rx masks. diff --git a/Bindings/sound/tlv320adcx140.yaml b/Bindings/sound/tlv320adcx140.yaml index ab2268c0ee67..2e6ac5d2ee96 100644 --- a/Bindings/sound/tlv320adcx140.yaml +++ b/Bindings/sound/tlv320adcx140.yaml @@ -49,9 +49,8 @@ properties: 0 - Mic bias is set to VREF 1 - Mic bias is set to VREF × 1.096 6 - Mic bias is set to AVDD - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [0, 1, 6] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 6] ti,vref-source: description: | @@ -59,9 +58,55 @@ properties: 0 - Set VREF to 2.75V 1 - Set VREF to 2.5V 2 - Set VREF to 1.375V - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [0, 1, 2] + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + + ti,pdm-edge-select: + description: | + Defines the PDMCLK sampling edge configuration for the PDM inputs. This + array is defined as . + + 0 - (default) Odd channel is latched on the negative edge and even + channel is latched on the the positive edge. + 1 - Odd channel is latched on the positive edge and even channel is + latched on the the negative edge. + + PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data + PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data + PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data + PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data + + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + maximum: 1 + default: [0, 0, 0, 0] + + ti,gpi-config: + description: | + Defines the configuration for the general purpose input pins (GPI). + The array is defined as . + + 0 - (default) disabled + 1 - GPIX is configured as a general-purpose input (GPI) + 2 - GPIX is configured as a master clock input (MCLK) + 3 - GPIX is configured as an ASI input for daisy-chain (SDIN) + 4 - GPIX is configured as a PDM data input for channel 1 and channel + (PDMDIN1) + 5 - GPIX is configured as a PDM data input for channel 3 and channel + (PDMDIN2) + 6 - GPIX is configured as a PDM data input for channel 5 and channel + (PDMDIN3) + 7 - GPIX is configured as a PDM data input for channel 7 and channel + (PDMDIN4) + + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + maximum: 7 + default: [0, 0, 0, 0] required: - compatible @@ -77,6 +122,8 @@ examples: compatible = "ti,tlv320adc5140"; reg = <0x4c>; ti,mic-bias-source = <6>; + ti,pdm-edge-select = <0 1 0 1>; + ti,gpi-config = <4 5 6 7>; reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; }; }; diff --git a/Bindings/sound/wlf,arizona.txt b/Bindings/sound/wlf,arizona.txt deleted file mode 100644 index e172c62dc2df..000000000000 --- a/Bindings/sound/wlf,arizona.txt +++ /dev/null @@ -1,53 +0,0 @@ -Cirrus Logic Arizona class audio SoCs - -These devices are audio SoCs with extensive digital capabilities and a range -of analogue I/O. - -This document lists sound specific bindings, see the primary binding -document: - ../mfd/arizona.txt - -Optional properties: - - - wlf,inmode : A list of INn_MODE register values, where n is the number - of input signals. Valid values are 0 (Differential), 1 (Single-ended) and - 2 (Digital Microphone). If absent, INn_MODE registers set to 0 by default. - If present, values must be specified less than or equal to the number of - input signals. If values less than the number of input signals, elements - that have not been specified are set to 0 by default. Entries are: - (wm5102, wm5110, wm8280, wm8997) - (wm8998, wm1814) - - wlf,out-mono : A list of boolean values indicating whether each output is - mono or stereo. Position within the list indicates the output affected - (eg. First entry in the list corresponds to output 1). A non-zero value - indicates a mono output. If present, the number of values should be less - than or equal to the number of outputs, if less values are supplied the - additional outputs will be treated as stereo. - - - wlf,dmic-ref : DMIC reference voltage source for each input, can be - selected from either MICVDD or one of the MICBIAS's, defines - (ARIZONA_DMIC_xxxx) are provided in . If - present, the number of values should be less than or equal to the - number of inputs, unspecified inputs will use the chip default. - - - wlf,max-channels-clocked : The maximum number of channels to be clocked on - each AIF, useful for I2S systems with multiple data lines being mastered. - Specify one cell for each AIF to be configured, specify zero for AIFs that - should be handled normally. - If present, number of cells must be less than or equal to the number of - AIFs. If less than the number of AIFs, for cells that have not been - specified the corresponding AIFs will be treated as default setting. - - - wlf,spk-fmt : PDM speaker data format, must contain 2 cells (OUT5 and OUT6). - See the datasheet for values. - The second cell is ignored for codecs that do not have OUT6 (wm5102, wm8997, - wm8998, wm1814) - - - wlf,spk-mute : PDM speaker mute setting, must contain 2 cells (OUT5 and OUT6). - See the datasheet for values. - The second cell is ignored for codecs that do not have OUT6 (wm5102, wm8997, - wm8998, wm1814) - - - wlf,out-volume-limit : The volume limit value that should be applied to each - output channel. See the datasheet for exact values. Channels are specified - in the order OUT1L, OUT1R, OUT2L, OUT2R, etc. diff --git a/Bindings/sound/wlf,arizona.yaml b/Bindings/sound/wlf,arizona.yaml new file mode 100644 index 000000000000..22d54be7900a --- /dev/null +++ b/Bindings/sound/wlf,arizona.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/wlf,arizona.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic/Wolfson Microelectronics Arizona class audio SoCs + +maintainers: + - patches@opensource.cirrus.com + +description: | + These devices are audio SoCs with extensive digital capabilities and a range + of analogue I/O. + + This document lists sound specific bindings, see the primary binding + document ../mfd/arizona.yaml + +properties: + '#sound-dai-cells': + description: + The first cell indicating the audio interface. + const: 1 + + wlf,inmode: + description: + A list of INn_MODE register values, where n is the number of input + signals. Valid values are 0 (Differential), 1 (Single-ended) and + 2 (Digital Microphone). If absent, INn_MODE registers set to 0 by + default. If present, values must be specified less than or equal + to the number of input signals. If values less than the number of + input signals, elements that have not been specified are set to 0 by + default. Entries are (wm5102, wm5110, wm8280, + wm8997) and (wm8998, wm1814) + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + minimum: 0 + maximum: 2 + default: 0 + + wlf,out-mono: + description: + A list of boolean values indicating whether each output is mono + or stereo. Position within the list indicates the output affected + (eg. First entry in the list corresponds to output 1). A non-zero + value indicates a mono output. If present, the number of values + should be less than or equal to the number of outputs, if less values + are supplied the additional outputs will be treated as stereo. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 6 + items: + minimum: 0 + maximum: 1 + default: 0 + + wlf,dmic-ref: + description: + DMIC reference voltage source for each input, can be selected from + either MICVDD or one of the MICBIAS's, defines (ARIZONA_DMIC_xxxx) + are provided in dt-bindings/mfd/arizona.h. If present, the number + of values should be less than or equal to the number of inputs, + unspecified inputs will use the chip default. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + minimum: 0 + maximum: 3 + default: 0 + + wlf,max-channels-clocked: + description: + The maximum number of channels to be clocked on each AIF, useful for + I2S systems with multiple data lines being mastered. Specify one + cell for each AIF to be configured, specify zero for AIFs that should + be handled normally. If present, number of cells must be less than + or equal to the number of AIFs. If less than the number of AIFs, for + cells that have not been specified the corresponding AIFs will be + treated as default setting. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 3 + items: + default: 0 + + wlf,spk-fmt: + description: + PDM speaker data format, must contain 2 cells (OUT5 and OUT6). See + the datasheet for values. The second cell is ignored for codecs that + do not have OUT6 (wm5102, wm8997, wm8998, wm1814) + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + + wlf,spk-mute: + description: + PDM speaker mute setting, must contain 2 cells (OUT5 and OUT6). See + the datasheet for values. The second cell is ignored for codecs that + do not have OUT6 (wm5102, wm8997, wm8998, wm1814) + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + + wlf,out-volume-limit: + description: + The volume limit value that should be applied to each output + channel. See the datasheet for exact values. Channels are specified + in the order OUT1L, OUT1R, OUT2L, OUT2R, etc. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 12 diff --git a/Bindings/sound/wm8994.txt b/Bindings/sound/wm8994.txt index 68cccc4653ba..367b58ce1bb9 100644 --- a/Bindings/sound/wm8994.txt +++ b/Bindings/sound/wm8994.txt @@ -14,9 +14,15 @@ Required properties: - #gpio-cells : Must be 2. The first cell is the pin number and the second cell is used to specify optional parameters (currently unused). - - AVDD2-supply, DBVDD1-supply, DBVDD2-supply, DBVDD3-supply, CPVDD-supply, - SPKVDD1-supply, SPKVDD2-supply : power supplies for the device, as covered - in Documentation/devicetree/bindings/regulator/regulator.txt + - power supplies for the device, as covered in + Documentation/devicetree/bindings/regulator/regulator.txt, depending + on compatible: + - for wlf,wm1811 and wlf,wm8958: + AVDD1-supply, AVDD2-supply, DBVDD1-supply, DBVDD2-supply, DBVDD3-supply, + DCVDD-supply, CPVDD-supply, SPKVDD1-supply, SPKVDD2-supply + - for wlf,wm8994: + AVDD1-supply, AVDD2-supply, DBVDD-supply, DCVDD-supply, CPVDD-supply, + SPKVDD1-supply, SPKVDD2-supply Optional properties: @@ -73,11 +79,11 @@ wm8994: codec@1a { lineout1-se; + AVDD1-supply = <®ulator>; AVDD2-supply = <®ulator>; CPVDD-supply = <®ulator>; - DBVDD1-supply = <®ulator>; - DBVDD2-supply = <®ulator>; - DBVDD3-supply = <®ulator>; + DBVDD-supply = <®ulator>; + DCVDD-supply = <®ulator>; SPKVDD1-supply = <®ulator>; SPKVDD2-supply = <®ulator>; }; diff --git a/Bindings/sound/zl38060.yaml b/Bindings/sound/zl38060.yaml new file mode 100644 index 000000000000..338e2a13c775 --- /dev/null +++ b/Bindings/sound/zl38060.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/zl38060.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZL38060 Connected Home Audio Processor from Microsemi. + +description: | + The ZL38060 is a "Connected Home Audio Processor" from Microsemi, + which consists of a Digital Signal Processor (DSP), several Digital + Audio Interfaces (DAIs), analog outputs, and a block of 14 GPIOs. + +maintainers: + - Jaroslav Kysela + - Takashi Iwai + +properties: + compatible: + const: mscc,zl38060 + + reg: + description: + SPI device address. + maxItems: 1 + + spi-max-frequency: + maximum: 24000000 + + reset-gpios: + description: + A GPIO line handling reset of the chip. As the line is active low, + it should be marked GPIO_ACTIVE_LOW (see ../gpio/gpio.txt) + maxItems: 1 + + '#gpio-cells': + const: 2 + + gpio-controller: true + + '#sound-dai-cells': + const: 0 + +required: + - compatible + - reg + - '#gpio-cells' + - gpio-controller + - '#sound-dai-cells' + +additionalProperties: false + +examples: + - | + #include + spi0 { + #address-cells = <1>; + #size-cells = <0>; + + codec: zl38060@0 { + gpio-controller; + #gpio-cells = <2>; + #sound-dai-cells = <0>; + compatible = "mscc,zl38060"; + reg = <0>; + spi-max-frequency = <12000000>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Bindings/spi/amlogic,meson-gx-spicc.yaml b/Bindings/spi/amlogic,meson-gx-spicc.yaml index 9147df29022a..38efb50081e3 100644 --- a/Bindings/spi/amlogic,meson-gx-spicc.yaml +++ b/Bindings/spi/amlogic,meson-gx-spicc.yaml @@ -34,12 +34,15 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + items: + - description: controller register bus clock + - description: baud rate generator and delay control clock clock-names: - description: input clock for the baud rate generator - items: - - const: core + minItems: 1 + maxItems: 2 if: properties: @@ -51,17 +54,22 @@ if: then: properties: clocks: - contains: - items: - - description: controller register bus clock - - description: baud rate generator and delay control clock + minItems: 2 clock-names: - minItems: 2 items: - const: core - const: pclk +else: + properties: + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + required: - compatible - reg diff --git a/Bindings/spi/brcm,spi-bcm-qspi.txt b/Bindings/spi/brcm,spi-bcm-qspi.txt index ad7ac80a3841..f5e518d099f2 100644 --- a/Bindings/spi/brcm,spi-bcm-qspi.txt +++ b/Bindings/spi/brcm,spi-bcm-qspi.txt @@ -26,6 +26,16 @@ Required properties: "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI BRCMSTB SoCs + "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs + "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs + "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs + "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs + "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI + BRCMSTB SoCs "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi" : NS2 SoCs diff --git a/Bindings/spi/marvell,mmp2-ssp.yaml b/Bindings/spi/marvell,mmp2-ssp.yaml new file mode 100644 index 000000000000..0abcac385e7c --- /dev/null +++ b/Bindings/spi/marvell,mmp2-ssp.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2019,2020 Lubomir Rintel +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/marvell,mmp2-ssp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PXA2xx SSP SPI Controller bindings + +maintainers: + - Lubomir Rintel + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + const: marvell,mmp2-ssp + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + ready-gpios: + description: | + GPIO used to signal a SPI master that the FIFO is filled and we're + ready to service a transfer. Only useful in slave mode. + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +dependencies: + ready-gpios: [ spi-slave ] + +unevaluatedProperties: false + +examples: + - | + #include + spi@d4035000 { + compatible = "marvell,mmp2-ssp"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xd4035000 0x1000>; + clocks = <&soc_clocks MMP2_CLK_SSP0>; + interrupts = <0>; + }; + +... diff --git a/Bindings/spi/mikrotik,rb4xx-spi.yaml b/Bindings/spi/mikrotik,rb4xx-spi.yaml new file mode 100644 index 000000000000..4ddb42a4ae05 --- /dev/null +++ b/Bindings/spi/mikrotik,rb4xx-spi.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/mikrotik,rb4xx-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MikroTik RB4xx series SPI master + +maintainers: + - Gabor Juhos + - Bert Vermeulen + +allOf: + - $ref: "spi-controller.yaml#" + +properties: + compatible: + const: mikrotik,rb4xx-spi + + reg: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + spi: spi@1f000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mikrotik,rb4xx-spi"; + reg = <0x1f000000 0x10>; + }; + +... \ No newline at end of file diff --git a/Bindings/spi/qcom,spi-geni-qcom.txt b/Bindings/spi/qcom,spi-geni-qcom.txt index 790311a42bf1..c8c1e913f4e7 100644 --- a/Bindings/spi/qcom,spi-geni-qcom.txt +++ b/Bindings/spi/qcom,spi-geni-qcom.txt @@ -19,7 +19,7 @@ Required properties: SPI Controller nodes must be child of GENI based Qualcomm Universal Peripharal. Please refer GENI based QUP wrapper controller node bindings -described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt. +described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. SPI slave nodes must be children of the SPI master node and conform to SPI bus binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt. diff --git a/Bindings/spi/qcom,spi-qcom-qspi.yaml b/Bindings/spi/qcom,spi-qcom-qspi.yaml index 5c16cf59ca00..0178831b0662 100644 --- a/Bindings/spi/qcom,spi-qcom-qspi.yaml +++ b/Bindings/spi/qcom,spi-qcom-qspi.yaml @@ -8,12 +8,12 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Qualcomm Quad Serial Peripheral Interface (QSPI) maintainers: - - Mukesh Savaliya - - Akash Asthana + - Mukesh Savaliya + - Akash Asthana -description: - The QSPI controller allows SPI protocol communication in single, dual, or quad - wire transmission modes for read/write access to slaves such as NOR flash. +description: The QSPI controller allows SPI protocol communication in single, + dual, or quad wire transmission modes for read/write access to slaves such + as NOR flash. allOf: - $ref: /spi/spi-controller.yaml# diff --git a/Bindings/spi/renesas,hspi.yaml b/Bindings/spi/renesas,hspi.yaml index c429cf4bea5b..f492cb9fea12 100644 --- a/Bindings/spi/renesas,hspi.yaml +++ b/Bindings/spi/renesas,hspi.yaml @@ -16,8 +16,8 @@ properties: compatible: items: - enum: - - renesas,hspi-r8a7778 # R-Car M1A - - renesas,hspi-r8a7779 # R-Car H1 + - renesas,hspi-r8a7778 # R-Car M1A + - renesas,hspi-r8a7779 # R-Car H1 - const: renesas,hspi reg: diff --git a/Bindings/spi/renesas,rspi.yaml b/Bindings/spi/renesas,rspi.yaml new file mode 100644 index 000000000000..c54ac059043f --- /dev/null +++ b/Bindings/spi/renesas,rspi.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/renesas,rspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas (Quad) Serial Peripheral Interface (RSPI/QSPI) + +maintainers: + - Geert Uytterhoeven + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,rspi-sh7757 # SH7757 + - const: renesas,rspi # Legacy SH + + - items: + - enum: + - renesas,rspi-r7s72100 # RZ/A1H + - renesas,rspi-r7s9210 # RZ/A2 + - const: renesas,rspi-rz # RZ/A + + - items: + - enum: + - renesas,qspi-r8a7743 # RZ/G1M + - renesas,qspi-r8a7744 # RZ/G1N + - renesas,qspi-r8a7745 # RZ/G1E + - renesas,qspi-r8a77470 # RZ/G1C + - renesas,qspi-r8a7790 # R-Car H2 + - renesas,qspi-r8a7791 # R-Car M2-W + - renesas,qspi-r8a7792 # R-Car V2H + - renesas,qspi-r8a7793 # R-Car M2-N + - renesas,qspi-r8a7794 # R-Car E2 + - const: renesas,qspi # R-Car Gen2 and RZ/G1 + + reg: + maxItems: 1 + + interrupts: + oneOf: + - items: + - description: A combined interrupt + - items: + - description: Error interrupt (SPEI) + - description: Receive Interrupt (SPRI) + - description: Transmit Interrupt (SPTI) + + interrupt-names: + oneOf: + - items: + - const: mux + - items: + - const: error + - const: rx + - const: tx + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + dmas: + description: + Must contain a list of pairs of references to DMA specifiers, one for + transmission, and one for reception. + + dma-names: + minItems: 2 + maxItems: 4 + items: + enum: + - tx + - rx + + num-cs: + description: | + Total number of native chip selects. + Hardware limitations related to chip selects: + - When using GPIO chip selects, at least one native chip select must + be left unused, as it will be driven anyway. + minimum: 1 + maximum: 2 + default: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + - '#address-cells' + - '#size-cells' + +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - renesas,rspi-rz + then: + properties: + interrupts: + minItems: 3 + required: + - interrupt-names + + - if: + properties: + compatible: + contains: + enum: + - renesas,qspi + then: + required: + - resets + +examples: + - | + #include + #include + #include + + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7791", "renesas,qspi"; + reg = <0xe6b10000 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 917>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Bindings/spi/renesas,sh-msiof.yaml b/Bindings/spi/renesas,sh-msiof.yaml index b6c1dd2a9c5e..e84edcf8b332 100644 --- a/Bindings/spi/renesas,sh-msiof.yaml +++ b/Bindings/spi/renesas,sh-msiof.yaml @@ -96,43 +96,39 @@ properties: renesas,dtdl: description: delay sync signal (setup) in transmit mode. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: - - 0 # no bit delay - - 50 # 0.5-clock-cycle delay - - 100 # 1-clock-cycle delay - - 150 # 1.5-clock-cycle delay - - 200 # 2-clock-cycle delay + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # no bit delay + - 50 # 0.5-clock-cycle delay + - 100 # 1-clock-cycle delay + - 150 # 1.5-clock-cycle delay + - 200 # 2-clock-cycle delay renesas,syncdl: description: delay sync signal (hold) in transmit mode - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: - - 0 # no bit delay - - 50 # 0.5-clock-cycle delay - - 100 # 1-clock-cycle delay - - 150 # 1.5-clock-cycle delay - - 200 # 2-clock-cycle delay - - 300 # 3-clock-cycle delay + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # no bit delay + - 50 # 0.5-clock-cycle delay + - 100 # 1-clock-cycle delay + - 150 # 1.5-clock-cycle delay + - 200 # 2-clock-cycle delay + - 300 # 3-clock-cycle delay renesas,tx-fifo-size: # deprecated for soctype-specific bindings description: | Override the default TX fifo size. Unit is words. Ignored if 0. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - maxItems: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 default: 64 renesas,rx-fifo-size: # deprecated for soctype-specific bindings description: | Override the default RX fifo size. Unit is words. Ignored if 0. - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - maxItems: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + maxItems: 1 default: 64 required: @@ -149,7 +145,7 @@ examples: msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof"; - reg = <0 0xe6e20000 0 0x0064>; + reg = <0xe6e20000 0x0064>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; dmas = <&dmac0 0x51>, <&dmac0 0x52>; diff --git a/Bindings/spi/snps,dw-apb-ssi.txt b/Bindings/spi/snps,dw-apb-ssi.txt deleted file mode 100644 index 3ed08ee9feba..000000000000 --- a/Bindings/spi/snps,dw-apb-ssi.txt +++ /dev/null @@ -1,41 +0,0 @@ -Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface. - -Required properties: -- compatible : "snps,dw-apb-ssi" or "mscc,-spi", where soc is "ocelot" or - "jaguar2", or "amazon,alpine-dw-apb-ssi" -- reg : The register base for the controller. For "mscc,-spi", a second - register set is required (named ICPU_CFG:SPI_MST) -- interrupts : One interrupt, used by the controller. -- #address-cells : <1>, as required by generic SPI binding. -- #size-cells : <0>, also as required by generic SPI binding. -- clocks : phandles for the clocks, see the description of clock-names below. - The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock - is optional. If a single clock is specified but no clock-name, it is the - "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first. - -Optional properties: -- clock-names : Contains the names of the clocks: - "ssi_clk", for the core clock used to generate the external SPI clock. - "pclk", the interface clock, required for register access. If a clock domain - used to enable this clock then it should be named "pclk_clkdomain". -- cs-gpios : Specifies the gpio pins to be used for chipselects. -- num-cs : The number of chipselects. If omitted, this will default to 4. -- reg-io-width : The I/O register width (in bytes) implemented by this - device. Supported values are 2 or 4 (the default). - -Child nodes as per the generic SPI binding. - -Example: - - spi@fff00000 { - compatible = "snps,dw-apb-ssi"; - reg = <0xfff00000 0x1000>; - interrupts = <0 154 4>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&spi_m_clk>; - num-cs = <2>; - cs-gpios = <&gpio0 13 0>, - <&gpio0 14 0>; - }; - diff --git a/Bindings/spi/snps,dw-apb-ssi.yaml b/Bindings/spi/snps,dw-apb-ssi.yaml new file mode 100644 index 000000000000..c62cbe79f00d --- /dev/null +++ b/Bindings/spi/snps,dw-apb-ssi.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface + +maintainers: + - Mark Brown + +allOf: + - $ref: "spi-controller.yaml#" + - if: + properties: + compatible: + contains: + enum: + - mscc,ocelot-spi + - mscc,jaguar2-spi + then: + properties: + reg: + minItems: 2 + +properties: + compatible: + oneOf: + - description: Generic DW SPI Controller + enum: + - snps,dw-apb-ssi + - snps,dwc-ssi-1.01a + - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller + items: + - enum: + - mscc,ocelot-spi + - mscc,jaguar2-spi + - const: snps,dw-apb-ssi + - description: Amazon Alpine SPI Controller + const: amazon,alpine-dw-apb-ssi + - description: Renesas RZ/N1 SPI Controller + items: + - const: renesas,rzn1-spi + - const: snps,dw-apb-ssi + - description: Intel Keem Bay SPI Controller + const: intel,keembay-ssi + + reg: + minItems: 1 + items: + - description: DW APB SSI controller memory mapped registers + - description: SPI MST region map + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: SPI Controller reference clock source + - description: APB interface clock source + + clock-names: + minItems: 1 + items: + - const: ssi_clk + - const: pclk + + resets: + maxItems: 1 + + reset-names: + const: spi + + reg-io-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: I/O register width (in bytes) implemented by this device + default: 4 + enum: [ 2, 4 ] + + num-cs: + default: 4 + minimum: 1 + maximum: 4 + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + +patternProperties: + "^.*@[0-9a-f]+$": + type: object + properties: + reg: + minimum: 0 + maximum: 3 + + spi-rx-bus-width: + const: 1 + + spi-tx-bus-width: + const: 1 + +unevaluatedProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - interrupts + - clocks + +examples: + - | + spi@fff00000 { + compatible = "snps,dw-apb-ssi"; + reg = <0xfff00000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 154 4>; + clocks = <&spi_m_clk>; + num-cs = <2>; + cs-gpios = <&gpio0 13 0>, + <&gpio0 14 0>; + }; +... diff --git a/Bindings/spi/socionext,uniphier-spi.yaml b/Bindings/spi/socionext,uniphier-spi.yaml new file mode 100644 index 000000000000..c25409298bdf --- /dev/null +++ b/Bindings/spi/socionext,uniphier-spi.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/socionext,uniphier-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier SPI controller + +description: | + UniPhier SoCs have SCSSI which supports SPI single channel. + +maintainers: + - Kunihiko Hayashi + - Keiji Hayashibara + +allOf: + - $ref: spi-controller.yaml# + +properties: + "#address-cells": true + "#size-cells": true + + compatible: + const: socionext,uniphier-scssi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - "#address-cells" + - "#size-cells" + +examples: + - | + spi0: spi@54006000 { + compatible = "socionext,uniphier-scssi"; + reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 39 4>; + clocks = <&peri_clk 11>; + resets = <&peri_rst 11>; + }; diff --git a/Bindings/spi/spi-controller.yaml b/Bindings/spi/spi-controller.yaml index d8e5509a7081..c6a2f543648b 100644 --- a/Bindings/spi/spi-controller.yaml +++ b/Bindings/spi/spi-controller.yaml @@ -115,24 +115,22 @@ patternProperties: Maximum SPI clocking speed of the device in Hz. spi-rx-bus-width: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 1, 2, 4, 8 ] - - default: 1 description: Bus width to the SPI bus used for read transfers. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8] + default: 1 spi-rx-delay-us: description: Delay, in microseconds, after a read transfer. spi-tx-bus-width: - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - enum: [ 1, 2, 4, 8 ] - - default: 1 description: Bus width to the SPI bus used for write transfers. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8] + default: 1 spi-tx-delay-us: description: diff --git a/Bindings/spi/spi-dw.txt b/Bindings/spi/spi-dw.txt deleted file mode 100644 index 7b63ed601990..000000000000 --- a/Bindings/spi/spi-dw.txt +++ /dev/null @@ -1,24 +0,0 @@ -Synopsys DesignWare SPI master - -Required properties: -- compatible: should be "snps,designware-spi" -- #address-cells: see spi-bus.txt -- #size-cells: see spi-bus.txt -- reg: address and length of the spi master registers -- interrupts: should contain one interrupt -- clocks: spi clock phandle -- num-cs: see spi-bus.txt - -Optional properties: -- cs-gpios: see spi-bus.txt - -Example: - -spi: spi@4020a000 { - compatible = "snps,designware-spi"; - interrupts = <11 1>; - reg = <0x4020a000 0x1000>; - clocks = <&pclk>; - num-cs = <2>; - cs-gpios = <&banka 0 0>; -}; diff --git a/Bindings/spi/spi-pl022.yaml b/Bindings/spi/spi-pl022.yaml index dfb697c69341..22999024477f 100644 --- a/Bindings/spi/spi-pl022.yaml +++ b/Bindings/spi/spi-pl022.yaml @@ -51,7 +51,7 @@ properties: pl022,rt: description: indicates the controller should run the message pump with realtime - priority to minimise the transfer latency on the bus (boolean) + priority to minimise the transfer latency on the bus (boolean) type: boolean dmas: @@ -80,55 +80,48 @@ patternProperties: properties: pl022,interface: description: SPI interface type - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - enum: - - 0 # SPI - - 1 # Texas Instruments Synchronous Serial Frame Format - - 2 # Microwire (Half Duplex) + $ref: "/schemas/types.yaml#/definitions/uint32" + enum: + - 0 # SPI + - 1 # Texas Instruments Synchronous Serial Frame Format + - 2 # Microwire (Half Duplex) pl022,com-mode: description: Specifies the transfer mode - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - enum: - - 0 # interrupt mode - - 1 # polling mode - - 2 # DMA mode - default: 1 + $ref: "/schemas/types.yaml#/definitions/uint32" + enum: + - 0 # interrupt mode + - 1 # polling mode + - 2 # DMA mode + default: 1 pl022,rx-level-trig: description: Rx FIFO watermark level - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - maximum: 4 + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 4 pl022,tx-level-trig: description: Tx FIFO watermark level - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - maximum: 4 + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 4 pl022,ctrl-len: description: Microwire interface - Control length - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0x03 - maximum: 0x1f + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0x03 + maximum: 0x1f pl022,wait-state: description: Microwire interface - Wait state - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - enum: [ 0, 1 ] + $ref: "/schemas/types.yaml#/definitions/uint32" + enum: [0, 1] pl022,duplex: description: Microwire interface - Full/Half duplex - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - enum: [ 0, 1 ] + $ref: "/schemas/types.yaml#/definitions/uint32" + enum: [0, 1] required: - compatible diff --git a/Bindings/spi/spi-pxa2xx.txt b/Bindings/spi/spi-pxa2xx.txt deleted file mode 100644 index e30e0c2a4bce..000000000000 --- a/Bindings/spi/spi-pxa2xx.txt +++ /dev/null @@ -1,27 +0,0 @@ -PXA2xx SSP SPI Controller - -Required properties: -- compatible: Must be "marvell,mmp2-ssp". -- reg: Offset and length of the device's register set. -- interrupts: Should be the interrupt number. -- clocks: Should contain a single entry describing the clock input. -- #address-cells: Number of cells required to define a chip select address. -- #size-cells: Should be zero. - -Optional properties: -- cs-gpios: list of GPIO chip selects. See the SPI bus bindings, - Documentation/devicetree/bindings/spi/spi-bus.txt -- spi-slave: Empty property indicating the SPI controller is used in slave mode. -- ready-gpios: GPIO used to signal a SPI master that the FIFO is filled - and we're ready to service a transfer. Only useful in slave mode. - -Child nodes represent devices on the SPI bus - See ../spi/spi-bus.txt - -Example: - ssp1: spi@d4035000 { - compatible = "marvell,mmp2-ssp"; - reg = <0xd4035000 0x1000>; - clocks = <&soc_clocks MMP2_CLK_SSP0>; - interrupts = <0>; - }; diff --git a/Bindings/spi/spi-rspi.txt b/Bindings/spi/spi-rspi.txt deleted file mode 100644 index 421722b93992..000000000000 --- a/Bindings/spi/spi-rspi.txt +++ /dev/null @@ -1,73 +0,0 @@ -Device tree configuration for Renesas RSPI/QSPI driver - -Required properties: -- compatible : For Renesas Serial Peripheral Interface on legacy SH: - "renesas,rspi-", "renesas,rspi" as fallback. - For Renesas Serial Peripheral Interface on RZ/A: - "renesas,rspi-", "renesas,rspi-rz" as fallback. - For Quad Serial Peripheral Interface on R-Car Gen2 and - RZ/G1 devices: - "renesas,qspi-", "renesas,qspi" as fallback. - Examples with soctypes are: - - "renesas,rspi-sh7757" (SH) - - "renesas,rspi-r7s72100" (RZ/A1H) - - "renesas,rspi-r7s9210" (RZ/A2) - - "renesas,qspi-r8a7743" (RZ/G1M) - - "renesas,qspi-r8a7744" (RZ/G1N) - - "renesas,qspi-r8a7745" (RZ/G1E) - - "renesas,qspi-r8a77470" (RZ/G1C) - - "renesas,qspi-r8a7790" (R-Car H2) - - "renesas,qspi-r8a7791" (R-Car M2-W) - - "renesas,qspi-r8a7792" (R-Car V2H) - - "renesas,qspi-r8a7793" (R-Car M2-N) - - "renesas,qspi-r8a7794" (R-Car E2) -- reg : Address start and address range size of the device -- interrupts : A list of interrupt-specifiers, one for each entry in - interrupt-names. - If interrupt-names is not present, an interrupt specifier - for a single muxed interrupt. -- interrupt-names : A list of interrupt names. Should contain (if present): - - "error" for SPEI, - - "rx" for SPRI, - - "tx" to SPTI, - - "mux" for a single muxed interrupt. -- num-cs : Number of chip selects. Some RSPI cores have more than 1. -- #address-cells : Must be <1> -- #size-cells : Must be <0> - -Optional properties: -- clocks : Must contain a reference to the functional clock. -- dmas : Must contain a list of two references to DMA specifiers, - one for transmission, and one for reception. -- dma-names : Must contain a list of two DMA names, "tx" and "rx". - -Pinctrl properties might be needed, too. See -Documentation/devicetree/bindings/pinctrl/renesas,*. - -Examples: - - spi0: spi@e800c800 { - compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; - reg = <0xe800c800 0x24>; - interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>, - <0 239 IRQ_TYPE_LEVEL_HIGH>, - <0 240 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", "rx", "tx"; - interrupt-parent = <&gic>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi: spi@e6b10000 { - compatible = "renesas,qspi-r8a7791", "renesas,qspi"; - reg = <0 0xe6b10000 0 0x2c>; - interrupt-parent = <&gic>; - interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; - num-cs = <1>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmac0 0x17>, <&dmac0 0x18>; - dma-names = "tx", "rx"; - }; diff --git a/Bindings/spi/spi-sifive.yaml b/Bindings/spi/spi-sifive.yaml index 140e4351a19f..4932205d1cba 100644 --- a/Bindings/spi/spi-sifive.yaml +++ b/Bindings/spi/spi-sifive.yaml @@ -32,11 +32,10 @@ properties: https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi reg: - maxItems: 1 - - description: - Physical base address and size of SPI registers map - A second (optional) range can indicate memory mapped flash + minItems: 1 + items: + - description: SPI registers region + - description: Memory mapped flash region interrupts: maxItems: 1 @@ -50,18 +49,16 @@ properties: sifive,fifo-depth: description: Depth of hardware queues; defaults to 8 - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - enum: [ 8 ] - - default: 8 + $ref: "/schemas/types.yaml#/definitions/uint32" + enum: [8] + default: 8 sifive,max-bits-per-word: description: Maximum bits per word; defaults to 8 - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 8 ] - - default: 8 + $ref: "/schemas/types.yaml#/definitions/uint32" + enum: [0, 1, 2, 3, 4, 5, 6, 7, 8] + default: 8 required: - compatible @@ -73,7 +70,7 @@ examples: - | spi: spi@10040000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>; + reg = <0x10040000 0x1000>, <0x20000000 0x10000000>; interrupt-parent = <&plic>; interrupts = <51>; clocks = <&tlclk>; diff --git a/Bindings/spi/spi-uniphier.txt b/Bindings/spi/spi-uniphier.txt deleted file mode 100644 index e1201573a29a..000000000000 --- a/Bindings/spi/spi-uniphier.txt +++ /dev/null @@ -1,28 +0,0 @@ -Socionext UniPhier SPI controller driver - -UniPhier SoCs have SCSSI which supports SPI single channel. - -Required properties: - - compatible: should be "socionext,uniphier-scssi" - - reg: address and length of the spi master registers - - #address-cells: must be <1>, see spi-bus.txt - - #size-cells: must be <0>, see spi-bus.txt - - interrupts: a single interrupt specifier - - pinctrl-names: should be "default" - - pinctrl-0: pin control state for the default mode - - clocks: a phandle to the clock for the device - - resets: a phandle to the reset control for the device - -Example: - -spi0: spi@54006000 { - compatible = "socionext,uniphier-scssi"; - reg = <0x54006000 0x100>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 39 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi0>; - clocks = <&peri_clk 11>; - resets = <&peri_rst 11>; -}; diff --git a/Bindings/spi/st,stm32-qspi.yaml b/Bindings/spi/st,stm32-qspi.yaml index 3665a5fe6b7f..1a342ce1f798 100644 --- a/Bindings/spi/st,stm32-qspi.yaml +++ b/Bindings/spi/st,stm32-qspi.yaml @@ -24,8 +24,8 @@ properties: reg-names: items: - - const: qspi - - const: qspi_mm + - const: qspi + - const: qspi_mm clocks: maxItems: 1 diff --git a/Bindings/spi/ti_qspi.txt b/Bindings/spi/ti_qspi.txt index e65fde4a7388..47b184bce414 100644 --- a/Bindings/spi/ti_qspi.txt +++ b/Bindings/spi/ti_qspi.txt @@ -29,7 +29,7 @@ modification to bootloader. Example: For am4372: -qspi: qspi@4b300000 { +qspi: qspi@47900000 { compatible = "ti,am4372-qspi"; reg = <0x47900000 0x100>, <0x30000000 0x4000000>; reg-names = "qspi_base", "qspi_mmap"; diff --git a/Bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Bindings/sram/allwinner,sun4i-a10-system-control.yaml index 4b5509436588..f5825935fd22 100644 --- a/Bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -29,8 +29,8 @@ properties: - const: allwinner,sun4i-a10-system-control - const: allwinner,sun5i-a13-system-control - items: - - const: allwinner,sun7i-a20-system-control - - const: allwinner,sun4i-a10-system-control + - const: allwinner,sun7i-a20-system-control + - const: allwinner,sun4i-a10-system-control - const: allwinner,sun8i-a23-system-control - const: allwinner,sun8i-h3-system-control - const: allwinner,sun50i-a64-sram-controller @@ -38,11 +38,11 @@ properties: - const: allwinner,sun50i-a64-system-control - const: allwinner,sun50i-h5-system-control - items: - - const: allwinner,sun50i-h6-system-control - - const: allwinner,sun50i-a64-system-control + - const: allwinner,sun50i-h6-system-control + - const: allwinner,sun50i-a64-system-control - items: - - const: allwinner,suniv-f1c100s-system-control - - const: allwinner,sun4i-a10-system-control + - const: allwinner,suniv-f1c100s-system-control + - const: allwinner,sun4i-a10-system-control reg: maxItems: 1 @@ -69,44 +69,44 @@ patternProperties: - const: allwinner,sun4i-a10-sram-d - const: allwinner,sun50i-a64-sram-c - items: - - const: allwinner,sun5i-a13-sram-a3-a4 - - const: allwinner,sun4i-a10-sram-a3-a4 + - const: allwinner,sun5i-a13-sram-a3-a4 + - const: allwinner,sun4i-a10-sram-a3-a4 - items: - - const: allwinner,sun7i-a20-sram-a3-a4 - - const: allwinner,sun4i-a10-sram-a3-a4 + - const: allwinner,sun7i-a20-sram-a3-a4 + - const: allwinner,sun4i-a10-sram-a3-a4 - items: - - const: allwinner,sun5i-a13-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 + - const: allwinner,sun5i-a13-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 - items: - - const: allwinner,sun7i-a20-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 + - const: allwinner,sun7i-a20-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 - items: - - const: allwinner,sun8i-a23-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 + - const: allwinner,sun8i-a23-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 - items: - - const: allwinner,sun8i-h3-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 + - const: allwinner,sun8i-h3-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 - items: - - const: allwinner,sun50i-a64-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 + - const: allwinner,sun50i-a64-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 - items: - - const: allwinner,sun50i-h5-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 + - const: allwinner,sun50i-h5-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 - items: - - const: allwinner,sun50i-h6-sram-c1 - - const: allwinner,sun4i-a10-sram-c1 + - const: allwinner,sun50i-h6-sram-c1 + - const: allwinner,sun4i-a10-sram-c1 - items: - - const: allwinner,sun5i-a13-sram-d - - const: allwinner,sun4i-a10-sram-d + - const: allwinner,sun5i-a13-sram-d + - const: allwinner,sun4i-a10-sram-d - items: - - const: allwinner,sun7i-a20-sram-d - - const: allwinner,sun4i-a10-sram-d + - const: allwinner,sun7i-a20-sram-d + - const: allwinner,sun4i-a10-sram-d - items: - - const: allwinner,suniv-f1c100s-sram-d - - const: allwinner,sun4i-a10-sram-d + - const: allwinner,suniv-f1c100s-sram-d + - const: allwinner,sun4i-a10-sram-d - items: - - const: allwinner,sun50i-h6-sram-c - - const: allwinner,sun50i-a64-sram-c + - const: allwinner,sun50i-h6-sram-c + - const: allwinner,sun50i-a64-sram-c required: - "#address-cells" diff --git a/Bindings/sram/rockchip-pmu-sram.txt b/Bindings/sram/rockchip-pmu-sram.txt deleted file mode 100644 index 6b42fda306ff..000000000000 --- a/Bindings/sram/rockchip-pmu-sram.txt +++ /dev/null @@ -1,16 +0,0 @@ -Rockchip SRAM for pmu: ------------------------------- - -The sram of pmu is used to store the function of resume from maskrom(the 1st -level loader). This is a common use of the "pmu-sram" because it keeps power -even in low power states in the system. - -Required node properties: -- compatible : should be "rockchip,rk3288-pmu-sram" -- reg : physical base address and the size of the registers window - -Example: - sram@ff720000 { - compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; - reg = <0xff720000 0x1000>; - }; diff --git a/Bindings/sram/sram.yaml b/Bindings/sram/sram.yaml index 7b83cc6c9bfa..19d116ff9ddc 100644 --- a/Bindings/sram/sram.yaml +++ b/Bindings/sram/sram.yaml @@ -29,6 +29,7 @@ properties: enum: - mmio-sram - atmel,sama5d2-securam + - rockchip,rk3288-pmu-sram reg: maxItems: 1 @@ -73,6 +74,8 @@ patternProperties: - allwinner,sun50i-a64-sram-c - amlogic,meson8-smp-sram - amlogic,meson8b-smp-sram + - amlogic,meson-gxbb-scp-shmem + - amlogic,meson-axg-scp-shmem - renesas,smp-sram - rockchip,rk3066-smp-sram - samsung,exynos4210-sysram @@ -118,9 +121,18 @@ patternProperties: required: - compatible - reg - - "#address-cells" - - "#size-cells" - - ranges + +if: + properties: + compatible: + contains: + const: rockchip,rk3288-pmu-sram + +else: + required: + - "#address-cells" + - "#size-cells" + - ranges additionalProperties: false @@ -223,6 +235,16 @@ examples: }; }; + - | + // Rockchip's rk3288 SoC uses the sram of pmu to store the function of + // resume from maskrom(the 1st level loader). This is a common use of + // the "pmu-sram" because it keeps power even in low power states + // in the system. + sram@ff720000 { + compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; + reg = <0xff720000 0x1000>; + }; + - | // Allwinner's A80 SoC uses part of the secure sram for hotplugging of the // primary core (cpu0). Once the core gets powered up it checks if a magic diff --git a/Bindings/submitting-patches.txt b/Bindings/submitting-patches.rst similarity index 92% rename from Bindings/submitting-patches.txt rename to Bindings/submitting-patches.rst index 98bee6240b65..0aab2b3f16d0 100644 --- a/Bindings/submitting-patches.txt +++ b/Bindings/submitting-patches.rst @@ -1,13 +1,17 @@ +.. SPDX-License-Identifier: GPL-2.0 - Submitting devicetree (DT) binding patches +========================================== +Submitting devicetree (DT) binding patches +========================================== I. For patch submitters +======================= 0) Normal patch submission rules from Documentation/process/submitting-patches.rst applies. 1) The Documentation/ and include/dt-bindings/ portion of the patch should - be a separate patch. The preferred subject prefix for binding patches is: + be a separate patch. The preferred subject prefix for binding patches is:: "dt-bindings: : ..." @@ -17,7 +21,7 @@ I. For patch submitters 2) DT binding files are written in DT schema format using json-schema vocabulary and YAML file format. The DT binding files must pass validation - by running: + by running:: make dt_binding_check @@ -60,6 +64,7 @@ I. For patch submitters II. For kernel maintainers +========================== 1) If you aren't comfortable reviewing a given binding, reply to it and ask the devicetree maintainers for guidance. This will help them prioritize @@ -76,6 +81,7 @@ II. For kernel maintainers kept with the driver using the binding. III. Notes +========== 0) Please see ...bindings/ABI.txt for details regarding devicetree ABI. diff --git a/Bindings/thermal/amlogic,thermal.yaml b/Bindings/thermal/amlogic,thermal.yaml index e43ec50bda37..999c6b365f1d 100644 --- a/Bindings/thermal/amlogic,thermal.yaml +++ b/Bindings/thermal/amlogic,thermal.yaml @@ -13,11 +13,11 @@ description: Binding for Amlogic Thermal properties: compatible: - items: - - enum: - - amlogic,g12a-cpu-thermal - - amlogic,g12a-ddr-thermal - - const: amlogic,g12a-thermal + items: + - enum: + - amlogic,g12a-cpu-thermal + - amlogic,g12a-ddr-thermal + - const: amlogic,g12a-thermal reg: maxItems: 1 diff --git a/Bindings/thermal/imx-thermal.txt b/Bindings/thermal/imx-thermal.txt deleted file mode 100644 index 823e4176eef8..000000000000 --- a/Bindings/thermal/imx-thermal.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Temperature Monitor (TEMPMON) on Freescale i.MX SoCs - -Required properties: -- compatible : must be one of following: - - "fsl,imx6q-tempmon" for i.MX6Q, - - "fsl,imx6sx-tempmon" for i.MX6SX, - - "fsl,imx7d-tempmon" for i.MX7S/D. -- interrupts : the interrupt output of the controller: - i.MX6Q has one IRQ which will be triggered when temperature is higher than high threshold, - i.MX6SX and i.MX7S/D have two more IRQs than i.MX6Q, one is IRQ_LOW and the other is IRQ_PANIC, - when temperature is below than low threshold, IRQ_LOW will be triggered, when temperature - is higher than panic threshold, system will auto reboot by SRC module. -- fsl,tempmon : phandle pointer to system controller that contains TEMPMON - control registers, e.g. ANATOP on imx6q. -- nvmem-cells: A phandle to the calibration cells provided by ocotp. -- nvmem-cell-names: Should be "calib", "temp_grade". - -Deprecated properties: -- fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON - calibration data, e.g. OCOTP on imx6q. The details about calibration data - can be found in SoC Reference Manual. - -Direct access to OCOTP via fsl,tempmon-data is incorrect on some newer chips -because it does not handle OCOTP clock requirements. - -Optional properties: -- clocks : thermal sensor's clock source. - -Example: -ocotp: ocotp@21bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx6sx-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SX_CLK_OCOTP>; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; -}; - -tempmon: tempmon { - compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; - interrupts = ; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; -}; - -Legacy method (Deprecated): -tempmon { - compatible = "fsl,imx6q-tempmon"; - fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks 172>; -}; diff --git a/Bindings/thermal/imx-thermal.yaml b/Bindings/thermal/imx-thermal.yaml new file mode 100644 index 000000000000..aedac1669998 --- /dev/null +++ b/Bindings/thermal/imx-thermal.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/imx-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX Thermal Binding + +maintainers: + - Shawn Guo + - Anson Huang + +properties: + compatible: + enum: + - fsl,imx6q-tempmon + - fsl,imx6sx-tempmon + - fsl,imx7d-tempmon + + interrupts: + description: | + The interrupt output of the controller, i.MX6Q has IRQ_HIGH which + will be triggered when temperature is higher than high threshold, + i.MX6SX and i.MX7S/D have two more IRQs than i.MX6Q, one is IRQ_LOW + and the other is IRQ_PANIC, when temperature is lower than low + threshold, IRQ_LOW will be triggered, when temperature is higher + than panic threshold, IRQ_PANIC will be triggered, and system can + be configured to auto reboot by SRC module for IRQ_PANIC. IRQ_HIGH, + IRQ_LOW and IRQ_PANIC share same interrupt output of controller. + maxItems: 1 + + nvmem-cells: + items: + - description: Phandle to the calibration data provided by ocotp + - description: Phandle to the temperature grade provided by ocotp + + nvmem-cell-names: + items: + - const: calib + - const: temp_grade + + fsl,tempmon: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: Phandle to anatop system controller node. + + fsl,tempmon-data: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Deprecated property, phandle pointer to fuse controller that contains + TEMPMON calibration data, e.g. OCOTP on imx6q. The details about + calibration data can be found in SoC Reference Manual. + deprecated: true + + clocks: + maxItems: 1 + +required: + - compatible + - interrupts + - fsl,tempmon + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false + +examples: + - | + #include + #include + + efuse@21bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx6sx-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SX_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; + }; + + anatop@20c8000 { + compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd"; + reg = <0x020c8000 0x1000>; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, + <0 54 IRQ_TYPE_LEVEL_HIGH>, + <0 127 IRQ_TYPE_LEVEL_HIGH>; + + tempmon { + compatible = "fsl,imx6sx-tempmon"; + interrupts = ; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; + }; + }; diff --git a/Bindings/thermal/imx8mm-thermal.txt b/Bindings/thermal/imx8mm-thermal.txt deleted file mode 100644 index 3629d3c7e76a..000000000000 --- a/Bindings/thermal/imx8mm-thermal.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Thermal Monitoring Unit (TMU) on Freescale i.MX8MM SoC - -Required properties: -- compatible : Must be "fsl,imx8mm-tmu" or "fsl,imx8mp-tmu". -- reg : Address range of TMU registers. -- clocks : TMU's clock source. -- #thermal-sensor-cells : Should be 0 or 1. See ./thermal.txt for a description. - -Example: -tmu: tmu@30260000 { - compatible = "fsl,imx8mm-tmu"; - reg = <0x30260000 0x10000>; - clocks = <&clk IMX8MM_CLK_TMU_ROOT>; - #thermal-sensor-cells = <0>; -}; diff --git a/Bindings/thermal/imx8mm-thermal.yaml b/Bindings/thermal/imx8mm-thermal.yaml new file mode 100644 index 000000000000..38852877b8e3 --- /dev/null +++ b/Bindings/thermal/imx8mm-thermal.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/imx8mm-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8M Mini Thermal Binding + +maintainers: + - Anson Huang + +description: | + i.MX8MM has TMU IP to allow temperature measurement, there are + currently two distinct major versions of the IP that is supported + by a single driver. The IP versions are named v1 and v2, v1 is + for i.MX8MM which has ONLY 1 sensor, v2 is for i.MX8MP which has + 2 sensors. + +properties: + compatible: + enum: + - fsl,imx8mm-tmu + - fsl,imx8mp-tmu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#thermal-sensor-cells": + description: | + Number of cells required to uniquely identify the thermal + sensors, 0 for ONLY one sensor and 1 for multiple sensors. + enum: + - 0 + - 1 + +required: + - compatible + - reg + - clocks + - '#thermal-sensor-cells' + +additionalProperties: false + +examples: + - | + #include + + thermal-sensor@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; + }; + +... diff --git a/Bindings/thermal/qcom-tsens.yaml b/Bindings/thermal/qcom-tsens.yaml index 2ddd39d96766..d7be931b42d2 100644 --- a/Bindings/thermal/qcom-tsens.yaml +++ b/Bindings/thermal/qcom-tsens.yaml @@ -73,12 +73,11 @@ properties: - const: calib_sel "#qcom,sensors": - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - minimum: 1 - - maximum: 16 description: Number of sensors enabled on this platform + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 16 "#thermal-sensor-cells": const: 1 diff --git a/Bindings/thermal/rcar-gen3-thermal.txt b/Bindings/thermal/rcar-gen3-thermal.txt deleted file mode 100644 index 2993fa720195..000000000000 --- a/Bindings/thermal/rcar-gen3-thermal.txt +++ /dev/null @@ -1,60 +0,0 @@ -* DT bindings for Renesas R-Car Gen3 Thermal Sensor driver - -On R-Car Gen3 SoCs, the thermal sensor controllers (TSC) control the thermal -sensors (THS) which are the analog circuits for measuring temperature (Tj) -inside the LSI. - -Required properties: -- compatible : "renesas,-thermal", - Examples with soctypes are: - - "renesas,r8a774a1-thermal" (RZ/G2M) - - "renesas,r8a774b1-thermal" (RZ/G2N) - - "renesas,r8a7795-thermal" (R-Car H3) - - "renesas,r8a7796-thermal" (R-Car M3-W) - - "renesas,r8a77961-thermal" (R-Car M3-W+) - - "renesas,r8a77965-thermal" (R-Car M3-N) - - "renesas,r8a77980-thermal" (R-Car V3H) -- reg : Address ranges of the thermal registers. Each sensor - needs one address range. Sorting must be done in - increasing order according to datasheet, i.e. - TSC1, TSC2, ... -- clocks : Must contain a reference to the functional clock. -- #thermal-sensor-cells : must be <1>. - -Optional properties: - -- interrupts : interrupts routed to the TSC (must be 3). -- power-domain : Must contain a reference to the power domain. This - property is mandatory if the thermal sensor instance - is part of a controllable power domain. - -Example: - - tsc: thermal@e6198000 { - compatible = "renesas,r8a7795-thermal"; - reg = <0 0xe6198000 0 0x100>, - <0 0xe61a0000 0 0x100>, - <0 0xe61a8000 0 0x100>; - interrupts = , - , - ; - clocks = <&cpg CPG_MOD 522>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #thermal-sensor-cells = <1>; - }; - - thermal-zones { - sensor_thermal1: sensor-thermal1 { - polling-delay-passive = <250>; - polling-delay = <1000>; - thermal-sensors = <&tsc 0>; - - trips { - sensor1_crit: sensor1-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; - }; diff --git a/Bindings/thermal/rcar-gen3-thermal.yaml b/Bindings/thermal/rcar-gen3-thermal.yaml new file mode 100644 index 000000000000..b1a55ae497de --- /dev/null +++ b/Bindings/thermal/rcar-gen3-thermal.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (C) 2020 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/rcar-gen3-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Gen3 Thermal Sensor + +description: + On R-Car Gen3 SoCs, the thermal sensor controllers (TSC) control the thermal + sensors (THS) which are the analog circuits for measuring temperature (Tj) + inside the LSI. + +maintainers: + - Niklas Söderlund + +properties: + compatible: + enum: + - renesas,r8a774a1-thermal # RZ/G2M + - renesas,r8a774b1-thermal # RZ/G2N + - renesas,r8a7795-thermal # R-Car H3 + - renesas,r8a7796-thermal # R-Car M3-W + - renesas,r8a77961-thermal # R-Car M3-W+ + - renesas,r8a77965-thermal # R-Car M3-N + - renesas,r8a77980-thermal # R-Car V3H + reg: + minItems: 2 + maxItems: 3 + items: + - description: TSC1 registers + - description: TSC2 registers + - description: TSC3 registers + + interrupts: + items: + - description: TEMP1 interrupt + - description: TEMP2 interrupt + - description: TEMP3 interrupt + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + - resets + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + + tsc: thermal@e6198000 { + compatible = "renesas,r8a7795-thermal"; + reg = <0xe6198000 0x100>, + <0xe61a0000 0x100>, + <0xe61a8000 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + }; + + thermal-zones { + sensor_thermal: sensor-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; diff --git a/Bindings/thermal/rcar-thermal.yaml b/Bindings/thermal/rcar-thermal.yaml index d2f4f1b063ac..0994693d240f 100644 --- a/Bindings/thermal/rcar-thermal.yaml +++ b/Bindings/thermal/rcar-thermal.yaml @@ -20,6 +20,7 @@ properties: - const: renesas,rcar-thermal # Generic without thermal-zone - items: - enum: + - renesas,thermal-r8a7742 # RZ/G1H - renesas,thermal-r8a7743 # RZ/G1M - renesas,thermal-r8a7744 # RZ/G1N - const: renesas,rcar-gen2-thermal # Generic thermal-zone @@ -94,8 +95,8 @@ examples: thermal@e61f0000 { compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, - <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; + reg = <0xe61f0000 0x14>, <0xe61f0100 0x38>, + <0xe61f0200 0x38>, <0xe61f0300 0x38>; interrupts = ; clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; power-domains = <&pd_c5>; @@ -111,7 +112,7 @@ examples: compatible = "renesas,thermal-r8a7790", "renesas,rcar-gen2-thermal", "renesas,rcar-thermal"; - reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; + reg = <0xe61f0000 0x10>, <0xe61f0100 0x38>; interrupts = ; clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; diff --git a/Bindings/thermal/socionext,uniphier-thermal.yaml b/Bindings/thermal/socionext,uniphier-thermal.yaml new file mode 100644 index 000000000000..553c9dcdaeeb --- /dev/null +++ b/Bindings/thermal/socionext,uniphier-thermal.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/socionext,uniphier-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier thermal monitor + +description: | + This describes the devicetree bindings for thermal monitor supported by + PVT(Process, Voltage and Temperature) monitoring unit implemented on + Socionext UniPhier SoCs. + +maintainers: + - Kunihiko Hayashi + +properties: + compatible: + enum: + - socionext,uniphier-pxs2-thermal + - socionext,uniphier-ld20-thermal + - socionext,uniphier-pxs3-thermal + + interrupts: + maxItems: 1 + + "#thermal-sensor-cells": + const: 0 + + socionext,tmod-calibration: + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 2 + description: + A pair of calibrated values referred from PVT, in case that the values + aren't set on SoC, like a reference board. + +required: + - compatible + - interrupts + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + // The UniPhier thermal should be a subnode of a "syscon" compatible node. + + sysctrl@61840000 { + compatible = "socionext,uniphier-ld20-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + pvtctl: thermal { + compatible = "socionext,uniphier-ld20-thermal"; + interrupts = <0 3 1>; + #thermal-sensor-cells = <0>; + }; + }; diff --git a/Bindings/thermal/sprd-thermal.yaml b/Bindings/thermal/sprd-thermal.yaml index 058c4cc06ba6..af2ff930646a 100644 --- a/Bindings/thermal/sprd-thermal.yaml +++ b/Bindings/thermal/sprd-thermal.yaml @@ -83,7 +83,7 @@ examples: - | ap_thm0: thermal@32200000 { compatible = "sprd,ums512-thermal"; - reg = <0 0x32200000 0 0x10000>; + reg = <0x32200000 0x10000>; clock-names = "enable"; clocks = <&aonapb_gate 32>; #thermal-sensor-cells = <1>; diff --git a/Bindings/thermal/thermal-cooling-devices.yaml b/Bindings/thermal/thermal-cooling-devices.yaml new file mode 100644 index 000000000000..5145883d932e --- /dev/null +++ b/Bindings/thermal/thermal-cooling-devices.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0) +# Copyright 2020 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/thermal-cooling-devices.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Thermal cooling device binding + +maintainers: + - Amit Kucheria + +description: | + Thermal management is achieved in devicetree by describing the sensor hardware + and the software abstraction of cooling devices and thermal zones required to + take appropriate action to mitigate thermal overload. + + The following node types are used to completely describe a thermal management + system in devicetree: + - thermal-sensor: device that measures temperature, has SoC-specific bindings + - cooling-device: device used to dissipate heat either passively or actively + - thermal-zones: a container of the following node types used to describe all + thermal data for the platform + + This binding describes the cooling devices. + + There are essentially two ways to provide control on power dissipation: + - Passive cooling: by means of regulating device performance. A typical + passive cooling mechanism is a CPU that has dynamic voltage and frequency + scaling (DVFS), and uses lower frequencies as cooling states. + - Active cooling: by means of activating devices in order to remove the + dissipated heat, e.g. regulating fan speeds. + + Any cooling device has a range of cooling states (i.e. different levels of + heat dissipation). They also have a way to determine the state of cooling in + which the device is. For example, a fan's cooling states correspond to the + different fan speeds possible. Cooling states are referred to by single + unsigned integers, where larger numbers mean greater heat dissipation. The + precise set of cooling states associated with a device should be defined in + a particular device's binding. + +select: true + +properties: + "#cooling-cells": + description: + Must be 2, in order to specify minimum and maximum cooling state used in + the cooling-maps reference. The first cell is the minimum cooling state + and the second cell is the maximum cooling state requested. + const: 2 + +examples: + - | + #include + #include + + // Example 1: Cpufreq cooling device on CPU0 + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; + capacity-dmips-mhz = <607>; + dynamic-power-coefficient = <100>; + qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + /* ... */ + + }; + + /* ... */ + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_alert0>; + /* Corresponds to 1000MHz in OPP table */ + cooling-device = <&CPU0 5 5>; + }; + }; + }; + + /* ... */ + }; +... diff --git a/Bindings/thermal/thermal-idle.yaml b/Bindings/thermal/thermal-idle.yaml new file mode 100644 index 000000000000..7a922f540934 --- /dev/null +++ b/Bindings/thermal/thermal-idle.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2020 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/thermal-idle.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Thermal idle cooling device binding + +maintainers: + - Daniel Lezcano + +description: | + The thermal idle cooling device allows the system to passively + mitigate the temperature on the device by injecting idle cycles, + forcing it to cool down. + + This binding describes the thermal idle node. + +properties: + $nodename: + const: thermal-idle + description: | + A thermal-idle node describes the idle cooling device properties to + cool down efficiently the attached thermal zone. + + '#cooling-cells': + const: 2 + description: | + Must be 2, in order to specify minimum and maximum cooling state used in + the cooling-maps reference. The first cell is the minimum cooling state + and the second cell is the maximum cooling state requested. + + duration-us: + description: | + The idle duration in microsecond the device should cool down. + + exit-latency-us: + description: | + The exit latency constraint in microsecond for the injected + idle state for the device. It is the latency constraint to + apply when selecting an idle state from among all the present + ones. + +required: + - '#cooling-cells' + +examples: + - | + #include + + // Example: Combining idle cooling device on big CPUs with cpufreq cooling device + cpus { + #address-cells = <2>; + #size-cells = <0>; + + /* ... */ + + cpu_b0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <436>; + #cooling-cells = <2>; /* min followed by max */ + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; + }; + + cpu_b1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <436>; + #cooling-cells = <2>; /* min followed by max */ + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + thermal-idle { + #cooling-cells = <2>; + duration-us = <10000>; + exit-latency-us = <500>; + }; + }; + + /* ... */ + + }; + + /* ... */ + + thermal_zones { + cpu_thermal: cpu { + polling-delay-passive = <100>; + polling-delay = <1000>; + + /* ... */ + + trips { + cpu_alert0: cpu_alert0 { + temperature = <65000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_alert1: cpu_alert1 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_alert2: cpu_alert2 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = <&{/cpus/cpu@100/thermal-idle} 0 15 >, + <&{/cpus/cpu@101/thermal-idle} 0 15>; + }; + + map1 { + trip = <&cpu_alert2>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; diff --git a/Bindings/thermal/thermal-sensor.yaml b/Bindings/thermal/thermal-sensor.yaml new file mode 100644 index 000000000000..727d04550324 --- /dev/null +++ b/Bindings/thermal/thermal-sensor.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0) +# Copyright 2020 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/thermal-sensor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Thermal sensor binding + +maintainers: + - Amit Kucheria + +description: | + Thermal management is achieved in devicetree by describing the sensor hardware + and the software abstraction of thermal zones required to take appropriate + action to mitigate thermal overloads. + + The following node types are used to completely describe a thermal management + system in devicetree: + - thermal-sensor: device that measures temperature, has SoC-specific bindings + - cooling-device: device used to dissipate heat either passively or actively + - thermal-zones: a container of the following node types used to describe all + thermal data for the platform + + This binding describes the thermal-sensor. + + Thermal sensor devices provide temperature sensing capabilities on thermal + zones. Typical devices are I2C ADC converters and bandgaps. Thermal sensor + devices may control one or more internal sensors. + +properties: + "#thermal-sensor-cells": + description: + Used to uniquely identify a thermal sensor instance within an IC. Will be + 0 on sensor nodes with only a single sensor and at least 1 on nodes + containing several internal sensors. + enum: [0, 1] + +examples: + - | + #include + + // Example 1: SDM845 TSENS + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + + /* ... */ + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x1ff>; /* SROT */ + #qcom,sensors = <13>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x1ff>; /* SROT */ + #qcom,sensors = <8>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + }; +... diff --git a/Bindings/thermal/thermal-zones.yaml b/Bindings/thermal/thermal-zones.yaml new file mode 100644 index 000000000000..3ec9cc87ec50 --- /dev/null +++ b/Bindings/thermal/thermal-zones.yaml @@ -0,0 +1,341 @@ +# SPDX-License-Identifier: (GPL-2.0) +# Copyright 2020 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/thermal-zones.yaml# +$schema: http://devicetree.org/meta-schemas/base.yaml# + +title: Thermal zone binding + +maintainers: + - Amit Kucheria + +description: | + Thermal management is achieved in devicetree by describing the sensor hardware + and the software abstraction of cooling devices and thermal zones required to + take appropriate action to mitigate thermal overloads. + + The following node types are used to completely describe a thermal management + system in devicetree: + - thermal-sensor: device that measures temperature, has SoC-specific bindings + - cooling-device: device used to dissipate heat either passively or actively + - thermal-zones: a container of the following node types used to describe all + thermal data for the platform + + This binding describes the thermal-zones. + + The polling-delay properties of a thermal-zone are bound to the maximum dT/dt + (temperature derivative over time) in two situations for a thermal zone: + 1. when passive cooling is activated (polling-delay-passive) + 2. when the zone just needs to be monitored (polling-delay) or when + active cooling is activated. + + The maximum dT/dt is highly bound to hardware power consumption and + dissipation capability. The delays should be chosen to account for said + max dT/dt, such that a device does not cross several trip boundaries + unexpectedly between polls. Choosing the right polling delays shall avoid + having the device in temperature ranges that may damage the silicon structures + and reduce silicon lifetime. + +properties: + $nodename: + const: thermal-zones + description: + A /thermal-zones node is required in order to use the thermal framework to + manage input from the various thermal zones in the system in order to + mitigate thermal overload conditions. It does not represent a real device + in the system, but acts as a container to link a thermal sensor device, + platform-data regarding temperature thresholds and the mitigation actions + to take when the temperature crosses those thresholds. + +patternProperties: + "^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$": + type: object + description: + Each thermal zone node contains information about how frequently it + must be checked, the sensor responsible for reporting temperature for + this zone, one sub-node containing the various trip points for this + zone and one sub-node containing all the zone cooling-maps. + + properties: + polling-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The maximum number of milliseconds to wait between polls when + checking this thermal zone. Setting this to 0 disables the polling + timers setup by the thermal framework and assumes that the thermal + sensors in this zone support interrupts. + + polling-delay-passive: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The maximum number of milliseconds to wait between polls when + checking this thermal zone while doing passive cooling. Setting + this to 0 disables the polling timers setup by the thermal + framework and assumes that the thermal sensors in this zone + support interrupts. + + thermal-sensors: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + description: + The thermal sensor phandle and sensor specifier used to monitor this + thermal zone. + + coefficients: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + An array of integers containing the coefficients of a linear equation + that binds all the sensors listed in this thermal zone. + + The linear equation used is as follows, + z = c0 * x0 + c1 * x1 + ... + c(n-1) * x(n-1) + cn + where c0, c1, .., cn are the coefficients. + + Coefficients default to 1 in case this property is not specified. The + coefficients are ordered and are matched with sensors by means of the + sensor ID. Additional coefficients are interpreted as constant offset. + + sustainable-power: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + An estimate of the sustainable power (in mW) that this thermal zone + can dissipate at the desired control temperature. For reference, the + sustainable power of a 4-inch phone is typically 2000mW, while on a + 10-inch tablet is around 4500mW. + + trips: + type: object + description: + This node describes a set of points in the temperature domain at + which the thermal framework needs to take action. The actions to + be taken are defined in another node called cooling-maps. + + patternProperties: + "^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$": + type: object + + properties: + temperature: + $ref: /schemas/types.yaml#/definitions/int32 + minimum: -273000 + maximum: 200000 + description: + An integer expressing the trip temperature in millicelsius. + + hysteresis: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + An unsigned integer expressing the hysteresis delta with + respect to the trip temperature property above, also in + millicelsius. Any cooling action initiated by the framework is + maintained until the temperature falls below + (trip temperature - hysteresis). This potentially prevents a + situation where the trip gets constantly triggered soon after + cooling action is removed. + + type: + $ref: /schemas/types.yaml#/definitions/string + enum: + - active # enable active cooling e.g. fans + - passive # enable passive cooling e.g. throttling cpu + - hot # send notification to driver + - critical # send notification to driver, trigger shutdown + description: | + There are four valid trip types: active, passive, hot, + critical. + + The critical trip type is used to set the maximum + temperature threshold above which the HW becomes + unstable and underlying firmware might even trigger a + reboot. Hitting the critical threshold triggers a system + shutdown. + + The hot trip type can be used to send a notification to + the thermal driver (if a .notify callback is registered). + The action to be taken is left to the driver. + + The passive trip type can be used to slow down HW e.g. run + the CPU, GPU, bus at a lower frequency. + + The active trip type can be used to control other HW to + help in cooling e.g. fans can be sped up or slowed down + + required: + - temperature + - hysteresis + - type + additionalProperties: false + + additionalProperties: false + + cooling-maps: + type: object + description: + This node describes the action to be taken when a thermal zone + crosses one of the temperature thresholds described in the trips + node. The action takes the form of a mapping relation between a + trip and the target cooling device state. + + patternProperties: + "^map[-a-zA-Z0-9]*$": + type: object + + properties: + trip: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle of a trip point node within this thermal zone. + + cooling-device: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A list of cooling device phandles along with the minimum + and maximum cooling state specifiers for each cooling + device. Using the THERMAL_NO_LIMIT (-1UL) constant in the + cooling-device phandle limit specifier lets the framework + use the minimum and maximum cooling state for that cooling + device automatically. + + contribution: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 100 + description: + The percentage contribution of the cooling devices at the + specific trip temperature referenced in this map + to this thermal zone + + required: + - trip + - cooling-device + additionalProperties: false + + required: + - polling-delay + - polling-delay-passive + - thermal-sensors + - trips + additionalProperties: false + +examples: + - | + #include + #include + + // Example 1: SDM845 TSENS + soc { + #address-cells = <2>; + #size-cells = <2>; + + /* ... */ + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x1ff>; /* SROT */ + #qcom,sensors = <13>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x1ff>; /* SROT */ + #qcom,sensors = <8>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + }; + + /* ... */ + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu0_alert0>; + /* Corresponds to 1400MHz in OPP table */ + cooling-device = <&CPU0 3 3>, <&CPU1 3 3>, + <&CPU2 3 3>, <&CPU3 3 3>; + }; + + map1 { + trip = <&cpu0_alert1>; + /* Corresponds to 1000MHz in OPP table */ + cooling-device = <&CPU0 5 5>, <&CPU1 5 5>, + <&CPU2 5 5>, <&CPU3 5 5>; + }; + }; + }; + + /* ... */ + + cluster0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 5>; + + trips { + cluster0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + cluster0_crit: cluster0_crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + /* ... */ + + gpu-top-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens0 11>; + + trips { + gpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; +... diff --git a/Bindings/thermal/ti,am654-thermal.yaml b/Bindings/thermal/ti,am654-thermal.yaml new file mode 100644 index 000000000000..ea14de80ec75 --- /dev/null +++ b/Bindings/thermal/ti,am654-thermal.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/ti,am654-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments AM654 VTM (DTS) binding + +maintainers: + - Keerthy + +properties: + compatible: + const: ti,am654-vtm + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + +required: + - compatible + - reg + - power-domains + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + vtm: thermal@42050000 { + compatible = "ti,am654-vtm"; + reg = <0x42050000 0x25c>; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; + + mpu0_thermal: mpu0_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&vtm0 0>; + + trips { + mpu0_crit: mpu0_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +... diff --git a/Bindings/thermal/uniphier-thermal.txt b/Bindings/thermal/uniphier-thermal.txt deleted file mode 100644 index ceb92a95727a..000000000000 --- a/Bindings/thermal/uniphier-thermal.txt +++ /dev/null @@ -1,65 +0,0 @@ -* UniPhier Thermal bindings - -This describes the devicetree bindings for thermal monitor supported by -PVT(Process, Voltage and Temperature) monitoring unit implemented on Socionext -UniPhier SoCs. - -Required properties: -- compatible : - - "socionext,uniphier-pxs2-thermal" : For UniPhier PXs2 SoC - - "socionext,uniphier-ld20-thermal" : For UniPhier LD20 SoC - - "socionext,uniphier-pxs3-thermal" : For UniPhier PXs3 SoC -- interrupts : IRQ for the temperature alarm -- #thermal-sensor-cells : Should be 0. See ./thermal.txt for details. - -Optional properties: -- socionext,tmod-calibration: A pair of calibrated values referred from PVT, - in case that the values aren't set on SoC, - like a reference board. - -Example: - - sysctrl@61840000 { - compatible = "socionext,uniphier-ld20-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x10000>; - ... - pvtctl: pvtctl { - compatible = "socionext,uniphier-ld20-thermal"; - interrupts = <0 3 1>; - #thermal-sensor-cells = <0>; - }; - ... - }; - - thermal-zones { - cpu_thermal { - polling-delay-passive = <250>; /* 250ms */ - polling-delay = <1000>; /* 1000ms */ - thermal-sensors = <&pvtctl>; - - trips { - cpu_crit: cpu_crit { - temperature = <110000>; /* 110C */ - hysteresis = <2000>; - type = "critical"; - }; - cpu_alert: cpu_alert { - temperature = <100000>; /* 100C */ - hysteresis = <2000>; - type = "passive"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = <&cpu0 (-1) (-1)>; - }; - map1 { - trip = <&cpu_alert>; - cooling-device = <&cpu2 (-1) (-1)>; - }; - }; - }; - }; diff --git a/Bindings/timer/arm,arch_timer.yaml b/Bindings/timer/arm,arch_timer.yaml index fa255672e8e5..2c75105c1398 100644 --- a/Bindings/timer/arm,arch_timer.yaml +++ b/Bindings/timer/arm,arch_timer.yaml @@ -28,10 +28,10 @@ properties: - arm,armv7-timer - items: - enum: - - arm,armv7-timer + - arm,armv7-timer - items: - enum: - - arm,armv8-timer + - arm,armv8-timer interrupts: items: @@ -51,6 +51,12 @@ properties: description: If present, the timer is powered through an always-on power domain, therefore it never loses context. + allwinner,erratum-unknown1: + type: boolean + description: Indicates the presence of an erratum found in Allwinner SoCs, + where reading certain values from the counter is unreliable. This also + affects writes to the tval register, due to the implicit counter read. + fsl,erratum-a008585: type: boolean description: Indicates the presence of QorIQ erratum A-008585, which says diff --git a/Bindings/timer/arm,arch_timer_mmio.yaml b/Bindings/timer/arm,arch_timer_mmio.yaml index 582bbef62b95..d83a1f97f911 100644 --- a/Bindings/timer/arm,arch_timer_mmio.yaml +++ b/Bindings/timer/arm,arch_timer_mmio.yaml @@ -20,7 +20,7 @@ properties: compatible: items: - enum: - - arm,armv7-timer-mem + - arm,armv7-timer-mem reg: maxItems: 1 @@ -65,10 +65,9 @@ patternProperties: description: A timer node has up to 8 frame sub-nodes, each with the following properties. properties: frame-number: - allOf: - - $ref: "/schemas/types.yaml#/definitions/uint32" - - minimum: 0 - maximum: 7 + $ref: "/schemas/types.yaml#/definitions/uint32" + minimum: 0 + maximum: 7 interrupts: minItems: 1 @@ -77,7 +76,7 @@ patternProperties: - description: physical timer irq - description: virtual timer irq - reg : + reg: minItems: 1 maxItems: 2 items: diff --git a/Bindings/timer/cadence,ttc-timer.txt b/Bindings/timer/cadence,ttc-timer.txt deleted file mode 100644 index eeee6cd51e5c..000000000000 --- a/Bindings/timer/cadence,ttc-timer.txt +++ /dev/null @@ -1,21 +0,0 @@ -Cadence TTC - Triple Timer Counter - -Required properties: -- compatible : Should be "cdns,ttc". -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 3 interrupts; one per timer channel. -- clocks: phandle to the source clock - -Optional properties: -- timer-width: Bit width of the timer, necessary if not 16. - -Example: - -ttc0: ttc0@f8001000 { - interrupt-parent = <&intc>; - interrupts = < 0 10 4 0 11 4 0 12 4 >; - compatible = "cdns,ttc"; - reg = <0xF8001000 0x1000>; - clocks = <&cpu_clk 3>; - timer-width = <32>; -}; diff --git a/Bindings/timer/cdns,ttc.yaml b/Bindings/timer/cdns,ttc.yaml new file mode 100644 index 000000000000..c532b60b9c63 --- /dev/null +++ b/Bindings/timer/cdns,ttc.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/cdns,ttc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence TTC - Triple Timer Counter + +maintainers: + - Michal Simek + +properties: + compatible: + const: cdns,ttc + + reg: + maxItems: 1 + + interrupts: + minItems: 3 + maxItems: 3 + description: | + A list of 3 interrupts; one per timer channel. + + clocks: + maxItems: 1 + + timer-width: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: | + Bit width of the timer, necessary if not 16. + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + ttc0: ttc0@f8001000 { + interrupt-parent = <&intc>; + interrupts = <0 10 4>, <0 11 4>, <0 12 4>; + compatible = "cdns,ttc"; + reg = <0xF8001000 0x1000>; + clocks = <&cpu_clk 3>; + timer-width = <32>; + }; diff --git a/Bindings/timer/csky,mptimer.txt b/Bindings/timer/csky,mptimer.txt index 15cfec08fbb8..f5c7e99cf52b 100644 --- a/Bindings/timer/csky,mptimer.txt +++ b/Bindings/timer/csky,mptimer.txt @@ -8,7 +8,7 @@ regs is accessed by cpu co-processor 4 registers with mtcr/mfcr. - PTIM_CTLR "cr<0, 14>" Control reg to start reset timer. - PTIM_TSR "cr<1, 14>" Interrupt cleanup status reg. - PTIM_CCVR "cr<3, 14>" Current counter value reg. - - PTIM_LVR "cr<6, 14>" Window value reg to triger next event. + - PTIM_LVR "cr<6, 14>" Window value reg to trigger next event. ============================== timer node bindings definition diff --git a/Bindings/timer/fsl,imxgpt.txt b/Bindings/timer/fsl,imxgpt.txt deleted file mode 100644 index 5d8fd5b52598..000000000000 --- a/Bindings/timer/fsl,imxgpt.txt +++ /dev/null @@ -1,45 +0,0 @@ -Freescale i.MX General Purpose Timer (GPT) - -Required properties: - -- compatible : should be one of following: - for i.MX1: - - "fsl,imx1-gpt"; - for i.MX21: - - "fsl,imx21-gpt"; - for i.MX27: - - "fsl,imx27-gpt", "fsl,imx21-gpt"; - for i.MX31: - - "fsl,imx31-gpt"; - for i.MX25: - - "fsl,imx25-gpt", "fsl,imx31-gpt"; - for i.MX50: - - "fsl,imx50-gpt", "fsl,imx31-gpt"; - for i.MX51: - - "fsl,imx51-gpt", "fsl,imx31-gpt"; - for i.MX53: - - "fsl,imx53-gpt", "fsl,imx31-gpt"; - for i.MX6Q: - - "fsl,imx6q-gpt", "fsl,imx31-gpt"; - for i.MX6DL: - - "fsl,imx6dl-gpt"; - for i.MX6SL: - - "fsl,imx6sl-gpt", "fsl,imx6dl-gpt"; - for i.MX6SX: - - "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; -- reg : specifies base physical address and size of the registers. -- interrupts : should be the gpt interrupt. -- clocks : the clocks provided by the SoC to drive the timer, must contain - an entry for each entry in clock-names. -- clock-names : must include "ipg" entry first, then "per" entry. - -Example: - -gpt1: timer@10003000 { - compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; - reg = <0x10003000 0x1000>; - interrupts = <26>; - clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, - <&clks IMX27_CLK_PER1_GATE>; - clock-names = "ipg", "per"; -}; diff --git a/Bindings/timer/fsl,imxgpt.yaml b/Bindings/timer/fsl,imxgpt.yaml new file mode 100644 index 000000000000..883f7f46650b --- /dev/null +++ b/Bindings/timer/fsl,imxgpt.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/fsl,imxgpt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX General Purpose Timer (GPT) + +maintainers: + - Sascha Hauer + +properties: + compatible: + oneOf: + - const: fsl,imx1-gpt + - const: fsl,imx21-gpt + - items: + - const: fsl,imx27-gpt + - const: fsl,imx21-gpt + - const: fsl,imx31-gpt + - items: + - enum: + - fsl,imx25-gpt + - fsl,imx50-gpt + - fsl,imx51-gpt + - fsl,imx53-gpt + - fsl,imx6q-gpt + - const: fsl,imx31-gpt + - const: fsl,imx6dl-gpt + - items: + - enum: + - fsl,imx6sl-gpt + - fsl,imx6sx-gpt + - const: fsl,imx6dl-gpt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: SoC GPT ipg clock + - description: SoC GPT per clock + + clock-names: + items: + - const: ipg + - const: per + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + timer@10003000 { + compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; + reg = <0x10003000 0x1000>; + interrupts = <26>; + clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; + clock-names = "ipg", "per"; + }; diff --git a/Bindings/timer/ingenic,tcu.txt b/Bindings/timer/ingenic,tcu.txt deleted file mode 100644 index 91f704951845..000000000000 --- a/Bindings/timer/ingenic,tcu.txt +++ /dev/null @@ -1,138 +0,0 @@ -Ingenic JZ47xx SoCs Timer/Counter Unit devicetree bindings -========================================================== - -For a description of the TCU hardware and drivers, have a look at -Documentation/mips/ingenic-tcu.rst. - -Required properties: - -- compatible: Must be one of: - * ingenic,jz4740-tcu - * ingenic,jz4725b-tcu - * ingenic,jz4770-tcu - * ingenic,x1000-tcu - followed by "simple-mfd". -- reg: Should be the offset/length value corresponding to the TCU registers -- clocks: List of phandle & clock specifiers for clocks external to the TCU. - The "pclk", "rtc" and "ext" clocks should be provided. The "tcu" clock - should be provided if the SoC has it. -- clock-names: List of name strings for the external clocks. -- #clock-cells: Should be <1>; - Clock consumers specify this argument to identify a clock. The valid values - may be found in . -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value should be 1. -- interrupts : Specifies the interrupt the controller is connected to. - -Optional properties: - -- ingenic,pwm-channels-mask: Bitmask of TCU channels reserved for PWM use. - Default value is 0xfc. - - -Children nodes -========================================================== - - -PWM node: ---------- - -Required properties: - -- compatible: Must be one of: - * ingenic,jz4740-pwm - * ingenic,jz4725b-pwm -- #pwm-cells: Should be 3. See ../pwm/pwm.yaml for a description of the cell - format. -- clocks: List of phandle & clock specifiers for the TCU clocks. -- clock-names: List of name strings for the TCU clocks. - - -Watchdog node: --------------- - -Required properties: - -- compatible: Must be "ingenic,jz4740-watchdog" -- clocks: phandle to the WDT clock -- clock-names: should be "wdt" - - -OS Timer node: ---------- - -Required properties: - -- compatible: Must be one of: - * ingenic,jz4725b-ost - * ingenic,jz4770-ost -- clocks: phandle to the OST clock -- clock-names: should be "ost" -- interrupts : Specifies the interrupt the OST is connected to. - - -Example -========================================================== - -#include -#include - -/ { - tcu: timer@10002000 { - compatible = "ingenic,jz4770-tcu", "simple-mfd"; - reg = <0x10002000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x10002000 0x1000>; - - #clock-cells = <1>; - - clocks = <&cgu JZ4770_CLK_RTC - &cgu JZ4770_CLK_EXT - &cgu JZ4770_CLK_PCLK>; - clock-names = "rtc", "ext", "pclk"; - - interrupt-controller; - #interrupt-cells = <1>; - - interrupt-parent = <&intc>; - interrupts = <27 26 25>; - - watchdog: watchdog@0 { - compatible = "ingenic,jz4740-watchdog"; - reg = <0x0 0xc>; - - clocks = <&tcu TCU_CLK_WDT>; - clock-names = "wdt"; - }; - - pwm: pwm@40 { - compatible = "ingenic,jz4740-pwm"; - reg = <0x40 0x80>; - - #pwm-cells = <3>; - - clocks = <&tcu TCU_CLK_TIMER0 - &tcu TCU_CLK_TIMER1 - &tcu TCU_CLK_TIMER2 - &tcu TCU_CLK_TIMER3 - &tcu TCU_CLK_TIMER4 - &tcu TCU_CLK_TIMER5 - &tcu TCU_CLK_TIMER6 - &tcu TCU_CLK_TIMER7>; - clock-names = "timer0", "timer1", "timer2", "timer3", - "timer4", "timer5", "timer6", "timer7"; - }; - - ost: timer@e0 { - compatible = "ingenic,jz4770-ost"; - reg = <0xe0 0x20>; - - clocks = <&tcu TCU_CLK_OST>; - clock-names = "ost"; - - interrupts = <15>; - }; - }; -}; diff --git a/Bindings/timer/ingenic,tcu.yaml b/Bindings/timer/ingenic,tcu.yaml new file mode 100644 index 000000000000..03893e6a2f57 --- /dev/null +++ b/Bindings/timer/ingenic,tcu.yaml @@ -0,0 +1,280 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/ingenic,tcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs Timer/Counter Unit (TCU) devicetree bindings + +description: | + For a description of the TCU hardware and drivers, have a look at + Documentation/mips/ingenic-tcu.rst. + +maintainers: + - Paul Cercueil + +select: + properties: + compatible: + contains: + enum: + - ingenic,jz4740-tcu + - ingenic,jz4725b-tcu + - ingenic,jz4770-tcu + - ingenic,jz4780-tcu + - ingenic,x1000-tcu + required: + - compatible + +properties: + $nodename: + pattern: "^timer@[0-9a-f]+$" + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + "#clock-cells": + const: 1 + + "#interrupt-cells": + const: 1 + + interrupt-controller: true + + ranges: true + + compatible: + oneOf: + - items: + - enum: + - ingenic,jz4740-tcu + - ingenic,jz4725b-tcu + - ingenic,jz4770-tcu + - ingenic,x1000-tcu + - const: simple-mfd + - items: + - const: ingenic,jz4780-tcu + - const: ingenic,jz4770-tcu + - const: simple-mfd + + reg: + maxItems: 1 + + clocks: + items: + - description: RTC clock + - description: EXT clock + - description: PCLK clock + - description: TCU clock + minItems: 3 + + clock-names: + items: + - const: rtc + - const: ext + - const: pclk + - const: tcu + minItems: 3 + + interrupts: + items: + - description: TCU0 interrupt + - description: TCU1 interrupt + - description: TCU2 interrupt + minItems: 1 + + assigned-clocks: + minItems: 1 + maxItems: 8 + + assigned-clock-parents: + minItems: 1 + maxItems: 8 + + assigned-clock-rates: + minItems: 1 + maxItems: 8 + + ingenic,pwm-channels-mask: + description: Bitmask of TCU channels reserved for PWM use. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x00 + maximum: 0xff + default: 0xfc + +patternProperties: + "^watchdog@[a-f0-9]+$": + type: object + $ref: ../watchdog/watchdog.yaml# + properties: + compatible: + oneOf: + - enum: + - ingenic,jz4740-watchdog + - ingenic,jz4780-watchdog + - items: + - const: ingenic,jz4770-watchdog + - const: ingenic,jz4740-watchdog + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: wdt + + required: + - compatible + - reg + - clocks + - clock-names + + "^pwm@[a-f0-9]+$": + type: object + $ref: ../pwm/pwm.yaml# + properties: + compatible: + oneOf: + - enum: + - ingenic,jz4740-pwm + - items: + - enum: + - ingenic,jz4770-pwm + - ingenic,jz4780-pwm + - const: ingenic,jz4740-pwm + + reg: + maxItems: 1 + + clocks: + minItems: 6 + maxItems: 8 + + clock-names: + items: + - const: timer0 + - const: timer1 + - const: timer2 + - const: timer3 + - const: timer4 + - const: timer5 + - const: timer6 + - const: timer7 + minItems: 6 + + required: + - compatible + - reg + - clocks + - clock-names + + "^timer@[a-f0-9]+$": + type: object + properties: + compatible: + oneOf: + - enum: + - ingenic,jz4725b-ost + - ingenic,jz4770-ost + - items: + - const: ingenic,jz4780-ost + - const: ingenic,jz4770-ost + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: ost + + interrupts: + maxItems: 1 + + required: + - compatible + - reg + - clocks + - clock-names + - interrupts + + additionalProperties: false + +required: + - "#clock-cells" + - "#interrupt-cells" + - interrupt-controller + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + tcu: timer@10002000 { + compatible = "ingenic,jz4770-tcu", "simple-mfd"; + reg = <0x10002000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10002000 0x1000>; + + #clock-cells = <1>; + + clocks = <&cgu JZ4770_CLK_RTC>, + <&cgu JZ4770_CLK_EXT>, + <&cgu JZ4770_CLK_PCLK>; + clock-names = "rtc", "ext", "pclk"; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&intc>; + interrupts = <27 26 25>; + + watchdog: watchdog@0 { + compatible = "ingenic,jz4770-watchdog", "ingenic,jz4740-watchdog"; + reg = <0x0 0xc>; + + clocks = <&tcu TCU_CLK_WDT>; + clock-names = "wdt"; + }; + + pwm: pwm@40 { + compatible = "ingenic,jz4770-pwm", "ingenic,jz4740-pwm"; + reg = <0x40 0x80>; + + #pwm-cells = <3>; + + clocks = <&tcu TCU_CLK_TIMER0>, + <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_TIMER2>, + <&tcu TCU_CLK_TIMER3>, + <&tcu TCU_CLK_TIMER4>, + <&tcu TCU_CLK_TIMER5>, + <&tcu TCU_CLK_TIMER6>, + <&tcu TCU_CLK_TIMER7>; + clock-names = "timer0", "timer1", "timer2", "timer3", + "timer4", "timer5", "timer6", "timer7"; + }; + + ost: timer@e0 { + compatible = "ingenic,jz4770-ost"; + reg = <0xe0 0x20>; + + clocks = <&tcu TCU_CLK_OST>; + clock-names = "ost"; + + interrupts = <15>; + }; + }; diff --git a/Bindings/timer/nxp,sysctr-timer.txt b/Bindings/timer/nxp,sysctr-timer.txt deleted file mode 100644 index d57659996d62..000000000000 --- a/Bindings/timer/nxp,sysctr-timer.txt +++ /dev/null @@ -1,25 +0,0 @@ -NXP System Counter Module(sys_ctr) - -The system counter(sys_ctr) is a programmable system counter which provides -a shared time base to Cortex A15, A7, A53, A73, etc. it is intended for use in -applications where the counter is always powered and support multiple, -unrelated clocks. The compare frame inside can be used for timer purpose. - -Required properties: - -- compatible : should be "nxp,sysctr-timer" -- reg : Specifies the base physical address and size of the comapre - frame and the counter control, read & compare. -- interrupts : should be the first compare frames' interrupt -- clocks : Specifies the counter clock. -- clock-names: Specifies the clock's name of this module - -Example: - - system_counter: timer@306a0000 { - compatible = "nxp,sysctr-timer"; - reg = <0x306a0000 0x20000>;/* system-counter-rd & compare */ - clocks = <&clk_8m>; - clock-names = "per"; - interrupts = ; - }; diff --git a/Bindings/timer/nxp,sysctr-timer.yaml b/Bindings/timer/nxp,sysctr-timer.yaml new file mode 100644 index 000000000000..830211c55b4a --- /dev/null +++ b/Bindings/timer/nxp,sysctr-timer.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/nxp,sysctr-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP System Counter Module(sys_ctr) + +maintainers: + - Bai Ping + +description: | + The system counter(sys_ctr) is a programmable system counter + which provides a shared time base to Cortex A15, A7, A53, A73, + etc. it is intended for use in applications where the counter + is always powered and support multiple, unrelated clocks. The + compare frame inside can be used for timer purpose. + +properties: + compatible: + const: nxp,sysctr-timer + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: per + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + + timer@306a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x306a0000 0x20000>; + clocks = <&clk_8m>; + clock-names = "per"; + interrupts = ; + }; diff --git a/Bindings/timer/nxp,tpm-timer.txt b/Bindings/timer/nxp,tpm-timer.txt deleted file mode 100644 index f82087b220f4..000000000000 --- a/Bindings/timer/nxp,tpm-timer.txt +++ /dev/null @@ -1,28 +0,0 @@ -NXP Low Power Timer/Pulse Width Modulation Module (TPM) - -The Timer/PWM Module (TPM) supports input capture, output compare, -and the generation of PWM signals to control electric motor and power -management applications. The counter, compare and capture registers -are clocked by an asynchronous clock that can remain enabled in low -power modes. TPM can support global counter bus where one TPM drives -the counter bus for the others, provided bit width is the same. - -Required properties: - -- compatible : should be "fsl,imx7ulp-tpm" -- reg : Specifies base physical address and size of the register sets - for the clock event device and clock source device. -- interrupts : Should be the clock event device interrupt. -- clocks : The clocks provided by the SoC to drive the timer, must contain - an entry for each entry in clock-names. -- clock-names : Must include the following entries: "ipg" and "per". - -Example: -tpm5: tpm@40260000 { - compatible = "fsl,imx7ulp-tpm"; - reg = <0x40260000 0x1000>; - interrupts = ; - clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>, - <&clks IMX7ULP_CLK_LPTPM5>; - clock-names = "ipg", "per"; -}; diff --git a/Bindings/timer/nxp,tpm-timer.yaml b/Bindings/timer/nxp,tpm-timer.yaml new file mode 100644 index 000000000000..edd9585f6726 --- /dev/null +++ b/Bindings/timer/nxp,tpm-timer.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Low Power Timer/Pulse Width Modulation Module (TPM) + +maintainers: + - Dong Aisheng + +description: | + The Timer/PWM Module (TPM) supports input capture, output compare, + and the generation of PWM signals to control electric motor and power + management applications. The counter, compare and capture registers + are clocked by an asynchronous clock that can remain enabled in low + power modes. TPM can support global counter bus where one TPM drives + the counter bus for the others, provided bit width is the same. + +properties: + compatible: + const: fsl,imx7ulp-tpm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: SoC TPM ipg clock + - description: SoC TPM per clock + + clock-names: + items: + - const: ipg + - const: per + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + timer@40260000 { + compatible = "fsl,imx7ulp-tpm"; + reg = <0x40260000 0x1000>; + interrupts = ; + clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, + <&pcc2 IMX7ULP_CLK_LPTPM5>; + clock-names = "ipg", "per"; + }; diff --git a/Bindings/timer/renesas,cmt.txt b/Bindings/timer/renesas,cmt.txt deleted file mode 100644 index a747fabab7d3..000000000000 --- a/Bindings/timer/renesas,cmt.txt +++ /dev/null @@ -1,110 +0,0 @@ -* Renesas R-Car Compare Match Timer (CMT) - -The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock -inputs and programmable compare match. - -Channels share hardware resources but their counter and compare match value -are independent. A particular CMT instance can implement only a subset of the -channels supported by the CMT model. Channel indices represent the hardware -position of the channel in the CMT and don't match the channel numbers in the -datasheets. - -Required Properties: - - - compatible: must contain one or more of the following: - - "renesas,r8a73a4-cmt0" for the 32-bit CMT0 device included in r8a73a4. - - "renesas,r8a73a4-cmt1" for the 48-bit CMT1 device included in r8a73a4. - - "renesas,r8a7740-cmt0" for the 32-bit CMT0 device included in r8a7740. - - "renesas,r8a7740-cmt1" for the 48-bit CMT1 device included in r8a7740. - - "renesas,r8a7740-cmt2" for the 32-bit CMT2 device included in r8a7740. - - "renesas,r8a7740-cmt3" for the 32-bit CMT3 device included in r8a7740. - - "renesas,r8a7740-cmt4" for the 32-bit CMT4 device included in r8a7740. - - "renesas,r8a7743-cmt0" for the 32-bit CMT0 device included in r8a7743. - - "renesas,r8a7743-cmt1" for the 48-bit CMT1 device included in r8a7743. - - "renesas,r8a7744-cmt0" for the 32-bit CMT0 device included in r8a7744. - - "renesas,r8a7744-cmt1" for the 48-bit CMT1 device included in r8a7744. - - "renesas,r8a7745-cmt0" for the 32-bit CMT0 device included in r8a7745. - - "renesas,r8a7745-cmt1" for the 48-bit CMT1 device included in r8a7745. - - "renesas,r8a77470-cmt0" for the 32-bit CMT0 device included in r8a77470. - - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470. - - "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1. - - "renesas,r8a774a1-cmt1" for the 48-bit CMT devices included in r8a774a1. - - "renesas,r8a774b1-cmt0" for the 32-bit CMT0 device included in r8a774b1. - - "renesas,r8a774b1-cmt1" for the 48-bit CMT devices included in r8a774b1. - - "renesas,r8a774c0-cmt0" for the 32-bit CMT0 device included in r8a774c0. - - "renesas,r8a774c0-cmt1" for the 48-bit CMT devices included in r8a774c0. - - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. - - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790. - - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791. - - "renesas,r8a7791-cmt1" for the 48-bit CMT1 device included in r8a7791. - - "renesas,r8a7792-cmt0" for the 32-bit CMT0 device included in r8a7792. - - "renesas,r8a7792-cmt1" for the 48-bit CMT1 device included in r8a7792. - - "renesas,r8a7793-cmt0" for the 32-bit CMT0 device included in r8a7793. - - "renesas,r8a7793-cmt1" for the 48-bit CMT1 device included in r8a7793. - - "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794. - - "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794. - - "renesas,r8a7795-cmt0" for the 32-bit CMT0 device included in r8a7795. - - "renesas,r8a7795-cmt1" for the 48-bit CMT devices included in r8a7795. - - "renesas,r8a7796-cmt0" for the 32-bit CMT0 device included in r8a7796. - - "renesas,r8a7796-cmt1" for the 48-bit CMT devices included in r8a7796. - - "renesas,r8a77965-cmt0" for the 32-bit CMT0 device included in r8a77965. - - "renesas,r8a77965-cmt1" for the 48-bit CMT devices included in r8a77965. - - "renesas,r8a77970-cmt0" for the 32-bit CMT0 device included in r8a77970. - - "renesas,r8a77970-cmt1" for the 48-bit CMT devices included in r8a77970. - - "renesas,r8a77980-cmt0" for the 32-bit CMT0 device included in r8a77980. - - "renesas,r8a77980-cmt1" for the 48-bit CMT devices included in r8a77980. - - "renesas,r8a77990-cmt0" for the 32-bit CMT0 device included in r8a77990. - - "renesas,r8a77990-cmt1" for the 48-bit CMT devices included in r8a77990. - - "renesas,r8a77995-cmt0" for the 32-bit CMT0 device included in r8a77995. - - "renesas,r8a77995-cmt1" for the 48-bit CMT devices included in r8a77995. - - "renesas,sh73a0-cmt0" for the 32-bit CMT0 device included in sh73a0. - - "renesas,sh73a0-cmt1" for the 48-bit CMT1 device included in sh73a0. - - "renesas,sh73a0-cmt2" for the 32-bit CMT2 device included in sh73a0. - - "renesas,sh73a0-cmt3" for the 32-bit CMT3 device included in sh73a0. - - "renesas,sh73a0-cmt4" for the 32-bit CMT4 device included in sh73a0. - - - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2 - and RZ/G1. - - "renesas,rcar-gen2-cmt1" for 48-bit CMT1 devices included in R-Car Gen2 - and RZ/G1. - These are fallbacks for r8a73a4, R-Car Gen2 and RZ/G1 entries - listed above. - - "renesas,rcar-gen3-cmt0" for 32-bit CMT0 devices included in R-Car Gen3 - and RZ/G2. - - "renesas,rcar-gen3-cmt1" for 48-bit CMT devices included in R-Car Gen3 - and RZ/G2. - These are fallbacks for R-Car Gen3 and RZ/G2 entries listed - above. - - - reg: base address and length of the registers block for the timer module. - - interrupts: interrupt-specifier for the timer, one per channel. - - clocks: a list of phandle + clock-specifier pairs, one for each entry - in clock-names. - - clock-names: must contain "fck" for the functional clock. - - -Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes - - cmt0: timer@ffca0000 { - compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0"; - reg = <0 0xffca0000 0 0x1004>; - interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, - <0 142 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp1_clks R8A7790_CLK_CMT0>; - clock-names = "fck"; - }; - - cmt1: timer@e6130000 { - compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1"; - reg = <0 0xe6130000 0 0x1004>; - interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, - <0 121 IRQ_TYPE_LEVEL_HIGH>, - <0 122 IRQ_TYPE_LEVEL_HIGH>, - <0 123 IRQ_TYPE_LEVEL_HIGH>, - <0 124 IRQ_TYPE_LEVEL_HIGH>, - <0 125 IRQ_TYPE_LEVEL_HIGH>, - <0 126 IRQ_TYPE_LEVEL_HIGH>, - <0 127 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_CMT1>; - clock-names = "fck"; - }; diff --git a/Bindings/timer/renesas,cmt.yaml b/Bindings/timer/renesas,cmt.yaml new file mode 100644 index 000000000000..7e4dc5623da8 --- /dev/null +++ b/Bindings/timer/renesas,cmt.yaml @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/renesas,cmt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Compare Match Timer (CMT) + +maintainers: + - Geert Uytterhoeven + - Laurent Pinchart + +description: + The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock + inputs and programmable compare match. + + Channels share hardware resources but their counter and compare match values + are independent. A particular CMT instance can implement only a subset of the + channels supported by the CMT model. Channel indices represent the hardware + position of the channel in the CMT and don't match the channel numbers in the + datasheets. + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1 + - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1 + - renesas,r8a7740-cmt2 # 32-bit CMT2 on R-Mobile A1 + - renesas,r8a7740-cmt3 # 32-bit CMT3 on R-Mobile A1 + - renesas,r8a7740-cmt4 # 32-bit CMT4 on R-Mobile A1 + - renesas,sh73a0-cmt0 # 32-bit CMT0 on SH-Mobile AG5 + - renesas,sh73a0-cmt1 # 48-bit CMT1 on SH-Mobile AG5 + - renesas,sh73a0-cmt2 # 32-bit CMT2 on SH-Mobile AG5 + - renesas,sh73a0-cmt3 # 32-bit CMT3 on SH-Mobile AG5 + - renesas,sh73a0-cmt4 # 32-bit CMT4 on SH-Mobile AG5 + + - items: + - enum: + - renesas,r8a73a4-cmt0 # 32-bit CMT0 on R-Mobile APE6 + - renesas,r8a7743-cmt0 # 32-bit CMT0 on RZ/G1M + - renesas,r8a7744-cmt0 # 32-bit CMT0 on RZ/G1N + - renesas,r8a7745-cmt0 # 32-bit CMT0 on RZ/G1E + - renesas,r8a77470-cmt0 # 32-bit CMT0 on RZ/G1C + - renesas,r8a7790-cmt0 # 32-bit CMT0 on R-Car H2 + - renesas,r8a7791-cmt0 # 32-bit CMT0 on R-Car M2-W + - renesas,r8a7792-cmt0 # 32-bit CMT0 on R-Car V2H + - renesas,r8a7793-cmt0 # 32-bit CMT0 on R-Car M2-N + - renesas,r8a7794-cmt0 # 32-bit CMT0 on R-Car E2 + - const: renesas,rcar-gen2-cmt0 # 32-bit CMT0 on R-Mobile APE6, R-Car Gen2 and RZ/G1 + + - items: + - enum: + - renesas,r8a73a4-cmt1 # 48-bit CMT1 on R-Mobile APE6 + - renesas,r8a7743-cmt1 # 48-bit CMT1 on RZ/G1M + - renesas,r8a7744-cmt1 # 48-bit CMT1 on RZ/G1N + - renesas,r8a7745-cmt1 # 48-bit CMT1 on RZ/G1E + - renesas,r8a77470-cmt1 # 48-bit CMT1 on RZ/G1C + - renesas,r8a7790-cmt1 # 48-bit CMT1 on R-Car H2 + - renesas,r8a7791-cmt1 # 48-bit CMT1 on R-Car M2-W + - renesas,r8a7792-cmt1 # 48-bit CMT1 on R-Car V2H + - renesas,r8a7793-cmt1 # 48-bit CMT1 on R-Car M2-N + - renesas,r8a7794-cmt1 # 48-bit CMT1 on R-Car E2 + - const: renesas,rcar-gen2-cmt1 # 48-bit CMT1 on R-Mobile APE6, R-Car Gen2 and RZ/G1 + + - items: + - enum: + - renesas,r8a774a1-cmt0 # 32-bit CMT0 on RZ/G2M + - renesas,r8a774b1-cmt0 # 32-bit CMT0 on RZ/G2N + - renesas,r8a774c0-cmt0 # 32-bit CMT0 on RZ/G2E + - renesas,r8a7795-cmt0 # 32-bit CMT0 on R-Car H3 + - renesas,r8a7796-cmt0 # 32-bit CMT0 on R-Car M3-W + - renesas,r8a77965-cmt0 # 32-bit CMT0 on R-Car M3-N + - renesas,r8a77970-cmt0 # 32-bit CMT0 on R-Car V3M + - renesas,r8a77980-cmt0 # 32-bit CMT0 on R-Car V3H + - renesas,r8a77990-cmt0 # 32-bit CMT0 on R-Car E3 + - renesas,r8a77995-cmt0 # 32-bit CMT0 on R-Car D3 + - const: renesas,rcar-gen3-cmt0 # 32-bit CMT0 on R-Car Gen3 and RZ/G2 + + - items: + - enum: + - renesas,r8a774a1-cmt1 # 48-bit CMT on RZ/G2M + - renesas,r8a774b1-cmt1 # 48-bit CMT on RZ/G2N + - renesas,r8a774c0-cmt1 # 48-bit CMT on RZ/G2E + - renesas,r8a7795-cmt1 # 48-bit CMT on R-Car H3 + - renesas,r8a7796-cmt1 # 48-bit CMT on R-Car M3-W + - renesas,r8a77965-cmt1 # 48-bit CMT on R-Car M3-N + - renesas,r8a77970-cmt1 # 48-bit CMT on R-Car V3M + - renesas,r8a77980-cmt1 # 48-bit CMT on R-Car V3H + - renesas,r8a77990-cmt1 # 48-bit CMT on R-Car E3 + - renesas,r8a77995-cmt1 # 48-bit CMT on R-Car D3 + - const: renesas,rcar-gen3-cmt1 # 48-bit CMT on R-Car Gen3 and RZ/G2 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 8 + + clocks: + maxItems: 1 + + clock-names: + const: fck + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-cmt0 + - renesas,rcar-gen3-cmt0 + then: + properties: + interrupts: + minItems: 2 + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - renesas,rcar-gen2-cmt1 + - renesas,rcar-gen3-cmt1 + then: + properties: + interrupts: + minItems: 8 + maxItems: 8 + +additionalProperties: false + +examples: + - | + #include + #include + #include + cmt0: timer@ffca0000 { + compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0"; + reg = <0xffca0000 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 124>; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1"; + reg = <0xe6130000 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 329>; + }; diff --git a/Bindings/timer/renesas,em-sti.yaml b/Bindings/timer/renesas,em-sti.yaml new file mode 100644 index 000000000000..233d74d5402c --- /dev/null +++ b/Bindings/timer/renesas,em-sti.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/renesas,em-sti.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas EMMA Mobile System Timer + +maintainers: + - Magnus Damm + +properties: + compatible: + const: renesas,em-sti + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: sclk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + timer@e0180000 { + compatible = "renesas,em-sti"; + reg = <0xe0180000 0x54>; + interrupts = ; + clocks = <&sti_sclk>; + clock-names = "sclk"; + }; diff --git a/Bindings/timer/renesas,mtu2.txt b/Bindings/timer/renesas,mtu2.txt deleted file mode 100644 index ba0a34d97eb8..000000000000 --- a/Bindings/timer/renesas,mtu2.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Renesas Multi-Function Timer Pulse Unit 2 (MTU2) - -The MTU2 is a multi-purpose, multi-channel timer/counter with configurable -clock inputs and programmable compare match. - -Channels share hardware resources but their counter and compare match value -are independent. The MTU2 hardware supports five channels indexed from 0 to 4. - -Required Properties: - - - compatible: must be one or more of the following: - - "renesas,mtu2-r7s72100" for the r7s72100 MTU2 - - "renesas,mtu2" for any MTU2 - This is a fallback for the above renesas,mtu2-* entries - - - reg: base address and length of the registers block for the timer module. - - - interrupts: interrupt specifiers for the timer, one for each entry in - interrupt-names. - - interrupt-names: must contain one entry named "tgi?a" for each enabled - channel, where "?" is the channel index expressed as one digit from "0" to - "4". - - - clocks: a list of phandle + clock-specifier pairs, one for each entry - in clock-names. - - clock-names: must contain "fck" for the functional clock. - - -Example: R7S72100 (RZ/A1H) MTU2 node - - mtu2: timer@fcff0000 { - compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; - reg = <0xfcff0000 0x400>; - interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>, - <0 146 IRQ_TYPE_LEVEL_HIGH>, - <0 150 IRQ_TYPE_LEVEL_HIGH>, - <0 154 IRQ_TYPE_LEVEL_HIGH>, - <0 159 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tgi0a", "tgi1a", "tgi2a", "tgi3a", "tgi4a"; - clocks = <&mstp3_clks R7S72100_CLK_MTU2>; - clock-names = "fck"; - }; diff --git a/Bindings/timer/renesas,mtu2.yaml b/Bindings/timer/renesas,mtu2.yaml new file mode 100644 index 000000000000..15d8dddf4ae9 --- /dev/null +++ b/Bindings/timer/renesas,mtu2.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/renesas,mtu2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Multi-Function Timer Pulse Unit 2 (MTU2) + +maintainers: + - Geert Uytterhoeven + - Laurent Pinchart + +description: + The MTU2 is a multi-purpose, multi-channel timer/counter with configurable clock inputs + and programmable compare match. + + Channels share hardware resources but their counter and compare match value are + independent. The MTU2 hardware supports five channels indexed from 0 to 4. + +properties: + compatible: + items: + - enum: + - renesas,mtu2-r7s72100 # RZ/A1H + - const: renesas,mtu2 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 5 + description: One entry for each enabled channel. + + interrupt-names: + minItems: 1 + items: + - const: tgi0a + - const: tgi1a + - const: tgi2a + - const: tgi3a + - const: tgi4a + + clocks: + maxItems: 1 + + clock-names: + const: fck + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + mtu2: timer@fcff0000 { + compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; + reg = <0xfcff0000 0x400>; + interrupts = ; + interrupt-names = "tgi0a"; + clocks = <&mstp3_clks R7S72100_CLK_MTU2>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + }; diff --git a/Bindings/timer/renesas,ostm.txt b/Bindings/timer/renesas,ostm.txt deleted file mode 100644 index 81a78f8bcf17..000000000000 --- a/Bindings/timer/renesas,ostm.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Renesas OS Timer (OSTM) - -The OSTM is a multi-channel 32-bit timer/counter with fixed clock -source that can operate in either interval count down timer or free-running -compare match mode. - -Channels are independent from each other. - -Required Properties: - - - compatible: must be one or more of the following: - - "renesas,r7s72100-ostm" for the R7S72100 (RZ/A1) OSTM - - "renesas,r7s9210-ostm" for the R7S9210 (RZ/A2) OSTM - - "renesas,ostm" for any OSTM - This is a fallback for the above renesas,*-ostm entries - - - reg: base address and length of the register block for a timer channel. - - - interrupts: interrupt specifier for the timer channel. - - - clocks: clock specifier for the timer channel. - -Example: R7S72100 (RZ/A1H) OSTM node - - ostm0: timer@fcfec000 { - compatible = "renesas,r7s72100-ostm", "renesas,ostm"; - reg = <0xfcfec000 0x30>; - interrupts = ; - clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; - power-domains = <&cpg_clocks>; - }; diff --git a/Bindings/timer/renesas,ostm.yaml b/Bindings/timer/renesas,ostm.yaml new file mode 100644 index 000000000000..600d47ab7d58 --- /dev/null +++ b/Bindings/timer/renesas,ostm.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/renesas,ostm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas OS Timer (OSTM) + +maintainers: + - Chris Brandt + - Geert Uytterhoeven + +description: + The OSTM is a multi-channel 32-bit timer/counter with fixed clock source that + can operate in either interval count down timer or free-running compare match + mode. + + Channels are independent from each other. + +properties: + compatible: + items: + - enum: + - renesas,r7s72100-ostm # RZ/A1H + - renesas,r7s9210-ostm # RZ/A2M + - const: renesas,ostm # Generic + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + ostm0: timer@fcfec000 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec000 0x30>; + interrupts = ; + clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; + power-domains = <&cpg_clocks>; + }; diff --git a/Bindings/timer/snps,dw-apb-timer.yaml b/Bindings/timer/snps,dw-apb-timer.yaml new file mode 100644 index 000000000000..5d300efdf0ca --- /dev/null +++ b/Bindings/timer/snps,dw-apb-timer.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare APB Timer + +maintainers: + - Daniel Lezcano + +properties: + compatible: + oneOf: + - const: snps,dw-apb-timer + - enum: + - snps,dw-apb-timer-sp + - snps,dw-apb-timer-osc + deprecated: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: Timer ticks reference clock source + - description: APB interface clock source + + clock-names: + minItems: 1 + items: + - const: timer + - const: pclk + + clock-frequency: true + + clock-freq: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: | + Has the same meaning as the 'clock-frequency' property - timer clock + frequency in HZ, but is defined only for the backwards compatibility + with the picoxcell platform. + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + +oneOf: + - required: + - clocks + - clock-names + - required: + - clock-frequency + - required: + - clock-freq + +examples: + - | + timer@ffe00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffe00000 0x1000>; + clocks = <&timer_clk>, <&timer_pclk>; + clock-names = "timer", "pclk"; + }; + - | + timer@ffe00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffe00000 0x1000>; + clocks = <&timer_clk>; + clock-names = "timer"; + }; + - | + timer@ffe00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 170 4>; + reg = <0xffe00000 0x1000>; + clock-frequency = <25000000>; + }; +... diff --git a/Bindings/ufs/ti,j721e-ufs.yaml b/Bindings/ufs/ti,j721e-ufs.yaml index c8a2a92074df..4d13e6bc1c50 100644 --- a/Bindings/ufs/ti,j721e-ufs.yaml +++ b/Bindings/ufs/ti,j721e-ufs.yaml @@ -25,6 +25,20 @@ properties: power-domains: maxItems: 1 + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + required: - compatible - reg @@ -39,30 +53,39 @@ patternProperties: Documentation/devicetree/bindings/ufs/cdns,ufshc.txt for binding documentation of child node +additionalProperties: false + examples: - | #include #include - ufs_wrapper: ufs-wrapper@4e80000 { - compatible = "ti,j721e-ufs"; - reg = <0x0 0x4e80000 0x0 0x100>; - power-domains = <&k3_pds 277>; - clocks = <&k3_clks 277 1>; - assigned-clocks = <&k3_clks 277 1>; - assigned-clock-parents = <&k3_clks 277 4>; - #address-cells = <2>; - #size-cells = <2>; + bus { + #address-cells = <2>; + #size-cells = <2>; - ufs@4e84000 { - compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; - reg = <0x0 0x4e84000 0x0 0x10000>; - interrupts = ; - freq-table-hz = <19200000 19200000>; - power-domains = <&k3_pds 277>; - clocks = <&k3_clks 277 1>; - assigned-clocks = <&k3_clks 277 1>; - assigned-clock-parents = <&k3_clks 277 4>; - clock-names = "core_clk"; - }; + ufs-wrapper@4e80000 { + compatible = "ti,j721e-ufs"; + reg = <0x0 0x4e80000 0x0 0x100>; + power-domains = <&k3_pds 277>; + clocks = <&k3_clks 277 1>; + assigned-clocks = <&k3_clks 277 1>; + assigned-clock-parents = <&k3_clks 277 4>; + + ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>; + #address-cells = <2>; + #size-cells = <2>; + + ufs@4000 { + compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; + reg = <0x0 0x4000 0x0 0x10000>; + interrupts = ; + freq-table-hz = <19200000 19200000>; + power-domains = <&k3_pds 277>; + clocks = <&k3_clks 277 1>; + assigned-clocks = <&k3_clks 277 1>; + assigned-clock-parents = <&k3_clks 277 4>; + clock-names = "core_clk"; + }; + }; }; diff --git a/Bindings/usb/amlogic,dwc3.txt b/Bindings/usb/amlogic,dwc3.txt deleted file mode 100644 index 9a8b631904fd..000000000000 --- a/Bindings/usb/amlogic,dwc3.txt +++ /dev/null @@ -1,42 +0,0 @@ -Amlogic Meson GX DWC3 USB SoC controller - -Required properties: -- compatible: depending on the SoC this should contain one of: - * amlogic,meson-axg-dwc3 - * amlogic,meson-gxl-dwc3 -- clocks: a handle for the "USB general" clock -- clock-names: must be "usb_general" -- resets: a handle for the shared "USB OTG" reset line -- reset-names: must be "usb_otg" - -Required child node: -A child node must exist to represent the core DWC3 IP block. The name of -the node is not important. The content of the node is defined in dwc3.txt. - -PHY documentation is provided in the following places: -- Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt -- Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt - -Example device nodes: - usb0: usb@ff500000 { - compatible = "amlogic,meson-axg-dwc3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&clkc CLKID_USB>; - clock-names = "usb_general"; - resets = <&reset RESET_USB_OTG>; - reset-names = "usb_otg"; - - dwc3: dwc3@ff500000 { - compatible = "snps,dwc3"; - reg = <0x0 0xff500000 0x0 0x100000>; - interrupts = ; - dr_mode = "host"; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - phys = <&usb3_phy>, <&usb2_phy0>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; diff --git a/Bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml index b0e5e0fe9386..5b04a7dfa018 100644 --- a/Bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml +++ b/Bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml @@ -25,9 +25,13 @@ description: | The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in host-only mode. + The Amlogic GXL & GXM SoCs doesn't embed an USB3 PHY. + properties: compatible: enum: + - amlogic,meson-gxl-usb-ctrl + - amlogic,meson-gxm-usb-ctrl - amlogic,meson-g12a-usb-ctrl - amlogic,meson-a1-usb-ctrl @@ -41,6 +45,11 @@ properties: clocks: minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 resets: minItems: 1 @@ -52,10 +61,8 @@ properties: maxItems: 1 phy-names: - items: - - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used - - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used - - const: usb3-phy0 # USB3 PHY if USB3_0 is used + minItems: 1 + maxItems: 3 phys: minItems: 1 @@ -89,6 +96,61 @@ required: - dr_mode allOf: + - if: + properties: + compatible: + enum: + - amlogic,meson-g12a-usb-ctrl + + then: + properties: + phy-names: + items: + - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used + - const: usb3-phy0 # USB3 PHY if USB3_0 is used + - if: + properties: + compatible: + enum: + - amlogic,meson-gxl-usb-ctrl + + then: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: usb_ctrl + - const: ddr + phy-names: + items: + - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used + required: + - clock-names + - if: + properties: + compatible: + enum: + - amlogic,meson-gxm-usb-ctrl + + then: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: usb_ctrl + - const: ddr + phy-names: + items: + - const: usb2-phy0 # USB2 PHY0 if USBHOST_A port is used + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used + - const: usb2-phy2 # USB2 PHY2 if USBOTG_C port is used + + required: + - clock-names - if: properties: compatible: @@ -97,6 +159,9 @@ allOf: then: properties: + phy-names: + items: + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used clocks: minItems: 3 clock-names: @@ -111,7 +176,7 @@ examples: - | usb: usb@ffe09000 { compatible = "amlogic,meson-g12a-usb-ctrl"; - reg = <0x0 0xffe09000 0x0 0xa0>; + reg = <0xffe09000 0xa0>; interrupts = <16>; #address-cells = <1>; #size-cells = <1>; @@ -147,4 +212,3 @@ examples: snps,quirk-frame-length-adjustment; }; }; - diff --git a/Bindings/usb/aspeed,usb-vhub.yaml b/Bindings/usb/aspeed,usb-vhub.yaml index 06399ba0d9e4..8b019ac05bbe 100644 --- a/Bindings/usb/aspeed,usb-vhub.yaml +++ b/Bindings/usb/aspeed,usb-vhub.yaml @@ -38,19 +38,64 @@ properties: aspeed,vhub-downstream-ports: description: Number of downstream ports supported by the Virtual Hub - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - default: 5 - minimum: 1 - maximum: 7 + $ref: /schemas/types.yaml#/definitions/uint32 + default: 5 + minimum: 1 + maximum: 7 aspeed,vhub-generic-endpoints: description: Number of generic endpoints supported by the Virtual Hub - allOf: - - $ref: /schemas/types.yaml#/definitions/uint32 - - default: 15 - minimum: 1 - maximum: 21 + $ref: /schemas/types.yaml#/definitions/uint32 + default: 15 + minimum: 1 + maximum: 21 + + vhub-vendor-id: + description: vhub Vendor ID + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 65535 + + vhub-product-id: + description: vhub Product ID + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 65535 + + vhub-device-revision: + description: vhub Device Revision in binary-coded decimal + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 65535 + + vhub-strings: + type: object + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + '^string@[0-9a-f]+$': + type: object + description: string descriptors of the specific language + + properties: + reg: + maxItems: 1 + description: 16-bit Language Identifier defined by USB-IF + + manufacturer: + description: vhub manufacturer + $ref: /schemas/types.yaml#/definitions/string + + product: + description: vhub product name + $ref: /schemas/types.yaml#/definitions/string + + serial-number: + description: vhub device serial number + $ref: /schemas/types.yaml#/definitions/string required: - compatible @@ -74,4 +119,19 @@ examples: aspeed,vhub-generic-endpoints = <15>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2ad_default>; + + vhub-vendor-id = <0x1d6b>; + vhub-product-id = <0x0107>; + vhub-device-revision = <0x0100>; + vhub-strings { + #address-cells = <1>; + #size-cells = <0>; + + string@409 { + reg = <0x409>; + manufacturer = "ASPEED"; + product = "USB Virtual Hub"; + serial-number = "0000"; + }; + }; }; diff --git a/Bindings/usb/atmel-usb.txt b/Bindings/usb/atmel-usb.txt index 44e80153b148..423b99a8fd97 100644 --- a/Bindings/usb/atmel-usb.txt +++ b/Bindings/usb/atmel-usb.txt @@ -88,13 +88,15 @@ Required properties: - clock-names: Should contain two strings "pclk" for the peripheral clock "hclk" for the host clock + +Deprecated property: - ep childnode: To specify the number of endpoints and their properties. Optional properties: - atmel,vbus-gpio: If present, specifies a gpio that allows to detect whether vbus is present (USB is connected). -Required child node properties: +Deprecated child node properties: - name: Name of the endpoint. - reg: Num of the endpoint. - atmel,fifo-size: Size of the fifo. @@ -112,56 +114,4 @@ usb2: gadget@fff78000 { clocks = <&utmi>, <&udphs_clk>; clock-names = "hclk", "pclk"; atmel,vbus-gpio = <&pioB 19 0>; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; }; diff --git a/Bindings/usb/brcm,bcm7445-ehci.yaml b/Bindings/usb/brcm,bcm7445-ehci.yaml new file mode 100644 index 000000000000..2a9acf2b5a64 --- /dev/null +++ b/Bindings/usb/brcm,bcm7445-ehci.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/brcm,bcm7445-ehci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom STB USB EHCI Controller Device Tree Bindings + +allOf: + - $ref: "usb-hcd.yaml" + +maintainers: + - Al Cooper + +properties: + compatible: + const: brcm,bcm7445-ehci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: Clock specifier for the EHCI clock + + clock-names: + const: sw_usb + + phys: + maxItems: 1 + + phy-names: + const: usbphy + +required: + - compatible + - reg + - interrupts + - phys + - clocks + +additionalProperties: false + +examples: + - | + usb@f0b00300 { + compatible = "brcm,bcm7445-ehci"; + reg = <0xf0b00300 0xa8>; + interrupts = <0x0 0x5a 0x0>; + phys = <&usbphy_0 0x0>; + phy-names = "usbphy"; + clocks = <&usb20>; + clock-names = "sw_usb"; + }; + +... diff --git a/Bindings/usb/dwc2.yaml b/Bindings/usb/dwc2.yaml index 0d6d850a7f17..9352a8ef60a6 100644 --- a/Bindings/usb/dwc2.yaml +++ b/Bindings/usb/dwc2.yaml @@ -62,14 +62,14 @@ properties: resets: items: - - description: common reset - - description: ecc reset + - description: common reset + - description: ecc reset minItems: 1 reset-names: items: - - const: dwc2 - - const: dwc2-ecc + - const: dwc2 + - const: dwc2-ecc minItems: 1 phys: @@ -78,6 +78,9 @@ properties: phy-names: const: usb2-phy + power-domains: + maxItems: 1 + vbus-supply: description: reference to the VBUS regulator. Depending on the current mode this is enabled (in "host" mode") or disabled (in "peripheral" mode). The diff --git a/Bindings/usb/dwc3.txt b/Bindings/usb/dwc3.txt index 9946ff9ba735..d03edf9d3935 100644 --- a/Bindings/usb/dwc3.txt +++ b/Bindings/usb/dwc3.txt @@ -15,8 +15,6 @@ Required properties: Exception for clocks: clocks are optional if the parent node (i.e. glue-layer) is compatible to one of the following: - "amlogic,meson-axg-dwc3" - "amlogic,meson-gxl-dwc3" "cavium,octeon-7130-usb-uctl" "qcom,dwc3" "samsung,exynos5250-dwusb3" diff --git a/Bindings/usb/ehci-mv.txt b/Bindings/usb/ehci-mv.txt deleted file mode 100644 index 335589895763..000000000000 --- a/Bindings/usb/ehci-mv.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Marvell PXA/MMP EHCI controller. - -Required properties: - -- compatible: must be "marvell,pxau2o-ehci" -- reg: physical base addresses of the controller and length of memory mapped region -- interrupts: one EHCI controller interrupt should be described here -- clocks: phandle list of usb clocks -- clock-names: should be "USBCLK" -- phys: phandle for the PHY device -- phy-names: should be "usb" - -Example: - - ehci0: usb-ehci@d4208000 { - compatible = "marvell,pxau2o-ehci"; - reg = <0xd4208000 0x200>; - interrupts = <44>; - clocks = <&soc_clocks MMP2_CLK_USB>; - clock-names = "USBCLK"; - phys = <&usb_otg_phy>; - phy-names = "usb"; - }; diff --git a/Bindings/usb/generic-ehci.yaml b/Bindings/usb/generic-ehci.yaml index 10edd05872ea..69f3f26d1207 100644 --- a/Bindings/usb/generic-ehci.yaml +++ b/Bindings/usb/generic-ehci.yaml @@ -6,19 +6,30 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: USB EHCI Controller Device Tree Bindings -allOf: - - $ref: "usb-hcd.yaml" - maintainers: - Greg Kroah-Hartman +allOf: + - $ref: "usb-hcd.yaml" + - if: + properties: + compatible: + not: + contains: + const: ibm,usb-ehci-440epx + then: + properties: + reg: + maxItems: 1 + properties: compatible: contains: const: generic-ehci reg: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupts: maxItems: 1 @@ -36,6 +47,9 @@ properties: - if a USB DRD channel: first clock should be host and second one should be peripheral + power-domains: + maxItems: 1 + big-endian: $ref: /schemas/types.yaml#/definitions/flag description: @@ -74,6 +88,9 @@ properties: phy-names: const: usb + iommus: + maxItems: 1 + required: - compatible - reg @@ -87,7 +104,7 @@ examples: compatible = "ibm,usb-ehci-440epx", "generic-ehci"; interrupt-parent = <&UIC0>; interrupts = <0x1a 4>; - reg = <0 0xe0000300 90 0 0xe0000390 70>; + reg = <0xe0000300 90>, <0xe0000390 70>; big-endian; }; diff --git a/Bindings/usb/generic-ohci.yaml b/Bindings/usb/generic-ohci.yaml index bcffec1f1341..2178bcc401bc 100644 --- a/Bindings/usb/generic-ohci.yaml +++ b/Bindings/usb/generic-ohci.yaml @@ -36,6 +36,9 @@ properties: - if a USB DRD channel: first clock should be host and second one should be peripheral + power-domains: + maxItems: 1 + big-endian: $ref: /schemas/types.yaml#/definitions/flag description: @@ -73,6 +76,9 @@ properties: phy-names: const: usb + iommus: + maxItems: 1 + required: - compatible - reg diff --git a/Bindings/usb/ingenic,musb.yaml b/Bindings/usb/ingenic,musb.yaml index c2d2ee43ba67..c334aea6b59d 100644 --- a/Bindings/usb/ingenic,musb.yaml +++ b/Bindings/usb/ingenic,musb.yaml @@ -42,6 +42,9 @@ properties: phys: description: PHY specifier for the USB PHY + usb-role-switch: + type: boolean + required: - compatible - reg diff --git a/Bindings/usb/keystone-usb.txt b/Bindings/usb/keystone-usb.txt deleted file mode 100644 index 77df82e36138..000000000000 --- a/Bindings/usb/keystone-usb.txt +++ /dev/null @@ -1,56 +0,0 @@ -TI Keystone Soc USB Controller - -DWC3 GLUE - -Required properties: - - compatible: should be - "ti,keystone-dwc3" for Keystone 2 SoCs - "ti,am654-dwc3" for AM654 SoC - - #address-cells, #size-cells : should be '1' if the device has sub-nodes - with 'reg' property. - - reg : Address and length of the register set for the USB subsystem on - the SOC. - - interrupts : The irq number of this device that is used to interrupt the - MPU. - - ranges: allows valid 1:1 translation between child's address space and - parent's address space. - -SoC-specific Required Properties: -The following are mandatory properties for Keystone 2 66AK2HK, 66AK2L and 66AK2E -SoCs only: - -- clocks: Clock ID for USB functional clock. -- clock-names: Must be "usb". - - -The following are mandatory properties for 66AK2G and AM654: - -- power-domains: Should contain a phandle to a PM domain provider node - and an args specifier containing the USB device id - value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt - -Sub-nodes: -The dwc3 core should be added as subnode to Keystone DWC3 glue. -- dwc3 : - The binding details of dwc3 can be found in: - Documentation/devicetree/bindings/usb/dwc3.txt - -Example: - usb: usb@2680000 { - compatible = "ti,keystone-dwc3"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x2680000 0x10000>; - clocks = <&clkusb>; - clock-names = "usb"; - interrupts = ; - ranges; - - dwc3@2690000 { - compatible = "synopsys,dwc3"; - reg = <0x2690000 0x70000>; - interrupts = ; - usb-phy = <&usb_phy>, <&usb_phy>; - }; - }; diff --git a/Bindings/usb/marvell,pxau2o-ehci.yaml b/Bindings/usb/marvell,pxau2o-ehci.yaml new file mode 100644 index 000000000000..3cf93dd45eb7 --- /dev/null +++ b/Bindings/usb/marvell,pxau2o-ehci.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2019,2020 Lubomir Rintel +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/marvell,pxau2o-ehci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell PXA/MMP EHCI bindings + +maintainers: + - Lubomir Rintel + +allOf: + - $ref: usb-hcd.yaml# + +properties: + compatible: + const: marvell,pxau2o-ehci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: USBCLK + + phys: + maxItems: 1 + + phy-names: + const: usb + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - phys + - phy-names + +unevaluatedProperties: false + +examples: + - | + #include + usb@d4208000 { + compatible = "marvell,pxau2o-ehci"; + reg = <0xd4208000 0x200>; + interrupts = <44>; + clocks = <&soc_clocks MMP2_CLK_USB>; + clock-names = "USBCLK"; + phys = <&usb_otg_phy>; + phy-names = "usb"; + }; + +... diff --git a/Bindings/usb/nvidia,tegra-xudc.yaml b/Bindings/usb/nvidia,tegra-xudc.yaml index b84ed8ee8cfc..0073763a30d8 100644 --- a/Bindings/usb/nvidia,tegra-xudc.yaml +++ b/Bindings/usb/nvidia,tegra-xudc.yaml @@ -21,6 +21,7 @@ properties: - enum: - nvidia,tegra210-xudc # For Tegra210 - nvidia,tegra186-xudc # For Tegra186 + - nvidia,tegra194-xudc # For Tegra194 reg: minItems: 2 @@ -63,13 +64,11 @@ properties: - const: hs_src power-domains: - maxItems: 2 items: - description: XUSBB(device) power-domain - description: XUSBA(superspeed) power-domain power-domain-names: - maxItems: 2 items: - const: dev - const: ss @@ -144,6 +143,7 @@ allOf: contains: enum: - nvidia,tegra186-xudc + - nvidia,tegra194-xudc then: properties: reg: @@ -163,9 +163,9 @@ examples: usb@700d0000 { compatible = "nvidia,tegra210-xudc"; - reg = <0x0 0x700d0000 0x0 0x8000>, - <0x0 0x700d8000 0x0 0x1000>, - <0x0 0x700d9000 0x0 0x1000>; + reg = <0x700d0000 0x8000>, + <0x700d8000 0x1000>, + <0x700d9000 0x1000>; reg-names = "base", "fpci", "ipfs"; interrupts = ; diff --git a/Bindings/usb/qcom,dwc3.txt b/Bindings/usb/qcom,dwc3.txt deleted file mode 100644 index fbdd01756752..000000000000 --- a/Bindings/usb/qcom,dwc3.txt +++ /dev/null @@ -1,104 +0,0 @@ -Qualcomm SuperSpeed DWC3 USB SoC controller - -Required properties: -- compatible: Compatible list, contains - "qcom,dwc3" - "qcom,msm8996-dwc3" for msm8996 SOC. - "qcom,msm8998-dwc3" for msm8998 SOC. - "qcom,sdm845-dwc3" for sdm845 SOC. -- reg: Offset and length of register set for QSCRATCH wrapper -- power-domains: specifies a phandle to PM domain provider node -- clocks: A list of phandle + clock-specifier pairs for the - clocks listed in clock-names -- clock-names: Should contain the following: - "core" Master/Core clock, have to be >= 125 MHz for SS - operation and >= 60MHz for HS operation - "mock_utmi" Mock utmi clock needed for ITP/SOF generation in - host mode. Its frequency should be 19.2MHz. - "sleep" Sleep clock, used for wakeup when USB3 core goes - into low power mode (U3). - -Optional clocks: - "iface" System bus AXI clock. - Not present on "qcom,msm8996-dwc3" compatible. - "cfg_noc" System Config NOC clock. - Not present on "qcom,msm8996-dwc3" compatible. -- assigned-clocks: Should be: - MOCK_UTMI_CLK - MASTER_CLK -- assigned-clock-rates: Should be: - 19.2Mhz (192000000) for MOCK_UTMI_CLK - >=125Mhz (125000000) for MASTER_CLK in SS mode - >=60Mhz (60000000) for MASTER_CLK in HS mode - -Optional properties: -- resets: Phandle to reset control that resets core and wrapper. -- interrupts: specifies interrupts from controller wrapper used - to wakeup from low power/susepnd state. Must contain - one or more entry for interrupt-names property -- interrupt-names: Must include the following entries: - - "hs_phy_irq": The interrupt that is asserted when a - wakeup event is received on USB2 bus - - "ss_phy_irq": The interrupt that is asserted when a - wakeup event is received on USB3 bus - - "dm_hs_phy_irq" and "dp_hs_phy_irq": Separate - interrupts for any wakeup event on DM and DP lines -- qcom,select-utmi-as-pipe-clk: if present, disable USB3 pipe_clk requirement. - Used when dwc3 operates without SSPHY and only - HS/FS/LS modes are supported. - -Required child node: -A child node must exist to represent the core DWC3 IP block. The name of -the node is not important. The content of the node is defined in dwc3.txt. - -Phy documentation is provided in the following places: -Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY -Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml - USB2 QUSB2 PHY - -Example device nodes: - - hs_phy: phy@100f8800 { - compatible = "qcom,qusb2-v2-phy"; - ... - }; - - ss_phy: phy@100f8830 { - compatible = "qcom,qmp-v3-usb3-phy"; - ... - }; - - usb3_0: usb30@a6f8800 { - compatible = "qcom,dwc3"; - reg = <0xa6f8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>; - clock-names = "core", "mock_utmi", "sleep"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <133000000>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - reset-names = "core_reset"; - power-domains = <&gcc USB30_PRIM_GDSC>; - qcom,select-utmi-as-pipe-clk; - - dwc3@10000000 { - compatible = "snps,dwc3"; - reg = <0x10000000 0xcd00>; - interrupts = <0 205 0x4>; - phys = <&hs_phy>, <&ss_phy>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "host"; - }; - }; - diff --git a/Bindings/usb/qcom,dwc3.yaml b/Bindings/usb/qcom,dwc3.yaml new file mode 100644 index 000000000000..dac10848dd7f --- /dev/null +++ b/Bindings/usb/qcom,dwc3.yaml @@ -0,0 +1,174 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SuperSpeed DWC3 USB SoC controller + +maintainers: + - Manu Gautam + +properties: + compatible: + items: + - enum: + - qcom,msm8996-dwc3 + - qcom,msm8998-dwc3 + - qcom,sc7180-dwc3 + - qcom,sdm845-dwc3 + - const: qcom,dwc3 + + reg: + description: Offset and length of register set for QSCRATCH wrapper + maxItems: 1 + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + ranges: true + + power-domains: + description: specifies a phandle to PM domain provider node + maxItems: 1 + + clocks: + description: + A list of phandle and clock-specifier pairs for the clocks + listed in clock-names. + items: + - description: System Config NOC clock. + - description: Master/Core clock, has to be >= 125 MHz + for SS operation and >= 60MHz for HS operation. + - description: System bus AXI clock. + - description: Mock utmi clock needed for ITP/SOF generation + in host mode. Its frequency should be 19.2MHz. + - description: Sleep clock, used for wakeup when + USB3 core goes into low power mode (U3). + + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: mock_utmi + - const: sleep + + assigned-clocks: + items: + - description: Phandle and clock specifier of MOCK_UTMI_CLK. + - description: Phandle and clock specifoer of MASTER_CLK. + + assigned-clock-rates: + items: + - description: Must be 19.2MHz (19200000). + - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode. + resets: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: usb-ddr + - const: apps-usb + + interrupts: + items: + - description: The interrupt that is asserted + when a wakeup event is received on USB2 bus. + - description: The interrupt that is asserted + when a wakeup event is received on USB3 bus. + - description: Wakeup event on DM line. + - description: Wakeup event on DP line. + + interrupt-names: + items: + - const: hs_phy_irq + - const: ss_phy_irq + - const: dm_hs_phy_irq + - const: dp_hs_phy_irq + + qcom,select-utmi-as-pipe-clk: + description: + If present, disable USB3 pipe_clk requirement. + Used when dwc3 operates without SSPHY and only + HS/FS/LS modes are supported. + type: boolean + +# Required child node: + +patternProperties: + "^dwc3@[0-9a-f]+$": + type: object + description: + A child node must exist to represent the core DWC3 IP block + The content of the node is defined in dwc3.txt. + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + - power-domains + - clocks + - clock-names + - interrupts + - interrupt-names + +examples: + - | + #include + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + usb@a6f8800 { + compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts = , + , + , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x740 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + }; diff --git a/Bindings/usb/renesas,usb3-peri.yaml b/Bindings/usb/renesas,usb3-peri.yaml index 031452aa25bc..e3cdeab1199f 100644 --- a/Bindings/usb/renesas,usb3-peri.yaml +++ b/Bindings/usb/renesas,usb3-peri.yaml @@ -73,7 +73,7 @@ examples: usb3_peri0: usb@ee020000 { compatible = "renesas,r8a774c0-usb3-peri", "renesas,rcar-gen3-usb3-peri"; - reg = <0 0xee020000 0 0x400>; + reg = <0xee020000 0x400>; interrupts = ; clocks = <&cpg CPG_MOD 328>; companion = <&xhci0>; diff --git a/Bindings/usb/renesas,usbhs.yaml b/Bindings/usb/renesas,usbhs.yaml index a7ae95598ccb..af4826fb6824 100644 --- a/Bindings/usb/renesas,usbhs.yaml +++ b/Bindings/usb/renesas,usbhs.yaml @@ -22,6 +22,7 @@ properties: - items: - enum: + - renesas,usbhs-r8a7742 # RZ/G1H - renesas,usbhs-r8a7743 # RZ/G1M - renesas,usbhs-r8a7744 # RZ/G1N - renesas,usbhs-r8a7745 # RZ/G1E @@ -121,7 +122,7 @@ examples: usbhs: usb@e6590000 { compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs"; - reg = <0 0xe6590000 0 0x100>; + reg = <0xe6590000 0x100>; interrupts = ; clocks = <&cpg CPG_MOD 704>; }; diff --git a/Bindings/usb/ti,j721e-usb.yaml b/Bindings/usb/ti,j721e-usb.yaml index 5f5264b2e9ad..90750255792f 100644 --- a/Bindings/usb/ti,j721e-usb.yaml +++ b/Bindings/usb/ti,j721e-usb.yaml @@ -57,30 +57,36 @@ examples: - | #include #include - cdns_usb@4104000 { - compatible = "ti,j721e-usb"; - reg = <0x00 0x4104000 0x00 0x100>; - power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; - clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ - assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ - #address-cells = <2>; - #size-cells = <2>; - usb@6000000 { - compatible = "cdns,usb3"; - reg = <0x00 0x6000000 0x00 0x10000>, - <0x00 0x6010000 0x00 0x10000>, - <0x00 0x6020000 0x00 0x10000>; - reg-names = "otg", "xhci", "dev"; - interrupts = , /* irq.0 */ - , /* irq.6 */ - ; /* otgirq.0 */ - interrupt-names = "host", - "peripheral", - "otg"; - maximum-speed = "super-speed"; - dr_mode = "otg"; + bus { + #address-cells = <2>; + #size-cells = <2>; + + cdns_usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x4104000 0x00 0x100>; + power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ + #address-cells = <2>; + #size-cells = <2>; + + usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x6000000 0x00 0x10000>, + <0x00 0x6010000 0x00 0x10000>, + <0x00 0x6020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq.0 */ + interrupt-names = "host", + "peripheral", + "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; }; }; diff --git a/Bindings/usb/ti,keystone-dwc3.yaml b/Bindings/usb/ti,keystone-dwc3.yaml new file mode 100644 index 000000000000..f127535feb0b --- /dev/null +++ b/Bindings/usb/ti,keystone-dwc3.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Keystone Soc USB Controller + +maintainers: + - Roger Quadros + +properties: + compatible: + oneOf: + - const: "ti,keystone-dwc3" + - const: "ti,am654-dwc3" + + reg: + maxItems: 1 + description: Address and length of the register set for the USB subsystem on + the SOC. + + interrupts: + maxItems: 1 + description: The irq number of this device that is used to interrupt the MPU. + + + clocks: + description: Clock ID for USB functional clock. + + power-domains: + description: Should contain a phandle to a PM domain provider node + and an args specifier containing the USB device id + value. This property is as per the binding, + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt + + phys: + description: + PHY specifier for the USB3.0 PHY. Some SoCs need the USB3.0 PHY + to be turned on before the controller. + Documentation/devicetree/bindings/phy/phy-bindings.txt + + phy-names: + items: + - const: "usb3-phy" + + dwc3: + description: This is the node representing the DWC3 controller instance + Documentation/devicetree/bindings/usb/dwc3.txt + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + #include + + usb: usb@2680000 { + compatible = "ti,keystone-dwc3"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2680000 0x10000>; + clocks = <&clkusb>; + clock-names = "usb"; + interrupts = ; + ranges; + + dwc3@2690000 { + compatible = "synopsys,dwc3"; + reg = <0x2690000 0x70000>; + interrupts = ; + usb-phy = <&usb_phy>, <&usb_phy>; + }; + }; diff --git a/Bindings/usb/ti,tps6598x.yaml b/Bindings/usb/ti,tps6598x.yaml new file mode 100644 index 000000000000..8eaf4b6c4735 --- /dev/null +++ b/Bindings/usb/ti,tps6598x.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/ti,tps6598x.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Texas Instruments 6598x Type-C Port Switch and Power Delivery controller DT bindings + +maintainers: + - Bryan O'Donoghue + +description: | + Texas Instruments 6598x Type-C Port Switch and Power Delivery controller + +properties: + compatible: + enum: + - ti,tps6598x + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: irq + +required: + - compatible + - reg + - interrupts + - interrupt-names + +examples: + - | + #include + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + tps6598x: tps6598x@38 { + compatible = "ti,tps6598x"; + reg = <0x38>; + + interrupt-parent = <&msmgpio>; + interrupts = <107 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + + pinctrl-names = "default"; + pinctrl-0 = <&typec_pins>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + port { + typec_ep: endpoint { + remote-endpoint = <&otg_ep>; + }; + }; + }; + }; + }; +... diff --git a/Bindings/usb/usb-conn-gpio.txt b/Bindings/usb/usb-conn-gpio.txt deleted file mode 100644 index ec80641208a5..000000000000 --- a/Bindings/usb/usb-conn-gpio.txt +++ /dev/null @@ -1,30 +0,0 @@ -USB GPIO Based Connection Detection - -This is typically used to switch dual role mode from the USB ID pin connected -to an input GPIO, and also used to enable/disable device mode from the USB -Vbus pin connected to an input GPIO. - -Required properties: -- compatible : should include "gpio-usb-b-connector" and "usb-b-connector". -- id-gpios, vbus-gpios : input gpios, either one of them must be present, - and both can be present as well. - see connector/usb-connector.yaml - -Optional properties: -- vbus-supply : can be present if needed when supports dual role mode. - see connector/usb-connector.yaml - -- Sub-nodes: - - port : can be present. - see graph.txt - -Example: - -&mtu3 { - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - type = "micro"; - id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>; - vbus-supply = <&usb_p0_vbus>; - }; -}; diff --git a/Bindings/usb/usb-xhci.txt b/Bindings/usb/usb-xhci.txt index dc025f126d71..b120dd6612a2 100644 --- a/Bindings/usb/usb-xhci.txt +++ b/Bindings/usb/usb-xhci.txt @@ -7,6 +7,7 @@ Required properties: - "marvell,armada3700-xhci" for Armada 37xx SoCs - "marvell,armada-375-xhci" for Armada 375 SoCs - "marvell,armada-380-xhci" for Armada 38x SoCs + - "renesas,xhci-r8a7742" for r8a7742 SoC - "renesas,xhci-r8a7743" for r8a7743 SoC - "renesas,xhci-r8a7744" for r8a7744 SoC - "renesas,xhci-r8a774a1" for r8a774a1 SoC @@ -24,6 +25,7 @@ Required properties: device - "renesas,rcar-gen3-xhci" for a generic R-Car Gen3 or RZ/G2 compatible device + - "brcm,bcm7445-xhci" for Broadcom STB SoCs with XHCI - "xhci-platform" (deprecated) When compatible with the generic version, nodes must list the diff --git a/Bindings/vendor-prefixes.yaml b/Bindings/vendor-prefixes.yaml index d3891386d671..9aeab66be85f 100644 --- a/Bindings/vendor-prefixes.yaml +++ b/Bindings/vendor-prefixes.yaml @@ -59,6 +59,8 @@ patternProperties: description: Allwinner Technology Co., Ltd. "^alphascale,.*": description: AlphaScale Integrated Circuits Systems, Inc. + "^alps,.*": + description: Alps Electric Co., Ltd. "^altr,.*": description: Altera Corp. "^amarula,.*": @@ -131,6 +133,8 @@ patternProperties: description: Shanghai AVIC Optoelectronics Co., Ltd. "^avnet,.*": description: Avnet, Inc. + "^awinic,.*": + description: Shanghai Awinic Technology Co., Ltd. "^axentia,.*": description: Axentia Technologies AB "^axis,.*": @@ -139,10 +143,14 @@ patternProperties: description: Azoteq (Pty) Ltd "^azw,.*": description: Shenzhen AZW Technology Co., Ltd. + "^baikal,.*": + description: BAIKAL ELECTRONICS, JSC "^bananapi,.*": description: BIPAI KEJI LIMITED "^beacon,.*": description: Compass Electronics Group, LLC + "^beagle,.*": + description: BeagleBoard.org Foundation "^bhf,.*": description: Beckhoff Automation GmbH & Co. KG "^bitmain,.*": @@ -179,14 +187,20 @@ patternProperties: description: Cadence Design Systems Inc. "^cdtech,.*": description: CDTech(H.K.) Electronics Limited + "^cellwise,.*": + description: CellWise Microelectronics Co., Ltd "^ceva,.*": description: Ceva, Inc. + "^checkpoint,.*": + description: Check Point Software Technologies Ltd. "^chipidea,.*": description: Chipidea, Inc "^chipone,.*": description: ChipOne "^chipspark,.*": description: ChipSPARK + "^chrontel,.*": + description: Chrontel, Inc. "^chrp,.*": description: Common Hardware Reference Platform "^chunghwa,.*": @@ -463,6 +477,8 @@ patternProperties: description: Infineon Technologies "^inforce,.*": description: Inforce Computing + "^ivo,.*": + description: InfoVision Optoelectronics Kunshan Co. Ltd. "^ingenic,.*": description: Ingenic Semiconductor "^innolux,.*": @@ -488,7 +504,7 @@ patternProperties: "^issi,.*": description: Integrated Silicon Solutions Inc. "^ite,.*": - description: ITE Tech, Inc. + description: ITE Tech. Inc. "^itead,.*": description: ITEAD Intelligent Systems Co.Ltd "^iwave,.*": @@ -585,6 +601,8 @@ patternProperties: description: LSI Corp. (LSI Logic) "^lwn,.*": description: Liebherr-Werk Nenzing GmbH + "^lxa,.*": + description: Linux Automation GmbH "^macnica,.*": description: Macnica Americas "^mapleboard,.*": @@ -633,6 +651,8 @@ patternProperties: description: Microsoft Corporation "^mikroe,.*": description: MikroElektronika d.o.o. + "^mikrotik,.*": + description: MikroTik "^miniand,.*": description: Miniand Tech "^minix,.*": @@ -808,6 +828,8 @@ patternProperties: description: Primux Trading, S.L. "^probox2,.*": description: PROBOX2 (by W2COMP Co., Ltd.) + "^prt,.*": + description: Protonic Holland "^pulsedlight,.*": description: PulsedLight, Inc "^purism,.*": @@ -900,6 +922,8 @@ patternProperties: description: Sharp Corporation "^shimafuji,.*": description: Shimafuji Electric, Inc. + "^shiratech,.*": + description: Shiratech Solutions "^si-en,.*": description: Si-En Technology Ltd. "^si-linux,.*": @@ -918,6 +942,8 @@ patternProperties: description: Silead Inc. "^silergy,.*": description: Silergy Corp. + "^silex-insight,.*": + description: Silex Insight "^siliconmitus,.*": description: Silicon Mitus, Inc. "^simtek,.*": @@ -936,6 +962,8 @@ patternProperties: description: Sitronix Technology Corporation "^skyworks,.*": description: Skyworks Solutions, Inc. + "^smartlabs,.*": + description: SmartLabs LLC "^smsc,.*": description: Standard Microsystems Corporation "^snps,.*": @@ -1039,12 +1067,16 @@ patternProperties: description: Tronsmart "^truly,.*": description: Truly Semiconductors Limited + "^visionox,.*": + description: Visionox "^tsd,.*": description: Theobroma Systems Design und Consulting GmbH "^tyan,.*": description: Tyan Computer Corporation "^u-blox,.*": description: u-blox + "^u-boot,.*": + description: U-Boot bootloader "^ucrobotics,.*": description: uCRobotics "^ubnt,.*": @@ -1065,6 +1097,8 @@ patternProperties: description: Aigo Digital Technology Co., Ltd. "^v3,.*": description: V3 Semiconductor + "^vaisala,.*": + description: Vaisala "^vamrs,.*": description: Vamrs Ltd. "^variscite,.*": @@ -1093,6 +1127,8 @@ patternProperties: description: Waveshare Electronics "^wd,.*": description: Western Digital Corp. + "^we,.*": + description: Würth Elektronik GmbH. "^wetek,.*": description: WeTek Electronics, limited. "^wexler,.*": @@ -1125,6 +1161,8 @@ patternProperties: description: Shenzhen Xinpeng Technology Co., Ltd "^xlnx,.*": description: Xilinx + "^xnano,.*": + description: Xnano "^xunlong,.*": description: Shenzhen Xunlong Software CO.,Limited "^xylon,.*": diff --git a/Bindings/watchdog/arm-smc-wdt.yaml b/Bindings/watchdog/arm-smc-wdt.yaml new file mode 100644 index 000000000000..8e4c7c69bc1c --- /dev/null +++ b/Bindings/watchdog/arm-smc-wdt.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/arm-smc-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Secure Monitor Call based watchdog + +allOf: + - $ref: "watchdog.yaml#" + +maintainers: + - Julius Werner + +properties: + compatible: + enum: + - arm,smc-wdt + arm,smc-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The ATF smc function id used by the firmware. + Defaults to 0x82003D06 if unset. + +required: + - compatible + +examples: + - | + watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0x82003D06>; + timeout-sec = <15>; + }; + +... diff --git a/Bindings/watchdog/fsl-imx-wdt.txt b/Bindings/watchdog/fsl-imx-wdt.txt deleted file mode 100644 index adc6b76fcb3a..000000000000 --- a/Bindings/watchdog/fsl-imx-wdt.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Freescale i.MX Watchdog Timer (WDT) Controller - -Required properties: -- compatible : Should be "fsl,-wdt" -- reg : Should contain WDT registers location and length -- interrupts : Should contain WDT interrupt - -Optional properties: -- big-endian: If present the watchdog device's registers are implemented - in big endian mode, otherwise in native mode(same with CPU), for more - detail please see: Documentation/devicetree/bindings/regmap/regmap.txt. -- fsl,ext-reset-output: If present the watchdog device is configured to - assert its external reset (WDOG_B) instead of issuing a software reset. -- timeout-sec : Contains the watchdog timeout in seconds - -Examples: - -wdt@73f98000 { - compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; - reg = <0x73f98000 0x4000>; - interrupts = <58>; - big-endian; - timeout-sec = <20>; -}; diff --git a/Bindings/watchdog/fsl-imx-wdt.yaml b/Bindings/watchdog/fsl-imx-wdt.yaml new file mode 100644 index 000000000000..d96b93b11fad --- /dev/null +++ b/Bindings/watchdog/fsl-imx-wdt.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/fsl-imx-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX Watchdog Timer (WDT) Controller + +maintainers: + - Anson Huang + +allOf: + - $ref: "watchdog.yaml#" + +properties: + compatible: + enum: + - fsl,imx21-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + fsl,ext-reset-output: + $ref: /schemas/types.yaml#/definitions/flag + description: | + If present, the watchdog device is configured to assert its + external reset (WDOG_B) instead of issuing a software reset. + +required: + - compatible + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + + watchdog@20bc000 { + compatible = "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPG>; + }; + +... diff --git a/Bindings/watchdog/fsl-imx7ulp-wdt.txt b/Bindings/watchdog/fsl-imx7ulp-wdt.txt deleted file mode 100644 index f902508d6cac..000000000000 --- a/Bindings/watchdog/fsl-imx7ulp-wdt.txt +++ /dev/null @@ -1,22 +0,0 @@ -* Freescale i.MX7ULP Watchdog Timer (WDT) Controller - -Required properties: -- compatible : Should be "fsl,imx7ulp-wdt" -- reg : Should contain WDT registers location and length -- interrupts : Should contain WDT interrupt -- clocks: Should contain a phandle pointing to the gated peripheral clock. - -Optional properties: -- timeout-sec : Contains the watchdog timeout in seconds - -Examples: - -wdog1: watchdog@403d0000 { - compatible = "fsl,imx7ulp-wdt"; - reg = <0x403d0000 0x10000>; - interrupts = ; - clocks = <&pcc2 IMX7ULP_CLK_WDG1>; - assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; - assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; - timeout-sec = <40>; -}; diff --git a/Bindings/watchdog/fsl-imx7ulp-wdt.yaml b/Bindings/watchdog/fsl-imx7ulp-wdt.yaml new file mode 100644 index 000000000000..51d6d482bbc2 --- /dev/null +++ b/Bindings/watchdog/fsl-imx7ulp-wdt.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/fsl-imx7ulp-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX7ULP Watchdog Timer (WDT) Controller + +maintainers: + - Anson Huang + +allOf: + - $ref: "watchdog.yaml#" + +properties: + compatible: + enum: + - fsl,imx7ulp-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + assigned-clocks: + maxItems: 1 + + assigned-clocks-parents: + maxItems: 1 + + timeout-sec: true + +required: + - compatible + - interrupts + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + watchdog@403d0000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x403d0000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + timeout-sec = <40>; + }; + +... diff --git a/Bindings/watchdog/renesas,wdt.txt b/Bindings/watchdog/renesas,wdt.txt deleted file mode 100644 index 79b3c62f183d..000000000000 --- a/Bindings/watchdog/renesas,wdt.txt +++ /dev/null @@ -1,50 +0,0 @@ -Renesas Watchdog Timer (WDT) Controller - -Required properties: - - compatible : Must be "renesas,-wdt", followed by a generic - fallback compatible string when compatible with the generic - version. - Examples with soctypes are: - - "renesas,r8a7743-wdt" (RZ/G1M) - - "renesas,r8a7744-wdt" (RZ/G1N) - - "renesas,r8a7745-wdt" (RZ/G1E) - - "renesas,r8a77470-wdt" (RZ/G1C) - - "renesas,r8a774a1-wdt" (RZ/G2M) - - "renesas,r8a774b1-wdt" (RZ/G2N) - - "renesas,r8a774c0-wdt" (RZ/G2E) - - "renesas,r8a7790-wdt" (R-Car H2) - - "renesas,r8a7791-wdt" (R-Car M2-W) - - "renesas,r8a7792-wdt" (R-Car V2H) - - "renesas,r8a7793-wdt" (R-Car M2-N) - - "renesas,r8a7794-wdt" (R-Car E2) - - "renesas,r8a7795-wdt" (R-Car H3) - - "renesas,r8a7796-wdt" (R-Car M3-W) - - "renesas,r8a77961-wdt" (R-Car M3-W+) - - "renesas,r8a77965-wdt" (R-Car M3-N) - - "renesas,r8a77970-wdt" (R-Car V3M) - - "renesas,r8a77990-wdt" (R-Car E3) - - "renesas,r8a77995-wdt" (R-Car D3) - - "renesas,r7s72100-wdt" (RZ/A1) - - "renesas,r7s9210-wdt" (RZ/A2) - The generic compatible string must be: - - "renesas,rza-wdt" for RZ/A - - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G1 - - "renesas,rcar-gen3-wdt" for R-Car Gen3 and RZ/G2 - -- reg : Should contain WDT registers location and length -- clocks : the clock feeding the watchdog timer. - -Optional properties: -- timeout-sec : Contains the watchdog timeout in seconds -- power-domains : the power domain the WDT belongs to -- interrupts: Some WDTs have an interrupt when used in interval timer mode - -Examples: - - wdt0: watchdog@e6020000 { - compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&cpg>; - timeout-sec = <60>; - }; diff --git a/Bindings/watchdog/renesas,wdt.yaml b/Bindings/watchdog/renesas,wdt.yaml new file mode 100644 index 000000000000..572f4c912fef --- /dev/null +++ b/Bindings/watchdog/renesas,wdt.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/renesas,wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Watchdog Timer (WDT) Controller + +maintainers: + - Wolfram Sang + - Geert Uytterhoeven + +allOf: + - $ref: "watchdog.yaml#" + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r7s72100-wdt # RZ/A1 + - renesas,r7s9210-wdt # RZ/A2 + - const: renesas,rza-wdt # RZ/A + + - items: + - enum: + - renesas,r8a7742-wdt # RZ/G1H + - renesas,r8a7743-wdt # RZ/G1M + - renesas,r8a7744-wdt # RZ/G1N + - renesas,r8a7745-wdt # RZ/G1E + - renesas,r8a77470-wdt # RZ/G1C + - renesas,r8a7790-wdt # R-Car H2 + - renesas,r8a7791-wdt # R-Car M2-W + - renesas,r8a7792-wdt # R-Car V2H + - renesas,r8a7793-wdt # R-Car M2-N + - renesas,r8a7794-wdt # R-Car E2 + - const: renesas,rcar-gen2-wdt # R-Car Gen2 and RZ/G1 + + - items: + - enum: + - renesas,r8a774a1-wdt # RZ/G2M + - renesas,r8a774b1-wdt # RZ/G2N + - renesas,r8a774c0-wdt # RZ/G2E + - renesas,r8a7795-wdt # R-Car H3 + - renesas,r8a7796-wdt # R-Car M3-W + - renesas,r8a77961-wdt # R-Car M3-W+ + - renesas,r8a77965-wdt # R-Car M3-N + - renesas,r8a77970-wdt # R-Car V3M + - renesas,r8a77980-wdt # R-Car V3H + - renesas,r8a77990-wdt # R-Car E3 + - renesas,r8a77995-wdt # R-Car D3 + - const: renesas,rcar-gen3-wdt # R-Car Gen3 and RZ/G2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + timeout-sec: true + +required: + - compatible + - reg + - clocks + +if: + not: + properties: + compatible: + contains: + enum: + - renesas,rza-wdt +then: + required: + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + wdt0: watchdog@e6020000 { + compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; + reg = <0xe6020000 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 402>; + timeout-sec = <60>; + }; diff --git a/Bindings/watchdog/socionext,uniphier-wdt.yaml b/Bindings/watchdog/socionext,uniphier-wdt.yaml new file mode 100644 index 000000000000..a059d16cb4f2 --- /dev/null +++ b/Bindings/watchdog/socionext,uniphier-wdt.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/socionext,uniphier-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier watchdog timer + +maintainers: + - Keiji Hayashibara + +allOf: + - $ref: "watchdog.yaml#" + +properties: + compatible: + const: socionext,uniphier-wdt + +required: + - compatible + +additionalProperties: false + +examples: + - | + // The UniPhier watchdog should be a subnode of a "syscon" compatible node. + + sysctrl@61840000 { + compatible = "socionext,uniphier-ld11-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x10000>; + + watchdog { + compatible = "socionext,uniphier-wdt"; + }; + }; diff --git a/Bindings/watchdog/ti,rti-wdt.yaml b/Bindings/watchdog/ti,rti-wdt.yaml index e83026fef2e9..f0452791c598 100644 --- a/Bindings/watchdog/ti,rti-wdt.yaml +++ b/Bindings/watchdog/ti,rti-wdt.yaml @@ -57,7 +57,7 @@ examples: watchdog0: rti@2200000 { compatible = "ti,rti-wdt"; - reg = <0x0 0x2200000 0x0 0x100>; + reg = <0x2200000 0x100>; clocks = <&k3_clks 252 1>; power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; assigned-clocks = <&k3_clks 252 1>; diff --git a/Bindings/watchdog/uniphier-wdt.txt b/Bindings/watchdog/uniphier-wdt.txt deleted file mode 100644 index bf6337546dd1..000000000000 --- a/Bindings/watchdog/uniphier-wdt.txt +++ /dev/null @@ -1,20 +0,0 @@ -UniPhier watchdog timer controller - -This UniPhier watchdog timer controller must be under sysctrl node. - -Required properties: -- compatible: should be "socionext,uniphier-wdt" - -Example: - - sysctrl@61840000 { - compatible = "socionext,uniphier-ld11-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - watchdog { - compatible = "socionext,uniphier-wdt"; - } - - other nodes ... - }; diff --git a/Bindings/writing-bindings.txt b/Bindings/writing-bindings.rst similarity index 89% rename from Bindings/writing-bindings.txt rename to Bindings/writing-bindings.rst index 27dfd2d8016e..45ff426d0019 100644 --- a/Bindings/writing-bindings.txt +++ b/Bindings/writing-bindings.rst @@ -1,13 +1,18 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================================================ DOs and DON'Ts for designing and writing Devicetree bindings +============================================================ This is a list of common review feedback items focused on binding design. With every rule, there are exceptions and bindings have many gray areas. For guidelines related to patches, see -Documentation/devicetree/bindings/submitting-patches.txt +Documentation/devicetree/bindings/submitting-patches.rst Overall design +============== - DO attempt to make bindings complete even if a driver doesn't support some features. For example, if a device has an interrupt, then include the @@ -32,6 +37,7 @@ Overall design Properties +========== - DO make 'compatible' properties specific. DON'T use wildcards in compatible strings. DO use fallback compatibles when devices are the same as or a subset @@ -53,6 +59,7 @@ Properties Board/SoC .dts Files +==================== - DO put all MMIO devices under a bus node and not at the top-level. diff --git a/Bindings/xilinx.txt b/Bindings/xilinx.txt index d058ace29345..28199b31fe5e 100644 --- a/Bindings/xilinx.txt +++ b/Bindings/xilinx.txt @@ -86,149 +86,6 @@ xlnx,use-parity = <0>; }; - Some IP cores actually implement 2 or more logical devices. In - this case, the device should still describe the whole IP core with - a single node and add a child node for each logical device. The - ranges property can be used to translate from parent IP-core to the - registers of each device. In addition, the parent node should be - compatible with the bus type 'xlnx,compound', and should contain - #address-cells and #size-cells, as with any other bus. (Note: this - makes the assumption that both logical devices have the same bus - binding. If this is not true, then separate nodes should be used - for each logical device). The 'cell-index' property can be used to - enumerate logical devices within an IP core. For example, the - following is the system.mhs entry for the dual ps2 controller found - on the ml403 reference design. - - BEGIN opb_ps2_dual_ref - PARAMETER INSTANCE = opb_ps2_dual_ref_0 - PARAMETER HW_VER = 1.00.a - PARAMETER C_BASEADDR = 0xA9000000 - PARAMETER C_HIGHADDR = 0xA9001FFF - BUS_INTERFACE SOPB = opb_v20_0 - PORT Sys_Intr1 = ps2_1_intr - PORT Sys_Intr2 = ps2_2_intr - PORT Clkin1 = ps2_clk_rx_1 - PORT Clkin2 = ps2_clk_rx_2 - PORT Clkpd1 = ps2_clk_tx_1 - PORT Clkpd2 = ps2_clk_tx_2 - PORT Rx1 = ps2_d_rx_1 - PORT Rx2 = ps2_d_rx_2 - PORT Txpd1 = ps2_d_tx_1 - PORT Txpd2 = ps2_d_tx_2 - END - - It would result in the following device tree nodes: - - opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,compound"; - ranges = <0 a9000000 2000>; - // If this device had extra parameters, then they would - // go here. - ps2@0 { - compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; - reg = <0 40>; - interrupt-parent = <&opb_intc_0>; - interrupts = <3 0>; - cell-index = <0>; - }; - ps2@1000 { - compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; - reg = <1000 40>; - interrupt-parent = <&opb_intc_0>; - interrupts = <3 0>; - cell-index = <0>; - }; - }; - - Also, the system.mhs file defines bus attachments from the processor - to the devices. The device tree structure should reflect the bus - attachments. Again an example; this system.mhs fragment: - - BEGIN ppc405_virtex4 - PARAMETER INSTANCE = ppc405_0 - PARAMETER HW_VER = 1.01.a - BUS_INTERFACE DPLB = plb_v34_0 - BUS_INTERFACE IPLB = plb_v34_0 - END - - BEGIN opb_intc - PARAMETER INSTANCE = opb_intc_0 - PARAMETER HW_VER = 1.00.c - PARAMETER C_BASEADDR = 0xD1000FC0 - PARAMETER C_HIGHADDR = 0xD1000FDF - BUS_INTERFACE SOPB = opb_v20_0 - END - - BEGIN opb_uart16550 - PARAMETER INSTANCE = opb_uart16550_0 - PARAMETER HW_VER = 1.00.d - PARAMETER C_BASEADDR = 0xa0000000 - PARAMETER C_HIGHADDR = 0xa0001FFF - BUS_INTERFACE SOPB = opb_v20_0 - END - - BEGIN plb_v34 - PARAMETER INSTANCE = plb_v34_0 - PARAMETER HW_VER = 1.02.a - END - - BEGIN plb_bram_if_cntlr - PARAMETER INSTANCE = plb_bram_if_cntlr_0 - PARAMETER HW_VER = 1.00.b - PARAMETER C_BASEADDR = 0xFFFF0000 - PARAMETER C_HIGHADDR = 0xFFFFFFFF - BUS_INTERFACE SPLB = plb_v34_0 - END - - BEGIN plb2opb_bridge - PARAMETER INSTANCE = plb2opb_bridge_0 - PARAMETER HW_VER = 1.01.a - PARAMETER C_RNG0_BASEADDR = 0x20000000 - PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF - PARAMETER C_RNG1_BASEADDR = 0x60000000 - PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF - PARAMETER C_RNG2_BASEADDR = 0x80000000 - PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF - PARAMETER C_RNG3_BASEADDR = 0xC0000000 - PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF - BUS_INTERFACE SPLB = plb_v34_0 - BUS_INTERFACE MOPB = opb_v20_0 - END - - Gives this device tree (some properties removed for clarity): - - plb@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,plb-v34-1.02.a"; - device_type = "ibm,plb"; - ranges; // 1:1 translation - - plb_bram_if_cntrl_0: bram@ffff0000 { - reg = ; - } - - opb@20000000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <20000000 20000000 20000000 - 60000000 60000000 20000000 - 80000000 80000000 40000000 - c0000000 c0000000 20000000>; - - opb_uart16550_0: serial@a0000000 { - reg = ; - }; - - opb_intc_0: interrupt-controller@d1000fc0 { - reg = ; - }; - }; - }; - That covers the general approach to binding xilinx IP cores into the device tree. The following are bindings for specific devices: diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h new file mode 100644 index 000000000000..f19cf8ccbdd2 --- /dev/null +++ b/include/dt-bindings/clock/agilex-clock.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019, Intel Corporation + */ + +#ifndef __AGILEX_CLOCK_H +#define __AGILEX_CLOCK_H + +/* fixed rate clocks */ +#define AGILEX_OSC1 0 +#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX_CB_INTOSC_LS_CLK 2 +#define AGILEX_L4_SYS_FREE_CLK 3 +#define AGILEX_F2S_FREE_CLK 4 + +/* PLL clocks */ +#define AGILEX_MAIN_PLL_CLK 5 +#define AGILEX_MAIN_PLL_C0_CLK 6 +#define AGILEX_MAIN_PLL_C1_CLK 7 +#define AGILEX_MAIN_PLL_C2_CLK 8 +#define AGILEX_MAIN_PLL_C3_CLK 9 +#define AGILEX_PERIPH_PLL_CLK 10 +#define AGILEX_PERIPH_PLL_C0_CLK 11 +#define AGILEX_PERIPH_PLL_C1_CLK 12 +#define AGILEX_PERIPH_PLL_C2_CLK 13 +#define AGILEX_PERIPH_PLL_C3_CLK 14 +#define AGILEX_MPU_FREE_CLK 15 +#define AGILEX_MPU_CCU_CLK 16 +#define AGILEX_BOOT_CLK 17 + +/* fixed factor clocks */ +#define AGILEX_L3_MAIN_FREE_CLK 18 +#define AGILEX_NOC_FREE_CLK 19 +#define AGILEX_S2F_USR0_CLK 20 +#define AGILEX_NOC_CLK 21 +#define AGILEX_EMAC_A_FREE_CLK 22 +#define AGILEX_EMAC_B_FREE_CLK 23 +#define AGILEX_EMAC_PTP_FREE_CLK 24 +#define AGILEX_GPIO_DB_FREE_CLK 25 +#define AGILEX_SDMMC_FREE_CLK 26 +#define AGILEX_S2F_USER0_FREE_CLK 27 +#define AGILEX_S2F_USER1_FREE_CLK 28 +#define AGILEX_PSI_REF_FREE_CLK 29 + +/* Gate clocks */ +#define AGILEX_MPU_CLK 30 +#define AGILEX_MPU_L2RAM_CLK 31 +#define AGILEX_MPU_PERIPH_CLK 32 +#define AGILEX_L4_MAIN_CLK 33 +#define AGILEX_L4_MP_CLK 34 +#define AGILEX_L4_SP_CLK 35 +#define AGILEX_CS_AT_CLK 36 +#define AGILEX_CS_TRACE_CLK 37 +#define AGILEX_CS_PDBG_CLK 38 +#define AGILEX_CS_TIMER_CLK 39 +#define AGILEX_S2F_USER0_CLK 40 +#define AGILEX_EMAC0_CLK 41 +#define AGILEX_EMAC1_CLK 43 +#define AGILEX_EMAC2_CLK 44 +#define AGILEX_EMAC_PTP_CLK 45 +#define AGILEX_GPIO_DB_CLK 46 +#define AGILEX_NAND_CLK 47 +#define AGILEX_PSI_REF_CLK 48 +#define AGILEX_S2F_USER1_CLK 49 +#define AGILEX_SDMMC_CLK 50 +#define AGILEX_SPI_M_CLK 51 +#define AGILEX_USB_CLK 52 +#define AGILEX_NUM_CLKS 53 + +#endif /* __AGILEX_CLOCK_H */ diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index 38b5554153c8..eba17106608b 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -12,6 +12,7 @@ #define PMC_TYPE_SYSTEM 1 #define PMC_TYPE_PERIPHERAL 2 #define PMC_TYPE_GCK 3 +#define PMC_TYPE_PROGRAMMABLE 4 #define PMC_SLOW 0 #define PMC_MCK 1 @@ -20,6 +21,9 @@ #define PMC_MCK2 4 #define PMC_I2S0_MUX 5 #define PMC_I2S1_MUX 6 +#define PMC_PLLACK 7 +#define PMC_PLLBCK 8 +#define PMC_AUDIOPLLCK 9 #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ diff --git a/include/dt-bindings/clock/bt1-ccu.h b/include/dt-bindings/clock/bt1-ccu.h new file mode 100644 index 000000000000..5f166d27a00a --- /dev/null +++ b/include/dt-bindings/clock/bt1-ccu.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC + * + * Baikal-T1 CCU clock indices + */ +#ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H +#define __DT_BINDINGS_CLOCK_BT1_CCU_H + +#define CCU_CPU_PLL 0 +#define CCU_SATA_PLL 1 +#define CCU_DDR_PLL 2 +#define CCU_PCIE_PLL 3 +#define CCU_ETH_PLL 4 + +#define CCU_AXI_MAIN_CLK 0 +#define CCU_AXI_DDR_CLK 1 +#define CCU_AXI_SATA_CLK 2 +#define CCU_AXI_GMAC0_CLK 3 +#define CCU_AXI_GMAC1_CLK 4 +#define CCU_AXI_XGMAC_CLK 5 +#define CCU_AXI_PCIE_M_CLK 6 +#define CCU_AXI_PCIE_S_CLK 7 +#define CCU_AXI_USB_CLK 8 +#define CCU_AXI_HWA_CLK 9 +#define CCU_AXI_SRAM_CLK 10 + +#define CCU_SYS_SATA_REF_CLK 0 +#define CCU_SYS_APB_CLK 1 +#define CCU_SYS_GMAC0_TX_CLK 2 +#define CCU_SYS_GMAC0_PTP_CLK 3 +#define CCU_SYS_GMAC1_TX_CLK 4 +#define CCU_SYS_GMAC1_PTP_CLK 5 +#define CCU_SYS_XGMAC_REF_CLK 6 +#define CCU_SYS_XGMAC_PTP_CLK 7 +#define CCU_SYS_USB_CLK 8 +#define CCU_SYS_PVT_CLK 9 +#define CCU_SYS_HWA_CLK 10 +#define CCU_SYS_UART_CLK 11 +#define CCU_SYS_I2C1_CLK 12 +#define CCU_SYS_I2C2_CLK 13 +#define CCU_SYS_GPIO_CLK 14 +#define CCU_SYS_TIMER0_CLK 15 +#define CCU_SYS_TIMER1_CLK 16 +#define CCU_SYS_TIMER2_CLK 17 +#define CCU_SYS_WDT_CLK 18 + +#endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */ diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h index 38145bdcd975..b58370d146e2 100644 --- a/include/dt-bindings/clock/imx7ulp-clock.h +++ b/include/dt-bindings/clock/imx7ulp-clock.h @@ -58,7 +58,10 @@ #define IMX7ULP_CLK_HSRUN_SYS_SEL 44 #define IMX7ULP_CLK_HSRUN_CORE_DIV 45 -#define IMX7ULP_CLK_SCG1_END 46 +#define IMX7ULP_CLK_CORE 46 +#define IMX7ULP_CLK_HSRUN_CORE 47 + +#define IMX7ULP_CLK_SCG1_END 48 /* PCC2 */ #define IMX7ULP_CLK_DMA1 0 diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 47ab082238b4..7a23f289b27f 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -296,6 +296,94 @@ #define IMX8MP_CLK_ARM 287 #define IMX8MP_CLK_A53_CORE 288 -#define IMX8MP_CLK_END 289 +#define IMX8MP_SYS_PLL1_40M_CG 289 +#define IMX8MP_SYS_PLL1_80M_CG 290 +#define IMX8MP_SYS_PLL1_100M_CG 291 +#define IMX8MP_SYS_PLL1_133M_CG 292 +#define IMX8MP_SYS_PLL1_160M_CG 293 +#define IMX8MP_SYS_PLL1_200M_CG 294 +#define IMX8MP_SYS_PLL1_266M_CG 295 +#define IMX8MP_SYS_PLL1_400M_CG 296 +#define IMX8MP_SYS_PLL2_50M_CG 297 +#define IMX8MP_SYS_PLL2_100M_CG 298 +#define IMX8MP_SYS_PLL2_125M_CG 299 +#define IMX8MP_SYS_PLL2_166M_CG 300 +#define IMX8MP_SYS_PLL2_200M_CG 301 +#define IMX8MP_SYS_PLL2_250M_CG 302 +#define IMX8MP_SYS_PLL2_333M_CG 303 +#define IMX8MP_SYS_PLL2_500M_CG 304 + +#define IMX8MP_CLK_M7_CORE 305 +#define IMX8MP_CLK_ML_CORE 306 +#define IMX8MP_CLK_GPU3D_CORE 307 +#define IMX8MP_CLK_GPU3D_SHADER_CORE 308 +#define IMX8MP_CLK_GPU2D_CORE 309 +#define IMX8MP_CLK_AUDIO_AXI 310 +#define IMX8MP_CLK_HSIO_AXI 311 +#define IMX8MP_CLK_MEDIA_ISP 312 + +#define IMX8MP_CLK_END 313 + +#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 +#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 +#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 +#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 +#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 +#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 +#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 +#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 +#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 +#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 +#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 +#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 +#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 +#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 +#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 +#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 +#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 +#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 +#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 +#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 +#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 +#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 +#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 +#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 +#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 +#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 +#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 +#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 +#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 +#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 +#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 +#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 +#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 +#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 +#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 + +#define IMX8MP_CLK_AUDIOMIX_END 59 #endif diff --git a/include/dt-bindings/clock/intel,lgm-clk.h b/include/dt-bindings/clock/intel,lgm-clk.h new file mode 100644 index 000000000000..92f5be6490bb --- /dev/null +++ b/include/dt-bindings/clock/intel,lgm-clk.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2020 Intel Corporation. + * Lei Chuanhua + * Zhu Yixin + */ +#ifndef __INTEL_LGM_CLK_H +#define __INTEL_LGM_CLK_H + +/* PLL clocks */ +#define LGM_CLK_OSC 1 +#define LGM_CLK_PLLPP 2 +#define LGM_CLK_PLL2 3 +#define LGM_CLK_PLL0CZ 4 +#define LGM_CLK_PLL0B 5 +#define LGM_CLK_PLL1 6 +#define LGM_CLK_LJPLL3 7 +#define LGM_CLK_LJPLL4 8 +#define LGM_CLK_PLL0CM0 9 +#define LGM_CLK_PLL0CM1 10 + +/* clocks from PLLs */ + +/* ROPLL clocks */ +#define LGM_CLK_PP_HW 15 +#define LGM_CLK_PP_UC 16 +#define LGM_CLK_PP_FXD 17 +#define LGM_CLK_PP_TBM 18 + +/* PLL2 clocks */ +#define LGM_CLK_DDR 20 + +/* PLL0CZ */ +#define LGM_CLK_CM 25 +#define LGM_CLK_IC 26 +#define LGM_CLK_SDXC3 27 + +/* PLL0B */ +#define LGM_CLK_NGI 30 +#define LGM_CLK_NOC4 31 +#define LGM_CLK_SW 32 +#define LGM_CLK_QSPI 33 +#define LGM_CLK_CQEM LGM_CLK_SW +#define LGM_CLK_EMMC5 LGM_CLK_NOC4 + +/* PLL1 */ +#define LGM_CLK_CT 35 +#define LGM_CLK_DSP 36 +#define LGM_CLK_VIF 37 + +/* LJPLL3 */ +#define LGM_CLK_CML 40 +#define LGM_CLK_SERDES 41 +#define LGM_CLK_POOL 42 +#define LGM_CLK_PTP 43 + +/* LJPLL4 */ +#define LGM_CLK_PCIE 45 +#define LGM_CLK_SATA LGM_CLK_PCIE + +/* PLL0CM0 */ +#define LGM_CLK_CPU0 50 + +/* PLL0CM1 */ +#define LGM_CLK_CPU1 55 + +/* Miscellaneous clocks */ +#define LGM_CLK_EMMC4 60 +#define LGM_CLK_SDXC2 61 +#define LGM_CLK_EMMC 62 +#define LGM_CLK_SDXC 63 +#define LGM_CLK_SLIC 64 +#define LGM_CLK_DCL 65 +#define LGM_CLK_DOCSIS 66 +#define LGM_CLK_PCM 67 +#define LGM_CLK_DDR_PHY 68 +#define LGM_CLK_PONDEF 69 +#define LGM_CLK_PL25M 70 +#define LGM_CLK_PL10M 71 +#define LGM_CLK_PL1544K 72 +#define LGM_CLK_PL2048K 73 +#define LGM_CLK_PL8K 74 +#define LGM_CLK_PON_NTR 75 +#define LGM_CLK_SYNC0 76 +#define LGM_CLK_SYNC1 77 +#define LGM_CLK_PROGDIV 78 +#define LGM_CLK_OD0 79 +#define LGM_CLK_OD1 80 +#define LGM_CLK_CBPHY0 81 +#define LGM_CLK_CBPHY1 82 +#define LGM_CLK_CBPHY2 83 +#define LGM_CLK_CBPHY3 84 + +/* Gate clocks */ +/* Gate CLK0 */ +#define LGM_GCLK_C55 100 +#define LGM_GCLK_QSPI 101 +#define LGM_GCLK_EIP197 102 +#define LGM_GCLK_VAULT 103 +#define LGM_GCLK_TOE 104 +#define LGM_GCLK_SDXC 105 +#define LGM_GCLK_EMMC 106 +#define LGM_GCLK_SPI_DBG 107 +#define LGM_GCLK_DMA3 108 + +/* Gate CLK1 */ +#define LGM_GCLK_DMA0 120 +#define LGM_GCLK_LEDC0 121 +#define LGM_GCLK_LEDC1 122 +#define LGM_GCLK_I2S0 123 +#define LGM_GCLK_I2S1 124 +#define LGM_GCLK_EBU 125 +#define LGM_GCLK_PWM 126 +#define LGM_GCLK_I2C0 127 +#define LGM_GCLK_I2C1 128 +#define LGM_GCLK_I2C2 129 +#define LGM_GCLK_I2C3 130 +#define LGM_GCLK_SSC0 131 +#define LGM_GCLK_SSC1 132 +#define LGM_GCLK_SSC2 133 +#define LGM_GCLK_SSC3 134 +#define LGM_GCLK_GPTC0 135 +#define LGM_GCLK_GPTC1 136 +#define LGM_GCLK_GPTC2 137 +#define LGM_GCLK_GPTC3 138 +#define LGM_GCLK_ASC0 139 +#define LGM_GCLK_ASC1 140 +#define LGM_GCLK_ASC2 141 +#define LGM_GCLK_ASC3 142 +#define LGM_GCLK_PCM0 143 +#define LGM_GCLK_PCM1 144 +#define LGM_GCLK_PCM2 145 + +/* Gate CLK2 */ +#define LGM_GCLK_PCIE10 150 +#define LGM_GCLK_PCIE11 151 +#define LGM_GCLK_PCIE30 152 +#define LGM_GCLK_PCIE31 153 +#define LGM_GCLK_PCIE20 154 +#define LGM_GCLK_PCIE21 155 +#define LGM_GCLK_PCIE40 156 +#define LGM_GCLK_PCIE41 157 +#define LGM_GCLK_XPCS0 158 +#define LGM_GCLK_XPCS1 159 +#define LGM_GCLK_XPCS2 160 +#define LGM_GCLK_XPCS3 161 +#define LGM_GCLK_SATA0 162 +#define LGM_GCLK_SATA1 163 +#define LGM_GCLK_SATA2 164 +#define LGM_GCLK_SATA3 165 + +/* Gate CLK3 */ +#define LGM_GCLK_ARCEM4 170 +#define LGM_GCLK_IDMAR1 171 +#define LGM_GCLK_IDMAT0 172 +#define LGM_GCLK_IDMAT1 173 +#define LGM_GCLK_IDMAT2 174 +#define LGM_GCLK_PPV4 175 +#define LGM_GCLK_GSWIPO 176 +#define LGM_GCLK_CQEM 177 +#define LGM_GCLK_XPCS5 178 +#define LGM_GCLK_USB1 179 +#define LGM_GCLK_USB2 180 + +#endif /* __INTEL_LGM_CLK_H */ diff --git a/include/dt-bindings/clock/marvell,mmp2-audio.h b/include/dt-bindings/clock/marvell,mmp2-audio.h new file mode 100644 index 000000000000..20664776f497 --- /dev/null +++ b/include/dt-bindings/clock/marvell,mmp2-audio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ +#ifndef __DT_BINDINGS_CLOCK_MARVELL_MMP2_AUDIO_H +#define __DT_BINDINGS_CLOCK_MARVELL_MMP2_AUDIO_H + +#define MMP2_CLK_AUDIO_SYSCLK 0 +#define MMP2_CLK_AUDIO_SSPA0 1 +#define MMP2_CLK_AUDIO_SSPA1 2 + +#define MMP2_CLK_AUDIO_NR_CLKS 3 +#endif diff --git a/include/dt-bindings/clock/marvell,mmp2.h b/include/dt-bindings/clock/marvell,mmp2.h index 06bb7fe4c62f..87f5ad5df72f 100644 --- a/include/dt-bindings/clock/marvell,mmp2.h +++ b/include/dt-bindings/clock/marvell,mmp2.h @@ -29,6 +29,8 @@ #define MMP3_CLK_PLL1_P 28 #define MMP3_CLK_PLL2_P 29 #define MMP3_CLK_PLL3 30 +#define MMP2_CLK_I2S0 31 +#define MMP2_CLK_I2S1 32 /* apb periphrals */ #define MMP2_CLK_TWSI0 60 @@ -87,6 +89,7 @@ #define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D #define MMP3_CLK_GPU_2D 125 #define MMP3_CLK_SDH4 126 +#define MMP2_CLK_AUDIO 127 #define MMP2_NR_CLKS 200 #endif diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index 68862aaf977e..4c5965ae1df4 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -107,6 +107,7 @@ #define CLKID_PERIPH 126 #define CLKID_AXI 128 #define CLKID_L2_DRAM 130 +#define CLKID_HDMI_SYS 174 #define CLKID_VPU 190 #define CLKID_VDEC_1 196 #define CLKID_VDEC_HCODEC 199 diff --git a/include/dt-bindings/clock/mt6765-clk.h b/include/dt-bindings/clock/mt6765-clk.h new file mode 100644 index 000000000000..eb97e568518e --- /dev/null +++ b/include/dt-bindings/clock/mt6765-clk.h @@ -0,0 +1,313 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_CLK_MT6765_H +#define _DT_BINDINGS_CLK_MT6765_H + +/* FIX Clks */ +#define CLK_TOP_CLK26M 0 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL_L 0 +#define CLK_APMIXED_ARMPLL 1 +#define CLK_APMIXED_CCIPLL 2 +#define CLK_APMIXED_MAINPLL 3 +#define CLK_APMIXED_MFGPLL 4 +#define CLK_APMIXED_MMPLL 5 +#define CLK_APMIXED_UNIV2PLL 6 +#define CLK_APMIXED_MSDCPLL 7 +#define CLK_APMIXED_APLL1 8 +#define CLK_APMIXED_MPLL 9 +#define CLK_APMIXED_ULPOSC1 10 +#define CLK_APMIXED_ULPOSC2 11 +#define CLK_APMIXED_SSUSB26M 12 +#define CLK_APMIXED_APPLL26M 13 +#define CLK_APMIXED_MIPIC0_26M 14 +#define CLK_APMIXED_MDPLLGP26M 15 +#define CLK_APMIXED_MMSYS_F26M 16 +#define CLK_APMIXED_UFS26M 17 +#define CLK_APMIXED_MIPIC1_26M 18 +#define CLK_APMIXED_MEMPLL26M 19 +#define CLK_APMIXED_CLKSQ_LVPLL_26M 20 +#define CLK_APMIXED_MIPID0_26M 21 +#define CLK_APMIXED_NR_CLK 22 + +/* TOPCKGEN */ +#define CLK_TOP_SYSPLL 0 +#define CLK_TOP_SYSPLL_D2 1 +#define CLK_TOP_SYSPLL1_D2 2 +#define CLK_TOP_SYSPLL1_D4 3 +#define CLK_TOP_SYSPLL1_D8 4 +#define CLK_TOP_SYSPLL1_D16 5 +#define CLK_TOP_SYSPLL_D3 6 +#define CLK_TOP_SYSPLL2_D2 7 +#define CLK_TOP_SYSPLL2_D4 8 +#define CLK_TOP_SYSPLL2_D8 9 +#define CLK_TOP_SYSPLL_D5 10 +#define CLK_TOP_SYSPLL3_D2 11 +#define CLK_TOP_SYSPLL3_D4 12 +#define CLK_TOP_SYSPLL_D7 13 +#define CLK_TOP_SYSPLL4_D2 14 +#define CLK_TOP_SYSPLL4_D4 15 +#define CLK_TOP_USB20_192M 16 +#define CLK_TOP_USB20_192M_D4 17 +#define CLK_TOP_USB20_192M_D8 18 +#define CLK_TOP_USB20_192M_D16 19 +#define CLK_TOP_USB20_192M_D32 20 +#define CLK_TOP_UNIVPLL 21 +#define CLK_TOP_UNIVPLL_D2 22 +#define CLK_TOP_UNIVPLL1_D2 23 +#define CLK_TOP_UNIVPLL1_D4 24 +#define CLK_TOP_UNIVPLL_D3 25 +#define CLK_TOP_UNIVPLL2_D2 26 +#define CLK_TOP_UNIVPLL2_D4 27 +#define CLK_TOP_UNIVPLL2_D8 28 +#define CLK_TOP_UNIVPLL2_D32 29 +#define CLK_TOP_UNIVPLL_D5 30 +#define CLK_TOP_UNIVPLL3_D2 31 +#define CLK_TOP_UNIVPLL3_D4 32 +#define CLK_TOP_MMPLL 33 +#define CLK_TOP_MMPLL_D2 34 +#define CLK_TOP_MPLL 35 +#define CLK_TOP_DA_MPLL_104M_DIV 36 +#define CLK_TOP_DA_MPLL_52M_DIV 37 +#define CLK_TOP_MFGPLL 38 +#define CLK_TOP_MSDCPLL 39 +#define CLK_TOP_MSDCPLL_D2 40 +#define CLK_TOP_APLL1 41 +#define CLK_TOP_APLL1_D2 42 +#define CLK_TOP_APLL1_D4 43 +#define CLK_TOP_APLL1_D8 44 +#define CLK_TOP_ULPOSC1 45 +#define CLK_TOP_ULPOSC1_D2 46 +#define CLK_TOP_ULPOSC1_D4 47 +#define CLK_TOP_ULPOSC1_D8 48 +#define CLK_TOP_ULPOSC1_D16 49 +#define CLK_TOP_ULPOSC1_D32 50 +#define CLK_TOP_DMPLL 51 +#define CLK_TOP_F_FRTC 52 +#define CLK_TOP_F_F26M 53 +#define CLK_TOP_AXI 54 +#define CLK_TOP_MM 55 +#define CLK_TOP_SCP 56 +#define CLK_TOP_MFG 57 +#define CLK_TOP_F_FUART 58 +#define CLK_TOP_SPI 59 +#define CLK_TOP_MSDC50_0 60 +#define CLK_TOP_MSDC30_1 61 +#define CLK_TOP_AUDIO 62 +#define CLK_TOP_AUD_1 63 +#define CLK_TOP_AUD_ENGEN1 64 +#define CLK_TOP_F_FDISP_PWM 65 +#define CLK_TOP_SSPM 66 +#define CLK_TOP_DXCC 67 +#define CLK_TOP_I2C 68 +#define CLK_TOP_F_FPWM 69 +#define CLK_TOP_F_FSENINF 70 +#define CLK_TOP_AES_FDE 71 +#define CLK_TOP_F_BIST2FPC 72 +#define CLK_TOP_ARMPLL_DIVIDER_PLL0 73 +#define CLK_TOP_ARMPLL_DIVIDER_PLL1 74 +#define CLK_TOP_ARMPLL_DIVIDER_PLL2 75 +#define CLK_TOP_DA_USB20_48M_DIV 76 +#define CLK_TOP_DA_UNIV_48M_DIV 77 +#define CLK_TOP_APLL12_DIV0 78 +#define CLK_TOP_APLL12_DIV1 79 +#define CLK_TOP_APLL12_DIV2 80 +#define CLK_TOP_APLL12_DIV3 81 +#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 82 +#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 83 +#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 84 +#define CLK_TOP_FMEM_OCC_DRC_EN 85 +#define CLK_TOP_USB20_48M_EN 86 +#define CLK_TOP_UNIVPLL_48M_EN 87 +#define CLK_TOP_MPLL_104M_EN 88 +#define CLK_TOP_MPLL_52M_EN 89 +#define CLK_TOP_F_UFS_MP_SAP_CFG_EN 90 +#define CLK_TOP_F_BIST2FPC_EN 91 +#define CLK_TOP_MD_32K 92 +#define CLK_TOP_MD_26M 93 +#define CLK_TOP_MD2_32K 94 +#define CLK_TOP_MD2_26M 95 +#define CLK_TOP_AXI_SEL 96 +#define CLK_TOP_MEM_SEL 97 +#define CLK_TOP_MM_SEL 98 +#define CLK_TOP_SCP_SEL 99 +#define CLK_TOP_MFG_SEL 100 +#define CLK_TOP_ATB_SEL 101 +#define CLK_TOP_CAMTG_SEL 102 +#define CLK_TOP_CAMTG1_SEL 103 +#define CLK_TOP_CAMTG2_SEL 104 +#define CLK_TOP_CAMTG3_SEL 105 +#define CLK_TOP_UART_SEL 106 +#define CLK_TOP_SPI_SEL 107 +#define CLK_TOP_MSDC50_0_HCLK_SEL 108 +#define CLK_TOP_MSDC50_0_SEL 109 +#define CLK_TOP_MSDC30_1_SEL 110 +#define CLK_TOP_AUDIO_SEL 111 +#define CLK_TOP_AUD_INTBUS_SEL 112 +#define CLK_TOP_AUD_1_SEL 113 +#define CLK_TOP_AUD_ENGEN1_SEL 114 +#define CLK_TOP_DISP_PWM_SEL 115 +#define CLK_TOP_SSPM_SEL 116 +#define CLK_TOP_DXCC_SEL 117 +#define CLK_TOP_USB_TOP_SEL 118 +#define CLK_TOP_SPM_SEL 119 +#define CLK_TOP_I2C_SEL 120 +#define CLK_TOP_PWM_SEL 121 +#define CLK_TOP_SENINF_SEL 122 +#define CLK_TOP_AES_FDE_SEL 123 +#define CLK_TOP_PWRAP_ULPOSC_SEL 124 +#define CLK_TOP_CAMTM_SEL 125 +#define CLK_TOP_NR_CLK 126 + +/* INFRACFG */ +#define CLK_IFR_ICUSB 0 +#define CLK_IFR_GCE 1 +#define CLK_IFR_THERM 2 +#define CLK_IFR_I2C_AP 3 +#define CLK_IFR_I2C_CCU 4 +#define CLK_IFR_I2C_SSPM 5 +#define CLK_IFR_I2C_RSV 6 +#define CLK_IFR_PWM_HCLK 7 +#define CLK_IFR_PWM1 8 +#define CLK_IFR_PWM2 9 +#define CLK_IFR_PWM3 10 +#define CLK_IFR_PWM4 11 +#define CLK_IFR_PWM5 12 +#define CLK_IFR_PWM 13 +#define CLK_IFR_UART0 14 +#define CLK_IFR_UART1 15 +#define CLK_IFR_GCE_26M 16 +#define CLK_IFR_CQ_DMA_FPC 17 +#define CLK_IFR_BTIF 18 +#define CLK_IFR_SPI0 19 +#define CLK_IFR_MSDC0 20 +#define CLK_IFR_MSDC1 21 +#define CLK_IFR_TRNG 22 +#define CLK_IFR_AUXADC 23 +#define CLK_IFR_CCIF1_AP 24 +#define CLK_IFR_CCIF1_MD 25 +#define CLK_IFR_AUXADC_MD 26 +#define CLK_IFR_AP_DMA 27 +#define CLK_IFR_DEVICE_APC 28 +#define CLK_IFR_CCIF_AP 29 +#define CLK_IFR_AUDIO 30 +#define CLK_IFR_CCIF_MD 31 +#define CLK_IFR_RG_PWM_FBCLK6 32 +#define CLK_IFR_DISP_PWM 33 +#define CLK_IFR_CLDMA_BCLK 34 +#define CLK_IFR_AUDIO_26M_BCLK 35 +#define CLK_IFR_SPI1 36 +#define CLK_IFR_I2C4 37 +#define CLK_IFR_SPI2 38 +#define CLK_IFR_SPI3 39 +#define CLK_IFR_I2C5 40 +#define CLK_IFR_I2C5_ARBITER 41 +#define CLK_IFR_I2C5_IMM 42 +#define CLK_IFR_I2C1_ARBITER 43 +#define CLK_IFR_I2C1_IMM 44 +#define CLK_IFR_I2C2_ARBITER 45 +#define CLK_IFR_I2C2_IMM 46 +#define CLK_IFR_SPI4 47 +#define CLK_IFR_SPI5 48 +#define CLK_IFR_CQ_DMA 49 +#define CLK_IFR_FAES_FDE 50 +#define CLK_IFR_MSDC0_SELF 51 +#define CLK_IFR_MSDC1_SELF 52 +#define CLK_IFR_I2C6 53 +#define CLK_IFR_AP_MSDC0 54 +#define CLK_IFR_MD_MSDC0 55 +#define CLK_IFR_MSDC0_SRC 56 +#define CLK_IFR_MSDC1_SRC 57 +#define CLK_IFR_AES_TOP0_BCLK 58 +#define CLK_IFR_MCU_PM_BCLK 59 +#define CLK_IFR_CCIF2_AP 60 +#define CLK_IFR_CCIF2_MD 61 +#define CLK_IFR_CCIF3_AP 62 +#define CLK_IFR_CCIF3_MD 63 +#define CLK_IFR_NR_CLK 64 + +/* AUDIO */ +#define CLK_AUDIO_AFE 0 +#define CLK_AUDIO_22M 1 +#define CLK_AUDIO_APLL_TUNER 2 +#define CLK_AUDIO_ADC 3 +#define CLK_AUDIO_DAC 4 +#define CLK_AUDIO_DAC_PREDIS 5 +#define CLK_AUDIO_TML 6 +#define CLK_AUDIO_I2S1_BCLK 7 +#define CLK_AUDIO_I2S2_BCLK 8 +#define CLK_AUDIO_I2S3_BCLK 9 +#define CLK_AUDIO_I2S4_BCLK 10 +#define CLK_AUDIO_NR_CLK 11 + +/* MIPI_RX_ANA_CSI0A */ + +#define CLK_MIPI0A_CSR_CSI_EN_0A 0 +#define CLK_MIPI0A_NR_CLK 1 + +/* MMSYS_CONFIG */ + +#define CLK_MM_MDP_RDMA0 0 +#define CLK_MM_MDP_CCORR0 1 +#define CLK_MM_MDP_RSZ0 2 +#define CLK_MM_MDP_RSZ1 3 +#define CLK_MM_MDP_TDSHP0 4 +#define CLK_MM_MDP_WROT0 5 +#define CLK_MM_MDP_WDMA0 6 +#define CLK_MM_DISP_OVL0 7 +#define CLK_MM_DISP_OVL0_2L 8 +#define CLK_MM_DISP_RSZ0 9 +#define CLK_MM_DISP_RDMA0 10 +#define CLK_MM_DISP_WDMA0 11 +#define CLK_MM_DISP_COLOR0 12 +#define CLK_MM_DISP_CCORR0 13 +#define CLK_MM_DISP_AAL0 14 +#define CLK_MM_DISP_GAMMA0 15 +#define CLK_MM_DISP_DITHER0 16 +#define CLK_MM_DSI0 17 +#define CLK_MM_FAKE_ENG 18 +#define CLK_MM_SMI_COMMON 19 +#define CLK_MM_SMI_LARB0 20 +#define CLK_MM_SMI_COMM0 21 +#define CLK_MM_SMI_COMM1 22 +#define CLK_MM_CAM_MDP 23 +#define CLK_MM_SMI_IMG 24 +#define CLK_MM_SMI_CAM 25 +#define CLK_MM_IMG_DL_RELAY 26 +#define CLK_MM_IMG_DL_ASYNC_TOP 27 +#define CLK_MM_DIG_DSI 28 +#define CLK_MM_F26M_HRTWT 29 +#define CLK_MM_NR_CLK 30 + +/* IMGSYS */ + +#define CLK_IMG_LARB2 0 +#define CLK_IMG_DIP 1 +#define CLK_IMG_FDVT 2 +#define CLK_IMG_DPE 3 +#define CLK_IMG_RSC 4 +#define CLK_IMG_NR_CLK 5 + +/* VENCSYS */ + +#define CLK_VENC_SET0_LARB 0 +#define CLK_VENC_SET1_VENC 1 +#define CLK_VENC_SET2_JPGENC 2 +#define CLK_VENC_SET3_VDEC 3 +#define CLK_VENC_NR_CLK 4 + +/* CAMSYS */ + +#define CLK_CAM_LARB3 0 +#define CLK_CAM_DFP_VAD 1 +#define CLK_CAM 2 +#define CLK_CAMTG 3 +#define CLK_CAM_SENINF 4 +#define CLK_CAMSV0 5 +#define CLK_CAMSV1 6 +#define CLK_CAMSV2 7 +#define CLK_CAM_CCU 8 +#define CLK_CAM_NR_CLK 9 + +#endif /* _DT_BINDINGS_CLK_MT6765_H */ diff --git a/include/dt-bindings/clock/qcom,gcc-msm8939.h b/include/dt-bindings/clock/qcom,gcc-msm8939.h new file mode 100644 index 000000000000..0634467c4ce5 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8939.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8939_H +#define _DT_BINDINGS_CLK_MSM_GCC_8939_H + +#define GPLL0 0 +#define GPLL0_VOTE 1 +#define BIMC_PLL 2 +#define BIMC_PLL_VOTE 3 +#define GPLL1 4 +#define GPLL1_VOTE 5 +#define GPLL2 6 +#define GPLL2_VOTE 7 +#define PCNOC_BFDCD_CLK_SRC 8 +#define SYSTEM_NOC_BFDCD_CLK_SRC 9 +#define CAMSS_AHB_CLK_SRC 10 +#define APSS_AHB_CLK_SRC 11 +#define CSI0_CLK_SRC 12 +#define CSI1_CLK_SRC 13 +#define GFX3D_CLK_SRC 14 +#define VFE0_CLK_SRC 15 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 16 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 17 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 18 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 19 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 20 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 21 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 22 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 23 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 24 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 25 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 26 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 27 +#define BLSP1_UART1_APPS_CLK_SRC 28 +#define BLSP1_UART2_APPS_CLK_SRC 29 +#define CCI_CLK_SRC 30 +#define CAMSS_GP0_CLK_SRC 31 +#define CAMSS_GP1_CLK_SRC 32 +#define JPEG0_CLK_SRC 33 +#define MCLK0_CLK_SRC 34 +#define MCLK1_CLK_SRC 35 +#define CSI0PHYTIMER_CLK_SRC 36 +#define CSI1PHYTIMER_CLK_SRC 37 +#define CPP_CLK_SRC 38 +#define CRYPTO_CLK_SRC 39 +#define GP1_CLK_SRC 40 +#define GP2_CLK_SRC 41 +#define GP3_CLK_SRC 42 +#define BYTE0_CLK_SRC 43 +#define ESC0_CLK_SRC 44 +#define MDP_CLK_SRC 45 +#define PCLK0_CLK_SRC 46 +#define VSYNC_CLK_SRC 47 +#define PDM2_CLK_SRC 48 +#define SDCC1_APPS_CLK_SRC 49 +#define SDCC2_APPS_CLK_SRC 50 +#define APSS_TCU_CLK_SRC 51 +#define USB_HS_SYSTEM_CLK_SRC 52 +#define VCODEC0_CLK_SRC 53 +#define GCC_BLSP1_AHB_CLK 54 +#define GCC_BLSP1_SLEEP_CLK 55 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 56 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 57 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 58 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 59 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 60 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 61 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 62 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 63 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 64 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 65 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 66 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 67 +#define GCC_BLSP1_UART1_APPS_CLK 68 +#define GCC_BLSP1_UART2_APPS_CLK 69 +#define GCC_BOOT_ROM_AHB_CLK 70 +#define GCC_CAMSS_CCI_AHB_CLK 71 +#define GCC_CAMSS_CCI_CLK 72 +#define GCC_CAMSS_CSI0_AHB_CLK 73 +#define GCC_CAMSS_CSI0_CLK 74 +#define GCC_CAMSS_CSI0PHY_CLK 75 +#define GCC_CAMSS_CSI0PIX_CLK 76 +#define GCC_CAMSS_CSI0RDI_CLK 77 +#define GCC_CAMSS_CSI1_AHB_CLK 78 +#define GCC_CAMSS_CSI1_CLK 79 +#define GCC_CAMSS_CSI1PHY_CLK 80 +#define GCC_CAMSS_CSI1PIX_CLK 81 +#define GCC_CAMSS_CSI1RDI_CLK 82 +#define GCC_CAMSS_CSI_VFE0_CLK 83 +#define GCC_CAMSS_GP0_CLK 84 +#define GCC_CAMSS_GP1_CLK 85 +#define GCC_CAMSS_ISPIF_AHB_CLK 86 +#define GCC_CAMSS_JPEG0_CLK 87 +#define GCC_CAMSS_JPEG_AHB_CLK 88 +#define GCC_CAMSS_JPEG_AXI_CLK 89 +#define GCC_CAMSS_MCLK0_CLK 90 +#define GCC_CAMSS_MCLK1_CLK 91 +#define GCC_CAMSS_MICRO_AHB_CLK 92 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 93 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 94 +#define GCC_CAMSS_AHB_CLK 95 +#define GCC_CAMSS_TOP_AHB_CLK 96 +#define GCC_CAMSS_CPP_AHB_CLK 97 +#define GCC_CAMSS_CPP_CLK 98 +#define GCC_CAMSS_VFE0_CLK 99 +#define GCC_CAMSS_VFE_AHB_CLK 100 +#define GCC_CAMSS_VFE_AXI_CLK 101 +#define GCC_CRYPTO_AHB_CLK 102 +#define GCC_CRYPTO_AXI_CLK 103 +#define GCC_CRYPTO_CLK 104 +#define GCC_OXILI_GMEM_CLK 105 +#define GCC_GP1_CLK 106 +#define GCC_GP2_CLK 107 +#define GCC_GP3_CLK 108 +#define GCC_MDSS_AHB_CLK 109 +#define GCC_MDSS_AXI_CLK 110 +#define GCC_MDSS_BYTE0_CLK 111 +#define GCC_MDSS_ESC0_CLK 112 +#define GCC_MDSS_MDP_CLK 113 +#define GCC_MDSS_PCLK0_CLK 114 +#define GCC_MDSS_VSYNC_CLK 115 +#define GCC_MSS_CFG_AHB_CLK 116 +#define GCC_OXILI_AHB_CLK 117 +#define GCC_OXILI_GFX3D_CLK 118 +#define GCC_PDM2_CLK 119 +#define GCC_PDM_AHB_CLK 120 +#define GCC_PRNG_AHB_CLK 121 +#define GCC_SDCC1_AHB_CLK 122 +#define GCC_SDCC1_APPS_CLK 123 +#define GCC_SDCC2_AHB_CLK 124 +#define GCC_SDCC2_APPS_CLK 125 +#define GCC_GTCU_AHB_CLK 126 +#define GCC_JPEG_TBU_CLK 127 +#define GCC_MDP_TBU_CLK 128 +#define GCC_SMMU_CFG_CLK 129 +#define GCC_VENUS_TBU_CLK 130 +#define GCC_VFE_TBU_CLK 131 +#define GCC_USB2A_PHY_SLEEP_CLK 132 +#define GCC_USB_HS_AHB_CLK 133 +#define GCC_USB_HS_SYSTEM_CLK 134 +#define GCC_VENUS0_AHB_CLK 135 +#define GCC_VENUS0_AXI_CLK 136 +#define GCC_VENUS0_VCODEC0_CLK 137 +#define BIMC_DDR_CLK_SRC 138 +#define GCC_APSS_TCU_CLK 139 +#define GCC_GFX_TCU_CLK 140 +#define BIMC_GPU_CLK_SRC 141 +#define GCC_BIMC_GFX_CLK 142 +#define GCC_BIMC_GPU_CLK 143 +#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144 +#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145 +#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146 +#define ULTAUDIO_XO_CLK_SRC 147 +#define ULTAUDIO_AHBFABRIC_CLK_SRC 148 +#define CODEC_DIGCODEC_CLK_SRC 149 +#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150 +#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151 +#define GCC_ULTAUDIO_AVSYNC_XO_CLK 152 +#define GCC_ULTAUDIO_STC_XO_CLK 153 +#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154 +#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155 +#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156 +#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157 +#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158 +#define GCC_CODEC_DIGCODEC_CLK 159 +#define GCC_MSS_Q6_BIMC_AXI_CLK 160 +#define GPLL3 161 +#define GPLL3_VOTE 162 +#define GPLL4 163 +#define GPLL4_VOTE 164 +#define GPLL5 165 +#define GPLL5_VOTE 166 +#define GPLL6 167 +#define GPLL6_VOTE 168 +#define BYTE1_CLK_SRC 169 +#define GCC_MDSS_BYTE1_CLK 170 +#define ESC1_CLK_SRC 171 +#define GCC_MDSS_ESC1_CLK 172 +#define PCLK1_CLK_SRC 173 +#define GCC_MDSS_PCLK1_CLK 174 +#define GCC_GFX_TBU_CLK 175 +#define GCC_CPP_TBU_CLK 176 +#define GCC_MDP_RT_TBU_CLK 177 +#define USB_FS_SYSTEM_CLK_SRC 178 +#define USB_FS_IC_CLK_SRC 179 +#define GCC_USB_FS_AHB_CLK 180 +#define GCC_USB_FS_IC_CLK 181 +#define GCC_USB_FS_SYSTEM_CLK 182 +#define GCC_VENUS0_CORE0_VCODEC0_CLK 183 +#define GCC_VENUS0_CORE1_VCODEC0_CLK 184 +#define GCC_OXILI_TIMER_CLK 185 + +/* Indexes for GDSCs */ +#define BIMC_GDSC 0 +#define VENUS_GDSC 1 +#define MDSS_GDSC 2 +#define JPEG_GDSC 3 +#define VFE_GDSC 4 +#define OXILI_GDSC 5 +#define VENUS_CORE0_GDSC 6 +#define VENUS_CORE1_GDSC 7 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 63e02dc32a0b..6a73a174f049 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -183,6 +183,7 @@ #define GCC_MSS_SNOC_AXI_CLK 174 #define GCC_MSS_MNOC_BIMC_AXI_CLK 175 #define GCC_BIMC_GFX_CLK 176 +#define UFS_UNIPRO_CORE_CLK_SRC 177 #define PCIE_0_GDSC 0 #define UFS_GDSC 1 diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h index 1258fd05db68..992b67b7e5e4 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc7180.h +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h @@ -137,6 +137,7 @@ #define GCC_MSS_NAV_AXI_CLK 127 #define GCC_MSS_Q6_MEMNOC_AXI_CLK 128 #define GCC_MSS_SNOC_AXI_CLK 129 +#define GCC_SEC_CTRL_CLK_SRC 130 /* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0 diff --git a/include/dt-bindings/clock/r8a7742-cpg-mssr.h b/include/dt-bindings/clock/r8a7742-cpg-mssr.h new file mode 100644 index 000000000000..e68191c24881 --- /dev/null +++ b/include/dt-bindings/clock/r8a7742-cpg-mssr.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ + +#include + +/* r8a7742 CPG Core Clocks */ +#define R8A7742_CLK_Z 0 +#define R8A7742_CLK_Z2 1 +#define R8A7742_CLK_ZG 2 +#define R8A7742_CLK_ZTR 3 +#define R8A7742_CLK_ZTRD2 4 +#define R8A7742_CLK_ZT 5 +#define R8A7742_CLK_ZX 6 +#define R8A7742_CLK_ZS 7 +#define R8A7742_CLK_HP 8 +#define R8A7742_CLK_B 9 +#define R8A7742_CLK_LB 10 +#define R8A7742_CLK_P 11 +#define R8A7742_CLK_CL 12 +#define R8A7742_CLK_M2 13 +#define R8A7742_CLK_ZB3 14 +#define R8A7742_CLK_ZB3D2 15 +#define R8A7742_CLK_DDR 16 +#define R8A7742_CLK_SDH 17 +#define R8A7742_CLK_SD0 18 +#define R8A7742_CLK_SD1 19 +#define R8A7742_CLK_SD2 20 +#define R8A7742_CLK_SD3 21 +#define R8A7742_CLK_MMC0 22 +#define R8A7742_CLK_MMC1 23 +#define R8A7742_CLK_MP 24 +#define R8A7742_CLK_QSPI 25 +#define R8A7742_CLK_CP 26 +#define R8A7742_CLK_RCAN 27 +#define R8A7742_CLK_R 28 +#define R8A7742_CLK_OSC 29 + +#endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/sprd,sc9863a-clk.h b/include/dt-bindings/clock/sprd,sc9863a-clk.h index 901ba59676c2..4e030421641f 100644 --- a/include/dt-bindings/clock/sprd,sc9863a-clk.h +++ b/include/dt-bindings/clock/sprd,sc9863a-clk.h @@ -308,6 +308,11 @@ #define CLK_MCPHY_CFG_EB 14 #define CLK_MM_GATE_NUM (CLK_MCPHY_CFG_EB + 1) +#define CLK_MIPI_CSI 0 +#define CLK_MIPI_CSI_S 1 +#define CLK_MIPI_CSI_M 2 +#define CLK_MM_CLK_NUM (CLK_MIPI_CSI_M + 1) + #define CLK_SIM0_EB 0 #define CLK_IIS0_EB 1 #define CLK_IIS1_EB 2 diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index df59aaf5bf34..a93426f008ac 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h @@ -272,10 +272,10 @@ #define TEGRA114_CLK_AUDIO3 242 #define TEGRA114_CLK_AUDIO4 243 #define TEGRA114_CLK_SPDIF 244 -#define TEGRA114_CLK_CLK_OUT_1 245 -#define TEGRA114_CLK_CLK_OUT_2 246 -#define TEGRA114_CLK_CLK_OUT_3 247 -#define TEGRA114_CLK_BLINK 248 +/* 245 */ +/* 246 */ +/* 247 */ +/* 248 */ #define TEGRA114_CLK_OSC 249 /* 250 */ /* 251 */ @@ -335,9 +335,9 @@ #define TEGRA114_CLK_AUDIO3_MUX 303 #define TEGRA114_CLK_AUDIO4_MUX 304 #define TEGRA114_CLK_SPDIF_MUX 305 -#define TEGRA114_CLK_CLK_OUT_1_MUX 306 -#define TEGRA114_CLK_CLK_OUT_2_MUX 307 -#define TEGRA114_CLK_CLK_OUT_3_MUX 308 +/* 306 */ +/* 307 */ +/* 308 */ #define TEGRA114_CLK_DSIA_MUX 309 #define TEGRA114_CLK_DSIB_MUX 310 #define TEGRA114_CLK_XUSB_SS_DIV2 311 diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h index 2a9acd592bff..c59f9de01b4d 100644 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ b/include/dt-bindings/clock/tegra124-car-common.h @@ -271,10 +271,10 @@ #define TEGRA124_CLK_AUDIO3 242 #define TEGRA124_CLK_AUDIO4 243 #define TEGRA124_CLK_SPDIF 244 -#define TEGRA124_CLK_CLK_OUT_1 245 -#define TEGRA124_CLK_CLK_OUT_2 246 -#define TEGRA124_CLK_CLK_OUT_3 247 -#define TEGRA124_CLK_BLINK 248 +/* 245 */ +/* 246 */ +/* 247 */ +/* 248 */ #define TEGRA124_CLK_OSC 249 /* 250 */ /* 251 */ @@ -334,9 +334,9 @@ #define TEGRA124_CLK_AUDIO3_MUX 303 #define TEGRA124_CLK_AUDIO4_MUX 304 #define TEGRA124_CLK_SPDIF_MUX 305 -#define TEGRA124_CLK_CLK_OUT_1_MUX 306 -#define TEGRA124_CLK_CLK_OUT_2_MUX 307 -#define TEGRA124_CLK_CLK_OUT_3_MUX 308 +/* 306 */ +/* 307 */ +/* 308 */ /* 309 */ /* 310 */ #define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */ diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h index b21a0eb32921..fe541f627965 100644 --- a/include/dt-bindings/clock/tegra20-car.h +++ b/include/dt-bindings/clock/tegra20-car.h @@ -131,7 +131,7 @@ #define TEGRA20_CLK_CCLK 108 #define TEGRA20_CLK_HCLK 109 #define TEGRA20_CLK_PCLK 110 -#define TEGRA20_CLK_BLINK 111 +/* 111 */ #define TEGRA20_CLK_PLL_A 112 #define TEGRA20_CLK_PLL_A_OUT0 113 #define TEGRA20_CLK_PLL_C 114 diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 7a8f10b9a66d..ab8b8a737a0a 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -306,10 +306,10 @@ #define TEGRA210_CLK_AUDIO3 274 #define TEGRA210_CLK_AUDIO4 275 #define TEGRA210_CLK_SPDIF 276 -#define TEGRA210_CLK_CLK_OUT_1 277 -#define TEGRA210_CLK_CLK_OUT_2 278 -#define TEGRA210_CLK_CLK_OUT_3 279 -#define TEGRA210_CLK_BLINK 280 +/* 277 */ +/* 278 */ +/* 279 */ +/* 280 */ #define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ #define TEGRA210_CLK_SOR0_OUT 281 #define TEGRA210_CLK_SOR1_OUT 282 @@ -351,14 +351,14 @@ #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 #define TEGRA210_CLK_XUSB_SSP_SRC 318 #define TEGRA210_CLK_PLL_RE_OUT1 319 -/* 320 */ -/* 321 */ +#define TEGRA210_CLK_PLL_MB_UD 320 +#define TEGRA210_CLK_PLL_P_UD 321 #define TEGRA210_CLK_ISP 322 #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 /* 325 */ #define TEGRA210_CLK_OSC 326 -/* 327 */ +#define TEGRA210_CLK_CSI_TPG 327 /* 328 */ /* 329 */ /* 330 */ @@ -388,9 +388,9 @@ #define TEGRA210_CLK_AUDIO3_MUX 353 #define TEGRA210_CLK_AUDIO4_MUX 354 #define TEGRA210_CLK_SPDIF_MUX 355 -#define TEGRA210_CLK_CLK_OUT_1_MUX 356 -#define TEGRA210_CLK_CLK_OUT_2_MUX 357 -#define TEGRA210_CLK_CLK_OUT_3_MUX 358 +/* 356 */ +/* 357 */ +/* 358 */ #define TEGRA210_CLK_DSIA_MUX 359 #define TEGRA210_CLK_DSIB_MUX 360 /* 361 */ diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h index 7b542c10fc27..f193663e6f28 100644 --- a/include/dt-bindings/clock/tegra30-car.h +++ b/include/dt-bindings/clock/tegra30-car.h @@ -232,11 +232,11 @@ #define TEGRA30_CLK_AUDIO3 204 #define TEGRA30_CLK_AUDIO4 205 #define TEGRA30_CLK_SPDIF 206 -#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ -#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ -#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ +/* 207 */ +/* 208 */ +/* 209 */ #define TEGRA30_CLK_SCLK 210 -#define TEGRA30_CLK_BLINK 211 +/* 211 */ #define TEGRA30_CLK_CCLK_G 212 #define TEGRA30_CLK_CCLK_LP 213 #define TEGRA30_CLK_TWD 214 @@ -262,9 +262,9 @@ /* 297 */ /* 298 */ /* 299 */ -#define TEGRA30_CLK_CLK_OUT_1_MUX 300 -#define TEGRA30_CLK_CLK_OUT_2_MUX 301 -#define TEGRA30_CLK_CLK_OUT_3_MUX 302 +/* 300 */ +/* 301 */ +/* 302 */ #define TEGRA30_CLK_AUDIO0_MUX 303 #define TEGRA30_CLK_AUDIO1_MUX 304 #define TEGRA30_CLK_AUDIO2_MUX 305 diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h index bbaebaf7adb9..0367c8c02e16 100644 --- a/include/dt-bindings/clock/x1000-cgu.h +++ b/include/dt-bindings/clock/x1000-cgu.h @@ -12,33 +12,41 @@ #ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ #define __DT_BINDINGS_CLOCK_X1000_CGU_H__ -#define X1000_CLK_EXCLK 0 -#define X1000_CLK_RTCLK 1 -#define X1000_CLK_APLL 2 -#define X1000_CLK_MPLL 3 -#define X1000_CLK_SCLKA 4 -#define X1000_CLK_CPUMUX 5 -#define X1000_CLK_CPU 6 -#define X1000_CLK_L2CACHE 7 -#define X1000_CLK_AHB0 8 -#define X1000_CLK_AHB2PMUX 9 -#define X1000_CLK_AHB2 10 -#define X1000_CLK_PCLK 11 -#define X1000_CLK_DDR 12 -#define X1000_CLK_MAC 13 -#define X1000_CLK_MSCMUX 14 -#define X1000_CLK_MSC0 15 -#define X1000_CLK_MSC1 16 -#define X1000_CLK_SSIPLL 17 -#define X1000_CLK_SSIMUX 18 -#define X1000_CLK_SFC 19 -#define X1000_CLK_I2C0 20 -#define X1000_CLK_I2C1 21 -#define X1000_CLK_I2C2 22 -#define X1000_CLK_UART0 23 -#define X1000_CLK_UART1 24 -#define X1000_CLK_UART2 25 -#define X1000_CLK_SSI 26 -#define X1000_CLK_PDMA 27 +#define X1000_CLK_EXCLK 0 +#define X1000_CLK_RTCLK 1 +#define X1000_CLK_APLL 2 +#define X1000_CLK_MPLL 3 +#define X1000_CLK_OTGPHY 4 +#define X1000_CLK_SCLKA 5 +#define X1000_CLK_CPUMUX 6 +#define X1000_CLK_CPU 7 +#define X1000_CLK_L2CACHE 8 +#define X1000_CLK_AHB0 9 +#define X1000_CLK_AHB2PMUX 10 +#define X1000_CLK_AHB2 11 +#define X1000_CLK_PCLK 12 +#define X1000_CLK_DDR 13 +#define X1000_CLK_MAC 14 +#define X1000_CLK_LCD 15 +#define X1000_CLK_MSCMUX 16 +#define X1000_CLK_MSC0 17 +#define X1000_CLK_MSC1 18 +#define X1000_CLK_OTG 19 +#define X1000_CLK_SSIPLL 20 +#define X1000_CLK_SSIPLL_DIV2 21 +#define X1000_CLK_SSIMUX 22 +#define X1000_CLK_EMC 23 +#define X1000_CLK_EFUSE 24 +#define X1000_CLK_SFC 25 +#define X1000_CLK_I2C0 26 +#define X1000_CLK_I2C1 27 +#define X1000_CLK_I2C2 28 +#define X1000_CLK_UART0 29 +#define X1000_CLK_UART1 30 +#define X1000_CLK_UART2 31 +#define X1000_CLK_TCU 32 +#define X1000_CLK_SSI 33 +#define X1000_CLK_OST 34 +#define X1000_CLK_PDMA 35 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ diff --git a/include/dt-bindings/clock/x1830-cgu.h b/include/dt-bindings/clock/x1830-cgu.h new file mode 100644 index 000000000000..801e1d09c881 --- /dev/null +++ b/include/dt-bindings/clock/x1830-cgu.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,x1830-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the x1830 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ +#define __DT_BINDINGS_CLOCK_X1830_CGU_H__ + +#define X1830_CLK_EXCLK 0 +#define X1830_CLK_RTCLK 1 +#define X1830_CLK_APLL 2 +#define X1830_CLK_MPLL 3 +#define X1830_CLK_EPLL 4 +#define X1830_CLK_VPLL 5 +#define X1830_CLK_OTGPHY 6 +#define X1830_CLK_SCLKA 7 +#define X1830_CLK_CPUMUX 8 +#define X1830_CLK_CPU 9 +#define X1830_CLK_L2CACHE 10 +#define X1830_CLK_AHB0 11 +#define X1830_CLK_AHB2PMUX 12 +#define X1830_CLK_AHB2 13 +#define X1830_CLK_PCLK 14 +#define X1830_CLK_DDR 15 +#define X1830_CLK_MAC 16 +#define X1830_CLK_LCD 17 +#define X1830_CLK_MSCMUX 18 +#define X1830_CLK_MSC0 19 +#define X1830_CLK_MSC1 20 +#define X1830_CLK_SSIPLL 21 +#define X1830_CLK_SSIPLL_DIV2 22 +#define X1830_CLK_SSIMUX 23 +#define X1830_CLK_EMC 24 +#define X1830_CLK_EFUSE 25 +#define X1830_CLK_OTG 26 +#define X1830_CLK_SSI0 27 +#define X1830_CLK_SMB0 28 +#define X1830_CLK_SMB1 29 +#define X1830_CLK_SMB2 30 +#define X1830_CLK_UART0 31 +#define X1830_CLK_UART1 32 +#define X1830_CLK_SSI1 33 +#define X1830_CLK_SFC 34 +#define X1830_CLK_PDMA 35 +#define X1830_CLK_TCU 36 +#define X1830_CLK_DTRNG 37 +#define X1830_CLK_OST 38 + +#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h index 4e61f6485097..54278d5c1856 100644 --- a/include/dt-bindings/firmware/imx/rsrc.h +++ b/include/dt-bindings/firmware/imx/rsrc.h @@ -547,4 +547,88 @@ #define IMX_SC_R_ATTESTATION 545 #define IMX_SC_R_LAST 546 +/* + * Defines for SC PM CLK + */ +#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */ +#define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */ +#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */ +#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */ +#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */ +#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */ +#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */ +#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */ +#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */ +#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */ +#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */ +#define IMX_SC_PM_CLK_PLL 4 /* PLL */ +#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */ + +/* + * Defines for SC CONTROL + */ +#define IMX_SC_C_TEMP 0 +#define IMX_SC_C_TEMP_HI 1 +#define IMX_SC_C_TEMP_LOW 2 +#define IMX_SC_C_PXL_LINK_MST1_ADDR 3 +#define IMX_SC_C_PXL_LINK_MST2_ADDR 4 +#define IMX_SC_C_PXL_LINK_MST_ENB 5 +#define IMX_SC_C_PXL_LINK_MST1_ENB 6 +#define IMX_SC_C_PXL_LINK_MST2_ENB 7 +#define IMX_SC_C_PXL_LINK_SLV1_ADDR 8 +#define IMX_SC_C_PXL_LINK_SLV2_ADDR 9 +#define IMX_SC_C_PXL_LINK_MST_VLD 10 +#define IMX_SC_C_PXL_LINK_MST1_VLD 11 +#define IMX_SC_C_PXL_LINK_MST2_VLD 12 +#define IMX_SC_C_SINGLE_MODE 13 +#define IMX_SC_C_ID 14 +#define IMX_SC_C_PXL_CLK_POLARITY 15 +#define IMX_SC_C_LINESTATE 16 +#define IMX_SC_C_PCIE_G_RST 17 +#define IMX_SC_C_PCIE_BUTTON_RST 18 +#define IMX_SC_C_PCIE_PERST 19 +#define IMX_SC_C_PHY_RESET 20 +#define IMX_SC_C_PXL_LINK_RATE_CORRECTION 21 +#define IMX_SC_C_PANIC 22 +#define IMX_SC_C_PRIORITY_GROUP 23 +#define IMX_SC_C_TXCLK 24 +#define IMX_SC_C_CLKDIV 25 +#define IMX_SC_C_DISABLE_50 26 +#define IMX_SC_C_DISABLE_125 27 +#define IMX_SC_C_SEL_125 28 +#define IMX_SC_C_MODE 29 +#define IMX_SC_C_SYNC_CTRL0 30 +#define IMX_SC_C_KACHUNK_CNT 31 +#define IMX_SC_C_KACHUNK_SEL 32 +#define IMX_SC_C_SYNC_CTRL1 33 +#define IMX_SC_C_DPI_RESET 34 +#define IMX_SC_C_MIPI_RESET 35 +#define IMX_SC_C_DUAL_MODE 36 +#define IMX_SC_C_VOLTAGE 37 +#define IMX_SC_C_PXL_LINK_SEL 38 +#define IMX_SC_C_OFS_SEL 39 +#define IMX_SC_C_OFS_AUDIO 40 +#define IMX_SC_C_OFS_PERIPH 41 +#define IMX_SC_C_OFS_IRQ 42 +#define IMX_SC_C_RST0 43 +#define IMX_SC_C_RST1 44 +#define IMX_SC_C_SEL0 45 +#define IMX_SC_C_CALIB0 46 +#define IMX_SC_C_CALIB1 47 +#define IMX_SC_C_CALIB2 48 +#define IMX_SC_C_IPG_DEBUG 49 +#define IMX_SC_C_IPG_DOZE 50 +#define IMX_SC_C_IPG_WAIT 51 +#define IMX_SC_C_IPG_STOP 52 +#define IMX_SC_C_IPG_STOP_MODE 53 +#define IMX_SC_C_IPG_STOP_ACK 54 +#define IMX_SC_C_SYNC_CTRL 55 +#define IMX_SC_C_OFS_AUDIO_ALT 56 +#define IMX_SC_C_DSP_BYP 57 +#define IMX_SC_C_CLK_GEN_EN 58 +#define IMX_SC_C_INTF_SEL 59 +#define IMX_SC_C_RXC_DLY 60 +#define IMX_SC_C_TIMER_SEL 61 +#define IMX_SC_C_LAST 62 + #endif /* __DT_BINDINGS_RSCRC_IMX_H */ diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h index b6a835d37826..0c2e27d28e0a 100644 --- a/include/dt-bindings/input/linux-event-codes.h +++ b/include/dt-bindings/input/linux-event-codes.h @@ -888,7 +888,8 @@ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_PEN_INSERTED 0x0f /* set = pen inserted */ -#define SW_MAX 0x0f +#define SW_MACHINE_COVER 0x10 /* set = cover closed */ +#define SW_MAX 0x10 #define SW_CNT (SW_MAX+1) /* diff --git a/include/dt-bindings/interconnect/imx8mm.h b/include/dt-bindings/interconnect/imx8mm.h new file mode 100644 index 000000000000..8f10bb06cb59 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mm.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019, BayLibre + * Copyright (c) 2019-2020, NXP + * Author: Alexandre Bailon + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MM_H + +#define IMX8MM_ICN_NOC 1 +#define IMX8MM_ICS_DRAM 2 +#define IMX8MM_ICS_OCRAM 3 +#define IMX8MM_ICM_A53 4 + +#define IMX8MM_ICM_VPU_H1 5 +#define IMX8MM_ICM_VPU_G1 6 +#define IMX8MM_ICM_VPU_G2 7 +#define IMX8MM_ICN_VIDEO 8 + +#define IMX8MM_ICM_GPU2D 9 +#define IMX8MM_ICM_GPU3D 10 +#define IMX8MM_ICN_GPU 11 + +#define IMX8MM_ICM_CSI 12 +#define IMX8MM_ICM_LCDIF 13 +#define IMX8MM_ICN_MIPI 14 + +#define IMX8MM_ICM_USB1 15 +#define IMX8MM_ICM_USB2 16 +#define IMX8MM_ICM_PCIE 17 +#define IMX8MM_ICN_HSIO 18 + +#define IMX8MM_ICM_SDMA2 19 +#define IMX8MM_ICM_SDMA3 20 +#define IMX8MM_ICN_AUDIO 21 + +#define IMX8MM_ICN_ENET 22 +#define IMX8MM_ICM_ENET 23 + +#define IMX8MM_ICN_MAIN 24 +#define IMX8MM_ICM_NAND 25 +#define IMX8MM_ICM_SDMA1 26 +#define IMX8MM_ICM_USDHC1 27 +#define IMX8MM_ICM_USDHC2 28 +#define IMX8MM_ICM_USDHC3 29 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */ diff --git a/include/dt-bindings/interconnect/imx8mn.h b/include/dt-bindings/interconnect/imx8mn.h new file mode 100644 index 000000000000..307b977100b6 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mn.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MN_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MN_H + +#define IMX8MN_ICN_NOC 1 +#define IMX8MN_ICS_DRAM 2 +#define IMX8MN_ICS_OCRAM 3 +#define IMX8MN_ICM_A53 4 + +#define IMX8MN_ICM_GPU 5 +#define IMX8MN_ICN_GPU 6 + +#define IMX8MN_ICM_CSI1 7 +#define IMX8MN_ICM_CSI2 8 +#define IMX8MN_ICM_ISI 9 +#define IMX8MN_ICM_LCDIF 10 +#define IMX8MN_ICN_MIPI 11 + +#define IMX8MN_ICM_USB 12 + +#define IMX8MN_ICM_SDMA2 13 +#define IMX8MN_ICM_SDMA3 14 +#define IMX8MN_ICN_AUDIO 15 + +#define IMX8MN_ICN_ENET 16 +#define IMX8MN_ICM_ENET 17 + +#define IMX8MN_ICM_NAND 18 +#define IMX8MN_ICM_SDMA1 19 +#define IMX8MN_ICM_USDHC1 20 +#define IMX8MN_ICM_USDHC2 21 +#define IMX8MN_ICM_USDHC3 22 +#define IMX8MN_ICN_MAIN 23 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MN_H */ diff --git a/include/dt-bindings/interconnect/imx8mq.h b/include/dt-bindings/interconnect/imx8mq.h new file mode 100644 index 000000000000..1a4cae7f8be2 --- /dev/null +++ b/include/dt-bindings/interconnect/imx8mq.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Interconnect framework driver for i.MX SoC + * + * Copyright (c) 2019-2020, NXP + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MQ_H +#define __DT_BINDINGS_INTERCONNECT_IMX8MQ_H + +#define IMX8MQ_ICN_NOC 1 +#define IMX8MQ_ICS_DRAM 2 +#define IMX8MQ_ICS_OCRAM 3 +#define IMX8MQ_ICM_A53 4 + +#define IMX8MQ_ICM_VPU 5 +#define IMX8MQ_ICN_VIDEO 6 + +#define IMX8MQ_ICM_GPU 7 +#define IMX8MQ_ICN_GPU 8 + +#define IMX8MQ_ICM_DCSS 9 +#define IMX8MQ_ICN_DCSS 10 + +#define IMX8MQ_ICM_USB1 11 +#define IMX8MQ_ICM_USB2 12 +#define IMX8MQ_ICN_USB 13 + +#define IMX8MQ_ICM_CSI1 14 +#define IMX8MQ_ICM_CSI2 15 +#define IMX8MQ_ICM_LCDIF 16 +#define IMX8MQ_ICN_DISPLAY 17 + +#define IMX8MQ_ICM_SDMA2 18 +#define IMX8MQ_ICN_AUDIO 19 + +#define IMX8MQ_ICN_ENET 20 +#define IMX8MQ_ICM_ENET 21 + +#define IMX8MQ_ICM_SDMA1 22 +#define IMX8MQ_ICM_NAND 23 +#define IMX8MQ_ICM_USDHC1 24 +#define IMX8MQ_ICM_USDHC2 25 +#define IMX8MQ_ICM_PCIE1 26 +#define IMX8MQ_ICM_PCIE2 27 +#define IMX8MQ_ICN_MAIN 28 + +#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MQ_H */ diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h b/include/dt-bindings/mailbox/qcom-ipcc.h new file mode 100644 index 000000000000..4c23eefed5f3 --- /dev/null +++ b/include/dt-bindings/mailbox/qcom-ipcc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_MAILBOX_IPCC_H +#define __DT_BINDINGS_MAILBOX_IPCC_H + +/* Signal IDs for MPROC protocol */ +#define IPCC_MPROC_SIGNAL_GLINK_QMP 0 +#define IPCC_MPROC_SIGNAL_SMP2P 2 +#define IPCC_MPROC_SIGNAL_PING 3 + +/* Client IDs */ +#define IPCC_CLIENT_AOP 0 +#define IPCC_CLIENT_TZ 1 +#define IPCC_CLIENT_MPSS 2 +#define IPCC_CLIENT_LPASS 3 +#define IPCC_CLIENT_SLPI 4 +#define IPCC_CLIENT_SDC 5 +#define IPCC_CLIENT_CDSP 6 +#define IPCC_CLIENT_NPU 7 +#define IPCC_CLIENT_APSS 8 +#define IPCC_CLIENT_GPU 9 +#define IPCC_CLIENT_CVP 10 +#define IPCC_CLIENT_CAM 11 +#define IPCC_CLIENT_VPU 12 +#define IPCC_CLIENT_PCIE0 13 +#define IPCC_CLIENT_PCIE1 14 +#define IPCC_CLIENT_PCIE2 15 +#define IPCC_CLIENT_SPSS 16 + +#endif diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h index 1f3f866fae7b..3727ef72138b 100644 --- a/include/dt-bindings/phy/phy.h +++ b/include/dt-bindings/phy/phy.h @@ -17,5 +17,6 @@ #define PHY_TYPE_USB3 4 #define PHY_TYPE_UFS 5 #define PHY_TYPE_DP 6 +#define PHY_TYPE_XPCS 7 #endif /* _DT_BINDINGS_PHY */ diff --git a/include/dt-bindings/pinctrl/pads-imx8dxl.h b/include/dt-bindings/pinctrl/pads-imx8dxl.h new file mode 100644 index 000000000000..b1d7b84c3e0a --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8dxl.h @@ -0,0 +1,639 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019~2020 NXP + */ + +#ifndef _IMX8DXL_PADS_H +#define _IMX8DXL_PADS_H + +/* pin id */ +#define IMX8DXL_PCIE_CTRL0_PERST_B 0 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B 1 +#define IMX8DXL_PCIE_CTRL0_WAKE_B 2 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 +#define IMX8DXL_USB_SS3_TC0 4 +#define IMX8DXL_USB_SS3_TC1 5 +#define IMX8DXL_USB_SS3_TC2 6 +#define IMX8DXL_USB_SS3_TC3 7 +#define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 8 +#define IMX8DXL_EMMC0_CLK 9 +#define IMX8DXL_EMMC0_CMD 10 +#define IMX8DXL_EMMC0_DATA0 11 +#define IMX8DXL_EMMC0_DATA1 12 +#define IMX8DXL_EMMC0_DATA2 13 +#define IMX8DXL_EMMC0_DATA3 14 +#define IMX8DXL_EMMC0_DATA4 15 +#define IMX8DXL_EMMC0_DATA5 16 +#define IMX8DXL_EMMC0_DATA6 17 +#define IMX8DXL_EMMC0_DATA7 18 +#define IMX8DXL_EMMC0_STROBE 19 +#define IMX8DXL_EMMC0_RESET_B 20 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 21 +#define IMX8DXL_USDHC1_RESET_B 22 +#define IMX8DXL_USDHC1_VSELECT 23 +#define IMX8DXL_CTL_NAND_RE_P_N 24 +#define IMX8DXL_USDHC1_WP 25 +#define IMX8DXL_USDHC1_CD_B 26 +#define IMX8DXL_CTL_NAND_DQS_P_N 27 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 28 +#define IMX8DXL_ENET0_RGMII_TXC 29 +#define IMX8DXL_ENET0_RGMII_TX_CTL 30 +#define IMX8DXL_ENET0_RGMII_TXD0 31 +#define IMX8DXL_ENET0_RGMII_TXD1 32 +#define IMX8DXL_ENET0_RGMII_TXD2 33 +#define IMX8DXL_ENET0_RGMII_TXD3 34 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 35 +#define IMX8DXL_ENET0_RGMII_RXC 36 +#define IMX8DXL_ENET0_RGMII_RX_CTL 37 +#define IMX8DXL_ENET0_RGMII_RXD0 38 +#define IMX8DXL_ENET0_RGMII_RXD1 39 +#define IMX8DXL_ENET0_RGMII_RXD2 40 +#define IMX8DXL_ENET0_RGMII_RXD3 41 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 42 +#define IMX8DXL_ENET0_REFCLK_125M_25M 43 +#define IMX8DXL_ENET0_MDIO 44 +#define IMX8DXL_ENET0_MDC 45 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 46 +#define IMX8DXL_ENET1_RGMII_TXC 47 +#define IMX8DXL_ENET1_RGMII_TXD2 48 +#define IMX8DXL_ENET1_RGMII_TX_CTL 49 +#define IMX8DXL_ENET1_RGMII_TXD3 50 +#define IMX8DXL_ENET1_RGMII_RXC 51 +#define IMX8DXL_ENET1_RGMII_RXD3 52 +#define IMX8DXL_ENET1_RGMII_RXD2 53 +#define IMX8DXL_ENET1_RGMII_RXD1 54 +#define IMX8DXL_ENET1_RGMII_TXD0 55 +#define IMX8DXL_ENET1_RGMII_TXD1 56 +#define IMX8DXL_ENET1_RGMII_RXD0 57 +#define IMX8DXL_ENET1_RGMII_RX_CTL 58 +#define IMX8DXL_ENET1_REFCLK_125M_25M 59 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 60 +#define IMX8DXL_SPI3_SCK 61 +#define IMX8DXL_SPI3_SDO 62 +#define IMX8DXL_SPI3_SDI 63 +#define IMX8DXL_SPI3_CS0 64 +#define IMX8DXL_SPI3_CS1 65 +#define IMX8DXL_MCLK_IN1 66 +#define IMX8DXL_MCLK_IN0 67 +#define IMX8DXL_MCLK_OUT0 68 +#define IMX8DXL_UART1_TX 69 +#define IMX8DXL_UART1_RX 70 +#define IMX8DXL_UART1_RTS_B 71 +#define IMX8DXL_UART1_CTS_B 72 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 73 +#define IMX8DXL_SPI0_SCK 74 +#define IMX8DXL_SPI0_SDI 75 +#define IMX8DXL_SPI0_SDO 76 +#define IMX8DXL_SPI0_CS1 77 +#define IMX8DXL_SPI0_CS0 78 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 79 +#define IMX8DXL_ADC_IN1 80 +#define IMX8DXL_ADC_IN0 81 +#define IMX8DXL_ADC_IN3 82 +#define IMX8DXL_ADC_IN2 83 +#define IMX8DXL_ADC_IN5 84 +#define IMX8DXL_ADC_IN4 85 +#define IMX8DXL_FLEXCAN0_RX 86 +#define IMX8DXL_FLEXCAN0_TX 87 +#define IMX8DXL_FLEXCAN1_RX 88 +#define IMX8DXL_FLEXCAN1_TX 89 +#define IMX8DXL_FLEXCAN2_RX 90 +#define IMX8DXL_FLEXCAN2_TX 91 +#define IMX8DXL_UART0_RX 92 +#define IMX8DXL_UART0_TX 93 +#define IMX8DXL_UART2_TX 94 +#define IMX8DXL_UART2_RX 95 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 96 +#define IMX8DXL_JTAG_TRST_B 97 +#define IMX8DXL_PMIC_I2C_SCL 98 +#define IMX8DXL_PMIC_I2C_SDA 99 +#define IMX8DXL_PMIC_INT_B 100 +#define IMX8DXL_SCU_GPIO0_00 101 +#define IMX8DXL_SCU_GPIO0_01 102 +#define IMX8DXL_SCU_PMIC_STANDBY 103 +#define IMX8DXL_SCU_BOOT_MODE1 104 +#define IMX8DXL_SCU_BOOT_MODE0 105 +#define IMX8DXL_SCU_BOOT_MODE2 106 +#define IMX8DXL_SNVS_TAMPER_OUT1 107 +#define IMX8DXL_SNVS_TAMPER_OUT2 108 +#define IMX8DXL_SNVS_TAMPER_OUT3 109 +#define IMX8DXL_SNVS_TAMPER_OUT4 110 +#define IMX8DXL_SNVS_TAMPER_IN0 111 +#define IMX8DXL_SNVS_TAMPER_IN1 112 +#define IMX8DXL_SNVS_TAMPER_IN2 113 +#define IMX8DXL_SNVS_TAMPER_IN3 114 +#define IMX8DXL_SPI1_SCK 115 +#define IMX8DXL_SPI1_SDO 116 +#define IMX8DXL_SPI1_SDI 117 +#define IMX8DXL_SPI1_CS0 118 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 119 +#define IMX8DXL_QSPI0A_DATA1 120 +#define IMX8DXL_QSPI0A_DATA0 121 +#define IMX8DXL_QSPI0A_DATA3 122 +#define IMX8DXL_QSPI0A_DATA2 123 +#define IMX8DXL_QSPI0A_SS0_B 124 +#define IMX8DXL_QSPI0A_DQS 125 +#define IMX8DXL_QSPI0A_SCLK 126 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 127 +#define IMX8DXL_QSPI0B_SCLK 128 +#define IMX8DXL_QSPI0B_DQS 129 +#define IMX8DXL_QSPI0B_DATA1 130 +#define IMX8DXL_QSPI0B_DATA0 131 +#define IMX8DXL_QSPI0B_DATA3 132 +#define IMX8DXL_QSPI0B_DATA2 133 +#define IMX8DXL_QSPI0B_SS0_B 134 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 135 + +/* format: */ +#define IMX8DXL_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8DXL_PCIE_CTRL0_PERST_B 0 +#define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 4 +#define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO7_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 5 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8DXL_PCIE_CTRL0_CLKREQ_B 0 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 4 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO7_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 5 +#define IMX8DXL_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8DXL_PCIE_CTRL0_WAKE_B 0 +#define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 4 +#define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO7_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 5 +#define IMX8DXL_USB_SS3_TC0_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC0 0 +#define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8DXL_USB_SS3_TC0 1 +#define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC0 2 +#define IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8DXL_USB_SS3_TC0 4 +#define IMX8DXL_USB_SS3_TC0_LSIO_GPIO7_IO03 IMX8DXL_USB_SS3_TC0 5 +#define IMX8DXL_USB_SS3_TC1_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC1 0 +#define IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC1 1 +#define IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8DXL_USB_SS3_TC1 4 +#define IMX8DXL_USB_SS3_TC1_LSIO_GPIO7_IO04 IMX8DXL_USB_SS3_TC1 5 +#define IMX8DXL_USB_SS3_TC2_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC2 0 +#define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8DXL_USB_SS3_TC2 1 +#define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC2 2 +#define IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8DXL_USB_SS3_TC2 4 +#define IMX8DXL_USB_SS3_TC2_LSIO_GPIO7_IO05 IMX8DXL_USB_SS3_TC2 5 +#define IMX8DXL_USB_SS3_TC3_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC3 0 +#define IMX8DXL_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC3 1 +#define IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8DXL_USB_SS3_TC3 4 +#define IMX8DXL_USB_SS3_TC3_LSIO_GPIO7_IO06 IMX8DXL_USB_SS3_TC3 5 +#define IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK IMX8DXL_EMMC0_CLK 0 +#define IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B IMX8DXL_EMMC0_CLK 1 +#define IMX8DXL_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8DXL_EMMC0_CLK 4 +#define IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD IMX8DXL_EMMC0_CMD 0 +#define IMX8DXL_EMMC0_CMD_CONN_NAND_DQS IMX8DXL_EMMC0_CMD 1 +#define IMX8DXL_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8DXL_EMMC0_CMD 4 +#define IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8DXL_EMMC0_DATA0 0 +#define IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 IMX8DXL_EMMC0_DATA0 1 +#define IMX8DXL_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8DXL_EMMC0_DATA0 4 +#define IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8DXL_EMMC0_DATA1 0 +#define IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 IMX8DXL_EMMC0_DATA1 1 +#define IMX8DXL_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8DXL_EMMC0_DATA1 4 +#define IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8DXL_EMMC0_DATA2 0 +#define IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 IMX8DXL_EMMC0_DATA2 1 +#define IMX8DXL_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8DXL_EMMC0_DATA2 4 +#define IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8DXL_EMMC0_DATA3 0 +#define IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 IMX8DXL_EMMC0_DATA3 1 +#define IMX8DXL_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8DXL_EMMC0_DATA3 4 +#define IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8DXL_EMMC0_DATA4 0 +#define IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 IMX8DXL_EMMC0_DATA4 1 +#define IMX8DXL_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8DXL_EMMC0_DATA4 4 +#define IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8DXL_EMMC0_DATA5 0 +#define IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 IMX8DXL_EMMC0_DATA5 1 +#define IMX8DXL_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8DXL_EMMC0_DATA5 4 +#define IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8DXL_EMMC0_DATA6 0 +#define IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 IMX8DXL_EMMC0_DATA6 1 +#define IMX8DXL_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8DXL_EMMC0_DATA6 4 +#define IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8DXL_EMMC0_DATA7 0 +#define IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 IMX8DXL_EMMC0_DATA7 1 +#define IMX8DXL_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8DXL_EMMC0_DATA7 4 +#define IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8DXL_EMMC0_STROBE 0 +#define IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE IMX8DXL_EMMC0_STROBE 1 +#define IMX8DXL_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8DXL_EMMC0_STROBE 4 +#define IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8DXL_EMMC0_RESET_B 0 +#define IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B IMX8DXL_EMMC0_RESET_B 1 +#define IMX8DXL_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8DXL_EMMC0_RESET_B 4 +#define IMX8DXL_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8DXL_USDHC1_RESET_B 0 +#define IMX8DXL_USDHC1_RESET_B_CONN_NAND_RE_N IMX8DXL_USDHC1_RESET_B 1 +#define IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8DXL_USDHC1_RESET_B 2 +#define IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B IMX8DXL_USDHC1_RESET_B 3 +#define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8DXL_USDHC1_RESET_B 4 +#define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO7_IO08 IMX8DXL_USDHC1_RESET_B 5 +#define IMX8DXL_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8DXL_USDHC1_VSELECT 0 +#define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_P IMX8DXL_USDHC1_VSELECT 1 +#define IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8DXL_USDHC1_VSELECT 2 +#define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B IMX8DXL_USDHC1_VSELECT 3 +#define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8DXL_USDHC1_VSELECT 4 +#define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO7_IO09 IMX8DXL_USDHC1_VSELECT 5 +#define IMX8DXL_USDHC1_WP_CONN_USDHC1_WP IMX8DXL_USDHC1_WP 0 +#define IMX8DXL_USDHC1_WP_CONN_NAND_DQS_N IMX8DXL_USDHC1_WP 1 +#define IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI IMX8DXL_USDHC1_WP 2 +#define IMX8DXL_USDHC1_WP_CONN_NAND_ALE IMX8DXL_USDHC1_WP 3 +#define IMX8DXL_USDHC1_WP_LSIO_GPIO4_IO21 IMX8DXL_USDHC1_WP 4 +#define IMX8DXL_USDHC1_WP_LSIO_GPIO7_IO10 IMX8DXL_USDHC1_WP 5 +#define IMX8DXL_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8DXL_USDHC1_CD_B 0 +#define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS_P IMX8DXL_USDHC1_CD_B 1 +#define IMX8DXL_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8DXL_USDHC1_CD_B 2 +#define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS IMX8DXL_USDHC1_CD_B 3 +#define IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8DXL_USDHC1_CD_B 4 +#define IMX8DXL_USDHC1_CD_B_LSIO_GPIO7_IO11 IMX8DXL_USDHC1_CD_B 5 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8DXL_ENET0_RGMII_TXC 0 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8DXL_ENET0_RGMII_TXC 1 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8DXL_ENET0_RGMII_TXC 2 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8DXL_ENET0_RGMII_TXC 3 +#define IMX8DXL_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8DXL_ENET0_RGMII_TXC 4 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK IMX8DXL_ENET0_RGMII_TXC 5 +#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8DXL_ENET0_RGMII_TX_CTL 0 +#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8DXL_ENET0_RGMII_TX_CTL 3 +#define IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8DXL_ENET0_RGMII_TX_CTL 4 +#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD IMX8DXL_ENET0_RGMII_TX_CTL 5 +#define IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8DXL_ENET0_RGMII_TXD0 0 +#define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8DXL_ENET0_RGMII_TXD0 3 +#define IMX8DXL_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8DXL_ENET0_RGMII_TXD0 4 +#define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 IMX8DXL_ENET0_RGMII_TXD0 5 +#define IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8DXL_ENET0_RGMII_TXD1 0 +#define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8DXL_ENET0_RGMII_TXD1 3 +#define IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8DXL_ENET0_RGMII_TXD1 4 +#define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 IMX8DXL_ENET0_RGMII_TXD1 5 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8DXL_ENET0_RGMII_TXD2 0 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8DXL_ENET0_RGMII_TXD2 2 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8DXL_ENET0_RGMII_TXD2 3 +#define IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8DXL_ENET0_RGMII_TXD2 4 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 IMX8DXL_ENET0_RGMII_TXD2 5 +#define IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8DXL_ENET0_RGMII_TXD3 0 +#define IMX8DXL_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8DXL_ENET0_RGMII_TXD3 2 +#define IMX8DXL_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8DXL_ENET0_RGMII_TXD3 4 +#define IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 IMX8DXL_ENET0_RGMII_TXD3 5 +#define IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8DXL_ENET0_RGMII_RXC 0 +#define IMX8DXL_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8DXL_ENET0_RGMII_RXC 2 +#define IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8DXL_ENET0_RGMII_RXC 3 +#define IMX8DXL_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8DXL_ENET0_RGMII_RXC 4 +#define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8DXL_ENET0_RGMII_RX_CTL 0 +#define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8DXL_ENET0_RGMII_RX_CTL 3 +#define IMX8DXL_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8DXL_ENET0_RGMII_RX_CTL 4 +#define IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8DXL_ENET0_RGMII_RXD0 0 +#define IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8DXL_ENET0_RGMII_RXD0 3 +#define IMX8DXL_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8DXL_ENET0_RGMII_RXD0 4 +#define IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8DXL_ENET0_RGMII_RXD1 0 +#define IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8DXL_ENET0_RGMII_RXD1 3 +#define IMX8DXL_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8DXL_ENET0_RGMII_RXD1 4 +#define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8DXL_ENET0_RGMII_RXD2 0 +#define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8DXL_ENET0_RGMII_RXD2 1 +#define IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8DXL_ENET0_RGMII_RXD2 3 +#define IMX8DXL_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8DXL_ENET0_RGMII_RXD2 4 +#define IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8DXL_ENET0_RGMII_RXD3 0 +#define IMX8DXL_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8DXL_ENET0_RGMII_RXD3 2 +#define IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8DXL_ENET0_RGMII_RXD3 3 +#define IMX8DXL_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8DXL_ENET0_RGMII_RXD3 4 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8DXL_ENET0_REFCLK_125M_25M 0 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8DXL_ENET0_REFCLK_125M_25M 1 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_IN IMX8DXL_ENET0_REFCLK_125M_25M 2 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_OUT IMX8DXL_ENET0_REFCLK_125M_25M 3 +#define IMX8DXL_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8DXL_ENET0_REFCLK_125M_25M 4 +#define IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO IMX8DXL_ENET0_MDIO 0 +#define IMX8DXL_ENET0_MDIO_ADMA_I2C3_SDA IMX8DXL_ENET0_MDIO 1 +#define IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO IMX8DXL_ENET0_MDIO 2 +#define IMX8DXL_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8DXL_ENET0_MDIO 4 +#define IMX8DXL_ENET0_MDIO_LSIO_GPIO7_IO16 IMX8DXL_ENET0_MDIO 5 +#define IMX8DXL_ENET0_MDC_CONN_ENET0_MDC IMX8DXL_ENET0_MDC 0 +#define IMX8DXL_ENET0_MDC_ADMA_I2C3_SCL IMX8DXL_ENET0_MDC 1 +#define IMX8DXL_ENET0_MDC_CONN_EQOS_MDC IMX8DXL_ENET0_MDC 2 +#define IMX8DXL_ENET0_MDC_LSIO_GPIO5_IO11 IMX8DXL_ENET0_MDC 4 +#define IMX8DXL_ENET0_MDC_LSIO_GPIO7_IO17 IMX8DXL_ENET0_MDC 5 +#define IMX8DXL_ENET1_RGMII_TXC_LSIO_GPIO0_IO00 IMX8DXL_ENET1_RGMII_TXC 0 +#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_OUT IMX8DXL_ENET1_RGMII_TXC 1 +#define IMX8DXL_ENET1_RGMII_TXC_ADMA_LCDIF_D00 IMX8DXL_ENET1_RGMII_TXC 2 +#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC IMX8DXL_ENET1_RGMII_TXC 3 +#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_IN IMX8DXL_ENET1_RGMII_TXC 4 +#define IMX8DXL_ENET1_RGMII_TXD2_ADMA_LCDIF_D01 IMX8DXL_ENET1_RGMII_TXD2 2 +#define IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 IMX8DXL_ENET1_RGMII_TXD2 3 +#define IMX8DXL_ENET1_RGMII_TXD2_LSIO_GPIO0_IO01 IMX8DXL_ENET1_RGMII_TXD2 4 +#define IMX8DXL_ENET1_RGMII_TX_CTL_ADMA_LCDIF_D02 IMX8DXL_ENET1_RGMII_TX_CTL 2 +#define IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL IMX8DXL_ENET1_RGMII_TX_CTL 3 +#define IMX8DXL_ENET1_RGMII_TX_CTL_LSIO_GPIO0_IO02 IMX8DXL_ENET1_RGMII_TX_CTL 4 +#define IMX8DXL_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 IMX8DXL_ENET1_RGMII_TXD3 2 +#define IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 IMX8DXL_ENET1_RGMII_TXD3 3 +#define IMX8DXL_ENET1_RGMII_TXD3_LSIO_GPIO0_IO03 IMX8DXL_ENET1_RGMII_TXD3 4 +#define IMX8DXL_ENET1_RGMII_RXC_ADMA_LCDIF_D04 IMX8DXL_ENET1_RGMII_RXC 2 +#define IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC IMX8DXL_ENET1_RGMII_RXC 3 +#define IMX8DXL_ENET1_RGMII_RXC_LSIO_GPIO0_IO04 IMX8DXL_ENET1_RGMII_RXC 4 +#define IMX8DXL_ENET1_RGMII_RXD3_ADMA_LCDIF_D05 IMX8DXL_ENET1_RGMII_RXD3 2 +#define IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 IMX8DXL_ENET1_RGMII_RXD3 3 +#define IMX8DXL_ENET1_RGMII_RXD3_LSIO_GPIO0_IO05 IMX8DXL_ENET1_RGMII_RXD3 4 +#define IMX8DXL_ENET1_RGMII_RXD2_ADMA_LCDIF_D06 IMX8DXL_ENET1_RGMII_RXD2 2 +#define IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 IMX8DXL_ENET1_RGMII_RXD2 3 +#define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO0_IO06 IMX8DXL_ENET1_RGMII_RXD2 4 +#define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO6_IO00 IMX8DXL_ENET1_RGMII_RXD2 5 +#define IMX8DXL_ENET1_RGMII_RXD1_ADMA_LCDIF_D07 IMX8DXL_ENET1_RGMII_RXD1 2 +#define IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 IMX8DXL_ENET1_RGMII_RXD1 3 +#define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO0_IO07 IMX8DXL_ENET1_RGMII_RXD1 4 +#define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO6_IO01 IMX8DXL_ENET1_RGMII_RXD1 5 +#define IMX8DXL_ENET1_RGMII_TXD0_ADMA_LCDIF_D08 IMX8DXL_ENET1_RGMII_TXD0 2 +#define IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 IMX8DXL_ENET1_RGMII_TXD0 3 +#define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO0_IO08 IMX8DXL_ENET1_RGMII_TXD0 4 +#define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO6_IO02 IMX8DXL_ENET1_RGMII_TXD0 5 +#define IMX8DXL_ENET1_RGMII_TXD1_ADMA_LCDIF_D09 IMX8DXL_ENET1_RGMII_TXD1 2 +#define IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 IMX8DXL_ENET1_RGMII_TXD1 3 +#define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO0_IO09 IMX8DXL_ENET1_RGMII_TXD1 4 +#define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO6_IO03 IMX8DXL_ENET1_RGMII_TXD1 5 +#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_SPDIF0_RX IMX8DXL_ENET1_RGMII_RXD0 0 +#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_MQS_R IMX8DXL_ENET1_RGMII_RXD0 1 +#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_LCDIF_D10 IMX8DXL_ENET1_RGMII_RXD0 2 +#define IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 IMX8DXL_ENET1_RGMII_RXD0 3 +#define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO0_IO10 IMX8DXL_ENET1_RGMII_RXD0 4 +#define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO6_IO04 IMX8DXL_ENET1_RGMII_RXD0 5 +#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_SPDIF0_TX IMX8DXL_ENET1_RGMII_RX_CTL 0 +#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_MQS_L IMX8DXL_ENET1_RGMII_RX_CTL 1 +#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_LCDIF_D11 IMX8DXL_ENET1_RGMII_RX_CTL 2 +#define IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL IMX8DXL_ENET1_RGMII_RX_CTL 3 +#define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO0_IO11 IMX8DXL_ENET1_RGMII_RX_CTL 4 +#define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO05 IMX8DXL_ENET1_RGMII_RX_CTL 5 +#define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_SPDIF0_EXT_CLK IMX8DXL_ENET1_REFCLK_125M_25M 0 +#define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_LCDIF_D12 IMX8DXL_ENET1_REFCLK_125M_25M 2 +#define IMX8DXL_ENET1_REFCLK_125M_25M_CONN_EQOS_REFCLK_125M_25M IMX8DXL_ENET1_REFCLK_125M_25M 3 +#define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO0_IO12 IMX8DXL_ENET1_REFCLK_125M_25M 4 +#define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO6_IO06 IMX8DXL_ENET1_REFCLK_125M_25M 5 +#define IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK IMX8DXL_SPI3_SCK 0 +#define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D13 IMX8DXL_SPI3_SCK 2 +#define IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 IMX8DXL_SPI3_SCK 4 +#define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D00 IMX8DXL_SPI3_SCK 5 +#define IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO IMX8DXL_SPI3_SDO 0 +#define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D14 IMX8DXL_SPI3_SDO 2 +#define IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 IMX8DXL_SPI3_SDO 4 +#define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D01 IMX8DXL_SPI3_SDO 5 +#define IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI IMX8DXL_SPI3_SDI 0 +#define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D15 IMX8DXL_SPI3_SDI 2 +#define IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 IMX8DXL_SPI3_SDI 4 +#define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D02 IMX8DXL_SPI3_SDI 5 +#define IMX8DXL_SPI3_CS0_ADMA_SPI3_CS0 IMX8DXL_SPI3_CS0 0 +#define IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8DXL_SPI3_CS0 1 +#define IMX8DXL_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8DXL_SPI3_CS0 2 +#define IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 IMX8DXL_SPI3_CS0 4 +#define IMX8DXL_SPI3_CS0_ADMA_LCDIF_CS IMX8DXL_SPI3_CS0 5 +#define IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 IMX8DXL_SPI3_CS1 0 +#define IMX8DXL_SPI3_CS1_ADMA_I2C3_SCL IMX8DXL_SPI3_CS1 1 +#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RESET IMX8DXL_SPI3_CS1 2 +#define IMX8DXL_SPI3_CS1_ADMA_SPI2_CS0 IMX8DXL_SPI3_CS1 3 +#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_D16 IMX8DXL_SPI3_CS1 4 +#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RD_E IMX8DXL_SPI3_CS1 5 +#define IMX8DXL_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8DXL_MCLK_IN1 0 +#define IMX8DXL_MCLK_IN1_ADMA_I2C3_SDA IMX8DXL_MCLK_IN1 1 +#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_EN IMX8DXL_MCLK_IN1 2 +#define IMX8DXL_MCLK_IN1_ADMA_SPI2_SCK IMX8DXL_MCLK_IN1 3 +#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D17 IMX8DXL_MCLK_IN1 4 +#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D03 IMX8DXL_MCLK_IN1 5 +#define IMX8DXL_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8DXL_MCLK_IN0 0 +#define IMX8DXL_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8DXL_MCLK_IN0 2 +#define IMX8DXL_MCLK_IN0_ADMA_SPI2_SDI IMX8DXL_MCLK_IN0 3 +#define IMX8DXL_MCLK_IN0_LSIO_GPIO0_IO19 IMX8DXL_MCLK_IN0 4 +#define IMX8DXL_MCLK_IN0_ADMA_LCDIF_RS IMX8DXL_MCLK_IN0 5 +#define IMX8DXL_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8DXL_MCLK_OUT0 0 +#define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_CLK IMX8DXL_MCLK_OUT0 2 +#define IMX8DXL_MCLK_OUT0_ADMA_SPI2_SDO IMX8DXL_MCLK_OUT0 3 +#define IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8DXL_MCLK_OUT0 4 +#define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_WR_RWN IMX8DXL_MCLK_OUT0 5 +#define IMX8DXL_UART1_TX_ADMA_UART1_TX IMX8DXL_UART1_TX 0 +#define IMX8DXL_UART1_TX_LSIO_PWM0_OUT IMX8DXL_UART1_TX 1 +#define IMX8DXL_UART1_TX_LSIO_GPT0_CAPTURE IMX8DXL_UART1_TX 2 +#define IMX8DXL_UART1_TX_LSIO_GPIO0_IO21 IMX8DXL_UART1_TX 4 +#define IMX8DXL_UART1_TX_ADMA_LCDIF_D04 IMX8DXL_UART1_TX 5 +#define IMX8DXL_UART1_RX_ADMA_UART1_RX IMX8DXL_UART1_RX 0 +#define IMX8DXL_UART1_RX_LSIO_PWM1_OUT IMX8DXL_UART1_RX 1 +#define IMX8DXL_UART1_RX_LSIO_GPT0_COMPARE IMX8DXL_UART1_RX 2 +#define IMX8DXL_UART1_RX_LSIO_GPT1_CLK IMX8DXL_UART1_RX 3 +#define IMX8DXL_UART1_RX_LSIO_GPIO0_IO22 IMX8DXL_UART1_RX 4 +#define IMX8DXL_UART1_RX_ADMA_LCDIF_D05 IMX8DXL_UART1_RX 5 +#define IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B IMX8DXL_UART1_RTS_B 0 +#define IMX8DXL_UART1_RTS_B_LSIO_PWM2_OUT IMX8DXL_UART1_RTS_B 1 +#define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D16 IMX8DXL_UART1_RTS_B 2 +#define IMX8DXL_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8DXL_UART1_RTS_B 3 +#define IMX8DXL_UART1_RTS_B_LSIO_GPT0_CLK IMX8DXL_UART1_RTS_B 4 +#define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D06 IMX8DXL_UART1_RTS_B 5 +#define IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B IMX8DXL_UART1_CTS_B 0 +#define IMX8DXL_UART1_CTS_B_LSIO_PWM3_OUT IMX8DXL_UART1_CTS_B 1 +#define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D17 IMX8DXL_UART1_CTS_B 2 +#define IMX8DXL_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8DXL_UART1_CTS_B 3 +#define IMX8DXL_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8DXL_UART1_CTS_B 4 +#define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D07 IMX8DXL_UART1_CTS_B 5 +#define IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK IMX8DXL_SPI0_SCK 0 +#define IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC IMX8DXL_SPI0_SCK 1 +#define IMX8DXL_SPI0_SCK_M40_I2C0_SCL IMX8DXL_SPI0_SCK 2 +#define IMX8DXL_SPI0_SCK_M40_GPIO0_IO00 IMX8DXL_SPI0_SCK 3 +#define IMX8DXL_SPI0_SCK_LSIO_GPIO1_IO04 IMX8DXL_SPI0_SCK 4 +#define IMX8DXL_SPI0_SCK_ADMA_LCDIF_D08 IMX8DXL_SPI0_SCK 5 +#define IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI IMX8DXL_SPI0_SDI 0 +#define IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD IMX8DXL_SPI0_SDI 1 +#define IMX8DXL_SPI0_SDI_M40_TPM0_CH0 IMX8DXL_SPI0_SDI 2 +#define IMX8DXL_SPI0_SDI_M40_GPIO0_IO02 IMX8DXL_SPI0_SDI 3 +#define IMX8DXL_SPI0_SDI_LSIO_GPIO1_IO05 IMX8DXL_SPI0_SDI 4 +#define IMX8DXL_SPI0_SDI_ADMA_LCDIF_D09 IMX8DXL_SPI0_SDI 5 +#define IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO IMX8DXL_SPI0_SDO 0 +#define IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS IMX8DXL_SPI0_SDO 1 +#define IMX8DXL_SPI0_SDO_M40_I2C0_SDA IMX8DXL_SPI0_SDO 2 +#define IMX8DXL_SPI0_SDO_M40_GPIO0_IO01 IMX8DXL_SPI0_SDO 3 +#define IMX8DXL_SPI0_SDO_LSIO_GPIO1_IO06 IMX8DXL_SPI0_SDO 4 +#define IMX8DXL_SPI0_SDO_ADMA_LCDIF_D10 IMX8DXL_SPI0_SDO 5 +#define IMX8DXL_SPI0_CS1_ADMA_SPI0_CS1 IMX8DXL_SPI0_CS1 0 +#define IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC IMX8DXL_SPI0_CS1 1 +#define IMX8DXL_SPI0_CS1_ADMA_SAI1_TXD IMX8DXL_SPI0_CS1 2 +#define IMX8DXL_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8DXL_SPI0_CS1 3 +#define IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 IMX8DXL_SPI0_CS1 4 +#define IMX8DXL_SPI0_CS1_ADMA_LCDIF_D11 IMX8DXL_SPI0_CS1 5 +#define IMX8DXL_SPI0_CS0_ADMA_SPI0_CS0 IMX8DXL_SPI0_CS0 0 +#define IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD IMX8DXL_SPI0_CS0 1 +#define IMX8DXL_SPI0_CS0_M40_TPM0_CH1 IMX8DXL_SPI0_CS0 2 +#define IMX8DXL_SPI0_CS0_M40_GPIO0_IO03 IMX8DXL_SPI0_CS0 3 +#define IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 IMX8DXL_SPI0_CS0 4 +#define IMX8DXL_SPI0_CS0_ADMA_LCDIF_D12 IMX8DXL_SPI0_CS0 5 +#define IMX8DXL_ADC_IN1_ADMA_ADC_IN1 IMX8DXL_ADC_IN1 0 +#define IMX8DXL_ADC_IN1_M40_I2C0_SDA IMX8DXL_ADC_IN1 1 +#define IMX8DXL_ADC_IN1_M40_GPIO0_IO01 IMX8DXL_ADC_IN1 2 +#define IMX8DXL_ADC_IN1_ADMA_I2C0_SDA IMX8DXL_ADC_IN1 3 +#define IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 IMX8DXL_ADC_IN1 4 +#define IMX8DXL_ADC_IN1_ADMA_LCDIF_D13 IMX8DXL_ADC_IN1 5 +#define IMX8DXL_ADC_IN0_ADMA_ADC_IN0 IMX8DXL_ADC_IN0 0 +#define IMX8DXL_ADC_IN0_M40_I2C0_SCL IMX8DXL_ADC_IN0 1 +#define IMX8DXL_ADC_IN0_M40_GPIO0_IO00 IMX8DXL_ADC_IN0 2 +#define IMX8DXL_ADC_IN0_ADMA_I2C0_SCL IMX8DXL_ADC_IN0 3 +#define IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 IMX8DXL_ADC_IN0 4 +#define IMX8DXL_ADC_IN0_ADMA_LCDIF_D14 IMX8DXL_ADC_IN0 5 +#define IMX8DXL_ADC_IN3_ADMA_ADC_IN3 IMX8DXL_ADC_IN3 0 +#define IMX8DXL_ADC_IN3_M40_UART0_TX IMX8DXL_ADC_IN3 1 +#define IMX8DXL_ADC_IN3_M40_GPIO0_IO03 IMX8DXL_ADC_IN3 2 +#define IMX8DXL_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8DXL_ADC_IN3 3 +#define IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 IMX8DXL_ADC_IN3 4 +#define IMX8DXL_ADC_IN3_ADMA_LCDIF_D15 IMX8DXL_ADC_IN3 5 +#define IMX8DXL_ADC_IN2_ADMA_ADC_IN2 IMX8DXL_ADC_IN2 0 +#define IMX8DXL_ADC_IN2_M40_UART0_RX IMX8DXL_ADC_IN2 1 +#define IMX8DXL_ADC_IN2_M40_GPIO0_IO02 IMX8DXL_ADC_IN2 2 +#define IMX8DXL_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8DXL_ADC_IN2 3 +#define IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 IMX8DXL_ADC_IN2 4 +#define IMX8DXL_ADC_IN2_ADMA_LCDIF_D16 IMX8DXL_ADC_IN2 5 +#define IMX8DXL_ADC_IN5_ADMA_ADC_IN5 IMX8DXL_ADC_IN5 0 +#define IMX8DXL_ADC_IN5_M40_TPM0_CH1 IMX8DXL_ADC_IN5 1 +#define IMX8DXL_ADC_IN5_M40_GPIO0_IO05 IMX8DXL_ADC_IN5 2 +#define IMX8DXL_ADC_IN5_ADMA_LCDIF_LCDBUSY IMX8DXL_ADC_IN5 3 +#define IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 IMX8DXL_ADC_IN5 4 +#define IMX8DXL_ADC_IN5_ADMA_LCDIF_D17 IMX8DXL_ADC_IN5 5 +#define IMX8DXL_ADC_IN4_ADMA_ADC_IN4 IMX8DXL_ADC_IN4 0 +#define IMX8DXL_ADC_IN4_M40_TPM0_CH0 IMX8DXL_ADC_IN4 1 +#define IMX8DXL_ADC_IN4_M40_GPIO0_IO04 IMX8DXL_ADC_IN4 2 +#define IMX8DXL_ADC_IN4_ADMA_LCDIF_LCDRESET IMX8DXL_ADC_IN4 3 +#define IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 IMX8DXL_ADC_IN4 4 +#define IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8DXL_FLEXCAN0_RX 0 +#define IMX8DXL_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8DXL_FLEXCAN0_RX 1 +#define IMX8DXL_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8DXL_FLEXCAN0_RX 2 +#define IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8DXL_FLEXCAN0_RX 3 +#define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8DXL_FLEXCAN0_RX 4 +#define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO6_IO08 IMX8DXL_FLEXCAN0_RX 5 +#define IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8DXL_FLEXCAN0_TX 0 +#define IMX8DXL_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8DXL_FLEXCAN0_TX 1 +#define IMX8DXL_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8DXL_FLEXCAN0_TX 2 +#define IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8DXL_FLEXCAN0_TX 3 +#define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8DXL_FLEXCAN0_TX 4 +#define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO6_IO09 IMX8DXL_FLEXCAN0_TX 5 +#define IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8DXL_FLEXCAN1_RX 0 +#define IMX8DXL_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8DXL_FLEXCAN1_RX 1 +#define IMX8DXL_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8DXL_FLEXCAN1_RX 2 +#define IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8DXL_FLEXCAN1_RX 3 +#define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8DXL_FLEXCAN1_RX 4 +#define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO6_IO10 IMX8DXL_FLEXCAN1_RX 5 +#define IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8DXL_FLEXCAN1_TX 0 +#define IMX8DXL_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8DXL_FLEXCAN1_TX 1 +#define IMX8DXL_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8DXL_FLEXCAN1_TX 2 +#define IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8DXL_FLEXCAN1_TX 3 +#define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8DXL_FLEXCAN1_TX 4 +#define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO6_IO11 IMX8DXL_FLEXCAN1_TX 5 +#define IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8DXL_FLEXCAN2_RX 0 +#define IMX8DXL_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8DXL_FLEXCAN2_RX 1 +#define IMX8DXL_FLEXCAN2_RX_ADMA_UART3_RX IMX8DXL_FLEXCAN2_RX 2 +#define IMX8DXL_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8DXL_FLEXCAN2_RX 3 +#define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8DXL_FLEXCAN2_RX 4 +#define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO6_IO12 IMX8DXL_FLEXCAN2_RX 5 +#define IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8DXL_FLEXCAN2_TX 0 +#define IMX8DXL_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8DXL_FLEXCAN2_TX 1 +#define IMX8DXL_FLEXCAN2_TX_ADMA_UART3_TX IMX8DXL_FLEXCAN2_TX 2 +#define IMX8DXL_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8DXL_FLEXCAN2_TX 3 +#define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8DXL_FLEXCAN2_TX 4 +#define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO6_IO13 IMX8DXL_FLEXCAN2_TX 5 +#define IMX8DXL_UART0_RX_ADMA_UART0_RX IMX8DXL_UART0_RX 0 +#define IMX8DXL_UART0_RX_ADMA_MQS_R IMX8DXL_UART0_RX 1 +#define IMX8DXL_UART0_RX_ADMA_FLEXCAN0_RX IMX8DXL_UART0_RX 2 +#define IMX8DXL_UART0_RX_SCU_UART0_RX IMX8DXL_UART0_RX 3 +#define IMX8DXL_UART0_RX_LSIO_GPIO1_IO21 IMX8DXL_UART0_RX 4 +#define IMX8DXL_UART0_RX_LSIO_GPIO6_IO14 IMX8DXL_UART0_RX 5 +#define IMX8DXL_UART0_TX_ADMA_UART0_TX IMX8DXL_UART0_TX 0 +#define IMX8DXL_UART0_TX_ADMA_MQS_L IMX8DXL_UART0_TX 1 +#define IMX8DXL_UART0_TX_ADMA_FLEXCAN0_TX IMX8DXL_UART0_TX 2 +#define IMX8DXL_UART0_TX_SCU_UART0_TX IMX8DXL_UART0_TX 3 +#define IMX8DXL_UART0_TX_LSIO_GPIO1_IO22 IMX8DXL_UART0_TX 4 +#define IMX8DXL_UART0_TX_LSIO_GPIO6_IO15 IMX8DXL_UART0_TX 5 +#define IMX8DXL_UART2_TX_ADMA_UART2_TX IMX8DXL_UART2_TX 0 +#define IMX8DXL_UART2_TX_ADMA_FTM_CH1 IMX8DXL_UART2_TX 1 +#define IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX IMX8DXL_UART2_TX 2 +#define IMX8DXL_UART2_TX_LSIO_GPIO1_IO23 IMX8DXL_UART2_TX 4 +#define IMX8DXL_UART2_TX_LSIO_GPIO6_IO16 IMX8DXL_UART2_TX 5 +#define IMX8DXL_UART2_RX_ADMA_UART2_RX IMX8DXL_UART2_RX 0 +#define IMX8DXL_UART2_RX_ADMA_FTM_CH0 IMX8DXL_UART2_RX 1 +#define IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX IMX8DXL_UART2_RX 2 +#define IMX8DXL_UART2_RX_LSIO_GPIO1_IO24 IMX8DXL_UART2_RX 4 +#define IMX8DXL_UART2_RX_LSIO_GPIO6_IO17 IMX8DXL_UART2_RX 5 +#define IMX8DXL_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8DXL_JTAG_TRST_B 0 +#define IMX8DXL_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8DXL_JTAG_TRST_B 1 +#define IMX8DXL_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8DXL_PMIC_I2C_SCL 0 +#define IMX8DXL_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8DXL_PMIC_I2C_SCL 1 +#define IMX8DXL_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8DXL_PMIC_I2C_SCL 4 +#define IMX8DXL_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8DXL_PMIC_I2C_SDA 0 +#define IMX8DXL_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8DXL_PMIC_I2C_SDA 1 +#define IMX8DXL_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8DXL_PMIC_I2C_SDA 4 +#define IMX8DXL_PMIC_INT_B_SCU_DSC_PMIC_INT_B IMX8DXL_PMIC_INT_B 0 +#define IMX8DXL_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8DXL_SCU_GPIO0_00 0 +#define IMX8DXL_SCU_GPIO0_00_SCU_UART0_RX IMX8DXL_SCU_GPIO0_00 1 +#define IMX8DXL_SCU_GPIO0_00_M40_UART0_RX IMX8DXL_SCU_GPIO0_00 2 +#define IMX8DXL_SCU_GPIO0_00_ADMA_UART3_RX IMX8DXL_SCU_GPIO0_00 3 +#define IMX8DXL_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8DXL_SCU_GPIO0_00 4 +#define IMX8DXL_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8DXL_SCU_GPIO0_01 0 +#define IMX8DXL_SCU_GPIO0_01_SCU_UART0_TX IMX8DXL_SCU_GPIO0_01 1 +#define IMX8DXL_SCU_GPIO0_01_M40_UART0_TX IMX8DXL_SCU_GPIO0_01 2 +#define IMX8DXL_SCU_GPIO0_01_ADMA_UART3_TX IMX8DXL_SCU_GPIO0_01 3 +#define IMX8DXL_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8DXL_SCU_GPIO0_01 4 +#define IMX8DXL_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY IMX8DXL_SCU_PMIC_STANDBY 0 +#define IMX8DXL_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8DXL_SCU_BOOT_MODE1 0 +#define IMX8DXL_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8DXL_SCU_BOOT_MODE0 0 +#define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8DXL_SCU_BOOT_MODE2 0 +#define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8DXL_SCU_BOOT_MODE2 1 +#define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN IMX8DXL_SNVS_TAMPER_OUT1 4 +#define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO6_IO19_IN IMX8DXL_SNVS_TAMPER_OUT1 5 +#define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN IMX8DXL_SNVS_TAMPER_OUT2 4 +#define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO6_IO20_IN IMX8DXL_SNVS_TAMPER_OUT2 5 +#define IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC IMX8DXL_SNVS_TAMPER_OUT3 2 +#define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO2_IO07_IN IMX8DXL_SNVS_TAMPER_OUT3 4 +#define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO6_IO21_IN IMX8DXL_SNVS_TAMPER_OUT3 5 +#define IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD IMX8DXL_SNVS_TAMPER_OUT4 2 +#define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN IMX8DXL_SNVS_TAMPER_OUT4 4 +#define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO6_IO22_IN IMX8DXL_SNVS_TAMPER_OUT4 5 +#define IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS IMX8DXL_SNVS_TAMPER_IN0 2 +#define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN IMX8DXL_SNVS_TAMPER_IN0 4 +#define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO6_IO23_IN IMX8DXL_SNVS_TAMPER_IN0 5 +#define IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC IMX8DXL_SNVS_TAMPER_IN1 2 +#define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN IMX8DXL_SNVS_TAMPER_IN1 4 +#define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO6_IO24_IN IMX8DXL_SNVS_TAMPER_IN1 5 +#define IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD IMX8DXL_SNVS_TAMPER_IN2 2 +#define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN IMX8DXL_SNVS_TAMPER_IN2 4 +#define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO6_IO25_IN IMX8DXL_SNVS_TAMPER_IN2 5 +#define IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS IMX8DXL_SNVS_TAMPER_IN3 2 +#define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO2_IO12_IN IMX8DXL_SNVS_TAMPER_IN3 4 +#define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO6_IO26_IN IMX8DXL_SNVS_TAMPER_IN3 5 +#define IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA IMX8DXL_SPI1_SCK 2 +#define IMX8DXL_SPI1_SCK_ADMA_SPI1_SCK IMX8DXL_SPI1_SCK 3 +#define IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 IMX8DXL_SPI1_SCK 4 +#define IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL IMX8DXL_SPI1_SDO 2 +#define IMX8DXL_SPI1_SDO_ADMA_SPI1_SDO IMX8DXL_SPI1_SDO 3 +#define IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 IMX8DXL_SPI1_SDO 4 +#define IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL IMX8DXL_SPI1_SDI 2 +#define IMX8DXL_SPI1_SDI_ADMA_SPI1_SDI IMX8DXL_SPI1_SDI 3 +#define IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 IMX8DXL_SPI1_SDI 4 +#define IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA IMX8DXL_SPI1_CS0 2 +#define IMX8DXL_SPI1_CS0_ADMA_SPI1_CS0 IMX8DXL_SPI1_CS0 3 +#define IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 IMX8DXL_SPI1_CS0 4 +#define IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8DXL_QSPI0A_DATA1 0 +#define IMX8DXL_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8DXL_QSPI0A_DATA1 4 +#define IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8DXL_QSPI0A_DATA0 0 +#define IMX8DXL_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8DXL_QSPI0A_DATA0 4 +#define IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8DXL_QSPI0A_DATA3 0 +#define IMX8DXL_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8DXL_QSPI0A_DATA3 4 +#define IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8DXL_QSPI0A_DATA2 0 +#define IMX8DXL_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8DXL_QSPI0A_DATA2 4 +#define IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8DXL_QSPI0A_SS0_B 0 +#define IMX8DXL_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8DXL_QSPI0A_SS0_B 4 +#define IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8DXL_QSPI0A_DQS 0 +#define IMX8DXL_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8DXL_QSPI0A_DQS 4 +#define IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8DXL_QSPI0A_SCLK 0 +#define IMX8DXL_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8DXL_QSPI0A_SCLK 4 +#define IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8DXL_QSPI0B_SCLK 0 +#define IMX8DXL_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8DXL_QSPI0B_SCLK 4 +#define IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8DXL_QSPI0B_DQS 0 +#define IMX8DXL_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8DXL_QSPI0B_DQS 4 +#define IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8DXL_QSPI0B_DATA1 0 +#define IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8DXL_QSPI0B_DATA1 4 +#define IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8DXL_QSPI0B_DATA0 0 +#define IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8DXL_QSPI0B_DATA0 4 +#define IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8DXL_QSPI0B_DATA3 0 +#define IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8DXL_QSPI0B_DATA3 4 +#define IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8DXL_QSPI0B_DATA2 0 +#define IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8DXL_QSPI0B_DATA2 4 +#define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8DXL_QSPI0B_SS0_B 0 +#define IMX8DXL_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8DXL_QSPI0B_SS0_B 4 +#define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0A_SS1_B IMX8DXL_QSPI0B_SS0_B 5 + +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO_PAD IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0 + +#endif diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h index 6d6bac1c26d7..5f291045e8fd 100644 --- a/include/dt-bindings/pinctrl/rockchip.h +++ b/include/dt-bindings/pinctrl/rockchip.h @@ -9,13 +9,6 @@ #ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ #define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__ -#define RK_GPIO0 0 -#define RK_GPIO1 1 -#define RK_GPIO2 2 -#define RK_GPIO3 3 -#define RK_GPIO4 4 -#define RK_GPIO6 6 - #define RK_PA0 0 #define RK_PA1 1 #define RK_PA2 2 @@ -50,9 +43,5 @@ #define RK_PD7 31 #define RK_FUNC_GPIO 0 -#define RK_FUNC_1 1 /* deprecated */ -#define RK_FUNC_2 2 /* deprecated */ -#define RK_FUNC_3 3 /* deprecated */ -#define RK_FUNC_4 4 /* deprecated */ #endif diff --git a/include/dt-bindings/power/marvell,mmp2.h b/include/dt-bindings/power/marvell,mmp2.h new file mode 100644 index 000000000000..c53d2b3e1057 --- /dev/null +++ b/include/dt-bindings/power/marvell,mmp2.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DTS_MARVELL_MMP2_POWER_H +#define __DTS_MARVELL_MMP2_POWER_H + +#define MMP2_POWER_DOMAIN_GPU 0 +#define MMP2_POWER_DOMAIN_AUDIO 1 +#define MMP3_POWER_DOMAIN_CAMERA 2 + +#define MMP2_NR_POWER_DOMAINS 3 + +#endif diff --git a/include/dt-bindings/power/meson-gxbb-power.h b/include/dt-bindings/power/meson-gxbb-power.h new file mode 100644 index 000000000000..1262dac696c0 --- /dev/null +++ b/include/dt-bindings/power/meson-gxbb-power.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + */ + +#ifndef _DT_BINDINGS_MESON_GXBB_POWER_H +#define _DT_BINDINGS_MESON_GXBB_POWER_H + +#define PWRC_GXBB_VPU_ID 0 +#define PWRC_GXBB_ETHERNET_MEM_ID 1 + +#endif diff --git a/include/dt-bindings/power/meson8-power.h b/include/dt-bindings/power/meson8-power.h new file mode 100644 index 000000000000..dd8b2ddb82a7 --- /dev/null +++ b/include/dt-bindings/power/meson8-power.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2019 Martin Blumenstingl + */ + +#ifndef _DT_BINDINGS_MESON8_POWER_H +#define _DT_BINDINGS_MESON8_POWER_H + +#define PWRC_MESON8_VPU_ID 0 +#define PWRC_MESON8_ETHERNET_MEM_ID 1 +#define PWRC_MESON8_AUDIO_DSP_MEM_ID 2 + +#endif /* _DT_BINDINGS_MESON8_POWER_H */ diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 3f74096d5a7c..dc146e44228b 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -28,6 +28,18 @@ #define SM8150_MMCX 9 #define SM8150_MMCX_AO 10 +/* SM8250 Power Domain Indexes */ +#define SM8250_CX 0 +#define SM8250_CX_AO 1 +#define SM8250_EBI 2 +#define SM8250_GFX 3 +#define SM8250_LCX 4 +#define SM8250_LMX 5 +#define SM8250_MMCX 6 +#define SM8250_MMCX_AO 7 +#define SM8250_MX 8 +#define SM8250_MX_AO 9 + /* SC7180 Power Domain Indexes */ #define SC7180_CX 0 #define SC7180_CX_AO 1 diff --git a/include/dt-bindings/power/r8a7742-sysc.h b/include/dt-bindings/power/r8a7742-sysc.h new file mode 100644 index 000000000000..1b1bd3cf95db --- /dev/null +++ b/include/dt-bindings/power/r8a7742-sysc.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A7742_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7742_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7742_PD_CA15_CPU0 0 +#define R8A7742_PD_CA15_CPU1 1 +#define R8A7742_PD_CA15_CPU2 2 +#define R8A7742_PD_CA15_CPU3 3 +#define R8A7742_PD_CA7_CPU0 5 +#define R8A7742_PD_CA7_CPU1 6 +#define R8A7742_PD_CA7_CPU2 7 +#define R8A7742_PD_CA7_CPU3 8 +#define R8A7742_PD_CA15_SCU 12 +#define R8A7742_PD_RGX 20 +#define R8A7742_PD_CA7_SCU 21 + +/* Always-on power area */ +#define R8A7742_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7742_SYSC_H__ */ diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h index ea5058618863..883bfd3bcbad 100644 --- a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h +++ b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h @@ -69,7 +69,7 @@ #define RESET_SYS_CPU_L2 58 #define RESET_SYS_CPU_P 59 #define RESET_SYS_CPU_MBIST 60 -/* 61 */ +#define RESET_ACODEC 61 /* 62 */ /* 63 */ /* RESET2 */ diff --git a/include/dt-bindings/reset/bt1-ccu.h b/include/dt-bindings/reset/bt1-ccu.h new file mode 100644 index 000000000000..3578e83026bc --- /dev/null +++ b/include/dt-bindings/reset/bt1-ccu.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC + * + * Baikal-T1 CCU reset indices + */ +#ifndef __DT_BINDINGS_RESET_BT1_CCU_H +#define __DT_BINDINGS_RESET_BT1_CCU_H + +#define CCU_AXI_MAIN_RST 0 +#define CCU_AXI_DDR_RST 1 +#define CCU_AXI_SATA_RST 2 +#define CCU_AXI_GMAC0_RST 3 +#define CCU_AXI_GMAC1_RST 4 +#define CCU_AXI_XGMAC_RST 5 +#define CCU_AXI_PCIE_M_RST 6 +#define CCU_AXI_PCIE_S_RST 7 +#define CCU_AXI_USB_RST 8 +#define CCU_AXI_HWA_RST 9 +#define CCU_AXI_SRAM_RST 10 + +#define CCU_SYS_SATA_REF_RST 0 +#define CCU_SYS_APB_RST 1 + +#endif /* __DT_BINDINGS_RESET_BT1_CCU_H */ diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h new file mode 100644 index 000000000000..2e8c9104b666 --- /dev/null +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 NXP + */ + +#ifndef DT_BINDING_RESET_IMX8MP_H +#define DT_BINDING_RESET_IMX8MP_H + +#define IMX8MP_RESET_A53_CORE_POR_RESET0 0 +#define IMX8MP_RESET_A53_CORE_POR_RESET1 1 +#define IMX8MP_RESET_A53_CORE_POR_RESET2 2 +#define IMX8MP_RESET_A53_CORE_POR_RESET3 3 +#define IMX8MP_RESET_A53_CORE_RESET0 4 +#define IMX8MP_RESET_A53_CORE_RESET1 5 +#define IMX8MP_RESET_A53_CORE_RESET2 6 +#define IMX8MP_RESET_A53_CORE_RESET3 7 +#define IMX8MP_RESET_A53_DBG_RESET0 8 +#define IMX8MP_RESET_A53_DBG_RESET1 9 +#define IMX8MP_RESET_A53_DBG_RESET2 10 +#define IMX8MP_RESET_A53_DBG_RESET3 11 +#define IMX8MP_RESET_A53_ETM_RESET0 12 +#define IMX8MP_RESET_A53_ETM_RESET1 13 +#define IMX8MP_RESET_A53_ETM_RESET2 14 +#define IMX8MP_RESET_A53_ETM_RESET3 15 +#define IMX8MP_RESET_A53_SOC_DBG_RESET 16 +#define IMX8MP_RESET_A53_L2RESET 17 +#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18 +#define IMX8MP_RESET_OTG1_PHY_RESET 19 +#define IMX8MP_RESET_OTG2_PHY_RESET 20 +#define IMX8MP_RESET_SUPERMIX_RESET 21 +#define IMX8MP_RESET_AUDIOMIX_RESET 22 +#define IMX8MP_RESET_MLMIX_RESET 23 +#define IMX8MP_RESET_PCIEPHY 24 +#define IMX8MP_RESET_PCIEPHY_PERST 25 +#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26 +#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27 +#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28 +#define IMX8MP_RESET_MEDIA_RESET 29 +#define IMX8MP_RESET_GPU2D_RESET 30 +#define IMX8MP_RESET_GPU3D_RESET 31 +#define IMX8MP_RESET_GPU_RESET 32 +#define IMX8MP_RESET_VPU_RESET 33 +#define IMX8MP_RESET_VPU_G1_RESET 34 +#define IMX8MP_RESET_VPU_G2_RESET 35 +#define IMX8MP_RESET_VPUVC8KE_RESET 36 +#define IMX8MP_RESET_NOC_RESET 37 + +#define IMX8MP_RESET_NUM 38 + +#endif diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h index 9a301082d361..a5b570737582 100644 --- a/include/dt-bindings/reset/imx8mq-reset.h +++ b/include/dt-bindings/reset/imx8mq-reset.h @@ -28,36 +28,36 @@ #define IMX8MQ_RESET_A53_L2RESET 17 #define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 #define IMX8MQ_RESET_OTG1_PHY_RESET 19 -#define IMX8MQ_RESET_OTG2_PHY_RESET 20 -#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 -#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 -#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 -#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 -#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 -#define IMX8MQ_RESET_PCIEPHY 26 -#define IMX8MQ_RESET_PCIEPHY_PERST 27 -#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 -#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 -#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */ #define IMX8MQ_RESET_DISP_RESET 31 #define IMX8MQ_RESET_GPU_RESET 32 -#define IMX8MQ_RESET_VPU_RESET 33 -#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC1_PRST 44 -#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 -#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 -#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */ -#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */ +#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */ #define IMX8MQ_RESET_NUM 50 diff --git a/include/dt-bindings/reset/qcom,gcc-msm8939.h b/include/dt-bindings/reset/qcom,gcc-msm8939.h new file mode 100644 index 000000000000..fa41ffeae7a2 --- /dev/null +++ b/include/dt-bindings/reset/qcom,gcc-msm8939.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_MSM_GCC_8939_H +#define _DT_BINDINGS_RESET_MSM_GCC_8939_H + +#define GCC_BLSP1_BCR 0 +#define GCC_BLSP1_QUP1_BCR 1 +#define GCC_BLSP1_UART1_BCR 2 +#define GCC_BLSP1_QUP2_BCR 3 +#define GCC_BLSP1_UART2_BCR 4 +#define GCC_BLSP1_QUP3_BCR 5 +#define GCC_BLSP1_QUP4_BCR 6 +#define GCC_BLSP1_QUP5_BCR 7 +#define GCC_BLSP1_QUP6_BCR 8 +#define GCC_IMEM_BCR 9 +#define GCC_SMMU_BCR 10 +#define GCC_APSS_TCU_BCR 11 +#define GCC_SMMU_XPU_BCR 12 +#define GCC_PCNOC_TBU_BCR 13 +#define GCC_PRNG_BCR 14 +#define GCC_BOOT_ROM_BCR 15 +#define GCC_CRYPTO_BCR 16 +#define GCC_SEC_CTRL_BCR 17 +#define GCC_AUDIO_CORE_BCR 18 +#define GCC_ULT_AUDIO_BCR 19 +#define GCC_DEHR_BCR 20 +#define GCC_SYSTEM_NOC_BCR 21 +#define GCC_PCNOC_BCR 22 +#define GCC_TCSR_BCR 23 +#define GCC_QDSS_BCR 24 +#define GCC_DCD_BCR 25 +#define GCC_MSG_RAM_BCR 26 +#define GCC_MPM_BCR 27 +#define GCC_SPMI_BCR 28 +#define GCC_SPDM_BCR 29 +#define GCC_MM_SPDM_BCR 30 +#define GCC_BIMC_BCR 31 +#define GCC_RBCPR_BCR 32 +#define GCC_TLMM_BCR 33 +#define GCC_USB_HS_BCR 34 +#define GCC_USB2A_PHY_BCR 35 +#define GCC_SDCC1_BCR 36 +#define GCC_SDCC2_BCR 37 +#define GCC_PDM_BCR 38 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 39 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 +#define GCC_MMSS_BCR 50 +#define GCC_VENUS0_BCR 51 +#define GCC_MDSS_BCR 52 +#define GCC_CAMSS_PHY0_BCR 53 +#define GCC_CAMSS_CSI0_BCR 54 +#define GCC_CAMSS_CSI0PHY_BCR 55 +#define GCC_CAMSS_CSI0RDI_BCR 56 +#define GCC_CAMSS_CSI0PIX_BCR 57 +#define GCC_CAMSS_PHY1_BCR 58 +#define GCC_CAMSS_CSI1_BCR 59 +#define GCC_CAMSS_CSI1PHY_BCR 60 +#define GCC_CAMSS_CSI1RDI_BCR 61 +#define GCC_CAMSS_CSI1PIX_BCR 62 +#define GCC_CAMSS_ISPIF_BCR 63 +#define GCC_CAMSS_CCI_BCR 64 +#define GCC_CAMSS_MCLK0_BCR 65 +#define GCC_CAMSS_MCLK1_BCR 66 +#define GCC_CAMSS_GP0_BCR 67 +#define GCC_CAMSS_GP1_BCR 68 +#define GCC_CAMSS_TOP_BCR 69 +#define GCC_CAMSS_MICRO_BCR 70 +#define GCC_CAMSS_JPEG_BCR 71 +#define GCC_CAMSS_VFE_BCR 72 +#define GCC_CAMSS_CSI_VFE0_BCR 73 +#define GCC_OXILI_BCR 74 +#define GCC_GMEM_BCR 75 +#define GCC_CAMSS_AHB_BCR 76 +#define GCC_MDP_TBU_BCR 77 +#define GCC_GFX_TBU_BCR 78 +#define GCC_GFX_TCU_BCR 79 +#define GCC_MSS_TBU_AXI_BCR 80 +#define GCC_MSS_TBU_GSS_AXI_BCR 81 +#define GCC_MSS_TBU_Q6_AXI_BCR 82 +#define GCC_GTCU_AHB_BCR 83 +#define GCC_SMMU_CFG_BCR 84 +#define GCC_VFE_TBU_BCR 85 +#define GCC_VENUS_TBU_BCR 86 +#define GCC_JPEG_TBU_BCR 87 +#define GCC_PRONTO_TBU_BCR 88 +#define GCC_SMMU_CATS_BCR 89 +#define GCC_BLSP1_UART3_BCR 90 +#define GCC_CAMSS_CSI2_BCR 91 +#define GCC_CAMSS_CSI2PHY_BCR 92 +#define GCC_CAMSS_CSI2RDI_BCR 93 +#define GCC_CAMSS_CSI2PIX_BCR 94 +#define GCC_USB_FS_BCR 95 +#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 96 +#define GCC_CAMSS_MCLK2_BCR 97 +#define GCC_CPP_TBU_BCR 98 +#define GCC_MDP_RT_TBU_BCR 99 + +#endif diff --git a/include/dt-bindings/reset/realtek,rtd1195.h b/include/dt-bindings/reset/realtek,rtd1195.h new file mode 100644 index 000000000000..27902abf935b --- /dev/null +++ b/include/dt-bindings/reset/realtek,rtd1195.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +/* + * Realtek RTD1195 reset controllers + * + * Copyright (c) 2017 Andreas Färber + */ +#ifndef DT_BINDINGS_RESET_RTD1195_H +#define DT_BINDINGS_RESET_RTD1195_H + +/* soft reset 1 */ +#define RTD1195_RSTN_MISC 0 +#define RTD1195_RSTN_RNG 1 +#define RTD1195_RSTN_USB3_POW 2 +#define RTD1195_RSTN_GSPI 3 +#define RTD1195_RSTN_USB3_P0_MDIO 4 +#define RTD1195_RSTN_VE_H265 5 +#define RTD1195_RSTN_USB 6 +#define RTD1195_RSTN_USB_PHY0 8 +#define RTD1195_RSTN_USB_PHY1 9 +#define RTD1195_RSTN_HDMIRX 11 +#define RTD1195_RSTN_HDMI 12 +#define RTD1195_RSTN_ETN 14 +#define RTD1195_RSTN_AIO 15 +#define RTD1195_RSTN_GPU 16 +#define RTD1195_RSTN_VE_H264 17 +#define RTD1195_RSTN_VE_JPEG 18 +#define RTD1195_RSTN_TVE 19 +#define RTD1195_RSTN_VO 20 +#define RTD1195_RSTN_LVDS 21 +#define RTD1195_RSTN_SE 22 +#define RTD1195_RSTN_DCU 23 +#define RTD1195_RSTN_DC_PHY 24 +#define RTD1195_RSTN_CP 25 +#define RTD1195_RSTN_MD 26 +#define RTD1195_RSTN_TP 27 +#define RTD1195_RSTN_AE 28 +#define RTD1195_RSTN_NF 29 +#define RTD1195_RSTN_MIPI 30 + +/* soft reset 2 */ +#define RTD1195_RSTN_ACPU 0 +#define RTD1195_RSTN_VCPU 1 +#define RTD1195_RSTN_PCR 9 +#define RTD1195_RSTN_CR 10 +#define RTD1195_RSTN_EMMC 11 +#define RTD1195_RSTN_SDIO 12 +#define RTD1195_RSTN_I2C_5 18 +#define RTD1195_RSTN_RTC 20 +#define RTD1195_RSTN_I2C_4 23 +#define RTD1195_RSTN_I2C_3 24 +#define RTD1195_RSTN_I2C_2 25 +#define RTD1195_RSTN_I2C_1 26 +#define RTD1195_RSTN_UR1 28 + +/* soft reset 3 */ +#define RTD1195_RSTN_SB2 0 + +/* iso soft reset */ +#define RTD1195_ISO_RSTN_VFD 0 +#define RTD1195_ISO_RSTN_IR 1 +#define RTD1195_ISO_RSTN_CEC0 2 +#define RTD1195_ISO_RSTN_CEC1 3 +#define RTD1195_ISO_RSTN_DP 4 +#define RTD1195_ISO_RSTN_CBUSTX 5 +#define RTD1195_ISO_RSTN_CBUSRX 6 +#define RTD1195_ISO_RSTN_EFUSE 7 +#define RTD1195_ISO_RSTN_UR0 8 +#define RTD1195_ISO_RSTN_GMAC 9 +#define RTD1195_ISO_RSTN_GPHY 10 +#define RTD1195_ISO_RSTN_I2C_0 11 +#define RTD1195_ISO_RSTN_I2C_6 12 +#define RTD1195_ISO_RSTN_CBUS 13 + +#endif diff --git a/include/dt-bindings/reset/realtek,rtd1295.h b/include/dt-bindings/reset/realtek,rtd1295.h index 2c0cb6afe816..dd89e4c80264 100644 --- a/include/dt-bindings/reset/realtek,rtd1295.h +++ b/include/dt-bindings/reset/realtek,rtd1295.h @@ -75,6 +75,9 @@ #define RTD1295_RSTN_CBUS_TX 30 #define RTD1295_RSTN_SDS_PHY 31 +/* soft reset 3 */ +#define RTD1295_RSTN_SB2 0 + /* soft reset 4 */ #define RTD1295_RSTN_DCPHY_CRT 0 #define RTD1295_RSTN_DCPHY_ALERT_RX 1 diff --git a/src/arm/am335x-baltos.dtsi b/src/arm/am335x-baltos.dtsi index 05e7b5d4a95b..04f0b1227efe 100644 --- a/src/arm/am335x-baltos.dtsi +++ b/src/arm/am335x-baltos.dtsi @@ -369,7 +369,7 @@ &mmc2 { status = "okay"; vmmc-supply = <&wl12xx_vmmc>; - ti,non-removable; + non-removable; bus-width = <4>; cap-power-off-card; pinctrl-names = "default"; diff --git a/src/arm/am335x-boneblack-common.dtsi b/src/arm/am335x-boneblack-common.dtsi index 91f93bc89716..dd932220a8bf 100644 --- a/src/arm/am335x-boneblack-common.dtsi +++ b/src/arm/am335x-boneblack-common.dtsi @@ -22,6 +22,7 @@ pinctrl-0 = <&emmc_pins>; bus-width = <8>; status = "okay"; + non-removable; }; &am33xx_pinmux { diff --git a/src/arm/am335x-boneblack-wireless.dts b/src/arm/am335x-boneblack-wireless.dts index 3124d94c0b3c..e07dd7979586 100644 --- a/src/arm/am335x-boneblack-wireless.dts +++ b/src/arm/am335x-boneblack-wireless.dts @@ -75,7 +75,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - ti,needs-special-hs-handling; keep-power-in-suspend; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins &wl18xx_pins>; diff --git a/src/arm/am335x-boneblue.dts b/src/arm/am335x-boneblue.dts index 5811fb8d4fdf..83f9452c9cd3 100644 --- a/src/arm/am335x-boneblue.dts +++ b/src/arm/am335x-boneblue.dts @@ -367,7 +367,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - ti,needs-special-hs-handling; keep-power-in-suspend; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins &wl18xx_pins>; diff --git a/src/arm/am335x-bonegreen-wireless.dts b/src/arm/am335x-bonegreen-wireless.dts index 4092cd193b8a..609c8db687ec 100644 --- a/src/arm/am335x-bonegreen-wireless.dts +++ b/src/arm/am335x-bonegreen-wireless.dts @@ -75,7 +75,6 @@ bus-width = <4>; non-removable; cap-power-off-card; - ti,needs-special-hs-handling; keep-power-in-suspend; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins &wl18xx_pins>; diff --git a/src/arm/am335x-evm.dts b/src/arm/am335x-evm.dts index 68252dab32c3..a4fc6b168a85 100644 --- a/src/arm/am335x-evm.dts +++ b/src/arm/am335x-evm.dts @@ -743,8 +743,7 @@ bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc3_pins &wlan_pins>; - ti,non-removable; - ti,needs-special-hs-handling; + non-removable; cap-power-off-card; keep-power-in-suspend; diff --git a/src/arm/am335x-evmsk.dts b/src/arm/am335x-evmsk.dts index 32f515a295ee..78b6e1f594c9 100644 --- a/src/arm/am335x-evmsk.dts +++ b/src/arm/am335x-evmsk.dts @@ -655,7 +655,7 @@ &mmc2 { status = "okay"; vmmc-supply = <&wl12xx_vmmc>; - ti,non-removable; + non-removable; bus-width = <4>; cap-power-off-card; keep-power-in-suspend; diff --git a/src/arm/am335x-guardian.dts b/src/arm/am335x-guardian.dts index 81e0f63e94d3..0ebe9e2c150e 100644 --- a/src/arm/am335x-guardian.dts +++ b/src/arm/am335x-guardian.dts @@ -105,6 +105,7 @@ ti,timers = <&timer7>; pinctrl-names = "default"; pinctrl-0 = <&dmtimer7_pins>; + ti,clock-source = <0x01>; }; vmmcsd_fixed: regulator-3v3 { diff --git a/src/arm/am335x-lxm.dts b/src/arm/am335x-lxm.dts index fef582852820..dbedf729205c 100644 --- a/src/arm/am335x-lxm.dts +++ b/src/arm/am335x-lxm.dts @@ -339,7 +339,7 @@ pinctrl-0 = <&emmc_pins>; vmmc-supply = <&vmmcsd_fixed>; bus-width = <8>; - ti,non-removable; + non-removable; status = "okay"; }; diff --git a/src/arm/am335x-moxa-uc-2100-common.dtsi b/src/arm/am335x-moxa-uc-2100-common.dtsi index 6495a125c01f..4e90f9c23d2e 100644 --- a/src/arm/am335x-moxa-uc-2100-common.dtsi +++ b/src/arm/am335x-moxa-uc-2100-common.dtsi @@ -159,7 +159,7 @@ vmmc-supply = <&vmmcsd_fixed>; bus-width = <8>; pinctrl-0 = <&mmc1_pins_default>; - ti,non-removable; + non-removable; status = "okay"; }; diff --git a/src/arm/am335x-moxa-uc-8100-me-t.dts b/src/arm/am335x-moxa-uc-8100-me-t.dts index 244df9c5a537..f03e72cada41 100644 --- a/src/arm/am335x-moxa-uc-8100-me-t.dts +++ b/src/arm/am335x-moxa-uc-8100-me-t.dts @@ -451,7 +451,7 @@ vmmc-supply = <&vmmcsd_fixed>; bus-width = <8>; pinctrl-0 = <&mmc2_pins_default>; - ti,non-removable; + non-removable; status = "okay"; }; diff --git a/src/arm/am335x-pepper.dts b/src/arm/am335x-pepper.dts index 6d7608d9377b..f9a027b47962 100644 --- a/src/arm/am335x-pepper.dts +++ b/src/arm/am335x-pepper.dts @@ -341,7 +341,7 @@ pinctrl-0 = <&emmc_pins>; vmmc-supply = <&ldo3_reg>; bus-width = <8>; - ti,non-removable; + non-removable; }; &mmc3 { @@ -351,7 +351,7 @@ pinctrl-0 = <&wireless_pins>; vmmmc-supply = <&v3v3c_reg>; bus-width = <4>; - ti,non-removable; + non-removable; dmas = <&edma_xbar 12 0 1 &edma_xbar 13 0 2>; dma-names = "tx", "rx"; diff --git a/src/arm/am335x-phycore-som.dtsi b/src/arm/am335x-phycore-som.dtsi index 3d0672b53d77..7e46b4c02709 100644 --- a/src/arm/am335x-phycore-som.dtsi +++ b/src/arm/am335x-phycore-som.dtsi @@ -69,7 +69,7 @@ pinctrl-0 = <&emmc_pins>; vmmc-supply = <&vmmc_reg>; bus-width = <8>; - ti,non-removable; + non-removable; status = "disabled"; }; diff --git a/src/arm/am335x-pocketbeagle.dts b/src/arm/am335x-pocketbeagle.dts index 4da719098028..f0b222201b86 100644 --- a/src/arm/am335x-pocketbeagle.dts +++ b/src/arm/am335x-pocketbeagle.dts @@ -88,7 +88,6 @@ AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* (B12) mcasp0_aclkr.mmc0_sdwp */ >; }; diff --git a/src/arm/am33xx-l4.dtsi b/src/arm/am33xx-l4.dtsi index 5ed7f3c58c0f..a9cbefc80c0c 100644 --- a/src/arm/am33xx-l4.dtsi +++ b/src/arm/am33xx-l4.dtsi @@ -330,9 +330,8 @@ }; }; - target-module@31000 { /* 0x44e31000, ap 25 40.0 */ + timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */ compatible = "ti,sysc-omap2-timer", "ti,sysc"; - ti,hwmods = "timer1"; reg = <0x31000 0x4>, <0x31010 0x4>, <0x31014 0x4>; @@ -1117,9 +1116,8 @@ }; }; - target-module@40000 { /* 0x48040000, ap 22 1e.0 */ + timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer2"; reg = <0x40000 0x4>, <0x40010 0x4>, <0x40014 0x4>; @@ -1337,10 +1335,8 @@ ranges = <0x0 0x60000 0x1000>; mmc1: mmc@0 { - compatible = "ti,omap4-hsmmc"; - ti,dual-volt; + compatible = "ti,am335-sdhci"; ti,needs-special-reset; - ti,needs-special-hs-handling; dmas = <&edma_xbar 24 0 0 &edma_xbar 25 0 0>; dma-names = "tx", "rx"; @@ -1818,7 +1814,7 @@ ranges = <0x0 0xd8000 0x1000>; mmc2: mmc@0 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,am335-sdhci"; ti,needs-special-reset; dmas = <&edma 2 0 &edma 3 0>; diff --git a/src/arm/am33xx.dtsi b/src/arm/am33xx.dtsi index a35f5052d76f..5fdce106edbb 100644 --- a/src/arm/am33xx.dtsi +++ b/src/arm/am33xx.dtsi @@ -322,10 +322,11 @@ ranges = <0x0 0x47810000 0x1000>; mmc3: mmc@0 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,am335-sdhci"; ti,needs-special-reset; interrupts = <29>; reg = <0x0 0x1000>; + status = "disabled"; }; }; @@ -335,7 +336,7 @@ <0x47400010 0x4>; reg-names = "rev", "sysc"; ti,sysc-mask = <(SYSC_OMAP4_FREEEMU | - SYSC_OMAP2_SOFTRESET)>; + SYSC_OMAP4_SOFTRESET)>; ti,sysc-midle = , , ; @@ -347,7 +348,7 @@ clock-names = "fck"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x47400000 0x5000>; + ranges = <0x0 0x47400000 0x8000>; usb0_phy: usb-phy@1300 { compatible = "ti,am335x-usb-phy"; @@ -619,3 +620,23 @@ #reset-cells = <1>; }; }; + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; diff --git a/src/arm/am3517-evm.dts b/src/arm/am3517-evm.dts index a1fd3e63e86e..92466b9eb6ba 100644 --- a/src/arm/am3517-evm.dts +++ b/src/arm/am3517-evm.dts @@ -156,6 +156,7 @@ pinctrl-0 = <&pwm_pins>; ti,timers = <&timer11>; #pwm-cells = <3>; + ti,clock-source = <0x01>; }; /* HS USB Host PHY on PORT 1 */ diff --git a/src/arm/am3517.dtsi b/src/arm/am3517.dtsi index e0b5a00e2078..dc8927f14b6c 100644 --- a/src/arm/am3517.dtsi +++ b/src/arm/am3517.dtsi @@ -169,5 +169,25 @@ status = "disabled"; }; -/include/ "am35xx-clocks.dtsi" -/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" +#include "am35xx-clocks.dtsi" +#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt2_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; diff --git a/src/arm/am4372.dtsi b/src/arm/am4372.dtsi index dba87bfaf33e..51ad9e881a62 100644 --- a/src/arm/am4372.dtsi +++ b/src/arm/am4372.dtsi @@ -316,10 +316,11 @@ ranges = <0x0 0x47810000 0x1000>; mmc3: mmc@0 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,am437-sdhci"; ti,needs-special-reset; interrupts = ; reg = <0x0 0x1000>; + status = "disabled"; }; }; @@ -553,3 +554,23 @@ #reset-cells = <1>; }; }; + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; diff --git a/src/arm/am437x-cm-t43.dts b/src/arm/am437x-cm-t43.dts index 063113a5da2d..a6b4fca8626a 100644 --- a/src/arm/am437x-cm-t43.dts +++ b/src/arm/am437x-cm-t43.dts @@ -291,7 +291,7 @@ pinctrl-0 = <&emmc_pins>; vmmc-supply = <&vmmc_3v3>; bus-width = <8>; - ti,non-removable; + non-removable; }; &spi0 { diff --git a/src/arm/am437x-gp-evm.dts b/src/arm/am437x-gp-evm.dts index d692e3b2812a..77378630e5ec 100644 --- a/src/arm/am437x-gp-evm.dts +++ b/src/arm/am437x-gp-evm.dts @@ -91,22 +91,6 @@ backlight = <&lcd_bl>; - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <210>; - hback-porch = <16>; - hsync-len = <30>; - vback-porch = <10>; - vfront-porch = <22>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; @@ -869,7 +853,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&emmc_pins_default>; pinctrl-1 = <&emmc_pins_sleep>; - ti,non-removable; + non-removable; }; &mmc3 { @@ -886,7 +870,7 @@ pinctrl-1 = <&mmc3_pins_sleep>; cap-power-off-card; keep-power-in-suspend; - ti,non-removable; + non-removable; #address-cells = <1>; #size-cells = <0>; diff --git a/src/arm/am437x-l4.dtsi b/src/arm/am437x-l4.dtsi index 49c6a872052e..906ac29f017d 100644 --- a/src/arm/am437x-l4.dtsi +++ b/src/arm/am437x-l4.dtsi @@ -328,9 +328,8 @@ }; }; - target-module@31000 { /* 0x44e31000, ap 24 40.0 */ + timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */ compatible = "ti,sysc-omap2-timer", "ti,sysc"; - ti,hwmods = "timer1"; reg = <0x31000 0x4>, <0x31010 0x4>, <0x31014 0x4>; @@ -450,7 +449,6 @@ target-module@86000 { /* 0x44e86000, ap 40 70.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; reg = <0x86000 0x4>, <0x86004 0x4>; reg-names = "rev", "sysc"; @@ -868,9 +866,8 @@ }; }; - target-module@40000 { /* 0x48040000, ap 18 1e.0 */ + timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer2"; reg = <0x40000 0x4>, <0x40010 0x4>, <0x40014 0x4>; @@ -1086,9 +1083,8 @@ ranges = <0x0 0x60000 0x1000>; mmc1: mmc@0 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,am437-sdhci"; reg = <0x0 0x1000>; - ti,dual-volt; ti,needs-special-reset; dmas = <&edma 24 0>, <&edma 25 0>; @@ -1544,8 +1540,9 @@ reg = <0xcc020 0x4>; reg-names = "rev"; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>, + <&dcan0_fck>; + clock-names = "fck", "osc"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xcc000 0x2000>; @@ -1553,6 +1550,8 @@ dcan0: can@0 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; reg = <0x0 0x2000>; + clocks = <&dcan0_fck>; + clock-names = "fck"; syscon-raminit = <&scm_conf 0x644 0>; interrupts = ; status = "disabled"; @@ -1564,8 +1563,9 @@ reg = <0xd0020 0x4>; reg-names = "rev"; /* Domains (P, C): per_pwrdm, l4ls_clkdm */ - clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>; - clock-names = "fck"; + clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>, + <&dcan1_fck>; + clock-names = "fck", "osc"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xd0000 0x2000>; @@ -1573,6 +1573,8 @@ dcan1: can@0 { compatible = "ti,am4372-d_can", "ti,am3352-d_can"; reg = <0x0 0x2000>; + clocks = <&dcan1_fck>; + clock-name = "fck"; syscon-raminit = <&scm_conf 0x644 1>; interrupts = ; status = "disabled"; @@ -1601,7 +1603,7 @@ ranges = <0x0 0xd8000 0x1000>; mmc2: mmc@0 { - compatible = "ti,omap4-hsmmc"; + compatible = "ti,am437-sdhci"; reg = <0x0 0x1000>; ti,needs-special-reset; dmas = <&edma 2 0>, diff --git a/src/arm/am437x-sk-evm.dts b/src/arm/am437x-sk-evm.dts index 4d5a7ca2e25d..08eabf0f3cbd 100644 --- a/src/arm/am437x-sk-evm.dts +++ b/src/arm/am437x-sk-evm.dts @@ -134,22 +134,6 @@ enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <2>; - hback-porch = <2>; - hsync-len = <41>; - vfront-porch = <2>; - vback-porch = <2>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; @@ -719,7 +703,7 @@ pinctrl-1 = <&mmc3_pins_sleep>; cap-power-off-card; keep-power-in-suspend; - ti,non-removable; + non-removable; #address-cells = <1>; #size-cells = <0>; diff --git a/src/arm/am43x-epos-evm.dts b/src/arm/am43x-epos-evm.dts index 27259fd6f741..7d4e0dffde7a 100644 --- a/src/arm/am43x-epos-evm.dts +++ b/src/arm/am43x-epos-evm.dts @@ -47,22 +47,6 @@ backlight = <&lcd_bl>; - panel-timing { - clock-frequency = <33000000>; - hactive = <800>; - vactive = <480>; - hfront-porch = <210>; - hback-porch = <16>; - hsync-len = <30>; - vback-porch = <10>; - vfront-porch = <22>; - vsync-len = <13>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - port { lcd_in: endpoint { remote-endpoint = <&dpi_out>; diff --git a/src/arm/am571x-idk.dts b/src/arm/am571x-idk.dts index c13756fa0f55..99a408a2ec6a 100644 --- a/src/arm/am571x-idk.dts +++ b/src/arm/am571x-idk.dts @@ -10,6 +10,7 @@ #include "dra7-mmc-iodelay.dtsi" #include "dra72x-mmc-iodelay.dtsi" #include "am57xx-idk-common.dtsi" +#include "dra7-ipu-dsp-common.dtsi" / { model = "TI AM5718 IDK"; @@ -20,6 +21,33 @@ reg = <0x0 0x80000000 0x0 0x40000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + leds { compatible = "gpio-leds"; cpu0-led { @@ -148,21 +176,19 @@ load-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; }; -&mailbox5 { +&ipu2 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; + memory-region = <&ipu2_memory_region>; }; -&mailbox6 { +&ipu1 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; }; &pcie1_rc { diff --git a/src/arm/am5729-beagleboneai.dts b/src/arm/am5729-beagleboneai.dts new file mode 100644 index 000000000000..4c51c6b05e64 --- /dev/null +++ b/src/arm/am5729-beagleboneai.dts @@ -0,0 +1,731 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2014-2019 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; + +#include "dra74x.dtsi" +#include "am57xx-commercial-grade.dtsi" +#include "dra74x-mmc-iodelay.dtsi" +#include +#include +#include + +/ { + model = "BeagleBoard.org BeagleBone AI"; + compatible = "beagle,am5729-beagleboneai", "ti,am5728", + "ti,dra742", "ti,dra74", "ti,dra7"; + + aliases { + rtc0 = &tps659038_rtc; + rtc1 = &rtc; + display0 = &hdmi_conn; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + + }; + + vdd_adc: gpioregulator-vdd_adc { + compatible = "regulator-gpio"; + regulator-name = "vdd_adc"; + vin-supply = <&vdd_5v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + states = <1800000 0 + 3300000 1>; + }; + + vdd_5v: fixedregulator-vdd_5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&vdd_ddr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "beaglebone:green:usr0"; + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led1 { + label = "beaglebone:green:usr1"; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led2 { + label = "beaglebone:green:usr2"; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu"; + default-state = "off"; + }; + + led3 { + label = "beaglebone:green:usr3"; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "beaglebone:green:usr4"; + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + default-state = "off"; + }; + }; + + hdmi_conn: connector@0 { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_encoder_out>; + }; + }; + }; + + hdmi_enc: encoder@0 { + /* "ti,tpd12s016" software compatible with "ti,tpd12s015" + * no need for individual driver + */ + compatible = "ti,tpd12s015"; + gpios = <0>, + <0>, + <&gpio7 12 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + + hdmi_encoder_in: endpoint@0 { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <0x1>; + + hdmi_encoder_out: endpoint@0 { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + emmc_pwrseq: emmc_pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; + }; + + brcmf_pwrseq: brcmf_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>, /* BT-REG-ON */ + <&gpio3 18 GPIO_ACTIVE_LOW>; /* WL-REG-ON */ + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + ti,enable-id-detection; + id-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + ti,palmas-override-powerhold; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + smps12-in-supply = <&vdd_5v>; + smps3-in-supply = <&vdd_5v>; + smps45-in-supply = <&vdd_5v>; + smps6-in-supply = <&vdd_5v>; + smps7-in-supply = <&vdd_5v>; + mps3-in-supply = <&vdd_5v>; + smps8-in-supply = <&vdd_5v>; + smps9-in-supply = <&vdd_5v>; + ldo1-in-supply = <&vdd_5v>; + ldo2-in-supply = <&vdd_5v>; + ldo3-in-supply = <&vdd_5v>; + ldo4-in-supply = <&vdd_5v>; + ldo9-in-supply = <&vdd_5v>; + ldoln-in-supply = <&vdd_5v>; + ldousb-in-supply = <&vdd_5v>; + ldortc-in-supply = <&vdd_5v>; + + regulators { + vdd_mpu: smps12 { + /* VDD_MPU */ + regulator-name = "smps12"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_ddr: smps3 { + /* VDD_DDR EMIF1 EMIF2 */ + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_dspeve: smps45 { + /* VDD_DSPEVE on AM572 */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_gpu: smps6 { + /* VDD_GPU */ + regulator-name = "smps6"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_core: smps7 { + /* VDD_CORE */ + regulator-name = "smps7"; + regulator-min-microvolt = < 850000>; /*** 1.15V */ + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_iva: smps8 { + /* VDD_IVAHD */ /*** 1.06V */ + regulator-name = "smps8"; + }; + + vdd_3v3: smps9 { + /* VDD_3V3 */ + regulator-name = "smps9"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_sd: ldo1 { + /* VDDSHV8 - VSDMMC */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_1v8: ldo2 { + /* VDDSH18V */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_phy_ldo3: ldo3 { + /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_phy_ldo4: ldo4 { + /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* LDO5-8 unused */ + + vdd_rtc: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = < 840000>; + regulator-max-microvolt = <1160000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8_pll: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldortc_reg: ldortc { + /* VDDA_RTC */ + regulator-name = "ldortc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + + regen2: regen2 { + /* Needed for PMIC internal resource */ + regulator-name = "regen2"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + + tps659038_gpio: tps659038_gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + /* STMPE811 touch screen controller */ + stmpe811@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio2>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + st,mod-12b = <1>; /* 12-bit ADC */ + st,ref-sel = <0>; /* internal ADC reference */ + st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ + st,sample-time = <4>; /* ADC converstion time: 80 clocks */ + + stmpe_adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x00>; /* mask any channels to be used by touchscreen */ + adc0: iio-device@0 { + #io-channel-cells = <1>; + iio-channels = <&adc0 4>, <&adc0 1>, <&adc0 2>, <&adc0 3>, <&adc0 4>, <&adc0 5>, <&adc0 6>; + iio-channel-names = "AIN0_P9_39", "AIN1_P9_40", "AIN2_P9_37", "AIN3_P9_38", + "AIN4_P9_33", "AIN5_P9_36", "AIN6_P9_35"; + }; + }; + + stmpe_touchscreen { + status = "disabled"; + compatible = "st,stmpe-ts"; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 7 length fractional part in z */ + st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ + st,i-drive = <1>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + }; + + stmpe_gpio { + compatible = "st,stmpe-gpio"; + }; + + stmpe_pwm { + compatible = "st,stmpe-pwm"; + #pwm-cells = <2>; + }; + }; +}; + +&mcspi3 { + status = "okay"; + ti,pindir-d0-out-d1-in; + + sn65hvs882: sn65hvs882@0 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + }; +}; + +&cpu0 { + vdd-supply = <&vdd_mpu>; + voltage-tolerance = <1>; +}; + +&uart1 { + status = "okay"; +}; + +&davinci_mdio { + reset-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; + + phy0: ethernet-phy@1 { + reg = <4>; + eee-broken-100tx; + eee-broken-1000t; + }; +}; + +&mac { + slaves = <1>; + status = "okay"; +}; + +&cpsw_emac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-rxid"; +}; + +&ocp { + pruss1_shmem: pruss_shmem@4b200000 { + status = "okay"; + compatible = "ti,pruss-shmem"; + reg = <0x4b200000 0x020000>; + }; + + pruss2_shmem: pruss_shmem@4b280000 { + status = "okay"; + compatible = "ti,pruss-shmem"; + reg = <0x4b280000 0x020000>; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vdd_3v3>; + vqmmc-supply = <&vdd_sd>; + bus-width = <4>; + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ + + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&vdd_1v8>; + vqmmc-supply = <&vdd_1v8>; + bus-width = <8>; + ti,non-removable; + non-removable; + mmc-pwrseq = <&emmc_pwrseq>; + + ti,needs-special-reset; + dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; + dma-names = "tx", "rx"; + +}; + +&mmc4 { + /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */ + /* HS: High speed up to 50 MHz (3.3 V signaling). */ + /* SDR12: SDR up to 25 MHz (1.8 V signaling). */ + /* SDR25: SDR up to 50 MHz (1.8 V signaling). */ + /* SDR50: SDR up to 100 MHz (1.8 V signaling). */ + /* SDR104: SDR up to 208 MHz (1.8 V signaling) */ + /* DDR50: DDR up to 50 MHz (1.8 V signaling). */ + status = "okay"; + + ti,needs-special-reset; + vmmc-supply = <&vdd_3v3>; + cap-power-off-card; + keep-power-in-suspend; + bus-width = <4>; + ti,non-removable; + non-removable; + no-1-8-v; + max-frequency = <24000000>; + + #address-cells = <1>; + #size-cells = <0>; + mmc-pwrseq = <&brcmf_pwrseq>; + + brcmf: wifi@1 { + status = "okay"; + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + + brcm,sd-head-align = <4>; + brcm,sd_head_align = <4>; + brcm,sd_sgentry_align = <512>; + + interrupt-parent = <&gpio3>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + status = "okay"; + dr_mode = "otg"; +}; + +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&usb2 { + status = "okay"; + dr_mode = "host"; +}; + +&dss { + status = "okay"; + vdda_video-supply = <&vdd_1v8_pll>; +}; + +&hdmi { + status = "okay"; + vdda-supply = <&vdd_1v8_phy_ldo4>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_encoder_in>; + }; + }; +}; + +&bandgap { + status = "okay"; +}; + +&mailbox1 { + status = "okay"; +}; + +&mailbox2 { + status = "okay"; +}; + +&mailbox3 { + status = "okay"; +}; + +&mailbox4 { + status = "okay"; +}; + +&mailbox5 { + status = "okay"; +}; + +&mailbox6 { + status = "okay"; +}; + +&mailbox7 { + status = "okay"; +}; + +&mailbox8 { + status = "okay"; +}; + +&mailbox9 { + status = "okay"; +}; + +&mailbox10 { + status = "okay"; +}; + +&mailbox11 { + status = "okay"; +}; + +&mailbox12 { + status = "okay"; +}; + +&mailbox13 { + status = "okay"; +}; + +&cpu_alert0 { + temperature = <55000>; /* milliCelsius */ +}; + +&cpu_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&gpu_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&core_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&dspeve_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&iva_crit { + temperature = <85000>; /* milliCelsius */ +}; + +&sata { + status = "disabled"; +}; + +&sata_phy { + status = "disabled"; +}; + +/* bluetooth */ +&uart6 { + status = "okay"; +}; + +/* cape header stuff */ +&i2c4 { + status = "okay"; + clock-frequency = <100000>; +}; + +&cpu0_opp_table { + opp_slow-500000000 { + opp-shared; + }; +}; diff --git a/src/arm/am572x-idk-common.dtsi b/src/arm/am572x-idk-common.dtsi index ddf123620e96..37ce2d7c4173 100644 --- a/src/arm/am572x-idk-common.dtsi +++ b/src/arm/am572x-idk-common.dtsi @@ -6,6 +6,7 @@ #include #include #include "am57xx-idk-common.dtsi" +#include "dra74-ipu-dsp-common.dtsi" / { memory@0 { @@ -13,6 +14,40 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + status-leds { compatible = "gpio-leds"; cpu0-led { @@ -147,22 +182,22 @@ gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; }; -&mailbox5 { +&ipu2 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; + memory-region = <&ipu2_memory_region>; }; -&mailbox6 { +&ipu1 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; }; diff --git a/src/arm/am57xx-beagle-x15-common.dtsi b/src/arm/am57xx-beagle-x15-common.dtsi index 565675354de4..94135fc5dd44 100644 --- a/src/arm/am57xx-beagle-x15-common.dtsi +++ b/src/arm/am57xx-beagle-x15-common.dtsi @@ -7,6 +7,7 @@ #include "am5728.dtsi" #include "am57xx-commercial-grade.dtsi" #include "dra74x-mmc-iodelay.dtsi" +#include "dra74-ipu-dsp-common.dtsi" #include #include @@ -50,6 +51,40 @@ regulator-boot-on; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + vdd_3v3: fixedregulator-vdd_3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_3v3"; @@ -584,22 +619,22 @@ rx-num-evt = <32>; }; -&mailbox5 { +&ipu2 { status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; + memory-region = <&ipu2_memory_region>; }; -&mailbox6 { +&ipu1 { status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; }; diff --git a/src/arm/am57xx-idk-common.dtsi b/src/arm/am57xx-idk-common.dtsi index a3ff1237d1fa..2c0aab352b44 100644 --- a/src/arm/am57xx-idk-common.dtsi +++ b/src/arm/am57xx-idk-common.dtsi @@ -35,6 +35,16 @@ regulator-boot-on; }; + v1_2d: fixedregulator-v1_2d { + compatible = "regulator-fixed"; + regulator-name = "V1_2D"; + vin-supply = <&vmain>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + vtt_fixed: fixedregulator-vtt { /* TPS51200 */ compatible = "regulator-fixed"; @@ -139,6 +149,12 @@ }; }; }; + + src_clk_x1: src_clk_x1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <20000000>; + }; }; &dra7_pmx_core { @@ -378,6 +394,32 @@ gpio-controller; #gpio-cells = <2>; }; + + dsi_bridge: tc358778@e { + compatible = "toshiba,tc358778", "toshiba,tc358768"; + reg = <0xe>; + status = "disabled"; + + clocks = <&src_clk_x1>; + clock-names = "refclk"; + + vddc-supply = <&v1_2d>; + vddmipi-supply = <&v1_2d>; + vddio-supply = <&v3_3d>; + + dsi_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rgb_in: endpoint { + remote-endpoint = <&dpi_out>; + data-lines = <24>; + }; + }; + }; + }; }; &mcspi3 { @@ -543,4 +585,20 @@ &dss { status = "okay"; + + vdda_video-supply = <&ldoln_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_out: endpoint { + remote-endpoint = <&rgb_in>; + data-lines = <24>; + }; + }; + }; }; diff --git a/src/arm/armada-370-xp.dtsi b/src/arm/armada-370-xp.dtsi index c15f5e92f97f..0b8c2a64b36f 100644 --- a/src/arm/armada-370-xp.dtsi +++ b/src/arm/armada-370-xp.dtsi @@ -114,7 +114,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <31>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -124,7 +123,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <32>; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/src/arm/armada-375.dtsi b/src/arm/armada-375.dtsi index 2932a29ae272..9805e507c695 100644 --- a/src/arm/armada-375.dtsi +++ b/src/arm/armada-375.dtsi @@ -236,7 +236,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -247,7 +246,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/src/arm/armada-38x.dtsi b/src/arm/armada-38x.dtsi index e038abc0c6b4..9b1a24cc5e91 100644 --- a/src/arm/armada-38x.dtsi +++ b/src/arm/armada-38x.dtsi @@ -153,7 +153,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -164,7 +163,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -344,7 +342,8 @@ comphy: phy@18300 { compatible = "marvell,armada-380-comphy"; - reg = <0x18300 0x100>; + reg-names = "comphy", "conf"; + reg = <0x18300 0x100>, <0x18460 4>; #address-cells = <1>; #size-cells = <0>; diff --git a/src/arm/armada-39x.dtsi b/src/arm/armada-39x.dtsi index b1b86934c688..e0b7c2099831 100644 --- a/src/arm/armada-39x.dtsi +++ b/src/arm/armada-39x.dtsi @@ -108,7 +108,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -119,7 +118,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -130,7 +128,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; @@ -141,7 +138,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&coreclk 0>; status = "disabled"; }; diff --git a/src/arm/aspeed-ast2600-evb.dts b/src/arm/aspeed-ast2600-evb.dts index 4afa8662c4e8..8d0f4656aa05 100644 --- a/src/arm/aspeed-ast2600-evb.dts +++ b/src/arm/aspeed-ast2600-evb.dts @@ -213,3 +213,7 @@ &i2c15 { status = "okay"; }; + +&fsim0 { + status = "okay"; +}; diff --git a/src/arm/aspeed-bmc-facebook-tiogapass.dts b/src/arm/aspeed-bmc-facebook-tiogapass.dts index 5d7cbd9164d4..2d44d9ad4e40 100644 --- a/src/arm/aspeed-bmc-facebook-tiogapass.dts +++ b/src/arm/aspeed-bmc-facebook-tiogapass.dts @@ -5,6 +5,7 @@ #include "aspeed-g5.dtsi" #include +#include / { model = "Facebook TiogaPass BMC"; @@ -112,13 +113,76 @@ &kcs2 { // BMC KCS channel 2 status = "okay"; - kcs_addr = <0xca8>; + aspeed,lpc-io-reg = <0xca8>; }; &kcs3 { // BMC KCS channel 3 status = "okay"; - kcs_addr = <0xca2>; + aspeed,lpc-io-reg = <0xca2>; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "BMC_CPLD_FPGA_SEL","","","","","","","", + /*B0-B7*/ "","BMC_DEBUG_EN","","","","BMC_PPIN","PS_PWROK", + "IRQ_PVDDQ_GHJ_VRHOT_LVT3", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "BIOS_MRC_DEBUG_MSG_DIS","BOARD_REV_ID0","", + "BOARD_REV_ID1","IRQ_DIMM_SAVE_LVT3","BOARD_REV_ID2", + "CPU_ERR0_LVT3_BMC","CPU_ERR1_LVT3_BMC", + /*E0-E7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON", + "POWER_OUT","NMI_BUTTON","","CPU0_PROCHOT_LVT3_ BMC", + "CPU1_PROCHOT_LVT3_ BMC", + /*F0-F7*/ "IRQ_PVDDQ_ABC_VRHOT_LVT3","", + "IRQ_PVCCIN_CPU0_VRHOT_LVC3", + "IRQ_PVCCIN_CPU1_VRHOT_LVC3", + "IRQ_PVDDQ_KLM_VRHOT_LVT3","","P3VBAT_BRIDGE_EN","", + /*G0-G7*/ "CPU_ERR2_LVT3","CPU_CATERR_LVT3","PCH_BMC_THERMTRIP", + "CPU0_SKTOCC_LVT3","","","","BIOS_SMI_ACTIVE", + /*H0-H7*/ "LED_POST_CODE_0","LED_POST_CODE_1","LED_POST_CODE_2", + "LED_POST_CODE_3","LED_POST_CODE_4","LED_POST_CODE_5", + "LED_POST_CODE_6","LED_POST_CODE_7", + /*I0-I7*/ "CPU0_FIVR_FAULT_LVT3","CPU1_FIVR_FAULT_LVT3", + "FORCE_ADR","UV_ADR_TRIGGER_EN","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "IRQ_UV_DETECT","IRQ_OC_DETECT","HSC_TIMER_EXP","", + "MEM_THERM_EVENT_PCH","PMBUS_ALERT_BUF_EN","","", + /*M0-M7*/ "CPU0_RC_ERROR","CPU1_RC_ERROR","","OC_DETECT_EN", + "CPU0_THERMTRIP_LATCH_LVT3", + "CPU1_THERMTRIP_LATCH_LVT3","","", + /*N0-N7*/ "","","","CPU_MSMI_LVT3","","BIOS_SPI_BMC_CTRL","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "BOARD_SKU_ID0","BOARD_SKU_ID1","BOARD_SKU_ID2", + "BOARD_SKU_ID3","BOARD_SKU_ID4","BMC_PREQ", + "BMC_PWR_DEBUG","RST_RSMRST", + /*Q0-Q7*/ "","","","","UARTSW_LSB","UARTSW_MSB", + "POST_CARD_PRES_BMC","PE_BMC_WAKE", + /*R0-R7*/ "","","BMC_TCK_MUX_SEL","BMC_PRDY", + "BMC_XDP_PRSNT_IN","RST_BMC_PLTRST_BUF","SLT_CFG0", + "SLT_CFG1", + /*S0-S7*/ "THROTTLE","BMC_READY","","HSC_SMBUS_SWITCH_EN","", + "","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","BMC_FAULT","","", + /*V0-V7*/ "","","","FAST_PROCHOT_EN","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","GLOBAL_RST_WARN", + "CPU0_MEMABC_MEMHOT_LVT3_BMC", + "CPU0_MEMDEF_MEMHOT_LVT3_BMC", + "CPU1_MEMGHJ_MEMHOT_LVT3_BMC", + "CPU1_MEMKLM_MEMHOT_LVT3_BMC", + /*Y0-Y7*/ "SIO_S3","SIO_S5","BMC_JTAG_SEL","SIO_ONCONTROL","", + "","","", + /*Z0-Z7*/ "","SIO_POWER_GOOD","IRQ_PVDDQ_DEF_VRHOT_LVT3","", + "","","","", + /*AA0-AA7*/ "CPU1_SKTOCC_LVT3","IRQ_SML1_PMBUS_ALERT", + "SERVER_POWER_LED","","PECI_MUX_SELECT","UV_HIGH_SET", + "","POST_COMPLETE", + /*AB0-AB7*/ "IRQ_HSC_FAULT","OCP_MEZZA_PRES","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; }; &mac0 { @@ -368,6 +432,11 @@ &i2c4 { status = "okay"; // BMC Debug Header + ipmb0@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; }; &i2c5 { @@ -449,6 +518,11 @@ &i2c9 { status = "okay"; //USB Debug Connector + ipmb0@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; }; &pwm_tacho { diff --git a/src/arm/aspeed-bmc-facebook-yosemitev2.dts b/src/arm/aspeed-bmc-facebook-yosemitev2.dts new file mode 100644 index 000000000000..8864e9c312a8 --- /dev/null +++ b/src/arm/aspeed-bmc-facebook-yosemitev2.dts @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; +#include "aspeed-g5.dtsi" +#include + +/ { + model = "Facebook Yosemitev2 BMC"; + compatible = "facebook,yosemitev2-bmc", "aspeed,ast2500"; + aliases { + serial4 = &uart5; + }; + chosen { + stdout-path = &uart5; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + iio-hwmon { + // VOLATAGE SENSOR + compatible = "iio-hwmon"; + io-channels = <&adc 0> , <&adc 1> , <&adc 2> , <&adc 3> , + <&adc 4> , <&adc 5> , <&adc 6> , <&adc 7> , + <&adc 8> , <&adc 9> , <&adc 10>, <&adc 11> , + <&adc 12> , <&adc 13> , <&adc 14> , <&adc 15> ; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + }; +}; +&uart1 { + // Host1 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + // Host2 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; + +}; + +&uart3 { + // Host3 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart4 { + // Host4 Console + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +&uart5 { + // BMC Console + status = "okay"; +}; + +&vuart { + // Virtual UART + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + use-ncsi; + mlx,multi-host; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&i2c1 { + //Host1 IPMB bus + status = "okay"; + multi-master; + ipmb1@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c3 { + //Host2 IPMB bus + status = "okay"; + multi-master; + ipmb3@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c5 { + //Host3 IPMB bus + status = "okay"; + multi-master; + ipmb5@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c7 { + //Host4 IPMB bus + status = "okay"; + multi-master; + ipmb7@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c8 { + status = "okay"; + //FRU EEPROM + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&i2c9 { + status = "okay"; + tmp421@4e { + //INLET TEMP + compatible = "ti,tmp421"; + reg = <0x4e>; + }; + //OUTLET TEMP + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; +}; + +&i2c10 { + status = "okay"; + //HSC + adm1278@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; +}; + +&i2c11 { + status = "okay"; + //MEZZ_TEMP_SENSOR + tmp421@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; +}; + +&i2c12 { + status = "okay"; + //MEZZ_FRU + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&pwm_tacho { + status = "okay"; + //FSC + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; +}; diff --git a/src/arm/aspeed-bmc-ibm-rainier.dts b/src/arm/aspeed-bmc-ibm-rainier.dts index 6232cd726a7f..bdfe342bf7c5 100644 --- a/src/arm/aspeed-bmc-ibm-rainier.dts +++ b/src/arm/aspeed-bmc-ibm-rainier.dts @@ -4,6 +4,7 @@ #include "aspeed-g6.dtsi" #include +#include / { model = "Rainier"; @@ -32,6 +33,11 @@ no-map; reg = <0xB8000000 0x04000000>; /* 64M */ }; + + vga_memory: region@bf000000 { + no-map; + reg = <0xbf000000 0x01000000>; /* 16M */ + }; }; gpio-keys { @@ -64,6 +70,40 @@ }; +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "cfam-reset","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "presence-ps0","presence-ps1","presence-ps2","presence-ps3", + "","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + &emmc_controller { status = "okay"; }; @@ -72,6 +112,88 @@ status = "okay"; }; +&fsim0 { + status = "okay"; + + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ0: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub0: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ1: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub1: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +&fsi_occ0 { + reg = <1>; +}; + +&fsi_occ1 { + reg = <2>; +}; + &ibt { status = "okay"; }; @@ -269,66 +391,82 @@ gpio@0 { reg = <0>; + type = ; }; gpio@1 { reg = <1>; + type = ; }; gpio@2 { reg = <2>; + type = ; }; gpio@3 { reg = <3>; + type = ; }; gpio@4 { reg = <4>; + type = ; }; gpio@5 { reg = <5>; + type = ; }; gpio@6 { reg = <6>; + type = ; }; gpio@7 { reg = <7>; + type = ; }; gpio@8 { reg = <8>; + type = ; }; gpio@9 { reg = <9>; + type = ; }; gpio@10 { reg = <10>; + type = ; }; gpio@11 { reg = <11>; + type = ; }; gpio@12 { reg = <12>; + type = ; }; gpio@13 { reg = <13>; + type = ; }; gpio@14 { reg = <14>; + type = ; }; gpio@15 { reg = <15>; + type = ; }; }; @@ -386,21 +524,6 @@ &i2c9 { status = "okay"; - ir35221@42 { - compatible = "infineon,ir35221"; - reg = <0x42>; - }; - - ir35221@43 { - compatible = "infineon,ir35221"; - reg = <0x43>; - }; - - ir35221@44 { - compatible = "infineon,ir35221"; - reg = <0x44>; - }; - tmp423a@4c { compatible = "ti,tmp423"; reg = <0x4c>; @@ -411,21 +534,6 @@ reg = <0x4d>; }; - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - - ir35221@73 { - compatible = "infineon,ir35221"; - reg = <0x73>; - }; - - ir35221@74 { - compatible = "infineon,ir35221"; - reg = <0x74>; - }; - eeprom@50 { compatible = "atmel,24c128"; reg = <0x50>; @@ -435,21 +543,6 @@ &i2c10 { status = "okay"; - ir35221@42 { - compatible = "infineon,ir35221"; - reg = <0x42>; - }; - - ir35221@43 { - compatible = "infineon,ir35221"; - reg = <0x43>; - }; - - ir35221@44 { - compatible = "infineon,ir35221"; - reg = <0x44>; - }; - tmp423a@4c { compatible = "ti,tmp423"; reg = <0x4c>; @@ -460,21 +553,6 @@ reg = <0x4d>; }; - ir35221@72 { - compatible = "infineon,ir35221"; - reg = <0x72>; - }; - - ir35221@73 { - compatible = "infineon,ir35221"; - reg = <0x73>; - }; - - ir35221@74 { - compatible = "infineon,ir35221"; - reg = <0x74>; - }; - eeprom@50 { compatible = "atmel,24c128"; reg = <0x50>; @@ -540,6 +618,10 @@ status = "okay"; }; +&vuart2 { + status = "okay"; +}; + &lpc_ctrl { status = "okay"; memory-region = <&flash_memory>; diff --git a/src/arm/aspeed-bmc-opp-mihawk.dts b/src/arm/aspeed-bmc-opp-mihawk.dts index f7e935ede919..60e545b6396f 100644 --- a/src/arm/aspeed-bmc-opp-mihawk.dts +++ b/src/arm/aspeed-bmc-opp-mihawk.dts @@ -8,6 +8,52 @@ model = "Mihawk BMC"; compatible = "ibm,mihawk-bmc", "aspeed,ast2500"; + aliases { + i2c215 = &bus6_mux215; + i2c216 = &bus6_mux216; + i2c217 = &bus6_mux217; + i2c218 = &bus6_mux218; + i2c219 = &bus6_mux219; + i2c220 = &bus6_mux220; + i2c221 = &bus6_mux221; + i2c222 = &bus6_mux222; + i2c223 = &bus7_mux223; + i2c224 = &bus7_mux224; + i2c225 = &bus7_mux225; + i2c226 = &bus7_mux226; + i2c227 = &bus7_mux227; + i2c228 = &bus7_mux228; + i2c229 = &bus7_mux229; + i2c230 = &bus7_mux230; + i2c231 = &bus9_mux231; + i2c232 = &bus9_mux232; + i2c233 = &bus9_mux233; + i2c234 = &bus9_mux234; + i2c235 = &bus9_mux235; + i2c236 = &bus9_mux236; + i2c237 = &bus9_mux237; + i2c238 = &bus9_mux238; + i2c239 = &bus10_mux239; + i2c240 = &bus10_mux240; + i2c241 = &bus10_mux241; + i2c242 = &bus10_mux242; + i2c243 = &bus10_mux243; + i2c244 = &bus10_mux244; + i2c245 = &bus10_mux245; + i2c246 = &bus10_mux246; + i2c247 = &bus12_mux247; + i2c248 = &bus12_mux248; + i2c249 = &bus12_mux249; + i2c250 = &bus12_mux250; + i2c251 = &bus13_mux251; + i2c252 = &bus13_mux252; + i2c253 = &bus13_mux253; + i2c254 = &bus13_mux254; + i2c255 = &bus13_mux255; + i2c256 = &bus13_mux256; + i2c257 = &bus13_mux257; + i2c258 = &bus13_mux258; + }; chosen { stdout-path = &uart5; @@ -120,35 +166,24 @@ leds { compatible = "gpio-leds"; - fault { + front-fault { retain-state-shutdown; default-state = "keep"; gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; }; - power { + power-button { retain-state-shutdown; default-state = "keep"; gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>; }; - rear-id { + front-id { retain-state-shutdown; default-state = "keep"; gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; }; - rear-g { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>; - }; - - rear-ok { - retain-state-shutdown; - default-state = "keep"; - gpios = <&gpio ASPEED_GPIO(Y, 0) GPIO_ACTIVE_LOW>; - }; fan0 { retain-state-shutdown; @@ -630,6 +665,54 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + + bus7_mux223: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus7_mux224: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus7_mux225: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus7_mux226: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + bus7_mux227: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + bus7_mux228: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + bus7_mux229: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + bus7_mux230: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; @@ -644,6 +727,54 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + + bus6_mux215: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus6_mux216: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus6_mux217: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus6_mux218: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + bus6_mux219: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + bus6_mux220: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + bus6_mux221: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + bus6_mux222: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; @@ -684,6 +815,30 @@ i2c-mux-idle-disconnect; interrupt-controller; #interrupt-cells = <2>; + + bus9_mux231: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus9_mux232: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus9_mux233: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus9_mux234: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; }; pca9545@71 { @@ -695,6 +850,30 @@ i2c-mux-idle-disconnect; interrupt-controller; #interrupt-cells = <2>; + + bus9_mux235: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus9_mux236: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus9_mux237: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus9_mux238: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; }; }; @@ -725,6 +904,30 @@ i2c-mux-idle-disconnect; interrupt-controller; #interrupt-cells = <2>; + + bus10_mux239: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus10_mux240: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus10_mux241: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus10_mux242: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; }; pca9545@71 { @@ -736,6 +939,30 @@ i2c-mux-idle-disconnect; interrupt-controller; #interrupt-cells = <2>; + + bus10_mux243: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus10_mux244: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus10_mux245: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus10_mux246: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; }; }; @@ -796,7 +1023,7 @@ interrupt-controller; #interrupt-cells = <2>; - i2c@0 { + bus12_mux247: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; @@ -807,7 +1034,7 @@ }; }; - i2c@1 { + bus12_mux248: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; @@ -818,7 +1045,7 @@ }; }; - i2c@2 { + bus12_mux249: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; @@ -829,7 +1056,7 @@ }; }; - i2c@3 { + bus12_mux250: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; @@ -857,6 +1084,53 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; + bus13_mux251: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + bus13_mux252: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + bus13_mux253: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + bus13_mux254: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + bus13_mux255: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + bus13_mux256: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + bus13_mux257: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + bus13_mux258: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; diff --git a/src/arm/aspeed-bmc-opp-nicole.dts b/src/arm/aspeed-bmc-opp-nicole.dts new file mode 100644 index 000000000000..91dced7e7849 --- /dev/null +++ b/src/arm/aspeed-bmc-opp-nicole.dts @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2019 YADRO +/dts-v1/; +#include "aspeed-g5.dtsi" +#include + +/ { + model = "Nicole BMC"; + compatible = "yadro,nicole-bmc", "aspeed,ast2500"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + coldfire_memory: codefire_memory@9ef00000 { + reg = <0x9ef00000 0x00100000>; + no-map; + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "platform:green:power"; + gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>; + }; + + identify { + label = "platform:blue:indicator"; + gpios = <&gpio ASPEED_GPIO(AA, 7) GPIO_ACTIVE_HIGH>; + }; + + fault { + label = "platform:red:fault"; + gpios = <&gpio ASPEED_GPIO(AA, 3) GPIO_ACTIVE_HIGH>; + }; + + attention { + label = "platform:yellow:alarm"; + gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_HIGH>; + }; + }; + + fsi: gpio-fsi { + compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + memory-region = <&coldfire_memory>; + aspeed,sram = <&sram>; + aspeed,cvic = <&cvic>; + + clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(A, 6) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; +}; + +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +&i2c2 { + status = "okay"; + /* CPU0 characterization connector */ +}; + +&i2c3 { + status = "okay"; + /* CLK GEN SI5338 */ +}; + +&i2c4 { + status = "okay"; + /* Voltage regulators for CPU0 */ +}; + +&i2c5 { + status = "okay"; + /* Voltage regulators for CPU1 */ +}; + +&i2c6 { + status = "okay"; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; +}; + +&i2c7 { + status = "okay"; + /* CPLD */ +}; + +&gpio { + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","bmc_power_up","sys_pwrok_buf", + "func_mode0","func_mode1","func_mode2","","", + /*E0-E7*/ "","ncsi_cfg","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","checkstop","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","power-button","","","","","", + /*P0-P7*/ "","fsi-trans","pm_rtc_adc_en","","","","","", + /*Q0-Q7*/ "","","","","","","","id-button", + /*R0-R7*/ "","software_pwrgood","","","","","","", + /*S0-S7*/ "","","","","","","","seq_cont", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "fsi-clock","led-attention","fsi-data","led-fault", + "led-power","","","led-identify", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; + + func_mode0 { + gpio-hog; + gpios = ; + output-low; + }; + func_mode1 { + gpio-hog; + gpios = ; + output-low; + }; + func_mode2 { + gpio-hog; + gpios = ; + output-low; + }; + seq_cont { + gpio-hog; + gpios = ; + output-low; + }; + ncsi_cfg { + gpio-hog; + input; + gpios = ; + }; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pinctrl { + aspeed,external-nodes = <&gfx &lhc>; +}; + +&ibt { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&adc { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +#include "ibm-power9-dual.dtsi" diff --git a/src/arm/aspeed-bmc-opp-romulus.dts b/src/arm/aspeed-bmc-opp-romulus.dts index edfa44fe1f75..fd2e014dae75 100644 --- a/src/arm/aspeed-bmc-opp-romulus.dts +++ b/src/arm/aspeed-bmc-opp-romulus.dts @@ -231,23 +231,52 @@ }; &gpio { + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","","","nic_func_mode0","nic_func_mode1","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","power-button","","","","", + /*J0-J7*/ "","","checkstop","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","led-fault","", + "led-identify","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","id-button", + /*R0-R7*/ "","","fsi-trans","","","led-power","","", + /*S0-S7*/ "","","","","","","","seq_cont", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "fsi-clock","","fsi-data","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; + nic_func_mode0 { gpio-hog; gpios = ; output-low; - line-name = "nic_func_mode0"; }; nic_func_mode1 { gpio-hog; gpios = ; output-low; - line-name = "nic_func_mode1"; }; seq_cont { gpio-hog; gpios = ; output-low; - line-name = "seq_cont"; }; }; diff --git a/src/arm/aspeed-bmc-opp-tacoma.dts b/src/arm/aspeed-bmc-opp-tacoma.dts index ff49ec76fa7c..13c4aa02f4de 100644 --- a/src/arm/aspeed-bmc-opp-tacoma.dts +++ b/src/arm/aspeed-bmc-opp-tacoma.dts @@ -31,6 +31,59 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + checkstop { + label = "checkstop"; + gpios = <&gpio0 ASPEED_GPIO(E, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ps0-presence { + label = "ps0-presence"; + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + ps1-presence { + label = "ps1-presence"; + gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 4 GPIO_ACTIVE_LOW>; + linux,code = <4>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 5 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -89,6 +142,49 @@ linux,code = <7>; }; }; + + iio-hwmon-dps310 { + compatible = "iio-hwmon"; + io-channels = <&dps 0>; + }; + + iio-hwmon-bmp280 { + compatible = "iio-hwmon"; + io-channels = <&bmp 1>; + }; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "fsi-mux","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "power-button","","","checkstop","","presence-ps1","","led-rear-fault", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","presence-ps0","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "led-rear-power","led-rear-id","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "cfam-reset","","","","","","","fsi-routing", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; }; &fmc { @@ -132,6 +228,10 @@ use-ncsi; }; +&emmc_controller { + status = "okay"; +}; + &emmc { status = "okay"; }; @@ -142,6 +242,9 @@ #address-cells = <2>; #size-cells = <0>; + fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; + fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; + cfam@0,0 { reg = <0 0>; #address-cells = <1>; @@ -394,6 +497,11 @@ &i2c1 { status = "okay"; + + tpm: tpm@2e { + compatible = "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; }; &i2c2 { @@ -774,6 +882,10 @@ status = "okay"; }; +&vuart2 { + status = "okay"; +}; + &lpc_ctrl { status = "okay"; memory-region = <&flash_memory>; diff --git a/src/arm/aspeed-bmc-opp-witherspoon.dts b/src/arm/aspeed-bmc-opp-witherspoon.dts index 421aa600148b..a0f99e34ac8e 100644 --- a/src/arm/aspeed-bmc-opp-witherspoon.dts +++ b/src/arm/aspeed-bmc-opp-witherspoon.dts @@ -191,6 +191,40 @@ }; +&gpio { + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","fsi-mux","", + /*B0-B7*/ "","","","","","air-water","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","","","","","","","", + /*E0-E7*/ "fsi-data","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","checkstop","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "presence-ps1","","led-rear-fault","led-rear-power", + "led-rear-id","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","presence-ps0", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","fsi-trans","","","power-button","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "fsi-clock","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + &fmc { status = "okay"; diff --git a/src/arm/aspeed-bmc-opp-zaius.dts b/src/arm/aspeed-bmc-opp-zaius.dts index bc60ec291681..4bcc82046362 100644 --- a/src/arm/aspeed-bmc-opp-zaius.dts +++ b/src/arm/aspeed-bmc-opp-zaius.dts @@ -478,32 +478,61 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpioh_unbiased>; + gpio-line-names = + /*A0-A7*/ "","cfam-reset","","","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "fsi-enable","","","","","led-sys-boot-status","led-attention", + "led-fault", + /*E0-E7*/ "","","","","","","","presence-pcie-e2b", + /*F0-F7*/ "","","","","","","","checkstop", + /*G0-G7*/ "fsi-clock","fsi-data","","","","","","", + /*H0-H7*/ "onewire0","onewire1","onewire2","onewire3","","","","", + /*I0-I7*/ "","","","power-button","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","iso_u164_en","","fsi-trans","", + /*P0-P7*/ "ncsi_mux_en_n","bmc_i2c2_sw_rst_n","","bmc_i2c5_sw_rst_n","", + "","fsi-mux","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","led-hdd-fault","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; + line_iso_u146_en { gpio-hog; gpios = ; output-high; - line-name = "iso_u164_en"; }; ncsi_mux_en_n { gpio-hog; gpios = ; output-low; - line-name = "ncsi_mux_en_n"; }; line_bmc_i2c2_sw_rst_n { gpio-hog; gpios = ; output-high; - line-name = "bmc_i2c2_sw_rst_n"; }; line_bmc_i2c5_sw_rst_n { gpio-hog; gpios = ; output-high; - line-name = "bmc_i2c5_sw_rst_n"; }; }; diff --git a/src/arm/aspeed-g4.dtsi b/src/arm/aspeed-g4.dtsi index 8e04303e8514..82f0213e3a3c 100644 --- a/src/arm/aspeed-g4.dtsi +++ b/src/arm/aspeed-g4.dtsi @@ -219,6 +219,16 @@ reg = <0x1e720000 0x8000>; // 32K }; + video: video@1e700000 { + compatible = "aspeed,ast2400-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = <7>; + status = "disabled"; + }; + sdmmc: sd-controller@1e740000 { compatible = "aspeed,ast2400-sd-controller"; reg = <0x1e740000 0x100>; diff --git a/src/arm/aspeed-g5.dtsi b/src/arm/aspeed-g5.dtsi index f12ec04d3cbc..de7fd80b022a 100644 --- a/src/arm/aspeed-g5.dtsi +++ b/src/arm/aspeed-g5.dtsi @@ -224,6 +224,14 @@ #clock-cells = <1>; #reset-cells = <1>; + scu_ic: interrupt-controller@18 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2500-scu-ic"; + reg = <0x18 0x4>; + interrupts = <21>; + interrupt-controller; + }; + p2a: p2a-control@2c { compatible = "aspeed,ast2500-p2a-ctrl"; reg = <0x2c 0x4>; @@ -254,6 +262,17 @@ interrupts = <0x19>; }; + xdma: xdma@1e6e7000 { + compatible = "aspeed,ast2500-xdma"; + reg = <0x1e6e7000 0x100>; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + resets = <&syscon ASPEED_RESET_XDMA>; + interrupts-extended = <&vic 6>, <&scu_ic 2>; + pcie-device = "bmc"; + aspeed,scu = <&syscon>; + status = "disabled"; + }; + adc: adc@1e6e9000 { compatible = "aspeed,ast2500-adc"; reg = <0x1e6e9000 0xb0>; @@ -426,22 +445,22 @@ #size-cells = <1>; ranges = <0x0 0x0 0x80>; - kcs1: kcs1@0 { - compatible = "aspeed,ast2500-kcs-bmc"; + kcs1: kcs@24 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; interrupts = <8>; - kcs_chan = <1>; status = "disabled"; }; - kcs2: kcs2@0 { - compatible = "aspeed,ast2500-kcs-bmc"; + kcs2: kcs@28 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; interrupts = <8>; - kcs_chan = <2>; status = "disabled"; }; - kcs3: kcs3@0 { - compatible = "aspeed,ast2500-kcs-bmc"; + kcs3: kcs@2c { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; interrupts = <8>; - kcs_chan = <3>; status = "disabled"; }; }; @@ -455,10 +474,10 @@ #size-cells = <1>; ranges = <0x0 0x80 0x1e0>; - kcs4: kcs4@0 { - compatible = "aspeed,ast2500-kcs-bmc"; + kcs4: kcs@94 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>; interrupts = <8>; - kcs_chan = <4>; status = "disabled"; }; diff --git a/src/arm/aspeed-g6.dtsi b/src/arm/aspeed-g6.dtsi index 0a29b3b57a9d..9d8d8e18bc90 100644 --- a/src/arm/aspeed-g6.dtsi +++ b/src/arm/aspeed-g6.dtsi @@ -65,6 +65,7 @@ ; clocks = <&syscon ASPEED_CLK_HPLL>; arm,cpu-registers-not-fw-configured; + always-on; }; ahb { @@ -313,6 +314,22 @@ compatible = "aspeed,ast2600-smpmem"; reg = <0x180 0x40>; }; + + scu_ic0: interrupt-controller@560 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2600-scu-ic0"; + reg = <0x560 0x4>; + interrupts = ; + interrupt-controller; + }; + + scu_ic1: interrupt-controller@570 { + #interrupt-cells = <1>; + compatible = "aspeed,ast2600-scu-ic1"; + reg = <0x570 0x4>; + interrupts = ; + interrupt-controller; + }; }; rng: hwrng@1e6e2524 { @@ -322,6 +339,29 @@ quality = <100>; }; + xdma: xdma@1e6e7000 { + compatible = "aspeed,ast2600-xdma"; + reg = <0x1e6e7000 0x100>; + clocks = <&syscon ASPEED_CLK_GATE_BCLK>; + resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>; + reset-names = "device", "root-complex"; + interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <&scu_ic0 2>; + pcie-device = "bmc"; + aspeed,scu = <&syscon>; + status = "disabled"; + }; + + video: video@1e700000 { + compatible = "aspeed,ast2600-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = ; + status = "disabled"; + }; + gpio0: gpio@1e780000 { #gpio-cells = <2>; gpio-controller; @@ -368,6 +408,7 @@ <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&syscon ASPEED_CLK_APB1>; clock-names = "PCLK"; + status = "disabled"; }; uart1: serial@1e783000 { @@ -433,22 +474,23 @@ #size-cells = <1>; ranges = <0x0 0x0 0x80>; - kcs1: kcs1@0 { - compatible = "aspeed,ast2600-kcs-bmc"; + kcs1: kcs@24 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>; interrupts = ; kcs_chan = <1>; status = "disabled"; }; - kcs2: kcs2@0 { - compatible = "aspeed,ast2600-kcs-bmc"; + kcs2: kcs@28 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x28 0x1>, <0x34 0x1>, <0x40 0x1>; interrupts = ; - kcs_chan = <2>; status = "disabled"; }; - kcs3: kcs3@0 { - compatible = "aspeed,ast2600-kcs-bmc"; + kcs3: kcs@2c { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x2c 0x1>, <0x38 0x1>, <0x44 0x1>; interrupts = ; - kcs_chan = <3>; status = "disabled"; }; }; @@ -462,10 +504,10 @@ #size-cells = <1>; ranges = <0x0 0x80 0x1e0>; - kcs4: kcs4@0 { - compatible = "aspeed,ast2600-kcs-bmc"; + kcs4: kcs@94 { + compatible = "aspeed,ast2500-kcs-bmc-v2"; + reg = <0x94 0x1>, <0x98 0x1>, <0x9c 0x1>; interrupts = ; - kcs_chan = <4>; status = "disabled"; }; diff --git a/src/arm/at91-dvk_su60_somc.dtsi b/src/arm/at91-dvk_su60_somc.dtsi index 21876da7c442..c1c8650dafce 100644 --- a/src/arm/at91-dvk_su60_somc.dtsi +++ b/src/arm/at91-dvk_su60_somc.dtsi @@ -62,7 +62,7 @@ wm8904: wm8904@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - clocks = <&pck2>; + clocks = <&pmc PMC_TYPE_SYSTEM 10>; clock-names = "mclk"; }; }; diff --git a/src/arm/at91-kizbox3-hs.dts b/src/arm/at91-kizbox3-hs.dts index 8734e7f8939e..0da1f0557eaf 100644 --- a/src/arm/at91-kizbox3-hs.dts +++ b/src/arm/at91-kizbox3-hs.dts @@ -283,7 +283,7 @@ &flx3 { status = "okay"; - uart6: serial@200 { + uart8: serial@200 { status = "okay"; }; }; @@ -291,7 +291,7 @@ &flx4 { status = "okay"; - i2c2: i2c@600 { + i2c6: i2c@600 { status = "okay"; }; }; diff --git a/src/arm/at91-kizbox3_common.dtsi b/src/arm/at91-kizbox3_common.dtsi index 299e74d23184..7c3076e245ef 100644 --- a/src/arm/at91-kizbox3_common.dtsi +++ b/src/arm/at91-kizbox3_common.dtsi @@ -28,7 +28,7 @@ serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; - serial6 = &uart6; + serial6 = &uart8; }; chosen { @@ -207,7 +207,7 @@ }; }; - pinctrl_flx4_default: flx4_i2c2_default { + pinctrl_flx4_default: flx4_i2c6_default { pinmux = , //DATA ; //CLK bias-disable; @@ -299,21 +299,8 @@ status = "disabled"; uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x400>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(11))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(12))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "usart"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx0_default>; - atmel,fifo-size = <32>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -324,22 +311,9 @@ atmel,flexcom-mode = ; status = "disabled"; - uart6: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x400>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(17))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(18))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usart"; + uart8: serial@200 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; - atmel,fifo-size = <32>; atmel,use-dma-rx; atmel,use-dma-tx; status = "disabled"; @@ -350,23 +324,9 @@ atmel,flexcom-mode = ; status = "disabled"; - i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(19))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) - | AT91_XDMAC_DT_PERID(20))>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + i2c6: i2c@600 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; status = "disabled"; }; }; diff --git a/src/arm/at91-sam9x60ek.dts b/src/arm/at91-sam9x60ek.dts index b484745bf2d4..a5f5718c711a 100644 --- a/src/arm/at91-sam9x60ek.dts +++ b/src/arm/at91-sam9x60ek.dts @@ -542,6 +542,18 @@ }; }; + sdmmc1 { + pinctrl_sdmmc1_default: sdmmc1 { + atmel,pins = + ; /* PA4 DAT3 periph B with pullup */ + }; + }; + gpio_keys { pinctrl_key_gpio_default: pinctrl_key_gpio { atmel,pins = ; @@ -568,6 +580,15 @@ disable-wp; }; +&sdmmc1 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + no-1-8-v; + non-removable; + status = "disabled"; /* Conflict with flx4. */ +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; @@ -579,6 +600,8 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; m25p,fast-read; at91bootstrap@0 { diff --git a/src/arm/at91-sama5d27_som1.dtsi b/src/arm/at91-sama5d27_som1.dtsi index 6281590150c8..b1f994c0ae79 100644 --- a/src/arm/at91-sama5d27_som1.dtsi +++ b/src/arm/at91-sama5d27_som1.dtsi @@ -13,6 +13,10 @@ model = "Atmel SAMA5D27 SoM1"; compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + aliases { + i2c0 = &i2c0; + }; + clocks { slow_xtal { clock-frequency = <32768>; @@ -34,12 +38,44 @@ pinctrl-0 = <&pinctrl_qspi1_default>; flash@0 { + #address-cells = <1>; + #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <80000000>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read; + + at91bootstrap@00000000 { + label = "at91bootstrap"; + reg = <0x00000000 0x00040000>; + }; + + bootloader@00040000 { + label = "bootloader"; + reg = <0x00040000 0x000c0000>; + }; + + bootloaderenvred@00100000 { + label = "bootloader env redundant"; + reg = <0x00100000 0x00040000>; + }; + + bootloaderenv@00140000 { + label = "bootloader env"; + reg = <0x00140000 0x00040000>; + }; + + dtb@00180000 { + label = "device tree"; + reg = <0x00180000 0x00080000>; + }; + + kernel@00200000 { + label = "kernel"; + reg = <0x00200000 0x00600000>; + }; }; }; @@ -57,7 +93,25 @@ }; }; + i2c0: i2c@f8028000 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_default>; + status = "okay"; + + at24@50 { + compatible = "24c02"; + reg = <0x50>; + pagesize = <8>; + }; + }; + pinctrl@fc038000 { + pinctrl_i2c0_default: i2c0_default { + pinmux = , + ; + bias-disable; + }; pinctrl_qspi1_default: qspi1_default { sck_cs { diff --git a/src/arm/at91-sama5d27_som1_ek.dts b/src/arm/at91-sama5d27_som1_ek.dts index b0853bf7901c..0e159f879c15 100644 --- a/src/arm/at91-sama5d27_som1_ek.dts +++ b/src/arm/at91-sama5d27_som1_ek.dts @@ -21,7 +21,7 @@ serial1 = &uart4; /* mikro BUS 1 */ serial2 = &uart2; /* mikro BUS 2 */ i2c1 = &i2c1; - i2c2 = &i2c2; + i2c2 = &i2c3; }; chosen { @@ -125,21 +125,13 @@ atmel,flexcom-mode = ; status = "okay"; - i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + i2c3: i2c@600 { dmas = <0>, <0>; - dma-names = "tx", "rx"; i2c-analog-filter; i2c-digital-filter; i2c-digital-filter-width-ns = <35>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_i2c>; - atmel,fifo-size = <16>; status = "okay"; }; }; @@ -178,27 +170,17 @@ atmel,flexcom-mode = ; status = "disabled"; - uart7: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "usart"; + uart8: serial@200 { + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; - atmel,fifo-size = <32>; status = "disabled"; /* Conflict with isc. */ }; - spi2: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; - clock-names = "spi_clk"; + spi5: spi@400 { + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx3_default>; - atmel,fifo-size = <16>; status = "disabled"; /* Conflict with isc. */ }; }; @@ -207,43 +189,25 @@ atmel,flexcom-mode = ; status = "okay"; - uart6: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "usart"; + uart9: serial@200 { + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <32>; - status = "disabled"; /* Conflict with spi3 and i2c3. */ + status = "disabled"; /* Conflict with spi6 and i2c6. */ }; - spi3: spi@400 { - compatible = "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; - clock-names = "spi_clk"; + spi6: spi@400 { + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus_spi &pinctrl_mikrobus1_spi_cs &pinctrl_mikrobus2_spi_cs>; - atmel,fifo-size = <16>; - status = "okay"; /* Conflict with uart6 and i2c3. */ + status = "okay"; /* Conflict with uart5 and i2c6. */ }; - i2c3: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + i2c6: i2c@600 { dmas = <0>, <0>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; - status = "disabled"; /* Conflict with uart6 and spi3. */ + status = "disabled"; /* Conflict with uart5 and spi6. */ }; }; diff --git a/src/arm/at91-sama5d27_wlsom1.dtsi b/src/arm/at91-sama5d27_wlsom1.dtsi index db3e2239eee8..a06700e53e4c 100644 --- a/src/arm/at91-sama5d27_wlsom1.dtsi +++ b/src/arm/at91-sama5d27_wlsom1.dtsi @@ -17,6 +17,10 @@ model = "Microchip SAMA5D27 WLSOM1"; compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + aliases { + i2c0 = &i2c0; + }; + clocks { slow_xtal { clock-frequency = <32768>; @@ -32,18 +36,6 @@ atmel,flexcom-mode = ; uart6: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(13))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(14))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; - clock-names = "usart"; pinctrl-0 = <&pinctrl_flx1_default>; pinctrl-names = "default"; }; diff --git a/src/arm/at91-sama5d27_wlsom1_ek.dts b/src/arm/at91-sama5d27_wlsom1_ek.dts index 6b8461278950..6b38fa3f5568 100644 --- a/src/arm/at91-sama5d27_wlsom1_ek.dts +++ b/src/arm/at91-sama5d27_wlsom1_ek.dts @@ -77,18 +77,6 @@ status = "okay"; uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(11))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(12))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "usart"; pinctrl-0 = <&pinctrl_flx0_default>; pinctrl-names = "default"; atmel,use-dma-rx; diff --git a/src/arm/at91-sama5d2_icp.dts b/src/arm/at91-sama5d2_icp.dts new file mode 100644 index 000000000000..8d19925fc09e --- /dev/null +++ b/src/arm/at91-sama5d2_icp.dts @@ -0,0 +1,767 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d2_icp.dts - Device Tree file for SAMA5D2-ICP board + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Radu Pirea & Razvan Stefanescu, + * Codrin Ciubotariu , + * Cristian Birsan + */ +/dts-v1/; +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" +#include +#include + +/ { + model = "Microchip SAMA5D2-ICP"; + compatible = "microchip,sama5d2-icp", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5"; + + aliases { + serial0 = &uart0; /* debug uart0 + mikro BUS 1 */ + serial1 = &uart1; /* mikro BUS 3 */ + serial3 = &uart3; /* mikro BUS 2 */ + serial5 = &uart7; /* flx2 */ + i2c0 = &i2c0; + i2c1 = &i2c1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + status = "okay"; + + sw4 { + label = "USER_PB1"; + gpios = <&pioA PIN_PD0 GPIO_ACTIVE_LOW>; + linux,code = <0x104>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led_gpio_default>; + status = "okay"; /* conflict with pwm0 */ + + red { + label = "red"; + gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>; + }; + + green { + label = "green"; + gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; + }; + + blue { + label = "blue"; + gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&adc { + vddana-supply = <&vdd_io_reg>; + vref-supply = <&vdd_io_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; +}; + +&flx0 { /* mikrobus2 spi */ + atmel,flexcom-mode = ; + status = "okay"; + + spi2: spi@400 { + dmas = <0>, <0>; + cs-gpios = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus2_spi &pinctrl_ksz_spi_cs>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + switch0: ksz8563@0 { + compatible = "microchip,ksz8563"; + reg = <0>; + phy-mode = "mii"; + reset-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_LOW>; + + spi-max-frequency = <500000>; + spi-cpha; + spi-cpol; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "cpu"; + ethernet = <&macb0>; + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&flx2 { + atmel,flexcom-mode = ; + status = "okay"; + + uart7: serial@200 { + pinctrl-0 = <&pinctrl_flx2_default>; + pinctrl-names = "default"; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; /* Conflict w/ qspi1. */ + }; +}; + +&flx3 { /* mikrobus1 spi */ + atmel,flexcom-mode = ; + status = "okay"; + + spi5: spi@400 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_spi &pinctrl_mikrobus1_spi_cs>; + status = "okay"; + }; +}; + +&flx4 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c6: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx4_default>; + status = "okay"; + + mcp16502@5b { + compatible = "microchip,mcp16502"; + reg = <0x5b>; + status = "okay"; + lpm-gpios = <&pioBU 7 GPIO_ACTIVE_LOW>; + + regulators { + vdd_io_reg: VDD_IO { + regulator-name = "VDD_IO"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_DDR { + regulator-name = "VDD_DDR"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_CORE { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + VDD_OTHER { + regulator-name = "VDD_OTHER"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1850000>; + regulator-initial-mode = <2>; + regulator-allowed-modes = <2>, <4>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + regulator-mode = <4>; + }; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-mode = <4>; + }; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + }; + }; + }; +}; + +&i2c0 { /* mikrobus i2c */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus_i2c>; + status = "okay"; +}; + +&i2c1 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <16>; + status = "okay"; + }; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <16>; + status = "disabled"; + }; + + eeprom@53 { + compatible = "atmel,24c32"; + reg = <0x53>; + pagesize = <16>; + status = "disabled"; + }; +}; + +&macb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq &pinctrl_macb0_rst>; + phy-mode = "mii"; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&pioA { + pinctrl_adc_default: adc_default { + pinmux = , + , + ; + bias-disable; + }; + + /* + * The ADTRG pin can work on any edge type. + * In here it's being pulled up, so need to + * connect it to ground to get an edge e.g. + * Trigger can be configured on falling, rise + * or any edge, and the pull-up can be changed + * to pull-down or left floating according to + * needs. + */ + pinctrl_adtrg_default: adtrg_default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_flx4_default: flx4_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_can0_default: can0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_can1_default: can1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_i2c1_default: i2c1_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_key_gpio_default: key_gpio_default { + pinmux = ; + bias-pull-up; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = , + , + ; + bias-pull-up; + }; + + pinctrl_qspi1_default: qspi1_default { + pinmux = , + , + , + , + , + ; + bias-disable; + }; + + pinctrl_sdmmc0_default: sdmmc0_default { + cmd_data { + pinmux = , + , + , + , + ; + bias-disable; + }; + + ck_cd { + pinmux = , + ; + bias-disable; + }; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { + pinmux = , + , + , + ; + bias-disable; + }; + + ck_cd { + pinmux = , + ; + bias-disable; + }; + }; + + pinctrl_mikrobus_i2c: mikrobus_i2c { + pinmux = , + ; + bias-disable; + }; + + pinctrl_mikrobus1_an: mikrobus1_an { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_rst: mikrobus1_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_spi_cs: mikrobus1_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_spi: mikrobus1_spi { + pinmux = , + , + ; + bias-disable; + }; + + pinctrl_mikrobus1_pwm: mikrobus1_pwm { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_int: mikrobus1_int { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus1_uart: mikrobus1_uart { + pinmux = , + ; + bias-disable; + }; + + pinctrl_mikrobus2_an: mikrobus2_an { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_rst: mikrobus2_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_spi_cs: mikrobus2_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_spi: mikrobus2_spi { + pinmux = , + , + ; + bias-disable; + }; + + pinctrl_ksz_spi_cs: ksz_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_pwm: mikrobus2_pwm { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_int: mikrobus2_int { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus2_uart: mikrobus2_uart { + pinmux = , + ; + bias-disable; + }; + + pinctrl_mikrobus3_an: mikrobus3_an { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_rst: mikrobus3_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_spi_cs: mikrobus3_spi_cs { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_spi: mikrobus3_spi { + pinmux = , + , + ; + bias-disable; + }; + + pinctrl_mikrobus3_pwm: mikrobus3_pwm { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_int: mikrobus3_int { + pinmux = ; + bias-disable; + }; + + pinctrl_mikrobus3_uart: mikrobus3_uart { + pinmux = , + ; + bias-disable; + }; + + pinctrl_usb_default: usb_default { + pinmux = ; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = ; + bias-disable; + }; + + pinctrl_pwm0_pwm2_default: pwm0_pwm2_default { + pinmux = , + ; + bias-pull-up; + }; + + pinctrl_macb0_default: macb0_default { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = ; + bias-disable; + }; + + pinctrl_macb0_rst: macb0_sw_rst { + pinmux = ; + bias-disable; + }; + + pinctrl_flx2_default: flx2_default { + pinmux = , + , + , + ; + bias-disable; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_pwm2_default>; + status = "disabled"; /* conflict with leds, HSIC */ +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + status = "disabled"; /* Conflict with wilc_pwrseq, flx2 */ + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + + at91bootstrap@0 { + label = "qspi: at91bootstrap"; + reg = <0x00000000 0x00040000>; + }; + + bootloader@40000 { + label = "qspi: bootloader"; + reg = <0x00040000 0x000c0000>; + }; + + bootloaderenvred@100000 { + label = "qspi: bootloader env redundant"; + reg = <0x00100000 0x00040000>; + }; + + bootloaderenv@140000 { + label = "qspi: bootloader env"; + reg = <0x00140000 0x00040000>; + }; + + dtb@180000 { + label = "qspi: device tree"; + reg = <0x00180000 0x00080000>; + }; + + kernel@200000 { + label = "qspi: kernel"; + reg = <0x00200000 0x00600000>; + }; + }; +}; + +&sdmmc0 { + no-1-8-v; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default>; + status = "okay"; +}; + +&shutdown_controller { + atmel,shdwc-debouncer = <976>; + atmel,wakeup-rtc-timer; + + input@0 { + reg = <0>; + atmel,wakeup-type = "low"; + }; +}; + +&spi0 { /* mikrobus3 spi */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus3_spi &pinctrl_mikrobus3_spi_cs>; + status = "okay"; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus3_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus2_uart>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "okay"; +}; + +&usb0 { + atmel,vbus-gpio = <&pioA PIN_PD23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { + num-ports = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + phy_type = "hsic"; + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/src/arm/at91-sama5d2_ptc_ek.dts b/src/arm/at91-sama5d2_ptc_ek.dts index 1c24ac8019ba..c894c7c788a9 100644 --- a/src/arm/at91-sama5d2_ptc_ek.dts +++ b/src/arm/at91-sama5d2_ptc_ek.dts @@ -18,9 +18,9 @@ compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5"; aliases { - serial0 = &uart0; - i2c0 = &i2c0; - i2c1 = &i2c1; + serial0 = &uart0; /* DBGU */ + i2c0 = &i2c0; /* mikroBUS 1 */ + i2c1 = &i2c1; /* XPRO EXT1 */ i2c2 = &i2c2; }; @@ -40,7 +40,7 @@ ahb { usb0: gadget@300000 { - atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>; + atmel,vbus-gpio = <&pioA PIN_PB11 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; status = "okay"; @@ -125,8 +125,6 @@ bus-width = <8>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdmmc0_default>; - non-removable; - mmc-ddr-1_8v; status = "okay"; }; @@ -184,7 +182,7 @@ pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD22 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; @@ -193,20 +191,12 @@ status = "okay"; i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <0>, <0>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_flx0_default>; pinctrl-1 = <&pinctrl_flx0_gpio>; sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PB29 GPIO_ACTIVE_HIGH>; - atmel,fifo-size = <16>; + scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; }; @@ -236,7 +226,7 @@ pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&pioA PIN_PC6 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PC7 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PC7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; at24@50 { @@ -414,6 +404,7 @@ label = "PB_USER"; gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>; linux,code = <0x104>; + wakeup-source; }; }; diff --git a/src/arm/at91-sama5d2_xplained.dts b/src/arm/at91-sama5d2_xplained.dts index 055ee53e4773..a927165ea7c2 100644 --- a/src/arm/at91-sama5d2_xplained.dts +++ b/src/arm/at91-sama5d2_xplained.dts @@ -16,6 +16,13 @@ model = "Atmel SAMA5D2 Xplained"; compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5"; + aliases { + serial0 = &uart1; /* DBGU */ + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; /* XPRO EXT2 */ + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -72,6 +79,58 @@ }; apb { + qspi0: spi@f0020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0_default>; + status = "disabled"; /* conflict with sdmmc1 */ + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + + at91bootstrap@00000000 { + label = "at91bootstrap"; + reg = <0x00000000 0x00040000>; + }; + + bootloader@00040000 { + label = "bootloader"; + reg = <0x00040000 0x000c0000>; + }; + + bootloaderenvred@00100000 { + label = "bootloader env redundant"; + reg = <0x00100000 0x00040000>; + }; + + bootloaderenv@00140000 { + label = "bootloader env"; + reg = <0x00140000 0x00040000>; + }; + + dtb@00180000 { + label = "device tree"; + reg = <0x00180000 0x00080000>; + }; + + kernel@00200000 { + label = "kernel"; + reg = <0x00200000 0x00600000>; + }; + + misc@00800000 { + label = "misc"; + reg = <0x00800000 0x00000000>; + }; + }; + }; + spi0: spi@f8000000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0_default>; @@ -133,7 +192,7 @@ pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD22 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-sda-hold-time-ns = <350>; status = "okay"; @@ -275,16 +334,25 @@ status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ uart5: serial@200 { - compatible = "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; - clock-names = "usart"; + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx0_default>; - atmel,fifo-size = <32>; status = "okay"; }; + + i2c2: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_flx0_default>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PB29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-sda-hold-time-ns = <350>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */ + }; }; shdwc@f8048010 { @@ -325,21 +393,13 @@ atmel,flexcom-mode = ; status = "okay"; - i2c2: i2c@600 { - compatible = "atmel,sama5d2-i2c"; - reg = <0x600 0x200>; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + i2c6: i2c@600 { dmas = <0>, <0>; - dma-names = "tx", "rx"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_flx4_default>; pinctrl-1 = <&pinctrl_flx4_gpio>; sda-gpios = <&pioA PIN_PD12 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD13 GPIO_ACTIVE_HIGH>; - atmel,fifo-size = <16>; + scl-gpios = <&pioA PIN_PD13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-analog-filter; i2c-digital-filter; i2c-digital-filter-width-ns = <35>; @@ -356,7 +416,7 @@ i2c-digital-filter-width-ns = <35>; pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&pioA PIN_PD4 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA PIN_PD5 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA PIN_PD5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; at24@54 { @@ -480,6 +540,12 @@ bias-disable; }; + pinctrl_i2c2_gpio: i2c2_gpio { + pinmux = , + ; + bias-disable; + }; + pinctrl_i2s0_default: i2s0_default { pinmux = , , @@ -535,6 +601,22 @@ bias-disable; }; + pinctrl_qspi0_default: qspi0_default { + sck_cs { + pinmux = , + ; + bias-disable; + }; + + data { + pinmux = , + , + , + ; + bias-pull-up; + }; + }; + pinctrl_sdmmc0_default: sdmmc0_default { cmd_data { pinmux = , diff --git a/src/arm/at91-wb50n.dtsi b/src/arm/at91-wb50n.dtsi index 4ed8500a5cb8..1487b893cfa7 100644 --- a/src/arm/at91-wb50n.dtsi +++ b/src/arm/at91-wb50n.dtsi @@ -46,10 +46,6 @@ atmel,osc-bypass; }; -&usart1_clk { - atmel,clk-output-range = <0 132000000>; -}; - &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; diff --git a/src/arm/at91rm9200.dtsi b/src/arm/at91rm9200.dtsi index 44385718d9d4..a5040f5ea641 100644 --- a/src/arm/at91rm9200.dtsi +++ b/src/arm/at91rm9200.dtsi @@ -101,259 +101,9 @@ compatible = "atmel,at91rm9200-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <80000000 160000000 0>, - <150000000 180000000 2>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <1000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <80000000 160000000 0>, - <150000000 180000000 2>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - atmel,clk-output-range = <0 80000000>; - atmel,clk-divisors = <1 2 3 4>; - }; - - usb: usbck { - compatible = "atmel,at91rm9200-clk-usb"; - #clock-cells = <0>; - atmel,clk-divisors = <1 2 0 0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91rm9200-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - - prog3: prog3 { - #clock-cells = <0>; - reg = <3>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - udpck: udpck { - #clock-cells = <0>; - reg = <2>; - clocks = <&usb>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <4>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - - pck3: pck3 { - #clock-cells = <0>; - reg = <11>; - clocks = <&prog3>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <9>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <10>; - }; - - udc_clk: udc_clk { - #clock-cells = <0>; - reg = <11>; - }; - - twi0_clk: twi0_clk { - reg = <12>; - #clock-cells = <0>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc2_clk: ssc2_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tc0_clk: tc0_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tc1_clk: tc1_clk { - #clock-cells = <0>; - reg = <18>; - }; - - tc2_clk: tc2_clk { - #clock-cells = <0>; - reg = <19>; - }; - - tc3_clk: tc3_clk { - #clock-cells = <0>; - reg = <20>; - }; - - tc4_clk: tc4_clk { - #clock-cells = <0>; - reg = <21>; - }; - - tc5_clk: tc5_clk { - #clock-cells = <0>; - reg = <22>; - }; - - ohci_clk: ohci_clk { - #clock-cells = <0>; - reg = <23>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <24>; - }; - }; + #clock-cells = <2>; + clocks = <&slow_xtal>, <&main_xtal>; + clock-names = "slow_xtal", "main_xtal"; }; st: timer@fffffd00 { @@ -383,7 +133,7 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 19 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -395,7 +145,7 @@ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 21 IRQ_TYPE_LEVEL_HIGH 0 22 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&slow_xtal>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -405,7 +155,7 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_twi>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -415,7 +165,7 @@ compatible = "atmel,hsmci"; reg = <0xfffb4000 0x4000>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; @@ -429,7 +179,7 @@ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "pclk"; status = "disabled"; }; @@ -440,7 +190,7 @@ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "pclk"; status = "disabled"; }; @@ -451,7 +201,7 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; - clocks = <&ssc2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "pclk"; status = "disabled"; }; @@ -463,7 +213,7 @@ phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; clock-names = "ether_clk"; status = "disabled"; }; @@ -803,7 +553,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff600 { @@ -814,7 +564,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioC: gpio@fffff800 { @@ -825,7 +575,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioC_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; pioD: gpio@fffffa00 { @@ -836,7 +586,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; }; }; @@ -846,7 +596,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -859,7 +609,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "usart"; status = "disabled"; }; @@ -872,7 +622,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -885,7 +635,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; @@ -898,7 +648,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "usart"; status = "disabled"; }; @@ -907,7 +657,7 @@ compatible = "atmel,at91rm9200-udc"; reg = <0xfffb0000 0x4000>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udc_clk>, <&udpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 2>; clock-names = "pclk", "hclk"; status = "disabled"; }; @@ -920,7 +670,7 @@ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "spi_clk"; status = "disabled"; }; @@ -947,7 +697,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00300000 0x100000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 4>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; diff --git a/src/arm/at91sam9g45.dtsi b/src/arm/at91sam9g45.dtsi index fd179097a4bf..1fbee2a7785f 100644 --- a/src/arm/at91sam9g45.dtsi +++ b/src/arm/at91sam9g45.dtsi @@ -103,14 +103,14 @@ ramc0: ramc@ffffe400 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe400 0x200>; - clocks = <&ddrck>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; clock-names = "ddrck"; }; ramc1: ramc@ffffe600 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe600 0x200>; - clocks = <&ddrck>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; clock-names = "ddrck"; }; @@ -128,271 +128,9 @@ compatible = "atmel,at91sam9g45-pmc", "syscon"; reg = <0xfffffc00 0x100>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91rm9200-clk-main"; - #clock-cells = <0>; - clocks = <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0 - 695000000 750000000 1 0 - 645000000 700000000 2 0 - 595000000 650000000 3 0 - 545000000 600000000 0 1 - 495000000 555000000 1 1 - 445000000 500000000 2 1 - 400000000 450000000 3 1>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKU>; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91rm9200-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <0 133333333>; - atmel,clk-divisors = <1 2 4 3>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9g45-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91rm9200-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <3>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <4>; - }; - - pioDE_clk: pioDE_clk { - #clock-cells = <0>; - reg = <5>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <8>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <9>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <10>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <11>; - }; - - twi0_clk: twi0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <14>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <15>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <16>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <17>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <18>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <19>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <20>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - lcd_clk: lcd_clk { - #clock-cells = <0>; - reg = <23>; - }; - - ac97_clk: ac97_clk { - #clock-cells = <0>; - reg = <24>; - }; - - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <25>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <26>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <27>; - }; - - aestdessha_clk: aestdessha_clk { - #clock-cells = <0>; - reg = <28>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <29>; - }; - - vdec_clk: vdec_clk { - #clock-cells = <0>; - reg = <30>; - }; - }; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; }; rstc@fffffd00 { @@ -405,7 +143,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffd30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; @@ -421,7 +159,7 @@ #size-cells = <0>; reg = <0xfff7c000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -431,7 +169,7 @@ #size-cells = <0>; reg = <0xfffd4000 0x100>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -440,7 +178,7 @@ reg = <0xffffec00 0x200>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "dma_clk"; }; @@ -883,7 +621,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff400 { @@ -894,7 +632,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioC: gpio@fffff600 { @@ -905,7 +643,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioC_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; }; pioD: gpio@fffff800 { @@ -916,7 +654,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioDE_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; }; pioE: gpio@fffffa00 { @@ -927,7 +665,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioDE_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; }; }; @@ -937,7 +675,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -950,7 +688,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -963,7 +701,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; @@ -976,7 +714,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "usart"; status = "disabled"; }; @@ -989,7 +727,7 @@ atmel,use-dma-tx; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; clock-names = "usart"; status = "disabled"; }; @@ -1000,7 +738,7 @@ interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb_rmii>; - clocks = <&macb0_clk>, <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_PERIPHERAL 25>; clock-names = "hclk", "pclk"; status = "disabled"; }; @@ -1009,7 +747,7 @@ compatible = "atmel,at91sam9g45-trng"; reg = <0xfffcc000 0x100>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; }; i2c0: i2c@fff84000 { @@ -1020,7 +758,7 @@ pinctrl-0 = <&pinctrl_i2c0>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; status = "disabled"; }; @@ -1032,7 +770,7 @@ pinctrl-0 = <&pinctrl_i2c1>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; status = "disabled"; }; @@ -1042,7 +780,7 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "pclk"; status = "disabled"; }; @@ -1053,7 +791,7 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; clock-names = "pclk"; status = "disabled"; }; @@ -1064,7 +802,7 @@ interrupts = <24 IRQ_TYPE_LEVEL_HIGH 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ac97>; - clocks = <&ac97_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; clock-names = "ac97_clk"; status = "disabled"; }; @@ -1075,7 +813,7 @@ compatible = "atmel,at91sam9g45-adc"; reg = <0xfffb0000 0x100>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&adc_clk>, <&adc_op_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>; clock-names = "adc_clk", "adc_op_clk"; atmel,adc-channels-used = <0xff>; atmel,adc-vref = <3300>; @@ -1111,7 +849,7 @@ compatible = "atmel,at91sam9g45-isi"; reg = <0xfffb4000 0x4000>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&isi_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; clock-names = "isi_clk"; status = "disabled"; port { @@ -1125,7 +863,7 @@ reg = <0xfffb8000 0x300>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; status = "disabled"; }; @@ -1138,7 +876,7 @@ dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; clock-names = "mci_clk"; status = "disabled"; }; @@ -1152,7 +890,7 @@ dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; clock-names = "mci_clk"; status = "disabled"; }; @@ -1176,7 +914,7 @@ interrupts = <14 4 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "spi_clk"; status = "disabled"; }; @@ -1189,73 +927,19 @@ interrupts = <15 4 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "spi_clk"; status = "disabled"; }; usb2: gadget@fff78000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9g45-udc"; reg = <0x00600000 0x80000 0xfff78000 0x400>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&udphs_clk>, <&utmi>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; }; clk32k: sckc@fffffd50 { @@ -1294,7 +978,7 @@ interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fb>; - clocks = <&lcd_clk>, <&lcd_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "hclk", "lcdc_clk"; status = "disabled"; }; @@ -1303,7 +987,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1312,7 +996,7 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; @@ -1330,7 +1014,7 @@ 0x3 0x0 0x40000000 0x10000000 0x4 0x0 0x50000000 0x10000000 0x5 0x0 0x60000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { diff --git a/src/arm/at91sam9m10g45ek.dts b/src/arm/at91sam9m10g45ek.dts index 84bed6f55fcd..a3a5c82d9f29 100644 --- a/src/arm/at91sam9m10g45ek.dts +++ b/src/arm/at91sam9m10g45ek.dts @@ -72,9 +72,9 @@ pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>; resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>; pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>; - clocks = <&pck1>; + clocks = <&pmc PMC_TYPE_SYSTEM 9>; clock-names = "xvclk"; - assigned-clocks = <&pck1>; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; assigned-clock-rates = <25000000>; port { diff --git a/src/arm/at91sam9n12.dtsi b/src/arm/at91sam9n12.dtsi index ea675174432e..a994d076dc7e 100644 --- a/src/arm/at91sam9n12.dtsi +++ b/src/arm/at91sam9n12.dtsi @@ -104,7 +104,7 @@ ramc0: ramc@ffffe800 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe800 0x200>; - clocks = <&ddrck>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; clock-names = "ddrck"; }; @@ -116,278 +116,10 @@ pmc: pmc@fffffc00 { compatible = "atmel,at91sam9n12-pmc", "syscon"; reg = <0xfffffc00 0x200>; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCRCS>; - clock-frequency = <12000000>; - clock-accuracy = <50000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCS>; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MOSCSELS>; - clocks = <&main_rc_osc>, <&main_osc>; - }; - - plla: pllack { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKA>; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <745000000 800000000 0 0>, - <695000000 750000000 1 0>, - <645000000 700000000 2 0>, - <595000000 650000000 3 0>, - <545000000 600000000 0 1>, - <495000000 555000000 1 1>, - <445000000 500000000 2 1>, - <400000000 450000000 3 1>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - pllb: pllbck { - compatible = "atmel,at91rm9200-clk-pll"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_LOCKB>; - clocks = <&main>; - reg = <1>; - atmel,clk-input-range = <2000000 32000000>; - #atmel,pll-clk-output-range-cells = <3>; - atmel,pll-clk-output-ranges = <30000000 100000000 0>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>; - atmel,clk-output-range = <0 133333333>; - atmel,clk-divisors = <1 2 4 3>; - atmel,master-clk-have-div3-pres; - }; - - usb: usbck { - compatible = "atmel,at91sam9n12-clk-usb"; - #clock-cells = <0>; - clocks = <&pllb>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - }; - - periphck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - pioAB_clk: pioAB_clk { - #clock-cells = <0>; - reg = <2>; - }; - - pioCD_clk: pioCD_clk { - #clock-cells = <0>; - reg = <3>; - }; - - fuse_clk: fuse_clk { - #clock-cells = <0>; - reg = <4>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <5>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <6>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <7>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <8>; - }; - - twi0_clk: twi0_clk { - reg = <9>; - #clock-cells = <0>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <10>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <12>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <13>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <14>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <15>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <16>; - }; - - tcb_clk: tcb_clk { - #clock-cells = <0>; - reg = <17>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <18>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <19>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <20>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <22>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <23>; - }; - - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <25>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <27>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <28>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <29>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <30>; - }; - }; }; rstc@fffffe00 { @@ -400,7 +132,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; shdwc@fffffe10 { @@ -439,7 +171,7 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; dma-names = "rxtx"; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "mci_clk"; #address-cells = <1>; #size-cells = <0>; @@ -452,7 +184,7 @@ #size-cells = <0>; reg = <0xf8008000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -462,7 +194,7 @@ #size-cells = <0>; reg = <0xf800c000 0x100>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -470,7 +202,7 @@ compatible = "atmel,at91sam9n12-hlcdc"; reg = <0xf8038000 0x2000>; interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; clock-names = "periph_clk", "sys_clk", "slow_clk"; status = "disabled"; @@ -499,7 +231,7 @@ reg = <0xffffec00 0x200>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; clock-names = "dma_clk"; }; @@ -817,7 +549,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioAB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioB: gpio@fffff600 { @@ -828,7 +560,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioAB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; }; pioC: gpio@fffff800 { @@ -839,7 +571,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioCD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; pioD: gpio@fffffa00 { @@ -850,7 +582,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioCD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; }; }; @@ -860,7 +592,7 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; clock-names = "usart"; status = "disabled"; }; @@ -874,7 +606,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; clock-names = "pclk"; status = "disabled"; }; @@ -885,7 +617,7 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; clock-names = "usart"; status = "disabled"; }; @@ -896,7 +628,7 @@ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; clock-names = "usart"; status = "disabled"; }; @@ -907,7 +639,7 @@ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; clock-names = "usart"; status = "disabled"; }; @@ -918,7 +650,7 @@ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; clock-names = "usart"; status = "disabled"; }; @@ -934,7 +666,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; status = "disabled"; }; @@ -949,7 +681,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&twi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; status = "disabled"; }; @@ -964,7 +696,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "spi_clk"; status = "disabled"; }; @@ -980,7 +712,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "spi_clk"; status = "disabled"; }; @@ -1009,7 +741,7 @@ reg = <0xf8034000 0x300>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; status = "disabled"; }; @@ -1017,7 +749,7 @@ compatible = "atmel,at91sam9260-udc"; reg = <0xf803c000 0x4000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&udpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_SYSTEM 7>; clock-names = "pclk", "hclk"; status = "disabled"; }; @@ -1027,7 +759,7 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x00100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1045,7 +777,7 @@ 0x3 0x0 0x40000000 0x10000000 0x4 0x0 0x50000000 0x10000000 0x5 0x0 0x60000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { diff --git a/src/arm/at91sam9n12ek.dts b/src/arm/at91sam9n12ek.dts index d36e162a8817..870b83ff6b97 100644 --- a/src/arm/at91sam9n12ek.dts +++ b/src/arm/at91sam9n12ek.dts @@ -59,7 +59,7 @@ wm8904: codec@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - clocks = <&pck0>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; clock-names = "mclk"; }; diff --git a/src/arm/at91sam9rl.dtsi b/src/arm/at91sam9rl.dtsi index ea024e4b6e09..4d70194fd808 100644 --- a/src/arm/at91sam9rl.dtsi +++ b/src/arm/at91sam9rl.dtsi @@ -299,8 +299,6 @@ }; usb0: gadget@fffd4000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9rl-udc"; reg = <0x00600000 0x100000>, <0xfffd4000 0x4000>; @@ -308,58 +306,6 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; }; dma0: dma-controller@ffffe600 { diff --git a/src/arm/at91sam9x5.dtsi b/src/arm/at91sam9x5.dtsi index 7c2eb93f8cac..948fe99ab6c3 100644 --- a/src/arm/at91sam9x5.dtsi +++ b/src/arm/at91sam9x5.dtsi @@ -867,8 +867,6 @@ }; usb2: gadget@f803c000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,at91sam9g45-udc"; reg = <0x00500000 0x80000 0xf803c000 0x400>; @@ -876,58 +874,6 @@ clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "hclk", "pclk"; status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; }; watchdog: watchdog@fffffe40 { diff --git a/src/arm/bcm-nsp.dtsi b/src/arm/bcm-nsp.dtsi index da6d70f09ef1..3175266ede64 100644 --- a/src/arm/bcm-nsp.dtsi +++ b/src/arm/bcm-nsp.dtsi @@ -200,7 +200,7 @@ status = "disabled"; }; - dma@20000 { + dma: dma@20000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x20000 0x1000>; interrupts = , @@ -215,6 +215,8 @@ clocks = <&iprocslow>; clock-names = "apb_pclk"; #dma-cells = <1>; + dma-coherent; + status = "disabled"; }; sdio: sdhci@21000 { @@ -257,10 +259,10 @@ status = "disabled"; }; - mailbox: mailbox@25000 { + mailbox: mailbox@25c00 { compatible = "brcm,iproc-fa2-mbox"; - reg = <0x25000 0x445>; - interrupts = ; + reg = <0x25c00 0x400>; + interrupts = ; #mbox-cells = <1>; brcm,rx-status-len = <32>; brcm,use-bcm-hdr; diff --git a/src/arm/bcm2711-rpi-4-b.dts b/src/arm/bcm2711-rpi-4-b.dts index e26ea9006378..c7f1d97e69bb 100644 --- a/src/arm/bcm2711-rpi-4-b.dts +++ b/src/arm/bcm2711-rpi-4-b.dts @@ -56,6 +56,16 @@ 3300000 0x0>; status = "okay"; }; + + sd_vcc_reg: sd_vcc_reg { + compatible = "regulator-fixed"; + regulator-name = "vcc-sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>; + }; }; &firmware { @@ -69,7 +79,7 @@ "GLOBAL_RESET", "VDD_SD_IO_SEL", "CAM_GPIO", - "", + "SD_PWR_ON", ""; status = "okay"; }; @@ -174,6 +184,7 @@ /* EMMC2 is used to drive the SD card */ &emmc2 { vqmmc-supply = <&sd_io_1v8_reg>; + vmmc-supply = <&sd_vcc_reg>; broken-cd; status = "okay"; }; diff --git a/src/arm/bcm2835-common.dtsi b/src/arm/bcm2835-common.dtsi index 2b1d9d4c0cde..4119271c979d 100644 --- a/src/arm/bcm2835-common.dtsi +++ b/src/arm/bcm2835-common.dtsi @@ -130,7 +130,6 @@ compatible = "brcm,bcm2835-v3d"; reg = <0x7ec00000 0x1000>; interrupts = <1 10>; - power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; }; vc4: gpu { diff --git a/src/arm/bcm2835-rpi-common.dtsi b/src/arm/bcm2835-rpi-common.dtsi new file mode 100644 index 000000000000..8a55b6cded59 --- /dev/null +++ b/src/arm/bcm2835-rpi-common.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This include file covers the common peripherals and configuration between + * bcm2835, bcm2836 and bcm2837 implementations that interact with RPi's + * firmware interface. + */ + +#include + +&v3d { + power-domains = <&power RPI_POWER_DOMAIN_V3D>; +}; diff --git a/src/arm/bcm2835.dtsi b/src/arm/bcm2835.dtsi index 53bf4579cc22..0549686134ea 100644 --- a/src/arm/bcm2835.dtsi +++ b/src/arm/bcm2835.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "bcm283x.dtsi" #include "bcm2835-common.dtsi" +#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2835"; diff --git a/src/arm/bcm2836.dtsi b/src/arm/bcm2836.dtsi index 82d6c4662ae4..b390006aef79 100644 --- a/src/arm/bcm2836.dtsi +++ b/src/arm/bcm2836.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "bcm283x.dtsi" #include "bcm2835-common.dtsi" +#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2836"; diff --git a/src/arm/bcm2837.dtsi b/src/arm/bcm2837.dtsi index 9e95fee78e19..0199ec98cd61 100644 --- a/src/arm/bcm2837.dtsi +++ b/src/arm/bcm2837.dtsi @@ -1,5 +1,6 @@ #include "bcm283x.dtsi" #include "bcm2835-common.dtsi" +#include "bcm2835-rpi-common.dtsi" / { compatible = "brcm,bcm2837"; diff --git a/src/arm/bcm47094-luxul-xwc-2000.dts b/src/arm/bcm47094-luxul-xwc-2000.dts index 334325390aed..29bbecd36f65 100644 --- a/src/arm/bcm47094-luxul-xwc-2000.dts +++ b/src/arm/bcm47094-luxul-xwc-2000.dts @@ -17,6 +17,7 @@ }; memory { + device_type = "memory"; reg = <0x00000000 0x08000000 0x88000000 0x18000000>; }; diff --git a/src/arm/bcm958522er.dts b/src/arm/bcm958522er.dts index 8c388eb8a08f..7be4c4e628e0 100644 --- a/src/arm/bcm958522er.dts +++ b/src/arm/bcm958522er.dts @@ -58,6 +58,10 @@ /* USB 3 support needed to be complete */ +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/src/arm/bcm958525er.dts b/src/arm/bcm958525er.dts index c339771bb22e..e58ed7e95346 100644 --- a/src/arm/bcm958525er.dts +++ b/src/arm/bcm958525er.dts @@ -58,6 +58,10 @@ /* USB 3 support needed to be complete */ +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/src/arm/bcm958525xmc.dts b/src/arm/bcm958525xmc.dts index 1c72ec8288de..716da62f5788 100644 --- a/src/arm/bcm958525xmc.dts +++ b/src/arm/bcm958525xmc.dts @@ -58,6 +58,10 @@ /* XHCI support needed to be complete */ +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/src/arm/bcm958622hr.dts b/src/arm/bcm958622hr.dts index 96a021cebd97..a49c2fd21f4a 100644 --- a/src/arm/bcm958622hr.dts +++ b/src/arm/bcm958622hr.dts @@ -58,6 +58,10 @@ /* USB 3 and SLIC support needed to be complete */ +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/src/arm/bcm958623hr.dts b/src/arm/bcm958623hr.dts index b2c7f21d471e..dd6dff6452b8 100644 --- a/src/arm/bcm958623hr.dts +++ b/src/arm/bcm958623hr.dts @@ -58,6 +58,10 @@ /* USB 3 and SLIC support needed to be complete */ +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/src/arm/bcm958625hr.dts b/src/arm/bcm958625hr.dts index 536fb24f38bb..a71371b4065e 100644 --- a/src/arm/bcm958625hr.dts +++ b/src/arm/bcm958625hr.dts @@ -69,6 +69,10 @@ status = "okay"; }; +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/src/arm/bcm958625k.dts b/src/arm/bcm958625k.dts index 3fcca12d83c2..7b84b54436ed 100644 --- a/src/arm/bcm958625k.dts +++ b/src/arm/bcm958625k.dts @@ -48,6 +48,10 @@ }; }; +&dma { + status = "okay"; +}; + &amac0 { status = "okay"; }; diff --git a/src/arm/berlin2.dtsi b/src/arm/berlin2.dtsi index d2f7d984bba5..3ab3cd250da7 100644 --- a/src/arm/berlin2.dtsi +++ b/src/arm/berlin2.dtsi @@ -77,7 +77,7 @@ ranges = <0 0xf7000000 0x1000000>; - sdhci0: sdhci@ab0000 { + sdhci0: mmc@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; @@ -86,7 +86,7 @@ status = "disabled"; }; - sdhci1: sdhci@ab0800 { + sdhci1: mmc@ab0800 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0800 0x200>; clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>; @@ -95,7 +95,7 @@ status = "disabled"; }; - sdhci2: sdhci@ab1000 { + sdhci2: mmc@ab1000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab1000 0x200>; interrupts = ; diff --git a/src/arm/berlin2cd.dtsi b/src/arm/berlin2cd.dtsi index e5c1f4213ff9..7cf3e6302d75 100644 --- a/src/arm/berlin2cd.dtsi +++ b/src/arm/berlin2cd.dtsi @@ -62,7 +62,7 @@ ranges = <0 0xf7000000 0x1000000>; - sdhci0: sdhci@ab0000 { + sdhci0: mmc@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; diff --git a/src/arm/berlin2q.dtsi b/src/arm/berlin2q.dtsi index 99d6872a6dfc..c44a32e873f4 100644 --- a/src/arm/berlin2q.dtsi +++ b/src/arm/berlin2q.dtsi @@ -122,7 +122,7 @@ ranges = <0 0xf7000000 0x1000000>; interrupt-parent = <&gic>; - sdhci0: sdhci@ab0000 { + sdhci0: mmc@ab0000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0000 0x200>; clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; @@ -131,7 +131,7 @@ status = "disabled"; }; - sdhci1: sdhci@ab0800 { + sdhci1: mmc@ab0800 { compatible = "mrvl,pxav3-mmc"; reg = <0xab0800 0x200>; clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; @@ -140,7 +140,7 @@ status = "disabled"; }; - sdhci2: sdhci@ab1000 { + sdhci2: mmc@ab1000 { compatible = "mrvl,pxav3-mmc"; reg = <0xab1000 0x200>; interrupts = ; diff --git a/src/arm/dm814x.dtsi b/src/arm/dm814x.dtsi index c28ca0540f03..7702e048e110 100644 --- a/src/arm/dm814x.dtsi +++ b/src/arm/dm814x.dtsi @@ -308,14 +308,30 @@ ti,hwmods = "mcspi4"; }; - timer1: timer@2e000 { - compatible = "ti,dm814-timer"; - reg = <0x2e000 0x2000>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; + timer1_target: target-module@2e000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x2e000 0x4>, + <0x2e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; clocks = <&timer1_fck>; clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2e000 0x1000>; + + timer1: timer@0 { + compatible = "ti,am335x-timer-1ms"; + reg = <0x0 0x400>; + interrupts = <67>; + ti,timer-alwon; + clocks = <&timer1_fck>; + clock-names = "fck"; + }; }; uart1: uart@20000 { @@ -348,13 +364,29 @@ dma-names = "tx", "rx"; }; - timer2: timer@40000 { - compatible = "ti,dm814-timer"; - reg = <0x40000 0x2000>; - interrupts = <68>; - ti,hwmods = "timer2"; + timer2_target: target-module@40000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x40000 0x4>, + <0x40010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; clocks = <&timer2_fck>; clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x40000 0x1000>; + + timer2: timer@0 { + compatible = "ti,dm814-timer"; + reg = <0 0x1000>; + interrupts = <68>; + clocks = <&timer2_fck>; + clock-names = "fck"; + }; }; timer3: timer@42000 { @@ -735,3 +767,23 @@ }; #include "dm814x-clocks.dtsi" + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&devosc_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&devosc_ck>; + }; +}; diff --git a/src/arm/dm816x.dtsi b/src/arm/dm816x.dtsi index 2a4934b60ded..3551a64963f8 100644 --- a/src/arm/dm816x.dtsi +++ b/src/arm/dm816x.dtsi @@ -440,23 +440,55 @@ dma-names = "tx", "rx"; }; - timer1: timer@4802e000 { - compatible = "ti,dm816-timer"; - reg = <0x4802e000 0x2000>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; - clocks = <&timer1_fck>; + timer1_target: target-module@4802e000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x4802e000 0x4>, + <0x4802e010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4802e000 0x1000>; + + timer1: timer@0 { + compatible = "ti,dm816-timer"; + reg = <0 0x1000>; + interrupts = <67>; + ti,timer-alwon; + clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>; + clock-names = "fck"; + }; }; - timer2: timer@48040000 { - compatible = "ti,dm816-timer"; - reg = <0x48040000 0x2000>; - interrupts = <68>; - ti,hwmods = "timer2"; - clocks = <&timer2_fck>; + timer2_target: target-module@48040000 { + compatible = "ti,sysc-omap4-timer", "ti,sysc"; + reg = <0x48040000 0x4>, + <0x48040010 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-mask = ; + ti,sysc-sidle = , + , + , + ; + clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48040000 0x1000>; + + timer2: timer@0 { + compatible = "ti,dm816-timer"; + reg = <0 0x1000>; + interrupts = <68>; + clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>; + clock-names = "fck"; + }; }; timer3: timer@48042000 { @@ -642,3 +674,23 @@ }; #include "dm816x-clocks.dtsi" + +/* Preferred always-on timer for clocksource */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer1_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&timer2_fck>; + assigned-clock-parents = <&sys_clkin_ck>; + }; +}; diff --git a/src/arm/dove.dtsi b/src/arm/dove.dtsi index 3081b04e8c08..89e0bdaf3a85 100644 --- a/src/arm/dove.dtsi +++ b/src/arm/dove.dtsi @@ -175,7 +175,6 @@ #size-cells = <0>; interrupts = <11>; clock-frequency = <400000>; - timeout-ms = <1000>; clocks = <&core_clk 0>; status = "okay"; }; @@ -248,7 +247,7 @@ marvell,#interrupts = <5>; }; - intc: main-interrupt-ctrl@20200 { + intc: interrupt-controller@20200 { compatible = "marvell,orion-intc"; interrupt-controller; #interrupt-cells = <1>; diff --git a/src/arm/dra7-evm-common.dtsi b/src/arm/dra7-evm-common.dtsi index 23244b5a9942..2cf6a529d4ad 100644 --- a/src/arm/dra7-evm-common.dtsi +++ b/src/arm/dra7-evm-common.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ */ +#include "dra74-ipu-dsp-common.dtsi" #include #include #include @@ -244,26 +245,6 @@ rx-num-evt = <32>; }; -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; -}; - &pcie1_rc { status = "okay"; }; diff --git a/src/arm/dra7-evm.dts b/src/arm/dra7-evm.dts index af06a55d1c5c..7aeb30daf3b8 100644 --- a/src/arm/dra7-evm.dts +++ b/src/arm/dra7-evm.dts @@ -35,6 +35,40 @@ regulator-max-microvolt = <1800000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_memory_region: dsp2-memory@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + evm_3v3_sd: fixedregulator-sd { compatible = "regulator-fixed"; regulator-name = "evm_3v3_sd"; @@ -537,3 +571,23 @@ pinctrl-1 = <&dcan1_pins_sleep>; pinctrl-2 = <&dcan1_pins_default>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_memory_region>; +}; diff --git a/src/arm/dra7-ipu-dsp-common.dtsi b/src/arm/dra7-ipu-dsp-common.dtsi new file mode 100644 index 000000000000..a25749a1c365 --- /dev/null +++ b/src/arm/dra7-ipu-dsp-common.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common IPU and DSP data for TI DRA7xx/AM57xx platforms + */ + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; +}; + +&ipu2 { + mboxes = <&mailbox6 &mbox_ipu2_ipc3x>; + ti,timers = <&timer3>; + ti,watchdog-timers = <&timer4>, <&timer9>; +}; + +&ipu1 { + mboxes = <&mailbox5 &mbox_ipu1_ipc3x>; + ti,timers = <&timer11>; + ti,watchdog-timers = <&timer7>, <&timer8>; +}; + +&dsp1 { + mboxes = <&mailbox5 &mbox_dsp1_ipc3x>; + ti,timers = <&timer5>; + ti,watchdog-timers = <&timer10>; +}; diff --git a/src/arm/dra7-l4.dtsi b/src/arm/dra7-l4.dtsi index 2119a78e9c15..0c6f26605506 100644 --- a/src/arm/dra7-l4.dtsi +++ b/src/arm/dra7-l4.dtsi @@ -1143,7 +1143,6 @@ target-module@32000 { /* 0x48032000, ap 5 3e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer2"; reg = <0x32000 0x4>, <0x32010 0x4>; reg-names = "rev", "sysc"; @@ -1163,15 +1162,14 @@ timer2: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; target-module@34000 { /* 0x48034000, ap 7 46.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer3"; reg = <0x34000 0x4>, <0x34010 0x4>; reg-names = "rev", "sysc"; @@ -1191,15 +1189,14 @@ timer3: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; target-module@36000 { /* 0x48036000, ap 9 4e.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer4"; reg = <0x36000 0x4>, <0x36010 0x4>; reg-names = "rev", "sysc"; @@ -1219,8 +1216,8 @@ timer4: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -1246,8 +1243,8 @@ timer9: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -1853,8 +1850,8 @@ timer10: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -1880,8 +1877,8 @@ timer11: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -3363,8 +3360,8 @@ timer5: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -3390,8 +3387,8 @@ timer6: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -3417,8 +3414,8 @@ timer7: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -3444,8 +3441,8 @@ timer8: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; }; }; @@ -3471,8 +3468,8 @@ timer13: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-pwm; }; @@ -3499,8 +3496,8 @@ timer14: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-pwm; }; @@ -3527,8 +3524,8 @@ timer15: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-pwm; }; @@ -3555,8 +3552,8 @@ timer16: timer@0 { compatible = "ti,omap5430-timer"; reg = <0x0 0x80>; - clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>; - clock-names = "fck"; + clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>; + clock-names = "fck", "timer_sys_ck"; interrupts = ; ti,timer-pwm; }; @@ -4295,7 +4292,6 @@ target-module@4000 { /* 0x4ae04000, ap 15 40.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; reg = <0x4000 0x4>, <0x4010 0x4>; reg-names = "rev", "sysc"; @@ -4430,9 +4426,8 @@ }; }; - target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ + timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer1"; reg = <0x8000 0x4>, <0x8010 0x4>; reg-names = "rev", "sysc"; diff --git a/src/arm/dra7.dtsi b/src/arm/dra7.dtsi index 7191ee6a1b82..099546be5014 100644 --- a/src/arm/dra7.dtsi +++ b/src/arm/dra7.dtsi @@ -410,6 +410,42 @@ ti,hwmods = "dmm"; }; + ipu1: ipu@58820000 { + compatible = "ti,dra7-ipu"; + reg = <0x58820000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu1>; + status = "disabled"; + resets = <&prm_ipu 0>, <&prm_ipu 1>; + clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>; + firmware-name = "dra7-ipu1-fw.xem4"; + }; + + ipu2: ipu@55020000 { + compatible = "ti,dra7-ipu"; + reg = <0x55020000 0x10000>; + reg-names = "l2ram"; + iommus = <&mmu_ipu2>; + status = "disabled"; + resets = <&prm_core 0>, <&prm_core 1>; + clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>; + firmware-name = "dra7-ipu2-fw.xem4"; + }; + + dsp1: dsp@40800000 { + compatible = "ti,dra7-dsp"; + reg = <0x40800000 0x48000>, + <0x40e00000 0x8000>, + <0x40f00000 0x8000>; + reg-names = "l2ram", "l1pram", "l1dram"; + ti,bootreg = <&scm_conf 0x55c 10>; + iommus = <&mmu0_dsp1>, <&mmu1_dsp1>; + status = "disabled"; + resets = <&prm_dsp1 0>; + clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>; + firmware-name = "dra7-dsp1-fw.xe66"; + }; + target-module@40d01000 { compatible = "ti,sysc-omap2", "ti,sysc"; reg = <0x40d01000 0x4>, @@ -1044,3 +1080,13 @@ reg = <0x1c00 0x60>; }; }; + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; + assigned-clock-parents = <&sys_32k_ck>; + }; +}; diff --git a/src/arm/dra71-evm.dts b/src/arm/dra71-evm.dts index fabeb7704753..a5d275ea7bd3 100644 --- a/src/arm/dra71-evm.dts +++ b/src/arm/dra71-evm.dts @@ -17,6 +17,33 @@ reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + vpo_sd_1v8_3v3: gpio-regulator-TPS74801 { compatible = "regulator-gpio"; @@ -270,3 +297,18 @@ &extcon_usb2 { vbus-gpio = <&pcf_lcd 15 GPIO_ACTIVE_HIGH>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; diff --git a/src/arm/dra72-evm-common.dtsi b/src/arm/dra72-evm-common.dtsi index 01558a86af82..c84b63bf0fc8 100644 --- a/src/arm/dra72-evm-common.dtsi +++ b/src/arm/dra72-evm-common.dtsi @@ -5,6 +5,7 @@ /dts-v1/; #include "dra72x.dtsi" +#include "dra7-ipu-dsp-common.dtsi" #include #include @@ -583,23 +584,6 @@ rx-num-evt = <32>; }; -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; -}; - &pcie1_rc { status = "okay"; }; diff --git a/src/arm/dra72-evm-revc.dts b/src/arm/dra72-evm-revc.dts index 2bb2e8be6276..6e70858f6313 100644 --- a/src/arm/dra72-evm-revc.dts +++ b/src/arm/dra72-evm-revc.dts @@ -14,6 +14,33 @@ reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + evm_1v8_sw: fixedregulator-evm_1v8 { compatible = "regulator-fixed"; regulator-name = "evm_1v8"; @@ -113,3 +140,18 @@ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; vmmc-supply = <&evm_1v8_sw>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_cma_pool>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_cma_pool>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_cma_pool>; +}; diff --git a/src/arm/dra72-evm.dts b/src/arm/dra72-evm.dts index 9adb77585ef1..951152fe206a 100644 --- a/src/arm/dra72-evm.dts +++ b/src/arm/dra72-evm.dts @@ -12,6 +12,33 @@ reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_memory_region: ipu2-memory@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_memory_region: dsp1-memory@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_memory_region: ipu1-memory@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + }; + evm_1v8_sw: fixedregulator-evm_1v8 { compatible = "regulator-fixed"; regulator-name = "evm_1v8"; @@ -78,3 +105,18 @@ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev10_conf>; vmmc-supply = <&evm_1v8_sw>; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_memory_region>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_memory_region>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_memory_region>; +}; diff --git a/src/arm/dra72x.dtsi b/src/arm/dra72x.dtsi index da334489b18f..ae23ec14e8fa 100644 --- a/src/arm/dra72x.dtsi +++ b/src/arm/dra72x.dtsi @@ -10,6 +10,12 @@ / { compatible = "ti,dra722", "ti,dra72", "ti,dra7"; + aliases { + rproc0 = &ipu1; + rproc1 = &ipu2; + rproc2 = &dsp1; + }; + pmu { compatible = "arm,cortex-a15-pmu"; interrupt-parent = <&wakeupgen>; diff --git a/src/arm/dra74-ipu-dsp-common.dtsi b/src/arm/dra74-ipu-dsp-common.dtsi new file mode 100644 index 000000000000..b1147a4b77f9 --- /dev/null +++ b/src/arm/dra74-ipu-dsp-common.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common IPU and DSP data for TI DRA74x/DRA76x/AM572x/AM574x platforms + */ + +#include "dra7-ipu-dsp-common.dtsi" + +&mailbox6 { + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +}; + +&dsp2 { + mboxes = <&mailbox6 &mbox_dsp2_ipc3x>; + ti,timers = <&timer6>; + ti,watchdog-timers = <&timer13>; +}; diff --git a/src/arm/dra74x.dtsi b/src/arm/dra74x.dtsi index 7b1c61298253..46d8e7615180 100644 --- a/src/arm/dra74x.dtsi +++ b/src/arm/dra74x.dtsi @@ -29,6 +29,13 @@ }; }; + aliases { + rproc0 = &ipu1; + rproc1 = &ipu2; + rproc2 = &dsp1; + rproc3 = &dsp2; + }; + pmu { compatible = "arm,cortex-a15-pmu"; interrupt-parent = <&wakeupgen>; @@ -124,6 +131,20 @@ ti,syscon-mmuconfig = <&dsp2_system 0x1>; }; }; + + dsp2: dsp@41000000 { + compatible = "ti,dra7-dsp"; + reg = <0x41000000 0x48000>, + <0x41600000 0x8000>, + <0x41700000 0x8000>; + reg-names = "l2ram", "l1pram", "l1dram"; + ti,bootreg = <&scm_conf 0x560 10>; + iommus = <&mmu0_dsp2>, <&mmu1_dsp2>; + status = "disabled"; + resets = <&prm_dsp2 0>; + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; + firmware-name = "dra7-dsp2-fw.xe66"; + }; }; }; diff --git a/src/arm/dra76-evm.dts b/src/arm/dra76-evm.dts index e958cb3d1b31..820a0ece20d4 100644 --- a/src/arm/dra76-evm.dts +++ b/src/arm/dra76-evm.dts @@ -25,6 +25,40 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipu2_cma_pool: ipu2_cma@95800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x95800000 0x0 0x3800000>; + reusable; + status = "okay"; + }; + + dsp1_cma_pool: dsp1_cma@99000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x99000000 0x0 0x4000000>; + reusable; + status = "okay"; + }; + + ipu1_cma_pool: ipu1_cma@9d000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9d000000 0x0 0x2000000>; + reusable; + status = "okay"; + }; + + dsp2_cma_pool: dsp2_cma@9f000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x9f000000 0x0 0x800000>; + reusable; + status = "okay"; + }; + }; + vsys_12v0: fixedregulator-vsys12v0 { /* main supply */ compatible = "regulator-fixed"; @@ -548,3 +582,23 @@ data-lanes = <1 2>; }; }; + +&ipu2 { + status = "okay"; + memory-region = <&ipu2_cma_pool>; +}; + +&ipu1 { + status = "okay"; + memory-region = <&ipu1_cma_pool>; +}; + +&dsp1 { + status = "okay"; + memory-region = <&dsp1_cma_pool>; +}; + +&dsp2 { + status = "okay"; + memory-region = <&dsp2_cma_pool>; +}; diff --git a/src/arm/e60k02.dtsi b/src/arm/e60k02.dtsi index ce50c4dc6f2a..3af1ab4458ef 100644 --- a/src/arm/e60k02.dtsi +++ b/src/arm/e60k02.dtsi @@ -117,6 +117,8 @@ ricoh619: pmic@32 { compatible = "ricoh,rc5t619"; reg = <0x32>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; system-power-controller; regulators { diff --git a/src/arm/exynos3250-monk.dts b/src/arm/exynos3250-monk.dts index 248bd372fe70..ca29d7ed8216 100644 --- a/src/arm/exynos3250-monk.dts +++ b/src/arm/exynos3250-monk.dts @@ -57,7 +57,8 @@ i2c_max77836: i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; diff --git a/src/arm/exynos3250-rinato.dts b/src/arm/exynos3250-rinato.dts index 86c26a4edfd7..aba8350cfdaf 100644 --- a/src/arm/exynos3250-rinato.dts +++ b/src/arm/exynos3250-rinato.dts @@ -50,9 +50,15 @@ }; }; + wlan_pwrseq: mshc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; + }; + i2c_max77836: i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&gpd0 2 GPIO_ACTIVE_HIGH>, <&gpd0 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpd0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpd0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; @@ -605,8 +611,6 @@ }; &mshc_0 { - #address-cells = <1>; - #size-cells = <0>; broken-cd; non-removable; cap-mmc-highspeed; @@ -625,10 +629,48 @@ status = "okay"; }; +&mshc_1 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus1 &sd1_bus4>; + bus-width = <4>; + + mmc-pwrseq = <&wlan_pwrseq>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4334-fmac"; + reg = <1>; + + interrupt-parent = <&gpx1>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + &serial_0 { assigned-clocks = <&cmu CLK_SCLK_UART0>; assigned-clock-rates = <100000000>; status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpe0 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + clocks = <&s2mps14_osc S2MPS11_CLK_BT>; + }; }; &serial_1 { diff --git a/src/arm/exynos4210-i9100.dts b/src/arm/exynos4210-i9100.dts new file mode 100644 index 000000000000..6d0c04d77a39 --- /dev/null +++ b/src/arm/exynos4210-i9100.dts @@ -0,0 +1,768 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4210 based Galaxy S2 (GT-I9100 version) device tree + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2020 Stenkin Evgeniy + * Copyright (c) 2020 Paul Cercueil + */ + +/dts-v1/; +#include "exynos4210.dtsi" +#include "exynos4412-ppmu-common.dtsi" + +#include +#include + +/ { + model = "Samsung Galaxy S2 (GT-I9100)"; + compatible = "samsung,i9100", "samsung,exynos4210", "samsung,exynos4"; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + vemmc_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VMEM_VDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + tsp_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "TSP_FIXED_VOLTAGES"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpl0 3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + cam_af_28v_reg: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "8M_AF_2.8V_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + cam_io_en_reg: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "CAM_IO_EN"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpe2 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + cam_io_12v_reg: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "8M_1.2V_EN"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpe2 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vt_core_15v_reg: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "VT_CORE_1.5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpe2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + gpio-keys { + compatible = "gpio-keys"; + + vol-down { + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume down"; + debounce-interval = <10>; + }; + + vol-up { + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume up"; + debounce-interval = <10>; + }; + + power { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "power"; + debounce-interval = <10>; + wakeup-source; + }; + + ok { + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "ok"; + debounce-interval = <10>; + }; + }; + + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; + }; + + i2c_max17042_fuel: i2c-gpio { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sda-gpios = <&gpy4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy4 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <5>; + + battery@36 { + compatible = "maxim,max17042"; + + interrupt-parent = <&gpx2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&max17042_fuel_irq>; + pinctrl-names = "default"; + + reg = <0x36>; + maxim,over-heat-temp = <700>; + maxim,over-volt = <4500>; + }; + }; + + spi-lcd { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + num-chipselects = <1>; + cs-gpios = <&gpy4 3 GPIO_ACTIVE_LOW>; + sck-gpios = <&gpy3 1 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpy3 3 GPIO_ACTIVE_HIGH>; + + lcd@0 { + compatible = "samsung,ld9040"; + reg = <0>; + + spi-max-frequency = <1200000>; + + vdd3-supply = <&vmipi_reg>; + vci-supply = <&vcclcd_reg>; + + reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; + power-on-delay = <10>; + reset-delay = <10>; + + panel-width-mm = <90>; + panel-height-mm = <154>; + + display-timings { + timing { + clock-frequency = <23492370>; + hactive = <480>; + vactive = <800>; + hback-porch = <16>; + hfront-porch = <16>; + vback-porch = <2>; + vfront-porch = <28>; + hsync-len = <2>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_dpi_ep>; + }; + }; + }; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 4 4>; + }; + }; + }; + }; +}; + +&camera { + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&varm_breg>; +}; + +&ehci { + status = "okay"; + + phys = <&exynos_usbphy 1>; + phy-names = "host"; +}; + +&exynos_usbphy { + status = "okay"; + + vbus-supply = <&safe1_sreg>; +}; + +&fimc_0 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC0>, <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_1 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC1>, <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_2 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC2>, <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimc_3 { + status = "okay"; + + assigned-clocks = <&clock CLK_MOUT_FIMC3>, <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; +}; + +&fimd { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + samsung,invert-vden; + samsung,invert-vclk; + + pinctrl-0 = <&lcd_clk>, <&lcd_data24>; + pinctrl-names = "default"; + + port@3 { + reg = <3>; + + fimd_dpi_ep: endpoint { + remote-endpoint = <&lcd_ep>; + }; + }; +}; + +&gpu { + status = "okay"; + + mali-supply = <&vg3d_breg>; + regulator-microvolt-offset = <50000>; + regulator-microsecs-delay = <50>; +}; + +&hsotg { + status = "okay"; + + dr_mode = "otg"; + vusb_d-supply = <&vusb_reg>; + vusb_a-supply = <&vusbdac_reg>; +}; + +&i2c_3 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + + mxt224-touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + + interrupt-parent = <&gpx0>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c_5 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + + pinctrl-0 = <&i2c5_bus>; + pinctrl-names = "default"; + + max8997_pmic@66 { + compatible = "maxim,max8997-pmic"; + reg = <0x66>; + + interrupts-extended = <&gpx0 7 IRQ_TYPE_NONE>, + <&gpx2 3 IRQ_TYPE_EDGE_FALLING>; + + max8997,pmic-buck1-uses-gpio-dvs; + max8997,pmic-buck2-uses-gpio-dvs; + max8997,pmic-buck5-uses-gpio-dvs; + + max8997,pmic-ignore-gpiodvs-side-effect; + max8997,pmic-buck125-default-dvs-idx = <0>; + + max8997,pmic-buck125-dvs-gpios = <&gpx0 5 GPIO_ACTIVE_HIGH>, + <&gpx0 6 GPIO_ACTIVE_HIGH>, + <&gpl0 0 GPIO_ACTIVE_HIGH>; + + max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + max8997,pmic-buck2-dvs-voltage = <1100000>, <1000000>, + <950000>, <900000>, + <1100000>, <1000000>, + <950000>, <900000>; + + max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + pinctrl-0 = <&max8997_irq>, <&otg_gp>, <&usb_sel>; + pinctrl-names = "default"; + + regulators { + vadc_reg: LDO1 { + regulator-name = "VADC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + + }; + valive_reg: LDO2 { + regulator-name = "VALIVE_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + }; + + vusb_reg: LDO3 { + regulator-name = "VUSB_1.1V_C210"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vmipi_reg: LDO4 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vhsic_reg: LDO5 { + regulator-name = "VHSIC_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vpda_reg: LDO6 { + regulator-name = "VCC_1.8V_PDA"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcam_reg: LDO7 { + regulator-name = "CAM_ISP_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vusbdac_reg: LDO8 { + regulator-name = "VUSB+VDAC_3.3V_C210"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccpda_reg: LDO9 { + regulator-name = "VCC_2.8V_PDA"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vtouch_reg: LDO11 { + regulator-name = "TOUCH_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + vpll_reg: LDO10 { + regulator-name = "VPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vtcam_reg: LDO12 { + regulator-name = "VT_CAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcclcd_reg: LDO13 { + regulator-name = "VCC_3.0V_LCD"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + vmotor_reg: LDO14 { + regulator-name = "VCC_2.8V_MOTOR"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vled_reg: LDO15 { + regulator-name = "LED_A_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + camsensor_reg: LDO16 { + regulator-name = "CAM_SENSOR_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vtf_reg: LDO17 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vtouchled_reg: LDO18 { + regulator-name = "TOUCH_LED_3.3V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + vddq_reg: LDO21 { + regulator-name = "VDDQ_M1M2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + varm_breg: BUCK1 { + regulator-name = "VARM_1.2V_C210"; + regulator-min-microvolt = <65000>; + regulator-max-microvolt = <2225000>; + regulator-always-on; + }; + + vint_breg: BUCK2 { + regulator-name = "VINT_1.1V_C210"; + regulator-min-microvolt = <65000>; + regulator-max-microvolt = <2225000>; + regulator-always-on; + }; + + vg3d_breg: BUCK3 { + regulator-name = "G3D_1.1V"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + camisp_breg: BUCK4 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vmem_breg: BUCK5 { + regulator-name = "VMEM_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vccsub_breg: BUCK7 { + regulator-name = "VCC_SUB_2.0V"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + safe1_sreg: ESAFEOUT1 { + regulator-name = "SAFEOUT1"; + }; + + safe2_sreg: ESAFEOUT2 { + regulator-name = "SAFEOUT2"; + regulator-boot-on; + }; + + charger_reg: CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <60000>; + regulator-max-microamp = <2580000>; + regulator-always-on; + }; + + chargercv_reg: CHARGER_CV { + regulator-name = "CHARGER_CV"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <4100000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c_7 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + + pinctrl-0 = <&i2c7_bus>; + pinctrl-names = "default"; + + ak8975@c { + compatible = "asahi-kasei,ak8975"; + reg = <0x0c>; + + gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + sleep0: sleep-states { + gpa0-0 { + samsung,pins = "gpa0-0"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + gpa0-1 { + samsung,pins = "gpa0-1"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + gpa0-2 { + samsung,pins = "gpa0-2"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + gpa0-3 { + samsung,pins = "gpa0-3"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + }; +}; + +&pinctrl_1 { + mhl_int: mhl-int { + samsung,pins = "gpf3-5"; + samsung,pin-pud = ; + }; + + i2c_mhl_bus: i2c-mhl-bus { + samsung,pins = "gpf0-4", "gpf0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + usb_sel: usb-sel { + samsung,pins = "gpl0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + bt_en: bt-en { + samsung,pins = "gpl0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + bt_res: bt-res { + samsung,pins = "gpl1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + otg_gp: otg-gp { + samsung,pins = "gpx3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + mag_mhl_gpio: mag-mhl-gpio { + samsung,pins = "gpd0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + max8997_irq: max8997-irq { + samsung,pins = "gpx0-7"; + samsung,pin-pud = ; + }; + + max17042_fuel_irq: max17042-fuel-irq { + samsung,pins = "gpx2-3"; + samsung,pin-pud = ; + }; + + tsp224_irq: tsp224-irq { + samsung,pins = "gpx0-4"; + samsung,pin-pud = ; + }; +}; + +&sdhci_0 { + status = "okay"; + + bus-width = <8>; + non-removable; + vmmc-supply = <&vemmc_reg>; + + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_bus8>; + pinctrl-names = "default"; +}; + +&sdhci_2 { + status = "okay"; + + bus-width = <4>; + cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vtf_reg>; + + pinctrl-0 = <&sd2_clk>, <&sd2_cmd>, <&sd2_bus4>; + pinctrl-names = "default"; +}; + +&sdhci_3 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + vmmc-supply = <&vtf_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4330-fmac"; + reg = <1>; + + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&serial_0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&bt_en>, <&bt_res>, <&uart0_data>, <&uart0_fctl>; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + + shutdown-gpios = <&gpl0 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpl1 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&tmu { + status = "okay"; +}; diff --git a/src/arm/exynos4210-origen.dts b/src/arm/exynos4210-origen.dts index 0d1e1a9c2f6e..890525b10d22 100644 --- a/src/arm/exynos4210-origen.dts +++ b/src/arm/exynos4210-origen.dts @@ -251,12 +251,7 @@ }; buck1_reg: BUCK1 { - /* - * HACK: The real name is VDD_ARM_1.2V, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM_1.2V"; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1350000>; regulator-always-on; diff --git a/src/arm/exynos4210-trats.dts b/src/arm/exynos4210-trats.dts index 7c39dd1c4d3a..3d791db6095c 100644 --- a/src/arm/exynos4210-trats.dts +++ b/src/arm/exynos4210-trats.dts @@ -121,6 +121,11 @@ }; }; + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpl1 2 GPIO_ACTIVE_LOW>; + }; + fixed-rate-clocks { xxti { compatible = "samsung,clock-xxti"; @@ -280,11 +285,10 @@ max8997_pmic@66 { compatible = "maxim,max8997-pmic"; - interrupts-extended = <&gpx0 7 0>, <&gpx2 3 0>; reg = <0x66>; - interrupt-parent = <&gpx0>; - interrupts = <7 IRQ_TYPE_NONE>; + interrupts-extended = <&gpx0 7 IRQ_TYPE_LEVEL_LOW>, + <&gpx2 3 IRQ_TYPE_EDGE_FALLING>; max8997,pmic-buck1-uses-gpio-dvs; max8997,pmic-buck2-uses-gpio-dvs; @@ -403,12 +407,7 @@ }; varm_breg: BUCK1 { - /* - * HACK: The real name is VARM_1.2V_C210, - * but exynos-cpufreq does not support - * DT-based regulator lookup yet. - */ - regulator-name = "vdd_arm"; + regulator-name = "VARM_1.2V_C210"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -471,6 +470,30 @@ status = "okay"; }; +&sdhci_3 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + vmmc-supply = <&tflash_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4330-fmac"; + reg = <1>; + + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + &serial_0 { status = "okay"; }; diff --git a/src/arm/exynos4210-universal_c210.dts b/src/arm/exynos4210-universal_c210.dts index 9dda6bdb9253..02fde1a75ebd 100644 --- a/src/arm/exynos4210-universal_c210.dts +++ b/src/arm/exynos4210-universal_c210.dts @@ -50,6 +50,11 @@ enable-active-high; }; + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpe3 1 GPIO_ACTIVE_LOW>; + }; + gpio-keys { compatible = "gpio-keys"; @@ -164,7 +169,8 @@ hdmi_ddc: i2c-ddc { compatible = "i2c-gpio"; - gpios = <&gpe4 2 GPIO_ACTIVE_HIGH &gpe4 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpe4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpe4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <100>; #address-cells = <1>; #size-cells = <0>; @@ -317,7 +323,7 @@ max8952,sync-freq = <0>; max8952,ramp-speed = <0>; - regulator-name = "vdd_arm"; + regulator-name = "VARM_1.2V_C210"; regulator-min-microvolt = <770000>; regulator-max-microvolt = <1400000>; regulator-always-on; @@ -563,6 +569,29 @@ status = "okay"; }; +&sdhci_3 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wlan_pwrseq>; + vmmc-supply = <&ldo5_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>; + + brcmf: wifi@1 { + compatible = "brcm,bcm4330-fmac"; + reg = <1>; + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + &serial_0 { status = "okay"; /delete-property/dmas; diff --git a/src/arm/exynos4412-galaxy-s3.dtsi b/src/arm/exynos4412-galaxy-s3.dtsi index 44f97546dd0a..53b3ca3effab 100644 --- a/src/arm/exynos4412-galaxy-s3.dtsi +++ b/src/arm/exynos4412-galaxy-s3.dtsi @@ -53,7 +53,8 @@ i2c_ak8975: i2c-gpio-0 { compatible = "i2c-gpio"; - gpios = <&gpy2 4 GPIO_ACTIVE_HIGH>, <&gpy2 5 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; @@ -68,7 +69,8 @@ i2c_cm36651: i2c-gpio-2 { compatible = "i2c-gpio"; - gpios = <&gpf0 0 GPIO_ACTIVE_LOW>, <&gpf0 1 GPIO_ACTIVE_LOW>; + sda-gpios = <&gpf0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpf0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; diff --git a/src/arm/exynos4412-midas.dtsi b/src/arm/exynos4412-midas.dtsi index 3023bc3b68ce..2c8111c6b065 100644 --- a/src/arm/exynos4412-midas.dtsi +++ b/src/arm/exynos4412-midas.dtsi @@ -140,7 +140,8 @@ i2c_max77693: i2c-gpio-1 { compatible = "i2c-gpio"; - gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpm2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm2 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; @@ -188,7 +189,8 @@ i2c_max77693_fuel: i2c-gpio-3 { compatible = "i2c-gpio"; - gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>, <&gpf1 4 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpf1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpf1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; @@ -228,7 +230,8 @@ i2c-mhl { compatible = "i2c-gpio"; - gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpf0 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpf0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <100>; #address-cells = <1>; #size-cells = <0>; @@ -820,7 +823,7 @@ }; buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; + regulator-name = "VDD_MIF"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1100000>; regulator-always-on; @@ -831,7 +834,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -842,7 +845,7 @@ }; buck3_reg: BUCK3 { - regulator-name = "vdd_int"; + regulator-name = "VDD_INT"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1150000>; regulator-always-on; @@ -853,7 +856,7 @@ }; buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; + regulator-name = "VDD_G3D"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1150000>; regulator-boot-on; diff --git a/src/arm/exynos4412-odroid-common.dtsi b/src/arm/exynos4412-odroid-common.dtsi index 73d6a71da88d..a5c1ce1e396c 100644 --- a/src/arm/exynos4412-odroid-common.dtsi +++ b/src/arm/exynos4412-odroid-common.dtsi @@ -430,7 +430,7 @@ }; buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; + regulator-name = "VDD_MIF"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1100000>; regulator-always-on; @@ -438,7 +438,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -446,7 +446,7 @@ }; buck3_reg: BUCK3 { - regulator-name = "vdd_int"; + regulator-name = "VDD_INT"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1050000>; regulator-always-on; @@ -454,7 +454,7 @@ }; buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; + regulator-name = "VDD_G3D"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1100000>; regulator-microvolt-offset = <50000>; diff --git a/src/arm/exynos4412-origen.dts b/src/arm/exynos4412-origen.dts index ecd14b283a6b..dc865be40751 100644 --- a/src/arm/exynos4412-origen.dts +++ b/src/arm/exynos4412-origen.dts @@ -363,7 +363,7 @@ }; buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; + regulator-name = "VDD_MIF"; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1100000>; regulator-always-on; @@ -372,7 +372,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1350000>; regulator-always-on; @@ -381,7 +381,7 @@ }; buck3_reg: BUCK3 { - regulator-name = "vdd_int"; + regulator-name = "VDD_INT"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1200000>; regulator-always-on; @@ -390,7 +390,7 @@ }; buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; + regulator-name = "VDD_G3D"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -399,7 +399,7 @@ }; buck5_reg: BUCK5 { - regulator-name = "vdd_m12"; + regulator-name = "VDD_M12"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -408,7 +408,7 @@ }; buck6_reg: BUCK6 { - regulator-name = "vdd12_5m"; + regulator-name = "VDD12_5M"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1500000>; regulator-always-on; @@ -417,7 +417,7 @@ }; buck9_reg: BUCK9 { - regulator-name = "vddf28_emmc"; + regulator-name = "VDDF28_EMMC"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <3000000>; regulator-always-on; diff --git a/src/arm/exynos5250-arndale.dts b/src/arm/exynos5250-arndale.dts index 6904091d4837..c4cc7611898c 100644 --- a/src/arm/exynos5250-arndale.dts +++ b/src/arm/exynos5250-arndale.dts @@ -454,7 +454,7 @@ }; buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; + regulator-name = "VDD_MIF"; regulator-min-microvolt = <950000>; regulator-max-microvolt = <1200000>; regulator-always-on; @@ -463,7 +463,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "VDD_ARM"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1300000>; regulator-always-on; @@ -472,7 +472,7 @@ }; buck3_reg: BUCK3 { - regulator-name = "vdd_int"; + regulator-name = "VDD_INT"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1200000>; regulator-always-on; @@ -481,7 +481,7 @@ }; buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; + regulator-name = "VDD_G3D"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1300000>; regulator-always-on; @@ -641,9 +641,8 @@ pinctrl-0 = <&i2c2_gpio_bus>; status = "okay"; compatible = "i2c-gpio"; - gpios = <&gpa0 6 0 /* sda */ - &gpa0 7 0 /* scl */ - >; + sda-gpios = <&gpa0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpa0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-gpio,delay-us = <2>; #address-cells = <1>; #size-cells = <0>; diff --git a/src/arm/exynos5420-arndale-octa.dts b/src/arm/exynos5420-arndale-octa.dts index e9a09dd0a49b..dd7f8385d81e 100644 --- a/src/arm/exynos5420-arndale-octa.dts +++ b/src/arm/exynos5420-arndale-octa.dts @@ -673,7 +673,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; + regulator-name = "PVDD_ARM_1V0"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1500000>; regulator-always-on; diff --git a/src/arm/imx50.dtsi b/src/arm/imx50.dtsi index d325658901c5..1f4ecbca5225 100644 --- a/src/arm/imx50.dtsi +++ b/src/arm/imx50.dtsi @@ -288,11 +288,6 @@ reg = <0x53fa8000 0x4000>; }; - gpr: iomuxc-gpr@53fa8000 { - compatible = "fsl,imx50-iomuxc-gpr", "syscon"; - reg = <0x53fa8000 0xc>; - }; - pwm1: pwm@53fb4000 { #pwm-cells = <2>; compatible = "fsl,imx50-pwm", "fsl,imx27-pwm"; @@ -333,9 +328,10 @@ status = "disabled"; }; - src: src@53fd0000 { + src: reset-controller@53fd0000 { compatible = "fsl,imx50-src", "fsl,imx51-src"; reg = <0x53fd0000 0x4000>; + interrupts = <75>; #reset-cells = <1>; }; diff --git a/src/arm/imx51.dtsi b/src/arm/imx51.dtsi index 92fbb90bec57..d3583aad8323 100644 --- a/src/arm/imx51.dtsi +++ b/src/arm/imx51.dtsi @@ -439,9 +439,10 @@ status = "disabled"; }; - src: src@73fd0000 { + src: reset-controller@73fd0000 { compatible = "fsl,imx51-src"; reg = <0x73fd0000 0x4000>; + interrupts = <75>; #reset-cells = <1>; }; diff --git a/src/arm/imx53-cx9020.dts b/src/arm/imx53-cx9020.dts index 0a475c234054..cfb18849a92b 100644 --- a/src/arm/imx53-cx9020.dts +++ b/src/arm/imx53-cx9020.dts @@ -59,23 +59,26 @@ }; dvi-converter { - #address-cells = <1>; - #size-cells = <0>; compatible = "ti,tfp410"; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - tfp410_in: endpoint { - remote-endpoint = <&display0_out>; + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&display0_out>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - tfp410_out: endpoint { - remote-endpoint = <&dvi_connector_in>; + tfp410_out: endpoint { + remote-endpoint = <&dvi_connector_in>; + }; }; }; }; diff --git a/src/arm/imx53.dtsi b/src/arm/imx53.dtsi index 8536f59f59e6..afa57bf7b0ed 100644 --- a/src/arm/imx53.dtsi +++ b/src/arm/imx53.dtsi @@ -588,9 +588,10 @@ status = "disabled"; }; - src: src@53fd0000 { + src: reset-controller@53fd0000 { compatible = "fsl,imx53-src", "fsl,imx51-src"; reg = <0x53fd0000 0x4000>; + interrupts = <75>; #reset-cells = <1>; }; diff --git a/src/arm/imx6dl-colibri-v1_1-eval-v3.dts b/src/arm/imx6dl-colibri-v1_1-eval-v3.dts new file mode 100644 index 000000000000..223275f028f1 --- /dev/null +++ b/src/arm/imx6dl-colibri-v1_1-eval-v3.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +/dts-v1/; + +#include "imx6dl-colibri-eval-v3.dts" +#include "imx6qdl-colibri-v1_1-uhs.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.1 on Colibri Evaluation Board V3"; + compatible = "toradex,colibri_imx6dl-v1_1-eval-v3", + "toradex,colibri_imx6dl-v1_1", + "toradex,colibri_imx6dl-eval-v3", + "toradex,colibri_imx6dl", + "fsl,imx6dl"; +}; + +/* Colibri MMC */ +&usdhc1 { + status = "okay"; + /* + * Please make sure your carrier board does not pull-up any of + * the MMC/SD signals to 3.3 volt before attempting to activate + * UHS-I support. + * To let signaling voltage be changed to 1.8V, please + * delete no-1-8-v property (example below): + * /delete-property/no-1-8-v; + */ +}; diff --git a/src/arm/imx6q-dhcom-pdk2.dts b/src/arm/imx6q-dhcom-pdk2.dts index bb74fc62d913..a2dd7e549568 100644 --- a/src/arm/imx6q-dhcom-pdk2.dts +++ b/src/arm/imx6q-dhcom-pdk2.dts @@ -22,6 +22,53 @@ clock-frequency = <24000000>; }; + display_bl: display-bl { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + lcd_display: disp0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel { + compatible = "edt,etm0700g0edh6"; + ddc-i2c-bus = <&i2c2>; + backlight = <&display_bl>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + sound { compatible = "fsl,imx-audio-sgtl5000"; model = "imx-sgtl5000"; @@ -65,6 +112,15 @@ VDDA-supply = <®_3p3v>; VDDIO-supply = <&sw2_reg>; }; + + touchscreen@38 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + }; }; &iomuxc { @@ -77,9 +133,7 @@ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x400120b0 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x400120b0 MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x400120b0 - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x120b0 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x400120b0 - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x120b0 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x400120b0 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x400120b0 @@ -132,6 +186,52 @@ >; }; + pinctrl_ipu1_lcdif: ipu1-lcdif-grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x120b0 + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_touchscreen: touchscreen-grp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 + >; + }; + pinctrl_pcie: pcie-grp { fsl,pins = < MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 @@ -139,6 +239,10 @@ }; }; +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; @@ -146,6 +250,13 @@ status = "okay"; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + #pwm-cells = <3>; + status = "okay"; +}; + &ssi1 { status = "okay"; }; diff --git a/src/arm/imx6qdl-colibri-v1_1-uhs.dtsi b/src/arm/imx6qdl-colibri-v1_1-uhs.dtsi new file mode 100644 index 000000000000..7672fbfc29be --- /dev/null +++ b/src/arm/imx6qdl-colibri-v1_1-uhs.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2020 Toradex + */ + +&iomuxc { + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 + >; + }; +}; + +/* Colibri MMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; + vmmc-supply = <®_module_3v3>; + vqmmc-supply = <&vgen3_reg>; + wakeup-source; + keep-power-in-suspend; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; diff --git a/src/arm/imx6qdl-colibri.dtsi b/src/arm/imx6qdl-colibri.dtsi index 6e3c6b4925a7..240b86d2eb71 100644 --- a/src/arm/imx6qdl-colibri.dtsi +++ b/src/arm/imx6qdl-colibri.dtsi @@ -193,7 +193,16 @@ regulator-always-on; }; - /* vgen3: unused */ + /* + * +V3.3_1.8_SD1 coming off VGEN3 and supplying + * the i.MX 6 NVCC_SD1. + */ + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; vgen4_reg: vgen4 { regulator-min-microvolt = <1800000>; diff --git a/src/arm/imx6qdl-gw551x.dtsi b/src/arm/imx6qdl-gw551x.dtsi index c38e86eedcc0..8c33510c9519 100644 --- a/src/arm/imx6qdl-gw551x.dtsi +++ b/src/arm/imx6qdl-gw551x.dtsi @@ -110,7 +110,7 @@ simple-audio-card,frame-master = <&sound_codec>; sound_cpu: simple-audio-card,cpu { - sound-dai = <&ssi2>; + sound-dai = <&ssi1>; }; sound_codec: simple-audio-card,codec { diff --git a/src/arm/imx6qdl-gw552x.dtsi b/src/arm/imx6qdl-gw552x.dtsi index dc646b72b59a..bb3597132c62 100644 --- a/src/arm/imx6qdl-gw552x.dtsi +++ b/src/arm/imx6qdl-gw552x.dtsi @@ -258,6 +258,14 @@ status = "okay"; }; +&usbotg { + vbus-supply = <®_5p0v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -359,6 +367,12 @@ >; }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 diff --git a/src/arm/imx6qdl-gw560x.dtsi b/src/arm/imx6qdl-gw560x.dtsi index e8e36dfd0a6b..69ca70d3baa8 100644 --- a/src/arm/imx6qdl-gw560x.dtsi +++ b/src/arm/imx6qdl-gw560x.dtsi @@ -295,6 +295,15 @@ VDDIO-supply = <®_3p3v>; }; + magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + }; + tca8418: keypad@34 { compatible = "ti,tca8418"; pinctrl-names = "default"; @@ -389,6 +398,16 @@ }; }; }; + + imu@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + st,drdy-int-pin = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + }; }; &i2c3 { @@ -609,6 +628,12 @@ >; }; + pinctrl_imu: imugrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0 + >; + }; + pinctrl_keypad: keypadgrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */ @@ -616,6 +641,12 @@ >; }; + pinctrl_mag: maggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */ diff --git a/src/arm/imx6qdl-gw5904.dtsi b/src/arm/imx6qdl-gw5904.dtsi index 6d21cc6a9d4b..76d6cf57f1c3 100644 --- a/src/arm/imx6qdl-gw5904.dtsi +++ b/src/arm/imx6qdl-gw5904.dtsi @@ -248,6 +248,15 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + magn@1c { + compatible = "st,lsm9ds1-magn"; + reg = <0x1c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio5>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + }; + ltc3676: pmic@3c { compatible = "lltc,ltc3676"; reg = <0x3c>; @@ -320,6 +329,16 @@ }; }; }; + + imu@6a { + compatible = "st,lsm9ds1-imu"; + reg = <0x6a>; + st,drdy-int-pin = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_imu>; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + }; }; &i2c3 { @@ -501,6 +520,18 @@ >; }; + pinctrl_imu: imugrp { + fsl,pins = < + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0 + >; + }; + + pinctrl_mag: maggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ diff --git a/src/arm/imx6qdl-gw5910.dtsi b/src/arm/imx6qdl-gw5910.dtsi index 30fe47ff64a4..0857de505192 100644 --- a/src/arm/imx6qdl-gw5910.dtsi +++ b/src/arm/imx6qdl-gw5910.dtsi @@ -81,20 +81,6 @@ enable-active-high; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_bt: regulator-bt { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_bt>; - compatible = "regulator-fixed"; - regulator-name = "bt"; - gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; - startup-delay-us = <100>; - enable-active-high; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; }; }; @@ -231,9 +217,14 @@ /* Sterling-LWB Bluetooth */ &uart4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; + pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>; uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; }; /* GPS */ @@ -259,7 +250,7 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; - vmmc-supply = <®_3p3v>; + vmmc-supply = <®_wl>; non-removable; bus-width = <4>; status = "okay"; @@ -288,6 +279,12 @@ >; }; + pinctrl_bten: btengrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 + >; + }; + pinctrl_ecspi3: escpi3grp { fsl,pins = < MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 @@ -393,12 +390,6 @@ >; }; - pinctrl_reg_bt: regbtgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 - >; - }; - pinctrl_reg_wl: regwlgrp { fsl,pins = < MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 diff --git a/src/arm/imx6qdl-icore.dtsi b/src/arm/imx6qdl-icore.dtsi index 756f3a9f1b4f..12997dae35d9 100644 --- a/src/arm/imx6qdl-icore.dtsi +++ b/src/arm/imx6qdl-icore.dtsi @@ -397,7 +397,7 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 >; }; @@ -409,6 +409,7 @@ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17070 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17070 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17070 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x1b0b0 >; }; diff --git a/src/arm/imx6qdl-sabresd.dtsi b/src/arm/imx6qdl-sabresd.dtsi index fe59dde41b64..28b35ccb3757 100644 --- a/src/arm/imx6qdl-sabresd.dtsi +++ b/src/arm/imx6qdl-sabresd.dtsi @@ -204,6 +204,7 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + fsl,magic-packet; status = "okay"; }; diff --git a/src/arm/imx6qdl-sr-som.dtsi b/src/arm/imx6qdl-sr-som.dtsi index 6d7f6b9035bc..b06577808ff4 100644 --- a/src/arm/imx6qdl-sr-som.dtsi +++ b/src/arm/imx6qdl-sr-som.dtsi @@ -53,10 +53,21 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; + phy-handle = <&phy>; phy-mode = "rgmii-id"; phy-reset-duration = <2>; phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@0 { + reg = <0>; + qca,clk-out-frequency = <125000000>; + }; + }; }; &iomuxc { diff --git a/src/arm/imx6qdl.dtsi b/src/arm/imx6qdl.dtsi index 98da446aa0f2..32114cf6acee 100644 --- a/src/arm/imx6qdl.dtsi +++ b/src/arm/imx6qdl.dtsi @@ -74,7 +74,8 @@ interrupt-parent = <&gpc>; interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; #thermal-sensor-cells = <0>; }; @@ -857,7 +858,7 @@ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@20d8000 { + src: reset-controller@20d8000 { compatible = "fsl,imx6q-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, @@ -1045,7 +1046,7 @@ <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET_REF>; clock-names = "ipg", "ahb", "ptp"; - gpr = <&gpr>; + fsl,stop-mode = <&gpr 0x34 27>; status = "disabled"; }; @@ -1171,6 +1172,14 @@ cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; tzasc@21d0000 { /* TZASC1 */ diff --git a/src/arm/imx6sl.dtsi b/src/arm/imx6sl.dtsi index 8230b45057a1..911d8cf77f2c 100644 --- a/src/arm/imx6sl.dtsi +++ b/src/arm/imx6sl.dtsi @@ -98,7 +98,8 @@ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gpc>; fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; }; @@ -677,7 +678,7 @@ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@20d8000 { + src: reset-controller@20d8000 { compatible = "fsl,imx6sl-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, @@ -961,6 +962,14 @@ cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; audmux: audmux@21d8000 { diff --git a/src/arm/imx6sx-sabreauto.dts b/src/arm/imx6sx-sabreauto.dts index 825924448ab4..14fd1de52a68 100644 --- a/src/arm/imx6sx-sabreauto.dts +++ b/src/arm/imx6sx-sabreauto.dts @@ -99,7 +99,7 @@ &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy0>; fsl,magic-packet; status = "okay"; diff --git a/src/arm/imx6sx-sdb.dtsi b/src/arm/imx6sx-sdb.dtsi index 3e5fb72f21fc..c99aa273c296 100644 --- a/src/arm/imx6sx-sdb.dtsi +++ b/src/arm/imx6sx-sdb.dtsi @@ -213,7 +213,7 @@ &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy2>; status = "okay"; }; diff --git a/src/arm/imx6sx.dtsi b/src/arm/imx6sx.dtsi index d6f831731460..94e3df47d1ad 100644 --- a/src/arm/imx6sx.dtsi +++ b/src/arm/imx6sx.dtsi @@ -754,7 +754,7 @@ interrupts = ; }; - src: src@20d8000 { + src: reset-controller@20d8000 { compatible = "fsl,imx6sx-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = , @@ -930,6 +930,7 @@ "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + fsl,stop-mode = <&gpr 0x10 3>; status = "disabled"; }; @@ -1039,6 +1040,7 @@ <&clks IMX6SX_CLK_ENET_PTP>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; + fsl,stop-mode = <&gpr 0x10 4>; status = "disabled"; }; diff --git a/src/arm/imx6ul-kontron-n6x1x-s.dtsi b/src/arm/imx6ul-kontron-n6x1x-s.dtsi index f05e91841202..53a25fba34f6 100644 --- a/src/arm/imx6ul-kontron-n6x1x-s.dtsi +++ b/src/arm/imx6ul-kontron-n6x1x-s.dtsi @@ -232,13 +232,6 @@ status = "okay"; }; -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - &iomuxc { pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; @@ -409,10 +402,4 @@ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 >; }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0 - >; - }; }; diff --git a/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi b/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi index a17af4d9bfdf..61ba21a605a8 100644 --- a/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi +++ b/src/arm/imx6ul-kontron-n6x1x-som-common.dtsi @@ -57,6 +57,13 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reset_out>; @@ -106,4 +113,10 @@ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0 + >; + }; }; diff --git a/src/arm/imx6ul.dtsi b/src/arm/imx6ul.dtsi index 2ccf67c4ac1a..5379a03391bd 100644 --- a/src/arm/imx6ul.dtsi +++ b/src/arm/imx6ul.dtsi @@ -520,6 +520,7 @@ "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <1>; fsl,num-rx-queues = <1>; + fsl,stop-mode = <&gpr 0x10 4>; status = "disabled"; }; @@ -676,7 +677,7 @@ interrupts = ; }; - src: src@20d8000 { + src: reset-controller@20d8000 { compatible = "fsl,imx6ul-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = , @@ -856,6 +857,7 @@ "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <1>; fsl,num-rx-queues = <1>; + fsl,stop-mode = <&gpr 0x10 3>; status = "disabled"; }; diff --git a/src/arm/imx7-tqma7.dtsi b/src/arm/imx7-tqma7.dtsi index 9aaed85138cb..8773344b54aa 100644 --- a/src/arm/imx7-tqma7.dtsi +++ b/src/arm/imx7-tqma7.dtsi @@ -16,7 +16,7 @@ }; &cpu0 { - arm-supply = <&sw1a_reg>; + cpu-supply = <&sw1a_reg>; }; &i2c1 { diff --git a/src/arm/imx7d-cl-som-imx7.dts b/src/arm/imx7d-cl-som-imx7.dts index 89267cd59037..713483c39c9d 100644 --- a/src/arm/imx7d-cl-som-imx7.dts +++ b/src/arm/imx7d-cl-som-imx7.dts @@ -37,6 +37,10 @@ cpu-supply = <&sw1a_reg>; }; +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; diff --git a/src/arm/imx7d-colibri.dtsi b/src/arm/imx7d-colibri.dtsi index c59d72e50920..219a0404a058 100644 --- a/src/arm/imx7d-colibri.dtsi +++ b/src/arm/imx7d-colibri.dtsi @@ -13,6 +13,10 @@ }; }; +&cpu1 { + cpu-supply = <®_DCDC2>; +}; + &gpmi { status = "okay"; }; diff --git a/src/arm/imx7d-nitrogen7.dts b/src/arm/imx7d-nitrogen7.dts index 6b4acea1ef79..e0751e6ba3c0 100644 --- a/src/arm/imx7d-nitrogen7.dts +++ b/src/arm/imx7d-nitrogen7.dts @@ -121,6 +121,10 @@ cpu-supply = <&sw1a_reg>; }; +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; diff --git a/src/arm/imx7d-pinfunc.h b/src/arm/imx7d-pinfunc.h index 08ca1608fdb1..69f2c1ec8254 100644 --- a/src/arm/imx7d-pinfunc.h +++ b/src/arm/imx7d-pinfunc.h @@ -592,7 +592,7 @@ #define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 #define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 #define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 -#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0 +#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0574 0x6 0x1 #define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 #define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3 #define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 diff --git a/src/arm/imx7d-sdb.dts b/src/arm/imx7d-sdb.dts index 869efbc4af42..17cca8a9f77b 100644 --- a/src/arm/imx7d-sdb.dts +++ b/src/arm/imx7d-sdb.dts @@ -162,6 +162,10 @@ cpu-supply = <&sw1a_reg>; }; +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; + &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; diff --git a/src/arm/imx7d-tqma7.dtsi b/src/arm/imx7d-tqma7.dtsi index 8ad3048dac0d..598aed1ffd99 100644 --- a/src/arm/imx7d-tqma7.dtsi +++ b/src/arm/imx7d-tqma7.dtsi @@ -9,3 +9,7 @@ #include "imx7d.dtsi" #include "imx7-tqma7.dtsi" + +&cpu1 { + cpu-supply = <&sw1a_reg>; +}; diff --git a/src/arm/imx7d-zii-rmu2.dts b/src/arm/imx7d-zii-rmu2.dts index 2b8d6cc45a53..e5e20b07f184 100644 --- a/src/arm/imx7d-zii-rmu2.dts +++ b/src/arm/imx7d-zii-rmu2.dts @@ -33,7 +33,7 @@ }; &cpu0 { - arm-supply = <&sw1a_reg>; + cpu-supply = <&sw1a_reg>; }; &ecspi1 { diff --git a/src/arm/imx7d-zii-rpu2.dts b/src/arm/imx7d-zii-rpu2.dts index 39812c92bf0d..cbf0dbb4c198 100644 --- a/src/arm/imx7d-zii-rpu2.dts +++ b/src/arm/imx7d-zii-rpu2.dts @@ -182,7 +182,7 @@ }; &cpu0 { - arm-supply = <&sw1a_reg>; + cpu-supply = <&sw1a_reg>; }; &clks { diff --git a/src/arm/imx7d.dtsi b/src/arm/imx7d.dtsi index 4c22828df55f..cff875b80b60 100644 --- a/src/arm/imx7d.dtsi +++ b/src/arm/imx7d.dtsi @@ -153,6 +153,7 @@ "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + fsl,stop-mode = <&gpr 0x10 4>; status = "disabled"; }; diff --git a/src/arm/imx7s.dtsi b/src/arm/imx7s.dtsi index 76e3ffbbbfbf..f6bb35d3ce51 100644 --- a/src/arm/imx7s.dtsi +++ b/src/arm/imx7s.dtsi @@ -624,7 +624,7 @@ clock-names = "ckil", "osc"; }; - src: src@30390000 { + src: reset-controller@30390000 { compatible = "fsl,imx7d-src", "syscon"; reg = <0x30390000 0x10000>; interrupts = ; @@ -1190,6 +1190,7 @@ "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + fsl,stop-mode = <&gpr 0x10 3>; status = "disabled"; }; }; diff --git a/src/arm/integratorap-im-pd1.dts b/src/arm/integratorap-im-pd1.dts new file mode 100644 index 000000000000..1412a1a968fc --- /dev/null +++ b/src/arm/integratorap-im-pd1.dts @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree for the ARM Integrator/AP platform + * with the IM-PD1 example logical module mounted. + */ + +#include "integratorap.dts" + +/ { + model = "ARM Integrator/AP with IM-PD1"; + compatible = "arm,integrator-ap"; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + impd1_ram: vram@c2000000 { + /* 1 MB of designated video RAM on the IM-PD1 */ + compatible = "shared-dma-pool"; + reg = <0xc2000000 0x00100000>; + no-map; + }; + }; +}; + +&lm0 { + syscon@0 { + compatible = "arm,im-pd1-syscon", "syscon"; + reg = <0x00000000 0x1000>; + + vco1: clock@00 { + compatible = "arm,impd1-vco1"; + #clock-cells = <0>; + lock-offset = <0x08>; + vco-offset = <0x00>; + clocks = <&sysclk>; + clock-output-names = "IM-PD1-VCO1"; + }; + + vco2: clock@04 { + compatible = "arm,impd1-vco2"; + #clock-cells = <0>; + lock-offset = <0x08>; + vco-offset = <0x04>; + clocks = <&sysclk>; + clock-output-names = "IM-PD1-VCO2"; + }; + }; + + /* Also used for the Smart Card Interface SCI */ + impd1_uartclk: clock@1_4 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clocks = <&vco2>; + clock-output-names = "VCO2_DIV4"; + }; + + /* For the SSP the clock is divided by 64 */ + impd1_sspclk: clock@1_64 { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <64>; + clock-mult = <1>; + clocks = <&vco2>; + clock-output-names = "VCO2_DIV64"; + }; + + /* Fixed regulator for the MMC */ + impd1_3v3: regulator { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* Push buttons on the IM-PD1 */ + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + debounce-interval = <50>; + linux,code = ; + label = "UP"; + gpios = <&impd1_gpio1 0 GPIO_ACTIVE_HIGH>; + }; + button@1 { + debounce-interval = <50>; + linux,code = ; + label = "DOWN"; + gpios = <&impd1_gpio1 1 GPIO_ACTIVE_HIGH>; + }; + button@2 { + debounce-interval = <50>; + linux,code = ; + label = "LEFT"; + gpios = <&impd1_gpio1 2 GPIO_ACTIVE_HIGH>; + }; + button@3 { + debounce-interval = <50>; + linux,code = ; + label = "UP"; + gpios = <&impd1_gpio1 3 GPIO_ACTIVE_HIGH>; + }; + button@4 { + debounce-interval = <50>; + linux,code = ; + label = "ESC"; + gpios = <&impd1_gpio1 4 GPIO_ACTIVE_HIGH>; + }; + button@5 { + debounce-interval = <50>; + linux,code = ; + label = "ENTER"; + gpios = <&impd1_gpio1 5 GPIO_ACTIVE_HIGH>; + }; + }; + + + bridge { + compatible = "ti,ths8134b", "ti,ths8134"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + vga_bridge_in: endpoint { + remote-endpoint = <&clcd_pads_vga_dac>; + }; + }; + + port@1 { + reg = <1>; + + vga_bridge_out: endpoint { + remote-endpoint = <&vga_con_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_con_in: endpoint { + remote-endpoint = <&vga_bridge_out>; + }; + }; + }; + + uart@100000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00100000 0x1000>; + interrupts-extended = <&impd1_vic 1>; + clocks = <&impd1_uartclk>, <&sysclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart@200000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x00200000 0x1000>; + interrupts-extended = <&impd1_vic 2>; + clocks = <&impd1_uartclk>, <&sysclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + ssp@300000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x00300000 0x1000>; + interrupts-extended = <&impd1_vic 3>; + clocks = <&impd1_sspclk>, <&sysclk>; + clock-names = "spiclk", "apb_pclk"; + }; + + impd1_gpio0: gpio@400000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x00400000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = <&impd1_vic 4>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + impd1_gpio1: gpio@500000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x00500000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = <&impd1_vic 5>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + rtc@600000 { + compatible = "arm,pl030", "arm,primecell"; + reg = <0x00600000 0x1000>; + interrupts-extended = <&impd1_vic 6>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + mmc@700000 { + compatible = "arm,pl181", "arm,primecell"; + reg = <0x00700000 0x1000>; + interrupts-extended = <&impd1_vic 7>, + <&impd1_vic 8>; + clocks = <&sysclk>, <&sysclk>; + clock-names = "mclk", "apb_pclk"; + bus-width = <1>; + max-frequency = <515633>; + vmmc-supply = <&impd1_3v3>; + wp-gpios = <&impd1_gpio0 3 GPIO_ACTIVE_HIGH>; + cd-gpios = <&impd1_gpio0 4 GPIO_ACTIVE_LOW>; + }; + + aaci@800000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x00800000 0x1000>; + interrupts-extended = <&impd1_vic 9>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + }; + + display@1000000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0x01000000 0x1000>; + interrupts-extended = <&impd1_vic 11>; + clocks = <&vco1>, <&sysclk>; + clock-names = "clcdclk", "apb_pclk"; + /* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */ + max-memory-bandwidth = <40000000>; + memory-region = <&impd1_ram>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + clcd_pads_vga_dac: endpoint@0 { + reg = <0>; + remote-endpoint = <&vga_bridge_in>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + }; + + impd1_vic: interrupt-controller@3000000 { + compatible = "arm,pl192-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x03000000 0x1000>; + /* Valid interrupts, 0-9 and 11 */ + valid-mask = <0x00000bff>; + /* LM site 0 has IRQ 9 on the PIC */ + interrupts-extended = <&pic 9>; + }; +}; diff --git a/src/arm/integratorap.dts b/src/arm/integratorap.dts index 198d66181c50..67d1f9b24a52 100644 --- a/src/arm/integratorap.dts +++ b/src/arm/integratorap.dts @@ -4,7 +4,9 @@ */ /dts-v1/; -/include/ "integrator.dtsi" +#include "integrator.dtsi" +#include +#include / { model = "ARM Integrator/AP"; @@ -107,9 +109,6 @@ syscon { compatible = "arm,integrator-ap-syscon", "syscon"; reg = <0x11000000 0x100>; - interrupt-parent = <&pic>; - /* These are the logical module IRQs */ - interrupts = <9>, <10>, <11>, <12>; /* * SYSCLK clocks PCIv3 bridge, system controller and the @@ -239,4 +238,50 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; }; + + /* + * Logic module bus, we support up to 4 logical modules + * They appear at 0xc0000000, 0xd0000000, 0xe0000000 and 0xf0000000 + * and use interrupts 9, 10, 11 and 12 respectively. + */ + bus@c0000000 { + compatible = "arm,integrator-ap-lm"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0xc0000000 0xc0000000 0x40000000>; + dma-ranges; + + lm0: bus@c0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xc0000000 0x10000000>; + dma-ranges = <0x00000000 0x80000000 0x10000000>; + reg = <0xc0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + lm1: bus@d0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xd0000000 0x10000000>; + dma-ranges = <0x00000000 0x80000000 0x10000000>; + reg = <0xd0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + lm2: bus@e0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xe0000000 0x10000000>; + dma-ranges = <0x00000000 0x80000000 0x10000000>; + reg = <0xe0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + lm3: bus@f0000000 { + compatible = "simple-bus"; + ranges = <0x00000000 0xf0000000 0x10000000>; + dma-ranges = <0x00000000 0x80000000 0x10000000>; + reg = <0xf0000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; }; diff --git a/src/arm/keystone-k2e.dtsi b/src/arm/keystone-k2e.dtsi index 085e7326ea8e..2d94faf31fab 100644 --- a/src/arm/keystone-k2e.dtsi +++ b/src/arm/keystone-k2e.dtsi @@ -86,14 +86,14 @@ }; }; - msm_ram: msmram@c000000 { + msm_ram: sram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x200000>; ranges = <0x0 0x0c000000 0x200000>; #address-cells = <1>; #size-cells = <1>; - sram-bm@1f0000 { + bm-sram@1f0000 { reg = <0x001f0000 0x8000>; }; }; diff --git a/src/arm/keystone-k2g-evm.dts b/src/arm/keystone-k2g-evm.dts index b7f10bf94576..8b3d64c913d8 100644 --- a/src/arm/keystone-k2g-evm.dts +++ b/src/arm/keystone-k2g-evm.dts @@ -45,6 +45,19 @@ regulator-max-microvolt = <1800000>; regulator-always-on; }; + + hdmi: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; }; &k2g_pinctrl { @@ -89,6 +102,13 @@ >; }; + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + >; + }; + ecap0_pins: ecap0_pins { pinctrl-single,pins = < K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */ @@ -160,6 +180,40 @@ K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */ >; }; + + vout_pins: pinmux_vout_pins { + pinctrl-single,pins = < + K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */ + K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */ + K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */ + K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */ + K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */ + K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */ + K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */ + K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */ + K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */ + K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */ + K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */ + K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */ + K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */ + K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */ + K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */ + K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */ + K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */ + K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */ + K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */ + K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */ + K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */ + K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */ + K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */ + K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */ + K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */ + K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */ + K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */ + K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */ + K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */ + >; + }; }; &uart0 { @@ -348,7 +402,7 @@ &gbe0 { phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii-rxid"; status = "okay"; }; @@ -357,3 +411,50 @@ pinctrl-0 = <&emac_pins>; status = "okay"; }; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + clock-frequency = <400000>; + + sii9022: sii9022@3b { + #sound-dai-cells = <0>; + compatible = "sil,sii9022"; + reg = <0x3b>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&vout_pins>; + status = "ok"; + + port { + dpi_out: endpoint { + remote-endpoint = <&sii9022_in>; + data-lines = <24>; + }; + }; +}; diff --git a/src/arm/keystone-k2g.dtsi b/src/arm/keystone-k2g.dtsi index 1c833105d6c5..05a75019275e 100644 --- a/src/arm/keystone-k2g.dtsi +++ b/src/arm/keystone-k2g.dtsi @@ -95,14 +95,14 @@ ranges = <0x0 0x0 0x0 0xc0000000>; dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; - msm_ram: msmram@c000000 { + msm_ram: sram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x100000>; ranges = <0x0 0x0c000000 0x100000>; #address-cells = <1>; #size-cells = <1>; - sram-bm@f7000 { + bm-sram@f7000 { reg = <0x000f7000 0x8000>; }; }; @@ -324,6 +324,28 @@ clock-names = "gpio"; }; + dss: dss@02540000 { + compatible = "ti,k2g-dss"; + reg = <0x02540000 0x400>, + <0x02550000 0x1000>, + <0x02557000 0x1000>, + <0x0255a800 0x100>, + <0x0255ac00 0x100>; + reg-names = "cfg", "common", "vid1", "ovr1", "vp1"; + clocks = <&k2g_clks 0x2 0>, + <&k2g_clks 0x2 1>; + clock-names = "fck", "vp1"; + interrupts = ; + + power-domains = <&k2g_pds 0x2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + max-memory-bandwidth = <230000000>; + }; + edma0: edma@2700000 { compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; reg = <0x02700000 0x8000>; diff --git a/src/arm/keystone-k2hk.dtsi b/src/arm/keystone-k2hk.dtsi index ca0f198ba627..8a9447703310 100644 --- a/src/arm/keystone-k2hk.dtsi +++ b/src/arm/keystone-k2hk.dtsi @@ -57,14 +57,14 @@ &soc0 { /include/ "keystone-k2hk-clocks.dtsi" - msm_ram: msmram@c000000 { + msm_ram: sram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x600000>; ranges = <0x0 0x0c000000 0x600000>; #address-cells = <1>; #size-cells = <1>; - sram-bm@5f0000 { + bm-sram@5f0000 { reg = <0x5f0000 0x8000>; }; }; diff --git a/src/arm/keystone-k2l.dtsi b/src/arm/keystone-k2l.dtsi index 374c80124c4e..dff5fea72b2f 100644 --- a/src/arm/keystone-k2l.dtsi +++ b/src/arm/keystone-k2l.dtsi @@ -255,14 +255,14 @@ }; }; - msm_ram: msmram@c000000 { + msm_ram: sram@c000000 { compatible = "mmio-sram"; reg = <0x0c000000 0x200000>; ranges = <0x0 0x0c000000 0x200000>; #address-cells = <1>; #size-cells = <1>; - sram-bm@1f8000 { + bm-sram@1f8000 { reg = <0x001f8000 0x8000>; }; }; diff --git a/src/arm/kirkwood-l-50.dts b/src/arm/kirkwood-l-50.dts new file mode 100644 index 000000000000..0d81c43a6a73 --- /dev/null +++ b/src/arm/kirkwood-l-50.dts @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Check Point L-50 Board Description + * Copyright 2020 Pawel Dembicki + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "Check Point L-50"; + compatible = "checkpoint,l-50", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 = <&pmx_led38 &pmx_sysrst &pmx_button29>; + pinctrl-names = "default"; + + pmx_sysrst: pmx-sysrst { + marvell,pins = "mpp6"; + marvell,function = "sysrst"; + }; + + pmx_button29: pmx_button29 { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led38: pmx_led38 { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; + + pmx_sdio_cd: pmx-sdio-cd { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + mvsdio@90000 { + status = "okay"; + cd-gpios = <&gpio1 14 9>; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + + gpio2: gpio-expander@20{ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1505q"; + reg = <0x20>; + + gpio-controller; + }; + + /* Three GPIOs from 0x21 exp. are undescribed in dts: + * 1: DSL module reset (active low) + * 5: mPCIE reset (active low) + * 6: Express card reset (active low) + */ + gpio3: gpio-expander@21{ + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "semtech,sx1505q"; + reg = <0x21>; + + gpio-controller; + }; + + rtc@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + status_green { + label = "l-50:green:status"; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + status_red { + label = "l-50:red:status"; + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + }; + + wifi { + label = "l-50:green:wifi"; + gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "phy0tpt"; + }; + + internet_green { + label = "l-50:green:internet"; + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + }; + + internet_red { + label = "l-50:red:internet"; + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + }; + + usb1_green { + label = "l-50:green:usb1"; + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port3>; + }; + + usb1_red { + label = "l-50:red:usb1"; + gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + }; + + usb2_green { + label = "l-50:green:usb2"; + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port1>; + }; + + usb2_red { + label = "l-50:red:usb2"; + gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + }; + }; + + usb2_pwr { + compatible = "regulator-fixed"; + regulator-name = "usb2_pwr"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + usb1_pwr { + compatible = "regulator-fixed"; + regulator-name = "usb1_pwr"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + mpcie_pwr { + compatible = "regulator-fixed"; + regulator-name = "mpcie_pwr"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + express_card_pwr { + compatible = "regulator-fixed"; + regulator-name = "express_card_pwr"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + keys { + compatible = "gpio-keys"; + + factory_defaults { + label = "factory_defaults"; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy8: ethernet-phy@8 { + reg = <0x08>; + }; + + switch0: switch@10 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10>; + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan5"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan6"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan7"; + }; + + switch0port5: port@5 { + reg = <5>; + phy-mode = "rgmii-txid"; + link = <&switch1port5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "cpu"; + phy-mode = "rgmii-id"; + ethernet = <ð1port>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + switch@11 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11>; + dsa,member = <0 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan3"; + }; + + port@1 { + reg = <1>; + label = "lan8"; + }; + + port@2 { + reg = <2>; + label = "lan4"; + }; + + port@3 { + reg = <3>; + label = "dmz"; + }; + + switch1port5: port@5 { + reg = <5>; + phy-mode = "rgmii-txid"; + link = <&switch0port5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "dsl"; + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; + +ð0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <ðphy8>; + }; +}; + +ð1 { + status = "okay"; + ethernet1-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partition@0 { + label = "u-boot"; + reg = <0x00000000 0x000c0000>; + }; + + partition@a0000 { + label = "bootldr-env"; + reg = <0x000c0000 0x00040000>; + }; + + partition@100000 { + label = "kernel-1"; + reg = <0x00100000 0x00800000>; + }; + + partition@900000 { + label = "rootfs-1"; + reg = <0x00900000 0x07100000>; + }; + + partition@7a00000 { + label = "kernel-2"; + reg = <0x07a00000 0x00800000>; + }; + + partition@8200000 { + label = "rootfs-2"; + reg = <0x08200000 0x07100000>; + }; + + partition@f300000 { + label = "default_sw"; + reg = <0x0f300000 0x07900000>; + }; + + partition@16c00000 { + label = "logs"; + reg = <0x16c00000 0x01800000>; + }; + + partition@18400000 { + label = "preset_cfg"; + reg = <0x18400000 0x00100000>; + }; + + partition@18500000 { + label = "adsl"; + reg = <0x18500000 0x00100000>; + }; + + partition@18600000 { + label = "storage"; + reg = <0x18600000 0x07a00000>; + }; +}; + +&rtc { + status = "disabled"; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&sata_phy0 { + status = "disabled"; +}; + +&sata_phy1 { + status = "disabled"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + #trigger-source-cells = <0>; + + hub_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + hub_port3: port@3 { + reg = <3>; + #trigger-source-cells = <0>; + }; + }; +}; diff --git a/src/arm/kirkwood-netgear_readynas_nv+_v2.dts b/src/arm/kirkwood-netgear_readynas_nv+_v2.dts index 8cc8550242ef..b13aee570804 100644 --- a/src/arm/kirkwood-netgear_readynas_nv+_v2.dts +++ b/src/arm/kirkwood-netgear_readynas_nv+_v2.dts @@ -113,6 +113,20 @@ }; }; + auxdisplay { + compatible = "hit,hd44780"; + data-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>, + <&gpio1 1 GPIO_ACTIVE_HIGH>, + <&gpio1 3 GPIO_ACTIVE_HIGH>, + <&gpio1 17 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + rs-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + rw-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + backlight-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + display-height-chars = <2>; + display-width-chars = <16>; + }; + gpio-leds { compatible = "gpio-leds"; pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_backup diff --git a/src/arm/kirkwood.dtsi b/src/arm/kirkwood.dtsi index 2161e23bd98e..6c8d94beae78 100644 --- a/src/arm/kirkwood.dtsi +++ b/src/arm/kirkwood.dtsi @@ -228,7 +228,7 @@ reg = <0x20128 0x4>; }; - intc: main-interrupt-ctrl@20200 { + intc: interrupt-controller@20200 { compatible = "marvell,orion-intc"; interrupt-controller; #interrupt-cells = <1>; diff --git a/src/arm/logicpd-torpedo-baseboard.dtsi b/src/arm/logicpd-torpedo-baseboard.dtsi index f7b82ced4080..381f0e82bb70 100644 --- a/src/arm/logicpd-torpedo-baseboard.dtsi +++ b/src/arm/logicpd-torpedo-baseboard.dtsi @@ -65,6 +65,7 @@ pinctrl-0 = <&pwm_pins>; ti,timers = <&timer10>; #pwm-cells = <3>; + ti,clock-source = <0x01>; }; }; diff --git a/src/arm/ls1021a-twr.dts b/src/arm/ls1021a-twr.dts index 9b1fe99d55b1..5edf001f6138 100644 --- a/src/arm/ls1021a-twr.dts +++ b/src/arm/ls1021a-twr.dts @@ -242,6 +242,20 @@ status = "okay"; }; +&qspi { + status = "okay"; + + n25q128a130: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + &sai1 { status = "okay"; }; diff --git a/src/arm/meson.dtsi b/src/arm/meson.dtsi index 5d198309058a..91129dc70d83 100644 --- a/src/arm/meson.dtsi +++ b/src/arm/meson.dtsi @@ -11,7 +11,7 @@ #size-cells = <1>; interrupt-parent = <&gic>; - L2: l2-cache-controller@c4200000 { + L2: cache-controller@c4200000 { compatible = "arm,pl310-cache"; reg = <0xc4200000 0x1000>; cache-unified; @@ -229,6 +229,9 @@ interrupts = ; phys = <&usb0_phy>; phy-names = "usb2-phy"; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <500>; + g-tx-fifo-size = <256 192 128 128 128>; dr_mode = "host"; status = "disabled"; }; diff --git a/src/arm/meson8b-odroidc1.dts b/src/arm/meson8b-odroidc1.dts index a2a47804fc4a..cb21ac9f517c 100644 --- a/src/arm/meson8b-odroidc1.dts +++ b/src/arm/meson8b-odroidc1.dts @@ -202,9 +202,8 @@ pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; - phy-mode = "rgmii"; phy-handle = <ð_phy>; - amlogic,tx-delay-ns = <4>; + phy-mode = "rgmii-id"; nvmem-cells = <ðernet_mac_address>; nvmem-cell-names = "mac-address"; diff --git a/src/arm/meson8b.dtsi b/src/arm/meson8b.dtsi index e34b039b9357..ba36168b9c1b 100644 --- a/src/arm/meson8b.dtsi +++ b/src/arm/meson8b.dtsi @@ -425,8 +425,9 @@ clocks = <&clkc CLKID_ETH>, <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; rx-fifo-depth = <4096>; tx-fifo-depth = <2048>; diff --git a/src/arm/meson8m2-mxiii-plus.dts b/src/arm/meson8m2-mxiii-plus.dts index d54477b1001c..cc498191ddd1 100644 --- a/src/arm/meson8m2-mxiii-plus.dts +++ b/src/arm/meson8m2-mxiii-plus.dts @@ -69,9 +69,7 @@ pinctrl-names = "default"; phy-handle = <ð_phy0>; - phy-mode = "rgmii"; - - amlogic,tx-delay-ns = <4>; + phy-mode = "rgmii-id"; mdio { compatible = "snps,dwmac-mdio"; diff --git a/src/arm/meson8m2.dtsi b/src/arm/meson8m2.dtsi index 5bde7f502007..2397ba06d608 100644 --- a/src/arm/meson8m2.dtsi +++ b/src/arm/meson8m2.dtsi @@ -30,8 +30,9 @@ 0xc1108140 0x8>; clocks = <&clkc CLKID_ETH>, <&clkc CLKID_MPLL2>, - <&clkc CLKID_MPLL2>; - clock-names = "stmmaceth", "clkin0", "clkin1"; + <&clkc CLKID_MPLL2>, + <&clkc CLKID_FCLK_DIV2>; + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment"; resets = <&reset RESET_ETHERNET>; reset-names = "stmmaceth"; }; @@ -64,6 +65,14 @@ compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc"; }; +&usb0_phy { + compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; +}; + +&usb1_phy { + compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; +}; + &wdt { compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; }; diff --git a/src/arm/mmp2.dtsi b/src/arm/mmp2.dtsi index da10567b5aca..4306f3a6742b 100644 --- a/src/arm/mmp2.dtsi +++ b/src/arm/mmp2.dtsi @@ -364,7 +364,7 @@ rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; - interrupts = <1 0>; + interrupts = <1>, <0>; interrupt-names = "rtc 1Hz", "rtc alarm"; interrupt-parent = <&intcmux5>; clocks = <&soc_clocks MMP2_CLK_RTC>; diff --git a/src/arm/mmp3.dtsi b/src/arm/mmp3.dtsi index 826f0a577859..57231d49d938 100644 --- a/src/arm/mmp3.dtsi +++ b/src/arm/mmp3.dtsi @@ -183,14 +183,14 @@ mrvl,intc-nr-irqs = <5>; }; - usb_otg_phy0: usb-otg-phy@d4207000 { + usb_otg_phy0: usb-phy@d4207000 { compatible = "marvell,mmp3-usb-phy"; reg = <0xd4207000 0x40>; #phy-cells = <0>; status = "disabled"; }; - usb_otg0: usb-otg@d4208000 { + usb_otg0: usb@d4208000 { compatible = "marvell,pxau2o-ehci"; reg = <0xd4208000 0x200>; interrupts = ; @@ -201,14 +201,14 @@ status = "disabled"; }; - hsic_phy0: hsic-phy@f0001800 { + hsic_phy0: usb-phy@f0001800 { compatible = "marvell,mmp3-hsic-phy"; reg = <0xf0001800 0x40>; #phy-cells = <0>; status = "disabled"; }; - hsic0: hsic@f0001000 { + hsic0: usb@f0001000 { compatible = "marvell,pxau2o-ehci"; reg = <0xf0001000 0x200>; interrupts = ; @@ -222,14 +222,14 @@ status = "disabled"; }; - hsic_phy1: hsic-phy@f0002800 { + hsic_phy1: usb-phy@f0002800 { compatible = "marvell,mmp3-hsic-phy"; reg = <0xf0002800 0x40>; #phy-cells = <0>; status = "disabled"; }; - hsic1: hsic@f0002000 { + hsic1: usb@f0002000 { compatible = "marvell,pxau2o-ehci"; reg = <0xf0002000 0x200>; interrupts = ; @@ -279,6 +279,16 @@ status = "disabled"; }; + mmc5: mmc@d4217000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xd4217000 0x120>; + clocks = <&soc_clocks MMP3_CLK_SDH4>; + clock-names = "io"; + interrupt-parent = <&hsi1_mux>; + interrupts = <0>; + status = "disabled"; + }; + camera0: camera@d420a000 { compatible = "marvell,mmp2-ccic"; reg = <0xd420a000 0x800>; @@ -472,7 +482,7 @@ rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; - interrupts = <1 0>; + interrupts = <1>, <0>; interrupt-names = "rtc 1Hz", "rtc alarm"; interrupt-parent = <&rtc_mux>; clocks = <&soc_clocks MMP2_CLK_RTC>; @@ -521,7 +531,7 @@ }; }; - l2: l2-cache-controller@d0020000 { + l2: cache-controller@d0020000 { compatible = "marvell,tauros3-cache", "arm,pl310-cache"; reg = <0xd0020000 0x1000>; cache-unified; diff --git a/src/arm/motorola-cpcap-mapphone.dtsi b/src/arm/motorola-cpcap-mapphone.dtsi index e39eee628afd..08a7d3ce383f 100644 --- a/src/arm/motorola-cpcap-mapphone.dtsi +++ b/src/arm/motorola-cpcap-mapphone.dtsi @@ -13,8 +13,10 @@ #interrupt-cells = <2>; #address-cells = <1>; #size-cells = <0>; - spi-max-frequency = <3000000>; + spi-max-frequency = <9600000>; spi-cs-high; + spi-cpol; + spi-cpha; cpcap_adc: adc { compatible = "motorola,mapphone-cpcap-adc"; diff --git a/src/arm/mt2701-evb.dts b/src/arm/mt2701-evb.dts index 88f8fd22302a..d1535f385f36 100644 --- a/src/arm/mt2701-evb.dts +++ b/src/arm/mt2701-evb.dts @@ -6,6 +6,7 @@ */ /dts-v1/; +#include #include "mt2701.dtsi" / { @@ -61,6 +62,15 @@ >; default-brightness-level = <9>; }; + + usb_vbus: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 45 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &auxadc { @@ -230,3 +240,14 @@ &uart0 { status = "okay"; }; + +&usb2 { + status = "okay"; + usb-role-switch; + connector{ + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + id-gpios = <&pio 44 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb_vbus>; + }; +}; diff --git a/src/arm/mt2701.dtsi b/src/arm/mt2701.dtsi index 2093b38d6e6d..39b3a2f4bef4 100644 --- a/src/arm/mt2701.dtsi +++ b/src/arm/mt2701.dtsi @@ -671,6 +671,39 @@ }; }; + usb2: usb@11200000 { + compatible = "mediatek,mt2701-musb", + "mediatek,mtk-musb"; + reg = <0 0x11200000 0 0x1000>; + interrupts = ; + interrupt-names = "mc"; + phys = <&u2port2 PHY_TYPE_USB2>; + dr_mode = "otg"; + clocks = <&pericfg CLK_PERI_USB0>, + <&pericfg CLK_PERI_USB0_MCU>, + <&pericfg CLK_PERI_USB_SLV>; + clock-names = "main","mcu","univpll"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; + status = "disabled"; + }; + + u2phy0: usb-phy@11210000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0 0x11210000 0 0x0800>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + u2port2: usb-phy@1a1c4800 { + reg = <0 0x11210800 0 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt2701-ethsys", "syscon"; reg = <0 0x1b000000 0 0x1000>; diff --git a/src/arm/mt7623.dtsi b/src/arm/mt7623.dtsi index f76b4a3c34b9..3a6b856e5b74 100644 --- a/src/arm/mt7623.dtsi +++ b/src/arm/mt7623.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2017-2018 MediaTek Inc. * Author: John Crispin * Sean Wang + * Ryder Lee * */ @@ -733,6 +734,30 @@ #reset-cells = <1>; }; + mali: gpu@13040000 { + compatible = "mediatek,mt7623-mali", "arm,mali-450"; + reg = <0 0x13040000 0 0x30000>; + interrupts = , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", + "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3", + "pp"; + clocks = <&topckgen CLK_TOP_MMPLL>, + <&g3dsys CLK_G3DSYS_CORE>; + clock-names = "bus", "core"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>; + resets = <&g3dsys MT2701_G3DSYS_CORE_RST>; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", diff --git a/src/arm/mt7623n-rfb-emmc.dts b/src/arm/mt7623n-rfb-emmc.dts index b7606130ade9..0447748f9fa0 100644 --- a/src/arm/mt7623n-rfb-emmc.dts +++ b/src/arm/mt7623n-rfb-emmc.dts @@ -138,6 +138,7 @@ mac@1 { compatible = "mediatek,eth-mac"; reg = <1>; + phy-mode = "rgmii"; phy-handle = <&phy5>; }; diff --git a/src/arm/omap2.dtsi b/src/arm/omap2.dtsi index 0e453fec2e3a..8a5cb44bfe2f 100644 --- a/src/arm/omap2.dtsi +++ b/src/arm/omap2.dtsi @@ -201,11 +201,32 @@ clock-frequency = <48000000>; }; - timer2: timer@4802a000 { - compatible = "ti,omap2420-timer"; - reg = <0x4802a000 0x400>; - interrupts = <38>; - ti,hwmods = "timer2"; + timer2_target: target-module@4802a000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x4802a000 0x4>, + <0x4802a010 0x4>, + <0x4802a014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt2_fck>, <&gpt2_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4802a000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap2420-timer"; + reg = <0 0x400>; + interrupts = <38>; + }; }; timer3: timer@48078000 { diff --git a/src/arm/omap2420.dtsi b/src/arm/omap2420.dtsi index aba542d63d6d..6c5c7c0e8b94 100644 --- a/src/arm/omap2420.dtsi +++ b/src/arm/omap2420.dtsi @@ -68,10 +68,23 @@ }; }; - counter32k: counter@4000 { - compatible = "ti,omap-counter32k"; - reg = <0x4000 0x20>; - ti,hwmods = "counter_32k"; + target-module@4000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4000 0x4>, + <0x4004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + clocks = <&func_32k_ck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0 0x20>; + }; }; }; @@ -194,12 +207,33 @@ }; }; - timer1: timer@48028000 { - compatible = "ti,omap2420-timer"; - reg = <0x48028000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; + timer1_target: target-module@48028000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x48028000 0x4>, + <0x48028010 0x4>, + <0x48028014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt1_fck>, <&gpt1_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48028000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap2420-timer"; + reg = <0 0x400>; + interrupts = <37>; + ti,timer-alwon; + }; }; wd_timer2: wdt@48022000 { @@ -218,5 +252,15 @@ compatible = "ti,omap2420-i2c"; }; -/include/ "omap24xx-clocks.dtsi" -/include/ "omap2420-clocks.dtsi" +#include "omap24xx-clocks.dtsi" +#include "omap2420-clocks.dtsi" + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&func_32k_ck>; + }; +}; diff --git a/src/arm/omap2430.dtsi b/src/arm/omap2430.dtsi index 15ef7593be12..6a1f5bb3c06a 100644 --- a/src/arm/omap2430.dtsi +++ b/src/arm/omap2430.dtsi @@ -81,10 +81,23 @@ }; }; - counter32k: counter@20000 { - compatible = "ti,omap-counter32k"; - reg = <0x20000 0x20>; - ti,hwmods = "counter_32k"; + target-module@20000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x20000 0x4>, + <0x20004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + clocks = <&func_32k_ck>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0 0x20>; + }; }; }; @@ -277,12 +290,33 @@ }; }; - timer1: timer@49018000 { - compatible = "ti,omap2420-timer"; - reg = <0x49018000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; + timer1_target: target-module@49018000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x49018000 0x4>, + <0x49018010 0x4>, + <0x49018014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt1_fck>, <&gpt1_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49018000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap2420-timer"; + reg = <0 0x400>; + interrupts = <37>; + ti,timer-alwon; + }; }; mcspi3: spi@480b8000 { @@ -321,5 +355,15 @@ compatible = "ti,omap2430-i2c"; }; -/include/ "omap24xx-clocks.dtsi" -/include/ "omap2430-clocks.dtsi" +#include "omap24xx-clocks.dtsi" +#include "omap2430-clocks.dtsi" + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&func_32k_ck>; + }; +}; diff --git a/src/arm/omap3-beagle.dts b/src/arm/omap3-beagle.dts index 4ed3f93f5841..dfa158647d91 100644 --- a/src/arm/omap3-beagle.dts +++ b/src/arm/omap3-beagle.dts @@ -304,6 +304,39 @@ phys = <0 &hsusb2_phy>; }; +/* Unusable as clocksource because of unreliable oscillator */ +&counter32k { + status = "disabled"; +}; + +/* Unusable as clockevent because if unreliable oscillator, allow to idle */ +&timer1_target { + /delete-property/ti,no-reset-on-init; + /delete-property/ti,no-idle; + timer@0 { + /delete-property/ti,timer-alwon; + }; +}; + +/* Preferred always-on timer for clocksource */ +&timer12_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + /* Always clocked by secure_32k_fck */ + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt2_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; + &twl_gpio { ti,use-leds; /* pullups: BIT(1) */ diff --git a/src/arm/omap3-devkit8000.dts b/src/arm/omap3-devkit8000.dts index 162d0726b008..c2995a280729 100644 --- a/src/arm/omap3-devkit8000.dts +++ b/src/arm/omap3-devkit8000.dts @@ -14,3 +14,36 @@ display2 = &tv0; }; }; + +/* Unusable as clocksource because of unreliable oscillator */ +&counter32k { + status = "disabled"; +}; + +/* Unusable as clockevent because if unreliable oscillator, allow to idle */ +&timer1_target { + /delete-property/ti,no-reset-on-init; + /delete-property/ti,no-idle; + timer@0 { + /delete-property/ti,timer-alwon; + }; +}; + +/* Preferred always-on timer for clocksource */ +&timer12_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + /* Always clocked by secure_32k_fck */ + }; +}; + +/* Preferred timer for clockevent */ +&timer2_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt2_fck>; + assigned-clock-parents = <&sys_ck>; + }; +}; diff --git a/src/arm/omap3-gta04.dtsi b/src/arm/omap3-gta04.dtsi index 409a758c99f1..ecc45862b4f3 100644 --- a/src/arm/omap3-gta04.dtsi +++ b/src/arm/omap3-gta04.dtsi @@ -150,6 +150,7 @@ compatible = "ti,omap-dmtimer-pwm"; ti,timers = <&timer11>; #pwm-cells = <3>; + ti,clock-source = <0x01>; }; hsusb2_phy: hsusb2_phy { diff --git a/src/arm/omap3-n900.dts b/src/arm/omap3-n900.dts index 4089d97405c9..3dbcae3d60d2 100644 --- a/src/arm/omap3-n900.dts +++ b/src/arm/omap3-n900.dts @@ -105,6 +105,14 @@ linux,code = ; linux,can-disable; }; + + machine_cover { + label = "Machine Cover"; + gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */ + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; }; isp1707: isp1707 { @@ -819,10 +827,6 @@ pinctrl-0 = <&mmc1_pins>; vmmc-supply = <&vmmc1>; bus-width = <4>; - /* For debugging, it is often good idea to remove this GPIO. - It means you can remove back cover (to reboot by removing - battery) and still use the MMC card. */ - cd-gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */ }; /* most boards use vaux3, only some old versions use vmmc2 instead */ diff --git a/src/arm/omap3.dtsi b/src/arm/omap3.dtsi index 634ea16a711e..1296d0643943 100644 --- a/src/arm/omap3.dtsi +++ b/src/arm/omap3.dtsi @@ -193,10 +193,23 @@ }; }; - counter32k: counter@48320000 { - compatible = "ti,omap-counter32k"; - reg = <0x48320000 0x20>; - ti,hwmods = "counter_32k"; + target-module@48320000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x48320000 0x4>, + <0x48320004 0x4>; + reg-names = "rev", "sysc"; + ti,sysc-sidle = , + ; + clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48320000 0x1000>; + + counter32k: counter@0 { + compatible = "ti,omap-counter32k"; + reg = <0x0 0x20>; + }; }; intc: interrupt-controller@48200000 { @@ -637,19 +650,63 @@ dma-names = "rx"; }; - timer1: timer@48318000 { - compatible = "ti,omap3430-timer"; - reg = <0x48318000 0x400>; - interrupts = <37>; - ti,hwmods = "timer1"; - ti,timer-alwon; + timer1_target: target-module@48318000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x48318000 0x4>, + <0x48318010 0x4>, + <0x48318014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt1_fck>, <&gpt1_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48318000 0x1000>; + + timer1: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0x0 0x80>; + clocks = <&gpt1_fck>; + clock-names = "fck"; + interrupts = <37>; + ti,timer-alwon; + }; }; - timer2: timer@49032000 { - compatible = "ti,omap3430-timer"; - reg = <0x49032000 0x400>; - interrupts = <38>; - ti,hwmods = "timer2"; + timer2_target: target-module@49032000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x49032000 0x4>, + <0x49032010 0x4>, + <0x49032014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt2_fck>, <&gpt2_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x49032000 0x1000>; + + timer2: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0 0x400>; + interrupts = <38>; + }; }; timer3: timer@49034000 { @@ -723,13 +780,34 @@ ti,timer-pwm; }; - timer12: timer@48304000 { - compatible = "ti,omap3430-timer"; - reg = <0x48304000 0x400>; - interrupts = <95>; - ti,hwmods = "timer12"; - ti,timer-alwon; - ti,timer-secure; + timer12_target: target-module@48304000 { + compatible = "ti,sysc-omap2-timer", "ti,sysc"; + reg = <0x48304000 0x4>, + <0x48304010 0x4>, + <0x48304014 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | + SYSC_OMAP2_EMUFREE | + SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + clocks = <&gpt12_fck>, <&gpt12_ick>; + clock-names = "fck", "ick"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x48304000 0x1000>; + + timer12: timer@0 { + compatible = "ti,omap3430-timer"; + reg = <0 0x400>; + interrupts = <95>; + ti,timer-alwon; + ti,timer-secure; + }; }; usbhstll: usbhstll@48062000 { @@ -886,4 +964,14 @@ }; }; -/include/ "omap3xxx-clocks.dtsi" +#include "omap3xxx-clocks.dtsi" + +/* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&gpt1_fck>; + assigned-clock-parents = <&omap_32k_fck>; + }; +}; diff --git a/src/arm/omap4-duovero-parlor.dts b/src/arm/omap4-duovero-parlor.dts index 8047e8cdb3af..4548d87534e3 100644 --- a/src/arm/omap4-duovero-parlor.dts +++ b/src/arm/omap4-duovero-parlor.dts @@ -139,7 +139,7 @@ ethernet@gpmc { reg = <5 0 0xff>; interrupt-parent = <&gpio2>; - interrupts = <12 IRQ_TYPE_EDGE_FALLING>; /* gpio_44 */ + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; /* gpio_44 */ phy-mode = "mii"; diff --git a/src/arm/omap4-l4.dtsi b/src/arm/omap4-l4.dtsi index ef59e4e97d7c..fcc52121ff09 100644 --- a/src/arm/omap4-l4.dtsi +++ b/src/arm/omap4-l4.dtsi @@ -974,7 +974,6 @@ target-module@4000 { /* 0x4a304000, ap 17 24.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; reg = <0x4000 0x4>, <0x4004 0x4>; reg-names = "rev", "sysc"; @@ -1139,9 +1138,8 @@ }; }; - target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ + timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */ compatible = "ti,sysc-omap2-timer", "ti,sysc"; - ti,hwmods = "timer1"; reg = <0x8000 0x4>, <0x8010 0x4>, <0x8014 0x4>; diff --git a/src/arm/omap4.dtsi b/src/arm/omap4.dtsi index 763bdea8c829..4400f5f8e099 100644 --- a/src/arm/omap4.dtsi +++ b/src/arm/omap4.dtsi @@ -655,3 +655,13 @@ #reset-cells = <1>; }; }; + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>; + assigned-clock-parents = <&sys_32k_ck>; + }; +}; diff --git a/src/arm/omap5-l4.dtsi b/src/arm/omap5-l4.dtsi index f68740abb8aa..5217805bf126 100644 --- a/src/arm/omap5-l4.dtsi +++ b/src/arm/omap5-l4.dtsi @@ -1003,6 +1003,7 @@ <0x00090000 0x00090000 0x002000>, /* ap 55 */ <0x00092000 0x00092000 0x001000>, /* ap 56 */ <0x000a4000 0x000a4000 0x001000>, /* ap 57 */ + <0x000a5000 0x000a5000 0x001000>, <0x000a6000 0x000a6000 0x001000>, /* ap 58 */ <0x000a8000 0x000a8000 0x004000>, /* ap 59 */ <0x000ac000 0x000ac000 0x001000>, /* ap 60 */ @@ -1908,6 +1909,36 @@ <0x00001000 0x000a5000 0x00001000>; }; + des_target: target-module@a5000 { /* 0x480a5000 */ + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0xa5030 0x4>, + <0xa5034 0x4>, + <0xa5038 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_DES3DES_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa5000 0x00001000>; + status = "disabled"; + + des: des@0 { + compatible = "ti,omap4-des"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 117>, <&sdma 116>; + dma-names = "tx", "rx"; + }; + }; + target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */ compatible = "ti,sysc"; status = "disabled"; @@ -2150,7 +2181,6 @@ target-module@4000 { /* 0x4ae04000, ap 17 20.0 */ compatible = "ti,sysc-omap2", "ti,sysc"; - ti,hwmods = "counter_32k"; reg = <0x4000 0x4>, <0x4010 0x4>; reg-names = "rev", "sysc"; @@ -2336,9 +2366,8 @@ }; }; - target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ + timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */ compatible = "ti,sysc-omap4-timer", "ti,sysc"; - ti,hwmods = "timer1"; reg = <0x8000 0x4>, <0x8010 0x4>; reg-names = "rev", "sysc"; diff --git a/src/arm/omap5.dtsi b/src/arm/omap5.dtsi index 2ac7f021c284..fb889c5b00c9 100644 --- a/src/arm/omap5.dtsi +++ b/src/arm/omap5.dtsi @@ -247,6 +247,92 @@ hw-caps-temp-alert; }; + aes1_target: target-module@4b501000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b501080 0x4>, + <0x4b501084 0x4>, + <0x4b501088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b501000 0x1000>; + + aes1: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 111>, <&sdma 110>; + dma-names = "tx", "rx"; + }; + }; + + aes2_target: target-module@4b701000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b701080 0x4>, + <0x4b701084 0x4>, + <0x4b701088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b701000 0x1000>; + + aes2: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = ; + dmas = <&sdma 114>, <&sdma 113>; + dma-names = "tx", "rx"; + }; + }; + + sham_target: target-module@4b100000 { + compatible = "ti,sysc-omap3-sham", "ti,sysc"; + reg = <0x4b100100 0x4>, + <0x4b100110 0x4>, + <0x4b100114 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + ; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b100000 0x1000>; + + sham: sham@0 { + compatible = "ti,omap4-sham"; + reg = <0 0x300>; + interrupts = ; + dmas = <&sdma 119>; + dma-names = "rx"; + }; + }; + bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc @@ -581,3 +667,13 @@ #reset-cells = <1>; }; }; + +/* Preferred always-on timer for clockevent */ +&timer1_target { + ti,no-reset-on-init; + ti,no-idle; + timer@0 { + assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; + assigned-clock-parents = <&sys_32k_ck>; + }; +}; diff --git a/src/arm/pxa168.dtsi b/src/arm/pxa168.dtsi index 9a9e38245e88..4fe7735c7c58 100644 --- a/src/arm/pxa168.dtsi +++ b/src/arm/pxa168.dtsi @@ -97,7 +97,7 @@ resets = <&soc_clocks PXA168_CLK_GPIO>; interrupt-names = "gpio_mux"; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; ranges; gcb0: gpio@d4019000 { @@ -119,6 +119,8 @@ twsi1: i2c@d4011000 { compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xd4011000 0x1000>; interrupts = <7>; clocks = <&soc_clocks PXA168_CLK_TWSI0>; @@ -129,6 +131,8 @@ twsi2: i2c@d4025000 { compatible = "mrvl,mmp-twsi"; + #address-cells = <1>; + #size-cells = <0>; reg = <0xd4025000 0x1000>; interrupts = <58>; clocks = <&soc_clocks PXA168_CLK_TWSI1>; @@ -139,7 +143,7 @@ rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; - interrupts = <5 6>; + interrupts = <5>, <6>; interrupt-names = "rtc 1Hz", "rtc alarm"; clocks = <&soc_clocks PXA168_CLK_RTC>; resets = <&soc_clocks PXA168_CLK_RTC>; diff --git a/src/arm/pxa3xx.dtsi b/src/arm/pxa3xx.dtsi index c237a0e4b12a..d19674812cd2 100644 --- a/src/arm/pxa3xx.dtsi +++ b/src/arm/pxa3xx.dtsi @@ -170,7 +170,7 @@ clocks = <&clks CLK_GPIO>; gpio-ranges = <&pinctrl 0 0 128>; interrupt-names = "gpio0", "gpio1", "gpio_mux"; - interrupts = <8 9 10>; + interrupts = <8>, <9>, <10>; gpio-controller; #gpio-cells = <0x2>; interrupt-controller; diff --git a/src/arm/pxa910.dtsi b/src/arm/pxa910.dtsi index 587a5e7f0702..352a39357810 100644 --- a/src/arm/pxa910.dtsi +++ b/src/arm/pxa910.dtsi @@ -109,7 +109,7 @@ clocks = <&soc_clocks PXA910_CLK_GPIO>; resets = <&soc_clocks PXA910_CLK_GPIO>; interrupt-controller; - #interrupt-cells = <1>; + #interrupt-cells = <2>; ranges; gcb0: gpio@d4019000 { @@ -155,7 +155,7 @@ rtc: rtc@d4010000 { compatible = "mrvl,mmp-rtc"; reg = <0xd4010000 0x1000>; - interrupts = <5 6>; + interrupts = <5>, <6>; interrupt-names = "rtc 1Hz", "rtc alarm"; clocks = <&soc_clocks PXA910_CLK_RTC>; resets = <&soc_clocks PXA910_CLK_RTC>; diff --git a/src/arm/qcom-ipq4019.dtsi b/src/arm/qcom-ipq4019.dtsi index bfa9ce4c6e69..74d8e2c8e4b3 100644 --- a/src/arm/qcom-ipq4019.dtsi +++ b/src/arm/qcom-ipq4019.dtsi @@ -166,6 +166,7 @@ <1 4 0xf08>, <1 1 0xf08>; clock-frequency = <48000000>; + always-on; }; soc { @@ -576,5 +577,33 @@ "legacy"; status = "disabled"; }; + + mdio: mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq4019-mdio"; + reg = <0x90000 0x64>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + }; + + ethphy4: ethernet-phy@4 { + reg = <4>; + }; + }; }; }; diff --git a/src/arm/qcom-ipq8064.dtsi b/src/arm/qcom-ipq8064.dtsi index 4021f661cd11..b912da9a3ff3 100644 --- a/src/arm/qcom-ipq8064.dtsi +++ b/src/arm/qcom-ipq8064.dtsi @@ -93,6 +93,12 @@ }; }; + firmware { + scm { + compatible = "qcom,scm-ipq806x", "qcom,scm"; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; diff --git a/src/arm/qcom-msm8974-samsung-klte.dts b/src/arm/qcom-msm8974-samsung-klte.dts index eaa1001d0a46..d4dc98214225 100644 --- a/src/arm/qcom-msm8974-samsung-klte.dts +++ b/src/arm/qcom-msm8974-samsung-klte.dts @@ -1,7 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-msm8974pro.dtsi" -#include "qcom-pm8841.dtsi" -#include "qcom-pm8941.dtsi" +#include "qcom-pma8084.dtsi" +#include +#include +#include / { model = "Samsung Galaxy S5"; @@ -14,6 +16,194 @@ chosen { stdout-path = "serial0:115200n8"; }; + + smd { + rpm { + rpm_requests { + pma8084-regulators { + compatible = "qcom,rpm-pma8084-regulators"; + status = "okay"; + + pma8084_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_s3: s3 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_s5: s5 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pma8084_s6: s6 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pma8084_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l3: l3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + }; + + pma8084_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l11: l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + pma8084_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pma8084_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pma8084_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pma8084_l19: l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-allow-set-load; + regulator-system-load = <200000>; + }; + + pma8084_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pma8084_l22: l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + pma8084_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pma8084_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pma8084_l25: l25 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + }; + + pma8084_l26: l26 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2050000>; + }; + + pma8084_l27: l27 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1225000>; + }; + + pma8084_lvs1: lvs1 {}; + pma8084_lvs2: lvs2 {}; + pma8084_lvs3: lvs3 {}; + pma8084_lvs4: lvs4 {}; + + pma8084_5vs1: 5vs1 {}; + }; + }; + }; + }; + + /delete-node/ vreg-boost; }; &soc { @@ -21,4 +211,215 @@ status = "ok"; }; + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + volume-down { + label = "volume_down"; + gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + }; + + home-key { + label = "home_key"; + gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + volume-up { + label = "volume_up"; + gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + pinctrl@fd510000 { + sdhc1_pin_a: sdhc1-pin-active { + clk { + pins = "sdc1_clk"; + drive-strength = <4>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <4>; + bias-pull-up; + }; + }; + }; + + sdhci@f9824900 { + status = "ok"; + + vmmc-supply = <&pma8084_l20>; + vqmmc-supply = <&pma8084_s4>; + + bus-width = <8>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_pin_a>; + }; + + usb@f9a55000 { + status = "ok"; + + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + /*extcon = <&smbb>, <&usb_id>;*/ + /*vbus-supply = <&chg_otg>;*/ + + hnp-disable; + srp-disable; + adp-disable; + + ulpi { + phy@a { + status = "ok"; + + v1p8-supply = <&pma8084_l6>; + v3p3-supply = <&pma8084_l24>; + + /*extcon = <&smbb>;*/ + qcom,init-seq = /bits/ 8 <0x1 0x64>; + }; + }; + }; + + pinctrl@fd510000 { + i2c6_pins: i2c6 { + mux { + pins = "gpio29", "gpio30"; + function = "blsp_i2c6"; + + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c@f9928000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + + pmic@60 { + reg = <0x60>; + compatible = "maxim,max77826"; + + regulators { + max77826_ldo1: LDO1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + max77826_ldo2: LDO2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + max77826_ldo3: LDO3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + max77826_ldo4: LDO4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo5: LDO5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo6: LDO6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo7: LDO7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo8: LDO8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo9: LDO9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_ldo10: LDO10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo11: LDO11 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2950000>; + }; + + max77826_ldo12: LDO12 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo13: LDO13 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo14: LDO14 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + max77826_ldo15: LDO15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + max77826_buck: BUCK { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + max77826_buckboost: BUCKBOOST { + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; + }; +}; + +&spmi_bus { + pma8084@0 { + gpios@c000 { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio2", "gpio3", "gpio5"; + function = "normal"; + + bias-pull-up; + power-source = ; + }; + }; + }; }; diff --git a/src/arm/qcom-msm8974.dtsi b/src/arm/qcom-msm8974.dtsi index 2ea2308d91b3..51f5f904f9eb 100644 --- a/src/arm/qcom-msm8974.dtsi +++ b/src/arm/qcom-msm8974.dtsi @@ -974,6 +974,17 @@ #size-cells = <0>; }; + blsp_i2c6: i2c@f9928000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9928000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + blsp_i2c8: i2c@f9964000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; diff --git a/src/arm/r8a7740.dtsi b/src/arm/r8a7740.dtsi index 90feb2cf9960..0588d4446f9a 100644 --- a/src/arm/r8a7740.dtsi +++ b/src/arm/r8a7740.dtsi @@ -83,7 +83,7 @@ }; cmt1: timer@e6138000 { - compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; + compatible = "renesas,r8a7740-cmt1"; reg = <0xe6138000 0x170>; interrupts = ; clocks = <&mstp3_clks R8A7740_CLK_CMT1>; diff --git a/src/arm/r8a7742-iwg21d-q7.dts b/src/arm/r8a7742-iwg21d-q7.dts new file mode 100644 index 000000000000..1f5c35c66d91 --- /dev/null +++ b/src/arm/r8a7742-iwg21d-q7.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave-RZ/G1H Qseven board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a7742-iwg21m.dtsi" + +/ { + model = "iWave Systems RainboW-G21D-Qseven board based on RZ/G1H"; + compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742"; + + aliases { + serial2 = &scifa2; + }; + + chosen { + bootargs = "ignore_loglevel root=/dev/mmcblk0p1 rw rootwait"; + stdout-path = "serial2:115200n8"; + }; +}; + +&pfc { + scifa2_pins: scifa2 { + groups = "scifa2_data_c"; + function = "scifa2"; + }; +}; + +&scifa2 { + pinctrl-0 = <&scifa2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/src/arm/r8a7742-iwg21m.dtsi b/src/arm/r8a7742-iwg21m.dtsi new file mode 100644 index 000000000000..85aff429d408 --- /dev/null +++ b/src/arm/r8a7742-iwg21m.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the iWave RZ/G1H Qseven SOM + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include "r8a7742.dtsi" +#include + +/ { + compatible = "iwave,g21m", "renesas,r8a7742"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + memory@200000000 { + device_type = "memory"; + reg = <2 0x00000000 0 0x40000000>; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + mmc1_pins: mmc1 { + groups = "mmc1_data4", "mmc1_ctrl"; + function = "mmc1"; + }; +}; + +&mmcif1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <4>; + non-removable; + status = "okay"; +}; diff --git a/src/arm/r8a7742.dtsi b/src/arm/r8a7742.dtsi new file mode 100644 index 000000000000..305d8086a3dd --- /dev/null +++ b/src/arm/r8a7742.dtsi @@ -0,0 +1,648 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a7742 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7742"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU1>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU2>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + clock-frequency = <1400000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z>; + power-domains = <&sysc R8A7742_PD_CA15_CPU3>; + next-level-cache = <&L2_CA15>; + capacity-dmips-mhz = <1024>; + voltage-tolerance = <1>; /* 1% */ + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1400000 1000000>, + <1225000 1000000>, + <1050000 1000000>, + < 875000 1000000>, + < 700000 1000000>, + < 350000 1000000>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x100>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU0>; + next-level-cache = <&L2_CA7>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x101>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU1>; + next-level-cache = <&L2_CA7>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x102>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU2>; + next-level-cache = <&L2_CA7>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x103>; + clock-frequency = <780000000>; + clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>; + power-domains = <&sysc R8A7742_PD_CA7_CPU3>; + next-level-cache = <&L2_CA7>; + }; + + L2_CA15: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7742_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA7: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7742_PD_CA7_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + pmu-0 { + compatible = "arm,cortex-a15-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + pmu-1 { + compatible = "arm,cortex-a7-pmu"; + interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7742", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7742"; + reg = <0 0xe6060000 0 0x250>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7742-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7742-rst"; + reg = <0 0xe6160000 0 0x0100>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7742-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7742", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + icram0: sram@e63a0000 { + compatible = "mmio-sram"; + reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; + }; + + icram1: sram@e63c0000 { + compatible = "mmio-sram"; + reg = <0 0xe63c0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63c0000 0x1000>; + + smp-sram@0 { + compatible = "renesas,smp-sram"; + reg = <0 0x100>; + }; + }; + + icram2: sram@e6300000 { + compatible = "mmio-sram"; + reg = <0 0xe6300000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe6300000 0x40000>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,dmac-r8a7742", + "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <15>; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>; + clock-names = "fck"; + dmas = <&dmac0 0x21>, <&dmac0 0x22>, + <&dmac1 0x21>, <&dmac1 0x22>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>; + clock-names = "fck"; + dmas = <&dmac0 0x25>, <&dmac0 0x26>, + <&dmac1 0x25>, <&dmac1 0x26>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7742", + "renesas,rcar-gen2-scifa", "renesas,scifa"; + reg = <0 0xe6c60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>; + clock-names = "fck"; + dmas = <&dmac0 0x27>, <&dmac0 0x28>, + <&dmac1 0x27>, <&dmac1 0x28>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>; + clock-names = "fck"; + dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, + <&dmac1 0x3d>, <&dmac1 0x3e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>; + clock-names = "fck"; + dmas = <&dmac0 0x19>, <&dmac0 0x1a>, + <&dmac1 0x19>, <&dmac1 0x1a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7742", + "renesas,rcar-gen2-scifb", "renesas,scifb"; + reg = <0 0xe6ce0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 216>; + clock-names = "fck"; + dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, + <&dmac1 0x1d>, <&dmac1 0x1e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 216>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x29>, <&dmac0 0x2a>, + <&dmac1 0x29>, <&dmac1 0x2a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 721>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, + <&dmac1 0x2d>, <&dmac1 0x2e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 720>; + status = "disabled"; + }; + + scif2: serial@e6e56000 { + compatible = "renesas,scif-r8a7742", + "renesas,rcar-gen2-scif", "renesas,scif"; + reg = <0 0xe6e56000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, + <&dmac1 0x2b>, <&dmac1 0x2c>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7742", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x3a>, + <&dmac1 0x39>, <&dmac1 0x3a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7742", + "renesas,rcar-gen2-hscif", "renesas,hscif"; + reg = <0 0xe62c8000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7742_CLK_ZS>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, + <&dmac1 0x4d>, <&dmac1 0x4e>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + mmcif1: mmc@ee220000 { + compatible = "renesas,mmcif-r8a7742", + "renesas,sh-mmcif"; + reg = <0 0xee220000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 305>; + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, + <&dmac1 0xe1>, <&dmac1 0xe2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 305>; + reg-io-width = <4>; + status = "disabled"; + max-frequency = <97500000>; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>, + <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + prr: chipid@ff000044 { + compatible = "renesas,prr"; + reg = <0 0xff000044 0 4>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; +}; diff --git a/src/arm/r8a7743.dtsi b/src/arm/r8a7743.dtsi index e8b340bb99bc..fff123753b85 100644 --- a/src/arm/r8a7743.dtsi +++ b/src/arm/r8a7743.dtsi @@ -338,7 +338,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -348,7 +348,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -357,7 +357,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -367,7 +367,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -376,7 +376,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -386,7 +386,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7743", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; diff --git a/src/arm/r8a7744.dtsi b/src/arm/r8a7744.dtsi index def840b8b2d3..5050ac19041d 100644 --- a/src/arm/r8a7744.dtsi +++ b/src/arm/r8a7744.dtsi @@ -338,7 +338,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -348,7 +348,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -357,7 +357,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -367,7 +367,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -376,7 +376,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -386,7 +386,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7744", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; diff --git a/src/arm/r8a7745.dtsi b/src/arm/r8a7745.dtsi index 7ab58d8bb740..b0d1fc24e97e 100644 --- a/src/arm/r8a7745.dtsi +++ b/src/arm/r8a7745.dtsi @@ -302,7 +302,7 @@ resets = <&cpg 407>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -312,7 +312,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -321,7 +321,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -331,7 +331,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -340,7 +340,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -350,7 +350,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7745", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; diff --git a/src/arm/r8a7790.dtsi b/src/arm/r8a7790.dtsi index e5ef9fd4284a..166d5566229d 100644 --- a/src/arm/r8a7790.dtsi +++ b/src/arm/r8a7790.dtsi @@ -427,7 +427,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -437,7 +437,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -446,7 +446,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -456,7 +456,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -465,7 +465,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -475,7 +475,7 @@ status = "disabled"; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa"; reg = <0 0xffc80000 0 0x1000>; diff --git a/src/arm/r8a7791.dtsi b/src/arm/r8a7791.dtsi index 6e5bd86731cd..225676fbe312 100644 --- a/src/arm/r8a7791.dtsi +++ b/src/arm/r8a7791.dtsi @@ -291,6 +291,17 @@ reg = <0 0xe6060000 0 0x250>; }; + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7791", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + interrupts = ; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7791-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; @@ -350,7 +361,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -360,7 +371,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -369,7 +380,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -379,7 +390,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -388,7 +399,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -398,7 +409,7 @@ status = "disabled"; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xffc80000 0 0x1000>; @@ -407,7 +418,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; @@ -1067,6 +1078,76 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7791", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + adc: adc@e6e54000 { compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; diff --git a/src/arm/r8a7793.dtsi b/src/arm/r8a7793.dtsi index dadbda16161b..1b62a7e06b42 100644 --- a/src/arm/r8a7793.dtsi +++ b/src/arm/r8a7793.dtsi @@ -336,7 +336,7 @@ #thermal-sensor-cells = <0>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -346,7 +346,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -355,7 +355,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -365,7 +365,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -374,7 +374,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -384,7 +384,7 @@ status = "disabled"; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xffc80000 0 0x1000>; @@ -393,7 +393,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; diff --git a/src/arm/r8a7794.dtsi b/src/arm/r8a7794.dtsi index 2c9e7a1ebfec..8d7f8798628a 100644 --- a/src/arm/r8a7794.dtsi +++ b/src/arm/r8a7794.dtsi @@ -290,7 +290,7 @@ resets = <&cpg 407>; }; - ipmmu_sy0: mmu@e6280000 { + ipmmu_sy0: iommu@e6280000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>; @@ -300,7 +300,7 @@ status = "disabled"; }; - ipmmu_sy1: mmu@e6290000 { + ipmmu_sy1: iommu@e6290000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xe6290000 0 0x1000>; @@ -309,7 +309,7 @@ status = "disabled"; }; - ipmmu_ds: mmu@e6740000 { + ipmmu_ds: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xe6740000 0 0x1000>; @@ -319,7 +319,7 @@ status = "disabled"; }; - ipmmu_mp: mmu@ec680000 { + ipmmu_mp: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xec680000 0 0x1000>; @@ -328,7 +328,7 @@ status = "disabled"; }; - ipmmu_mx: mmu@fe951000 { + ipmmu_mx: iommu@fe951000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xfe951000 0 0x1000>; @@ -338,7 +338,7 @@ status = "disabled"; }; - ipmmu_gp: mmu@e62a0000 { + ipmmu_gp: iommu@e62a0000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xe62a0000 0 0x1000>; diff --git a/src/arm/rk3036-kylin.dts b/src/arm/rk3036-kylin.dts index 2ff9f152d29b..7154b827ea2f 100644 --- a/src/arm/rk3036-kylin.dts +++ b/src/arm/rk3036-kylin.dts @@ -16,7 +16,7 @@ leds: gpio-leds { compatible = "gpio-leds"; - work { + work_led: led-0 { gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; label = "kylin:red:led"; pinctrl-names = "default"; diff --git a/src/arm/rk3066a-mk808.dts b/src/arm/rk3066a-mk808.dts index 365eff621113..eed9e60cffa2 100644 --- a/src/arm/rk3066a-mk808.dts +++ b/src/arm/rk3066a-mk808.dts @@ -22,7 +22,7 @@ gpio-leds { compatible = "gpio-leds"; - blue { + blue_led: led-0 { label = "mk808:blue:power"; gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/src/arm/rk3188-radxarock.dts b/src/arm/rk3188-radxarock.dts index c9a7f5409960..b0fef82c0a71 100644 --- a/src/arm/rk3188-radxarock.dts +++ b/src/arm/rk3188-radxarock.dts @@ -33,19 +33,19 @@ gpio-leds { compatible = "gpio-leds"; - green { + green_led: led-0 { label = "rock:green:user1"; gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; default-state = "off"; }; - blue { + blue_led: led-1 { label = "rock:blue:user2"; gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; default-state = "off"; }; - sleep { + sleep_led: led-2 { label = "rock:red:power"; gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/src/arm/rk3229-xms6.dts b/src/arm/rk3229-xms6.dts index 933ef69da32a..263393ac4fa6 100644 --- a/src/arm/rk3229-xms6.dts +++ b/src/arm/rk3229-xms6.dts @@ -33,12 +33,18 @@ power-led { compatible = "gpio-leds"; - blue { + blue_led: led-0 { gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>, + <&gpio2 29 GPIO_ACTIVE_LOW>; + }; + vcc_host: vcc-host-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -131,7 +137,6 @@ &emmc { cap-mmc-highspeed; - disable-wp; non-removable; status = "okay"; }; @@ -202,6 +207,16 @@ status = "okay"; }; +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + vqmmc-supply = <&vccio_1v8>; + status = "okay"; +}; + &sdmmc { cap-mmc-highspeed; disable-wp; diff --git a/src/arm/rk322x.dtsi b/src/arm/rk322x.dtsi index 5485a9918da6..b0fd92befdeb 100644 --- a/src/arm/rk322x.dtsi +++ b/src/arm/rk322x.dtsi @@ -615,6 +615,16 @@ status = "disabled"; }; + rga: rga@20060000 { + compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; + reg = <0x20060000 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; + reset-names = "core", "axi", "ahb"; + }; + iep_mmu: iommu@20070800 { compatible = "rockchip,iommu"; reg = <0x20070800 0x100>; diff --git a/src/arm/rk3288-firefly-reload.dts b/src/arm/rk3288-firefly-reload.dts index 8c38bda21a7c..9a4a9749c405 100644 --- a/src/arm/rk3288-firefly-reload.dts +++ b/src/arm/rk3288-firefly-reload.dts @@ -45,20 +45,20 @@ leds { compatible = "gpio-leds"; - power { + power_led: led-0 { gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; label = "firefly:blue:power"; pinctrl-names = "default"; - pinctrl-0 = <&power_led>; + pinctrl-0 = <&power_led_pin>; panic-indicator; }; - work { + work_led: led-1 { gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; label = "firefly:blue:user"; linux,default-trigger = "rc-feedback"; pinctrl-names = "default"; - pinctrl-0 = <&work_led>; + pinctrl-0 = <&work_led_pin>; }; }; @@ -334,11 +334,11 @@ }; leds { - power_led: power-led { + power_led_pin: power-led-pin { rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; - work_led: work-led { + work_led_pin: work-led-pin { rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/src/arm/rk3288-firefly.dtsi b/src/arm/rk3288-firefly.dtsi index 5e0a19004e46..e5c4fd4ea67e 100644 --- a/src/arm/rk3288-firefly.dtsi +++ b/src/arm/rk3288-firefly.dtsi @@ -62,20 +62,20 @@ leds { compatible = "gpio-leds"; - work { + work_led: led-0 { gpios = <&gpio8 RK_PA1 GPIO_ACTIVE_LOW>; label = "firefly:blue:user"; linux,default-trigger = "rc-feedback"; pinctrl-names = "default"; - pinctrl-0 = <&work_led>; + pinctrl-0 = <&work_led_pin>; }; - power { + power_led: led-1 { gpios = <&gpio8 RK_PA2 GPIO_ACTIVE_LOW>; label = "firefly:green:power"; linux,default-trigger = "default-on"; pinctrl-names = "default"; - pinctrl-0 = <&power_led>; + pinctrl-0 = <&power_led_pin>; }; }; @@ -429,11 +429,11 @@ }; leds { - power_led: power-led { + power_led_pin: power-led-pin { rockchip,pins = <8 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; - work_led: work-led { + work_led_pin: work-led-pin { rockchip,pins = <8 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/src/arm/rk3288-miqi.dts b/src/arm/rk3288-miqi.dts index c41d012c8850..213c9eb84f76 100644 --- a/src/arm/rk3288-miqi.dts +++ b/src/arm/rk3288-miqi.dts @@ -30,7 +30,7 @@ leds { compatible = "gpio-leds"; - work { + work_led: led-0 { gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>; label = "miqi:green:user"; linux,default-trigger = "timer"; diff --git a/src/arm/rk3288-phycore-som.dtsi b/src/arm/rk3288-phycore-som.dtsi index 77a47b9b756d..e43887c9635f 100644 --- a/src/arm/rk3288-phycore-som.dtsi +++ b/src/arm/rk3288-phycore-som.dtsi @@ -36,9 +36,9 @@ leds: user-leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&user_led>; + pinctrl-0 = <&user_led_pin>; - user { + user_led: led-0 { label = "green_led"; gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -372,7 +372,7 @@ }; leds { - user_led: user-led { + user_led_pin: user-led-pin { rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>; }; }; diff --git a/src/arm/rk3288-rock2-square.dts b/src/arm/rk3288-rock2-square.dts index cdcdc921ee09..3cca4d0f9b09 100644 --- a/src/arm/rk3288-rock2-square.dts +++ b/src/arm/rk3288-rock2-square.dts @@ -41,13 +41,13 @@ gpio-leds { compatible = "gpio-leds"; - heartbeat { + heartbeat_led: led-0 { gpios = <&gpio7 RK_PB7 GPIO_ACTIVE_LOW>; label = "rock2:green:state1"; linux,default-trigger = "heartbeat"; }; - mmc { + mmc_led: led-1 { gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; label = "rock2:blue:state2"; linux,default-trigger = "mmc0"; diff --git a/src/arm/rk3288-tinker.dtsi b/src/arm/rk3288-tinker.dtsi index acfaa12ec239..90e9be443fe6 100644 --- a/src/arm/rk3288-tinker.dtsi +++ b/src/arm/rk3288-tinker.dtsi @@ -46,17 +46,17 @@ gpio-leds { compatible = "gpio-leds"; - act-led { + act_led: led-0 { gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; }; - heartbeat-led { + heartbeat_led: led-1 { gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - pwr-led { + pwr_led: led-2 { gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; }; diff --git a/src/arm/rk3288.dtsi b/src/arm/rk3288.dtsi index 0cd88774db95..2e1edd85f04a 100644 --- a/src/arm/rk3288.dtsi +++ b/src/arm/rk3288.dtsi @@ -7,7 +7,6 @@ #include #include #include -#include #include / { diff --git a/src/arm/rtd1195-horseradish.dts b/src/arm/rtd1195-horseradish.dts new file mode 100644 index 000000000000..9d06d3d34c74 --- /dev/null +++ b/src/arm/rtd1195-horseradish.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1195.dtsi" + +/ { + compatible = "realtek,horseradish", "realtek,rtd1195"; + model = "Realtek Horseradish EVB"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@a800 { + device_type = "memory"; + reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */ + <0x18070000 0x00090000>, /* r-bus to NOR flash */ + <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */ + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/src/arm/rtd1195-mele-x1000.dts b/src/arm/rtd1195-mele-x1000.dts new file mode 100644 index 000000000000..c7951b9a2c97 --- /dev/null +++ b/src/arm/rtd1195-mele-x1000.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2017-2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1195.dtsi" + +/ { + compatible = "mele,x1000", "realtek,rtd1195"; + model = "MeLE X1000"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@a800 { + device_type = "memory"; + reg = <0x0000a800 0x17ff5800>, /* boot ROM to r-bus */ + <0x18070000 0x00090000>, /* r-bus to NOR flash */ + <0x19100000 0x26f00000>; /* NOR flash to 1 GiB */ + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/src/arm/rtd1195.dtsi b/src/arm/rtd1195.dtsi new file mode 100644 index 000000000000..21897210d9d0 --- /dev/null +++ b/src/arm/rtd1195.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2017-2019 Andreas Färber + */ + +/memreserve/ 0x00000000 0x0000a800; /* boot code */ +/memreserve/ 0x0000a800 0x000f5800; +/memreserve/ 0x17fff000 0x00001000; + +#include +#include + +/ { + compatible = "realtek,rtd1195"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + clock-frequency = <1000000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + clock-frequency = <1000000000>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rpc_comm: rpc@b000 { + reg = <0x0000b000 0x1000>; + }; + + audio@1b00000 { + reg = <0x01b00000 0x400000>; + }; + + rpc_ringbuf: rpc@1ffe000 { + reg = <0x01ffe000 0x4000>; + }; + + secure@10000000 { + reg = <0x10000000 0x100000>; + no-map; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <27000000>; + }; + + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + #clock-cells = <0>; + clock-output-names = "osc27M"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x0000a800>, + <0x18000000 0x18000000 0x00070000>, + <0x18100000 0x18100000 0x01000000>, + <0x80000000 0x80000000 0x80000000>; + + rbus: bus@18000000 { + compatible = "simple-bus"; + reg = <0x18000000 0x70000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000000 0x70000>; + + crt: syscon@0 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + iso: syscon@7000 { + compatible = "syscon", "simple-mfd"; + reg = <0x7000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; + }; + + sb2: syscon@1a000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1a000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + + misc: syscon@1b000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1b000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b000 0x1000>; + }; + + scpu_wrapper: syscon@1d000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1d000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1d000 0x1000>; + }; + }; + + gic: interrupt-controller@ff011000 { + compatible = "arm,cortex-a7-gic"; + reg = <0xff011000 0x1000>, + <0xff012000 0x2000>, + <0xff014000 0x2000>, + <0xff016000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; + +&crt { + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; +}; + +&iso { + iso_reset: reset-controller@88 { + compatible = "snps,dw-low-reset"; + reg = <0x88 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@800 { + compatible = "snps,dw-apb-uart"; + reg = <0x800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&iso_reset RTD1195_ISO_RSTN_UR0>; + clock-frequency = <27000000>; + status = "disabled"; + }; +}; + +&misc { + uart1: serial@200 { + compatible = "snps,dw-apb-uart"; + reg = <0x200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&reset2 RTD1195_RSTN_UR1>; + clock-frequency = <27000000>; + status = "disabled"; + }; +}; diff --git a/src/arm/s5pv210-aries.dtsi b/src/arm/s5pv210-aries.dtsi index 8ff70b856334..cf858029292e 100644 --- a/src/arm/s5pv210-aries.dtsi +++ b/src/arm/s5pv210-aries.dtsi @@ -11,9 +11,15 @@ / { compatible = "samsung,aries", "samsung,s5pv210"; - aliases { + aliases: aliases { + i2c4 = &i2c_sound; + i2c5 = &i2c_accel; i2c6 = &i2c_pmic; + i2c7 = &i2c_musb; i2c9 = &i2c_fuel; + i2c10 = &i2c_touchkey; + i2c11 = &i2c_prox; + i2c12 = &i2c_magnetometer; }; memory@30000000 { @@ -46,6 +52,21 @@ regulator-name = "vibrator-en"; enable-active-high; gpio = <&gpj1 1 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctr-0 = <&vibrator_ena>; + }; + + touchkey_vdd: regulator-fixed-1 { + compatible = "regulator-fixed"; + regulator-name = "VTOUCH_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpj3 2 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_vdd_ena>; }; wifi_pwrseq: wifi-pwrseq { @@ -57,7 +78,71 @@ power-off-delay-us = <500>; }; - i2c_pmic: i2c-gpio-0 { + i2c_sound: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&mp05 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&mp05 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&sound_i2c_pins>; + + wm8994: wm8994@1a { + compatible = "wlf,wm8994"; + reg = <0x1a>; + + #sound-dai-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + clocks = <&clocks MOUT_CLKOUT>; + clock-names = "MCLK1"; + + AVDD2-supply = <&buck3_reg>; + DBVDD-supply = <&buck3_reg>; + CPVDD-supply = <&buck3_reg>; + SPKVDD1-supply = <&buck3_reg>; + SPKVDD2-supply = <&buck3_reg>; + + wlf,gpio-cfg = <0xa101 0x8100 0x0100 0x0100 0x8100 + 0xa101 0x0100 0x8100 0x0100 0x0100 + 0x0100>; + + wlf,ldo1ena = <&gpf3 4 GPIO_ACTIVE_HIGH>; + wlf,ldo2ena = <&gpf3 4 GPIO_ACTIVE_HIGH>; + + wlf,lineout1-se; + wlf,lineout2-se; + + assigned-clocks = <&clocks MOUT_CLKOUT>; + assigned-clock-rates = <0>; + assigned-clock-parents = <&xusbxti>; + + pinctrl-names = "default"; + pinctrl-0 = <&codec_ldo>; + }; + }; + + i2c_accel: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&accel_i2c_pins>; + + status = "disabled"; + + /* bma023 accelerometer, no mainline binding */ + }; + + i2c_pmic: i2c-gpio-2 { compatible = "i2c-gpio"; sda-gpios = <&gpj4 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpj4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -65,6 +150,9 @@ #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_i2c_pins>; + pmic@66 { compatible = "maxim,max8998"; reg = <0x66>; @@ -81,6 +169,9 @@ max8998,pmic-buck2-dvs-gpio = <&gph0 5 GPIO_ACTIVE_HIGH>; max8998,pmic-buck2-dvs-voltage = <1100000>, <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_dvs_pins &pmic_irq>; + regulators { ldo2_reg: LDO2 { regulator-name = "VALIVE_1.2V"; @@ -107,7 +198,6 @@ regulator-name = "VADC_3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; regulator-state-mem { regulator-off-in-suspend; @@ -134,8 +224,6 @@ regulator-name = "VLCD_1.8V"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - /* Till we get panel driver */ - regulator-always-on; regulator-state-mem { regulator-off-in-suspend; @@ -234,8 +322,6 @@ regulator-name = "VCC_3.0V_LCD"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; - /* Till we get panel driver */ - regulator-always-on; regulator-state-mem { regulator-off-in-suspend; @@ -306,7 +392,29 @@ }; }; - i2c_fuel: i2c-gpio-1 { + i2c_musb: i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj3 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&musb_i2c_pins>; + + fsa9480: musb@25 { + compatible = "fcs,fsa9480"; + reg = <0x25>; + interrupt-parent = <&gph2>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&musb_irq>; + }; + }; + + i2c_fuel: i2c-gpio-4 { compatible = "i2c-gpio"; sda-gpios = <&mp05 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&mp05 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -314,6 +422,9 @@ #address-cells = <1>; #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fg_i2c_pins>; + fuelgauge@36 { compatible = "maxim,max17040"; interrupt-parent = <&vic0>; @@ -322,6 +433,64 @@ }; }; + i2c_touchkey: i2c-gpio-5 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_i2c_pins>; + + touchkey@20 { + compatible = "cypress,aries-touchkey"; + reg = <0x20>; + vdd-supply = <&touchkey_vdd>; + vcc-supply = <&buck3_reg>; + linux,keycodes = ; + interrupt-parent = <&gpj4>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&touchkey_irq>; + }; + }; + + i2c_prox: i2c-gpio-6 { + compatible = "i2c-gpio"; + sda-gpios = <&gpg2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpg0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&prox_i2c_pins>; + + status = "disabled"; + + /* Sharp gp2a prox/light sensor, incomplete mainline binding */ + }; + + i2c_magnetometer: i2c-gpio-7 { + compatible = "i2c-gpio"; + sda-gpios = <&gpj0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpj0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&magnetometer_i2c_pins>; + + status = "disabled"; + + /* Yamaha yas529 magnetometer, no mainline binding */ + }; + vibrator: pwm-vibrator { compatible = "pwm-vibrator"; pwms = <&pwm 1 44642 0>; @@ -337,6 +506,45 @@ offset = <0x681c>; /* PS_HOLD_CONTROL */ value = <0x5200>; }; + + spi_lcd: spi-gpio-0 { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&mp04 1 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&mp04 3 GPIO_ACTIVE_HIGH>; + cs-gpios = <&mp01 1 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_spi_pins>; + + panel@0 { + compatible = "samsung,s6e63m0"; + reg = <0>; + reset-gpios = <&mp05 5 GPIO_ACTIVE_LOW>; + vdd3-supply = <&ldo7_reg>; + vci-supply = <&ldo17_reg>; + spi-cs-high; + spi-max-frequency = <1200000>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_rst>; + + port { + lcd_ep: endpoint { + remote-endpoint = <&fimd_ep>; + }; + }; + }; + }; +}; + +&adc { + vdd-supply = <&ldo4_reg>; + + status = "okay"; }; &fimd { @@ -347,18 +555,13 @@ samsung,invert-vden; samsung,invert-vclk; - display-timings { - timing-0 { - /* 480x800@60Hz */ - clock-frequency = <25628040>; - hactive = <480>; - vactive = <800>; - hfront-porch = <16>; - hback-porch = <16>; - hsync-len = <2>; - vfront-porch = <28>; - vback-porch = <1>; - vsync-len = <2>; + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + fimd_ep: endpoint { + remote-endpoint = <&lcd_ep>; }; }; }; @@ -399,12 +602,39 @@ samsung,pin-val = <1>; }; + codec_ldo: codec-ldo { + samsung,pins = "gpf3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + prox_i2c_pins: gp2a-i2c-pins { + samsung,pins = "gpg0-2", "gpg2-2"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + wlan_gpio_rst: wlan-gpio-rst { samsung,pins = "gpg1-2"; samsung,pin-function = ; samsung,pin-pud = ; }; + pmic_dvs_pins: pmic-dvs-pins { + samsung,pins = "gph0-3", "gph0-4", "gph0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + + pmic_irq: pmic-irq { + samsung,pins = "gph0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + wifi_host_wake: wifi-host-wake { samsung,pins = "gph2-4"; samsung,pin-function = ; @@ -419,6 +649,13 @@ samsung,pin-drv = ; }; + musb_irq: musq-irq { + samsung,pins = "gph2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + tf_detect: tf-detect { samsung,pins = "gph3-4"; samsung,pin-function = ; @@ -432,12 +669,85 @@ samsung,pin-pud = ; }; + magnetometer_i2c_pins: yas529-i2c-pins { + samsung,pins = "gpj0-0", "gpj0-1"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + ts_irq: ts-irq { samsung,pins = "gpj0-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; + + vibrator_ena: vibrator-ena { + samsung,pins = "gpj1-1"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + touchkey_i2c_pins: touchkey-i2c-pins { + samsung,pins = "gpj3-0", "gpj3-1"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + touchkey_vdd_ena: touchkey-vdd-ena { + samsung,pins = "gpj3-2"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + musb_i2c_pins: musb-i2c-pins { + samsung,pins = "gpj3-4", "gpj3-5"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + accel_i2c_pins: accel-i2c-pins { + samsung,pins = "gpj3-6", "gpj3-7"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pmic_i2c_pins: pmic-i2c-pins { + samsung,pins = "gpj4-0", "gpj4-3"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + touchkey_irq: touchkey-irq { + samsung,pins = "gpj4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_spi_pins: spi-lcd-pins { + samsung,pins = "mp01-1", "mp04-1", "mp04-3"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fg_i2c_pins: fg-i2c-pins { + samsung,pins = "mp05-0", "mp05-1"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sound_i2c_pins: sound-i2c-pins { + samsung,pins = "mp05-2", "mp05-3"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + panel_rst: panel-rst { + samsung,pins = "mp05-5"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pwm { @@ -454,11 +764,16 @@ pinctrl-names = "default"; cap-sd-highspeed; cap-mmc-highspeed; + keep-power-in-suspend; mmc-pwrseq = <&wifi_pwrseq>; non-removable; status = "okay"; + assigned-clocks = <&clocks MOUT_MMC1>, <&clocks SCLK_MMC1>; + assigned-clock-rates = <0>, <50000000>; + assigned-clock-parents = <&clocks MOUT_MPLL>; + wlan@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; @@ -475,6 +790,10 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &tf_detect>; pinctrl-names = "default"; status = "okay"; + + assigned-clocks = <&clocks MOUT_MMC2>, <&clocks SCLK_MMC2>; + assigned-clock-rates = <0>, <50000000>; + assigned-clock-parents = <&clocks MOUT_MPLL>; }; &uart0 { diff --git a/src/arm/s5pv210-fascinate4g.dts b/src/arm/s5pv210-fascinate4g.dts index 07a8d9bbe5b8..5e1b81823a8d 100644 --- a/src/arm/s5pv210-fascinate4g.dts +++ b/src/arm/s5pv210-fascinate4g.dts @@ -36,3 +36,252 @@ }; }; }; + +&pinctrl0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep_cfg>; + + /* Based on vendor kernel v2.6.35.7 */ + sleep_cfg: sleep-cfg { + PIN_SLP(gpa0-0, PREV, NONE); + PIN_SLP(gpa0-1, PREV, NONE); + PIN_SLP(gpa0-2, PREV, NONE); + PIN_SLP(gpa0-3, OUT1, NONE); + PIN_SLP(gpa0-4, PREV, NONE); + PIN_SLP(gpa0-5, PREV, NONE); + PIN_SLP(gpa0-6, PREV, NONE); + PIN_SLP(gpa0-7, PREV, NONE); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, OUT0, NONE); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, OUT0, NONE); + + PIN_SLP(gpb-0, OUT0, NONE); + PIN_SLP(gpb-1, OUT1, NONE); + PIN_SLP(gpb-2, OUT0, NONE); + PIN_SLP(gpb-3, PREV, NONE); + PIN_SLP(gpb-4, INPUT, NONE); + PIN_SLP(gpb-5, PREV, NONE); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, OUT0, NONE); + + PIN_SLP(gpc0-0, OUT0, NONE); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, OUT0, NONE); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, OUT0, NONE); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, OUT0, NONE); + PIN_SLP(gpd0-2, INPUT, DOWN); + PIN_SLP(gpd0-3, INPUT, DOWN); + + PIN_SLP(gpd1-0, INPUT, NONE); + PIN_SLP(gpd1-1, INPUT, NONE); + PIN_SLP(gpd1-2, INPUT, DOWN); + PIN_SLP(gpd1-3, INPUT, DOWN); + PIN_SLP(gpd1-4, INPUT, DOWN); + PIN_SLP(gpd1-5, INPUT, DOWN); + + PIN_SLP(gpe0-0, INPUT, DOWN); + PIN_SLP(gpe0-1, INPUT, DOWN); + PIN_SLP(gpe0-2, INPUT, DOWN); + PIN_SLP(gpe0-3, INPUT, DOWN); + PIN_SLP(gpe0-4, INPUT, DOWN); + PIN_SLP(gpe0-5, INPUT, DOWN); + PIN_SLP(gpe0-6, INPUT, DOWN); + PIN_SLP(gpe0-7, INPUT, DOWN); + + PIN_SLP(gpe1-0, INPUT, DOWN); + PIN_SLP(gpe1-1, INPUT, DOWN); + PIN_SLP(gpe1-2, INPUT, DOWN); + PIN_SLP(gpe1-3, OUT0, NONE); + PIN_SLP(gpe1-4, INPUT, DOWN); + + PIN_SLP(gpf0-0, OUT0, NONE); + PIN_SLP(gpf0-1, OUT0, NONE); + PIN_SLP(gpf0-2, OUT0, NONE); + PIN_SLP(gpf0-3, OUT0, NONE); + PIN_SLP(gpf0-4, OUT0, NONE); + PIN_SLP(gpf0-5, OUT0, NONE); + PIN_SLP(gpf0-6, OUT0, NONE); + PIN_SLP(gpf0-7, OUT0, NONE); + + PIN_SLP(gpf1-0, OUT0, NONE); + PIN_SLP(gpf1-1, OUT0, NONE); + PIN_SLP(gpf1-2, OUT0, NONE); + PIN_SLP(gpf1-3, OUT0, NONE); + PIN_SLP(gpf1-4, OUT0, NONE); + PIN_SLP(gpf1-5, OUT0, NONE); + PIN_SLP(gpf1-6, OUT0, NONE); + PIN_SLP(gpf1-7, OUT0, NONE); + + PIN_SLP(gpf2-0, OUT0, NONE); + PIN_SLP(gpf2-1, OUT0, NONE); + PIN_SLP(gpf2-2, OUT0, NONE); + PIN_SLP(gpf2-3, OUT0, NONE); + PIN_SLP(gpf2-4, OUT0, NONE); + PIN_SLP(gpf2-5, OUT0, NONE); + PIN_SLP(gpf2-6, OUT0, NONE); + PIN_SLP(gpf2-7, OUT0, NONE); + + PIN_SLP(gpf3-0, OUT0, NONE); + PIN_SLP(gpf3-1, OUT0, NONE); + PIN_SLP(gpf3-2, OUT0, NONE); + PIN_SLP(gpf3-3, OUT0, NONE); + PIN_SLP(gpf3-4, PREV, NONE); + PIN_SLP(gpf3-5, INPUT, DOWN); + + PIN_SLP(gpg0-0, INPUT, DOWN); + PIN_SLP(gpg0-1, INPUT, DOWN); + PIN_SLP(gpg0-2, INPUT, NONE); + PIN_SLP(gpg0-3, INPUT, DOWN); + PIN_SLP(gpg0-4, INPUT, DOWN); + PIN_SLP(gpg0-5, INPUT, DOWN); + PIN_SLP(gpg0-6, INPUT, DOWN); + + PIN_SLP(gpg1-0, OUT0, NONE); + PIN_SLP(gpg1-1, OUT1, NONE); + PIN_SLP(gpg1-2, PREV, NONE); + PIN_SLP(gpg1-3, OUT1, NONE); + PIN_SLP(gpg1-4, OUT1, NONE); + PIN_SLP(gpg1-5, OUT1, NONE); + PIN_SLP(gpg1-6, OUT1, NONE); + + PIN_SLP(gpg2-0, OUT0, NONE); + PIN_SLP(gpg2-1, OUT0, NONE); + PIN_SLP(gpg2-2, INPUT, NONE); + PIN_SLP(gpg2-3, OUT0, NONE); + PIN_SLP(gpg2-4, OUT0, NONE); + PIN_SLP(gpg2-5, OUT0, NONE); + PIN_SLP(gpg2-6, OUT0, NONE); + + PIN_SLP(gpg3-0, PREV, UP); + PIN_SLP(gpg3-1, PREV, UP); + PIN_SLP(gpg3-2, INPUT, NONE); + PIN_SLP(gpg3-3, INPUT, DOWN); + PIN_SLP(gpg3-4, OUT0, NONE); + PIN_SLP(gpg3-5, OUT0, NONE); + PIN_SLP(gpg3-6, INPUT, DOWN); + + PIN_SLP(gpi-0, PREV, NONE); + PIN_SLP(gpi-1, INPUT, DOWN); + PIN_SLP(gpi-2, PREV, NONE); + PIN_SLP(gpi-3, PREV, NONE); + PIN_SLP(gpi-4, PREV, NONE); + PIN_SLP(gpi-5, INPUT, DOWN); + PIN_SLP(gpi-6, INPUT, DOWN); + + PIN_SLP(gpj0-0, INPUT, NONE); + PIN_SLP(gpj0-1, INPUT, NONE); + PIN_SLP(gpj0-2, INPUT, NONE); + PIN_SLP(gpj0-3, INPUT, NONE); + PIN_SLP(gpj0-4, INPUT, NONE); + PIN_SLP(gpj0-5, INPUT, DOWN); + PIN_SLP(gpj0-6, OUT0, NONE); + PIN_SLP(gpj0-7, INPUT, NONE); + + PIN_SLP(gpj1-0, OUT1, NONE); + PIN_SLP(gpj1-1, OUT0, NONE); + PIN_SLP(gpj1-2, INPUT, DOWN); + PIN_SLP(gpj1-3, PREV, NONE); + PIN_SLP(gpj1-4, PREV, NONE); + PIN_SLP(gpj1-5, OUT0, NONE); + + PIN_SLP(gpj2-0, INPUT, DOWN); + PIN_SLP(gpj2-1, INPUT, DOWN); + PIN_SLP(gpj2-2, OUT0, NONE); + PIN_SLP(gpj2-3, INPUT, DOWN); + PIN_SLP(gpj2-4, INPUT, DOWN); + PIN_SLP(gpj2-5, PREV, NONE); + PIN_SLP(gpj2-6, PREV, NONE); + PIN_SLP(gpj2-7, INPUT, DOWN); + + PIN_SLP(gpj3-0, INPUT, NONE); + PIN_SLP(gpj3-1, INPUT, NONE); + PIN_SLP(gpj3-2, OUT0, NONE); + PIN_SLP(gpj3-3, INPUT, DOWN); + PIN_SLP(gpj3-4, INPUT, NONE); + PIN_SLP(gpj3-5, INPUT, NONE); + PIN_SLP(gpj3-6, INPUT, NONE); + PIN_SLP(gpj3-7, INPUT, NONE); + + PIN_SLP(gpj4-0, INPUT, NONE); + PIN_SLP(gpj4-1, INPUT, DOWN); + PIN_SLP(gpj4-2, PREV, NONE); + PIN_SLP(gpj4-3, INPUT, NONE); + PIN_SLP(gpj4-4, INPUT, DOWN); + + PIN_SLP(mp01-0, OUT1, NONE); + PIN_SLP(mp01-1, OUT0, NONE); + PIN_SLP(mp01-2, INPUT, DOWN); + PIN_SLP(mp01-3, INPUT, DOWN); + PIN_SLP(mp01-4, OUT1, NONE); + PIN_SLP(mp01-5, INPUT, DOWN); + PIN_SLP(mp01-6, INPUT, DOWN); + PIN_SLP(mp01-7, INPUT, DOWN); + + PIN_SLP(mp02-0, INPUT, DOWN); + PIN_SLP(mp02-1, INPUT, DOWN); + PIN_SLP(mp02-2, INPUT, NONE); + PIN_SLP(mp02-3, INPUT, DOWN); + + PIN_SLP(mp03-0, INPUT, DOWN); + PIN_SLP(mp03-1, INPUT, DOWN); + PIN_SLP(mp03-2, OUT1, NONE); + PIN_SLP(mp03-3, OUT0, NONE); + PIN_SLP(mp03-4, INPUT, NONE); + PIN_SLP(mp03-5, OUT0, NONE); + PIN_SLP(mp03-6, INPUT, DOWN); + PIN_SLP(mp03-7, INPUT, DOWN); + + PIN_SLP(mp04-0, INPUT, DOWN); + PIN_SLP(mp04-1, OUT0, NONE); + PIN_SLP(mp04-2, INPUT, DOWN); + PIN_SLP(mp04-3, OUT0, NONE); + PIN_SLP(mp04-4, INPUT, DOWN); + PIN_SLP(mp04-5, INPUT, DOWN); + PIN_SLP(mp04-6, OUT0, NONE); + PIN_SLP(mp04-7, INPUT, DOWN); + + PIN_SLP(mp05-0, INPUT, NONE); + PIN_SLP(mp05-1, INPUT, NONE); + PIN_SLP(mp05-2, INPUT, NONE); + PIN_SLP(mp05-3, INPUT, NONE); + PIN_SLP(mp05-4, INPUT, DOWN); + PIN_SLP(mp05-5, OUT0, NONE); + PIN_SLP(mp05-6, INPUT, DOWN); + PIN_SLP(mp05-7, PREV, NONE); + + PIN_SLP(mp06-0, INPUT, DOWN); + PIN_SLP(mp06-1, INPUT, DOWN); + PIN_SLP(mp06-2, INPUT, DOWN); + PIN_SLP(mp06-3, INPUT, DOWN); + PIN_SLP(mp06-4, INPUT, DOWN); + PIN_SLP(mp06-5, INPUT, DOWN); + PIN_SLP(mp06-6, INPUT, DOWN); + PIN_SLP(mp06-7, INPUT, DOWN); + + PIN_SLP(mp07-0, INPUT, DOWN); + PIN_SLP(mp07-1, INPUT, DOWN); + PIN_SLP(mp07-2, INPUT, DOWN); + PIN_SLP(mp07-3, INPUT, DOWN); + PIN_SLP(mp07-4, INPUT, DOWN); + PIN_SLP(mp07-5, INPUT, DOWN); + PIN_SLP(mp07-6, INPUT, DOWN); + PIN_SLP(mp07-7, INPUT, DOWN); + }; +}; + +&wm8994 { + /* GPIO3 (BCLK2) and GPIO4 (LRCLK2) as outputs */ + wlf,gpio-cfg = <0xa101 0x8100 0x8100 0x8100 0x8100 0xa101 + 0x0100 0x8100 0x0100 0x0100 0x0100>; +}; diff --git a/src/arm/s5pv210-galaxys.dts b/src/arm/s5pv210-galaxys.dts index cf161bbfbacf..5d10dd67eacc 100644 --- a/src/arm/s5pv210-galaxys.dts +++ b/src/arm/s5pv210-galaxys.dts @@ -49,15 +49,303 @@ wakeup-source; }; }; + + i2c_fmradio: i2c-gpio-8 { + compatible = "i2c-gpio"; + sda-gpios = <&gpd1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpd1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&fm_i2c_pins>; + + fmradio@10 { + compatible = "silabs,si470x"; + reg = <0x10>; + interrupt-parent = <&gpj2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpj2 5 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&fm_irq &fm_rst>; + }; + }; +}; + +&aliases { + i2c8 = &i2c_fmradio; }; &pinctrl0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep_cfg>; + + fm_i2c_pins: fm-i2c-pins { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fm_irq: fm-irq { + samsung,pins = "gpj2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fm_rst: fm-rst { + samsung,pins = "gpj2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + massmemory_en: massmemory-en { samsung,pins = "gpj2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; + + /* Based on CyanogenMod 3.0.101 kernel */ + sleep_cfg: sleep-cfg { + PIN_SLP(gpa0-0, PREV, NONE); + PIN_SLP(gpa0-1, PREV, NONE); + PIN_SLP(gpa0-2, PREV, NONE); + PIN_SLP(gpa0-3, OUT1, NONE); + PIN_SLP(gpa0-4, INPUT, DOWN); + PIN_SLP(gpa0-5, OUT0, NONE); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, OUT1, NONE); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, OUT0, NONE); + PIN_SLP(gpa1-2, INPUT, NONE); + PIN_SLP(gpa1-3, OUT0, NONE); + + PIN_SLP(gpb-0, OUT0, NONE); + PIN_SLP(gpb-1, OUT1, NONE); + PIN_SLP(gpb-2, OUT0, NONE); + PIN_SLP(gpb-3, PREV, NONE); + PIN_SLP(gpb-4, INPUT, NONE); + PIN_SLP(gpb-5, PREV, NONE); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, OUT0, NONE); + + PIN_SLP(gpc0-0, OUT0, NONE); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, OUT0, NONE); + PIN_SLP(gpc0-3, INPUT, NONE); + PIN_SLP(gpc0-4, OUT0, NONE); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, OUT0, NONE); + PIN_SLP(gpd0-2, INPUT, DOWN); + PIN_SLP(gpd0-3, INPUT, DOWN); + + PIN_SLP(gpd1-0, INPUT, NONE); + PIN_SLP(gpd1-1, INPUT, NONE); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + PIN_SLP(gpd1-4, INPUT, DOWN); + PIN_SLP(gpd1-5, INPUT, DOWN); + + PIN_SLP(gpe0-0, INPUT, DOWN); + PIN_SLP(gpe0-1, INPUT, DOWN); + PIN_SLP(gpe0-2, INPUT, DOWN); + PIN_SLP(gpe0-3, INPUT, DOWN); + PIN_SLP(gpe0-4, INPUT, DOWN); + PIN_SLP(gpe0-5, INPUT, DOWN); + PIN_SLP(gpe0-6, INPUT, DOWN); + PIN_SLP(gpe0-7, INPUT, DOWN); + + PIN_SLP(gpe1-0, INPUT, DOWN); + PIN_SLP(gpe1-1, INPUT, DOWN); + PIN_SLP(gpe1-2, INPUT, DOWN); + PIN_SLP(gpe1-3, OUT0, NONE); + PIN_SLP(gpe1-4, INPUT, DOWN); + + PIN_SLP(gpf0-0, OUT0, NONE); + PIN_SLP(gpf0-1, OUT0, NONE); + PIN_SLP(gpf0-2, OUT0, NONE); + PIN_SLP(gpf0-3, OUT0, NONE); + PIN_SLP(gpf0-4, OUT0, NONE); + PIN_SLP(gpf0-5, OUT0, NONE); + PIN_SLP(gpf0-6, OUT0, NONE); + PIN_SLP(gpf0-7, OUT0, NONE); + + PIN_SLP(gpf1-0, OUT0, NONE); + PIN_SLP(gpf1-1, OUT0, NONE); + PIN_SLP(gpf1-2, OUT0, NONE); + PIN_SLP(gpf1-3, OUT0, NONE); + PIN_SLP(gpf1-4, OUT0, NONE); + PIN_SLP(gpf1-5, OUT0, NONE); + PIN_SLP(gpf1-6, OUT0, NONE); + PIN_SLP(gpf1-7, OUT0, NONE); + + PIN_SLP(gpf2-0, OUT0, NONE); + PIN_SLP(gpf2-1, OUT0, NONE); + PIN_SLP(gpf2-2, OUT0, NONE); + PIN_SLP(gpf2-3, OUT0, NONE); + PIN_SLP(gpf2-4, OUT0, NONE); + PIN_SLP(gpf2-5, OUT0, NONE); + PIN_SLP(gpf2-6, OUT0, NONE); + PIN_SLP(gpf2-7, OUT0, NONE); + + PIN_SLP(gpf3-0, OUT0, NONE); + PIN_SLP(gpf3-1, OUT0, NONE); + PIN_SLP(gpf3-2, OUT0, NONE); + PIN_SLP(gpf3-3, OUT0, NONE); + PIN_SLP(gpf3-4, PREV, NONE); + PIN_SLP(gpf3-5, INPUT, DOWN); + + PIN_SLP(gpg0-0, OUT0, NONE); + PIN_SLP(gpg0-1, INPUT, NONE); + PIN_SLP(gpg0-2, INPUT, NONE); + PIN_SLP(gpg0-3, INPUT, NONE); + PIN_SLP(gpg0-4, INPUT, NONE); + PIN_SLP(gpg0-5, INPUT, NONE); + PIN_SLP(gpg0-6, INPUT, NONE); + + PIN_SLP(gpg1-0, OUT0, NONE); + PIN_SLP(gpg1-1, OUT1, NONE); + PIN_SLP(gpg1-2, PREV, NONE); + PIN_SLP(gpg1-3, OUT1, NONE); + PIN_SLP(gpg1-4, OUT1, NONE); + PIN_SLP(gpg1-5, OUT1, NONE); + PIN_SLP(gpg1-6, OUT1, NONE); + + PIN_SLP(gpg2-0, OUT0, NONE); + PIN_SLP(gpg2-1, OUT0, NONE); + PIN_SLP(gpg2-2, INPUT, NONE); + PIN_SLP(gpg2-3, OUT0, NONE); + PIN_SLP(gpg2-4, OUT0, NONE); + PIN_SLP(gpg2-5, OUT0, NONE); + PIN_SLP(gpg2-6, OUT0, NONE); + + PIN_SLP(gpg3-0, OUT1, NONE); + PIN_SLP(gpg3-1, OUT0, NONE); + PIN_SLP(gpg3-2, INPUT, NONE); + PIN_SLP(gpg3-3, INPUT, DOWN); + PIN_SLP(gpg3-4, OUT0, NONE); + PIN_SLP(gpg3-5, OUT0, NONE); + PIN_SLP(gpg3-6, INPUT, DOWN); + + PIN_SLP(gpi-0, PREV, NONE); + PIN_SLP(gpi-1, INPUT, DOWN); + PIN_SLP(gpi-2, PREV, NONE); + PIN_SLP(gpi-3, PREV, NONE); + PIN_SLP(gpi-4, PREV, NONE); + PIN_SLP(gpi-5, INPUT, DOWN); + PIN_SLP(gpi-6, INPUT, DOWN); + + PIN_SLP(gpj0-0, INPUT, NONE); + PIN_SLP(gpj0-1, INPUT, NONE); + PIN_SLP(gpj0-2, INPUT, NONE); + PIN_SLP(gpj0-3, INPUT, NONE); + PIN_SLP(gpj0-4, INPUT, NONE); + PIN_SLP(gpj0-5, INPUT, DOWN); + PIN_SLP(gpj0-6, OUT0, NONE); + PIN_SLP(gpj0-7, INPUT, NONE); + + PIN_SLP(gpj1-0, INPUT, DOWN); + PIN_SLP(gpj1-1, OUT0, NONE); + PIN_SLP(gpj1-2, INPUT, DOWN); + PIN_SLP(gpj1-3, PREV, NONE); + PIN_SLP(gpj1-4, PREV, NONE); + PIN_SLP(gpj1-5, OUT0, NONE); + + PIN_SLP(gpj2-0, INPUT, DOWN); + PIN_SLP(gpj2-1, INPUT, DOWN); + PIN_SLP(gpj2-2, OUT0, NONE); + PIN_SLP(gpj2-3, INPUT, DOWN); + PIN_SLP(gpj2-4, INPUT, UP); + PIN_SLP(gpj2-5, PREV, NONE); + PIN_SLP(gpj2-6, PREV, NONE); + PIN_SLP(gpj2-7, OUT1, NONE); + + PIN_SLP(gpj3-0, INPUT, NONE); + PIN_SLP(gpj3-1, INPUT, NONE); + PIN_SLP(gpj3-2, OUT0, NONE); + PIN_SLP(gpj3-3, INPUT, DOWN); + PIN_SLP(gpj3-4, INPUT, NONE); + PIN_SLP(gpj3-5, INPUT, NONE); + PIN_SLP(gpj3-6, INPUT, NONE); + PIN_SLP(gpj3-7, INPUT, NONE); + + PIN_SLP(gpj4-0, INPUT, NONE); + PIN_SLP(gpj4-1, INPUT, DOWN); + PIN_SLP(gpj4-2, PREV, NONE); + PIN_SLP(gpj4-3, INPUT, NONE); + PIN_SLP(gpj4-4, INPUT, DOWN); + + PIN_SLP(mp01-0, INPUT, DOWN); + PIN_SLP(mp01-1, OUT0, NONE); + PIN_SLP(mp01-2, INPUT, DOWN); + PIN_SLP(mp01-3, INPUT, DOWN); + PIN_SLP(mp01-4, OUT1, NONE); + PIN_SLP(mp01-5, INPUT, DOWN); + PIN_SLP(mp01-6, INPUT, DOWN); + PIN_SLP(mp01-7, INPUT, DOWN); + + PIN_SLP(mp02-0, INPUT, DOWN); + PIN_SLP(mp02-1, INPUT, DOWN); + PIN_SLP(mp02-2, INPUT, NONE); + PIN_SLP(mp02-3, INPUT, DOWN); + + PIN_SLP(mp03-0, INPUT, DOWN); + PIN_SLP(mp03-1, INPUT, DOWN); + PIN_SLP(mp03-2, OUT1, NONE); + PIN_SLP(mp03-3, OUT0, NONE); + PIN_SLP(mp03-4, INPUT, NONE); + PIN_SLP(mp03-5, OUT1, NONE); + PIN_SLP(mp03-6, INPUT, DOWN); + PIN_SLP(mp03-7, INPUT, DOWN); + + PIN_SLP(mp04-0, INPUT, DOWN); + PIN_SLP(mp04-1, OUT0, NONE); + PIN_SLP(mp04-2, INPUT, DOWN); + PIN_SLP(mp04-3, OUT0, NONE); + PIN_SLP(mp04-4, INPUT, DOWN); + PIN_SLP(mp04-5, INPUT, DOWN); + PIN_SLP(mp04-6, OUT0, NONE); + PIN_SLP(mp04-7, INPUT, DOWN); + + PIN_SLP(mp05-0, INPUT, NONE); + PIN_SLP(mp05-1, INPUT, NONE); + PIN_SLP(mp05-2, INPUT, NONE); + PIN_SLP(mp05-3, INPUT, NONE); + PIN_SLP(mp05-4, INPUT, DOWN); + PIN_SLP(mp05-5, OUT0, NONE); + PIN_SLP(mp05-6, INPUT, DOWN); + PIN_SLP(mp05-7, PREV, NONE); + + PIN_SLP(mp06-0, INPUT, DOWN); + PIN_SLP(mp06-1, INPUT, DOWN); + PIN_SLP(mp06-2, INPUT, DOWN); + PIN_SLP(mp06-3, INPUT, DOWN); + PIN_SLP(mp06-4, INPUT, DOWN); + PIN_SLP(mp06-5, INPUT, DOWN); + PIN_SLP(mp06-6, INPUT, DOWN); + PIN_SLP(mp06-7, INPUT, DOWN); + + PIN_SLP(mp07-0, INPUT, DOWN); + PIN_SLP(mp07-1, INPUT, DOWN); + PIN_SLP(mp07-2, INPUT, DOWN); + PIN_SLP(mp07-3, INPUT, DOWN); + PIN_SLP(mp07-4, INPUT, DOWN); + PIN_SLP(mp07-5, INPUT, DOWN); + PIN_SLP(mp07-6, INPUT, DOWN); + PIN_SLP(mp07-7, INPUT, DOWN); + }; }; &sdhci0 { @@ -67,4 +355,8 @@ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>; pinctrl-names = "default"; status = "okay"; + + assigned-clocks = <&clocks MOUT_MMC0>, <&clocks SCLK_MMC0>; + assigned-clock-rates = <0>, <52000000>; + assigned-clock-parents = <&clocks MOUT_MPLL>; }; diff --git a/src/arm/s5pv210-pinctrl.dtsi b/src/arm/s5pv210-pinctrl.dtsi index 7f0c9d447871..5e8b66281f01 100644 --- a/src/arm/s5pv210-pinctrl.dtsi +++ b/src/arm/s5pv210-pinctrl.dtsi @@ -18,6 +18,13 @@ #include +#define PIN_SLP(_pin, _mode, _pull) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-con-pdn = ; \ + samsung,pin-pud-pdn = ; \ + } + &pinctrl0 { gpa0: gpa0 { gpio-controller; @@ -195,7 +202,7 @@ #interrupt-cells = <2>; }; - gpgi: gpgi { + gpi: gpi { gpio-controller; #gpio-cells = <2>; }; diff --git a/src/arm/s5pv210.dtsi b/src/arm/s5pv210.dtsi index 2ad642f51fd9..1b0ee884e91d 100644 --- a/src/arm/s5pv210.dtsi +++ b/src/arm/s5pv210.dtsi @@ -159,6 +159,18 @@ }; }; + adc: adc@e1700000 { + compatible = "samsung,s5pv210-adc"; + reg = <0xe1700000 0x1000>; + interrupt-parent = <&vic2>; + interrupts = <23>, <24>; + clocks = <&clocks CLK_TSADC>; + clock-names = "adc"; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; + spi0: spi@e1300000 { compatible = "samsung,s5pv210-spi"; reg = <0xe1300000 0x1000>; @@ -614,7 +626,7 @@ clock-names = "fimc", "sclk_fimc"; samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; + samsung,min-pix-alignment = <16 8>; samsung,cam-if; }; @@ -628,8 +640,10 @@ clock-names = "fimc", "sclk_fimc"; samsung,pix-limits = <4224 8192 1920 4224>; + samsung,min-pix-alignment = <1 1>; samsung,mainscaler-ext; samsung,cam-if; + samsung,lcd-wb; }; fimc2: fimc@fb400000 { @@ -641,9 +655,10 @@ <&clocks SCLK_FIMC2>; clock-names = "fimc", "sclk_fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,lcd-wb; + samsung,pix-limits = <1920 8192 1280 1920>; + samsung,min-pix-alignment = <16 8>; + samsung,rotators = <0>; + samsung,cam-if; }; }; diff --git a/src/arm/sama5d2.dtsi b/src/arm/sama5d2.dtsi index ab550d69db91..31d8766ec7ef 100644 --- a/src/arm/sama5d2.dtsi +++ b/src/arm/sama5d2.dtsi @@ -21,10 +21,6 @@ aliases { serial0 = &uart1; serial1 = &uart3; - tcb0 = &tcb0; - tcb1 = &tcb1; - i2s0 = &i2s0; - i2s1 = &i2s1; }; cpus { @@ -113,8 +109,6 @@ }; usb0: gadget@300000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,sama5d3-udc"; reg = <0x00300000 0x100000 0xfc02c000 0x400>; @@ -122,124 +116,6 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@7 { - reg = <7>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@8 { - reg = <8>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@9 { - reg = <9>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@10 { - reg = <10>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@11 { - reg = <11>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@12 { - reg = <12>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@13 { - reg = <13>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@14 { - reg = <14>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@15 { - reg = <15>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; }; usb1: ohci@400000 { @@ -635,6 +511,64 @@ #size-cells = <1>; ranges = <0x0 0xf8034000 0x800>; status = "disabled"; + + uart5: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi2: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx1: flexcom@f8038000 { @@ -645,6 +579,64 @@ #size-cells = <1>; ranges = <0x0 0xf8038000 0x800>; status = "disabled"; + + uart6: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi3: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c3: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; securam: sram@f8044000 { @@ -794,6 +786,64 @@ #size-cells = <1>; ranges = <0x0 0xfc010000 0x800>; status = "disabled"; + + uart7: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi4: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c4: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx3: flexcom@fc014000 { @@ -804,6 +854,65 @@ #size-cells = <1>; ranges = <0x0 0xfc014000 0x800>; status = "disabled"; + + uart8: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi5: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c5: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + }; flx4: flexcom@fc018000 { @@ -814,6 +923,64 @@ #size-cells = <1>; ranges = <0x0 0xfc018000 0x800>; status = "disabled"; + + uart9: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "usart"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi6: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c6: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; trng@fc01c000 { diff --git a/src/arm/sama5d3.dtsi b/src/arm/sama5d3.dtsi index f11b018e9173..0bb5b6fa0748 100644 --- a/src/arm/sama5d3.dtsi +++ b/src/arm/sama5d3.dtsi @@ -108,7 +108,7 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; clock-names = "mci_clk"; }; @@ -123,7 +123,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; - clocks = <&spi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; clock-names = "spi_clk"; status = "disabled"; }; @@ -137,7 +137,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; - clocks = <&ssc0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; clock-names = "pclk"; status = "disabled"; }; @@ -148,7 +148,7 @@ #size-cells = <0>; reg = <0xf0010000 0x100>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb0_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; @@ -163,10 +163,10 @@ pinctrl-0 = <&pinctrl_i2c0>; pinctrl-1 = <&pinctrl_i2c0_gpio>; sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; status = "disabled"; }; @@ -181,10 +181,10 @@ pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&pioC 26 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioC 27 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioC 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; status = "disabled"; }; @@ -197,7 +197,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; - clocks = <&usart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "usart"; status = "disabled"; }; @@ -211,7 +211,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; - clocks = <&usart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; clock-names = "usart"; status = "disabled"; }; @@ -222,7 +222,7 @@ interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "usart"; status = "disabled"; }; @@ -232,7 +232,7 @@ reg = <0xf002c000 0x300>; interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; #pwm-cells = <3>; - clocks = <&pwm_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; status = "disabled"; }; @@ -242,7 +242,7 @@ interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_isi_data_0_7>; - clocks = <&isi_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; clock-names = "isi_clk"; status = "disabled"; port { @@ -267,7 +267,7 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; - clocks = <&mci1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; clock-names = "mci_clk"; }; @@ -282,7 +282,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; - clocks = <&spi1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; clock-names = "spi_clk"; status = "disabled"; }; @@ -296,7 +296,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; - clocks = <&ssc1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; clock-names = "pclk"; status = "disabled"; }; @@ -323,7 +323,7 @@ &pinctrl_adc0_ad10 &pinctrl_adc0_ad11 >; - clocks = <&adc_clk>, + clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&adc_op_clk>; clock-names = "adc_clk", "adc_op_clk"; atmel,adc-channels-used = <0xfff>; @@ -367,10 +367,10 @@ pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; sda-gpios = <&pioA 18 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA 19 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; - clocks = <&twi2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; status = "disabled"; }; @@ -383,7 +383,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; - clocks = <&usart2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "usart"; status = "disabled"; }; @@ -397,7 +397,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; - clocks = <&usart3_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "usart"; status = "disabled"; }; @@ -408,7 +408,7 @@ interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; dma-names = "tx"; - clocks = <&sha_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; clock-names = "sha_clk"; }; @@ -419,7 +419,7 @@ dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; dma-names = "tx", "rx"; - clocks = <&aes_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; clock-names = "aes_clk"; }; @@ -430,7 +430,7 @@ dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; dma-names = "tx", "rx"; - clocks = <&tdes_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; clock-names = "tdes_clk"; }; @@ -438,14 +438,14 @@ compatible = "atmel,at91sam9g45-trng"; reg = <0xf8040000 0x100>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&trng_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; }; hsmc: hsmc@ffffc000 { compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; reg = <0xffffc000 0x1000>; interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; - clocks = <&hsmc_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -462,7 +462,7 @@ reg = <0xffffe600 0x200>; interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; clock-names = "dma_clk"; }; @@ -471,14 +471,14 @@ reg = <0xffffe800 0x200>; interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; - clocks = <&dma1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; clock-names = "dma_clk"; }; ramc0: ramc@ffffea00 { compatible = "atmel,sama5d3-ddramc"; reg = <0xffffea00 0x200>; - clocks = <&ddrck>, <&mpddr_clk>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>; clock-names = "ddrck", "mpddr"; }; @@ -491,7 +491,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; - clocks = <&dbgu_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; clock-names = "usart"; status = "disabled"; }; @@ -967,7 +967,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioA_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; }; pioB: gpio@fffff400 { @@ -978,7 +978,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioB_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; }; pioC: gpio@fffff600 { @@ -989,7 +989,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioC_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; }; pioD: gpio@fffff800 { @@ -1000,7 +1000,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioD_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; }; pioE: gpio@fffffa00 { @@ -1011,7 +1011,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; - clocks = <&pioE_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; }; }; @@ -1019,353 +1019,9 @@ compatible = "atmel,sama5d3-pmc", "syscon"; reg = <0xfffffc00 0x120>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; - interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - - main_rc_osc: main_rc_osc { - compatible = "atmel,at91sam9x5-clk-main-rc-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clock-frequency = <12000000>; - clock-accuracy = <50000000>; - }; - - main_osc: main_osc { - compatible = "atmel,at91rm9200-clk-main-osc"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_xtal>; - }; - - main: mainck { - compatible = "atmel,at91sam9x5-clk-main"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main_rc_osc &main_osc>; - }; - - plla: pllack { - compatible = "atmel,sama5d3-clk-pll"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - reg = <0>; - atmel,clk-input-range = <8000000 50000000>; - #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; - }; - - plladiv: plladivck { - compatible = "atmel,at91sam9x5-clk-plldiv"; - #clock-cells = <0>; - clocks = <&plla>; - }; - - utmi: utmick { - compatible = "atmel,at91sam9x5-clk-utmi"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&main>; - }; - - mck: masterck { - compatible = "atmel,at91sam9x5-clk-master"; - #clock-cells = <0>; - interrupt-parent = <&pmc>; - interrupts = ; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; - atmel,clk-output-range = <0 166000000>; - atmel,clk-divisors = <1 2 4 3>; - }; - - usb: usbck { - compatible = "atmel,at91sam9x5-clk-usb"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - prog: progck { - compatible = "atmel,at91sam9x5-clk-programmable"; - #address-cells = <1>; - #size-cells = <0>; - interrupt-parent = <&pmc>; - clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; - - prog0: prog0 { - #clock-cells = <0>; - reg = <0>; - interrupts = ; - }; - - prog1: prog1 { - #clock-cells = <0>; - reg = <1>; - interrupts = ; - }; - - prog2: prog2 { - #clock-cells = <0>; - reg = <2>; - interrupts = ; - }; - }; - - smd: smdclk { - compatible = "atmel,at91sam9x5-clk-smd"; - #clock-cells = <0>; - clocks = <&plladiv>, <&utmi>; - }; - - systemck { - compatible = "atmel,at91rm9200-clk-system"; - #address-cells = <1>; - #size-cells = <0>; - - ddrck: ddrck { - #clock-cells = <0>; - reg = <2>; - clocks = <&mck>; - }; - - smdck: smdck { - #clock-cells = <0>; - reg = <4>; - clocks = <&smd>; - }; - - uhpck: uhpck { - #clock-cells = <0>; - reg = <6>; - clocks = <&usb>; - }; - - udpck: udpck { - #clock-cells = <0>; - reg = <7>; - clocks = <&usb>; - }; - - pck0: pck0 { - #clock-cells = <0>; - reg = <8>; - clocks = <&prog0>; - }; - - pck1: pck1 { - #clock-cells = <0>; - reg = <9>; - clocks = <&prog1>; - }; - - pck2: pck2 { - #clock-cells = <0>; - reg = <10>; - clocks = <&prog2>; - }; - }; - - periphck { - compatible = "atmel,at91sam9x5-clk-peripheral"; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&mck>; - - dbgu_clk: dbgu_clk { - #clock-cells = <0>; - reg = <2>; - }; - - hsmc_clk: hsmc_clk { - #clock-cells = <0>; - reg = <5>; - }; - - pioA_clk: pioA_clk { - #clock-cells = <0>; - reg = <6>; - }; - - pioB_clk: pioB_clk { - #clock-cells = <0>; - reg = <7>; - }; - - pioC_clk: pioC_clk { - #clock-cells = <0>; - reg = <8>; - }; - - pioD_clk: pioD_clk { - #clock-cells = <0>; - reg = <9>; - }; - - pioE_clk: pioE_clk { - #clock-cells = <0>; - reg = <10>; - }; - - usart0_clk: usart0_clk { - #clock-cells = <0>; - reg = <12>; - atmel,clk-output-range = <0 83000000>; - }; - - usart1_clk: usart1_clk { - #clock-cells = <0>; - reg = <13>; - atmel,clk-output-range = <0 83000000>; - }; - - usart2_clk: usart2_clk { - #clock-cells = <0>; - reg = <14>; - atmel,clk-output-range = <0 83000000>; - }; - - usart3_clk: usart3_clk { - #clock-cells = <0>; - reg = <15>; - atmel,clk-output-range = <0 83000000>; - }; - - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <16>; - atmel,clk-output-range = <0 83000000>; - }; - - twi0_clk: twi0_clk { - reg = <18>; - #clock-cells = <0>; - atmel,clk-output-range = <0 41500000>; - }; - - twi1_clk: twi1_clk { - #clock-cells = <0>; - reg = <19>; - atmel,clk-output-range = <0 41500000>; - }; - - twi2_clk: twi2_clk { - #clock-cells = <0>; - reg = <20>; - atmel,clk-output-range = <0 41500000>; - }; - - mci0_clk: mci0_clk { - #clock-cells = <0>; - reg = <21>; - }; - - mci1_clk: mci1_clk { - #clock-cells = <0>; - reg = <22>; - }; - - spi0_clk: spi0_clk { - #clock-cells = <0>; - reg = <24>; - atmel,clk-output-range = <0 166000000>; - }; - - spi1_clk: spi1_clk { - #clock-cells = <0>; - reg = <25>; - atmel,clk-output-range = <0 166000000>; - }; - - tcb0_clk: tcb0_clk { - #clock-cells = <0>; - reg = <26>; - atmel,clk-output-range = <0 166000000>; - }; - - pwm_clk: pwm_clk { - #clock-cells = <0>; - reg = <28>; - }; - - adc_clk: adc_clk { - #clock-cells = <0>; - reg = <29>; - atmel,clk-output-range = <0 83000000>; - }; - - dma0_clk: dma0_clk { - #clock-cells = <0>; - reg = <30>; - }; - - dma1_clk: dma1_clk { - #clock-cells = <0>; - reg = <31>; - }; - - uhphs_clk: uhphs_clk { - #clock-cells = <0>; - reg = <32>; - }; - - udphs_clk: udphs_clk { - #clock-cells = <0>; - reg = <33>; - }; - - isi_clk: isi_clk { - #clock-cells = <0>; - reg = <37>; - }; - - ssc0_clk: ssc0_clk { - #clock-cells = <0>; - reg = <38>; - atmel,clk-output-range = <0 83000000>; - }; - - ssc1_clk: ssc1_clk { - #clock-cells = <0>; - reg = <39>; - atmel,clk-output-range = <0 83000000>; - }; - - sha_clk: sha_clk { - #clock-cells = <0>; - reg = <42>; - }; - - aes_clk: aes_clk { - #clock-cells = <0>; - reg = <43>; - }; - - tdes_clk: tdes_clk { - #clock-cells = <0>; - reg = <44>; - }; - - trng_clk: trng_clk { - #clock-cells = <0>; - reg = <45>; - }; - - fuse_clk: fuse_clk { - #clock-cells = <0>; - reg = <48>; - }; - - mpddr_clk: mpddr_clk { - #clock-cells = <0>; - reg = <49>; - }; - }; + #clock-cells = <2>; + clocks = <&clk32k>, <&main_xtal>; + clock-names = "slow_clk", "main_xtal"; }; reset_controller: rstc@fffffe00 { @@ -1384,7 +1040,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; }; watchdog: watchdog@fffffe40 { @@ -1420,127 +1076,20 @@ }; usb0: gadget@500000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,sama5d3-udc"; reg = <0x00500000 0x100000 0xf8030000 0x4000>; interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&udphs_clk>, <&utmi>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@7 { - reg = <7>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - }; - - ep@8 { - reg = <8>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@9 { - reg = <9>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@10 { - reg = <10>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@11 { - reg = <11>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@12 { - reg = <12>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@13 { - reg = <13>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@14 { - reg = <14>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; - - ep@15 { - reg = <15>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - }; }; usb1: ohci@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_SYSTEM 6>; clock-names = "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -1549,7 +1098,7 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; - clocks = <&utmi>, <&uhphs_clk>; + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 32>; clock-names = "usb_clk", "ehci_clk"; status = "disabled"; }; @@ -1565,7 +1114,7 @@ 0x1 0x0 0x40000000 0x10000000 0x2 0x0 0x50000000 0x10000000 0x3 0x0 0x60000000 0x10000000>; - clocks = <&mck>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; status = "disabled"; nand_controller: nand-controller { diff --git a/src/arm/sama5d3_can.dtsi b/src/arm/sama5d3_can.dtsi index 2470dd3fff25..9ac29bf3f933 100644 --- a/src/arm/sama5d3_can.dtsi +++ b/src/arm/sama5d3_can.dtsi @@ -31,29 +31,13 @@ }; - pmc: pmc@fffffc00 { - periphck { - can0_clk: can0_clk { - #clock-cells = <0>; - reg = <40>; - atmel,clk-output-range = <0 83000000>; - }; - - can1_clk: can1_clk { - #clock-cells = <0>; - reg = <41>; - atmel,clk-output-range = <0 83000000>; - }; - }; - }; - can0: can@f000c000 { compatible = "atmel,at91sam9x5-can"; reg = <0xf000c000 0x300>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_rx_tx>; - clocks = <&can0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; clock-names = "can_clk"; status = "disabled"; }; @@ -64,7 +48,7 @@ interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_rx_tx>; - clocks = <&can1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "can_clk"; status = "disabled"; }; diff --git a/src/arm/sama5d3_emac.dtsi b/src/arm/sama5d3_emac.dtsi index 9aef414bcd2e..45226108850d 100644 --- a/src/arm/sama5d3_emac.dtsi +++ b/src/arm/sama5d3_emac.dtsi @@ -31,12 +31,6 @@ }; pmc: pmc@fffffc00 { - periphck { - macb1_clk: macb1_clk { - #clock-cells = <0>; - reg = <35>; - }; - }; }; macb1: ethernet@f802c000 { @@ -45,7 +39,7 @@ interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb1_rmii>; - clocks = <&macb1_clk>, <&macb1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_PERIPHERAL 35>; clock-names = "hclk", "pclk"; status = "disabled"; }; diff --git a/src/arm/sama5d3_gmac.dtsi b/src/arm/sama5d3_gmac.dtsi index 3667765a138b..884df7a54dbb 100644 --- a/src/arm/sama5d3_gmac.dtsi +++ b/src/arm/sama5d3_gmac.dtsi @@ -63,22 +63,13 @@ }; }; - pmc: pmc@fffffc00 { - periphck { - macb0_clk: macb0_clk { - #clock-cells = <0>; - reg = <34>; - }; - }; - }; - macb0: ethernet@f0028000 { compatible = "atmel,sama5d3-gem"; reg = <0xf0028000 0x100>; interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; - clocks = <&macb0_clk>, <&macb0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_PERIPHERAL 34>; clock-names = "hclk", "pclk"; status = "disabled"; }; diff --git a/src/arm/sama5d3_lcd.dtsi b/src/arm/sama5d3_lcd.dtsi index 2cf046cd4e99..308d2fc276d6 100644 --- a/src/arm/sama5d3_lcd.dtsi +++ b/src/arm/sama5d3_lcd.dtsi @@ -16,7 +16,7 @@ compatible = "atmel,sama5d3-hlcdc"; reg = <0xf0030000 0x2000>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; clock-names = "periph_clk","sys_clk", "slow_clk"; status = "disabled"; @@ -192,23 +192,6 @@ }; }; }; - - pmc: pmc@fffffc00 { - periphck { - lcdc_clk: lcdc_clk { - #clock-cells = <0>; - reg = <36>; - }; - }; - - systemck { - lcdck: lcdck { - #clock-cells = <0>; - reg = <3>; - clocks = <&mck>; - }; - }; - }; }; }; }; diff --git a/src/arm/sama5d3_mci2.dtsi b/src/arm/sama5d3_mci2.dtsi index 3c83c1c36ac8..7141ee97ec3e 100644 --- a/src/arm/sama5d3_mci2.dtsi +++ b/src/arm/sama5d3_mci2.dtsi @@ -30,15 +30,6 @@ }; }; - pmc: pmc@fffffc00 { - periphck { - mci2_clk: mci2_clk { - #clock-cells = <0>; - reg = <23>; - }; - }; - }; - mmc2: mmc@f8004000 { compatible = "atmel,hsmci"; reg = <0xf8004000 0x600>; @@ -47,7 +38,7 @@ dma-names = "rxtx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; - clocks = <&mci2_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; clock-names = "mci_clk"; status = "disabled"; #address-cells = <1>; diff --git a/src/arm/sama5d3_tcb1.dtsi b/src/arm/sama5d3_tcb1.dtsi index 215802b8db30..2b18c5c2cc03 100644 --- a/src/arm/sama5d3_tcb1.dtsi +++ b/src/arm/sama5d3_tcb1.dtsi @@ -17,23 +17,13 @@ ahb { apb { - pmc: pmc@fffffc00 { - periphck { - tcb1_clk: tcb1_clk { - #clock-cells = <0>; - reg = <27>; - atmel,clk-output-range = <0 166000000>; - }; - }; - }; - tcb1: timer@f8014000 { compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; #address-cells = <1>; #size-cells = <0>; reg = <0xf8014000 0x100>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&tcb1_clk>, <&clk32k>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&clk32k>; clock-names = "t0_clk", "slow_clk"; }; }; diff --git a/src/arm/sama5d3_uart.dtsi b/src/arm/sama5d3_uart.dtsi index cb62adbd28ed..a3eaba995cf4 100644 --- a/src/arm/sama5d3_uart.dtsi +++ b/src/arm/sama5d3_uart.dtsi @@ -36,29 +36,13 @@ }; }; - pmc: pmc@fffffc00 { - periphck { - uart0_clk: uart0_clk { - #clock-cells = <0>; - reg = <16>; - atmel,clk-output-range = <0 83000000>; - }; - - uart1_clk: uart1_clk { - #clock-cells = <0>; - reg = <17>; - atmel,clk-output-range = <0 83000000>; - }; - }; - }; - uart0: serial@f0024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf0024000 0x100>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart0_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; clock-names = "usart"; status = "disabled"; }; @@ -69,7 +53,7 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart1_clk>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; clock-names = "usart"; status = "disabled"; }; diff --git a/src/arm/sama5d3xmb.dtsi b/src/arm/sama5d3xmb.dtsi index 35031bbc7e70..a499de8a7a64 100644 --- a/src/arm/sama5d3xmb.dtsi +++ b/src/arm/sama5d3xmb.dtsi @@ -46,7 +46,7 @@ wm8904: wm8904@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - clocks = <&pck0>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; clock-names = "mclk"; }; }; @@ -60,9 +60,9 @@ resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; /* use pck1 for the master clock of ov2640 */ - clocks = <&pck1>; + clocks = <&pmc PMC_TYPE_SYSTEM 9>; clock-names = "xvclk"; - assigned-clocks = <&pck1>; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; assigned-clock-rates = <25000000>; port { diff --git a/src/arm/sama5d3xmb_cmp.dtsi b/src/arm/sama5d3xmb_cmp.dtsi index 8a6916a69da4..fa9e5e2a745d 100644 --- a/src/arm/sama5d3xmb_cmp.dtsi +++ b/src/arm/sama5d3xmb_cmp.dtsi @@ -45,7 +45,7 @@ wm8904: wm8904@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - clocks = <&pck0>; + clocks = <&pmc PMC_TYPE_SYSTEM 8>; clock-names = "mclk"; }; }; @@ -59,9 +59,9 @@ resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>; pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; /* use pck1 for the master clock of ov2640 */ - clocks = <&pck1>; + clocks = <&pmc PMC_TYPE_SYSTEM 9>; clock-names = "xvclk"; - assigned-clocks = <&pck1>; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; assigned-clock-rates = <25000000>; port { diff --git a/src/arm/sama5d4.dtsi b/src/arm/sama5d4.dtsi index c9c0316b5b0e..2d9f853ab15f 100644 --- a/src/arm/sama5d4.dtsi +++ b/src/arm/sama5d4.dtsi @@ -96,8 +96,6 @@ }; usb0: gadget@400000 { - #address-cells = <1>; - #size-cells = <0>; compatible = "atmel,sama5d3-udc"; reg = <0x00400000 0x100000 0xfc02c000 0x4000>; @@ -105,124 +103,6 @@ clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>; clock-names = "pclk", "hclk"; status = "disabled"; - - ep@0 { - reg = <0>; - atmel,fifo-size = <64>; - atmel,nb-banks = <1>; - }; - - ep@1 { - reg = <1>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@2 { - reg = <2>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <3>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@3 { - reg = <3>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@4 { - reg = <4>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@5 { - reg = <5>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@6 { - reg = <6>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@7 { - reg = <7>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-dma; - atmel,can-isoc; - }; - - ep@8 { - reg = <8>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@9 { - reg = <9>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@10 { - reg = <10>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@11 { - reg = <11>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@12 { - reg = <12>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@13 { - reg = <13>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@14 { - reg = <14>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; - - ep@15 { - reg = <15>; - atmel,fifo-size = <1024>; - atmel,nb-banks = <2>; - atmel,can-isoc; - }; }; usb1: ohci@500000 { @@ -462,7 +342,7 @@ pinctrl-0 = <&pinctrl_i2c0>; pinctrl-1 = <&pinctrl_i2c0_gpio>; sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; @@ -484,7 +364,7 @@ pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; sda-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioE 30 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioE 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; @@ -529,7 +409,7 @@ pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; sda-gpios = <&pioB 29 GPIO_ACTIVE_HIGH>; - scl-gpios = <&pioB 30 GPIO_ACTIVE_HIGH>; + scl-gpios = <&pioB 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; #address-cells = <1>; #size-cells = <0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; diff --git a/src/arm/sh73a0.dtsi b/src/arm/sh73a0.dtsi index c134154bcce8..01fd06328420 100644 --- a/src/arm/sh73a0.dtsi +++ b/src/arm/sh73a0.dtsi @@ -99,7 +99,7 @@ }; cmt1: timer@e6138000 { - compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; + compatible = "renesas,sh73a0-cmt1"; reg = <0xe6138000 0x200>; interrupts = ; clocks = <&mstp3_clks SH73A0_CLK_CMT1>; diff --git a/src/arm/socfpga.dtsi b/src/arm/socfpga.dtsi index 4f3993cc0227..78f3267d9cbf 100644 --- a/src/arm/socfpga.dtsi +++ b/src/arm/socfpga.dtsi @@ -531,6 +531,7 @@ reg = <0xff400000 0x100000>; resets = <&rst LWHPS2FPGA_RESET>; clocks = <&l4_main_clk>; + status = "disabled"; }; fpga_bridge1: fpga_bridge@ff500000 { @@ -538,6 +539,21 @@ reg = <0xff500000 0x10000>; resets = <&rst HPS2FPGA_RESET>; clocks = <&l4_main_clk>; + status = "disabled"; + }; + + fpga_bridge2: fpga-bridge@ff600000 { + compatible = "altr,socfpga-fpga2hps-bridge"; + reg = <0xff600000 0x100000>; + resets = <&rst FPGA2HPS_RESET>; + clocks = <&l4_main_clk>; + status = "disabled"; + }; + + fpga_bridge3: fpga-bridge@ffc25080 { + compatible = "altr,socfpga-fpga2sdram-bridge"; + reg = <0xffc25080 0x4>; + status = "disabled"; }; fpgamgr0: fpgamgr@ff706000 { @@ -710,7 +726,7 @@ }; }; - L2: l2-cache@fffef000 { + L2: cache-controller@fffef000 { compatible = "arm,pl310-cache"; reg = <0xfffef000 0x1000>; interrupts = <0 38 0x04>; diff --git a/src/arm/socfpga_arria10.dtsi b/src/arm/socfpga_arria10.dtsi index 3b8571b8b412..8f614c4b0e3e 100644 --- a/src/arm/socfpga_arria10.dtsi +++ b/src/arm/socfpga_arria10.dtsi @@ -636,7 +636,7 @@ reg = <0xffcfb100 0x80>; }; - L2: l2-cache@fffff000 { + L2: cache-controller@fffff000 { compatible = "arm,pl310-cache"; reg = <0xfffff000 0x1000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; diff --git a/src/arm/ste-ux500-samsung-golden.dts b/src/arm/ste-ux500-samsung-golden.dts index 313f0ab16866..5b499c0b2745 100644 --- a/src/arm/ste-ux500-samsung-golden.dts +++ b/src/arm/ste-ux500-samsung-golden.dts @@ -24,6 +24,26 @@ stdout-path = &serial2; }; + i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpio4 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio4 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c_gpio_1_default>; + + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + + avdd-supply = <&ab8500_ldo_aux1_reg>; + dvdd-supply = <&ab8500_ldo_aux8_reg>; + }; + }; + soc { /* External Micro SD card slot */ sdi0_per1@80126000 { @@ -146,6 +166,32 @@ pinctrl-1 = <&u2rxtx_c_1_sleep>; }; + i2c@80004000 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c0_a_1_default>; + pinctrl-1 = <&i2c0_a_1_sleep>; + + proximity@44 { + compatible = "sharp,gp2ap002s00f"; + reg = <0x44>; + + /* GPIO146 (PS_INT) */ + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&ab8500_ldo_aux1_reg>; + vio-supply = <&ab8500_ldo_aux8_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&proximity_default>; + + sharp,proximity-far-hysteresis = <0x40>; + sharp,proximity-close-hysteresis = <0x0f>; + }; + }; + i2c@80128000 { status = "okay"; @@ -357,6 +403,16 @@ }; }; + i2c-gpio-1 { + i2c_gpio_1_default: i2c_gpio_1 { + golden_cfg1 { + pins = "GPIO151", /* COMP_SCL */ + "GPIO152"; /* COMP_SDA */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + sdi0 { sd_level_translator_default: sd_level_translator_default { golden_cfg1 { @@ -375,6 +431,15 @@ }; }; + proximity { + proximity_default: proximity_default { + golden_cfg1 { + pins = "GPIO146_D13"; /* PS_INT */ + ste,config = <&gpio_in_nopull>; + }; + }; + }; + imu { imu_default: imu_default { golden_cfg1 { diff --git a/src/arm/ste-ux500-samsung-skomer.dts b/src/arm/ste-ux500-samsung-skomer.dts index 292ed5286652..8edef161613a 100644 --- a/src/arm/ste-ux500-samsung-skomer.dts +++ b/src/arm/ste-ux500-samsung-skomer.dts @@ -140,7 +140,12 @@ pinctrl-0 = <&i2c_gpio_1_default>; #address-cells = <1>; #size-cells = <0>; - /* TODO: this should be used by the ALPS HSCDTD008A compass sensor */ + magnetometer@c { + compatible = "alps,hscdtd008a"; + reg = <0x0c>; + avdd-supply = <&ab8500_ldo_aux1_reg>; + dvdd-supply = <&ab8500_ldo_aux8_reg>; + }; }; soc { @@ -362,7 +367,28 @@ pinctrl-0 = <&i2c3_c_2_default>; pinctrl-1 = <&i2c3_c_2_sleep>; - /* TODO: this should be used by the Cypress TMA140 touchscreen */ + /* Cypress CY8CTMA140 touchscreen */ + touchscreen@20 { + compatible = "cypress,cy8ctma140"; + clock-frequency = <400000>; + reg = <0x20>; + + touchscreen-size-x = <480>; + touchscreen-size-y = <800>; + touchscreen-max-pressure = <255>; + + /* GPIO218 for IRQ */ + interrupt-parent = <&gpio6>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + + /* VDD is "digital supply" nominally 1.71-3.6V */ + vdd-supply = <&ab8500_ldo_aux2_reg>; + /* VCPIN is "analog supply", 2.7-3.6 V */ + vcpin-supply = <&ab8500_ldo_aux2_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&tma140_skomer_default>; + }; }; mcde@a0350000 { @@ -557,6 +583,15 @@ }; }; }; + /* Interrupt line for the Cypress TMA140 touchscreen */ + touchscreen { + tma140_skomer_default: tma140_skomer { + skomer_cfg1 { + pins = "GPIO218_AH11"; + ste,config = <&gpio_in_nopull>; + }; + }; + }; }; &ab8505_gpio { diff --git a/src/arm/stih407-family.dtsi b/src/arm/stih407-family.dtsi index 7c36c37260a4..23a1746f3baa 100644 --- a/src/arm/stih407-family.dtsi +++ b/src/arm/stih407-family.dtsi @@ -767,20 +767,6 @@ <&clk_s_c0_flexgen CLK_ETH_PHY>; }; - rng10: rng@8a89000 { - compatible = "st,rng"; - reg = <0x08a89000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - - rng11: rng@8a8a000 { - compatible = "st,rng"; - reg = <0x08a8a000 0x1000>; - clocks = <&clk_sysin>; - status = "okay"; - }; - mailbox0: mailbox@8f00000 { compatible = "st,stih407-mailbox"; reg = <0x8f00000 0x1000>; diff --git a/src/arm/stih418.dtsi b/src/arm/stih418.dtsi index 83411322bd92..a05e2278b448 100644 --- a/src/arm/stih418.dtsi +++ b/src/arm/stih418.dtsi @@ -50,7 +50,7 @@ ohci0: usb@9a03c00 { compatible = "st,st-ohci-300x"; reg = <0x9a03c00 0x100>; - interrupts = ; + interrupts = ; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, <&softreset STIH407_USB2_PORT0_SOFTRESET>; @@ -62,7 +62,7 @@ ehci0: usb@9a03e00 { compatible = "st,st-ehci-300x"; reg = <0x9a03e00 0x100>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; @@ -76,7 +76,7 @@ ohci1: usb@9a83c00 { compatible = "st,st-ohci-300x"; reg = <0x9a83c00 0x100>; - interrupts = ; + interrupts = ; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, <&softreset STIH407_USB2_PORT1_SOFTRESET>; @@ -88,7 +88,7 @@ ehci1: usb@9a83e00 { compatible = "st,st-ehci-300x"; reg = <0x9a83e00 0x100>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; diff --git a/src/arm/stm32f429.dtsi b/src/arm/stm32f429.dtsi index d7770699feb5..393f43c85a3c 100644 --- a/src/arm/stm32f429.dtsi +++ b/src/arm/stm32f429.dtsi @@ -414,14 +414,14 @@ dac1: dac@1 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <1>; status = "disabled"; }; dac2: dac@2 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <2>; status = "disabled"; }; diff --git a/src/arm/stm32h743.dtsi b/src/arm/stm32h743.dtsi index 05eb02e6d083..9b7fc68380e9 100644 --- a/src/arm/stm32h743.dtsi +++ b/src/arm/stm32h743.dtsi @@ -180,14 +180,14 @@ dac1: dac@1 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <1>; status = "disabled"; }; dac2: dac@2 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <2>; status = "disabled"; }; diff --git a/src/arm/stm32mp15-pinctrl.dtsi b/src/arm/stm32mp15-pinctrl.dtsi index 73c07f0dfad2..7eb858732d6d 100644 --- a/src/arm/stm32mp15-pinctrl.dtsi +++ b/src/arm/stm32mp15-pinctrl.dtsi @@ -6,7 +6,7 @@ #include &pinctrl { - adc1_in6_pins_a: adc1-in6 { + adc1_in6_pins_a: adc1-in6-0 { pins { pinmux = ; }; @@ -21,6 +21,13 @@ }; }; + adc12_ain_pins_b: adc12-ain-1 { + pins { + pinmux = , /* ADC1 in6 */ + ; /* ADC2 in2 */ + }; + }; + adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { pins { pinmux = , /* ADC12 in18 */ @@ -37,7 +44,7 @@ }; }; - cec_pins_sleep_a: cec-sleep-0 { + cec_sleep_pins_a: cec-sleep-0 { pins { pinmux = ; /* HDMI_CEC */ }; @@ -52,19 +59,19 @@ }; }; - cec_pins_sleep_b: cec-sleep-1 { + cec_sleep_pins_b: cec-sleep-1 { pins { pinmux = ; /* HDMI_CEC */ }; }; - dac_ch1_pins_a: dac-ch1 { + dac_ch1_pins_a: dac-ch1-0 { pins { pinmux = ; }; }; - dac_ch2_pins_a: dac-ch2 { + dac_ch2_pins_a: dac-ch2-0 { pins { pinmux = ; }; @@ -142,7 +149,7 @@ }; }; - ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 { + ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ , /* ETH_RGMII_GTX_CLK */ @@ -162,6 +169,108 @@ }; }; + ethernet0_rgmii_pins_b: rgmii-1 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDC */ + , /* ETH_MDIO */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + + ethernet0_rgmii_pins_c: rgmii-2 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; + ethernet0_rmii_pins_a: rmii-0 { pins1 { pinmux = , /* ETH1_RMII_TXD0 */ @@ -182,7 +291,7 @@ }; }; - ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { + ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { pins1 { pinmux = , /* ETH1_RMII_TXD0 */ , /* ETH1_RMII_TXD1 */ @@ -250,14 +359,14 @@ }; }; - i2c1_pins_sleep_a: i2c1-1 { + i2c1_sleep_pins_a: i2c1-sleep-0 { pins { pinmux = , /* I2C1_SCL */ ; /* I2C1_SDA */ }; }; - i2c1_pins_b: i2c1-2 { + i2c1_pins_b: i2c1-1 { pins { pinmux = , /* I2C1_SCL */ ; /* I2C1_SDA */ @@ -267,7 +376,7 @@ }; }; - i2c1_pins_sleep_b: i2c1-3 { + i2c1_sleep_pins_b: i2c1-sleep-1 { pins { pinmux = , /* I2C1_SCL */ ; /* I2C1_SDA */ @@ -284,14 +393,14 @@ }; }; - i2c2_pins_sleep_a: i2c2-1 { + i2c2_sleep_pins_a: i2c2-sleep-0 { pins { pinmux = , /* I2C2_SCL */ ; /* I2C2_SDA */ }; }; - i2c2_pins_b1: i2c2-2 { + i2c2_pins_b1: i2c2-1 { pins { pinmux = ; /* I2C2_SDA */ bias-disable; @@ -300,12 +409,29 @@ }; }; - i2c2_pins_sleep_b1: i2c2-3 { + i2c2_sleep_pins_b1: i2c2-sleep-1 { pins { pinmux = ; /* I2C2_SDA */ }; }; + i2c2_pins_c: i2c2-2 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_pins_sleep_c: i2c2-sleep-2 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + i2c5_pins_a: i2c5-0 { pins { pinmux = , /* I2C5_SCL */ @@ -316,7 +442,7 @@ }; }; - i2c5_pins_sleep_a: i2c5-1 { + i2c5_sleep_pins_a: i2c5-sleep-0 { pins { pinmux = , /* I2C5_SCL */ ; /* I2C5_SDA */ @@ -324,6 +450,23 @@ }; }; + i2c5_pins_b: i2c5-1 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_b: i2c5-sleep-1 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + }; + }; + i2s2_pins_a: i2s2-0 { pins { pinmux = , /* I2S2_SDO */ @@ -335,7 +478,7 @@ }; }; - i2s2_pins_sleep_a: i2s2-1 { + i2s2_sleep_pins_a: i2s2-sleep-0 { pins { pinmux = , /* I2S2_SDO */ , /* I2S2_WS */ @@ -343,7 +486,7 @@ }; }; - ltdc_pins_a: ltdc-a-0 { + ltdc_pins_a: ltdc-0 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ @@ -379,7 +522,7 @@ }; }; - ltdc_pins_sleep_a: ltdc-a-1 { + ltdc_sleep_pins_a: ltdc-sleep-0 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ @@ -412,7 +555,7 @@ }; }; - ltdc_pins_b: ltdc-b-0 { + ltdc_pins_b: ltdc-1 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ @@ -448,7 +591,7 @@ }; }; - ltdc_pins_sleep_b: ltdc-b-1 { + ltdc_sleep_pins_b: ltdc-sleep-1 { pins { pinmux = , /* LCD_CLK */ , /* LCD_HSYNC */ @@ -481,6 +624,142 @@ }; }; + ltdc_pins_c: ltdc-2 { + pins1 { + pinmux = , /* LTDC_R6 */ + , /* LTDC_B7 */ + , /* LTDC_R5 */ + , /* LTDC_G7 */ + , /* LTDC_B2 */ + , /* LTDC_B3 */ + , /* LTDC_G3 */ + , /* LTDC_B4 */ + , /* LTDC_DE */ + , /* LTDC_R7 */ + , /* LTDC_G5 */ + , /* LTDC_R2 */ + , /* LTDC_R3 */ + , /* LTDC_R4 */ + , /* LTDC_G2 */ + , /* LTDC_G4 */ + , /* LTDC_G6 */ + , /* LTDC_B5 */ + , /* LTDC_B6 */ + , /* LTDC_VSYNC */ + ; /* LTDC_HSYNC */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* LTDC_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_sleep_pins_c: ltdc-sleep-2 { + pins1 { + pinmux = , /* LTDC_R6 */ + , /* LTDC_B7 */ + , /* LTDC_R5 */ + , /* LTDC_G7 */ + , /* LTDC_B2 */ + , /* LTDC_B3 */ + , /* LTDC_G3 */ + , /* LTDC_B4 */ + , /* LTDC_DE */ + , /* LTDC_R7 */ + , /* LTDC_G5 */ + , /* LTDC_R2 */ + , /* LTDC_R3 */ + , /* LTDC_R4 */ + , /* LTDC_G2 */ + , /* LTDC_G4 */ + , /* LTDC_G6 */ + , /* LTDC_B5 */ + , /* LTDC_B6 */ + , /* LTDC_VSYNC */ + , /* LTDC_HSYNC */ + ; /* LTDC_CLK */ + }; + }; + + ltdc_pins_d: ltdc-3 { + pins1 { + pinmux = ; /* LCD_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + ltdc_sleep_pins_d: ltdc-sleep-3 { + pins { + pinmux = , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ @@ -501,6 +780,46 @@ }; }; + m_can1_pins_b: m-can1-1 { + pins1 { + pinmux = ; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_b: m_can1-sleep-1 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + + m_can2_pins_a: m-can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-disable; + }; + }; + + m_can2_sleep_pins_a: m_can2-sleep-0 { + pins { + pinmux = , /* CAN2_TX */ + ; /* CAN2_RX */ + }; + }; + pwm1_pins_a: pwm1-0 { pins { pinmux = , /* TIM1_CH1 */ @@ -550,6 +869,21 @@ }; }; + pwm3_pins_b: pwm3-1 { + pins { + pinmux = ; /* TIM3_CH2 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_b: pwm3-sleep-1 { + pins { + pinmux = ; /* TIM3_CH2 */ + }; + }; + pwm4_pins_a: pwm4-0 { pins { pinmux = , /* TIM4_CH3 */ @@ -597,6 +931,25 @@ }; }; + pwm5_pins_b: pwm5-1 { + pins { + pinmux = , /* TIM5_CH2 */ + , /* TIM5_CH3 */ + ; /* TIM5_CH4 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm5_sleep_pins_b: pwm5-sleep-1 { + pins { + pinmux = , /* TIM5_CH2 */ + , /* TIM5_CH3 */ + ; /* TIM5_CH4 */ + }; + }; + pwm8_pins_a: pwm8-0 { pins { pinmux = ; /* TIM8_CH4 */ @@ -710,7 +1063,7 @@ }; }; - sai2a_sleep_pins_a: sai2a-1 { + sai2a_sleep_pins_a: sai2a-sleep-0 { pins { pinmux = , /* SAI2_SCK_A */ , /* SAI2_SD_A */ @@ -720,7 +1073,7 @@ }; - sai2a_pins_b: sai2a-2 { + sai2a_pins_b: sai2a-1 { pins1 { pinmux = , /* SAI2_SD_A */ , /* SAI2_FS_A */ @@ -731,7 +1084,7 @@ }; }; - sai2a_sleep_pins_b: sai2a-sleep-3 { + sai2a_sleep_pins_b: sai2a-sleep-1 { pins { pinmux = , /* SAI2_SD_A */ , /* SAI2_FS_A */ @@ -739,6 +1092,25 @@ }; }; + sai2a_pins_c: sai2a-4 { + pins { + pinmux = , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ + ; /* SAI2_FS_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + sai2a_sleep_pins_c: sai2a-5 { + pins { + pinmux = , /* SAI2_SCK_A */ + , /* SAI2_SD_A */ + ; /* SAI2_FS_A */ + }; + }; + sai2b_pins_a: sai2b-0 { pins1 { pinmux = , /* SAI2_SCK_B */ @@ -754,7 +1126,7 @@ }; }; - sai2b_sleep_pins_a: sai2b-1 { + sai2b_sleep_pins_a: sai2b-sleep-0 { pins { pinmux = , /* SAI2_SD_B */ , /* SAI2_SCK_B */ @@ -763,14 +1135,27 @@ }; }; - sai2b_pins_b: sai2b-2 { + sai2b_pins_b: sai2b-1 { pins { pinmux = ; /* SAI2_SD_B */ bias-disable; }; }; - sai2b_sleep_pins_b: sai2b-3 { + sai2b_sleep_pins_b: sai2b-sleep-1 { + pins { + pinmux = ; /* SAI2_SD_B */ + }; + }; + + sai2b_pins_c: sai2a-4 { + pins1 { + pinmux = ; /* SAI2_SD_B */ + bias-disable; + }; + }; + + sai2b_sleep_pins_c: sai2a-sleep-5 { pins { pinmux = ; /* SAI2_SD_B */ }; @@ -785,7 +1170,7 @@ }; }; - sai4a_sleep_pins_a: sai4a-1 { + sai4a_sleep_pins_a: sai4a-sleep-0 { pins { pinmux = ; /* SAI4_SD_A */ }; @@ -869,6 +1254,30 @@ }; }; + sdmmc1_dir_pins_b: sdmmc1-dir-1 { + pins1 { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + ; /* SDMMC1_CDIR */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2{ + pinmux = ; /* SDMMC1_CKIN */ + bias-pull-up; + }; + }; + + sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { + pins { + pinmux = , /* SDMMC1_D0DIR */ + , /* SDMMC1_D123DIR */ + , /* SDMMC1_CDIR */ + ; /* SDMMC1_CKIN */ + }; + }; + sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins1 { pinmux = , /* SDMMC2_D0 */ @@ -987,6 +1396,48 @@ }; }; + sdmmc2_d47_pins_b: sdmmc2-d47-1 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + sdmmc2_d47_pins_c: sdmmc2-d47-2 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = , /* SDMMC3_D0 */ @@ -1041,6 +1492,60 @@ }; }; + sdmmc3_b4_pins_b: sdmmc3-b4-1 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + pins3 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { + pins { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ + }; + }; + spdifrx_pins_a: spdifrx-0 { pins { pinmux = ; /* SPDIF_IN1 */ @@ -1048,12 +1553,75 @@ }; }; - spdifrx_sleep_pins_a: spdifrx-1 { + spdifrx_sleep_pins_a: spdifrx-sleep-0 { pins { pinmux = ; /* SPDIF_IN1 */ }; }; + spi2_pins_a: spi2-0 { + pins1 { + pinmux = , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI1_MISO */ + bias-disable; + }; + }; + + usart2_pins_a: usart2-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; + + usart2_pins_b: usart2-1 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_sleep_pins_b: usart2-sleep-1 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; + usart3_pins_a: usart3-0 { pins1 { pinmux = ; /* USART3_TX */ @@ -1093,6 +1661,19 @@ }; }; + uart4_pins_c: uart4-2 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + uart7_pins_a: uart7-0 { pins1 { pinmux = ; /* UART4_TX */ @@ -1108,6 +1689,19 @@ }; }; + uart7_pins_b: uart7-1 { + pins1 { + pinmux = ; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART7_RX */ + bias-disable; + }; + }; + uart8_pins_a: uart8-0 { pins1 { pinmux = ; /* UART8_TX */ @@ -1145,7 +1739,7 @@ }; }; - i2c2_pins_sleep_b2: i2c2-1 { + i2c2_sleep_pins_b2: i2c2-sleep-0 { pins { pinmux = ; /* I2C2_SCL */ }; @@ -1161,7 +1755,7 @@ }; }; - i2c4_pins_sleep_a: i2c4-1 { + i2c4_sleep_pins_a: i2c4-sleep-0 { pins { pinmux = , /* I2C4_SCL */ ; /* I2C4_SDA */ @@ -1182,4 +1776,18 @@ bias-disable; }; }; + + spi4_pins_a: spi4-0 { + pins { + pinmux = , /* SPI4_SCK */ + ; /* SPI4_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SPI4_MISO */ + bias-disable; + }; + }; }; diff --git a/src/arm/stm32mp151.dtsi b/src/arm/stm32mp151.dtsi index 3ea05ba48215..36f38a95b4de 100644 --- a/src/arm/stm32mp151.dtsi +++ b/src/arm/stm32mp151.dtsi @@ -24,10 +24,8 @@ }; psci { - compatible = "arm,psci"; + compatible = "arm,psci-1.0"; method = "smc"; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; }; intc: interrupt-controller@a0021000 { @@ -475,7 +473,7 @@ }; i2c1: i2c@40012000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40012000 0x400>; interrupt-names = "event", "error"; interrupts = , @@ -484,12 +482,13 @@ resets = <&rcc I2C1_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x1>; wakeup-source; status = "disabled"; }; i2c2: i2c@40013000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40013000 0x400>; interrupt-names = "event", "error"; interrupts = , @@ -498,12 +497,13 @@ resets = <&rcc I2C2_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x2>; wakeup-source; status = "disabled"; }; i2c3: i2c@40014000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40014000 0x400>; interrupt-names = "event", "error"; interrupts = , @@ -512,12 +512,13 @@ resets = <&rcc I2C3_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x4>; wakeup-source; status = "disabled"; }; i2c5: i2c@40015000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x40015000 0x400>; interrupt-names = "event", "error"; interrupts = , @@ -526,6 +527,7 @@ resets = <&rcc I2C5_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x10>; wakeup-source; status = "disabled"; }; @@ -550,14 +552,14 @@ dac1: dac@1 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <1>; status = "disabled"; }; dac2: dac@2 { compatible = "st,stm32-dac"; - #io-channels-cells = <1>; + #io-channel-cells = <1>; reg = <2>; status = "disabled"; }; @@ -1124,6 +1126,11 @@ }; }; + pwr_mcu: pwr_mcu@50001014 { + compatible = "syscon"; + reg = <0x50001014 0x4>; + }; + exti: interrupt-controller@5000d000 { compatible = "st,stm32mp1-exti", "syscon"; interrupt-controller; @@ -1423,6 +1430,11 @@ clock-names = "lcd"; resets = <&rcc LTDC_R>; status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + }; }; iwdg2: watchdog@5a002000 { @@ -1476,7 +1488,7 @@ }; i2c4: i2c@5c002000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x5c002000 0x400>; interrupt-names = "event", "error"; interrupts = , @@ -1485,6 +1497,7 @@ resets = <&rcc I2C4_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x8>; wakeup-source; status = "disabled"; }; @@ -1512,7 +1525,7 @@ }; i2c6: i2c@5c009000 { - compatible = "st,stm32f7-i2c"; + compatible = "st,stm32mp15-i2c"; reg = <0x5c009000 0x400>; interrupt-names = "event", "error"; interrupts = , @@ -1521,6 +1534,7 @@ resets = <&rcc I2C6_R>; #address-cells = <1>; #size-cells = <0>; + st,syscfg-fmp = <&syscfg 0x4 0x20>; wakeup-source; status = "disabled"; }; @@ -1700,6 +1714,7 @@ resets = <&rcc MCU_R>; st,syscfg-holdboot = <&rcc 0x10C 0x1>; st,syscfg-tz = <&rcc 0x000 0x1>; + st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; status = "disabled"; }; }; diff --git a/src/arm/stm32mp157.dtsi b/src/arm/stm32mp157.dtsi index 3f0a4a91cce6..54e73ccea446 100644 --- a/src/arm/stm32mp157.dtsi +++ b/src/arm/stm32mp157.dtsi @@ -15,7 +15,6 @@ clocks = <&rcc GPU>, <&rcc GPU_K>; clock-names = "bus" ,"core"; resets = <&rcc GPU_R>; - status = "disabled"; }; dsi: dsi@5a000000 { @@ -25,7 +24,14 @@ clock-names = "pclk", "ref", "px_clk"; resets = <&rcc DSI_R>; reset-names = "apb"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; }; }; }; diff --git a/src/arm/stm32mp157a-avenger96.dts b/src/arm/stm32mp157a-avenger96.dts index 425175f7d83c..8a6eaca994d1 100644 --- a/src/arm/stm32mp157a-avenger96.dts +++ b/src/arm/stm32mp157a-avenger96.dts @@ -2,318 +2,10 @@ /* * Copyright (C) Linaro Ltd 2019 - All Rights Reserved * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut */ /dts-v1/; -#include "stm32mp157.dtsi" -#include "stm32mp15-pinctrl.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" -#include -#include - -/ { - model = "Arrow Electronics STM32MP157A Avenger96 board"; - compatible = "arrow,stm32mp157a-avenger96", "st,stm32mp157"; - - aliases { - ethernet0 = ðernet0; - mmc0 = &sdmmc1; - serial0 = &uart4; - serial1 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@c0000000 { - device_type = "memory"; - reg = <0xc0000000 0x40000000>; - }; - - led { - compatible = "gpio-leds"; - led1 { - label = "green:user1"; - gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led2 { - label = "green:user2"; - gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "green:user3"; - gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc1"; - default-state = "off"; - }; - - led4 { - label = "green:user3"; - gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "none"; - default-state = "off"; - panic-indicator; - }; - - led5 { - label = "yellow:wifi"; - gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "phy0tx"; - default-state = "off"; - }; - - led6 { - label = "blue:bt"; - gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "bluetooth-power"; - default-state = "off"; - }; - }; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; - max-speed = <1000>; - phy-handle = <&phy0>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@7 { - reg = <7>; - }; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_b>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins_b1 &i2c2_pins_b2>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /delete-property/dmas; - /delete-property/dma-names; - - pmic: stpmic@33 { - compatible = "st,stpmic1"; - reg = <0x33>; - interrupts-extended = <&exti 55 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - status = "okay"; - - regulators { - compatible = "st,stpmic1-regulators"; - - ldo1-supply = <&v3v3>; - ldo2-supply = <&v3v3>; - ldo3-supply = <&vdd_ddr>; - ldo5-supply = <&v3v3>; - ldo6-supply = <&v3v3>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; - - vddcore: buck1 { - regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd_ddr: buck2 { - regulator-name = "vdd_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - vdd: buck3 { - regulator-name = "vdd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-initial-mode = <0>; - regulator-over-current-protection; - }; - - v3v3: buck4 { - regulator-name = "v3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-over-current-protection; - regulator-initial-mode = <0>; - }; - - vdda: ldo1 { - regulator-name = "vdda"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - v2v8: ldo2 { - regulator-name = "v2v8"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - vtt_ddr: ldo3 { - regulator-name = "vtt_ddr"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name = "vdd_usb"; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - vdd_sd: ldo5 { - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - interrupts = ; - interrupt-parent = <&pmic>; - regulator-boot-on; - }; - - v1v8: ldo6 { - regulator-name = "v1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - interrupts = ; - interrupt-parent = <&pmic>; - regulator-enable-ramp-delay = <300000>; - }; - - vref_ddr: vref_ddr { - regulator-name = "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name = "bst_out"; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - vbus_otg: pwr_sw1 { - regulator-name = "vbus_otg"; - interrupts = ; - interrupt-parent = <&pmic>; - }; - - vbus_sw: pwr_sw2 { - regulator-name = "vbus_sw"; - interrupts = ; - interrupt-parent = <&pmic>; - regulator-active-discharge = <1>; - }; - }; - - onkey { - compatible = "st,stpmic1-onkey"; - interrupts = , ; - interrupt-names = "onkey-falling", "onkey-rising"; - status = "okay"; - }; - - watchdog { - compatible = "st,stpmic1-wdt"; - status = "disabled"; - }; - }; -}; - -&iwdg2 { - timeout-sec = <32>; - status = "okay"; -}; - -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - -&rng1 { - status = "okay"; -}; - -&rtc { - status = "okay"; -}; - -&sdmmc1 { - pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; - pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; - cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - disable-wp; - st,sig-dir; - st,neg-edge; - st,use-ckin; - bus-width = <4>; - vmmc-supply = <&vdd_sd>; - status = "okay"; -}; - -&uart4 { - /* On Low speed expansion header */ - label = "LS-UART1"; - pinctrl-names = "default"; - pinctrl-0 = <&uart4_pins_b>; - status = "okay"; -}; - -&uart7 { - /* On Low speed expansion header */ - label = "LS-UART0"; - pinctrl-names = "default"; - pinctrl-0 = <&uart7_pins_a>; - status = "okay"; -}; +/* This DT is here only for backward compatibility */ +#include "stm32mp157a-dhcor-avenger96.dts" diff --git a/src/arm/stm32mp157a-dhcor-avenger96.dts b/src/arm/stm32mp157a-dhcor-avenger96.dts new file mode 100644 index 000000000000..2e3c9fbb4eb3 --- /dev/null +++ b/src/arm/stm32mp157a-dhcor-avenger96.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + * + * DHCOR STM32MP1 variant: + * DHCR-STM32MP157A-C065-R102-V18-SPI-C-01LG + * DHCOR PCB number: 586-100 or newer + * Avenger96 PCB number: 588-200 or newer + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-avenger96.dtsi" + +/ { + model = "Arrow Electronics STM32MP157A Avenger96 board"; + compatible = "arrow,stm32mp157a-avenger96", "dh,stm32mp157a-dhcor-som", + "st,stm32mp157"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_b>; + pinctrl-1 = <&m_can1_sleep_pins_b>; + status = "disabled"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "disabled"; +}; diff --git a/src/arm/stm32mp157a-iot-box.dts b/src/arm/stm32mp157a-iot-box.dts new file mode 100644 index 000000000000..70f394b4d3c0 --- /dev/null +++ b/src/arm/stm32mp157a-iot-box.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "stm32mp157a-stinger96.dtsi" + +/ { + model = "Shiratech STM32MP157A IoT Box"; + compatible = "shiratech,stm32mp157a-iot-box", "st,stm32mp157"; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&i2c2 { + ccs811@5b { + compatible = "ams,ccs811"; + reg = <0x5b>; + wakeup-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; + }; +}; + +/* WiFi */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <1>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* Bluetooth */ +&uart4 { + /* Note: HW flow control is broken, hence using custom CTS/RTS gpios */ + /delete-property/st,hw-flow-ctrl; + cts-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + bluetooth { + shutdown-gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; + compatible = "brcm,bcm43438-bt"; + max-speed = <115200>; + }; +}; diff --git a/src/arm/stm32mp157a-stinger96.dts b/src/arm/stm32mp157a-stinger96.dts new file mode 100644 index 000000000000..249a53877512 --- /dev/null +++ b/src/arm/stm32mp157a-stinger96.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; +#include "stm32mp157a-stinger96.dtsi" + +/ { + model = "Shiratech STM32MP157A Stinger96 board"; + compatible = "shiratech,stm32mp157a-stinger96", "st,stm32mp157"; +}; diff --git a/src/arm/stm32mp157a-stinger96.dtsi b/src/arm/stm32mp157a-stinger96.dtsi new file mode 100644 index 000000000000..58275bcf9e26 --- /dev/null +++ b/src/arm/stm32mp157a-stinger96.dtsi @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Manivannan Sadhasivam + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include + +/ { + aliases { + mmc0 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + serial2 = &usart2; + spi0 = &spi4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x10000000>; + }; + + led { + compatible = "gpio-leds"; + + led1 { + label = "green:user1"; + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user2"; + gpios = <&gpioh 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user3"; + gpios = <&gpioh 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user4"; + gpios = <&gpiof 12 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +/* Only headless mode is supported */ +&gpu { + status = "disabled"; +}; + +/* LS-I2C0 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <1000>; + i2c-scl-falling-time-ns = <300>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v2v9: ldo2 { + regulator-name = "v2v9"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + broken-cd; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +/* LS-SPI0 */ +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins_a>; + cs-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* BG96 */ +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_b>; + pinctrl-1 = <&usart2_sleep_pins_b>; + st,hw-flow-ctrl; + status = "okay"; +}; + +/* LS-UART0 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_c>; + st,hw-flow-ctrl; + status = "okay"; +}; + +/* Debug console */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_b>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; diff --git a/src/arm/stm32mp157c-dhcom-pdk2.dts b/src/arm/stm32mp157c-dhcom-pdk2.dts index af99e132e1b1..197aa98d49e2 100644 --- a/src/arm/stm32mp157c-dhcom-pdk2.dts +++ b/src/arm/stm32mp157c-dhcom-pdk2.dts @@ -1,160 +1,23 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* - * Copyright (C) 2019 Marek Vasut + * Copyright (C) 2019-2020 Marek Vasut + * + * DHCOM STM32MP1 variant: + * DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2 + * DHCOR PCB number: 587-200 or newer + * PDK2 PCB number: 516-400 or newer */ +/dts-v1/; -#include "stm32mp157c-dhcom-som.dtsi" -#include +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-pdk2.dtsi" / { - model = "STMicroelectronics STM32MP157C DHCOM Premium Developer Kit (2)"; - compatible = "dh,stm32mp157c-dhcom-pdk2", "st,stm32mp157"; - - aliases { - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart8; - ethernet0 = ðernet0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clk_ext_audio_codec: clock-codec { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - - display_bl: display-bl { - compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; - default-brightness-level = <8>; - enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - ethernet_vio: vioregulator { - compatible = "regulator-fixed"; - regulator-name = "vio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; - regulator-always-on; - regulator-boot-on; - }; - - panel { - compatible = "edt,etm0700g0edh6"; - backlight = <&display_bl>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - sound { - compatible = "audio-graph-card"; - routing = - "MIC_IN", "Capture", - "Capture", "Mic Bias", - "Playback", "HP_OUT"; - dais = <&sai2a_port &sai2b_port>; - status = "okay"; - }; -}; - -&cec { - pinctrl-names = "default"; - pinctrl-0 = <&cec_pins_a>; - status = "okay"; -}; - -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_pins_sleep_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rmii"; - max-speed = <100>; - phy-handle = <&phy0>; - st,eth-ref-clk-sel; - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins_a>; - i2c-scl-rising-time-ns = <185>; - i2c-scl-falling-time-ns = <20>; - status = "okay"; - /* spare dmas for other usage */ - /delete-property/dmas; - /delete-property/dma-names; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - clocks = <&clk_ext_audio_codec>; - VDDA-supply = <&v3v3>; - VDDIO-supply = <&vdd>; - - sgtl5000_port: port { - #address-cells = <1>; - #size-cells = <0>; - - sgtl5000_tx_endpoint: endpoint@0 { - reg = <0>; - remote-endpoint = <&sai2a_endpoint>; - frame-master; - bitclock-master; - }; - - sgtl5000_rx_endpoint: endpoint@1 { - reg = <1>; - remote-endpoint = <&sai2b_endpoint>; - frame-master; - bitclock-master; - }; - }; - - }; - - polytouch@38 { - compatible = "edt,edt-ft5x06"; - reg = <0x38>; - interrupt-parent = <&gpiog>; - interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - linux,wakeup; - }; -}; - -<dc { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <<dc_pins_b>; - pinctrl-1 = <<dc_pins_sleep_b>; - status = "okay"; - - port { - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; + model = "DH Electronics STM32MP157C DHCOM Premium Developer Kit (2)"; + compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som", + "st,stm32mp157"; }; &m_can1 { @@ -163,103 +26,3 @@ pinctrl-1 = <&m_can1_sleep_pins_a>; status = "okay"; }; - -&sai2 { - clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; - clock-names = "pclk", "x8k", "x11k"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>; - pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>; - status = "okay"; - - sai2a: audio-controller@4400b004 { - #clock-cells = <0>; - dma-names = "tx"; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; - status = "okay"; - - sai2a_port: port { - sai2a_endpoint: endpoint { - remote-endpoint = <&sgtl5000_tx_endpoint>; - format = "i2s"; - mclk-fs = <512>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; - }; - - sai2b: audio-controller@4400b024 { - dma-names = "rx"; - st,sync = <&sai2a 2>; - clocks = <&rcc SAI2_K>, <&sai2a>; - clock-names = "sai_ck", "MCLK"; - status = "okay"; - - sai2b_port: port { - sai2b_endpoint: endpoint { - remote-endpoint = <&sgtl5000_rx_endpoint>; - format = "i2s"; - mclk-fs = <512>; - dai-tdm-slot-num = <2>; - dai-tdm-slot-width = <16>; - }; - }; - }; -}; - -&timers2 { - /* spare dmas for other usage (un-delete to enable pwm capture) */ - /delete-property/dmas; - /delete-property/dma-names; - status = "okay"; - pwm2: pwm { - pinctrl-0 = <&pwm2_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - timer@1 { - status = "okay"; - }; -}; - -&usart3 { - pinctrl-names = "default"; - pinctrl-0 = <&usart3_pins_a>; - status = "okay"; -}; - -&uart8 { - pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a>; - status = "okay"; -}; - -&usbh_ehci { - phys = <&usbphyc_port0>; - status = "okay"; -}; - -&usbotg_hs { - dr_mode = "peripheral"; - phys = <&usbphyc_port1 0>; - phy-names = "usb2-phy"; - status = "okay"; -}; - -&usbphyc { - status = "okay"; -}; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; -}; diff --git a/src/arm/stm32mp157c-dk2.dts b/src/arm/stm32mp157c-dk2.dts index 7985b80967ca..9a8a26710ac1 100644 --- a/src/arm/stm32mp157c-dk2.dts +++ b/src/arm/stm32mp157c-dk2.dts @@ -27,15 +27,10 @@ }; &dsi { - #address-cells = <1>; - #size-cells = <0>; status = "okay"; phy-dsi-supply = <®18>; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; dsi_in: endpoint { @@ -83,9 +78,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - ltdc_ep1_out: endpoint@1 { reg = <1>; remote-endpoint = <&dsi_in>; diff --git a/src/arm/stm32mp157c-ed1.dts b/src/arm/stm32mp157c-ed1.dts index 9d2592db630c..32ccd50b4144 100644 --- a/src/arm/stm32mp157c-ed1.dts +++ b/src/arm/stm32mp157c-ed1.dts @@ -126,13 +126,12 @@ &gpu { contiguous-area = <&gpu_reserved>; - status = "okay"; }; &i2c4 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_pins_sleep_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; clock-frequency = <400000>; @@ -320,6 +319,10 @@ bus-width = <4>; vmmc-supply = <&vdd_sd>; vqmmc-supply = <&sd_switch>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; status = "okay"; }; diff --git a/src/arm/stm32mp157c-ev1.dts b/src/arm/stm32mp157c-ev1.dts index 8a4c7ff31a92..b19056557ef0 100644 --- a/src/arm/stm32mp157c-ev1.dts +++ b/src/arm/stm32mp157c-ev1.dts @@ -98,15 +98,10 @@ }; &dsi { - #address-cells = <1>; - #size-cells = <0>; phy-dsi-supply = <®18>; status = "okay"; ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { reg = <0>; dsi_in: endpoint { @@ -141,7 +136,7 @@ ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii-id"; max-speed = <1000>; @@ -176,7 +171,7 @@ &i2c2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_pins_a>; - pinctrl-1 = <&i2c2_pins_sleep_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; @@ -230,7 +225,7 @@ &i2c5 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c5_pins_a>; - pinctrl-1 = <&i2c5_pins_sleep_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; @@ -240,9 +235,6 @@ status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - ltdc_ep0_out: endpoint@0 { reg = <0>; remote-endpoint = <&dsi_in>; diff --git a/src/arm/stm32mp157c-lxa-mc1.dts b/src/arm/stm32mp157c-lxa-mc1.dts new file mode 100644 index 000000000000..5700e6b700d3 --- /dev/null +++ b/src/arm/stm32mp157c-lxa-mc1.dts @@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2020 Ahmad Fatoum, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xx-osd32.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" + +#include +#include + +/ { + model = "Linux Automation MC-1 board"; + compatible = "lxa,stm32mp157c-mc1", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&backlight_pwm 1 100000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 31 63 95 127 159 191 223 255>; + default-brightness-level = <7>; + power-supply = <®_5v2>; /* 3V3_BACKLIGHT */ + }; + + chosen { + stdout-path = &uart4; + }; + + led-act { + compatible = "gpio-leds"; + + led-green { + label = "mc1:green:act"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + led-rgb { + compatible = "pwm-leds"; + + led-red { + label = "mc1:red:rgb"; + pwms = <&leds_pwm 1 1000000 0>; + max-brightness = <255>; + active-low; + }; + + led-green { + label = "mc1:green:rgb"; + pwms = <&leds_pwm 2 1000000 0>; + max-brightness = <255>; + active-low; + }; + + led-blue { + label = "mc1:blue:rgb"; + pwms = <&leds_pwm 3 1000000 0>; + max-brightness = <255>; + active-low; + }; + }; + + panel: panel { + compatible = "edt,etm0700g0edh6", "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + + port { + panel_input: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + }; + + reg_3v3: regulator_3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&v3v3>; + }; + + /* supplied by either debug board or PoE */ + reg_5v2: regulator_5v2 { + compatible = "regulator-fixed"; + regulator-name = "5V2"; + regulator-min-microvolt = <5200000>; + regulator-max-microvolt = <5200000>; + regulator-always-on; + }; +}; + +ðernet0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rgmii_pins_b>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_b>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + status = "okay"; + + mdio0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { /* KSZ9031RN */ + reg = <3>; + reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ + interrupt-parent = <&gpioa>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ + rxc-skew-ps = <1860>; + txc-skew-ps = <1860>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + micrel,force-master; + }; + }; +}; + +&gpioz { + gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", "", + "HWID4", "HWID5"; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_b>; + pinctrl-1 = <&i2c5_sleep_pins_b>; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + interrupt-parent = <&gpiod>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; /* TOUCH_INT# */ + vcc-supply = <®_3v3>; + reg = <0x38>; + reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>; /* TOUCH_RESET# */ + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + wakeup-source; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_c>; + pinctrl-1 = <<dc_sleep_pins_c>; + status = "okay"; + + port { + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; + }; +}; + +&pmic { + regulators { + buck4-supply = <®_5v2>; /* VIN */ + ldo2-supply = <®_5v2>; /* PMIC_LDO25IN */ + ldo5-supply = <®_5v2>; /* PMIC_LDO25IN */ + boost-supply = <®_5v2>; /* PMIC_BSTIN */ + pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */ + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + bus-width = <4>; + cd-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + disable-wp; + no-1-8-v; + st,neg-edge; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&sdmmc1_b4_pins_a { + /* + * board lacks external pull-ups on SDMMC lines. Class 10 SD refuses to + * work, thus enable internal pull-ups. + */ + pins1 { + /delete-property/ bias-disable; + bias-pull-up; + }; + pins2 { + /delete-property/ bias-disable; + bias-pull-up; + }; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + bus-width = <8>; + no-1-8-v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&timers3 { + status = "okay"; + + backlight_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm3_pins_b>; + pinctrl-1 = <&pwm3_sleep_pins_b>; + status = "okay"; + }; +}; + +&timers5 { + status = "okay"; + + leds_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm5_pins_b>; + pinctrl-1 = <&pwm5_sleep_pins_b>; + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; diff --git a/src/arm/stm32mp15xx-dhcom-pdk2.dtsi b/src/arm/stm32mp15xx-dhcom-pdk2.dtsi new file mode 100644 index 000000000000..7c4bd615b311 --- /dev/null +++ b/src/arm/stm32mp15xx-dhcom-pdk2.dtsi @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019-2020 Marek Vasut + */ + +#include +#include + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + ethernet0 = ðernet0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + display_bl: display-bl { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #size-cells = <0>; + poll-interval = <20>; + + /* + * The EXTi IRQ line 3 is shared with touchscreen and ethernet, + * so mark this as polled GPIO key. + */ + button-0 { + label = "TA1-GPIO-A"; + linux,code = ; + gpios = <&gpiof 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #size-cells = <0>; + + button-1 { + label = "TA2-GPIO-B"; + linux,code = ; + gpios = <&gpiod 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-2 { + label = "TA3-GPIO-C"; + linux,code = ; + gpios = <&gpioi 11 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-3 { + label = "TA4-GPIO-D"; + linux,code = ; + gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + label = "green:led5"; + gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + label = "green:led6"; + gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + label = "green:led7"; + gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + label = "green:led8"; + gpios = <&gpioi 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + panel { + compatible = "edt,etm0700g0edh6"; + backlight = <&display_bl>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + sound { + compatible = "audio-graph-card"; + routing = + "MIC_IN", "Capture", + "Capture", "Mic Bias", + "Playback", "HP_OUT"; + dais = <&sai2a_port &sai2b_port>; + status = "okay"; + }; +}; + +&cec { + pinctrl-names = "default"; + pinctrl-0 = <&cec_pins_a>; + status = "okay"; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + st,eth-ref-clk-sel; + phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&i2c2 { /* Header X22 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&i2c5 { /* Header X21 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + VDDA-supply = <&v3v3>; + VDDIO-supply = <&vdd>; + + sgtl5000_port: port { + #address-cells = <1>; + #size-cells = <0>; + + sgtl5000_tx_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai2a_endpoint>; + frame-master; + bitclock-master; + }; + + sgtl5000_rx_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai2b_endpoint>; + frame-master; + bitclock-master; + }; + }; + + }; + + polytouch@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpiog>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + linux,wakeup; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_b>; + pinctrl-1 = <<dc_sleep_pins_b>; + status = "okay"; + + port { + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_b &sai2b_pins_b>; + pinctrl-1 = <&sai2a_sleep_pins_b &sai2b_sleep_pins_b>; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&sgtl5000_tx_endpoint>; + format = "i2s"; + mclk-fs = <512>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + }; + + sai2b: audio-controller@4400b024 { + dma-names = "rx"; + st,sync = <&sai2a 2>; + clocks = <&rcc SAI2_K>, <&sai2a>; + clock-names = "sai_ck", "MCLK"; + status = "okay"; + + sai2b_port: port { + sai2b_endpoint: endpoint { + remote-endpoint = <&sgtl5000_rx_endpoint>; + format = "i2s"; + mclk-fs = <512>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + }; +}; + +&timers2 { + /* spare dmas for other usage (un-delete to enable pwm capture) */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + pwm2: pwm { + pinctrl-0 = <&pwm2_pins_a>; + pinctrl-names = "default"; + status = "okay"; + }; + timer@1 { + status = "okay"; + }; +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; diff --git a/src/arm/stm32mp157c-dhcom-som.dtsi b/src/arm/stm32mp15xx-dhcom-som.dtsi similarity index 98% rename from src/arm/stm32mp157c-dhcom-som.dtsi rename to src/arm/stm32mp15xx-dhcom-som.dtsi index f81dc3134135..ba905196fb54 100644 --- a/src/arm/stm32mp157c-dhcom-som.dtsi +++ b/src/arm/stm32mp15xx-dhcom-som.dtsi @@ -1,11 +1,8 @@ // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) /* - * Copyright (C) 2019 Marek Vasut + * Copyright (C) 2019-2020 Marek Vasut */ -/dts-v1/; -#include "stm32mp157.dtsi" -#include "stm32mp15xc.dtsi" #include "stm32mp15-pinctrl.dtsi" #include "stm32mp15xxaa-pinctrl.dtsi" #include @@ -97,10 +94,6 @@ status = "okay"; }; -&gpu { - status = "okay"; -}; - &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; diff --git a/src/arm/stm32mp15xx-dhcor-avenger96.dtsi b/src/arm/stm32mp15xx-dhcor-avenger96.dtsi new file mode 100644 index 000000000000..930202742a3f --- /dev/null +++ b/src/arm/stm32mp15xx-dhcor-avenger96.dtsi @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ + +/* Avenger96 uses DHCOR SoM configured for 1V8 IO operation */ +#include "stm32mp15xx-dhcor-io1v8.dtsi" + +/ { + aliases { + ethernet0 = ðernet0; + mmc0 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + serial2 = &usart2; + spi0 = &qspi; + }; + + /* XTal Q1 */ + cec_clock: clk-cec-fixed { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7513_out>; + }; + }; + }; + + led { + compatible = "gpio-leds"; + led1 { + label = "green:user0"; + gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led2 { + label = "green:user1"; + gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "green:user2"; + gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + led4 { + label = "green:user3"; + gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP1-AV96-HDMI"; + dais = <&sai2a_port>; + status = "okay"; + }; + + wlan_pwr: regulator-wlan { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpioz 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&i2c1 { /* X6 I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c2 { /* X6 I2C2 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_c>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + hdmi-transmitter@3d { + compatible = "adi,adv7513"; + reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>; + reg-names = "main", "cec", "edid", "packet"; + clocks = <&cec_clock>; + clock-names = "cec"; + + avdd-supply = <&v3v3>; + dvdd-supply = <&v3v3>; + pvdd-supply = <&v3v3>; + dvdd-3v-supply = <&v3v3>; + bgvdd-supply = <&v3v3>; + + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpiog>; + + status = "okay"; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_in: endpoint { + remote-endpoint = <<dc_ep0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7513_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + + port@2 { + reg = <2>; + adv7513_i2s0: endpoint { + remote-endpoint = <&sai2a_endpoint>; + }; + }; + }; + }; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_d>; + pinctrl-1 = <<dc_sleep_pins_d>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_ep0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&adv7513_in>; + }; + }; +}; + +&sai2 { + clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai2a_pins_c>; + pinctrl-1 = <&sai2a_sleep_pins_c>; + clock-names = "pclk", "x8k", "x11k"; + status = "okay"; + + sai2a: audio-controller@4400b004 { + #clock-cells = <0>; + dma-names = "tx"; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + status = "okay"; + + sai2a_port: port { + sai2a_endpoint: endpoint { + remote-endpoint = <&adv7513_i2s0>; + format = "i2s"; + mclk-fs = <256>; + }; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd_io>; + status = "okay"; +}; + +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_b>; + pinctrl-1 = <&sdmmc3_b4_od_pins_b>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_b>; + broken-cd; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&wlan_pwr>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + cs-gpios = <&gpioi 0 0>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&uart4 { + /* On Low speed expansion header */ + label = "LS-UART1"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + status = "okay"; +}; + +&uart7 { + /* On Low speed expansion header */ + label = "LS-UART0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + st,hw-flow-ctrl; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; diff --git a/src/arm/stm32mp15xx-dhcor-io1v8.dtsi b/src/arm/stm32mp15xx-dhcor-io1v8.dtsi new file mode 100644 index 000000000000..75172314d7af --- /dev/null +++ b/src/arm/stm32mp15xx-dhcor-io1v8.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ + +/ { + /* Enpirion EP3A8LQI U2 on the DHCOR */ + vdd_io: regulator-buck-io { + compatible = "regulator-fixed"; + regulator-name = "buck-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; +}; + +&pwr_regulators { + vdd-supply = <&vdd_io>; +}; diff --git a/src/arm/stm32mp15xx-dhcor-som.dtsi b/src/arm/stm32mp15xx-dhcor-som.dtsi new file mode 100644 index 000000000000..04fbb324a541 --- /dev/null +++ b/src/arm/stm32mp15xx-dhcor-som.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) Linaro Ltd 2019 - All Rights Reserved + * Author: Manivannan Sadhasivam + * Copyright (C) 2020 Marek Vasut + */ + +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include + +/ { + aliases { + spi0 = &qspi; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x40000000>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo2-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo5-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + vdda: ldo1 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + }; + + v2v8: ldo2 { + regulator-name = "v2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v8: ldo6 { + regulator-name = "v1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = ; + regulator-enable-ramp-delay = <300000>; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge = <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x200000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; diff --git a/src/arm/stm32mp15xx-dkx.dtsi b/src/arm/stm32mp15xx-dkx.dtsi index d946e0a02f5c..70db923a45f7 100644 --- a/src/arm/stm32mp15xx-dkx.dtsi +++ b/src/arm/stm32mp15xx-dkx.dtsi @@ -112,14 +112,18 @@ &cec { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cec_pins_b>; - pinctrl-1 = <&cec_pins_sleep_b>; + pinctrl-1 = <&cec_sleep_pins_b>; + status = "okay"; +}; + +&dts { status = "okay"; }; ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; - pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; pinctrl-names = "default", "sleep"; phy-mode = "rgmii-id"; max-speed = <1000>; @@ -137,13 +141,12 @@ &gpu { contiguous-area = <&gpu_reserved>; - status = "okay"; }; &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; - pinctrl-1 = <&i2c1_pins_sleep_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; i2c-scl-rising-time-ns = <100>; i2c-scl-falling-time-ns = <7>; status = "okay"; @@ -218,7 +221,7 @@ &i2c4 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_pins_a>; - pinctrl-1 = <&i2c4_pins_sleep_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; clock-frequency = <400000>; @@ -367,7 +370,7 @@ clock-names = "pclk", "i2sclk", "x8k", "x11k"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2s2_pins_a>; - pinctrl-1 = <&i2s2_pins_sleep_a>; + pinctrl-1 = <&i2s2_sleep_pins_a>; status = "okay"; i2s2_port: port { @@ -391,13 +394,10 @@ <dc { pinctrl-names = "default", "sleep"; pinctrl-0 = <<dc_pins_a>; - pinctrl-1 = <<dc_pins_sleep_a>; + pinctrl-1 = <<dc_sleep_pins_a>; status = "okay"; port { - #address-cells = <1>; - #size-cells = <0>; - ltdc_ep0_out: endpoint@0 { reg = <0>; remote-endpoint = <&sii9022_in>; diff --git a/src/arm/stm32mp15xx-osd32.dtsi b/src/arm/stm32mp15xx-osd32.dtsi new file mode 100644 index 000000000000..713485a95795 --- /dev/null +++ b/src/arm/stm32mp15xx-osd32.dtsi @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2020 Ahmad Fatoum, Pengutronix + */ + +#include "stm32mp15-pinctrl.dtsi" + +#include + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + reg_sip_eeprom: regulator_eeprom { + compatible = "regulator-fixed"; + regulator-name = "sip_eeprom"; + regulator-always-on; + }; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v2_hdmi: ldo6 { + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = ; + + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + }; + + pmic_watchdog: watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + sip_eeprom: eeprom@50 { + compatible = "atmel,24c32"; + vcc-supply = <®_sip_eeprom>; + reg = <0x50>; + }; +}; + +&ipcc { + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; diff --git a/src/arm/sun4i-a10.dtsi b/src/arm/sun4i-a10.dtsi index bf531efc0610..0f95a6ef8543 100644 --- a/src/arm/sun4i-a10.dtsi +++ b/src/arm/sun4i-a10.dtsi @@ -198,7 +198,7 @@ default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; - alloc-ranges = <0x4a000000 0x6000000>; + alloc-ranges = <0x40000000 0x10000000>; reusable; linux,cma-default; }; diff --git a/src/arm/sun5i.dtsi b/src/arm/sun5i.dtsi index e6b036734a64..c2b4fbf552a3 100644 --- a/src/arm/sun5i.dtsi +++ b/src/arm/sun5i.dtsi @@ -117,7 +117,7 @@ default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; - alloc-ranges = <0x4a000000 0x6000000>; + alloc-ranges = <0x40000000 0x10000000>; reusable; linux,cma-default; }; diff --git a/src/arm/sun7i-a20-olinuxino-lime-emmc.dts b/src/arm/sun7i-a20-olinuxino-lime-emmc.dts new file mode 100644 index 000000000000..033cab3443f8 --- /dev/null +++ b/src/arm/sun7i-a20-olinuxino-lime-emmc.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Olimex Ltd. + * Author: Stefan Mavrodiev + */ + +#include "sun7i-a20-olinuxino-lime.dts" + +/ { + model = "Olimex A20-OLinuXino-LIME-eMMC"; + compatible = "olimex,a20-olinuxino-lime-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&mmc2_pwrseq>; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/src/arm/sun7i-a20.dtsi b/src/arm/sun7i-a20.dtsi index ffe1d10a1a84..6d6a37940db2 100644 --- a/src/arm/sun7i-a20.dtsi +++ b/src/arm/sun7i-a20.dtsi @@ -181,7 +181,7 @@ default-pool { compatible = "shared-dma-pool"; size = <0x6000000>; - alloc-ranges = <0x4a000000 0x6000000>; + alloc-ranges = <0x40000000 0x10000000>; reusable; linux,cma-default; }; diff --git a/src/arm/sun8i-a83t.dtsi b/src/arm/sun8i-a83t.dtsi index 655404d6d3a3..c010b27fdb6a 100644 --- a/src/arm/sun8i-a83t.dtsi +++ b/src/arm/sun8i-a83t.dtsi @@ -610,6 +610,16 @@ clock-names = "bus", "mod"; }; + msgbox: mailbox@1c17000 { + compatible = "allwinner,sun8i-a83t-msgbox", + "allwinner,sun6i-a31-msgbox"; + reg = <0x01c17000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = ; + #mbox-cells = <1>; + }; + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-a83t-musb", "allwinner,sun8i-a33-musb"; diff --git a/src/arm/sun8i-h2-plus-bananapi-m2-zero.dts b/src/arm/sun8i-h2-plus-bananapi-m2-zero.dts index d277d043031b..4c6704e4c57e 100644 --- a/src/arm/sun8i-h2-plus-bananapi-m2-zero.dts +++ b/src/arm/sun8i-h2-plus-bananapi-m2-zero.dts @@ -31,7 +31,7 @@ pwr_led { label = "bananapi-m2-zero:red:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */ default-state = "on"; }; }; diff --git a/src/arm/sun8i-h3.dtsi b/src/arm/sun8i-h3.dtsi index e83aa6866e7e..4e89701df91f 100644 --- a/src/arm/sun8i-h3.dtsi +++ b/src/arm/sun8i-h3.dtsi @@ -112,6 +112,26 @@ }; }; + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + }; + + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + }; + + opp-432000000 { + opp-hz = /bits/ 64 <432000000>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + }; + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts = , @@ -205,9 +225,7 @@ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; clock-names = "bus", "core"; resets = <&ccu RST_BUS_GPU>; - - assigned-clocks = <&ccu CLK_GPU>; - assigned-clock-rates = <384000000>; + operating-points-v2 = <&gpu_opp_table>; }; ths: thermal-sensor@1c25000 { diff --git a/src/arm/sunxi-h3-h5.dtsi b/src/arm/sunxi-h3-h5.dtsi index 01a5df9aa71b..22d533d18992 100644 --- a/src/arm/sunxi-h3-h5.dtsi +++ b/src/arm/sunxi-h3-h5.dtsi @@ -239,6 +239,16 @@ }; }; + msgbox: mailbox@1c17000 { + compatible = "allwinner,sun8i-h3-msgbox", + "allwinner,sun6i-a31-msgbox"; + reg = <0x01c17000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = ; + #mbox-cells = <1>; + }; + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-h3-musb"; reg = <0x01c19000 0x400>; diff --git a/src/arm/tegra114-dalmore.dts b/src/arm/tegra114-dalmore.dts index d3e032e7d21a..08be733ee2cd 100644 --- a/src/arm/tegra114-dalmore.dts +++ b/src/arm/tegra114-dalmore.dts @@ -46,8 +46,7 @@ avdd-dsi-csi-supply = <&avdd_1v2_reg>; panel@0 { - compatible = "panasonic,vvx10f004b00", - "simple-panel"; + compatible = "panasonic,vvx10f004b00"; reg = <0>; power-supply = <&avdd_lcd_reg>; diff --git a/src/arm/tegra124-venice2.dts b/src/arm/tegra124-venice2.dts index 8c2ee6e7d6f1..73361dbe2e43 100644 --- a/src/arm/tegra124-venice2.dts +++ b/src/arm/tegra124-venice2.dts @@ -1087,7 +1087,7 @@ }; panel: panel { - compatible = "lg,lp129qe", "simple-panel"; + compatible = "lg,lp129qe"; backlight = <&backlight>; ddc-i2c-bus = <&dpaux>; diff --git a/src/arm/tegra20-colibri-eval-v3.dts b/src/arm/tegra20-colibri-eval-v3.dts index 3c0f2681fcde..37ad508b61d9 100644 --- a/src/arm/tegra20-colibri-eval-v3.dts +++ b/src/arm/tegra20-colibri-eval-v3.dts @@ -223,7 +223,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/src/arm/tegra20-colibri-iris.dts b/src/arm/tegra20-colibri-iris.dts index d8004d68efa0..af4740847769 100644 --- a/src/arm/tegra20-colibri-iris.dts +++ b/src/arm/tegra20-colibri-iris.dts @@ -205,7 +205,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/src/arm/tegra20-harmony.dts b/src/arm/tegra20-harmony.dts index 1d96d92b72a7..02cd67ea2503 100644 --- a/src/arm/tegra20-harmony.dts +++ b/src/arm/tegra20-harmony.dts @@ -665,7 +665,7 @@ }; panel: panel { - compatible = "auo,b101aw03", "simple-panel"; + compatible = "auo,b101aw03"; power-supply = <&vdd_pnl_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; diff --git a/src/arm/tegra20-medcom-wide.dts b/src/arm/tegra20-medcom-wide.dts index cda5448c2ace..c73510cd501c 100644 --- a/src/arm/tegra20-medcom-wide.dts +++ b/src/arm/tegra20-medcom-wide.dts @@ -57,7 +57,7 @@ }; panel: panel { - compatible = "innolux,n156bge-l21", "simple-panel"; + compatible = "innolux,n156bge-l21"; power-supply = <&vdd_1v8_reg>, <&vdd_3v3_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; diff --git a/src/arm/tegra20-paz00.dts b/src/arm/tegra20-paz00.dts index be0ab9b84b9a..cce3a3fb82ed 100644 --- a/src/arm/tegra20-paz00.dts +++ b/src/arm/tegra20-paz00.dts @@ -604,7 +604,7 @@ }; panel: panel { - compatible = "samsung,ltn101nt05", "simple-panel"; + compatible = "samsung,ltn101nt05"; ddc-i2c-bus = <&lvds_ddc>; power-supply = <&vdd_pnl_reg>; diff --git a/src/arm/tegra20-seaboard.dts b/src/arm/tegra20-seaboard.dts index f91441683aad..376ecb6435f4 100644 --- a/src/arm/tegra20-seaboard.dts +++ b/src/arm/tegra20-seaboard.dts @@ -826,7 +826,7 @@ }; panel: panel { - compatible = "chunghwa,claa101wa01a", "simple-panel"; + compatible = "chunghwa,claa101wa01a"; power-supply = <&vdd_pnl_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; diff --git a/src/arm/tegra20-ventana.dts b/src/arm/tegra20-ventana.dts index f44551e2d9d0..022649119821 100644 --- a/src/arm/tegra20-ventana.dts +++ b/src/arm/tegra20-ventana.dts @@ -611,7 +611,7 @@ }; panel: panel { - compatible = "chunghwa,claa101wa01a", "simple-panel"; + compatible = "chunghwa,claa101wa01a"; power-supply = <&vdd_pnl_reg>; enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; diff --git a/src/arm/tegra30-apalis-eval.dts b/src/arm/tegra30-apalis-eval.dts index 749fc6d1ff70..b39c26806bf2 100644 --- a/src/arm/tegra30-apalis-eval.dts +++ b/src/arm/tegra30-apalis-eval.dts @@ -195,7 +195,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/src/arm/tegra30-apalis-v1.1-eval.dts b/src/arm/tegra30-apalis-v1.1-eval.dts index 0be50e881684..e29dca92ba0a 100644 --- a/src/arm/tegra30-apalis-v1.1-eval.dts +++ b/src/arm/tegra30-apalis-v1.1-eval.dts @@ -196,7 +196,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/src/arm/tegra30-beaver.dts b/src/arm/tegra30-beaver.dts index 45ef6002b225..6b6fd8a8058f 100644 --- a/src/arm/tegra30-beaver.dts +++ b/src/arm/tegra30-beaver.dts @@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" / { model = "NVIDIA Tegra30 Beaver evaluation board"; @@ -1806,9 +1808,14 @@ vddctrl_reg: vddctrl { regulator-name = "vdd_cpu,vdd_sys"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-coupled-with = <&core_vdd_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; vio_reg: vio { @@ -1868,17 +1875,22 @@ }; }; - tps62361@60 { + core_vdd_reg: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; regulator-name = "tps62361-vout"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1500000>; + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; regulator-boot-on; regulator-always-on; ti,vsel0-state-high; ti,vsel1-state-high; + + nvidia,tegra-core-regulator; }; }; @@ -2120,4 +2132,26 @@ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, <&tegra_car TEGRA30_CLK_EXTERN1>; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; }; diff --git a/src/arm/tegra30-cardhu.dtsi b/src/arm/tegra30-cardhu.dtsi index 4b4f49a49394..5ee5d141bd81 100644 --- a/src/arm/tegra30-cardhu.dtsi +++ b/src/arm/tegra30-cardhu.dtsi @@ -432,7 +432,7 @@ }; panel: panel { - compatible = "chunghwa,claa101wb01", "simple-panel"; + compatible = "chunghwa,claa101wb01"; ddc-i2c-bus = <&panelddc>; power-supply = <&vdd_pnl1_reg>; diff --git a/src/arm/tegra30-colibri-eval-v3.dts b/src/arm/tegra30-colibri-eval-v3.dts index 5965150ecdd2..8e106e784dce 100644 --- a/src/arm/tegra30-colibri-eval-v3.dts +++ b/src/arm/tegra30-colibri-eval-v3.dts @@ -159,7 +159,7 @@ * edt,et057090dhu: EDT 5.7" LCD TFT * edt,et070080dh6: EDT 7.0" LCD TFT */ - compatible = "edt,et057090dhu", "simple-panel"; + compatible = "edt,et057090dhu"; backlight = <&backlight>; power-supply = <®_3v3>; }; diff --git a/src/arm/uniphier-ld4.dtsi b/src/arm/uniphier-ld4.dtsi index 06e7400d2940..b52957ccda0d 100644 --- a/src/arm/uniphier-ld4.dtsi +++ b/src/arm/uniphier-ld4.dtsi @@ -67,6 +67,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; diff --git a/src/arm/uniphier-ld6b-ref.dts b/src/arm/uniphier-ld6b-ref.dts index 60994b6e8b99..079cadc11e6c 100644 --- a/src/arm/uniphier-ld6b-ref.dts +++ b/src/arm/uniphier-ld6b-ref.dts @@ -29,6 +29,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/src/arm/uniphier-pro4-ace.dts b/src/arm/uniphier-pro4-ace.dts index 92cc48dd86d0..64246fad325c 100644 --- a/src/arm/uniphier-pro4-ace.dts +++ b/src/arm/uniphier-pro4-ace.dts @@ -26,6 +26,7 @@ i2c3 = &i2c3; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/src/arm/uniphier-pro4-ref.dts b/src/arm/uniphier-pro4-ref.dts index 854f2eba3e72..181442c48532 100644 --- a/src/arm/uniphier-pro4-ref.dts +++ b/src/arm/uniphier-pro4-ref.dts @@ -29,6 +29,7 @@ i2c3 = &i2c3; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/src/arm/uniphier-pro4-sanji.dts b/src/arm/uniphier-pro4-sanji.dts index dda1a2f214a8..5396556dee58 100644 --- a/src/arm/uniphier-pro4-sanji.dts +++ b/src/arm/uniphier-pro4-sanji.dts @@ -25,6 +25,7 @@ i2c3 = &i2c3; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/src/arm/uniphier-pro4.dtsi b/src/arm/uniphier-pro4.dtsi index 1c866f0306fc..a53b73ee93e9 100644 --- a/src/arm/uniphier-pro4.dtsi +++ b/src/arm/uniphier-pro4.dtsi @@ -75,6 +75,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -426,6 +428,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pro4-aidet"; reg = <0x5fc20000 0x200>; diff --git a/src/arm/uniphier-pro5.dtsi b/src/arm/uniphier-pro5.dtsi index 8f1ae0957f5f..feadb4a378eb 100644 --- a/src/arm/uniphier-pro5.dtsi +++ b/src/arm/uniphier-pro5.dtsi @@ -160,6 +160,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -171,6 +173,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; @@ -408,6 +412,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pro5-aidet"; reg = <0x5fc20000 0x200>; diff --git a/src/arm/uniphier-pxs2-gentil.dts b/src/arm/uniphier-pxs2-gentil.dts index e27fd4f2a569..8e9ac579aa9a 100644 --- a/src/arm/uniphier-pxs2-gentil.dts +++ b/src/arm/uniphier-pxs2-gentil.dts @@ -26,6 +26,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/src/arm/uniphier-pxs2-vodka.dts b/src/arm/uniphier-pxs2-vodka.dts index 23fe42b7408b..8eacc7bdecb7 100644 --- a/src/arm/uniphier-pxs2-vodka.dts +++ b/src/arm/uniphier-pxs2-vodka.dts @@ -24,6 +24,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + ethernet0 = ð }; memory@80000000 { diff --git a/src/arm/uniphier-pxs2.dtsi b/src/arm/uniphier-pxs2.dtsi index 2f2a24994c69..b0b15c97306b 100644 --- a/src/arm/uniphier-pxs2.dtsi +++ b/src/arm/uniphier-pxs2.dtsi @@ -173,6 +173,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -184,6 +186,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; @@ -508,6 +512,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pxs2-aidet"; reg = <0x5fc20000 0x200>; diff --git a/src/arm/uniphier-sld8.dtsi b/src/arm/uniphier-sld8.dtsi index 09992163e1f4..96a766deb8d1 100644 --- a/src/arm/uniphier-sld8.dtsi +++ b/src/arm/uniphier-sld8.dtsi @@ -67,6 +67,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; diff --git a/src/arm/vexpress-v2m-rs1.dtsi b/src/arm/vexpress-v2m-rs1.dtsi index 5c183483ec3b..a88ee5294d35 100644 --- a/src/arm/vexpress-v2m-rs1.dtsi +++ b/src/arm/vexpress-v2m-rs1.dtsi @@ -19,8 +19,89 @@ */ / { + v2m_fixed_3v3: fixed-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + label = "v2m:green:user1"; + gpios = <&v2m_led_gpios 0 0>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + label = "v2m:green:user2"; + gpios = <&v2m_led_gpios 1 0>; + linux,default-trigger = "disk-activity"; + }; + + led-3 { + label = "v2m:green:user3"; + gpios = <&v2m_led_gpios 2 0>; + linux,default-trigger = "cpu0"; + }; + + led-4 { + label = "v2m:green:user4"; + gpios = <&v2m_led_gpios 3 0>; + linux,default-trigger = "cpu1"; + }; + + led-5 { + label = "v2m:green:user5"; + gpios = <&v2m_led_gpios 4 0>; + linux,default-trigger = "cpu2"; + }; + + led-6 { + label = "v2m:green:user6"; + gpios = <&v2m_led_gpios 5 0>; + linux,default-trigger = "cpu3"; + }; + + led-7 { + label = "v2m:green:user7"; + gpios = <&v2m_led_gpios 6 0>; + linux,default-trigger = "cpu4"; + }; + + led-8 { + label = "v2m:green:user8"; + gpios = <&v2m_led_gpios 7 0>; + linux,default-trigger = "cpu5"; + }; + }; + bus@8000000 { - motherboard { + motherboard-bus { model = "V2M-P1"; arm,hbi = <0x190>; arm,vexpress,site = <0>; @@ -31,7 +112,7 @@ #interrupt-cells = <1>; ranges; - nor_flash: flash@0,00000000 { + nor_flash: flash@0 { compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>, <4 0x00000000 0x04000000>; @@ -41,13 +122,13 @@ }; }; - psram@1,00000000 { + psram@100000000 { compatible = "arm,vexpress-psram", "mtd-ram"; reg = <1 0x00000000 0x02000000>; bank-width = <4>; }; - ethernet@2,02000000 { + ethernet@202000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <2 0x02000000 0x10000>; interrupts = <15>; @@ -59,14 +140,14 @@ vddvario-supply = <&v2m_fixed_3v3>; }; - usb@2,03000000 { + usb@203000000 { compatible = "nxp,usb-isp1761"; reg = <2 0x03000000 0x20000>; interrupts = <16>; port1-otg; }; - iofpga@3,00000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -162,7 +243,7 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - v2m_serial0: uart@90000 { + v2m_serial0: serial@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -170,7 +251,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@a0000 { + v2m_serial1: serial@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -178,7 +259,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@b0000 { + v2m_serial2: serial@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -186,7 +267,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@c0000 { + v2m_serial3: serial@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; @@ -281,159 +362,78 @@ }; }; }; - }; - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; + oscclk0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 65000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; + v2m_oscclk2: oscclk2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; - leds { - compatible = "gpio-leds"; + volt-vio { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; + temp-mcc { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; }; }; }; diff --git a/src/arm64/allwinner/sun50i-a64-olinuxino.dts b/src/arm64/allwinner/sun50i-a64-olinuxino.dts index 5fa9ca0191a8..f3f8e177ab61 100644 --- a/src/arm64/allwinner/sun50i-a64-olinuxino.dts +++ b/src/arm64/allwinner/sun50i-a64-olinuxino.dts @@ -32,6 +32,15 @@ }; }; + leds { + compatible = "gpio-leds"; + + led-0 { + label = "a64-olinuxino:red:user"; + gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ + }; + }; + reg_usb1_vbus: usb1-vbus { compatible = "regulator-fixed"; regulator-name = "usb1-vbus"; diff --git a/src/arm64/allwinner/sun50i-a64.dtsi b/src/arm64/allwinner/sun50i-a64.dtsi index c26cc1fcaffd..8dfbcd144072 100644 --- a/src/arm64/allwinner/sun50i-a64.dtsi +++ b/src/arm64/allwinner/sun50i-a64.dtsi @@ -539,6 +539,16 @@ resets = <&ccu RST_BUS_CE>; }; + msgbox: mailbox@1c17000 { + compatible = "allwinner,sun50i-a64-msgbox", + "allwinner,sun6i-a31-msgbox"; + reg = <0x01c17000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = ; + #mbox-cells = <1>; + }; + usb_otg: usb@1c19000 { compatible = "allwinner,sun8i-a33-musb"; reg = <0x01c19000 0x0400>; @@ -1065,6 +1075,8 @@ compatible = "allwinner,sun50i-a64-mbus"; reg = <0x01c62000 0x1000>; clocks = <&ccu 112>; + #address-cells = <1>; + #size-cells = <1>; dma-ranges = <0x00000000 0x40000000 0xc0000000>; #interconnect-cells = <1>; }; diff --git a/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts b/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts index 8f09d209359b..3f7ceeb1a767 100644 --- a/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts +++ b/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts @@ -4,6 +4,7 @@ /dts-v1/; #include "sun50i-h6.dtsi" +#include "sun50i-h6-cpu-opp.dtsi" #include @@ -77,6 +78,10 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdca>; +}; + &de { status = "okay"; }; @@ -234,7 +239,8 @@ reg_dcdca: dcdca { regulator-always-on; regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; + regulator-max-microvolt = <1160000>; + regulator-ramp-delay = <2500>; regulator-name = "vdd-cpu"; }; @@ -242,6 +248,7 @@ regulator-enable-ramp-delay = <32000>; regulator-min-microvolt = <810000>; regulator-max-microvolt = <1080000>; + regulator-ramp-delay = <2500>; regulator-name = "vdd-gpu"; }; diff --git a/src/arm64/allwinner/sun50i-h6-cpu-opp.dtsi b/src/arm64/allwinner/sun50i-h6-cpu-opp.dtsi new file mode 100644 index 000000000000..1a5eddc5a40f --- /dev/null +++ b/src/arm64/allwinner/sun50i-h6-cpu-opp.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Ondrej Jirman +// Copyright (C) 2020 Clément Péron + +/ { + cpu_opp_table: cpu-opp-table { + compatible = "allwinner,sun50i-h6-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + opp-shared; + + opp@480000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <480000000>; + + opp-microvolt-speed0 = <880000 880000 1200000>; + opp-microvolt-speed1 = <820000 820000 1200000>; + opp-microvolt-speed2 = <820000 820000 1200000>; + }; + + opp@720000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <720000000>; + + opp-microvolt-speed0 = <880000 880000 1200000>; + opp-microvolt-speed1 = <820000 820000 1200000>; + opp-microvolt-speed2 = <820000 820000 1200000>; + }; + + opp@816000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <816000000>; + + opp-microvolt-speed0 = <880000 880000 1200000>; + opp-microvolt-speed1 = <820000 820000 1200000>; + opp-microvolt-speed2 = <820000 820000 1200000>; + }; + + opp@888000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <888000000>; + + opp-microvolt-speed0 = <880000 880000 1200000>; + opp-microvolt-speed1 = <820000 820000 1200000>; + opp-microvolt-speed2 = <820000 820000 1200000>; + }; + + opp@1080000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1080000000>; + + opp-microvolt-speed0 = <940000 940000 1200000>; + opp-microvolt-speed1 = <880000 880000 1200000>; + opp-microvolt-speed2 = <880000 880000 1200000>; + }; + + opp@1320000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1320000000>; + + opp-microvolt-speed0 = <1000000 1000000 1200000>; + opp-microvolt-speed1 = <940000 940000 1200000>; + opp-microvolt-speed2 = <940000 940000 1200000>; + }; + + opp@1488000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1488000000>; + + opp-microvolt-speed0 = <1060000 1060000 1200000>; + opp-microvolt-speed1 = <1000000 1000000 1200000>; + opp-microvolt-speed2 = <1000000 1000000 1200000>; + }; + + opp@1608000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1608000000>; + + opp-microvolt-speed0 = <1090000 1090000 1200000>; + opp-microvolt-speed1 = <1030000 1030000 1200000>; + opp-microvolt-speed2 = <1030000 1030000 1200000>; + }; + + opp@1704000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1704000000>; + + opp-microvolt-speed0 = <1120000 1120000 1200000>; + opp-microvolt-speed1 = <1060000 1060000 1200000>; + opp-microvolt-speed2 = <1060000 1060000 1200000>; + }; + + opp@1800000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1800000000>; + + opp-microvolt-speed0 = <1160000 1160000 1200000>; + opp-microvolt-speed1 = <1100000 1100000 1200000>; + opp-microvolt-speed2 = <1100000 1100000 1200000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opp_table>; +}; diff --git a/src/arm64/allwinner/sun50i-h6-orangepi-3.dts b/src/arm64/allwinner/sun50i-h6-orangepi-3.dts index 47f579610dcc..15c9dd8c4479 100644 --- a/src/arm64/allwinner/sun50i-h6-orangepi-3.dts +++ b/src/arm64/allwinner/sun50i-h6-orangepi-3.dts @@ -4,6 +4,7 @@ /dts-v1/; #include "sun50i-h6.dtsi" +#include "sun50i-h6-cpu-opp.dtsi" #include @@ -257,6 +258,7 @@ regulator-always-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1160000>; + regulator-ramp-delay = <2500>; regulator-name = "vdd-cpu"; }; @@ -264,6 +266,7 @@ regulator-enable-ramp-delay = <32000>; regulator-min-microvolt = <810000>; regulator-max-microvolt = <1080000>; + regulator-ramp-delay = <2500>; regulator-name = "vdd-gpu"; }; diff --git a/src/arm64/allwinner/sun50i-h6-orangepi-lite2.dts b/src/arm64/allwinner/sun50i-h6-orangepi-lite2.dts index e7ca75c0d0f7..e8770858b5d0 100644 --- a/src/arm64/allwinner/sun50i-h6-orangepi-lite2.dts +++ b/src/arm64/allwinner/sun50i-h6-orangepi-lite2.dts @@ -6,4 +6,69 @@ / { model = "OrangePi Lite2"; compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6"; + + aliases { + serial1 = &uart1; /* BT-UART */ + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc 1>; + clock-names = "ext_clock"; + reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ + post-power-on-delay-ms = <200>; + }; +}; + +&mmc1 { + vmmc-supply = <®_cldo2>; + vqmmc-supply = <®_bldo3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcm: sdio-wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ + interrupt-names = "host-wake"; + }; +}; + +®_cldo2 { + /* + * This regulator is connected with CLDO3. + * Before the kernel can support synchronized + * enable of coupled regulators, keep them + * both always on as a ugly hack. + */ + regulator-always-on; +}; + +®_cldo3 { + /* + * This regulator is connected with CLDO2. + * See the comments for CLDO2. + */ + regulator-always-on; +}; + +/* There's the BT part of the AP6255 connected to that UART */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rtc 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ + host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ + shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ + max-speed = <1500000>; + }; }; diff --git a/src/arm64/allwinner/sun50i-h6-orangepi.dtsi b/src/arm64/allwinner/sun50i-h6-orangepi.dtsi index 9287976c4a50..ebc120a9232f 100644 --- a/src/arm64/allwinner/sun50i-h6-orangepi.dtsi +++ b/src/arm64/allwinner/sun50i-h6-orangepi.dtsi @@ -106,6 +106,12 @@ status = "okay"; }; +&pio { + vcc-pc-supply = <®_bldo2>; + vcc-pd-supply = <®_cldo1>; + vcc-pg-supply = <®_aldo1>; +}; + &r_i2c { status = "okay"; @@ -230,6 +236,10 @@ status = "okay"; }; +&r_pio { + vcc-pm-supply = <®_bldo3>; +}; + &rtc { clocks = <&ext_osc32k>; }; @@ -241,7 +251,12 @@ }; &usb2otg { - dr_mode = "otg"; + /* + * OrangePi Lite 2 and One Plus, where this DT is used, don't + * have a controllable VBUS even though they do have an ID pin. + * Using it as anything but a USB host is unsafe. + */ + dr_mode = "host"; status = "okay"; }; diff --git a/src/arm64/allwinner/sun50i-h6-pine-h64.dts b/src/arm64/allwinner/sun50i-h6-pine-h64.dts index b0642d841933..af85b2074867 100644 --- a/src/arm64/allwinner/sun50i-h6-pine-h64.dts +++ b/src/arm64/allwinner/sun50i-h6-pine-h64.dts @@ -4,6 +4,7 @@ /dts-v1/; #include "sun50i-h6.dtsi" +#include "sun50i-h6-cpu-opp.dtsi" #include @@ -80,6 +81,22 @@ }; }; +&cpu0 { + cpu-supply = <®_dcdca>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + &emac { pinctrl-names = "default"; pinctrl-0 = <&ext_rgmii_pins>; @@ -91,17 +108,6 @@ status = "okay"; }; -&mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; -}; - -&de { - status = "okay"; -}; - &gpu { mali-supply = <®_dcdcc>; status = "okay"; @@ -117,12 +123,11 @@ }; }; -&ehci0 { - status = "okay"; -}; - -&ehci3 { - status = "okay"; +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; }; &mmc0 { @@ -238,7 +243,8 @@ reg_dcdca: dcdca { regulator-always-on; regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; + regulator-max-microvolt = <1160000>; + regulator-ramp-delay = <2500>; regulator-name = "vdd-cpu"; }; @@ -246,6 +252,7 @@ regulator-enable-ramp-delay = <32000>; regulator-min-microvolt = <810000>; regulator-max-microvolt = <1080000>; + regulator-ramp-delay = <2500>; regulator-name = "vdd-gpu"; }; diff --git a/src/arm64/allwinner/sun50i-h6-tanix-tx6.dts b/src/arm64/allwinner/sun50i-h6-tanix-tx6.dts index 83e6cb0e59ce..be81330db14f 100644 --- a/src/arm64/allwinner/sun50i-h6-tanix-tx6.dts +++ b/src/arm64/allwinner/sun50i-h6-tanix-tx6.dts @@ -4,6 +4,7 @@ /dts-v1/; #include "sun50i-h6.dtsi" +#include "sun50i-h6-cpu-opp.dtsi" #include @@ -37,6 +38,17 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + reg_vdd_cpu_gpu: vdd-cpu-gpu { + compatible = "regulator-fixed"; + regulator-name = "vdd-cpu-gpu"; + regulator-min-microvolt = <1135000>; + regulator-max-microvolt = <1135000>; + }; +}; + +&cpu0 { + cpu-supply = <®_vdd_cpu_gpu>; }; &de { @@ -56,6 +68,7 @@ }; &gpu { + mali-supply = <®_vdd_cpu_gpu>; status = "okay"; }; diff --git a/src/arm64/allwinner/sun50i-h6.dtsi b/src/arm64/allwinner/sun50i-h6.dtsi index b9ab7d8fa8af..9ce78a7b117d 100644 --- a/src/arm64/allwinner/sun50i-h6.dtsi +++ b/src/arm64/allwinner/sun50i-h6.dtsi @@ -25,6 +25,9 @@ device_type = "cpu"; reg = <0>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -32,6 +35,9 @@ device_type = "cpu"; reg = <1>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -39,6 +45,9 @@ device_type = "cpu"; reg = <2>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -46,6 +55,9 @@ device_type = "cpu"; reg = <3>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; + clock-latency-ns = <244144>; /* 8 32k periods */ + #cooling-cells = <2>; }; }; @@ -123,6 +135,7 @@ clock-names = "bus", "mod"; resets = <&display_clocks RST_MIXER0>; + iommus = <&iommu 0>; ports { #address-cells = <1>; @@ -148,6 +161,7 @@ resets = <&ccu RST_BUS_VE>; interrupts = ; allwinner,sram = <&ve_sram 1>; + iommus = <&iommu 3>; }; gpu: gpu@1800000 { @@ -231,6 +245,16 @@ #dma-cells = <1>; }; + msgbox: mailbox@3003000 { + compatible = "allwinner,sun50i-h6-msgbox", + "allwinner,sun6i-a31-msgbox"; + reg = <0x03003000 0x1000>; + clocks = <&ccu CLK_BUS_MSGBOX>; + resets = <&ccu RST_BUS_MSGBOX>; + interrupts = ; + #mbox-cells = <1>; + }; + sid: efuse@3006000 { compatible = "allwinner,sun50i-h6-sid"; reg = <0x03006000 0x400>; @@ -240,6 +264,10 @@ ths_calibration: thermal-sensor-calibration@14 { reg = <0x14 0x8>; }; + + cpu_speed_grade: cpu-speed-grade@1c { + reg = <0x1c 0x4>; + }; }; watchdog: watchdog@30090a0 { @@ -387,6 +415,15 @@ #interrupt-cells = <3>; }; + iommu: iommu@30f0000 { + compatible = "allwinner,sun50i-h6-iommu"; + reg = <0x030f0000 0x10000>; + interrupts = ; + clocks = <&ccu CLK_BUS_IOMMU>; + resets = <&ccu RST_BUS_IOMMU>; + #iommu-cells = <1>; + }; + mmc0: mmc@4020000 { compatible = "allwinner,sun50i-h6-mmc", "allwinner,sun50i-a64-mmc"; @@ -946,6 +983,30 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpu-thermal { diff --git a/src/arm64/altera/socfpga_stratix10.dtsi b/src/arm64/altera/socfpga_stratix10.dtsi index d1fc9c2055f4..9498d1de730c 100644 --- a/src/arm64/altera/socfpga_stratix10.dtsi +++ b/src/arm64/altera/socfpga_stratix10.dtsi @@ -77,7 +77,7 @@ method = "smc"; }; - intc: intc@fffc1000 { + intc: interrupt-controller@fffc1000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; @@ -302,7 +302,7 @@ status = "disabled"; }; - nand: nand@ffb90000 { + nand: nand-controller@ffb90000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,socfpga-denali-nand"; @@ -445,7 +445,7 @@ clock-names = "timer"; }; - uart0: serial0@ffc02000 { + uart0: serial@ffc02000 { compatible = "snps,dw-apb-uart"; reg = <0xffc02000 0x100>; interrupts = <0 108 4>; @@ -456,7 +456,7 @@ status = "disabled"; }; - uart1: serial1@ffc02100 { + uart1: serial@ffc02100 { compatible = "snps,dw-apb-uart"; reg = <0xffc02100 0x100>; interrupts = <0 109 4>; diff --git a/src/arm64/altera/socfpga_stratix10_socdk.dts b/src/arm64/altera/socfpga_stratix10_socdk.dts index f6c4a15079d3..feadd21bc0dc 100644 --- a/src/arm64/altera/socfpga_stratix10_socdk.dts +++ b/src/arm64/altera/socfpga_stratix10_socdk.dts @@ -155,6 +155,7 @@ }; &qspi { + status = "okay"; flash@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/src/arm64/altera/socfpga_stratix10_socdk_nand.dts b/src/arm64/altera/socfpga_stratix10_socdk_nand.dts index 9946515b8afd..c07966740e14 100644 --- a/src/arm64/altera/socfpga_stratix10_socdk_nand.dts +++ b/src/arm64/altera/socfpga_stratix10_socdk_nand.dts @@ -188,6 +188,7 @@ }; &qspi { + status = "okay"; flash@0 { #address-cells = <1>; #size-cells = <1>; @@ -211,12 +212,12 @@ qspi_boot: partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x034B0000>; + reg = <0x0 0x03FE0000>; }; - qspi_rootfs: partition@4000000 { + qspi_rootfs: partition@3FE0000 { label = "Root Filesystem - JFFS2"; - reg = <0x034B0000 0x0EB50000>; + reg = <0x03FE0000 0x0C020000>; }; }; }; diff --git a/src/arm64/amlogic/meson-axg.dtsi b/src/arm64/amlogic/meson-axg.dtsi index aace3d32a3df..8e6281c685fa 100644 --- a/src/arm64/amlogic/meson-axg.dtsi +++ b/src/arm64/amlogic/meson-axg.dtsi @@ -1735,18 +1735,18 @@ }; sram: sram@fffc0000 { - compatible = "amlogic,meson-axg-sram", "mmio-sram"; + compatible = "mmio-sram"; reg = <0x0 0xfffc0000 0x0 0x20000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0xfffc0000 0x20000>; - cpu_scp_lpri: scp-shmem@13000 { + cpu_scp_lpri: scp-sram@13000 { compatible = "amlogic,meson-axg-scp-shmem"; reg = <0x13000 0x400>; }; - cpu_scp_hpri: scp-shmem@13400 { + cpu_scp_hpri: scp-sram@13400 { compatible = "amlogic,meson-axg-scp-shmem"; reg = <0x13400 0x400>; }; diff --git a/src/arm64/amlogic/meson-g12-common.dtsi b/src/arm64/amlogic/meson-g12-common.dtsi index c0aef7d69117..593a006f4b7b 100644 --- a/src/arm64/amlogic/meson-g12-common.dtsi +++ b/src/arm64/amlogic/meson-g12-common.dtsi @@ -250,6 +250,17 @@ }; }; + acodec: audio-controller@32000 { + compatible = "amlogic,t9015"; + reg = <0x0 0x32000 0x0 0x14>; + #sound-dai-cells = <0>; + sound-name-prefix = "ACODEC"; + clocks = <&clkc CLKID_AUDIO_CODEC>; + clock-names = "pclk"; + resets = <&reset RESET_AUDIO_CODEC>; + status = "disabled"; + }; + periphs: bus@34400 { compatible = "simple-bus"; reg = <0x0 0x34400 0x0 0x400>; diff --git a/src/arm64/amlogic/meson-g12.dtsi b/src/arm64/amlogic/meson-g12.dtsi index 55d39020ec72..6a1f4dcf6488 100644 --- a/src/arm64/amlogic/meson-g12.dtsi +++ b/src/arm64/amlogic/meson-g12.dtsi @@ -343,6 +343,15 @@ status = "disabled"; }; + toacodec: audio-controller@740 { + compatible = "amlogic,g12a-toacodec"; + reg = <0x0 0x740 0x0 0x4>; + #sound-dai-cells = <1>; + sound-name-prefix = "TOACODEC"; + resets = <&clkc_audio AUD_RESET_TOACODEC>; + status = "disabled"; + }; + tohdmitx: audio-controller@744 { compatible = "amlogic,g12a-tohdmitx"; reg = <0x0 0x744 0x0 0x4>; @@ -354,29 +363,6 @@ }; }; -&cpu_thermal { - cooling-maps { - map0 { - trip = <&cpu_passive>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_hot>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - ðmac { power-domains = <&pwrc PWRC_G12A_ETH_ID>; }; diff --git a/src/arm64/amlogic/meson-g12b-gtking-pro.dts b/src/arm64/amlogic/meson-g12b-gtking-pro.dts new file mode 100644 index 000000000000..f0c56a16af3d --- /dev/null +++ b/src/arm64/amlogic/meson-g12b-gtking-pro.dts @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + * Copyright (c) 2019 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-g12b-w400.dtsi" +#include + +/ { + compatible = "azw,gtking", "amlogic,g12b"; + model = "Beelink GT-King Pro"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + power-button { + label = "power"; + linux,code = ; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + + white { + label = "power:white"; + gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "G12B-GTKING-PRO"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; diff --git a/src/arm64/amlogic/meson-g12b-gtking.dts b/src/arm64/amlogic/meson-g12b-gtking.dts new file mode 100644 index 000000000000..eeb7bc5539ef --- /dev/null +++ b/src/arm64/amlogic/meson-g12b-gtking.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + * Copyright (c) 2019 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-g12b-w400.dtsi" +#include + +/ { + compatible = "azw,gtking", "amlogic,g12b"; + model = "Beelink GT-King"; + + spdif_dit: audio-codec-1 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + sound-name-prefix = "DIT"; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "G12B-GTKING"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT", + "SPDIFOUT IN 0", "FRDDR_A OUT 3", + "SPDIFOUT IN 1", "FRDDR_B OUT 3", + "SPDIFOUT IN 2", "FRDDR_C OUT 3"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* spdif hdmi or toslink interface */ + dai-link-4 { + sound-dai = <&spdifout>; + + codec-0 { + sound-dai = <&spdif_dit>; + }; + + codec-1 { + sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_A>; + }; + }; + + /* spdif hdmi interface */ + dai-link-5 { + sound-dai = <&spdifout_b>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_SPDIF_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-6 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&spdifout { + pinctrl-0 = <&spdif_out_h_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spdifout_b { + status = "okay"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; diff --git a/src/arm64/amlogic/meson-g12b-khadas-vim3.dtsi b/src/arm64/amlogic/meson-g12b-khadas-vim3.dtsi index c6c8caed8327..224c890d32d3 100644 --- a/src/arm64/amlogic/meson-g12b-khadas-vim3.dtsi +++ b/src/arm64/amlogic/meson-g12b-khadas-vim3.dtsi @@ -51,11 +51,11 @@ sound { compatible = "amlogic,axg-sound-card"; model = "G12B-KHADAS-VIM3"; - audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", - "TDMOUT_B IN 1", "FRDDR_B OUT 1", - "TDMOUT_B IN 2", "FRDDR_C OUT 1", - "TDM_B Playback", "TDMOUT_B OUT"; + audio-aux-devs = <&tdmout_a>; + audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0", + "TDMOUT_A IN 1", "FRDDR_B OUT 0", + "TDMOUT_A IN 2", "FRDDR_C OUT 0", + "TDM_A Playback", "TDMOUT_A OUT"; assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, @@ -80,7 +80,7 @@ /* 8ch hdmi interface */ dai-link-3 { - sound-dai = <&tdmif_b>; + sound-dai = <&tdmif_a>; dai-format = "i2s"; dai-tdm-slot-tx-mask-0 = <1 1>; dai-tdm-slot-tx-mask-1 = <1 1>; @@ -89,7 +89,7 @@ mclk-fs = <256>; codec { - sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_A>; }; }; @@ -182,11 +182,11 @@ status = "okay"; }; -&tdmif_b { +&tdmif_a { status = "okay"; }; -&tdmout_b { +&tdmout_a { status = "okay"; }; diff --git a/src/arm64/amlogic/meson-g12b-s922x.dtsi b/src/arm64/amlogic/meson-g12b-s922x.dtsi index 046cc332d07f..1e5d0ee5d541 100644 --- a/src/arm64/amlogic/meson-g12b-s922x.dtsi +++ b/src/arm64/amlogic/meson-g12b-s922x.dtsi @@ -65,6 +65,11 @@ opp-hz = /bits/ 64 <1896000000>; opp-microvolt = <981000>; }; + + opp-1992000000 { + opp-hz = /bits/ 64 <1992000000>; + opp-microvolt = <1001000>; + }; }; cpub_opp_table_1: opp-table-1 { @@ -120,5 +125,15 @@ opp-hz = /bits/ 64 <1704000000>; opp-microvolt = <891000>; }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <981000>; + }; + + opp-1908000000 { + opp-hz = /bits/ 64 <1908000000>; + opp-microvolt = <1022000>; + }; }; }; diff --git a/src/arm64/amlogic/meson-g12b-ugoos-am6.dts b/src/arm64/amlogic/meson-g12b-ugoos-am6.dts index 06c5430eb92d..b57bb0befc69 100644 --- a/src/arm64/amlogic/meson-g12b-ugoos-am6.dts +++ b/src/arm64/amlogic/meson-g12b-ugoos-am6.dts @@ -7,42 +7,13 @@ /dts-v1/; -#include "meson-g12b.dtsi" -#include "meson-g12b-s922x.dtsi" -#include -#include +#include "meson-g12b-w400.dtsi" #include / { - compatible = "ugoos,am6", "amlogic,g12b"; + compatible = "ugoos,am6", "amlogic,s922x", "amlogic,g12b"; model = "Ugoos AM6"; - aliases { - serial0 = &uart_AO; - ethernet0 = ðmac; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; - }; - - emmc_pwrseq: emmc-pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; - }; - - sdio_pwrseq: sdio-pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; - clocks = <&wifi32k>; - clock-names = "ext_clock"; - }; - spdif_dit: audio-codec-1 { #sound-dai-cells = <0>; compatible = "linux,spdif-dit"; @@ -50,154 +21,6 @@ sound-name-prefix = "DIT"; }; - flash_1v8: regulator-flash_1v8 { - compatible = "regulator-fixed"; - regulator-name = "FLASH_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - main_12v: regulator-main_12v { - compatible = "regulator-fixed"; - regulator-name = "12V"; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - regulator-always-on; - }; - - vcc_5v: regulator-vcc_5v { - compatible = "regulator-fixed"; - regulator-name = "VCC_5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&main_12v>; - - gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; - enable-active-high; - }; - - vcc_1v8: regulator-vcc_1v8 { - compatible = "regulator-fixed"; - regulator-name = "VCC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc_3v3>; - regulator-always-on; - }; - - vcc_3v3: regulator-vcc_3v3 { - compatible = "regulator-fixed"; - regulator-name = "VCC_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - /* FIXME: actually controlled by VDDCPU_B_EN */ - }; - - vddcpu_a: regulator-vddcpu-a { - /* - * MP1653 Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_A"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_ab 0 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - vddcpu_b: regulator-vddcpu-b { - /* - * MP1652 Regulator. - */ - compatible = "pwm-regulator"; - - regulator-name = "VDDCPU_B"; - regulator-min-microvolt = <721000>; - regulator-max-microvolt = <1022000>; - - vin-supply = <&main_12v>; - - pwms = <&pwm_AO_cd 1 1250 0>; - pwm-dutycycle-range = <100 0>; - - regulator-boot-on; - regulator-always-on; - }; - - usb1_pow: regulator-usb1-pow { - compatible = "regulator-fixed"; - regulator-name = "USB1_POW"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* connected to SY6280A Power Switch */ - gpio = <&gpio GPIOA_8 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - usb_pwr_en: regulator-usb-pwr-en { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR_EN"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc_5v>; - - /* Connected to USB3 Type-A Port power enable */ - gpio = <&gpio GPIOAO_7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vddao_1v8: regulator-vddao-1v8 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vddao_3v3>; - regulator-always-on; - }; - - vddao_3v3: regulator-vddao-3v3 { - compatible = "regulator-fixed"; - regulator-name = "VDDAO_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&main_12v>; - regulator-always-on; - }; - - cvbs-connector { - compatible = "composite-video-connector"; - - port { - cvbs_connector_in: endpoint { - remote-endpoint = <&cvbs_vdac_out>; - }; - }; - }; - - hdmi-connector { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_tmds_out>; - }; - }; - }; - sound { compatible = "amlogic,axg-sound-card"; model = "G12B-UGOOS-AM6"; @@ -277,110 +100,16 @@ }; }; }; - - wifi32k: wifi32k { - compatible = "pwm-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ - }; }; &arb { status = "okay"; }; -&cec_AO { - pinctrl-0 = <&cec_ao_a_h_pins>; - pinctrl-names = "default"; - status = "disabled"; - hdmi-phandle = <&hdmi_tx>; -}; - -&cecb_AO { - pinctrl-0 = <&cec_ao_b_h_pins>; - pinctrl-names = "default"; - status = "okay"; - hdmi-phandle = <&hdmi_tx>; -}; - &clkc_audio { status = "okay"; }; -&cpu0 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu1 { - cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; - clock-latency = <50000>; -}; - -&cpu100 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu101 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu102 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cpu103 { - cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; - clock-latency = <50000>; -}; - -&cvbs_vdac_port { - cvbs_vdac_out: endpoint { - remote-endpoint = <&cvbs_connector_in>; - }; -}; - -&ext_mdio { - external_phy: ethernet-phy@0 { - /* Realtek RTL8211F (0x001cc916) */ - reg = <0>; - max-speed = <1000>; - - reset-assert-us = <10000>; - reset-deassert-us = <30000>; - reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; - - interrupt-parent = <&gpio_intc>; - /* MAC_INTR on GPIOZ_14 */ - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -ðmac { - pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; - pinctrl-names = "default"; - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&external_phy>; - amlogic,tx-delay-ns = <2>; -}; - &frddr_a { status = "okay"; }; @@ -393,112 +122,10 @@ status = "okay"; }; -&hdmi_tx { - status = "okay"; - pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; - pinctrl-names = "default"; - hdmi-supply = <&vcc_5v>; -}; - -&hdmi_tx_tmds_port { - hdmi_tx_tmds_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; -}; - &ir { - status = "okay"; - pinctrl-0 = <&remote_input_ao_pins>; - pinctrl-names = "default"; linux,rc-map-name = "rc-khadas"; }; -&pwm_ab { - pinctrl-0 = <&pwm_a_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -&pwm_AO_cd { - pinctrl-0 = <&pwm_ao_d_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; - status = "okay"; -}; - -&pwm_ef { - pinctrl-0 = <&pwm_e_pins>; - pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; - status = "okay"; -}; - -/* SDIO */ -&sd_emmc_a { - status = "okay"; - pinctrl-0 = <&sdio_pins>; - pinctrl-1 = <&sdio_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - #address-cells = <1>; - #size-cells = <0>; - - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr50; - max-frequency = <100000000>; - - non-removable; - disable-wp; - - mmc-pwrseq = <&sdio_pwrseq>; - - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_1v8>; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; -}; - -/* SD card */ -&sd_emmc_b { - status = "okay"; - pinctrl-0 = <&sdcard_c_pins>; - pinctrl-1 = <&sdcard_clk_gate_c_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <4>; - cap-sd-highspeed; - max-frequency = <50000000>; - disable-wp; - - cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; - vmmc-supply = <&vddao_3v3>; - vqmmc-supply = <&vddao_3v3>; -}; - -/* eMMC */ -&sd_emmc_c { - status = "okay"; - pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; - pinctrl-1 = <&emmc_clk_gate_pins>; - pinctrl-names = "default", "clk-gate"; - - bus-width = <8>; - cap-mmc-highspeed; - max-frequency = <100000000>; - disable-wp; - - mmc-pwrseq = <&emmc_pwrseq>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&flash_1v8>; -}; - &spdifout { pinctrl-0 = <&spdif_out_h_pins>; pinctrl-names = "default"; diff --git a/src/arm64/amlogic/meson-g12b-w400.dtsi b/src/arm64/amlogic/meson-g12b-w400.dtsi new file mode 100644 index 000000000000..98b70d216a6f --- /dev/null +++ b/src/arm64/amlogic/meson-g12b-w400.dtsi @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + * Copyright (c) 2019 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-g12b.dtsi" +#include "meson-g12b-s922x.dtsi" +#include +#include + +/ { + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + flash_1v8: regulator-flash_1v8 { + compatible = "regulator-fixed"; + regulator-name = "FLASH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + main_12v: regulator-main_12v { + compatible = "regulator-fixed"; + regulator-name = "12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + vcc_5v: regulator-vcc_5v { + compatible = "regulator-fixed"; + regulator-name = "VCC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&main_12v>; + + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + }; + + vcc_1v8: regulator-vcc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + /* FIXME: actually controlled by VDDCPU_B_EN */ + }; + + vddcpu_a: regulator-vddcpu-a { + /* + * MP1653 Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU_A"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&main_12v>; + + pwms = <&pwm_ab 0 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vddcpu_b: regulator-vddcpu-b { + /* + * MP1652 Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU_B"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&main_12v>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + usb1_pow: regulator-usb1-pow { + compatible = "regulator-fixed"; + regulator-name = "USB1_POW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* connected to SY6280A Power Switch */ + gpio = <&gpio GPIOA_8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_pwr_en: regulator-usb-pwr-en { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR_EN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* Connected to USB3 Type-A Port power enable */ + gpio = <&gpio GPIOAO_7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vddao_1v8: regulator-vddao-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&main_12v>; + regulator-always-on; + }; + + cvbs-connector { + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; +}; + +&cec_AO { + pinctrl-0 = <&cec_ao_a_h_pins>; + pinctrl-names = "default"; + status = "disabled"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + status = "okay"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cpu0 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu100 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu101 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu102 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu103 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +ðmac { + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; + hdmi-supply = <&vcc_5v>; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&pwm_ab { + pinctrl-0 = <&pwm_a_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; + status = "okay"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +&pwm_ef { + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; + status = "okay"; +}; + +/* SDIO */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr50; + max-frequency = <100000000>; + + non-removable; + disable-wp; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_1v8>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <100000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&flash_1v8>; +}; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; + vbus-supply = <&usb_pwr_en>; +}; + +&usb2_phy0 { + phy-supply = <&usb1_pow>; +}; + +&usb2_phy1 { + phy-supply = <&usb1_pow>; +}; diff --git a/src/arm64/amlogic/meson-g12b.dtsi b/src/arm64/amlogic/meson-g12b.dtsi index 6dbc3968045b..9b8548e5f6e5 100644 --- a/src/arm64/amlogic/meson-g12b.dtsi +++ b/src/arm64/amlogic/meson-g12b.dtsi @@ -113,3 +113,25 @@ compatible = "amlogic,g12b-clkc"; }; +&cpu_thermal { + cooling-maps { + map0 { + trip = <&cpu_passive>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; diff --git a/src/arm64/amlogic/meson-gx-libretech-pc.dtsi b/src/arm64/amlogic/meson-gx-libretech-pc.dtsi index 248b018c83d5..c2480bab8d33 100644 --- a/src/arm64/amlogic/meson-gx-libretech-pc.dtsi +++ b/src/arm64/amlogic/meson-gx-libretech-pc.dtsi @@ -8,6 +8,7 @@ #include #include +#include / { adc-keys { @@ -29,6 +30,13 @@ spi0 = &spifc; }; + dio2133: analog-amplifier { + compatible = "simple-audio-amplifier"; + sound-name-prefix = "AU2"; + VCC-supply = <&vcc5v>; + enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -96,14 +104,14 @@ leds { compatible = "gpio-leds"; - green { + led-green { color = ; function = LED_FUNCTION_DISK_ACTIVITY; gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "disk-activity"; }; - blue { + led-blue { color = ; function = LED_FUNCTION_STATUS; gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; @@ -175,6 +183,69 @@ regulator-settling-time-up-us = <200>; regulator-settling-time-down-us = <50000>; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXL-LIBRETECH-S9XX-PC"; + audio-aux-devs = <&dio2133>; + audio-widgets = "Speaker", "7J4-14 LEFT", + "Speaker", "7J4-11 RIGHT"; + audio-routing = "AU2 INL", "ACODEC LOLN", + "AU2 INR", "ACODEC LORN", + "7J4-14 LEFT", "AU2 OUTL", + "7J4-11 RIGHT", "AU2 OUTR"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + + codec-1 { + sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + + dai-link-3 { + sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; + + codec-0 { + sound-dai = <&acodec>; + }; + }; + }; +}; + +&acodec { + AVDD-supply = <&vddio_ao18>; + status = "okay"; +}; + +&aiu { + status = "okay"; }; &cec_AO { @@ -360,8 +431,9 @@ status = "okay"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; &usb2_phy0 { diff --git a/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi b/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi index 12d5e333e5f2..6b57e15aade3 100644 --- a/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi +++ b/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi @@ -8,12 +8,28 @@ * the pin-compatible S912 (GXM) or S905D (GXL) SoCs. */ +#include + / { aliases { serial0 = &uart_AO; ethernet0 = ðmac; }; + dio2133: analog-amplifier { + compatible = "simple-audio-amplifier"; + sound-name-prefix = "AU2"; + VCC-supply = <&hdmi_5v>; + enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; + }; + + spdif_dit: audio-codec-0 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + sound-name-prefix = "DIT"; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -102,6 +118,85 @@ }; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GX-P230-Q200"; + audio-aux-devs = <&dio2133>; + audio-widgets = "Line", "Lineout"; + audio-routing = "AU2 INL", "ACODEC LOLP", + "AU2 INR", "ACODEC LORP", + "AU2 INL", "ACODEC LOLN", + "AU2 INR", "ACODEC LORN", + "Lineout", "AU2 OUTL", + "Lineout", "AU2 OUTR"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + + codec-1 { + sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; + }; + }; + + dai-link-3 { + sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; + + codec-0 { + sound-dai = <&spdif_dit>; + }; + }; + + dai-link-4 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + + dai-link-5 { + sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; + + codec-0 { + sound-dai = <&acodec>; + }; + }; + }; +}; + +&acodec { + AVDD-supply = <&vddio_ao18>; + status = "okay"; +}; + +&aiu { + status = "okay"; + pinctrl-0 = <&spdif_out_h_pins>; + pinctrl-names = "default"; + }; &cec_AO { @@ -223,6 +318,7 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "otg"; }; diff --git a/src/arm64/amlogic/meson-gx.dtsi b/src/arm64/amlogic/meson-gx.dtsi index 03f79fe045b7..ba63c36b22e0 100644 --- a/src/arm64/amlogic/meson-gx.dtsi +++ b/src/arm64/amlogic/meson-gx.dtsi @@ -278,6 +278,17 @@ #reset-cells = <1>; }; + aiu: audio-controller@5400 { + compatible = "amlogic,aiu"; + #sound-dai-cells = <2>; + sound-name-prefix = "AIU"; + reg = <0x0 0x5400 0x0 0x2ac>; + interrupts = , + ; + interrupt-names = "i2s", "spdif"; + status = "disabled"; + }; + uart_A: serial@84c0 { compatible = "amlogic,meson-gx-uart"; reg = <0x0 0x84c0 0x0 0x18>; @@ -398,20 +409,20 @@ }; sram: sram@c8000000 { - compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram"; + compatible = "mmio-sram"; reg = <0x0 0xc8000000 0x0 0x14000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0xc8000000 0x14000>; - cpu_scp_lpri: scp-shmem@0 { - compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + cpu_scp_lpri: scp-sram@0 { + compatible = "amlogic,meson-gxbb-scp-shmem"; reg = <0x13000 0x400>; }; - cpu_scp_hpri: scp-shmem@200 { - compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; + cpu_scp_hpri: scp-sram@200 { + compatible = "amlogic,meson-gxbb-scp-shmem"; reg = <0x13400 0x400>; }; }; @@ -626,6 +637,8 @@ interrupts = ; #address-cells = <1>; #size-cells = <0>; + #sound-dai-cells = <0>; + sound-name-prefix = "HDMITX"; status = "disabled"; /* VPU VENC Input */ diff --git a/src/arm64/amlogic/meson-gxbb-kii-pro.dts b/src/arm64/amlogic/meson-gxbb-kii-pro.dts index 6c9cc45fb417..e8394a8269ee 100644 --- a/src/arm64/amlogic/meson-gxbb-kii-pro.dts +++ b/src/arm64/amlogic/meson-gxbb-kii-pro.dts @@ -11,7 +11,7 @@ #include #include / { - compatible = "videostrong,kii-pro", "amlogic,p201", "amlogic,s905", "amlogic,meson-gxbb"; + compatible = "videostrong,kii-pro", "amlogic,meson-gxbb"; model = "Videostrong KII Pro"; leds { diff --git a/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts b/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts index d6ca684e0e61..7be3e354093b 100644 --- a/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts +++ b/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts @@ -29,7 +29,7 @@ leds { compatible = "gpio-leds"; - stat { + led-stat { label = "nanopi-k2:blue:stat"; gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; default-state = "on"; diff --git a/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts b/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts index 65ec7dea828c..67d901ed2fa3 100644 --- a/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts @@ -31,7 +31,7 @@ leds { compatible = "gpio-leds"; - blue { + led-blue { label = "a95x:system-status"; gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; diff --git a/src/arm64/amlogic/meson-gxbb-odroidc2.dts b/src/arm64/amlogic/meson-gxbb-odroidc2.dts index b46ef985bb44..70fcfb7b0683 100644 --- a/src/arm64/amlogic/meson-gxbb-odroidc2.dts +++ b/src/arm64/amlogic/meson-gxbb-odroidc2.dts @@ -49,7 +49,7 @@ leds { compatible = "gpio-leds"; - blue { + led-blue { label = "c2:blue:alive"; gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; diff --git a/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi b/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi index 45cb83625951..222ee8069cfa 100644 --- a/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi +++ b/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi @@ -20,7 +20,7 @@ leds { compatible = "gpio-leds"; - blue { + led-blue { label = "vega-s95:blue:on"; gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; default-state = "on"; diff --git a/src/arm64/amlogic/meson-gxbb-wetek-play2.dts b/src/arm64/amlogic/meson-gxbb-wetek-play2.dts index 1d32d1f6d032..2ab8a3d10079 100644 --- a/src/arm64/amlogic/meson-gxbb-wetek-play2.dts +++ b/src/arm64/amlogic/meson-gxbb-wetek-play2.dts @@ -14,13 +14,13 @@ model = "WeTek Play 2"; leds { - wifi { + led-wifi { label = "wetek-play:wifi-status"; gpios = <&gpio GPIODV_26 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - ethernet { + led-ethernet { label = "wetek-play:ethernet-status"; gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/src/arm64/amlogic/meson-gxbb-wetek.dtsi b/src/arm64/amlogic/meson-gxbb-wetek.dtsi index dee51cf95223..ad812854a107 100644 --- a/src/arm64/amlogic/meson-gxbb-wetek.dtsi +++ b/src/arm64/amlogic/meson-gxbb-wetek.dtsi @@ -25,7 +25,7 @@ leds { compatible = "gpio-leds"; - system { + led-system { label = "wetek-play:system-status"; gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>; default-state = "on"; @@ -149,6 +149,10 @@ reset-assert-us = <10000>; reset-deassert-us = <30000>; reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_15 */ + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; }; }; }; diff --git a/src/arm64/amlogic/meson-gxbb.dtsi b/src/arm64/amlogic/meson-gxbb.dtsi index 0cb40326b0d3..234490d3ee68 100644 --- a/src/arm64/amlogic/meson-gxbb.dtsi +++ b/src/arm64/amlogic/meson-gxbb.dtsi @@ -60,6 +60,29 @@ }; }; +&aiu { + compatible = "amlogic,aiu-gxbb", "amlogic,aiu"; + clocks = <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_CTS_AMCLK>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>, + <&clkc CLKID_CTS_MCLK_I958>, + <&clkc CLKID_CTS_I958>; + clock-names = "pclk", + "i2s_pclk", + "i2s_aoclk", + "i2s_mclk", + "i2s_mixer", + "spdif_pclk", + "spdif_aoclk", + "spdif_mclk", + "spdif_mclk_sel"; + resets = <&reset RESET_AIU>; +}; + &aobus { pinctrl_aobus: pinctrl@14 { compatible = "amlogic,meson-gxbb-aobus-pinctrl"; diff --git a/src/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts b/src/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts index 4d5949496596..9e43f4dca90d 100644 --- a/src/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts +++ b/src/arm64/amlogic/meson-gxl-s805x-libretech-ac.dts @@ -8,8 +8,9 @@ /dts-v1/; #include +#include -#include "meson-gxl-s905x.dtsi" +#include "meson-gxl-s805x.dtsi" / { compatible = "libretech,aml-s805x-ac", "amlogic,s805x", @@ -97,6 +98,15 @@ regulator-always-on; }; + vddio_ao18: regulator-vddio_ao18 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + vddio_boot: regulator-vddio_boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; @@ -105,6 +115,66 @@ vin-supply = <&vcc_3v3>; regulator-always-on; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXL-LIBRETECH-S805X-AC"; + audio-widgets = "Speaker", "9J5-3 LEFT", + "Speaker", "9J5-2 RIGHT"; + audio-routing = "9J5-3 LEFT", "ACODEC LOLN", + "9J5-2 RIGHT", "ACODEC LORN"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + + codec-1 { + sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + + dai-link-3 { + sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; + + codec-0 { + sound-dai = <&acodec>; + }; + }; + }; +}; + +&acodec { + AVDD-supply = <&vddio_ao18>; + status = "okay"; +}; + +&aiu { + status = "okay"; }; &cec_AO { @@ -243,6 +313,7 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; diff --git a/src/arm64/amlogic/meson-gxl-s805x-p241.dts b/src/arm64/amlogic/meson-gxl-s805x-p241.dts index a1119cfb0280..eb7f5a3fefd4 100644 --- a/src/arm64/amlogic/meson-gxl-s805x-p241.dts +++ b/src/arm64/amlogic/meson-gxl-s805x-p241.dts @@ -9,7 +9,7 @@ #include -#include "meson-gxl-s905x.dtsi" +#include "meson-gxl-s805x.dtsi" / { compatible = "amlogic,p241", "amlogic,s805x", "amlogic,meson-gxl"; @@ -216,6 +216,7 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; diff --git a/src/arm64/amlogic/meson-gxl-s805x.dtsi b/src/arm64/amlogic/meson-gxl-s805x.dtsi new file mode 100644 index 000000000000..f9d705648426 --- /dev/null +++ b/src/arm64/amlogic/meson-gxl-s805x.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 BayLibre SAS + * Author: Neil Armstrong + */ + +#include "meson-gxl-s905x.dtsi" + +/ { + compatible = "amlogic,s805x", "amlogic,meson-gxl"; +}; + +/* The S805X Package doesn't seem to handle the 744MHz OPP correctly */ +&mali { + assigned-clocks = <&clkc CLKID_MALI_0_SEL>, + <&clkc CLKID_MALI_0>, + <&clkc CLKID_MALI>; /* Glitch free mux */ + assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, + <0>, /* Do Nothing */ + <&clkc CLKID_MALI_0>; + assigned-clock-rates = <0>, /* Do Nothing */ + <666666666>, + <0>; /* Do Nothing */ +}; diff --git a/src/arm64/amlogic/meson-gxl-s905d-phicomm-n1.dts b/src/arm64/amlogic/meson-gxl-s905d-phicomm-n1.dts index b5667f1fb2c8..9ef210f17b4a 100644 --- a/src/arm64/amlogic/meson-gxl-s905d-phicomm-n1.dts +++ b/src/arm64/amlogic/meson-gxl-s905d-phicomm-n1.dts @@ -29,3 +29,7 @@ &cvbs_vdac_port { status = "disabled"; }; + +&usb { + dr_mode = "host"; +}; diff --git a/src/arm64/amlogic/meson-gxl-s905d-sml5442tw.dts b/src/arm64/amlogic/meson-gxl-s905d-sml5442tw.dts new file mode 100644 index 000000000000..0b95e9ecbef0 --- /dev/null +++ b/src/arm64/amlogic/meson-gxl-s905d-sml5442tw.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) Christian Hewitt + */ + +/dts-v1/; + +#include "meson-gxl-s905d.dtsi" +#include "meson-gx-p23x-q20x.dtsi" +#include + +/ { + compatible = "smartlabs,sml5442tw", "amlogic,s905d", "amlogic,meson-gxl"; + model = "SmartLabs SML-5442TW"; + + leds { + compatible = "gpio-leds"; + + yellow { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + blue { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + green { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + red { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio GPIODV_27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +ðmac { + status = "okay"; + phy-mode = "rmii"; + phy-handle = <&internal_phy>; +}; + +&i2c_A { + status = "okay"; + pinctrl-0 = <&i2c_a_pins>; + pinctrl-names = "default"; +}; + +&internal_phy { + pinctrl-0 = <ð_link_led_pins>, <ð_act_led_pins>; + pinctrl-names = "default"; +}; + +/* This is connected to the Bluetooth module: */ +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "qcom,qca9377-bt"; + enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + }; +}; diff --git a/src/arm64/amlogic/meson-gxl-s905w-p281.dts b/src/arm64/amlogic/meson-gxl-s905w-p281.dts index 6509c4950950..ecc9df7ca023 100644 --- a/src/arm64/amlogic/meson-gxl-s905w-p281.dts +++ b/src/arm64/amlogic/meson-gxl-s905w-p281.dts @@ -20,3 +20,7 @@ reg = <0x0 0x0 0x0 0x40000000>; }; }; + +&usb { + dr_mode = "host"; +}; diff --git a/src/arm64/amlogic/meson-gxl-s905w-tx3-mini.dts b/src/arm64/amlogic/meson-gxl-s905w-tx3-mini.dts index dd729ac2300d..6705c2082a78 100644 --- a/src/arm64/amlogic/meson-gxl-s905w-tx3-mini.dts +++ b/src/arm64/amlogic/meson-gxl-s905w-tx3-mini.dts @@ -24,3 +24,7 @@ &ir { linux,rc-map-name = "rc-tanix-tx3mini"; }; + +&usb { + dr_mode = "host"; +}; diff --git a/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts b/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts index 440bc23c7342..8bcdffdf55d0 100644 --- a/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -207,3 +207,7 @@ pinctrl-0 = <&uart_ao_b_pins>; pinctrl-names = "default"; }; + +&usb { + dr_mode = "peripheral"; +}; diff --git a/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts b/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts index e8348b2728db..5ae7bb6209cb 100644 --- a/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/src/arm64/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -8,6 +8,7 @@ /dts-v1/; #include +#include #include "meson-gxl-s905x.dtsi" @@ -21,6 +22,13 @@ ethernet0 = ðmac; }; + dio2133: analog-amplifier { + compatible = "simple-audio-amplifier"; + sound-name-prefix = "AU2"; + VCC-supply = <&hdmi_5v>; + enable-gpios = <&gpio GPIOH_5 GPIO_ACTIVE_HIGH>; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -54,14 +62,14 @@ leds { compatible = "gpio-leds"; - system { + led-system { label = "librecomputer:system-status"; gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>; default-state = "on"; panic-indicator; }; - blue { + led-blue { label = "librecomputer:blue"; gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -124,6 +132,68 @@ regulator-max-microvolt = <1800000>; vin-supply = <&vcc_3v3>; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "GXL-LIBRETECH-S905X-CC"; + audio-aux-devs = <&dio2133>; + audio-widgets = "Line", "Lineout"; + audio-routing = "AU2 INL", "ACODEC LOLN", + "AU2 INR", "ACODEC LORN", + "Lineout", "AU2 OUTL", + "Lineout", "AU2 OUTR"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + + codec-1 { + sound-dai = <&aiu AIU_ACODEC CTRL_I2S>; + }; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + + dai-link-3 { + sound-dai = <&aiu AIU_ACODEC CTRL_OUT>; + + codec-0 { + sound-dai = <&acodec>; + }; + }; + }; +}; + +&acodec { + AVDD-supply = <&vddio_ao18>; + status = "okay"; +}; + +&aiu { + status = "okay"; }; &cec_AO { @@ -272,8 +342,9 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; &usb2_phy0 { diff --git a/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts index 62dd87821ce5..f1acca5c4434 100644 --- a/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts +++ b/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts @@ -218,6 +218,7 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; diff --git a/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi b/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi index 6ac678f88bd8..05cb2f5e5c36 100644 --- a/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi +++ b/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi @@ -195,8 +195,9 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; &usb2_phy0 { diff --git a/src/arm64/amlogic/meson-gxl.dtsi b/src/arm64/amlogic/meson-gxl.dtsi index 259d86399390..6c8b189884ca 100644 --- a/src/arm64/amlogic/meson-gxl.dtsi +++ b/src/arm64/amlogic/meson-gxl.dtsi @@ -14,29 +14,57 @@ compatible = "amlogic,meson-gxl"; soc { - usb0: usb@c9000000 { - status = "disabled"; - compatible = "amlogic,meson-gxl-dwc3"; + usb: usb@d0078080 { + compatible = "amlogic,meson-gxl-usb-ctrl"; + reg = <0x0 0xd0078080 0x0 0x20>; + interrupts = ; #address-cells = <2>; #size-cells = <2>; ranges; - clocks = <&clkc CLKID_USB>; - clock-names = "usb_general"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "usb_ctrl", "ddr"; resets = <&reset RESET_USB_OTG>; - reset-names = "usb_otg"; - dwc3: dwc3@c9000000 { + dr_mode = "otg"; + + phys = <&usb2_phy0>, <&usb2_phy1>; + phy-names = "usb2-phy0", "usb2-phy1"; + + dwc2: usb@c9100000 { + compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; + reg = <0x0 0xc9100000 0x0 0x40000>; + interrupts = ; + clocks = <&clkc CLKID_USB1>; + clock-names = "otg"; + phys = <&usb2_phy1>; + dr_mode = "peripheral"; + g-rx-fifo-size = <192>; + g-np-tx-fifo-size = <128>; + g-tx-fifo-size = <128 128 16 16 16>; + }; + + dwc3: usb@c9000000 { compatible = "snps,dwc3"; reg = <0x0 0xc9000000 0x0 0x100000>; interrupts = ; dr_mode = "host"; maximum-speed = "high-speed"; snps,dis_u2_susphy_quirk; - phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>; }; }; + acodec: audio-controller@c8832000 { + compatible = "amlogic,t9015"; + reg = <0x0 0xc8832000 0x0 0x14>; + #sound-dai-cells = <0>; + sound-name-prefix = "ACODEC"; + clocks = <&clkc CLKID_ACODEC>; + clock-names = "pclk"; + resets = <&reset RESET_ACODEC>; + status = "disabled"; + }; + crypto: crypto@c883e000 { compatible = "amlogic,gxl-crypto"; reg = <0x0 0xc883e000 0x0 0x36>; @@ -49,6 +77,29 @@ }; }; +&aiu { + compatible = "amlogic,aiu-gxl", "amlogic,aiu"; + clocks = <&clkc CLKID_AIU_GLUE>, + <&clkc CLKID_I2S_OUT>, + <&clkc CLKID_AOCLK_GATE>, + <&clkc CLKID_CTS_AMCLK>, + <&clkc CLKID_MIXER_IFACE>, + <&clkc CLKID_IEC958>, + <&clkc CLKID_IEC958_GATE>, + <&clkc CLKID_CTS_MCLK_I958>, + <&clkc CLKID_CTS_I958>; + clock-names = "pclk", + "i2s_pclk", + "i2s_aoclk", + "i2s_mclk", + "i2s_mixer", + "spdif_pclk", + "spdif_aoclk", + "spdif_mclk", + "spdif_mclk_sel"; + resets = <&reset RESET_AIU>; +}; + &apb { usb2_phy0: phy@78000 { compatible = "amlogic,meson-gxl-usb2-phy"; @@ -71,18 +122,6 @@ reset-names = "phy"; status = "okay"; }; - - usb3_phy: phy@78080 { - compatible = "amlogic,meson-gxl-usb3-phy"; - #phy-cells = <0>; - reg = <0x0 0x78080 0x0 0x20>; - interrupts = ; - clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>; - clock-names = "phy", "peripheral"; - resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>; - reset-names = "phy", "peripheral"; - status = "okay"; - }; }; &efuse { @@ -298,6 +337,11 @@ }; }; +&hwrng { + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + &i2c_A { clocks = <&clkc CLKID_I2C>; }; diff --git a/src/arm64/amlogic/meson-gxm-khadas-vim2.dts b/src/arm64/amlogic/meson-gxm-khadas-vim2.dts index 27eeab71ec77..bff8ec2c1c70 100644 --- a/src/arm64/amlogic/meson-gxm-khadas-vim2.dts +++ b/src/arm64/amlogic/meson-gxm-khadas-vim2.dts @@ -380,6 +380,7 @@ vref-supply = <&vddio_ao18>; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "peripheral"; }; diff --git a/src/arm64/amlogic/meson-gxm-nexbox-a1.dts b/src/arm64/amlogic/meson-gxm-nexbox-a1.dts index c2bd4dbbf38c..83eca3af44ce 100644 --- a/src/arm64/amlogic/meson-gxm-nexbox-a1.dts +++ b/src/arm64/amlogic/meson-gxm-nexbox-a1.dts @@ -179,6 +179,7 @@ pinctrl-names = "default"; }; -&usb0 { +&usb { status = "okay"; + dr_mode = "host"; }; diff --git a/src/arm64/amlogic/meson-gxm-rbox-pro.dts b/src/arm64/amlogic/meson-gxm-rbox-pro.dts index 420a88e9a195..c89c9f846fb1 100644 --- a/src/arm64/amlogic/meson-gxm-rbox-pro.dts +++ b/src/arm64/amlogic/meson-gxm-rbox-pro.dts @@ -36,13 +36,13 @@ leds { compatible = "gpio-leds"; - blue { + led-blue { label = "rbox-pro:blue:on"; gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>; default-state = "on"; }; - red { + led-red { label = "rbox-pro:red:standby"; gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/src/arm64/amlogic/meson-gxm-vega-s96.dts b/src/arm64/amlogic/meson-gxm-vega-s96.dts index 0bdf51d041ae..d3fdba4da9a6 100644 --- a/src/arm64/amlogic/meson-gxm-vega-s96.dts +++ b/src/arm64/amlogic/meson-gxm-vega-s96.dts @@ -39,3 +39,7 @@ &ir { linux,rc-map-name = "rc-vega-s9x"; }; + +&usb { + dr_mode = "host"; +}; diff --git a/src/arm64/amlogic/meson-gxm.dtsi b/src/arm64/amlogic/meson-gxm.dtsi index b6f89f108e28..40e3e123e05b 100644 --- a/src/arm64/amlogic/meson-gxm.dtsi +++ b/src/arm64/amlogic/meson-gxm.dtsi @@ -169,8 +169,11 @@ compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; }; -&dwc3 { - phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>; +&usb { + compatible = "amlogic,meson-gxm-usb-ctrl"; + + phy-names = "usb2-phy0", "usb2-phy1", "usb2-phy2"; + phys = <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>; }; &vdec { diff --git a/src/arm64/amlogic/meson-khadas-vim3.dtsi b/src/arm64/amlogic/meson-khadas-vim3.dtsi index 094ecf2222bb..1ef1e3672b96 100644 --- a/src/arm64/amlogic/meson-khadas-vim3.dtsi +++ b/src/arm64/amlogic/meson-khadas-vim3.dtsi @@ -39,13 +39,13 @@ leds { compatible = "gpio-leds"; - white { + led-white { label = "vim3:white:sys"; gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; - red { + led-red { label = "vim3:red"; gpios = <&gpio_expander 5 GPIO_ACTIVE_LOW>; }; diff --git a/src/arm64/amlogic/meson-sm1-odroid-c4.dts b/src/arm64/amlogic/meson-sm1-odroid-c4.dts new file mode 100644 index 000000000000..00d90b30f8b4 --- /dev/null +++ b/src/arm64/amlogic/meson-sm1-odroid-c4.dts @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Dongjin Kim + */ + +/dts-v1/; + +#include "meson-sm1.dtsi" +#include +#include + +/ { + compatible = "hardkernel,odroid-c4", "amlogic,sm1"; + model = "Hardkernel ODROID-C4"; + + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + panic-indicator; + }; + }; + + tflash_vdd: regulator-tflash_vdd { + compatible = "regulator-fixed"; + + regulator-name = "TFLASH_VDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + tf_io: gpio-regulator-tf_io { + compatible = "regulator-gpio"; + + regulator-name = "TF_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + + states = <3300000 0>, + <1800000 1>; + }; + + flash_1v8: regulator-flash_1v8 { + compatible = "regulator-fixed"; + regulator-name = "FLASH_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + main_12v: regulator-main_12v { + compatible = "regulator-fixed"; + regulator-name = "12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + vcc_5v: regulator-vcc_5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&main_12v>; + }; + + vcc_1v8: regulator-vcc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + /* FIXME: actually controlled by VDDCPU_B_EN */ + }; + + vddcpu: regulator-vddcpu { + /* + * MP8756GD Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <721000>; + regulator-max-microvolt = <1022000>; + + vin-supply = <&main_12v>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + hub_5v: regulator-hub_5v { + compatible = "regulator-fixed"; + regulator-name = "HUB_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* Connected to the Hub CHIPENABLE, LOW sets low power state */ + gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_pwr_en: regulator-usb_pwr_en { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR_EN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + /* Connected to the microUSB port power enable */ + gpio = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vddao_1v8: regulator-vddao_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&main_12v>; + regulator-always-on; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU1_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU2_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU3_CLK>; + clock-latency = <50000>; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +ðmac { + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; +}; + +&gpio { + gpio-line-names = + /* GPIOZ */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* GPIOH */ + "", "", "", "", "", + "PIN_36", /* GPIOH_5 */ + "PIN_26", /* GPIOH_6 */ + "PIN_32", /* GPIOH_7 */ + "", + /* BOOT */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* GPIOC */ + "", "", "", "", "", "", "", "", + /* GPIOA */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", + "PIN_27", /* GPIOA_14 */ + "PIN_28", /* GPIOA_15 */ + /* GPIOX */ + "PIN_16", /* GPIOX_0 */ + "PIN_18", /* GPIOX_1 */ + "PIN_22", /* GPIOX_2 */ + "PIN_11", /* GPIOX_3 */ + "PIN_13", /* GPIOX_4 */ + "PIN_7", /* GPIOX_5 */ + "PIN_33", /* GPIOX_6 */ + "PIN_15", /* GPIOX_7 */ + "PIN_19", /* GPIOX_8 */ + "PIN_21", /* GPIOX_9 */ + "PIN_24", /* GPIOX_10 */ + "PIN_23", /* GPIOX_11 */ + "PIN_8", /* GPIOX_12 */ + "PIN_10", /* GPIOX_13 */ + "PIN_29", /* GPIOX_14 */ + "PIN_31", /* GPIOX_15 */ + "PIN_12", /* GPIOX_16 */ + "PIN_3", /* GPIOX_17 */ + "PIN_5", /* GPIOX_18 */ + "PIN_35"; /* GPIOX_19 */ + + /* + * WARNING: The USB Hub on the Odroid-C4 needs a reset signal + * to be turned high in order to be detected by the USB Controller + * This signal should be handled by a USB specific power sequence + * in order to reset the Hub when USB bus is powered down. + */ + usb-hub { + gpio-hog; + gpios = ; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&gpio_ao { + gpio-line-names = + /* GPIOAO */ + "", "", "", "", + "PIN_47", /* GPIOAO_4 */ + "", "", + "PIN_45", /* GPIOAO_7 */ + "PIN_46", /* GPIOAO_8 */ + "PIN_44", /* GPIOAO_9 */ + "PIN_42", /* GPIOAO_10 */ + "", + /* GPIOE */ + "", "", ""; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; + hdmi-supply = <&vcc_5v>; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; + linux,rc-map-name = "rc-odroid"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <200000000>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&tflash_vdd>; + vqmmc-supply = <&tf_io>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&flash_1v8>; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + vbus-supply = <&usb_pwr_en>; +}; + +&usb2_phy0 { + phy-supply = <&vcc_5v>; +}; + +&usb2_phy1 { + /* Enable the hub which is connected to this port */ + phy-supply = <&hub_5v>; +}; diff --git a/src/arm64/amlogic/meson-sm1-sei610.dts b/src/arm64/amlogic/meson-sm1-sei610.dts index dfb2438851c0..5ab139a34c01 100644 --- a/src/arm64/amlogic/meson-sm1-sei610.dts +++ b/src/arm64/amlogic/meson-sm1-sei610.dts @@ -104,7 +104,7 @@ leds { compatible = "gpio-leds"; - bluetooth { + led-bluetooth { label = "sei610:blue:bt"; gpios = <&gpio GPIOC_7 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; default-state = "off"; diff --git a/src/arm64/amlogic/meson-sm1.dtsi b/src/arm64/amlogic/meson-sm1.dtsi index d4ec735fb1a5..71317f5aada1 100644 --- a/src/arm64/amlogic/meson-sm1.dtsi +++ b/src/arm64/amlogic/meson-sm1.dtsi @@ -56,6 +56,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -64,6 +65,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -72,6 +74,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -80,6 +83,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; l2: l2-cache0 { @@ -466,6 +470,26 @@ compatible = "amlogic,sm1-clkc"; }; +&cpu_thermal { + cooling-maps { + map0 { + trip = <&cpu_passive>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&cpu_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + ðmac { power-domains = <&pwrc PWRC_SM1_ETH_ID>; }; diff --git a/src/arm64/arm/foundation-v8-gicv2.dtsi b/src/arm64/arm/foundation-v8-gicv2.dtsi index 15fe81738e94..655fdcce1561 100644 --- a/src/arm64/arm/foundation-v8-gicv2.dtsi +++ b/src/arm64/arm/foundation-v8-gicv2.dtsi @@ -6,9 +6,9 @@ / { gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; - #address-cells = <2>; + #address-cells = <1>; interrupt-controller; reg = <0x0 0x2c001000 0 0x1000>, <0x0 0x2c002000 0 0x2000>, diff --git a/src/arm64/arm/foundation-v8-gicv3.dtsi b/src/arm64/arm/foundation-v8-gicv3.dtsi index f2c75c756039..e4a3c7dbcc20 100644 --- a/src/arm64/arm/foundation-v8-gicv3.dtsi +++ b/src/arm64/arm/foundation-v8-gicv3.dtsi @@ -8,9 +8,9 @@ gic: interrupt-controller@2f000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x2f000000 0x100000>; interrupt-controller; reg = <0x0 0x2f000000 0x0 0x10000>, <0x0 0x2f100000 0x0 0x200000>, @@ -19,10 +19,11 @@ <0x0 0x2c02f000 0x0 0x2000>; interrupts = ; - its: its@2f020000 { + its: msi-controller@2f020000 { compatible = "arm,gic-v3-its"; msi-controller; - reg = <0x0 0x2f020000 0x0 0x20000>; + #msi-cells = <1>; + reg = <0x20000 0x20000>; }; }; }; diff --git a/src/arm64/arm/foundation-v8.dtsi b/src/arm64/arm/foundation-v8.dtsi index 12f039fa3dad..05ae893d1b2e 100644 --- a/src/arm64/arm/foundation-v8.dtsi +++ b/src/arm64/arm/foundation-v8.dtsi @@ -92,6 +92,27 @@ timeout-sec = <30>; }; + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + bus@8000000 { compatible = "arm,vexpress,v2m-p1", "simple-bus"; arm,v2m-memory-map = "rs1"; @@ -107,78 +128,57 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, - <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, - <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, - <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, - <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, - <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, - <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, - <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, - <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, - <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, - <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, - <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, - <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, - <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, - <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, - <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, + <0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - ethernet@2,02000000 { + ethernet@202000000 { compatible = "smsc,lan91c111"; reg = <2 0x02000000 0x10000>; interrupts = <15>; }; - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - iofpga@3,00000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -189,7 +189,7 @@ reg = <0x010000 0x1000>; }; - v2m_serial0: uart@90000 { + v2m_serial0: serial@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -197,7 +197,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@a0000 { + v2m_serial1: serial@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -205,7 +205,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@b0000 { + v2m_serial2: serial@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -213,7 +213,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@c0000 { + v2m_serial3: serial@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; diff --git a/src/arm64/arm/fvp-base-revc.dts b/src/arm64/arm/fvp-base-revc.dts index 66381d89c1ce..b8a21092db4d 100644 --- a/src/arm64/arm/fvp-base-revc.dts +++ b/src/arm64/arm/fvp-base-revc.dts @@ -126,7 +126,7 @@ <0x0 0x2c02f000 0 0x2000>; // GICV interrupts = ; - its: its@2f020000 { + its: msi-controller@2f020000 { #msi-cells = <1>; compatible = "arm,gic-v3-its"; reg = <0x0 0x2f020000 0x0 0x20000>; // GITS @@ -172,14 +172,14 @@ dma-coherent; }; - smmu: smmu@2b400000 { + smmu: iommu@2b400000 { compatible = "arm,smmu-v3"; reg = <0x0 0x2b400000 0x0 0x100000>; interrupts = , + , , - , - ; - interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; dma-coherent; #iommu-cells = <1>; msi-parent = <&its 0x10000>; diff --git a/src/arm64/arm/juno-base.dtsi b/src/arm64/arm/juno-base.dtsi index f5889281545f..f6c55877fbd9 100644 --- a/src/arm64/arm/juno-base.dtsi +++ b/src/arm64/arm/juno-base.dtsi @@ -11,14 +11,14 @@ compatible = "arm,armv7-timer-mem"; reg = <0x0 0x2a810000 0x0 0x10000>; clock-frequency = <50000000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x2a820000 0x20000>; status = "disabled"; frame@2a830000 { frame-number = <1>; interrupts = ; - reg = <0x0 0x2a830000 0x0 0x10000>; + reg = <0x10000 0x10000>; }; }; @@ -74,35 +74,35 @@ <0x0 0x2c02f000 0 0x2000>, <0x0 0x2c04f000 0 0x2000>, <0x0 0x2c06f000 0 0x2000>; - #address-cells = <2>; + #address-cells = <1>; #interrupt-cells = <3>; - #size-cells = <2>; + #size-cells = <1>; interrupt-controller; interrupts = ; - ranges = <0 0 0 0x2c1c0000 0 0x40000>; + ranges = <0 0 0x2c1c0000 0x40000>; v2m_0: v2m@0 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0 0 0 0x10000>; + reg = <0 0x10000>; }; v2m@10000 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0 0x10000 0 0x10000>; + reg = <0x10000 0x10000>; }; v2m@20000 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0 0x20000 0 0x10000>; + reg = <0x20000 0x10000>; }; v2m@30000 { compatible = "arm,gic-v2m-frame"; msi-controller; - reg = <0 0x30000 0 0x10000>; + reg = <0x30000 0x10000>; }; }; @@ -501,10 +501,10 @@ gpu: gpu@2d000000 { compatible = "arm,juno-mali", "arm,mali-t624"; reg = <0 0x2d000000 0 0x10000>; - interrupts = , - , - ; - interrupt-names = "gpu", "job", "mmu"; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; clocks = <&scpi_dvfs 2>; power-domains = <&scpi_devpd 1>; dma-coherent; @@ -521,12 +521,12 @@ #size-cells = <1>; ranges = <0 0x0 0x2e000000 0x8000>; - cpu_scp_lpri: scp-shmem@0 { + cpu_scp_lpri: scp-sram@0 { compatible = "arm,juno-scp-shmem"; reg = <0x0 0x200>; }; - cpu_scp_hpri: scp-shmem@200 { + cpu_scp_hpri: scp-sram@200 { compatible = "arm,juno-scp-shmem"; reg = <0x200 0x200>; }; @@ -546,10 +546,10 @@ <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic 0 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic 0 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic 0 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; msi-parent = <&v2m_0>; status = "disabled"; iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ @@ -729,7 +729,7 @@ }; }; - soc_uart0: uart@7ff80000 { + soc_uart0: serial@7ff80000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0x7ff80000 0x0 0x1000>; interrupts = ; @@ -768,7 +768,7 @@ }; }; - ohci@7ffb0000 { + usb@7ffb0000 { compatible = "generic-ohci"; reg = <0x0 0x7ffb0000 0x0 0x10000>; interrupts = ; @@ -776,7 +776,7 @@ clocks = <&soc_usb48mhz>; }; - ehci@7ffc0000 { + usb@7ffc0000 { compatible = "generic-ehci"; reg = <0x0 0x7ffc0000 0x0 0x10000>; interrupts = ; @@ -813,28 +813,28 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 15>; - interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, - <0 0 1 &gic 0 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <0 0 2 &gic 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <0 0 3 &gic 0 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, - <0 0 4 &gic 0 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <0 0 5 &gic 0 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <0 0 6 &gic 0 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, - <0 0 7 &gic 0 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, - <0 0 8 &gic 0 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, - <0 0 9 &gic 0 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, - <0 0 10 &gic 0 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, - <0 0 11 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, - <0 0 12 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; }; - site2: tlx@60000000 { + site2: tlx-bus@60000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0x60000000 0x10000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0>; - interrupt-map = <0 0 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/src/arm64/arm/juno-motherboard.dtsi b/src/arm64/arm/juno-motherboard.dtsi index e3983ded3c3c..eeee51f1251b 100644 --- a/src/arm64/arm/juno-motherboard.dtsi +++ b/src/arm64/arm/juno-motherboard.dtsi @@ -8,36 +8,91 @@ */ / { + mb_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "juno_mb:clk24mhz"; + }; + + mb_clk25mhz: clk25mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "juno_mb:clk25mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "juno_mb:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "juno_mb:refclk32khz"; + }; + + mb_fixed_3v3: mcc-sb-3v3 { + compatible = "regulator-fixed"; + regulator-name = "MCC_SB_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + + power-button { + debounce-interval = <50>; + wakeup-source; + linux,code = <116>; + label = "POWER"; + gpios = <&iofpga_gpio0 0 0x4>; + }; + home-button { + debounce-interval = <50>; + wakeup-source; + linux,code = <102>; + label = "HOME"; + gpios = <&iofpga_gpio0 1 0x4>; + }; + rlock-button { + debounce-interval = <50>; + wakeup-source; + linux,code = <152>; + label = "RLOCK"; + gpios = <&iofpga_gpio0 2 0x4>; + }; + vol-up-button { + debounce-interval = <50>; + wakeup-source; + linux,code = <115>; + label = "VOL+"; + gpios = <&iofpga_gpio0 3 0x4>; + }; + vol-down-button { + debounce-interval = <50>; + wakeup-source; + linux,code = <114>; + label = "VOL-"; + gpios = <&iofpga_gpio0 4 0x4>; + }; + nmi-button { + debounce-interval = <50>; + wakeup-source; + linux,code = <99>; + label = "NMI"; + gpios = <&iofpga_gpio0 5 0x4>; + }; + }; + bus@8000000 { - mb_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "juno_mb:clk24mhz"; - }; - - mb_clk25mhz: clk25mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "juno_mb:clk25mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "juno_mb:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "juno_mb:refclk32khz"; - }; - - motherboard { + motherboard-bus { compatible = "arm,vexpress,v2p-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ #size-cells = <1>; @@ -48,62 +103,7 @@ arm,vexpress,site = <0>; arm,v2m-memory-map = "rs1"; - mb_fixed_3v3: mcc-sb-3v3 { - compatible = "regulator-fixed"; - regulator-name = "MCC_SB_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <116>; - label = "POWER"; - gpios = <&iofpga_gpio0 0 0x4>; - }; - home-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <102>; - label = "HOME"; - gpios = <&iofpga_gpio0 1 0x4>; - }; - rlock-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <152>; - label = "RLOCK"; - gpios = <&iofpga_gpio0 2 0x4>; - }; - vol-up-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <115>; - label = "VOL+"; - gpios = <&iofpga_gpio0 3 0x4>; - }; - vol-down-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <114>; - label = "VOL-"; - gpios = <&iofpga_gpio0 4 0x4>; - }; - nmi-button { - debounce-interval = <50>; - wakeup-source; - linux,code = <99>; - label = "NMI"; - gpios = <&iofpga_gpio0 5 0x4>; - }; - }; - - flash@0,00000000 { + flash@0 { /* 2 * 32MiB NOR Flash memory mounted on CS0 */ compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>; @@ -120,7 +120,7 @@ }; }; - ethernet@2,00000000 { + ethernet@200000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <2 0x00000000 0x10000>; interrupts = <3>; @@ -133,7 +133,7 @@ vddvario-supply = <&mb_fixed_3v3>; }; - iofpga@3,00000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/src/arm64/arm/rtsm_ve-aemv8a.dts b/src/arm64/arm/rtsm_ve-aemv8a.dts index c5d15cbd8cf6..3050f45bade4 100644 --- a/src/arm64/arm/rtsm_ve-aemv8a.dts +++ b/src/arm64/arm/rtsm_ve-aemv8a.dts @@ -95,7 +95,7 @@ }; gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; diff --git a/src/arm64/arm/rtsm_ve-motherboard-rs2.dtsi b/src/arm64/arm/rtsm_ve-motherboard-rs2.dtsi index 60703b5763c6..b917d9d3f1c4 100644 --- a/src/arm64/arm/rtsm_ve-motherboard-rs2.dtsi +++ b/src/arm64/arm/rtsm_ve-motherboard-rs2.dtsi @@ -6,10 +6,10 @@ */ / { bus@8000000 { - motherboard { + motherboard-bus { arm,v2m-memory-map = "rs2"; - iofpga@3,00000000 { + iofpga-bus@300000000 { virtio-p9@140000 { compatible = "virtio,mmio"; reg = <0x140000 0x200>; diff --git a/src/arm64/arm/rtsm_ve-motherboard.dtsi b/src/arm64/arm/rtsm_ve-motherboard.dtsi index e333c8d2d0e4..001a0a3c7f66 100644 --- a/src/arm64/arm/rtsm_ve-motherboard.dtsi +++ b/src/arm64/arm/rtsm_ve-motherboard.dtsi @@ -8,8 +8,76 @@ * VEMotherBoard.lisa */ / { + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + v2m_fixed_3v3: v2m-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + bus@8000000 { - motherboard { + motherboard-bus { arm,v2m-memory-map = "rs1"; compatible = "arm,vexpress,v2m-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ @@ -17,41 +85,20 @@ #interrupt-cells = <1>; ranges; - flash@0,00000000 { + flash@0 { compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>, <4 0x00000000 0x04000000>; bank-width = <4>; }; - ethernet@2,02000000 { + ethernet@202000000 { compatible = "smsc,lan91c111"; reg = <2 0x02000000 0x10000>; interrupts = <15>; }; - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; - - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; - - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; - - iofpga@3,00000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -111,7 +158,7 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - v2m_serial0: uart@90000 { + v2m_serial0: serial@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -119,7 +166,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@a0000 { + v2m_serial1: serial@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -127,7 +174,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@b0000 { + v2m_serial2: serial@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -135,7 +182,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@c0000 { + v2m_serial3: serial@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; @@ -198,53 +245,6 @@ }; }; }; - - v2m_fixed_3v3: v2m-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 63500000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; - }; }; }; }; diff --git a/src/arm64/arm/vexpress-v2m-rs1.dtsi b/src/arm64/arm/vexpress-v2m-rs1.dtsi index 5c183483ec3b..a88ee5294d35 100644 --- a/src/arm64/arm/vexpress-v2m-rs1.dtsi +++ b/src/arm64/arm/vexpress-v2m-rs1.dtsi @@ -19,8 +19,89 @@ */ / { + v2m_fixed_3v3: fixed-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + label = "v2m:green:user1"; + gpios = <&v2m_led_gpios 0 0>; + linux,default-trigger = "heartbeat"; + }; + + led-2 { + label = "v2m:green:user2"; + gpios = <&v2m_led_gpios 1 0>; + linux,default-trigger = "disk-activity"; + }; + + led-3 { + label = "v2m:green:user3"; + gpios = <&v2m_led_gpios 2 0>; + linux,default-trigger = "cpu0"; + }; + + led-4 { + label = "v2m:green:user4"; + gpios = <&v2m_led_gpios 3 0>; + linux,default-trigger = "cpu1"; + }; + + led-5 { + label = "v2m:green:user5"; + gpios = <&v2m_led_gpios 4 0>; + linux,default-trigger = "cpu2"; + }; + + led-6 { + label = "v2m:green:user6"; + gpios = <&v2m_led_gpios 5 0>; + linux,default-trigger = "cpu3"; + }; + + led-7 { + label = "v2m:green:user7"; + gpios = <&v2m_led_gpios 6 0>; + linux,default-trigger = "cpu4"; + }; + + led-8 { + label = "v2m:green:user8"; + gpios = <&v2m_led_gpios 7 0>; + linux,default-trigger = "cpu5"; + }; + }; + bus@8000000 { - motherboard { + motherboard-bus { model = "V2M-P1"; arm,hbi = <0x190>; arm,vexpress,site = <0>; @@ -31,7 +112,7 @@ #interrupt-cells = <1>; ranges; - nor_flash: flash@0,00000000 { + nor_flash: flash@0 { compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>, <4 0x00000000 0x04000000>; @@ -41,13 +122,13 @@ }; }; - psram@1,00000000 { + psram@100000000 { compatible = "arm,vexpress-psram", "mtd-ram"; reg = <1 0x00000000 0x02000000>; bank-width = <4>; }; - ethernet@2,02000000 { + ethernet@202000000 { compatible = "smsc,lan9118", "smsc,lan9115"; reg = <2 0x02000000 0x10000>; interrupts = <15>; @@ -59,14 +140,14 @@ vddvario-supply = <&v2m_fixed_3v3>; }; - usb@2,03000000 { + usb@203000000 { compatible = "nxp,usb-isp1761"; reg = <2 0x03000000 0x20000>; interrupts = <16>; port1-otg; }; - iofpga@3,00000000 { + iofpga-bus@300000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -162,7 +243,7 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - v2m_serial0: uart@90000 { + v2m_serial0: serial@90000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; @@ -170,7 +251,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@a0000 { + v2m_serial1: serial@a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; @@ -178,7 +259,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@b0000 { + v2m_serial2: serial@b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; @@ -186,7 +267,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@c0000 { + v2m_serial3: serial@c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; @@ -281,159 +362,78 @@ }; }; }; - }; - v2m_fixed_3v3: fixed-regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + mcc { + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; - v2m_clk24mhz: clk24mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "v2m:clk24mhz"; - }; + oscclk0 { + /* MCC static memory clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 0>; + freq-range = <25000000 60000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk0"; + }; - v2m_refclk1mhz: refclk1mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1000000>; - clock-output-names = "v2m:refclk1mhz"; - }; + v2m_oscclk1: oscclk1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 65000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; - v2m_refclk32khz: refclk32khz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "v2m:refclk32khz"; - }; + v2m_oscclk2: oscclk2 { + /* IO FPGA peripheral clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 2>; + freq-range = <24000000 24000000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk2"; + }; - leds { - compatible = "gpio-leds"; + volt-vio { + /* Logic level voltage */ + compatible = "arm,vexpress-volt"; + arm,vexpress-sysreg,func = <2 0>; + regulator-name = "VIO"; + regulator-always-on; + label = "VIO"; + }; - user1 { - label = "v2m:green:user1"; - gpios = <&v2m_led_gpios 0 0>; - linux,default-trigger = "heartbeat"; - }; + temp-mcc { + /* MCC internal operating temperature */ + compatible = "arm,vexpress-temp"; + arm,vexpress-sysreg,func = <4 0>; + label = "MCC"; + }; - user2 { - label = "v2m:green:user2"; - gpios = <&v2m_led_gpios 1 0>; - linux,default-trigger = "mmc0"; - }; + reset { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; - user3 { - label = "v2m:green:user3"; - gpios = <&v2m_led_gpios 2 0>; - linux,default-trigger = "cpu0"; - }; + muxfpga { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; - user4 { - label = "v2m:green:user4"; - gpios = <&v2m_led_gpios 3 0>; - linux,default-trigger = "cpu1"; - }; + shutdown { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; - user5 { - label = "v2m:green:user5"; - gpios = <&v2m_led_gpios 4 0>; - linux,default-trigger = "cpu2"; - }; + reboot { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; - user6 { - label = "v2m:green:user6"; - gpios = <&v2m_led_gpios 5 0>; - linux,default-trigger = "cpu3"; - }; - - user7 { - label = "v2m:green:user7"; - gpios = <&v2m_led_gpios 6 0>; - linux,default-trigger = "cpu4"; - }; - - user8 { - label = "v2m:green:user8"; - gpios = <&v2m_led_gpios 7 0>; - linux,default-trigger = "cpu5"; - }; - }; - - mcc { - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - - oscclk0 { - /* MCC static memory clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 0>; - freq-range = <25000000 60000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk0"; - }; - - v2m_oscclk1: oscclk1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 65000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk1"; - }; - - v2m_oscclk2: oscclk2 { - /* IO FPGA peripheral clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 2>; - freq-range = <24000000 24000000>; - #clock-cells = <0>; - clock-output-names = "v2m:oscclk2"; - }; - - volt-vio { - /* Logic level voltage */ - compatible = "arm,vexpress-volt"; - arm,vexpress-sysreg,func = <2 0>; - regulator-name = "VIO"; - regulator-always-on; - label = "VIO"; - }; - - temp-mcc { - /* MCC internal operating temperature */ - compatible = "arm,vexpress-temp"; - arm,vexpress-sysreg,func = <4 0>; - label = "MCC"; - }; - - reset { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - - muxfpga { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - - shutdown { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - - reboot { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - - dvimode { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; + dvimode { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; }; }; }; diff --git a/src/arm64/freescale/fsl-ls1012a-frdm.dts b/src/arm64/freescale/fsl-ls1012a-frdm.dts index f90c040fd5e8..67702667ed8a 100644 --- a/src/arm64/freescale/fsl-ls1012a-frdm.dts +++ b/src/arm64/freescale/fsl-ls1012a-frdm.dts @@ -74,6 +74,21 @@ }; }; +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + m25p,fast-read; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &sai2 { status = "okay"; }; diff --git a/src/arm64/freescale/fsl-ls1012a-frwy.dts b/src/arm64/freescale/fsl-ls1012a-frwy.dts index 8749634c55ee..6290e2f9de6a 100644 --- a/src/arm64/freescale/fsl-ls1012a-frwy.dts +++ b/src/arm64/freescale/fsl-ls1012a-frwy.dts @@ -23,3 +23,18 @@ &i2c0 { status = "okay"; }; + +&qspi { + status = "okay"; + + w25q16dw0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + m25p,fast-read; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; diff --git a/src/arm64/freescale/fsl-ls1012a-qds.dts b/src/arm64/freescale/fsl-ls1012a-qds.dts index 2fb1cb1f7d8f..449475a97bf1 100644 --- a/src/arm64/freescale/fsl-ls1012a-qds.dts +++ b/src/arm64/freescale/fsl-ls1012a-qds.dts @@ -128,6 +128,21 @@ }; }; +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + m25p,fast-read; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &sai2 { status = "okay"; }; diff --git a/src/arm64/freescale/fsl-ls1012a-rdb.dts b/src/arm64/freescale/fsl-ls1012a-rdb.dts index 5edb1e137a52..d45c17620b98 100644 --- a/src/arm64/freescale/fsl-ls1012a-rdb.dts +++ b/src/arm64/freescale/fsl-ls1012a-rdb.dts @@ -35,6 +35,21 @@ status = "okay"; }; +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + m25p,fast-read; + reg = <0>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &sata { status = "okay"; }; diff --git a/src/arm64/freescale/fsl-ls1012a.dtsi b/src/arm64/freescale/fsl-ls1012a.dtsi index 337919366dc8..006e544d1fdb 100644 --- a/src/arm64/freescale/fsl-ls1012a.dtsi +++ b/src/arm64/freescale/fsl-ls1012a.dtsi @@ -137,6 +137,19 @@ #size-cells = <2>; ranges; + qspi: spi@1550000 { + compatible = "fsl,ls1021a-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1550000 0x0 0x10000>, + <0x0 0x40000000 0x0 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clock-names = "qspi_en", "qspi"; + clocks = <&clockgen 4 0>, <&clockgen 4 0>; + status = "disabled"; + }; + esdhc0: esdhc@1560000 { compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; reg = <0x0 0x1560000 0x0 0x10000>; diff --git a/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var2.dts b/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var2.dts index 901b5b161def..dd764b720fb0 100644 --- a/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var2.dts +++ b/src/arm64/freescale/fsl-ls1028a-kontron-sl28-var2.dts @@ -53,14 +53,14 @@ }; &mscc_felix_port0 { - label = "gbe0"; + label = "swp0"; phy-handle = <&phy0>; phy-mode = "sgmii"; status = "okay"; }; &mscc_felix_port1 { - label = "gbe1"; + label = "swp1"; phy-handle = <&phy1>; phy-mode = "sgmii"; status = "okay"; diff --git a/src/arm64/freescale/fsl-ls1028a-kontron-sl28.dts b/src/arm64/freescale/fsl-ls1028a-kontron-sl28.dts index 1648a04ea79f..852dad8d70ab 100644 --- a/src/arm64/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/src/arm64/freescale/fsl-ls1028a-kontron-sl28.dts @@ -17,6 +17,7 @@ crypto = &crypto; serial0 = &duart0; serial1 = &duart1; + serial2 = &lpuart1; spi0 = &fspi; spi1 = &dspi2; }; @@ -185,3 +186,7 @@ pagesize = <32>; }; }; + +&lpuart1 { + status = "okay"; +}; diff --git a/src/arm64/freescale/fsl-ls1028a.dtsi b/src/arm64/freescale/fsl-ls1028a.dtsi index 13d0570c7ed6..055f114cf848 100644 --- a/src/arm64/freescale/fsl-ls1028a.dtsi +++ b/src/arm64/freescale/fsl-ls1028a.dtsi @@ -298,6 +298,8 @@ interrupts = ; clock-names = "dspi"; clocks = <&clockgen 4 1>; + dmas = <&edma0 0 62>, <&edma0 0 60>; + dma-names = "tx", "rx"; spi-num-chipselects = <4>; little-endian; status = "disabled"; @@ -311,6 +313,8 @@ interrupts = ; clock-names = "dspi"; clocks = <&clockgen 4 1>; + dmas = <&edma0 0 58>, <&edma0 0 56>; + dma-names = "tx", "rx"; spi-num-chipselects = <4>; little-endian; status = "disabled"; @@ -324,6 +328,8 @@ interrupts = ; clock-names = "dspi"; clocks = <&clockgen 4 1>; + dmas = <&edma0 0 54>, <&edma0 0 2>; + dma-names = "tx", "rx"; spi-num-chipselects = <3>; little-endian; status = "disabled"; diff --git a/src/arm64/freescale/fsl-ls1043a-rdb.dts b/src/arm64/freescale/fsl-ls1043a-rdb.dts index dde50c88f5e3..bfa9d957e536 100644 --- a/src/arm64/freescale/fsl-ls1043a-rdb.dts +++ b/src/arm64/freescale/fsl-ls1043a-rdb.dts @@ -13,6 +13,7 @@ / { model = "LS1043A RDB Board"; + compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; aliases { serial0 = &duart0; @@ -94,6 +95,22 @@ reg = <0>; spi-max-frequency = <1000000>; /* input clock */ }; + + slic@2 { + compatible = "maxim,ds26522"; + reg = <2>; + spi-max-frequency = <2000000>; + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <50>; + }; + + slic@3 { + compatible = "maxim,ds26522"; + reg = <3>; + spi-max-frequency = <2000000>; + fsl,spi-cs-sck-delay = <100>; + fsl,spi-sck-cs-delay = <50>; + }; }; &duart0 { @@ -176,3 +193,19 @@ }; }; }; + +&uqe { + ucc_hdlc: ucc@2000 { + compatible = "fsl,ucc-hdlc"; + rx-clock-name = "clk8"; + tx-clock-name = "clk9"; + fsl,rx-sync-clock = "rsync_pin"; + fsl,tx-sync-clock = "tsync_pin"; + fsl,tx-timeslot-mask = <0xfffffffe>; + fsl,rx-timeslot-mask = <0xfffffffe>; + fsl,tdm-framer-type = "e1"; + fsl,tdm-id = <0>; + fsl,siram-entry-id = <0>; + fsl,tdm-interface; + }; +}; diff --git a/src/arm64/freescale/fsl-ls1043a.dtsi b/src/arm64/freescale/fsl-ls1043a.dtsi index c084c7a4b6a6..3b641bd43229 100644 --- a/src/arm64/freescale/fsl-ls1043a.dtsi +++ b/src/arm64/freescale/fsl-ls1043a.dtsi @@ -525,6 +525,71 @@ #interrupt-cells = <2>; }; + uqe: uqe@2400000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe", "simple-bus"; + ranges = <0x0 0x0 0x2400000 0x40000>; + reg = <0x0 0x2400000 0x0 0x480>; + brg-frequency = <100000000>; + bus-frequency = <200000000>; + fsl,qe-num-riscs = <1>; + fsl,qe-num-snums = <28>; + + qeic: qeic@80 { + compatible = "fsl,qe-ic"; + reg = <0x80 0x80>; + #address-cells = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = , + ; + }; + + si1: si@700 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,ls1043-qe-si", + "fsl,t1040-qe-si"; + reg = <0x700 0x80>; + }; + + siram1: siram@1000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1043-qe-siram", + "fsl,t1040-qe-siram"; + reg = <0x1000 0x800>; + }; + + ucc@2000 { + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + }; + + ucc@2200 { + cell-index = <3>; + reg = <0x2200 0x200>; + interrupts = <34>; + interrupt-parent = <&qeic>; + }; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x10000 0x6000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x6000>; + }; + }; + }; + lpuart0: serial@2950000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2950000 0x0 0x1000>; diff --git a/src/arm64/freescale/fsl-lx2160a.dtsi b/src/arm64/freescale/fsl-lx2160a.dtsi index ae1b113ab162..abaeb587de48 100644 --- a/src/arm64/freescale/fsl-lx2160a.dtsi +++ b/src/arm64/freescale/fsl-lx2160a.dtsi @@ -436,19 +436,19 @@ }; thermal-zones { - core_thermal1: core-thermal1 { + cluster6-7 { polling-delay-passive = <1000>; polling-delay = <5000>; thermal-sensors = <&tmu 0>; trips { - core_cluster_alert: core-cluster-alert { + cluster6_7_alert: cluster6-7-alert { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - core_cluster_crit: core-cluster-crit { + cluster6_7_crit: cluster6-7-crit { temperature = <95000>; hysteresis = <2000>; type = "critical"; @@ -457,7 +457,7 @@ cooling-maps { map0 { - trip = <&core_cluster_alert>; + trip = <&cluster6_7_alert>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -478,6 +478,126 @@ }; }; }; + + ddr-cluster5 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 1>; + + trips { + ddr-cluster5-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + ddr-cluster5-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + wriop { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 2>; + + trips { + wriop-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + wriop-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + dce-qbman-hsio2 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 3>; + + trips { + dce-qbman-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + dce-qbman-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + ccn-dpaa-tbu { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 4>; + + trips { + ccn-dpaa-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + ccn-dpaa-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cluster4-hsio3 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 5>; + + trips { + clust4-hsio3-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + clust4-hsio3-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cluster2-3 { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 6>; + + trips { + cluster2-3-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster2-3-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; }; soc { @@ -549,7 +669,7 @@ /* Calibration data group 1 */ <0x00000000 0x00000035 /* Calibration data group 2 */ - 0x00010001 0x00000154>; + 0x00000001 0x00000154>; little-endian; #thermal-sensor-cells = <1>; }; diff --git a/src/arm64/freescale/imx8mm-beacon-baseboard.dtsi b/src/arm64/freescale/imx8mm-beacon-baseboard.dtsi new file mode 100644 index 000000000000..baa5f997d018 --- /dev/null +++ b/src/arm64/freescale/imx8mm-beacon-baseboard.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/ { + leds { + compatible = "gpio-leds"; + + led0 { + label = "gen_led0"; + gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; + default-state = "none"; + }; + + led1 { + label = "gen_led1"; + gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; + default-state = "none"; + }; + + led2 { + label = "gen_led2"; + gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; + default-state = "none"; + }; + + led3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led3>; + label = "heartbeat"; + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_audio: regulator-audio { + compatible = "regulator-fixed"; + regulator-name = "3v3_aud"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8962>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_espi2>; + cs-gpios = <&gpio5 9 0>; + status = "okay"; + + eeprom@0 { + compatible = "microchip,at25160bn", "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + pagesize = <32>; + size = <2048>; + address-width = <16>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + wm8962: audio-codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; + clock-names = "xclk"; + DCVDD-supply = <®_audio>; + DBVDD-supply = <®_audio>; + AVDD-supply = <®_audio>; + CPVDD-supply = <®_audio>; + MICVDD-supply = <®_audio>; + PLLVDD-supply = <®_audio>; + SPKVDD1-supply = <®_audio>; + SPKVDD2-supply = <®_audio>; + gpio-cfg = < + 0x0000 /* 0:Default */ + 0x0000 /* 1:Default */ + 0x0000 /* 2:FN_DMICCLK */ + 0x0000 /* 3:Default */ + 0x0000 /* 4:FN_DMICCDAT */ + 0x0000 /* 5:Default */ + >; + }; + + pca6416_0: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6414>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6416_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_espi2: espi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_led3: led3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 + >; + }; + + pinctrl_pcal6414: pcal6414-gpio { + fsl,pins = < + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; +}; diff --git a/src/arm64/freescale/imx8mm-beacon-kit.dts b/src/arm64/freescale/imx8mm-beacon-kit.dts new file mode 100644 index 000000000000..74a7b0cc10c2 --- /dev/null +++ b/src/arm64/freescale/imx8mm-beacon-kit.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/dts-v1/; + +#include "imx8mm.dtsi" +#include "imx8mm-beacon-som.dtsi" +#include "imx8mm-beacon-baseboard.dtsi" + +/ { + model = "Beacon EmbeddedWorks i.MX8M Mini Development Kit"; + compatible = "beacon,imx8mm-beacon-kit", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; +}; diff --git a/src/arm64/freescale/imx8mm-beacon-som.dtsi b/src/arm64/freescale/imx8mm-beacon-som.dtsi new file mode 100644 index 000000000000..94911b1707ef --- /dev/null +++ b/src/arm64/freescale/imx8mm-beacon-som.dtsi @@ -0,0 +1,410 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Compass Electronics Group, LLC + */ + +/ { + usdhc1_pwrseq: usdhc1_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_gpio>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + clocks = <&osc_32k>; + clock-names = "ext_clock"; + post-power-on-delay-ms = <80>; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "BUCK3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + eeprom@50 { + compatible = "microchip, at24c64d", "atmel,24c64"; + pagesize = <32>; + read-only; /* Manufacturing EEPROM programmed at factory */ + reg = <0x50>; + }; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + clocks = <&osc_32k>; + clock-names = "extclk"; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + non-removable; + cap-power-off-card; + pm-ignore-notify; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc1_pwrseq>; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; +}; diff --git a/src/arm64/freescale/imx8mm-evk.dts b/src/arm64/freescale/imx8mm-evk.dts index 951e14a3de0e..0f1d7f8aeac4 100644 --- a/src/arm64/freescale/imx8mm-evk.dts +++ b/src/arm64/freescale/imx8mm-evk.dts @@ -82,6 +82,18 @@ cpu-supply = <&buck2_reg>; }; +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; @@ -196,7 +208,7 @@ ldo1_reg: LDO1 { regulator-name = "LDO1"; - regulator-min-microvolt = <3000000>; + regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; @@ -204,7 +216,7 @@ ldo2_reg: LDO2 { regulator-name = "LDO2"; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; diff --git a/src/arm64/freescale/imx8mm.dtsi b/src/arm64/freescale/imx8mm.dtsi index 8829628f757a..aaf6e71101a1 100644 --- a/src/arm64/freescale/imx8mm.dtsi +++ b/src/arm64/freescale/imx8mm.dtsi @@ -270,6 +270,7 @@ ranges = <0x30000000 0x30000000 0x400000>; sai1: sai@30010000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30010000 0x10000>; interrupts = ; @@ -283,6 +284,7 @@ }; sai2: sai@30020000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; interrupts = ; @@ -310,6 +312,7 @@ }; sai5: sai@30050000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; interrupts = ; @@ -323,6 +326,7 @@ }; sai6: sai@30060000 { + #sound-dai-cells = <0>; compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; interrupts = ; @@ -515,16 +519,20 @@ <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MM_CLK_NOC>, + assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, + <&clk IMX8MM_CLK_A53_CORE>, + <&clk IMX8MM_CLK_NOC>, <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MM_SYS_PLL3>, <&clk IMX8MM_VIDEO_PLL1>, <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>, + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_ARM_PLL_OUT>, + <&clk IMX8MM_SYS_PLL3_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; - assigned-clock-rates = <0>, + assigned-clock-rates = <0>, <0>, <0>, <400000000>, <400000000>, <750000000>, diff --git a/src/arm64/freescale/imx8mn-ddr4-evk.dts b/src/arm64/freescale/imx8mn-ddr4-evk.dts index 2497eebb5739..a1e5483dbbbe 100644 --- a/src/arm64/freescale/imx8mn-ddr4-evk.dts +++ b/src/arm64/freescale/imx8mn-ddr4-evk.dts @@ -17,6 +17,18 @@ cpu-supply = <&buck2_reg>; }; +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; @@ -101,7 +113,7 @@ ldo1_reg: LDO1 { regulator-name = "LDO1"; - regulator-min-microvolt = <3000000>; + regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; @@ -109,7 +121,7 @@ ldo2_reg: LDO2 { regulator-name = "LDO2"; - regulator-min-microvolt = <900000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; diff --git a/src/arm64/freescale/imx8mn.dtsi b/src/arm64/freescale/imx8mn.dtsi index 43971abe218b..9a4b65a267d4 100644 --- a/src/arm64/freescale/imx8mn.dtsi +++ b/src/arm64/freescale/imx8mn.dtsi @@ -121,7 +121,7 @@ opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <950000>; + opp-microvolt = <850000>; opp-supported-hw = <0xb00>, <0x7>; clock-latency-ns = <150000>; opp-suspend; @@ -426,13 +426,17 @@ <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MN_CLK_NOC>, + assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, + <&clk IMX8MN_CLK_A53_CORE>, + <&clk IMX8MN_CLK_NOC>, <&clk IMX8MN_CLK_AUDIO_AHB>, <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MN_SYS_PLL3>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL3_OUT>, + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_ARM_PLL_OUT>, + <&clk IMX8MN_SYS_PLL3_OUT>, <&clk IMX8MN_SYS_PLL1_800M>; - assigned-clock-rates = <0>, + assigned-clock-rates = <0>, <0>, <0>, <400000000>, <400000000>, <600000000>; diff --git a/src/arm64/freescale/imx8mp.dtsi b/src/arm64/freescale/imx8mp.dtsi index 9f6ba763238d..45e2c0a4e889 100644 --- a/src/arm64/freescale/imx8mp.dtsi +++ b/src/arm64/freescale/imx8mp.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include "imx8mp-pinfunc.h" @@ -43,6 +44,7 @@ clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -53,6 +55,7 @@ clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_2: cpu@2 { @@ -63,6 +66,7 @@ clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_3: cpu@3 { @@ -73,6 +77,7 @@ clocks = <&clk IMX8MP_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -127,6 +132,68 @@ method = "smc"; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + soc-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 1>; + trips { + soc_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&soc_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -215,6 +282,13 @@ gpio-ranges = <&iomuxc 0 114 30>; }; + tmu: tmu@30260000 { + compatible = "fsl,imx8mp-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; + #thermal-sensor-cells = <1>; + }; + wdog1: watchdog@30280000 { compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; @@ -286,7 +360,9 @@ <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MP_CLK_NOC>, + assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, + <&clk IMX8MP_CLK_A53_CORE>, + <&clk IMX8MP_CLK_NOC>, <&clk IMX8MP_CLK_NOC_IO>, <&clk IMX8MP_CLK_GIC>, <&clk IMX8MP_CLK_AUDIO_AHB>, @@ -294,12 +370,15 @@ <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_ARM_PLL_OUT>, + <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL2_500M>, <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <1000000000>, + assigned-clock-rates = <0>, <0>, + <1000000000>, <800000000>, <500000000>, <400000000>, @@ -312,6 +391,7 @@ src: reset-controller@30390000 { compatible = "fsl,imx8mp-src", "syscon"; reg = <0x30390000 0x10000>; + interrupts = ; #reset-cells = <1>; }; }; @@ -615,7 +695,7 @@ }; fec: ethernet@30be0000 { - compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec"; + compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; interrupts = , , diff --git a/src/arm64/freescale/imx8mq-librem5-devkit.dts b/src/arm64/freescale/imx8mq-librem5-devkit.dts index 10eca94194be..6900ac274f5b 100644 --- a/src/arm64/freescale/imx8mq-librem5-devkit.dts +++ b/src/arm64/freescale/imx8mq-librem5-devkit.dts @@ -318,7 +318,7 @@ regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; - rohm,dvs-run-voltage = <1000000>; + rohm,dvs-run-voltage = <900000>; }; buck4_reg: BUCK4 { @@ -410,7 +410,7 @@ }; }; - typec_ptn5100: usb_typec@52 { + typec_ptn5100: usb-typec@52 { compatible = "nxp,ptn5110"; reg = <0x52>; pinctrl-names = "default"; diff --git a/src/arm64/freescale/imx8mq.dtsi b/src/arm64/freescale/imx8mq.dtsi index bab88369be1b..978f8122c0d2 100644 --- a/src/arm64/freescale/imx8mq.dtsi +++ b/src/arm64/freescale/imx8mq.dtsi @@ -595,13 +595,19 @@ clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; - assigned-clocks = <&clk IMX8MQ_CLK_NOC>; - assigned-clock-rates = <800000000>; + assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, + <&clk IMX8MQ_CLK_A53_CORE>, + <&clk IMX8MQ_CLK_NOC>; + assigned-clock-rates = <0>, <0>, + <800000000>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_ARM_PLL_OUT>; }; src: reset-controller@30390000 { compatible = "fsl,imx8mq-src", "syscon"; reg = <0x30390000 0x10000>; + interrupts = ; #reset-cells = <1>; }; diff --git a/src/arm64/freescale/imx8qxp-mek.dts b/src/arm64/freescale/imx8qxp-mek.dts index 13460a360c6a..46437d3c7a04 100644 --- a/src/arm64/freescale/imx8qxp-mek.dts +++ b/src/arm64/freescale/imx8qxp-mek.dts @@ -30,31 +30,10 @@ }; }; -&adma_lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; +&adma_dsp { status = "okay"; }; -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - }; -}; - &adma_i2c1 { #address-cells = <1>; #size-cells = <0>; @@ -131,6 +110,68 @@ }; }; +&adma_lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&scu_key { + status = "okay"; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + &usdhc1 { assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; assigned-clock-rates = <200000000>; @@ -175,7 +216,7 @@ >; }; - pinctrl_ioexp_rst: ioexp_rst_grp { + pinctrl_ioexp_rst: ioexprstgrp { fsl,pins = < IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 >; @@ -229,11 +270,3 @@ >; }; }; - -&adma_dsp { - status = "okay"; -}; - -&scu_key { - status = "okay"; -}; diff --git a/src/arm64/freescale/imx8qxp.dtsi b/src/arm64/freescale/imx8qxp.dtsi index e8ffb7590656..d1c3c98e4b39 100644 --- a/src/arm64/freescale/imx8qxp.dtsi +++ b/src/arm64/freescale/imx8qxp.dtsi @@ -141,17 +141,11 @@ scu { compatible = "fsl,imx-scu"; - mbox-names = "tx0", "tx1", "tx2", "tx3", - "rx0", "rx1", "rx2", "rx3", + mbox-names = "tx0", + "rx0", "gip3"; mboxes = <&lsio_mu1 0 0 - &lsio_mu1 0 1 - &lsio_mu1 0 2 - &lsio_mu1 0 3 &lsio_mu1 1 0 - &lsio_mu1 1 1 - &lsio_mu1 1 2 - &lsio_mu1 1 3 &lsio_mu1 3 3>; clk: clock-controller { @@ -548,14 +542,14 @@ }; lsio_mu1: mailbox@5d1c0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; reg = <0x5d1c0000 0x10000>; interrupts = ; #mbox-cells = <2>; }; lsio_mu2: mailbox@5d1d0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; reg = <0x5d1d0000 0x10000>; interrupts = ; #mbox-cells = <2>; @@ -563,7 +557,7 @@ }; lsio_mu3: mailbox@5d1e0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; reg = <0x5d1e0000 0x10000>; interrupts = ; #mbox-cells = <2>; @@ -571,7 +565,7 @@ }; lsio_mu4: mailbox@5d1f0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; + compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; reg = <0x5d1f0000 0x10000>; interrupts = ; #mbox-cells = <2>; diff --git a/src/arm64/freescale/qoriq-fman3-0.dtsi b/src/arm64/freescale/qoriq-fman3-0.dtsi index 263b972a6d1e..8bc6caa9167d 100644 --- a/src/arm64/freescale/qoriq-fman3-0.dtsi +++ b/src/arm64/freescale/qoriq-fman3-0.dtsi @@ -81,4 +81,5 @@ ptp_timer0: ptp-timer@1afe000 { reg = <0x0 0x1afe000 0x0 0x1000>; interrupts = ; clocks = <&clockgen 3 0>; + fsl,extts-fifo; }; diff --git a/src/arm64/hisilicon/hi3660.dtsi b/src/arm64/hisilicon/hi3660.dtsi index 253cc345f143..c39b78989ff9 100644 --- a/src/arm64/hisilicon/hi3660.dtsi +++ b/src/arm64/hisilicon/hi3660.dtsi @@ -974,7 +974,7 @@ clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; clock-names = "apb_pclk"; pinctrl-names = "default"; - pinctrl-0 = <&spi2_pmx_func>; + pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>; num-cs = <1>; cs-gpios = <&gpio27 2 0>; status = "disabled"; @@ -989,7 +989,7 @@ clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; clock-names = "apb_pclk"; pinctrl-names = "default"; - pinctrl-0 = <&spi3_pmx_func>; + pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>; num-cs = <1>; cs-gpios = <&gpio18 5 0>; status = "disabled"; diff --git a/src/arm64/hisilicon/hi6220-coresight.dtsi b/src/arm64/hisilicon/hi6220-coresight.dtsi index 651771a73ed6..7b3010f448c5 100644 --- a/src/arm64/hisilicon/hi6220-coresight.dtsi +++ b/src/arm64/hisilicon/hi6220-coresight.dtsi @@ -213,7 +213,7 @@ }; }; - etm@f659c000 { + etm0: etm@f659c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659c000 0 0x1000>; @@ -232,7 +232,7 @@ }; }; - etm@f659d000 { + etm1: etm@f659d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659d000 0 0x1000>; @@ -251,7 +251,7 @@ }; }; - etm@f659e000 { + etm2: etm@f659e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659e000 0 0x1000>; @@ -270,7 +270,7 @@ }; }; - etm@f659f000 { + etm3: etm@f659f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf659f000 0 0x1000>; @@ -289,7 +289,7 @@ }; }; - etm@f65dc000 { + etm4: etm@f65dc000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65dc000 0 0x1000>; @@ -308,7 +308,7 @@ }; }; - etm@f65dd000 { + etm5: etm@f65dd000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65dd000 0 0x1000>; @@ -327,7 +327,7 @@ }; }; - etm@f65de000 { + etm6: etm@f65de000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65de000 0 0x1000>; @@ -346,7 +346,7 @@ }; }; - etm@f65df000 { + etm7: etm@f65df000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0xf65df000 0 0x1000>; @@ -364,5 +364,119 @@ }; }; }; + + /* System CTIs */ + /* CTI 0 - TMC and TPIU connections */ + cti@f6403000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0xf6403000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + }; + + /* CTI - CPU-0 */ + cti@f6598000 { + compatible = "arm,coresight-cti-v8-arch", + "arm,coresight-cti", "arm,primecell"; + reg = <0 0xf6598000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu0>; + arm,cs-dev-assoc = <&etm0>; + }; + + /* CTI - CPU-1 */ + cti@f6599000 { + compatible = "arm,coresight-cti-v8-arch", + "arm,coresight-cti", "arm,primecell"; + reg = <0 0xf6599000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu1>; + arm,cs-dev-assoc = <&etm1>; + }; + + /* CTI - CPU-2 */ + cti@f659a000 { + compatible = "arm,coresight-cti-v8-arch", + "arm,coresight-cti", "arm,primecell"; + reg = <0 0xf659a000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu2>; + arm,cs-dev-assoc = <&etm2>; + }; + + /* CTI - CPU-3 */ + cti@f659b000 { + compatible = "arm,coresight-cti-v8-arch", + "arm,coresight-cti", "arm,primecell"; + reg = <0 0xf659b000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu3>; + arm,cs-dev-assoc = <&etm3>; + }; + + /* CTI - CPU-4 */ + cti@f65d8000 { + compatible = "arm,coresight-cti-v8-arch", + "arm,coresight-cti", "arm,primecell"; + reg = <0 0xf65d8000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu4>; + arm,cs-dev-assoc = <&etm4>; + }; + + /* CTI - CPU-5 */ + cti@f65d9000 { + compatible = "arm,coresight-cti-v8-arch", + "arm,coresight-cti", "arm,primecell"; + reg = <0 0xf65d9000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu5>; + arm,cs-dev-assoc = <&etm5>; + }; + + /* CTI - CPU-6 */ + cti@f65da000 { + compatible = "arm,coresight-cti-v8-arch", + "arm,coresight-cti", "arm,primecell"; + reg = <0 0xf65da000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu6>; + arm,cs-dev-assoc = <&etm6>; + }; + + /* CTI - CPU-7 */ + cti@f65db000 { + compatible = "arm,coresight-cti-v8-arch", + "arm,coresight-cti", "arm,primecell"; + reg = <0 0xf65db000 0 0x1000>; + + clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>; + clock-names = "apb_pclk"; + + cpu = <&cpu7>; + arm,cs-dev-assoc = <&etm7>; + }; }; }; diff --git a/src/arm64/hisilicon/hikey960-pinctrl.dtsi b/src/arm64/hisilicon/hikey960-pinctrl.dtsi index d11efc81958c..920a3111c66d 100644 --- a/src/arm64/hisilicon/hikey960-pinctrl.dtsi +++ b/src/arm64/hisilicon/hikey960-pinctrl.dtsi @@ -717,7 +717,7 @@ spi3_cfg_func: spi3_cfg_func { pinctrl-single,pins = < 0x008 0x0 /* SPI3_CLK */ - 0x0 /* SPI3_DI */ + 0x00c 0x0 /* SPI3_DI */ 0x010 0x0 /* SPI3_DO */ 0x014 0x0 /* SPI3_CS0_N */ >; @@ -734,7 +734,7 @@ PULL_UP >; pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK + DRIVE7_06MA DRIVE6_MASK >; }; }; @@ -1031,7 +1031,7 @@ PULL_UP >; pinctrl-single,drive-strength = < - DRIVE7_02MA DRIVE6_MASK + DRIVE7_06MA DRIVE6_MASK >; }; diff --git a/src/arm64/intel/socfpga_agilex.dtsi b/src/arm64/intel/socfpga_agilex.dtsi index d8c44d3ca15a..f52de8f7806a 100644 --- a/src/arm64/intel/socfpga_agilex.dtsi +++ b/src/arm64/intel/socfpga_agilex.dtsi @@ -539,12 +539,12 @@ firmware { svc { - compatible = "intel,stratix10-svc"; + compatible = "intel,agilex-svc"; method = "smc"; memory-region = <&service_reserved>; fpga_mgr: fpga-mgr { - compatible = "intel,stratix10-soc-fpga-mgr"; + compatible = "intel,agilex-soc-fpga-mgr"; }; }; }; diff --git a/src/arm64/intel/socfpga_agilex_socdk.dts b/src/arm64/intel/socfpga_agilex_socdk.dts index 51d948323bfd..92f478def723 100644 --- a/src/arm64/intel/socfpga_agilex_socdk.dts +++ b/src/arm64/intel/socfpga_agilex_socdk.dts @@ -98,6 +98,7 @@ }; &qspi { + status = "okay"; flash@0 { #address-cells = <1>; #size-cells = <1>; diff --git a/src/arm64/marvell/armada-3720-db.dts b/src/arm64/marvell/armada-3720-db.dts index f2cc00594d64..3e5789f37206 100644 --- a/src/arm64/marvell/armada-3720-db.dts +++ b/src/arm64/marvell/armada-3720-db.dts @@ -128,6 +128,9 @@ /* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */ &pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; + reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/src/arm64/marvell/armada-3720-espressobin.dtsi b/src/arm64/marvell/armada-3720-espressobin.dtsi index 42e992f9c8a5..b97218c72727 100644 --- a/src/arm64/marvell/armada-3720-espressobin.dtsi +++ b/src/arm64/marvell/armada-3720-espressobin.dtsi @@ -44,9 +44,9 @@ /* J9 */ &pcie0 { status = "okay"; - phys = <&comphy1 0>; pinctrl-names = "default"; pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; + reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; }; /* J6 */ diff --git a/src/arm64/marvell/armada-3720-turris-mox.dts b/src/arm64/marvell/armada-3720-turris-mox.dts index bb42d1e6a4e9..f3a678e0fd99 100644 --- a/src/arm64/marvell/armada-3720-turris-mox.dts +++ b/src/arm64/marvell/armada-3720-turris-mox.dts @@ -95,7 +95,7 @@ }; sfp: sfp { - compatible = "sff,sfp+"; + compatible = "sff,sfp"; i2c-bus = <&i2c0>; los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>; tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>; @@ -128,17 +128,11 @@ }; }; -&pcie_reset_pins { - function = "gpio"; -}; - &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; status = "okay"; - max-link-speed = <2>; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; - phys = <&comphy1 0>; /* enabled by U-Boot if PCIe module is present */ status = "disabled"; @@ -179,6 +173,8 @@ marvell,pad-type = "sd"; vqmmc-supply = <&vsdio_reg>; mmc-pwrseq = <&sdhci1_pwrseq>; + /* forbid SDR104 for FCC purposes */ + sdhci-caps-mask = <0x2 0x0>; status = "okay"; }; diff --git a/src/arm64/marvell/armada-3720-uDPU.dts b/src/arm64/marvell/armada-3720-uDPU.dts index 7eb6c1796cef..95d46e8d081c 100644 --- a/src/arm64/marvell/armada-3720-uDPU.dts +++ b/src/arm64/marvell/armada-3720-uDPU.dts @@ -117,18 +117,36 @@ }; }; +&pinctrl_nb { + i2c1_recovery_pins: i2c1-recovery-pins { + groups = "i2c1"; + function = "gpio"; + }; + + i2c2_recovery_pins: i2c2-recovery-pins { + groups = "i2c2"; + function = "gpio"; + }; +}; + &i2c0 { status = "okay"; - pinctrl-names = "default"; + pinctrl-names = "default", "recovery"; pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_recovery_pins>; /delete-property/mrvl,i2c-fast-mode; + scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; &i2c1 { status = "okay"; - pinctrl-names = "default"; + pinctrl-names = "default", "recovery"; pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_recovery_pins>; /delete-property/mrvl,i2c-fast-mode; + scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; lm75@48 { status = "okay"; diff --git a/src/arm64/marvell/armada-37xx.dtsi b/src/arm64/marvell/armada-37xx.dtsi index 000c135e39b7..2bbc69b4dc99 100644 --- a/src/arm64/marvell/armada-37xx.dtsi +++ b/src/arm64/marvell/armada-37xx.dtsi @@ -317,7 +317,7 @@ pcie_reset_pins: pcie-reset-pins { groups = "pcie1"; - function = "pcie"; + function = "gpio"; }; pcie_clkreq_pins: pcie-clkreq-pins { @@ -493,6 +493,8 @@ <0 0 0 2 &pcie_intc 1>, <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; + max-link-speed = <2>; + phys = <&comphy1 0>; pcie_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; diff --git a/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts b/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts index b90d78a5724b..eb01cc96ba7a 100644 --- a/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts +++ b/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts @@ -276,7 +276,7 @@ /* SFP */ &cp0_eth0 { status = "okay"; - phy-mode = "10gbase-kr"; + phy-mode = "10gbase-r"; managed = "in-band-status"; phys = <&cp0_comphy2 0>; sfp = <&sfp_cp0_eth0>; @@ -454,10 +454,7 @@ status = "okay"; phy-mode = "2500base-x"; phys = <&cp1_comphy5 2>; - fixed-link { - speed = <2500>; - full-duplex; - }; + managed = "in-band-status"; }; &cp1_spi1 { diff --git a/src/arm64/marvell/armada-8040-mcbin-singleshot.dts b/src/arm64/marvell/armada-8040-mcbin-singleshot.dts index c3e18fd5bc27..2e6832d02a59 100644 --- a/src/arm64/marvell/armada-8040-mcbin-singleshot.dts +++ b/src/arm64/marvell/armada-8040-mcbin-singleshot.dts @@ -16,14 +16,14 @@ &cp0_eth0 { status = "okay"; - phy-mode = "10gbase-kr"; + phy-mode = "10gbase-r"; managed = "in-band-status"; sfp = <&sfp_eth0>; }; &cp1_eth0 { status = "okay"; - phy-mode = "10gbase-kr"; + phy-mode = "10gbase-r"; managed = "in-band-status"; sfp = <&sfp_eth1>; }; diff --git a/src/arm64/marvell/armada-8040-mcbin.dts b/src/arm64/marvell/armada-8040-mcbin.dts index d06f5ab7ddab..1766cf58101b 100644 --- a/src/arm64/marvell/armada-8040-mcbin.dts +++ b/src/arm64/marvell/armada-8040-mcbin.dts @@ -34,12 +34,12 @@ status = "okay"; /* Network PHY */ phy = <&phy0>; - phy-mode = "10gbase-kr"; + phy-mode = "10gbase-r"; }; &cp1_eth0 { status = "okay"; /* Network PHY */ phy = <&phy8>; - phy-mode = "10gbase-kr"; + phy-mode = "10gbase-r"; }; diff --git a/src/arm64/marvell/armada-ap80x.dtsi b/src/arm64/marvell/armada-ap80x.dtsi index e7438c21ccee..7f9b9a647717 100644 --- a/src/arm64/marvell/armada-ap80x.dtsi +++ b/src/arm64/marvell/armada-ap80x.dtsi @@ -201,7 +201,6 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - timeout-ms = <1000>; clocks = <&ap_clk 3>; status = "disabled"; }; diff --git a/src/arm64/mediatek/mt2712-evb.dts b/src/arm64/mediatek/mt2712-evb.dts index 2b91daf5c1a6..7d369fdd3117 100644 --- a/src/arm64/mediatek/mt2712-evb.dts +++ b/src/arm64/mediatek/mt2712-evb.dts @@ -105,7 +105,81 @@ proc-supply = <&cpus_fixed_vproc1>; }; +ð { + phy-mode ="rgmii-rxid"; + phy-handle = <ðernet_phy0>; + mediatek,tx-delay-ps = <1530>; + snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default>; + pinctrl-1 = <ð_sleep>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@5 { + compatible = "ethernet-phy-id0243.0d90"; + reg = <0x5>; + }; + }; +}; + &pio { + eth_default: eth_default { + tx_pins { + pinmux = , + , + , + , + , + ; + drive-strength = ; + }; + rx_pins { + pinmux = , + , + , + , + , + ; + input-enable; + }; + mdio_pins { + pinmux = , + ; + drive-strength = ; + input-enable; + }; + }; + + eth_sleep: eth_sleep { + tx_pins { + pinmux = , + , + , + , + , + ; + }; + rx_pins { + pinmux = , + , + , + , + , + ; + input-disable; + }; + mdio_pins { + pinmux = , + ; + input-disable; + bias-disable; + }; + }; + usb0_id_pins_float: usb0_iddig { pins_iddig { pinmux = ; diff --git a/src/arm64/mediatek/mt2712e.dtsi b/src/arm64/mediatek/mt2712e.dtsi index 2cd8b33886e5..db17d0a4ed57 100644 --- a/src/arm64/mediatek/mt2712e.dtsi +++ b/src/arm64/mediatek/mt2712e.dtsi @@ -300,6 +300,9 @@ interrupts = ; clocks = <&baud_clk>, <&sys_clk>; clock-names = "baud", "bus"; + dmas = <&apdma 10 + &apdma 11>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -375,6 +378,39 @@ (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; }; + apdma: dma-controller@11000400 { + compatible = "mediatek,mt2712-uart-dma", + "mediatek,mt6577-uart-dma"; + reg = <0 0x11000400 0 0x80>, + <0 0x11000480 0 0x80>, + <0 0x11000500 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>, + <0 0x11000680 0 0x80>, + <0 0x11000700 0 0x80>, + <0 0x11000780 0 0x80>, + <0 0x11000800 0 0x80>, + <0 0x11000880 0 0x80>, + <0 0x11000900 0 0x80>, + <0 0x11000980 0 0x80>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-requests = <12>; + clocks = <&pericfg CLK_PERI_AP_DMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + auxadc: adc@11001000 { compatible = "mediatek,mt2712-auxadc"; reg = <0 0x11001000 0 0x1000>; @@ -391,6 +427,9 @@ interrupts = ; clocks = <&baud_clk>, <&sys_clk>; clock-names = "baud", "bus"; + dmas = <&apdma 0 + &apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -401,6 +440,9 @@ interrupts = ; clocks = <&baud_clk>, <&sys_clk>; clock-names = "baud", "bus"; + dmas = <&apdma 2 + &apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -411,6 +453,9 @@ interrupts = ; clocks = <&baud_clk>, <&sys_clk>; clock-names = "baud", "bus"; + dmas = <&apdma 4 + &apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -421,6 +466,9 @@ interrupts = ; clocks = <&baud_clk>, <&sys_clk>; clock-names = "baud", "bus"; + dmas = <&apdma 6 + &apdma 7>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -635,6 +683,74 @@ interrupts = ; clocks = <&baud_clk>, <&sys_clk>; clock-names = "baud", "bus"; + dmas = <&apdma 8 + &apdma 9>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,priority = <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <3>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + queue1 { + snps,weight = <0x11>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + queue2 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + }; + + eth: ethernet@1101c000 { + compatible = "mediatek,mt2712-gmac"; + reg = <0 0x1101c000 0 0x1300>; + interrupts = ; + interrupt-names = "macirq"; + mac-address = [00 55 7b b5 7d f7]; + clock-names = "axi", + "apb", + "mac_main", + "ptp_ref"; + clocks = <&pericfg CLK_PERI_GMAC>, + <&pericfg CLK_PERI_GMAC_PCLK>, + <&topckgen CLK_TOP_ETHER_125M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_SEL>; + assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, + <&topckgen CLK_TOP_ETHER_50M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, + <&topckgen CLK_TOP_APLL1_D3>; + power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; + mediatek,pericfg = <&pericfg>; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <1>; + snps,rxpbl = <1>; + clk_csr = <0>; status = "disabled"; }; @@ -703,30 +819,31 @@ }; u3phy0: usb-phy@11290000 { - compatible = "mediatek,mt2712-u3phy"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + compatible = "mediatek,mt2712-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11290000 0x9000>; status = "okay"; - u2port0: usb-phy@11290000 { - reg = <0 0x11290000 0 0x700>; + u2port0: usb-phy@0 { + reg = <0x0 0x700>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; - u2port1: usb-phy@11298000 { - reg = <0 0x11298000 0 0x700>; + u2port1: usb-phy@8000 { + reg = <0x8000 0x700>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; - u3port0: usb-phy@11298700 { - reg = <0 0x11298700 0 0x900>; + u3port0: usb-phy@8700 { + reg = <0x8700 0x900>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; @@ -766,30 +883,31 @@ }; u3phy1: usb-phy@112e0000 { - compatible = "mediatek,mt2712-u3phy"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + compatible = "mediatek,mt2712-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x112e0000 0x9000>; status = "okay"; - u2port2: usb-phy@112e0000 { - reg = <0 0x112e0000 0 0x700>; + u2port2: usb-phy@0 { + reg = <0x0 0x700>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; - u2port3: usb-phy@112e8000 { - reg = <0 0x112e8000 0 0x700>; + u2port3: usb-phy@8000 { + reg = <0x8000 0x700>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; status = "okay"; }; - u3port1: usb-phy@112e8700 { - reg = <0 0x112e8700 0 0x900>; + u3port1: usb-phy@8700 { + reg = <0x8700 0x900>; clocks = <&clk26m>; clock-names = "ref"; #phy-cells = <1>; diff --git a/src/arm64/mediatek/mt6358.dtsi b/src/arm64/mediatek/mt6358.dtsi new file mode 100644 index 000000000000..9361ada0c497 --- /dev/null +++ b/src/arm64/mediatek/mt6358.dtsi @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +&pwrap { + pmic: mt6358 { + compatible = "mediatek,mt6358"; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <182 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + + mt6358codec: mt6358codec { + compatible = "mediatek,mt6358-sound"; + }; + + mt6358regulator: mt6358regulator { + mt6358_vdram1_reg: buck_vdram1 { + regulator-name = "vdram1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2087500>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vcore_reg: buck_vcore { + regulator-name = "vcore"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vpa_reg: buck_vpa { + regulator-name = "vpa"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3650000>; + regulator-ramp-delay = <50000>; + regulator-enable-ramp-delay = <250>; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vproc11_reg: buck_vproc11 { + regulator-name = "vproc11"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vproc12_reg: buck_vproc12 { + regulator-name = "vproc12"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vgpu_reg: buck_vgpu { + regulator-name = "vgpu"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vs2_reg: buck_vs2 { + regulator-name = "vs2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2087500>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + + mt6358_vmodem_reg: buck_vmodem { + regulator-name = "vmodem"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <900>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + mt6358_vs1_reg: buck_vs1 { + regulator-name = "vs1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <2587500>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + + mt6358_vdram2_reg: ldo_vdram2 { + regulator-name = "vdram2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <3300>; + }; + + mt6358_vsim1_reg: ldo_vsim1 { + regulator-name = "vsim1"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <540>; + }; + + mt6358_vibr_reg: ldo_vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6358_vrf12_reg: ldo_vrf12 { + compatible = "regulator-fixed"; + regulator-name = "vrf12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <120>; + }; + + mt6358_vio18_reg: ldo_vio18 { + compatible = "regulator-fixed"; + regulator-name = "vio18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <2700>; + regulator-always-on; + }; + + mt6358_vusb_reg: ldo_vusb { + regulator-name = "vusb"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <270>; + regulator-always-on; + }; + + mt6358_vcamio_reg: ldo_vcamio { + compatible = "regulator-fixed"; + regulator-name = "vcamio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <325>; + }; + + mt6358_vcamd_reg: ldo_vcamd { + regulator-name = "vcamd"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <325>; + }; + + mt6358_vcn18_reg: ldo_vcn18 { + compatible = "regulator-fixed"; + regulator-name = "vcn18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vfe28_reg: ldo_vfe28 { + compatible = "regulator-fixed"; + regulator-name = "vfe28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vsram_proc11_reg: ldo_vsram_proc11 { + regulator-name = "vsram_proc11"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + mt6358_vcn28_reg: ldo_vcn28 { + compatible = "regulator-fixed"; + regulator-name = "vcn28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vsram_others_reg: ldo_vsram_others { + regulator-name = "vsram_others"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + mt6358_vsram_gpu_reg: ldo_vsram_gpu { + regulator-name = "vsram_gpu"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + }; + + mt6358_vxo22_reg: ldo_vxo22 { + compatible = "regulator-fixed"; + regulator-name = "vxo22"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-enable-ramp-delay = <120>; + regulator-always-on; + }; + + mt6358_vefuse_reg: ldo_vefuse { + regulator-name = "vefuse"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vaux18_reg: ldo_vaux18 { + compatible = "regulator-fixed"; + regulator-name = "vaux18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vmch_reg: ldo_vmch { + regulator-name = "vmch"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6358_vbif28_reg: ldo_vbif28 { + compatible = "regulator-fixed"; + regulator-name = "vbif28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vsram_proc12_reg: ldo_vsram_proc12 { + regulator-name = "vsram_proc12"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + + mt6358_vcama1_reg: ldo_vcama1 { + regulator-name = "vcama1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <325>; + }; + + mt6358_vemc_reg: ldo_vemc { + regulator-name = "vemc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6358_vio28_reg: ldo_vio28 { + compatible = "regulator-fixed"; + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_va12_reg: ldo_va12 { + compatible = "regulator-fixed"; + regulator-name = "va12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <270>; + regulator-always-on; + }; + + mt6358_vrf18_reg: ldo_vrf18 { + compatible = "regulator-fixed"; + regulator-name = "vrf18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <120>; + }; + + mt6358_vcn33_bt_reg: ldo_vcn33_bt { + regulator-name = "vcn33_bt"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3500000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vcn33_wifi_reg: ldo_vcn33_wifi { + regulator-name = "vcn33_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3500000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vcama2_reg: ldo_vcama2 { + regulator-name = "vcama2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <325>; + }; + + mt6358_vmc_reg: ldo_vmc { + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <60>; + }; + + mt6358_vldo28_reg: ldo_vldo28 { + regulator-name = "vldo28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vaud28_reg: ldo_vaud28 { + compatible = "regulator-fixed"; + regulator-name = "vaud28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <270>; + }; + + mt6358_vsim2_reg: ldo_vsim2 { + regulator-name = "vsim2"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <540>; + }; + }; + + mt6358rtc: mt6358rtc { + compatible = "mediatek,mt6358-rtc"; + }; + }; +}; diff --git a/src/arm64/mediatek/mt6797-x20-dev.dts b/src/arm64/mediatek/mt6797-x20-dev.dts index 13939d55b85b..eff9e8dbd076 100644 --- a/src/arm64/mediatek/mt6797-x20-dev.dts +++ b/src/arm64/mediatek/mt6797-x20-dev.dts @@ -28,6 +28,55 @@ }; }; +/* HDMI */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +/* HS - I2C2 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +/* HS - I2C3 */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; + status = "okay"; +}; + +/* LS - I2C0 */ +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + status = "okay"; +}; + +/* LS - I2C1 */ +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + status = "okay"; +}; + +/* POWER_VPROC */ +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins_a>; + status = "okay"; +}; + +/* FAN53555 */ +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins_a>; + status = "okay"; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/src/arm64/mediatek/mt6797.dtsi b/src/arm64/mediatek/mt6797.dtsi index 136ef9527a0d..15616231022a 100644 --- a/src/arm64/mediatek/mt6797.dtsi +++ b/src/arm64/mediatek/mt6797.dtsi @@ -1,14 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017 MediaTek Inc. * Author: Mars.C - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include @@ -155,6 +148,62 @@ ; }; }; + + i2c0_pins_a: i2c0 { + pins0 { + pinmux = , + ; + }; + }; + + i2c1_pins_a: i2c1 { + pins1 { + pinmux = , + ; + }; + }; + + i2c2_pins_a: i2c2 { + pins2 { + pinmux = , + ; + }; + }; + + i2c3_pins_a: i2c3 { + pins3 { + pinmux = , + ; + }; + }; + + i2c4_pins_a: i2c4 { + pins4 { + pinmux = , + ; + }; + }; + + i2c5_pins_a: i2c5 { + pins5 { + pinmux = , + ; + }; + }; + + i2c6_pins_a: i2c6 { + pins6 { + pinmux = , + ; + }; + }; + + i2c7_pins_a: i2c7 { + pins7 { + pinmux = , + ; + }; + }; }; scpsys: power-controller@10006000 { @@ -233,7 +282,171 @@ status = "disabled"; }; - mmsys: mmsys_config@14000000 { + i2c0: i2c@11007000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <0>; + reg = <0 0x11007000 0 0x1000>, + <0 0x11000100 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C0>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <1>; + reg = <0 0x11008000 0 0x1000>, + <0 0x11000180 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C1>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@11009000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <8>; + reg = <0 0x11009000 0 0x1000>, + <0 0x11000200 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C2>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C2_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@1100d000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <9>; + reg = <0 0x1100d000 0 0x1000>, + <0 0x11000280 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C3>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C3_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@1100e000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <6>; + reg = <0 0x1100e000 0 0x1000>, + <0 0x11000500 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C_APPM>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@11010000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <7>; + reg = <0 0x11010000 0 0x1000>, + <0 0x11000580 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C_GPUPM>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11011000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <4>; + reg = <0 0x11011000 0 0x1000>, + <0 0x11000300 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C4>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11013000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <2>; + reg = <0 0x11013000 0 0x1000>, + <0 0x11000400 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C2_IMM>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C2_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@11014000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <3>; + reg = <0 0x11014000 0 0x1000>, + <0 0x11000480 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C3_IMM>, + <&infrasys CLK_INFRA_AP_DMA>, + <&infrasys CLK_INFRA_I2C3_ARB>; + clock-names = "main", "dma", "arb"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@1101c000 { + compatible = "mediatek,mt6797-i2c", + "mediatek,mt6577-i2c"; + id = <5>; + reg = <0 0x1101c000 0 0x1000>, + <0 0x11000380 0 0x80>; + interrupts = ; + clocks = <&infrasys CLK_INFRA_I2C5>, + <&infrasys CLK_INFRA_AP_DMA>; + clock-names = "main", "dma"; + clock-div = <10>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mmsys: syscon@14000000 { compatible = "mediatek,mt6797-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; diff --git a/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts b/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts index 83e10591e0e5..d174ad214857 100644 --- a/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/src/arm64/mediatek/mt7622-bananapi-bpi-r64.dts @@ -543,3 +543,7 @@ pinctrl-0 = <&watchdog_pins>; status = "okay"; }; + +&wmac { + status = "okay"; +}; diff --git a/src/arm64/mediatek/mt7622-rfb1.dts b/src/arm64/mediatek/mt7622-rfb1.dts index 3f783348c66a..0b4de627f96e 100644 --- a/src/arm64/mediatek/mt7622-rfb1.dts +++ b/src/arm64/mediatek/mt7622-rfb1.dts @@ -506,3 +506,7 @@ pinctrl-0 = <&watchdog_pins>; status = "okay"; }; + +&wmac { + status = "okay"; +}; diff --git a/src/arm64/mediatek/mt7622.dtsi b/src/arm64/mediatek/mt7622.dtsi index 339dc9f88f43..1a39e0ef776b 100644 --- a/src/arm64/mediatek/mt7622.dtsi +++ b/src/arm64/mediatek/mt7622.dtsi @@ -699,6 +699,17 @@ status = "disabled"; }; + wmac: wmac@18000000 { + compatible = "mediatek,mt7622-wmac"; + reg = <0 0x18000000 0 0x100000>; + interrupts = ; + + mediatek,infracfg = <&infracfg>; + status = "disabled"; + + power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; + }; + ssusbsys: ssusbsys@1a000000 { compatible = "mediatek,mt7622-ssusbsys", "syscon"; diff --git a/src/arm64/mediatek/mt8173-elm-hana-rev7.dts b/src/arm64/mediatek/mt8173-elm-hana-rev7.dts new file mode 100644 index 000000000000..44f6149c1307 --- /dev/null +++ b/src/arm64/mediatek/mt8173-elm-hana-rev7.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2019 MediaTek Inc. + */ + +/dts-v1/; +#include "mt8173-elm-hana.dtsi" + +/ { + model = "Google Hanawl"; + compatible = "google,hana-rev7", "mediatek,mt8173"; +}; + +&cpu_thermal { + trips { + cpu_crit: cpu_crit0 { + temperature = <100000>; + type = "critical"; + }; + }; +}; + +&gpio_keys { + /delete-node/tablet_mode; + /delete-node/volume_down; + /delete-node/volume_up; +}; diff --git a/src/arm64/mediatek/mt8173-elm-hana.dts b/src/arm64/mediatek/mt8173-elm-hana.dts new file mode 100644 index 000000000000..c234296755e1 --- /dev/null +++ b/src/arm64/mediatek/mt8173-elm-hana.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016 MediaTek Inc. + */ + +/dts-v1/; +#include "mt8173-elm-hana.dtsi" + +/ { + model = "Google Hana"; + compatible = "google,hana-rev6", "google,hana-rev5", + "google,hana-rev4", "google,hana-rev3", + "google,hana", "mediatek,mt8173"; +}; diff --git a/src/arm64/mediatek/mt8173-elm-hana.dtsi b/src/arm64/mediatek/mt8173-elm-hana.dtsi new file mode 100644 index 000000000000..bdcd35cecad9 --- /dev/null +++ b/src/arm64/mediatek/mt8173-elm-hana.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016 MediaTek Inc. + */ + +#include "mt8173-elm.dtsi" + +&i2c0 { + clock-frequency = <200000>; +}; + +&i2c3 { + touchscreen2: touchscreen@34 { + compatible = "melfas,mip4_ts"; + reg = <0x34>; + interrupt-parent = <&pio>; + interrupts = <88 IRQ_TYPE_LEVEL_LOW>; + }; + + /* + * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd + * Gen (MTK) are using synaptics touchscreen (hid-over-i2c driver) as a + * second source touchscreen. + */ + touchscreen3: touchscreen@20 { + compatible = "hid-over-i2c"; + reg = <0x20>; + hid-descr-addr = <0x0020>; + interrupt-parent = <&pio>; + interrupts = <88 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c4 { + /* + * Lenovo 100e Chromebook 2nd Gen (MTK) and Lenovo 300e Chromebook 2nd + * Gen (MTK) are using synaptics trackpad (hid-over-i2c driver) as a + * second source trackpad. + */ + trackpad2: trackpad@2c { + compatible = "hid-over-i2c"; + interrupt-parent = <&pio>; + interrupts = <117 IRQ_TYPE_LEVEL_LOW>; + reg = <0x2c>; + hid-descr-addr = <0x0020>; + wakeup-source; + }; +}; + +&mmc1 { + wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; +}; + +&pio { + hdmi_mux_pins: hdmi_mux_pins { + pins2 { + pinmux = ; + bias-pull-up; + output-high; + }; + }; + + mmc1_pins_default: mmc1default { + pins_wp { + pinmux = ; + input-enable; + bias-pull-up; + }; + }; +}; diff --git a/src/arm64/mediatek/mt8173-elm.dts b/src/arm64/mediatek/mt8173-elm.dts new file mode 100644 index 000000000000..e9e4ac0b74b2 --- /dev/null +++ b/src/arm64/mediatek/mt8173-elm.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016 MediaTek Inc. + */ + +/dts-v1/; +#include "mt8173-elm.dtsi" + +/ { + model = "Google Elm"; + compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6", + "google,elm-rev5", "google,elm-rev4", "google,elm-rev3", + "google,elm", "mediatek,mt8173"; +}; diff --git a/src/arm64/mediatek/mt8173-elm.dtsi b/src/arm64/mediatek/mt8173-elm.dtsi new file mode 100644 index 000000000000..a5a12b2599a4 --- /dev/null +++ b/src/arm64/mediatek/mt8173-elm.dtsi @@ -0,0 +1,1173 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2016 MediaTek Inc. + */ + +#include +#include +#include +#include "mt8173.dtsi" + +/ { + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 1000000>; + power-supply = <&bl_fixed_reg>; + enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; + status = "okay"; + }; + + bl_fixed_reg: fixedregulator2 { + compatible = "regulator-fixed"; + regulator-name = "bl_fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <1000>; + enable-active-high; + gpio = <&pio 32 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_fixed_pins>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + lid { + label = "Lid"; + gpios = <&pio 69 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + gpio-key,wakeup; + }; + + power { + label = "Power"; + gpios = <&pio 14 GPIO_ACTIVE_HIGH>; + linux,code = ; + debounce-interval = <30>; + gpio-key,wakeup; + }; + + tablet_mode { + label = "Tablet_mode"; + gpios = <&pio 121 GPIO_ACTIVE_HIGH>; + linux,code = ; + linux,input-type = ; + gpio-key,wakeup; + }; + + volume_down { + label = "Volume_down"; + gpios = <&pio 123 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume_up { + label = "Volume_up"; + gpios = <&pio 124 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + panel: panel { + compatible = "lg,lp120up1"; + power-supply = <&panel_fixed_3v3>; + ddc-i2c-bus = <&i2c0>; + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&ps8640_out>; + }; + }; + }; + + panel_fixed_3v3: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "PANEL_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 41 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_fixed_pins>; + }; + + ps8640_fixed_1v2: regulator2 { + compatible = "regulator-fixed"; + regulator-name = "PS8640_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <2000>; + enable-active-high; + regulator-boot-on; + gpio = <&pio 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ps8640_fixed_pins>; + }; + + sdio_fixed_3v3: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 85 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_fixed_3v3_pins>; + }; + + sound: sound { + compatible = "mediatek,mt8173-rt5650"; + mediatek,audio-codec = <&rt5650 &hdmi0>; + mediatek,platform = <&afe>; + pinctrl-names = "default"; + pinctrl-0 = <&aud_i2s2>; + + mediatek,mclk = <1>; + codec-capture { + sound-dai = <&rt5650 1>; + }; + }; + + hdmicon: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmiddc0>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; +}; + +&cec { + status = "okay"; +}; + +&cpu0 { + proc-supply = <&mt6397_vpca15_reg>; +}; + +&cpu1 { + proc-supply = <&mt6397_vpca15_reg>; +}; + +&cpu2 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; +}; + +&cpu3 { + proc-supply = <&da9211_vcpu_reg>; + sram-supply = <&mt6397_vsramca7_reg>; +}; + +&cpu_thermal { + sustainable-power = <4500>; /* milliwatts */ + trips { + threshold: trip-point0 { + temperature = <60000>; + }; + + target: trip-point1 { + temperature = <65000>; + }; + }; +}; + +&dsi0 { + status = "okay"; + ports { + port { + dsi0_out: endpoint { + remote-endpoint = <&ps8640_in>; + }; + }; + }; +}; + +&dpi0 { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; + ports { + port@1 { + reg = <1>; + + hdmi0_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_phy { + status = "okay"; + mediatek,ibias = <0xc>; +}; + +&i2c0 { + status = "okay"; + + rt5650: audio-codec@1a { + compatible = "realtek,rt5650"; + reg = <0x1a>; + avdd-supply = <&mt6397_vgp1_reg>; + cpvdd-supply = <&mt6397_vcama_reg>; + interrupt-parent = <&pio>; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + pinctrl-names = "default"; + pinctrl-0 = <&rt5650_irq>; + #sound-dai-cells = <1>; + realtek,dmic1-data-pin = <2>; + realtek,jd-mode = <2>; + }; + + ps8640: edp-bridge@8 { + compatible = "parade,ps8640"; + reg = <0x8>; + powerdown-gpios = <&pio 127 GPIO_ACTIVE_LOW>; + reset-gpios = <&pio 115 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ps8640_pins>; + vdd12-supply = <&ps8640_fixed_1v2>; + vdd33-supply = <&mt6397_vgp2_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ps8640_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + ps8640_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <1500000>; + status = "okay"; + + da9211: da9211@68 { + compatible = "dlg,da9211"; + reg = <0x68>; + interrupt-parent = <&pio>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + + regulators { + da9211_vcpu_reg: BUCKA { + regulator-name = "VBUCKA"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1310000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <4400000>; + regulator-ramp-delay = <10000>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + da9211_vgpu_reg: BUCKB { + regulator-name = "VBUCKB"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1310000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <3000000>; + regulator-ramp-delay = <10000>; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + tpm: tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + powered-while-suspended; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&pio>; + interrupts = <88 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_irq>; + + trackpad: trackpad@15 { + compatible = "elan,ekth3000"; + interrupt-parent = <&pio>; + interrupts = <117 IRQ_TYPE_LEVEL_LOW>; + reg = <0x15>; + vcc-supply = <&mt6397_vgp6_reg>; + wakeup-source; + }; +}; + +&mipi_tx0 { + status = "okay"; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + hs400-ds-delay = <0x14015>; + mediatek,hs200-cmd-int-delay=<30>; + mediatek,hs400-cmd-int-delay=<14>; + mediatek,hs400-cmd-resp-sel-rising; + vmmc-supply = <&mt6397_vemc_3v3_reg>; + vqmmc-supply = <&mt6397_vio18_reg>; + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + cd-gpios = <&pio 1 GPIO_ACTIVE_LOW>; + vmmc-supply = <&mt6397_vmch_reg>; + vqmmc-supply = <&mt6397_vmc_reg>; +}; + +&mmc3 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc3_pins_default>; + pinctrl-1 = <&mmc3_pins_uhs>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + keep-power-in-suspend; + enable-sdio-wakeup; + cap-sdio-irq; + vmmc-supply = <&sdio_fixed_3v3>; + vqmmc-supply = <&mt6397_vgp3_reg>; + non-removable; + cap-power-off-card; + + #address-cells = <1>; + #size-cells = <0>; + + btmrvl: btmrvl@2 { + compatible = "marvell,sd8897-bt"; + reg = <2>; + interrupt-parent = <&pio>; + interrupts = <119 IRQ_TYPE_LEVEL_LOW>; + marvell,wakeup-pin = /bits/ 16 <0x0d>; + marvell,wakeup-gap-ms = /bits/ 16 <0x64>; + }; + + mwifiex: mwifiex@1 { + compatible = "marvell,sd8897"; + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_LOW>; + marvell,wakeup-pin = <3>; + }; +}; + +&nor_flash { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nor_gpio1_pins>; + bus-width = <8>; + max-frequency = <50000000>; + non-removable; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + }; +}; + +&pio { + gpio-line-names = "EC_INT_1V8", + "SD_CD_L", + "ALC5514_IRQ", + "ALC5650_IRQ", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it SFWP_B. + */ + "AP_FLASH_WP_L", + "SFIN", + "SFCS0", + "SFHOLD", + "SFOUT", + "SFCK", + "WRAP_EVENT_S_EINT10", + "PMU_INT", + "I2S2_WS_ALC5650", + "I2S2_BCK_ALC5650", + "PWR_BTN_1V8", + "DA9212_IRQ", + "IDDIG", + "WATCHDOG", + "CEC", + "HDMISCK", + "HDMISD", + "HTPLG", + "MSDC3_DAT0", + "MSDC3_DAT1", + "MSDC3_DAT2", + "MSDC3_DAT3", + "MSDC3_CLK", + "MSDC3_CMD", + "USB_C0_OC_FLAGB", + "USBA_OC1_L", + "PS8640_1V2_ENABLE", + "THERM_ALERT_N", + "PANEL_LCD_POWER_EN", + "ANX7688_CHIP_PD_C", + "EC_IN_RW_1V8", + "ANX7688_1V_EN_C", + "USB_DP_HPD_C", + "TPM_DAVINT_N", + "MARVELL8897_IRQ", + "EN_USB_A0_PWR", + "USBA_A0_OC_L", + "EN_PP3300_DX_EDP", + "", + "SOC_I2C2_1V8_SDA_400K", + "SOC_I2C2_1V8_SCL_400K", + "SOC_I2C0_1V8_SDA_400K", + "SOC_I2C0_1V8_SCL_400K", + "EMMC_ID1", + "EMMC_ID0", + "MEM_CONFIG3", + "EMMC_ID2", + "MEM_CONFIG1", + "MEM_CONFIG2", + "BRD_ID2", + "MEM_CONFIG0", + "BRD_ID0", + "BRD_ID1", + "EMMC_DAT0", + "EMMC_DAT1", + "EMMC_DAT2", + "EMMC_DAT3", + "EMMC_DAT4", + "EMMC_DAT5", + "EMMC_DAT6", + "EMMC_DAT7", + "EMMC_CLK", + "EMMC_CMD", + "EMMC_RCLK", + "PLT_RST_L", + "LID_OPEN_1V8_L", + "AUDIO_SPI_MISO_R", + "", + "AC_OK_1V8", + "SD_DATA0", + "SD_DATA1", + "SD_DATA2", + "SD_DATA3", + "SD_CLK", + "SD_CMD", + "PWRAP_SPI0_MI", + "PWRAP_SPI0_MO", + "PWRAP_SPI0_CK", + "PWRAP_SPI0_CSN", + "", + "", + "WIFI_PDN", + "RTC32K_1V8", + "DISP_PWM0", + "TOUCHSCREEN_INT_L", + "", + "SRCLKENA0", + "SRCLKENA1", + "PS8640_MODE_CONF", + "TOUCHSCREEN_RESET_R", + "PLATFORM_PROCHOT_L", + "PANEL_POWER_EN", + "REC_MODE_L", + "EC_FW_UPDATE_L", + "ACCEL2_INT_L", + "HDMI_DP_INT", + "ACCELGYRO3_INT_L", + "ACCELGYRO4_INT_L", + "SPI_EC_CLK", + "SPI_EC_MI", + "SPI_EC_MO", + "SPI_EC_CSN", + "SOC_I2C3_1V8_SDA_400K", + "SOC_I2C3_1V8_SCL_400K", + "", + "", + "", + "", + "", + "", + "", + "PS8640_SYSRSTN_1V8", + "APIN_MAX98090_DOUT2", + "TP_INT_1V8_L_R", + "RST_USB_HUB_R", + "BT_WAKE_L", + "ACCEL1_INT_L", + "TABLET_MODE_L", + "", + "V_UP_IN_L_R", + "V_DOWN_IN_L_R", + "SOC_I2C1_1V8_SDA_1M", + "SOC_I2C1_1V8_SCL_1M", + "PS8640_PDN_1V8", + "MAX98090_LRCLK", + "MAX98090_BCLK", + "MAX98090_MCLK", + "APOUT_MAX98090_DIN", + "APIN_MAX98090_DOUT", + "SOC_I2C4_1V8_SDA_400K", + "SOC_I2C4_1V8_SCL_400K"; + + aud_i2s2: aud_i2s2 { + pins1 { + pinmux = , + , + , + , + , + , + ; + bias-pull-down; + }; + }; + + bl_fixed_pins: bl_fixed_pins { + pins1 { + pinmux = ; + output-low; + }; + }; + + bt_wake_pins: bt_wake_pins { + pins1 { + pinmux = ; + bias-pull-up; + }; + }; + + disp_pwm0_pins: disp_pwm0_pins { + pins1 { + pinmux = ; + output-low; + }; + }; + + gpio_keys_pins: gpio_keys_pins { + volume_pins { + pinmux = , + ; + bias-pull-up; + }; + + tablet_mode_pins { + pinmux = ; + bias-pull-up; + }; + }; + + hdmi_mux_pins: hdmi_mux_pins { + pins1 { + pinmux = ; + }; + }; + + i2c1_pins_a: i2c1 { + da9211_pins { + pinmux = ; + bias-pull-up; + }; + }; + + mmc0_pins_default: mmc0default { + pins_cmd_dat { + pinmux = , + , + , + , + , + , + , + , + ; + bias-pull-up; + }; + + pins_clk { + pinmux = ; + bias-pull-down; + }; + + pins_rst { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1default { + pins_cmd_dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins_clk { + pinmux = ; + bias-pull-down; + drive-strength = ; + }; + + pins_insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc3_pins_default: mmc3default { + pins_dat { + pinmux = , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins_cmd { + pinmux = ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins_clk { + pinmux = ; + bias-pull-down; + drive-strength = ; + }; + }; + + mmc0_pins_uhs: mmc0 { + pins_cmd_dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins_clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins_ds { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins_rst { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_pins_uhs: mmc1 { + pins_cmd_dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins_clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + }; + + mmc3_pins_uhs: mmc3 { + pins_dat { + pinmux = , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins_cmd { + pinmux = ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins_clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + }; + + nor_gpio1_pins: nor { + pins1 { + pinmux = , + , + ; + input-enable; + drive-strength = ; + bias-pull-up; + }; + + pins2 { + pinmux = ; + drive-strength = ; + bias-pull-up; + }; + + pins_clk { + pinmux = ; + input-enable; + drive-strength = ; + bias-pull-up; + }; + }; + + panel_fixed_pins: panel_fixed_pins { + pins1 { + pinmux = ; + }; + }; + + ps8640_pins: ps8640_pins { + pins1 { + pinmux = , + , + ; + }; + }; + + ps8640_fixed_pins: ps8640_fixed_pins { + pins1 { + pinmux = ; + }; + }; + + rt5650_irq: rt5650_irq { + pins1 { + pinmux = ; + bias-pull-down; + }; + }; + + sdio_fixed_3v3_pins: sdio_fixed_3v3_pins { + pins1 { + pinmux = ; + output-low; + }; + }; + + spi_pins_a: spi1 { + pins1 { + pinmux = ; + bias-pull-up; + }; + + pins_spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + trackpad_irq: trackpad_irq { + pins1 { + pinmux = ; + input-enable; + bias-pull-up; + }; + }; + + usb_pins: usb { + pins1 { + pinmux = ; + output-high; + bias-disable; + }; + }; + + wifi_wake_pins: wifi_wake_pins { + pins1 { + pinmux = ; + bias-pull-up; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwrap { + pmic: mt6397 { + compatible = "mediatek,mt6397"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + clock: mt6397clock { + compatible = "mediatek,mt6397-clk"; + #clock-cells = <1>; + }; + + pio6397: pinctrl { + compatible = "mediatek,mt6397-pinctrl"; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + }; + + regulator: mt6397regulator { + compatible = "mediatek,mt6397-regulator"; + + mt6397_vpca15_reg: buck_vpca15 { + regulator-compatible = "buck_vpca15"; + regulator-name = "vpca15"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-allowed-modes = <0 1>; + }; + + mt6397_vpca7_reg: buck_vpca7 { + regulator-compatible = "buck_vpca7"; + regulator-name = "vpca7"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <115>; + regulator-always-on; + }; + + mt6397_vsramca15_reg: buck_vsramca15 { + regulator-compatible = "buck_vsramca15"; + regulator-name = "vsramca15"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vsramca7_reg: buck_vsramca7 { + regulator-compatible = "buck_vsramca7"; + regulator-name = "vsramca7"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vcore_reg: buck_vcore { + regulator-compatible = "buck_vcore"; + regulator-name = "vcore"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vgpu_reg: buck_vgpu { + regulator-compatible = "buck_vgpu"; + regulator-name = "vgpu"; + regulator-min-microvolt = < 700000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <115>; + }; + + mt6397_vdrm_reg: buck_vdrm { + regulator-compatible = "buck_vdrm"; + regulator-name = "vdrm"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vio18_reg: buck_vio18 { + regulator-compatible = "buck_vio18"; + regulator-name = "vio18"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + }; + + mt6397_vtcxo_reg: ldo_vtcxo { + regulator-compatible = "ldo_vtcxo"; + regulator-name = "vtcxo"; + regulator-always-on; + }; + + mt6397_va28_reg: ldo_va28 { + regulator-compatible = "ldo_va28"; + regulator-name = "va28"; + }; + + mt6397_vcama_reg: ldo_vcama { + regulator-compatible = "ldo_vcama"; + regulator-name = "vcama"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vio28_reg: ldo_vio28 { + regulator-compatible = "ldo_vio28"; + regulator-name = "vio28"; + regulator-always-on; + }; + + mt6397_vusb_reg: ldo_vusb { + regulator-compatible = "ldo_vusb"; + regulator-name = "vusb"; + }; + + mt6397_vmc_reg: ldo_vmc { + regulator-compatible = "ldo_vmc"; + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vmch_reg: ldo_vmch { + regulator-compatible = "ldo_vmch"; + regulator-name = "vmch"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vemc_3v3_reg: ldo_vemc3v3 { + regulator-compatible = "ldo_vemc3v3"; + regulator-name = "vemc_3v3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp1_reg: ldo_vgp1 { + regulator-compatible = "ldo_vgp1"; + regulator-name = "vcamd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <240>; + }; + + mt6397_vgp2_reg: ldo_vgp2 { + regulator-compatible = "ldo_vgp2"; + regulator-name = "vcamio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp3_reg: ldo_vgp3 { + regulator-compatible = "ldo_vgp3"; + regulator-name = "vcamaf"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp4_reg: ldo_vgp4 { + regulator-compatible = "ldo_vgp4"; + regulator-name = "vgp4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp5_reg: ldo_vgp5 { + regulator-compatible = "ldo_vgp5"; + regulator-name = "vgp5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <218>; + }; + + mt6397_vgp6_reg: ldo_vgp6 { + regulator-compatible = "ldo_vgp6"; + regulator-name = "vgp6"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + regulator-always-on; + }; + + mt6397_vibr_reg: ldo_vibr { + regulator-compatible = "ldo_vibr"; + regulator-name = "vibr"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <218>; + }; + }; + + rtc: mt6397rtc { + compatible = "mediatek,mt6397-rtc"; + }; + + syscfg_pctl_pmic: syscfg_pctl_pmic@c000 { + compatible = "mediatek,mt6397-pctl-pmic-syscfg", + "syscon"; + reg = <0 0x0000c000 0 0x0108>; + }; + }; +}; + +&spi { + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins_a>; + mediatek,pad-select = <1>; + status = "okay"; + /* clients */ + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0x0>; + spi-max-frequency = <12000000>; + interrupt-parent = <&pio>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + google,cros-ec-spi-msg-delay = <500>; + + i2c_tunnel: i2c-tunnel0 { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <1>; + }; + }; + }; +}; + +&ssusb { + dr_mode = "host"; + wakeup-source; + vusb33-supply = <&mt6397_vusb_reg>; + status = "okay"; +}; + +&thermal { + bank0-supply = <&mt6397_vpca15_reg>; + bank1-supply = <&da9211_vcpu_reg>; +}; + +&uart0 { + status = "okay"; +}; + +&usb_host { + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins>; + vusb33-supply = <&mt6397_vusb_reg>; + status = "okay"; +}; + +#include diff --git a/src/arm64/mediatek/mt8173.dtsi b/src/arm64/mediatek/mt8173.dtsi index d819e44d94a8..70b1ffcab7f0 100644 --- a/src/arm64/mediatek/mt8173.dtsi +++ b/src/arm64/mediatek/mt8173.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include #include "mt8173-pinfunc.h" / { @@ -42,14 +43,18 @@ dpi0 = &dpi0; dsi0 = &dsi0; dsi1 = &dsi1; - mdp_rdma0 = &mdp_rdma0; - mdp_rdma1 = &mdp_rdma1; - mdp_rsz0 = &mdp_rsz0; - mdp_rsz1 = &mdp_rsz1; - mdp_rsz2 = &mdp_rsz2; - mdp_wdma0 = &mdp_wdma0; - mdp_wrot0 = &mdp_wrot0; - mdp_wrot1 = &mdp_wrot1; + mdp-rdma0 = &mdp_rdma0; + mdp-rdma1 = &mdp_rdma1; + mdp-rsz0 = &mdp_rsz0; + mdp-rsz1 = &mdp_rsz1; + mdp-rsz2 = &mdp_rsz2; + mdp-wdma0 = &mdp_wdma0; + mdp-wrot0 = &mdp_wrot0; + mdp-wrot1 = &mdp_wrot1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; }; cluster0_opp: opp_table0 { @@ -162,6 +167,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <526>; }; cpu1: cpu@1 { @@ -176,6 +182,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <526>; }; cpu2: cpu@100 { @@ -190,6 +197,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <1024>; }; cpu3: cpu@101 { @@ -204,6 +212,7 @@ <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <1024>; }; idle-states { @@ -242,21 +251,21 @@ cpu_on = <0x84000003>; }; - clk26m: oscillator@0 { + clk26m: oscillator0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; clock-output-names = "clk26m"; }; - clk32k: oscillator@1 { + clk32k: oscillator1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32000>; clock-output-names = "clk32k"; }; - cpum_ck: oscillator@2 { + cpum_ck: oscillator2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; @@ -272,19 +281,19 @@ sustainable-power = <1500>; /* milliwatts */ trips { - threshold: trip-point@0 { + threshold: trip-point0 { temperature = <68000>; hysteresis = <2000>; type = "passive"; }; - target: trip-point@1 { + target: trip-point1 { temperature = <85000>; hysteresis = <2000>; type = "passive"; }; - cpu_crit: cpu_crit@0 { + cpu_crit: cpu_crit0 { temperature = <115000>; hysteresis = <2000>; type = "critical"; @@ -292,16 +301,20 @@ }; cooling-maps { - map@0 { + map0 { trip = <&target>; - cooling-device = <&cpu0 0 0>, - <&cpu1 0 0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; contribution = <3072>; }; - map@1 { + map1 { trip = <&target>; - cooling-device = <&cpu2 0 0>, - <&cpu3 0 0>; + cooling-device = <&cpu2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; contribution = <1024>; }; }; @@ -312,7 +325,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; - vpu_dma_reserved: vpu_dma_mem_region { + vpu_dma_reserved: vpu_dma_mem_region@b7000000 { compatible = "shared-dma-pool"; reg = <0 0xb7000000 0 0x500000>; alignment = <0x1000>; @@ -365,7 +378,7 @@ reg = <0 0x10005000 0 0x1000>; }; - pio: pinctrl@10005000 { + pio: pinctrl@1000b000 { compatible = "mediatek,mt8173-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; @@ -549,7 +562,7 @@ interrupts = ; clocks = <&infracfg CLK_INFRA_GCE>; clock-names = "gce"; - #mbox-cells = <3>; + #mbox-cells = <2>; }; mipi_tx0: mipi-dphy@10215000 { @@ -572,7 +585,7 @@ status = "disabled"; }; - gic: interrupt-controller@10220000 { + gic: interrupt-controller@10221000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; interrupt-parent = <&gic>; @@ -909,13 +922,16 @@ }; }; - mmsys: clock-controller@14000000 { + mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; assigned-clock-rates = <400000000>; #clock-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; mdp_rdma0: rdma@14001000 { @@ -996,6 +1012,7 @@ clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; ovl1: ovl@1400d000 { @@ -1006,6 +1023,7 @@ clocks = <&mmsys CLK_MM_DISP_OVL1>; iommus = <&iommu M4U_PORT_DISP_OVL1>; mediatek,larb = <&larb4>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; }; rdma0: rdma@1400e000 { @@ -1016,6 +1034,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA0>; iommus = <&iommu M4U_PORT_DISP_RDMA0>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; rdma1: rdma@1400f000 { @@ -1026,6 +1045,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu M4U_PORT_DISP_RDMA1>; mediatek,larb = <&larb4>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; }; rdma2: rdma@14010000 { @@ -1036,6 +1056,7 @@ clocks = <&mmsys CLK_MM_DISP_RDMA2>; iommus = <&iommu M4U_PORT_DISP_RDMA2>; mediatek,larb = <&larb4>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; }; wdma0: wdma@14011000 { @@ -1046,6 +1067,7 @@ clocks = <&mmsys CLK_MM_DISP_WDMA0>; iommus = <&iommu M4U_PORT_DISP_WDMA0>; mediatek,larb = <&larb0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; }; wdma1: wdma@14012000 { @@ -1056,6 +1078,7 @@ clocks = <&mmsys CLK_MM_DISP_WDMA1>; iommus = <&iommu M4U_PORT_DISP_WDMA1>; mediatek,larb = <&larb4>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; }; color0: color@14013000 { @@ -1064,6 +1087,7 @@ interrupts = ; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; }; color1: color@14014000 { @@ -1072,6 +1096,7 @@ interrupts = ; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_COLOR1>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; }; aal@14015000 { @@ -1080,6 +1105,7 @@ interrupts = ; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_AAL>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; }; gamma@14016000 { @@ -1088,6 +1114,7 @@ interrupts = ; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_GAMMA>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; }; merge@14017000 { @@ -1193,6 +1220,8 @@ interrupts = ; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_MUTEX_32K>; + mediatek,gce-events = , + ; }; larb0: larb@14021000 { @@ -1437,4 +1466,3 @@ }; }; }; - diff --git a/src/arm64/mediatek/mt8183-evb.dts b/src/arm64/mediatek/mt8183-evb.dts index 1fb195c683c3..afd6ddbcbdf2 100644 --- a/src/arm64/mediatek/mt8183-evb.dts +++ b/src/arm64/mediatek/mt8183-evb.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "mt8183.dtsi" +#include "mt6358.dtsi" / { model = "MediaTek MT8183 evaluation board"; @@ -72,6 +73,47 @@ clock-frequency = <1000000>; }; +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x12814>; + vmmc-supply = <&mt6358_vemc_reg>; + vqmmc-supply = <&mt6358_vio18_reg>; + assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + cap-sdio-irq; + no-mmc; + no-sd; + vmmc-supply = <&mt6358_vmch_reg>; + vqmmc-supply = <&mt6358_vmc_reg>; + keep-power-in-suspend; + enable-sdio-wakeup; + non-removable; +}; + &pio { i2c_pins_0: i2c0{ pins_i2c{ @@ -137,6 +179,111 @@ }; }; + mmc0_pins_default: mmc0default { + pins_cmd_dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up; + }; + + pins_clk { + pinmux = ; + bias-pull-down; + }; + + pins_rst { + pinmux = ; + bias-pull-up; + }; + }; + + mmc0_pins_uhs: mmc0@0{ + pins_cmd_dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins_clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins_ds { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins_rst { + pinmux = ; + drive-strength = ; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1default { + pins_cmd_dat { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-up; + }; + + pins_clk { + pinmux = ; + input-enable; + bias-pull-down; + }; + + pins_pmu { + pinmux = , + ; + output-high; + }; + }; + + mmc1_pins_uhs: mmc1@0{ + pins_cmd_dat { + pinmux = , + , + , + , + ; + drive-strength = ; + input-enable; + bias-pull-up = ; + }; + + pins_clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + input-enable; + }; + }; + spi_pins_1: spi1{ pins_spi{ pinmux = , diff --git a/src/arm64/mediatek/mt8183.dtsi b/src/arm64/mediatek/mt8183.dtsi index 97863adb7bc0..1e03c849dc5d 100644 --- a/src/arm64/mediatek/mt8183.dtsi +++ b/src/arm64/mediatek/mt8183.dtsi @@ -74,7 +74,7 @@ reg = <0x000>; enable-method = "psci"; capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -85,7 +85,7 @@ reg = <0x001>; enable-method = "psci"; capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -96,7 +96,7 @@ reg = <0x002>; enable-method = "psci"; capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -107,7 +107,7 @@ reg = <0x003>; enable-method = "psci"; capacity-dmips-mhz = <741>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -118,7 +118,7 @@ reg = <0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -129,7 +129,7 @@ reg = <0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -140,7 +140,7 @@ reg = <0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -151,7 +151,7 @@ reg = <0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -168,7 +168,15 @@ min-residency-us = <800>; }; - CLUSTER_SLEEP: cluster-sleep { + CLUSTER_SLEEP0: cluster-sleep@0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x01010001>; + entry-latency-us = <250>; + exit-latency-us = <400>; + min-residency-us = <1000>; + }; + CLUSTER_SLEEP1: cluster-sleep@1 { compatible = "arm,idle-state"; local-timer-stop; arm,psci-suspend-param = <0x01010001>; @@ -640,6 +648,30 @@ #clock-cells = <1>; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11f50000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, + <&infracfg CLK_INFRA_MSDC0>, + <&infracfg CLK_INFRA_MSDC0_SCK>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11e10000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, + <&infracfg CLK_INFRA_MSDC1>, + <&infracfg CLK_INFRA_MSDC1_SCK>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + efuse: efuse@11f10000 { compatible = "mediatek,mt8183-efuse", "mediatek,efuse"; diff --git a/src/arm64/mediatek/mt8516.dtsi b/src/arm64/mediatek/mt8516.dtsi index 2f8adf042195..89af661e7f63 100644 --- a/src/arm64/mediatek/mt8516.dtsi +++ b/src/arm64/mediatek/mt8516.dtsi @@ -191,6 +191,11 @@ #clock-cells = <1>; }; + pericfg: pericfg@10003050 { + compatible = "mediatek,mt8516-pericfg", "syscon"; + reg = <0 0x10003050 0 0x1000>; + }; + apmixedsys: apmixedsys@10018000 { compatible = "mediatek,mt8516-apmixedsys", "syscon"; reg = <0 0x10018000 0 0x710>; @@ -401,6 +406,18 @@ status = "disabled"; }; + ethernet: ethernet@11180000 { + compatible = "mediatek,mt8516-eth"; + reg = <0 0x11180000 0 0x1000>; + mediatek,pericfg = <&pericfg>; + interrupts = ; + clocks = <&topckgen CLK_TOP_RG_ETH>, + <&topckgen CLK_TOP_66M_ETH>, + <&topckgen CLK_TOP_133M_ETH>; + clock-names = "core", "reg", "trans"; + status = "disabled"; + }; + rng: rng@1020c000 { compatible = "mediatek,mt8516-rng", "mediatek,mt7623-rng"; diff --git a/src/arm64/mediatek/pumpkin-common.dtsi b/src/arm64/mediatek/pumpkin-common.dtsi index a31093d7142b..dfceffe6950a 100644 --- a/src/arm64/mediatek/pumpkin-common.dtsi +++ b/src/arm64/mediatek/pumpkin-common.dtsi @@ -9,6 +9,7 @@ / { aliases { serial0 = &uart0; + ethernet0 = ðernet; }; chosen { @@ -166,6 +167,24 @@ status = "okay"; }; +ðernet { + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins_default>; + phy-handle = <ð_phy>; + phy-mode = "rmii"; + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + eth_phy: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + &usb0 { status = "okay"; dr_mode = "peripheral"; @@ -218,4 +237,19 @@ bias-pull-up; }; }; + + ethernet_pins_default: ethernet { + pins_ethernet { + pinmux = , + , + , + , + , + , + , + , + , + ; + }; + }; }; diff --git a/src/arm64/nvidia/tegra132-norrin.dts b/src/arm64/nvidia/tegra132-norrin.dts index a0385a386a3f..9f3206c63900 100644 --- a/src/arm64/nvidia/tegra132-norrin.dts +++ b/src/arm64/nvidia/tegra132-norrin.dts @@ -990,7 +990,7 @@ }; panel: panel { - compatible = "innolux,n116bge", "simple-panel"; + compatible = "innolux,n116bge"; backlight = <&backlight>; ddc-i2c-bus = <&dpaux>; }; diff --git a/src/arm64/nvidia/tegra186-p3310.dtsi b/src/arm64/nvidia/tegra186-p3310.dtsi index da96de04d003..2fcaa2e64370 100644 --- a/src/arm64/nvidia/tegra186-p3310.dtsi +++ b/src/arm64/nvidia/tegra186-p3310.dtsi @@ -221,7 +221,8 @@ compatible = "maxim,max77620"; reg = <0x3c>; - interrupts = ; + interrupt-parent = <&pmc>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; #interrupt-cells = <2>; interrupt-controller; diff --git a/src/arm64/nvidia/tegra194-p2888.dtsi b/src/arm64/nvidia/tegra194-p2888.dtsi index 623f7d7d216b..b96eb4e14556 100644 --- a/src/arm64/nvidia/tegra194-p2888.dtsi +++ b/src/arm64/nvidia/tegra194-p2888.dtsi @@ -33,7 +33,7 @@ phy-reset-gpios = <&gpio TEGRA194_MAIN_GPIO(G, 5) GPIO_ACTIVE_LOW>; phy-handle = <&phy>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; mdio { #address-cells = <1>; @@ -111,7 +111,8 @@ compatible = "maxim,max20024"; reg = <0x3c>; - interrupts = ; + interrupt-parent = <&pmc>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; #interrupt-cells = <2>; interrupt-controller; diff --git a/src/arm64/nvidia/tegra194.dtsi b/src/arm64/nvidia/tegra194.dtsi index f4ede86e32b4..4bc187a4eacd 100644 --- a/src/arm64/nvidia/tegra194.dtsi +++ b/src/arm64/nvidia/tegra194.dtsi @@ -644,6 +644,24 @@ }; }; + usb@3550000 { + compatible = "nvidia,tegra194-xudc"; + reg = <0x03550000 0x8000>, + <0x03558000 0x1000>; + reg-names = "base", "fpci"; + interrupts = ; + clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, + <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA194_CLK_XUSB_SS>, + <&bpmp TEGRA194_CLK_XUSB_FS>; + clock-names = "dev", "ss", "ss_src", "fs_src"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, + <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; + usb@3610000 { compatible = "nvidia,tegra194-xusb"; reg = <0x03610000 0x40000>, @@ -1387,7 +1405,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ + 0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ }; @@ -1432,7 +1450,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ + 0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ }; @@ -1477,7 +1495,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ + 0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ }; @@ -1522,7 +1540,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ + 0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ }; @@ -1567,7 +1585,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ + 0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ }; @@ -1616,7 +1634,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ - 0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ + 0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ }; diff --git a/src/arm64/nvidia/tegra210-p2180.dtsi b/src/arm64/nvidia/tegra210-p2180.dtsi index f87d2437d11c..cc6ed45a2b48 100644 --- a/src/arm64/nvidia/tegra210-p2180.dtsi +++ b/src/arm64/nvidia/tegra210-p2180.dtsi @@ -38,7 +38,8 @@ pmic: pmic@3c { compatible = "maxim,max77620"; reg = <0x3c>; - interrupts = ; + interrupt-parent = <&tegra_pmc>; + interrupts = <51 IRQ_TYPE_LEVEL_LOW>; #interrupt-cells = <2>; interrupt-controller; diff --git a/src/arm64/nvidia/tegra210-p2597.dtsi b/src/arm64/nvidia/tegra210-p2597.dtsi index 313a4c29d37a..b57d837d5fc7 100644 --- a/src/arm64/nvidia/tegra210-p2597.dtsi +++ b/src/arm64/nvidia/tegra210-p2597.dtsi @@ -14,6 +14,16 @@ status = "okay"; }; + vi@54080000 { + status = "okay"; + + avdd-dsi-csi-supply = <&vdd_dsi_csi>; + + csi@838 { + status = "okay"; + }; + }; + sor@54580000 { status = "okay"; diff --git a/src/arm64/nvidia/tegra210-p3450-0000.dts b/src/arm64/nvidia/tegra210-p3450-0000.dts index 21ed1756b889..9bc52fdb393c 100644 --- a/src/arm64/nvidia/tegra210-p3450-0000.dts +++ b/src/arm64/nvidia/tegra210-p3450-0000.dts @@ -90,6 +90,10 @@ dpaux@545c0000 { status = "okay"; }; + + i2c@546c0000 { + status = "okay"; + }; }; gpu@57000000 { @@ -145,7 +149,8 @@ pmic: pmic@3c { compatible = "maxim,max77620"; reg = <0x3c>; - interrupts = ; + interrupt-parent = <&tegra_pmc>; + interrupts = <51 IRQ_TYPE_LEVEL_LOW>; #interrupt-cells = <2>; interrupt-controller; diff --git a/src/arm64/nvidia/tegra210.dtsi b/src/arm64/nvidia/tegra210.dtsi index 64c46ce3849d..08655081f72d 100644 --- a/src/arm64/nvidia/tegra210.dtsi +++ b/src/arm64/nvidia/tegra210.dtsi @@ -137,9 +137,44 @@ vi@54080000 { compatible = "nvidia,tegra210-vi"; - reg = <0x0 0x54080000 0x0 0x00040000>; + reg = <0x0 0x54080000 0x0 0x700>; interrupts = ; status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; + + clocks = <&tegra_car TEGRA210_CLK_VI>; + power-domains = <&pd_venc>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x54080000 0x2000>; + + csi@838 { + compatible = "nvidia,tegra210-csi"; + reg = <0x838 0x1300>; + status = "disabled"; + assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>, + <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <102000000>, + <102000000>, + <102000000>, + <972000000>; + + clocks = <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, + <&tegra_car TEGRA210_CLK_CSI_TPG>; + clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; + power-domains = <&pd_sor>; + }; }; tsec@54100000 { @@ -796,7 +831,9 @@ pd_sor: sor { clocks = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, <&tegra_car TEGRA210_CLK_DSIA>, <&tegra_car TEGRA210_CLK_DSIB>, <&tegra_car TEGRA210_CLK_DPAUX>, @@ -804,7 +841,6 @@ <&tegra_car TEGRA210_CLK_MIPI_CAL>; resets = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, <&tegra_car TEGRA210_CLK_DSIA>, <&tegra_car TEGRA210_CLK_DSIB>, <&tegra_car TEGRA210_CLK_DPAUX>, @@ -838,6 +874,15 @@ reset-names = "vic"; #power-domain-cells = <0>; }; + + pd_venc: venc { + clocks = <&tegra_car TEGRA210_CLK_VI>, + <&tegra_car TEGRA210_CLK_CSI>; + resets = <&mc TEGRA210_MC_RESET_VI>, + <&tegra_car 20>, + <&tegra_car 52>; + #power-domain-cells = <0>; + }; }; sdmmc1_3v3: sdmmc1-3v3 { @@ -893,6 +938,19 @@ interrupts = ; #iommu-cells = <1>; + #reset-cells = <1>; + }; + + emc: external-memory-controller@7001b000 { + compatible = "nvidia,tegra210-emc"; + reg = <0x0 0x7001b000 0x0 0x1000>, + <0x0 0x7001e000 0x0 0x1000>, + <0x0 0x7001f000 0x0 0x1000>; + clocks = <&tegra_car TEGRA210_CLK_EMC>; + clock-names = "emc"; + interrupts = ; + nvidia,memory-controller = <&mc>; + #cooling-cells = <2>; }; sata@70020000 { @@ -1550,6 +1608,18 @@ <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; trips { + dram_nominal: mem-nominal-trip { + temperature = <50000>; + hysteresis = <1000>; + type = "passive"; + }; + + dram_throttle: mem-throttle-trip { + temperature = <70000>; + hysteresis = <1000>; + type = "active"; + }; + mem-shutdown-trip { temperature = <103000>; hysteresis = <0>; @@ -1558,10 +1628,15 @@ }; cooling-maps { - /* - * There are currently no cooling maps, - * because there are no cooling devices. - */ + dram-passive { + cooling-device = <&emc 0 0>; + trip = <&dram_nominal>; + }; + + dram-active { + cooling-device = <&emc 1 1>; + trip = <&dram_throttle>; + }; }; }; diff --git a/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi b/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi deleted file mode 100644 index aff218c1b7b6..000000000000 --- a/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include -#include - -&pm8916_gpios { - - usb_hub_reset_pm: usb_hub_reset_pm { - pinconf { - pins = "gpio3"; - function = PMIC_GPIO_FUNC_NORMAL; - input-disable; - output-high; - }; - }; - - usb_hub_reset_pm_device: usb_hub_reset_pm_device { - pinconf { - pins = "gpio3"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - }; - }; - - usb_sw_sel_pm: usb_sw_sel_pm { - pinconf { - pins = "gpio4"; - function = PMIC_GPIO_FUNC_NORMAL; - power-source = ; - input-disable; - output-high; - }; - }; - - usb_sw_sel_pm_device: usb_sw_sel_pm_device { - pinconf { - pins = "gpio4"; - function = PMIC_GPIO_FUNC_NORMAL; - power-source = ; - input-disable; - output-low; - }; - }; - - pm8916_gpios_leds: pm8916_gpios_leds { - pinconf { - pins = "gpio1", "gpio2"; - function = PMIC_GPIO_FUNC_NORMAL; - output-low; - }; - }; -}; - -&pm8916_mpps { - - pinctrl-names = "default"; - pinctrl-0 = <&ls_exp_gpio_f>; - - ls_exp_gpio_f: pm8916_mpp4 { - pinconf { - pins = "mpp4"; - function = "digital"; - output-low; - power-source = ; // 1.8V - }; - }; - - pm8916_mpps_leds: pm8916_mpps_leds { - pinconf { - pins = "mpp2", "mpp3"; - function = "digital"; - output-low; - }; - }; -}; diff --git a/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi b/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi deleted file mode 100644 index 21d0822f1ca6..000000000000 --- a/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include - -&msmgpio { - - msmgpio_leds: msmgpio_leds { - pinconf { - pins = "gpio21", "gpio120"; - function = "gpio"; - output-low; - }; - }; - - usb_id_default: usb-id-default { - pinmux { - function = "gpio"; - pins = "gpio121"; - }; - - pinconf { - pins = "gpio121"; - drive-strength = <8>; - input-enable; - bias-pull-up; - }; - }; - - adv7533_int_active: adv533_int_active { - pinmux { - function = "gpio"; - pins = "gpio31"; - }; - pinconf { - pins = "gpio31"; - drive-strength = <16>; - bias-disable; - }; - }; - - adv7533_int_suspend: adv7533_int_suspend { - pinmux { - function = "gpio"; - pins = "gpio31"; - }; - pinconf { - pins = "gpio31"; - drive-strength = <2>; - bias-disable; - }; - }; - - adv7533_switch_active: adv7533_switch_active { - pinmux { - function = "gpio"; - pins = "gpio32"; - }; - pinconf { - pins = "gpio32"; - drive-strength = <16>; - bias-disable; - }; - }; - - adv7533_switch_suspend: adv7533_switch_suspend { - pinmux { - function = "gpio"; - pins = "gpio32"; - }; - pinconf { - pins = "gpio32"; - drive-strength = <2>; - bias-disable; - }; - }; - - msm_key_volp_n_default: msm_key_volp_n_default { - pinmux { - function = "gpio"; - pins = "gpio107"; - }; - pinconf { - pins = "gpio107"; - drive-strength = <8>; - input-enable; - bias-pull-up; - }; - }; -}; diff --git a/src/arm64/qcom/apq8016-sbc.dtsi b/src/arm64/qcom/apq8016-sbc.dtsi index 06aab44d798c..8a4b790aa7ff 100644 --- a/src/arm64/qcom/apq8016-sbc.dtsi +++ b/src/arm64/qcom/apq8016-sbc.dtsi @@ -5,10 +5,10 @@ #include "msm8916.dtsi" #include "pm8916.dtsi" -#include "apq8016-sbc-soc-pins.dtsi" -#include "apq8016-sbc-pmic-pins.dtsi" #include #include +#include +#include #include /* @@ -51,6 +51,30 @@ stdout-path = "serial0"; }; + camera_vdddo_1v8: camera-vdddo-1v8 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdddo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + camera_vdda_2v8: camera-vdda-2v8 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdda"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + camera_vddd_1v5: camera-vddd-1v5 { + compatible = "regulator-fixed"; + regulator-name = "camera_vddd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + reserved-memory { ramoops@bff00000{ compatible = "ramoops"; @@ -495,6 +519,27 @@ wcnss@a21b000 { status = "okay"; }; + + tpiu@820000 { status = "okay"; }; + funnel@821000 { status = "okay"; }; + replicator@824000 { status = "okay"; }; + etf@825000 { status = "okay"; }; + etr@826000 { status = "okay"; }; + funnel@841000 { status = "okay"; }; + debug@850000 { status = "okay"; }; + debug@852000 { status = "okay"; }; + debug@854000 { status = "okay"; }; + debug@856000 { status = "okay"; }; + etm@85c000 { status = "okay"; }; + etm@85d000 { status = "okay"; }; + etm@85e000 { status = "okay"; }; + etm@85f000 { status = "okay"; }; + cti@810000 { status = "okay"; }; + cti@811000 { status = "okay"; }; + cti@858000 { status = "okay"; }; + cti@859000 { status = "okay"; }; + cti@85a000 { status = "okay"; }; + cti@85b000 { status = "okay"; }; }; usb2513 { @@ -521,7 +566,7 @@ }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; @@ -538,6 +583,58 @@ }; }; +&camss { + status = "ok"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csiphy0_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 2>; + remote-endpoint = <&ov5640_ep>; + status = "okay"; + }; + }; + }; +}; + +&cci { + status = "ok"; +}; + +&cci_i2c0 { + camera_rear@3b { + compatible = "ovti,ov5640"; + reg = <0x3b>; + + enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>; + reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_rear_default>; + + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "xclk"; + clock-frequency = <23880000>; + + vdddo-supply = <&camera_vdddo_1v8>; + vdda-supply = <&camera_vdda_2v8>; + vddd-supply = <&camera_vddd_1v5>; + + /* No camera mezzanine by default */ + status = "disabled"; + + port { + ov5640_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 2>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; +}; + &spmi_bus { pm8916_0: pm8916@0 { pon@800 { @@ -680,3 +777,157 @@ regulator-max-microvolt = <3337000>; }; }; + +&msmgpio { + msmgpio_leds: msmgpio-leds { + pinconf { + pins = "gpio21", "gpio120"; + function = "gpio"; + output-low; + }; + }; + + usb_id_default: usb-id-default { + pinmux { + function = "gpio"; + pins = "gpio121"; + }; + + pinconf { + pins = "gpio121"; + drive-strength = <8>; + input-enable; + bias-pull-up; + }; + }; + + adv7533_int_active: adv533-int-active { + pinmux { + function = "gpio"; + pins = "gpio31"; + }; + pinconf { + pins = "gpio31"; + drive-strength = <16>; + bias-disable; + }; + }; + + adv7533_int_suspend: adv7533-int-suspend { + pinmux { + function = "gpio"; + pins = "gpio31"; + }; + pinconf { + pins = "gpio31"; + drive-strength = <2>; + bias-disable; + }; + }; + + adv7533_switch_active: adv7533-switch-active { + pinmux { + function = "gpio"; + pins = "gpio32"; + }; + pinconf { + pins = "gpio32"; + drive-strength = <16>; + bias-disable; + }; + }; + + adv7533_switch_suspend: adv7533-switch-suspend { + pinmux { + function = "gpio"; + pins = "gpio32"; + }; + pinconf { + pins = "gpio32"; + drive-strength = <2>; + bias-disable; + }; + }; + + msm_key_volp_n_default: msm-key-volp-n-default { + pinmux { + function = "gpio"; + pins = "gpio107"; + }; + pinconf { + pins = "gpio107"; + drive-strength = <8>; + input-enable; + bias-pull-up; + }; + }; +}; + +&pm8916_gpios { + usb_hub_reset_pm: usb-hub-reset-pm { + pinconf { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + input-disable; + output-high; + }; + }; + + usb_hub_reset_pm_device: usb-hub-reset-pm-device { + pinconf { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + }; + }; + + usb_sw_sel_pm: usb-sw-sel-pm { + pinconf { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = ; + input-disable; + output-high; + }; + }; + + usb_sw_sel_pm_device: usb-sw-sel-pm-device { + pinconf { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = ; + input-disable; + output-low; + }; + }; + + pm8916_gpios_leds: pm8916-gpios-leds { + pinconf { + pins = "gpio1", "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + }; + }; +}; + +&pm8916_mpps { + pinctrl-names = "default"; + pinctrl-0 = <&ls_exp_gpio_f>; + + ls_exp_gpio_f: pm8916-mpp4 { + pinconf { + pins = "mpp4"; + function = "digital"; + output-low; + power-source = ; // 1.8V + }; + }; + + pm8916_mpps_leds: pm8916-mpps-leds { + pinconf { + pins = "mpp2", "mpp3"; + function = "digital"; + output-low; + }; + }; +}; diff --git a/src/arm64/qcom/apq8096-db820c.dtsi b/src/arm64/qcom/apq8096-db820c.dtsi index c4abbccf2bed..defcbd15edf9 100644 --- a/src/arm64/qcom/apq8096-db820c.dtsi +++ b/src/arm64/qcom/apq8096-db820c.dtsi @@ -117,16 +117,6 @@ regulator-max-microvolt = <3700000>; }; - vreg_s8a_l3a_input: vreg-s8a-l3a-input { - compatible = "regulator-fixed"; - regulator-name = "vreg_s8a_l3a_input"; - regulator-always-on; - regulator-boot-on; - - regulator-min-microvolt = <0>; - regulator-max-microvolt = <0>; - }; - wlan_en: wlan-en-1-8v { pinctrl-names = "default"; pinctrl-0 = <&wlan_en_gpios>; @@ -251,6 +241,10 @@ status = "okay"; }; +&mmcc { + vdd-gfx-supply = <&vdd_gfx>; +}; + &msmgpio { gpio-line-names = "[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */ @@ -688,6 +682,15 @@ }; }; +&pmi8994_spmi_regulators { + vdd_gfx: s2@1700 { + reg = <0x1700 0x100>; + regulator-name = "VDD_GFX"; + regulator-min-microvolt = <980000>; + regulator-max-microvolt = <980000>; + }; +}; + &rpm_requests { pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; @@ -704,15 +707,20 @@ vdd_s10-supply = <&vph_pwr>; vdd_s11-supply = <&vph_pwr>; vdd_s12-supply = <&vph_pwr>; + vdd_l1-supply = <&vreg_s1b_1p025>; vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; - vdd_l3_l11-supply = <&vreg_s8a_l3a_input>; + vdd_l3_l11-supply = <&vreg_s3a_1p3>; vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; vdd_l5_l7-supply = <&vreg_s5a_2p15>; vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; vdd_l8_l16_l30-supply = <&vph_pwr>; + vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; + vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; vdd_l14_l15-supply = <&vreg_s5a_2p15>; + vdd_l17_l29-supply = <&vph_pwr_bbyp>; + vdd_l20_l21-supply = <&vph_pwr_bbyp>; vdd_l25-supply = <&vreg_s3a_1p3>; - vdd_lvs1_2-supply = <&vreg_s4a_1p8>; + vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; vreg_s3a_1p3: s3 { regulator-name = "vreg_s3a_1p3"; @@ -895,6 +903,27 @@ regulator-name = "vreg_lvs2a_1p8"; }; }; + + pmi8994-regulators { + compatible = "qcom,rpm-pmi8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_bst_byp-supply = <&vph_pwr>; + + vph_pwr_bbyp: boost-bypass { + regulator-name = "vph_pwr_bbyp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vreg_s1b_1p025: s1 { + regulator-name = "vreg_s1b_1p025"; + regulator-min-microvolt = <1025000>; + regulator-max-microvolt = <1025000>; + }; + }; }; &sdhc2 { diff --git a/src/arm64/qcom/ipq8074-hk01.dts b/src/arm64/qcom/ipq8074-hk01.dts index 70be3f95209b..6754cb0638f4 100644 --- a/src/arm64/qcom/ipq8074-hk01.dts +++ b/src/arm64/qcom/ipq8074-hk01.dts @@ -24,63 +24,61 @@ device_type = "memory"; reg = <0x0 0x40000000 0x0 0x20000000>; }; +}; - soc { - serial@78b3000 { - status = "ok"; - }; +&blsp1_i2c2 { + status = "ok"; +}; - spi@78b5000 { - status = "ok"; +&blsp1_spi1 { + status = "ok"; - m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - }; - }; - - serial@78b1000 { - status = "ok"; - }; - - i2c@78b6000 { - status = "ok"; - }; - - dma@7984000 { - status = "ok"; - }; - - nand@79b0000 { - status = "ok"; - - nand@0 { - reg = <0>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - nand-bus-width = <8>; - }; - }; - - phy@86000 { - status = "ok"; - }; - - phy@8e000 { - status = "ok"; - }; - - pci@20000000 { - status = "ok"; - perst-gpio = <&tlmm 58 0x1>; - }; - - pci@10000000 { - status = "ok"; - perst-gpio = <&tlmm 61 0x1>; - }; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&blsp1_uart3 { + status = "ok"; +}; + +&blsp1_uart5 { + status = "ok"; +}; + +&pcie0 { + status = "ok"; + perst-gpio = <&tlmm 61 0x1>; +}; + +&pcie1 { + status = "ok"; + perst-gpio = <&tlmm 58 0x1>; +}; + +&pcie_phy0 { + status = "ok"; +}; + +&pcie_phy1 { + status = "ok"; +}; + +&qpic_bam { + status = "ok"; +}; + +&qpic_nand { + status = "ok"; + + nand@0 { + reg = <0>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; }; }; diff --git a/src/arm64/qcom/ipq8074.dtsi b/src/arm64/qcom/ipq8074.dtsi index 2b31823d3ccd..5303821300b4 100644 --- a/src/arm64/qcom/ipq8074.dtsi +++ b/src/arm64/qcom/ipq8074.dtsi @@ -10,15 +10,111 @@ model = "Qualcomm Technologies, Inc. IPQ8074"; compatible = "qcom,ipq8074"; + clocks { + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + xo: xo { + compatible = "fixed-clock"; + clock-frequency = <19200000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x1>; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x2>; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + enable-method = "psci"; + reg = <0x3>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <0x2>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + soc: soc { #address-cells = <0x1>; #size-cells = <0x1>; ranges = <0 0 0 0xffffffff>; compatible = "simple-bus"; + pcie_phy0: phy@86000 { + compatible = "qcom,ipq8074-qmp-pcie-phy"; + reg = <0x00086000 0x1000>; + #phy-cells = <0>; + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "pipe_clk"; + clock-output-names = "pcie20_phy0_pipe_clk"; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", + "common"; + status = "disabled"; + }; + + pcie_phy1: phy@8e000 { + compatible = "qcom,ipq8074-qmp-pcie-phy"; + reg = <0x0008e000 0x1000>; + #phy-cells = <0>; + clocks = <&gcc GCC_PCIE1_PIPE_CLK>; + clock-names = "pipe_clk"; + clock-output-names = "pcie20_phy1_pipe_clk"; + + resets = <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names = "phy", + "common"; + status = "disabled"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq8074-pinctrl"; - reg = <0x1000000 0x300000>; + reg = <0x01000000 0x300000>; interrupts = ; gpio-controller; gpio-ranges = <&tlmm 0 0 70>; @@ -66,102 +162,16 @@ }; }; - intc: interrupt-controller@b000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells = <0x3>; - reg = <0xb000000 0x1000>, <0xb002000 0x1000>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - timer@b120000 { - #address-cells = <1>; - #size-cells = <1>; - ranges; - compatible = "arm,armv7-timer-mem"; - reg = <0xb120000 0x1000>; - clock-frequency = <19200000>; - - frame@b120000 { - frame-number = <0>; - interrupts = , - ; - reg = <0xb121000 0x1000>, - <0xb122000 0x1000>; - }; - - frame@b123000 { - frame-number = <1>; - interrupts = ; - reg = <0xb123000 0x1000>; - status = "disabled"; - }; - - frame@b124000 { - frame-number = <2>; - interrupts = ; - reg = <0xb124000 0x1000>; - status = "disabled"; - }; - - frame@b125000 { - frame-number = <3>; - interrupts = ; - reg = <0xb125000 0x1000>; - status = "disabled"; - }; - - frame@b126000 { - frame-number = <4>; - interrupts = ; - reg = <0xb126000 0x1000>; - status = "disabled"; - }; - - frame@b127000 { - frame-number = <5>; - interrupts = ; - reg = <0xb127000 0x1000>; - status = "disabled"; - }; - - frame@b128000 { - frame-number = <6>; - interrupts = ; - reg = <0xb128000 0x1000>; - status = "disabled"; - }; - }; - gcc: gcc@1800000 { compatible = "qcom,gcc-ipq8074"; - reg = <0x1800000 0x80000>; + reg = <0x01800000 0x80000>; #clock-cells = <0x1>; #reset-cells = <0x1>; }; - blsp1_uart5: serial@78b3000 { - compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78b3000 0x200>; - interrupts = ; - clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, - <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; - pinctrl-0 = <&serial_4_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - blsp_dma: dma@7884000 { compatible = "qcom,bam-v1.7.0"; - reg = <0x7884000 0x2b000>; + reg = <0x07884000 0x2b000>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "bam_clk"; @@ -171,7 +181,7 @@ blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; + reg = <0x078af000 0x200>; interrupts = ; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -181,7 +191,7 @@ blsp1_uart3: serial@78b1000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78b1000 0x200>; + reg = <0x078b1000 0x200>; interrupts = ; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -194,11 +204,23 @@ status = "disabled"; }; + blsp1_uart5: serial@78b3000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b3000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-0 = <&serial_4_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + blsp1_spi1: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x78b5000 0x600>; + reg = <0x078b5000 0x600>; interrupts = ; spi-max-frequency = <50000000>; clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, @@ -215,7 +237,7 @@ compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x78b6000 0x600>; + reg = <0x078b6000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; @@ -232,7 +254,7 @@ compatible = "qcom,i2c-qup-v2.2.1"; #address-cells = <1>; #size-cells = <0>; - reg = <0x78b7000 0x600>; + reg = <0x078b7000 0x600>; interrupts = ; clocks = <&gcc GCC_BLSP1_AHB_CLK>, <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; @@ -245,7 +267,7 @@ qpic_bam: dma@7984000 { compatible = "qcom,bam-v1.7.0"; - reg = <0x7984000 0x1a000>; + reg = <0x07984000 0x1a000>; interrupts = ; clocks = <&gcc GCC_QPIC_AHB_CLK>; clock-names = "bam_clk"; @@ -256,7 +278,7 @@ qpic_nand: nand@79b0000 { compatible = "qcom,ipq8074-nand"; - reg = <0x79b0000 0x10000>; + reg = <0x079b0000 0x10000>; #address-cells = <1>; #size-cells = <0>; clocks = <&gcc GCC_QPIC_CLK>, @@ -272,18 +294,139 @@ status = "disabled"; }; - pcie_phy0: phy@86000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x86000 0x1000>; - #phy-cells = <0>; - clocks = <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "pipe_clk"; - clock-output-names = "pcie20_phy0_pipe_clk"; + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <0x3>; + reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + }; - resets = <&gcc GCC_PCIE0_PHY_BCR>, - <&gcc GCC_PCIE0PHY_PHY_BCR>; - reset-names = "phy", - "common"; + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + timer@b120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + clock-frequency = <19200000>; + + frame@b120000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = ; + reg = <0x0b123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = ; + reg = <0x0b124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = ; + reg = <0x0b125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = ; + reg = <0x0b126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = ; + reg = <0x0b127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = ; + reg = <0x0b128000 0x1000>; + status = "disabled"; + }; + }; + + pcie1: pci@10000000 { + compatible = "qcom,pcie-ipq8074"; + reg = <0x10000000 0xf1d + 0x10000f20 0xa8 + 0x00088000 0x2000 + 0x10100000 0x1000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + + phys = <&pcie_phy1>; + phy-names = "pciephy"; + + ranges = <0x81000000 0 0x10200000 0x10200000 + 0 0x100000 /* downstream I/O */ + 0x82000000 0 0x10300000 0x10300000 + 0 0xd00000>; /* non-prefetchable memory */ + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 142 + IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 143 + IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 144 + IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 145 + IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, + <&gcc GCC_PCIE1_AXI_M_CLK>, + <&gcc GCC_PCIE1_AXI_S_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_AUX_CLK>; + clock-names = "iface", + "axi_m", + "axi_s", + "ahb", + "aux"; + resets = <&gcc GCC_PCIE1_PIPE_ARES>, + <&gcc GCC_PCIE1_SLEEP_ARES>, + <&gcc GCC_PCIE1_CORE_STICKY_ARES>, + <&gcc GCC_PCIE1_AXI_MASTER_ARES>, + <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE1_AHB_ARES>, + <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; + reset-names = "pipe", + "sleep", + "sticky", + "axi_m", + "axi_s", + "ahb", + "axi_m_sticky"; status = "disabled"; }; @@ -291,7 +434,7 @@ compatible = "qcom,pcie-ipq8074"; reg = <0x20000000 0xf1d 0x20000f20 0xa8 - 0x80000 0x2000 + 0x00080000 0x2000 0x20100000 0x1000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; @@ -349,148 +492,5 @@ "axi_m_sticky"; status = "disabled"; }; - - pcie_phy1: phy@8e000 { - compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x8e000 0x1000>; - #phy-cells = <0>; - clocks = <&gcc GCC_PCIE1_PIPE_CLK>; - clock-names = "pipe_clk"; - clock-output-names = "pcie20_phy1_pipe_clk"; - - resets = <&gcc GCC_PCIE1_PHY_BCR>, - <&gcc GCC_PCIE1PHY_PHY_BCR>; - reset-names = "phy", - "common"; - status = "disabled"; - }; - - pcie1: pci@10000000 { - compatible = "qcom,pcie-ipq8074"; - reg = <0x10000000 0xf1d - 0x10000f20 0xa8 - 0x88000 0x2000 - 0x10100000 0x1000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - - phys = <&pcie_phy1>; - phy-names = "pciephy"; - - ranges = <0x81000000 0 0x10200000 0x10200000 - 0 0x100000 /* downstream I/O */ - 0x82000000 0 0x10300000 0x10300000 - 0 0xd00000>; /* non-prefetchable memory */ - - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 142 - IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 143 - IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 144 - IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 145 - IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, - <&gcc GCC_PCIE1_AXI_M_CLK>, - <&gcc GCC_PCIE1_AXI_S_CLK>, - <&gcc GCC_PCIE1_AHB_CLK>, - <&gcc GCC_PCIE1_AUX_CLK>; - clock-names = "iface", - "axi_m", - "axi_s", - "ahb", - "aux"; - resets = <&gcc GCC_PCIE1_PIPE_ARES>, - <&gcc GCC_PCIE1_SLEEP_ARES>, - <&gcc GCC_PCIE1_CORE_STICKY_ARES>, - <&gcc GCC_PCIE1_AXI_MASTER_ARES>, - <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, - <&gcc GCC_PCIE1_AHB_ARES>, - <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; - reset-names = "pipe", - "sleep", - "sticky", - "axi_m", - "axi_s", - "ahb", - "axi_m_sticky"; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <0x1>; - #size-cells = <0x0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0x0>; - next-level-cache = <&L2_0>; - enable-method = "psci"; - }; - - CPU1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; - next-level-cache = <&L2_0>; - }; - - CPU2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x2>; - next-level-cache = <&L2_0>; - }; - - CPU3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x3>; - next-level-cache = <&L2_0>; - }; - - L2_0: l2-cache { - compatible = "cache"; - cache-level = <0x2>; - }; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = ; - }; - - clocks { - sleep_clk: sleep_clk { - compatible = "fixed-clock"; - clock-frequency = <32000>; - #clock-cells = <0>; - }; - - xo: xo { - compatible = "fixed-clock"; - clock-frequency = <19200000>; - #clock-cells = <0>; - }; }; }; diff --git a/src/arm64/qcom/msm8916-longcheer-l8150.dts b/src/arm64/qcom/msm8916-longcheer-l8150.dts index d1ccb9472c8b..d5230cb76eb1 100644 --- a/src/arm64/qcom/msm8916-longcheer-l8150.dts +++ b/src/arm64/qcom/msm8916-longcheer-l8150.dts @@ -82,29 +82,6 @@ wcnss@a21b000 { status = "okay"; }; - - /* - * Attempting to enable these devices causes a "synchronous - * external abort". Suspected cause is that the debug power - * domain is not enabled by default on this device. - * Disable these devices for now to avoid the crash. - * - * See: https://lore.kernel.org/linux-arm-msm/20190618202623.GA53651@gerhold.net/ - */ - tpiu@820000 { status = "disabled"; }; - funnel@821000 { status = "disabled"; }; - replicator@824000 { status = "disabled"; }; - etf@825000 { status = "disabled"; }; - etr@826000 { status = "disabled"; }; - funnel@841000 { status = "disabled"; }; - debug@850000 { status = "disabled"; }; - debug@852000 { status = "disabled"; }; - debug@854000 { status = "disabled"; }; - debug@856000 { status = "disabled"; }; - etm@85c000 { status = "disabled"; }; - etm@85d000 { status = "disabled"; }; - etm@85e000 { status = "disabled"; }; - etm@85f000 { status = "disabled"; }; }; // FIXME: Use extcon device provided by charger driver when available @@ -132,7 +109,7 @@ }; &msmgpio { - gpio_keys_default: gpio_keys_default { + gpio_keys_default: gpio-keys-default { pinmux { function = "gpio"; pins = "gpio107"; diff --git a/src/arm64/qcom/msm8916-pins.dtsi b/src/arm64/qcom/msm8916-pins.dtsi index 242aaea68804..e9c00367f7fd 100644 --- a/src/arm64/qcom/msm8916-pins.dtsi +++ b/src/arm64/qcom/msm8916-pins.dtsi @@ -5,7 +5,7 @@ &msmgpio { - blsp1_uart1_default: blsp1_uart1_default { + blsp1_uart1_default: blsp1-uart1-default { pinmux { function = "blsp_uart1"; // TX, RX, CTS_N, RTS_N @@ -20,7 +20,7 @@ }; }; - blsp1_uart1_sleep: blsp1_uart1_sleep { + blsp1_uart1_sleep: blsp1-uart1-sleep { pinmux { function = "gpio"; pins = "gpio0", "gpio1", @@ -34,7 +34,7 @@ }; }; - blsp1_uart2_default: blsp1_uart2_default { + blsp1_uart2_default: blsp1-uart2-default { pinmux { function = "blsp_uart2"; pins = "gpio4", "gpio5"; @@ -46,7 +46,7 @@ }; }; - blsp1_uart2_sleep: blsp1_uart2_sleep { + blsp1_uart2_sleep: blsp1-uart2-sleep { pinmux { function = "gpio"; pins = "gpio4", "gpio5"; @@ -58,12 +58,12 @@ }; }; - spi1_default: spi1_default { + spi1_default: spi1-default { pinmux { function = "blsp_spi1"; pins = "gpio0", "gpio1", "gpio3"; }; - pinmux_cs { + pinmux-cs { function = "gpio"; pins = "gpio2"; }; @@ -72,7 +72,7 @@ drive-strength = <12>; bias-disable; }; - pinconf_cs { + pinconf-cs { pins = "gpio2"; drive-strength = <16>; bias-disable; @@ -80,7 +80,7 @@ }; }; - spi1_sleep: spi1_sleep { + spi1_sleep: spi1-sleep { pinmux { function = "gpio"; pins = "gpio0", "gpio1", "gpio2", "gpio3"; @@ -92,12 +92,12 @@ }; }; - spi2_default: spi2_default { + spi2_default: spi2-default { pinmux { function = "blsp_spi2"; pins = "gpio4", "gpio5", "gpio7"; }; - pinmux_cs { + pinmux-cs { function = "gpio"; pins = "gpio6"; }; @@ -106,7 +106,7 @@ drive-strength = <12>; bias-disable; }; - pinconf_cs { + pinconf-cs { pins = "gpio6"; drive-strength = <16>; bias-disable; @@ -114,7 +114,7 @@ }; }; - spi2_sleep: spi2_sleep { + spi2_sleep: spi2-sleep { pinmux { function = "gpio"; pins = "gpio4", "gpio5", "gpio6", "gpio7"; @@ -126,12 +126,12 @@ }; }; - spi3_default: spi3_default { + spi3_default: spi3-default { pinmux { function = "blsp_spi3"; pins = "gpio8", "gpio9", "gpio11"; }; - pinmux_cs { + pinmux-cs { function = "gpio"; pins = "gpio10"; }; @@ -140,7 +140,7 @@ drive-strength = <12>; bias-disable; }; - pinconf_cs { + pinconf-cs { pins = "gpio10"; drive-strength = <16>; bias-disable; @@ -148,7 +148,7 @@ }; }; - spi3_sleep: spi3_sleep { + spi3_sleep: spi3-sleep { pinmux { function = "gpio"; pins = "gpio8", "gpio9", "gpio10", "gpio11"; @@ -160,12 +160,12 @@ }; }; - spi4_default: spi4_default { + spi4_default: spi4-default { pinmux { function = "blsp_spi4"; pins = "gpio12", "gpio13", "gpio15"; }; - pinmux_cs { + pinmux-cs { function = "gpio"; pins = "gpio14"; }; @@ -174,7 +174,7 @@ drive-strength = <12>; bias-disable; }; - pinconf_cs { + pinconf-cs { pins = "gpio14"; drive-strength = <16>; bias-disable; @@ -182,7 +182,7 @@ }; }; - spi4_sleep: spi4_sleep { + spi4_sleep: spi4-sleep { pinmux { function = "gpio"; pins = "gpio12", "gpio13", "gpio14", "gpio15"; @@ -194,12 +194,12 @@ }; }; - spi5_default: spi5_default { + spi5_default: spi5-default { pinmux { function = "blsp_spi5"; pins = "gpio16", "gpio17", "gpio19"; }; - pinmux_cs { + pinmux-cs { function = "gpio"; pins = "gpio18"; }; @@ -208,7 +208,7 @@ drive-strength = <12>; bias-disable; }; - pinconf_cs { + pinconf-cs { pins = "gpio18"; drive-strength = <16>; bias-disable; @@ -216,7 +216,7 @@ }; }; - spi5_sleep: spi5_sleep { + spi5_sleep: spi5-sleep { pinmux { function = "gpio"; pins = "gpio16", "gpio17", "gpio18", "gpio19"; @@ -228,12 +228,12 @@ }; }; - spi6_default: spi6_default { + spi6_default: spi6-default { pinmux { function = "blsp_spi6"; pins = "gpio20", "gpio21", "gpio23"; }; - pinmux_cs { + pinmux-cs { function = "gpio"; pins = "gpio22"; }; @@ -242,7 +242,7 @@ drive-strength = <12>; bias-disable; }; - pinconf_cs { + pinconf-cs { pins = "gpio22"; drive-strength = <16>; bias-disable; @@ -250,7 +250,7 @@ }; }; - spi6_sleep: spi6_sleep { + spi6_sleep: spi6-sleep { pinmux { function = "gpio"; pins = "gpio20", "gpio21", "gpio22", "gpio23"; @@ -262,7 +262,31 @@ }; }; - i2c2_default: i2c2_default { + i2c1_default: i2c1-default { + pinmux { + function = "blsp_i2c1"; + pins = "gpio2", "gpio3"; + }; + pinconf { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c1_sleep: i2c1-sleep { + pinmux { + function = "gpio"; + pins = "gpio2", "gpio3"; + }; + pinconf { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c2_default: i2c2-default { pinmux { function = "blsp_i2c2"; pins = "gpio6", "gpio7"; @@ -274,7 +298,7 @@ }; }; - i2c2_sleep: i2c2_sleep { + i2c2_sleep: i2c2-sleep { pinmux { function = "gpio"; pins = "gpio6", "gpio7"; @@ -286,7 +310,7 @@ }; }; - i2c4_default: i2c4_default { + i2c4_default: i2c4-default { pinmux { function = "blsp_i2c4"; pins = "gpio14", "gpio15"; @@ -298,7 +322,7 @@ }; }; - i2c4_sleep: i2c4_sleep { + i2c4_sleep: i2c4-sleep { pinmux { function = "gpio"; pins = "gpio14", "gpio15"; @@ -310,7 +334,31 @@ }; }; - i2c6_default: i2c6_default { + i2c5_default: i2c5-default { + pinmux { + function = "blsp_i2c5"; + pins = "gpio18", "gpio19"; + }; + pinconf { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c5_sleep: i2c5-sleep { + pinmux { + function = "gpio"; + pins = "gpio18", "gpio19"; + }; + pinconf { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c6_default: i2c6-default { pinmux { function = "blsp_i2c6"; pins = "gpio22", "gpio23"; @@ -322,7 +370,7 @@ }; }; - i2c6_sleep: i2c6_sleep { + i2c6_sleep: i2c6-sleep { pinmux { function = "gpio"; pins = "gpio22", "gpio23"; @@ -334,8 +382,8 @@ }; }; - pmx_sdc1_clk { - sdc1_clk_on: clk_on { + pmx-sdc1-clk { + sdc1_clk_on: clk-on { pinmux { pins = "sdc1_clk"; }; @@ -345,7 +393,7 @@ drive-strength = <16>; }; }; - sdc1_clk_off: clk_off { + sdc1_clk_off: clk-off { pinmux { pins = "sdc1_clk"; }; @@ -357,8 +405,8 @@ }; }; - pmx_sdc1_cmd { - sdc1_cmd_on: cmd_on { + pmx-sdc1-cmd { + sdc1_cmd_on: cmd-on { pinmux { pins = "sdc1_cmd"; }; @@ -368,7 +416,7 @@ drive-strength = <10>; }; }; - sdc1_cmd_off: cmd_off { + sdc1_cmd_off: cmd-off { pinmux { pins = "sdc1_cmd"; }; @@ -380,8 +428,8 @@ }; }; - pmx_sdc1_data { - sdc1_data_on: data_on { + pmx-sdc1-data { + sdc1_data_on: data-on { pinmux { pins = "sdc1_data"; }; @@ -391,7 +439,7 @@ drive-strength = <10>; }; }; - sdc1_data_off: data_off { + sdc1_data_off: data-off { pinmux { pins = "sdc1_data"; }; @@ -403,8 +451,8 @@ }; }; - pmx_sdc2_clk { - sdc2_clk_on: clk_on { + pmx-sdc2-clk { + sdc2_clk_on: clk-on { pinmux { pins = "sdc2_clk"; }; @@ -414,7 +462,7 @@ drive-strength = <16>; }; }; - sdc2_clk_off: clk_off { + sdc2_clk_off: clk-off { pinmux { pins = "sdc2_clk"; }; @@ -426,8 +474,8 @@ }; }; - pmx_sdc2_cmd { - sdc2_cmd_on: cmd_on { + pmx-sdc2-cmd { + sdc2_cmd_on: cmd-on { pinmux { pins = "sdc2_cmd"; }; @@ -437,7 +485,7 @@ drive-strength = <10>; }; }; - sdc2_cmd_off: cmd_off { + sdc2_cmd_off: cmd-off { pinmux { pins = "sdc2_cmd"; }; @@ -449,8 +497,8 @@ }; }; - pmx_sdc2_data { - sdc2_data_on: data_on { + pmx-sdc2-data { + sdc2_data_on: data-on { pinmux { pins = "sdc2_data"; }; @@ -460,7 +508,7 @@ drive-strength = <10>; }; }; - sdc2_data_off: data_off { + sdc2_data_off: data-off { pinmux { pins = "sdc2_data"; }; @@ -472,8 +520,8 @@ }; }; - pmx_sdc2_cd_pin { - sdc2_cd_on: cd_on { + pmx-sdc2-cd-pin { + sdc2_cd_on: cd-on { pinmux { function = "gpio"; pins = "gpio38"; @@ -484,7 +532,7 @@ bias-pull-up; }; }; - sdc2_cd_off: cd_off { + sdc2_cd_off: cd-off { pinmux { function = "gpio"; pins = "gpio38"; @@ -498,7 +546,7 @@ }; cdc-pdm-lines { - cdc_pdm_lines_act: pdm_lines_on { + cdc_pdm_lines_act: pdm-lines-on { pinmux { function = "cdc_pdm0"; pins = "gpio63", "gpio64", "gpio65", "gpio66", @@ -511,7 +559,7 @@ bias-pull-none; }; }; - cdc_pdm_lines_sus: pdm_lines_off { + cdc_pdm_lines_sus: pdm-lines-off { pinmux { function = "cdc_pdm0"; pins = "gpio63", "gpio64", "gpio65", "gpio66", @@ -527,7 +575,7 @@ }; ext-pri-tlmm-lines { - ext_pri_tlmm_lines_act: ext_pa_on { + ext_pri_tlmm_lines_act: ext-pa-on { pinmux { function = "pri_mi2s"; pins = "gpio113", "gpio114", "gpio115", @@ -541,7 +589,7 @@ }; }; - ext_pri_tlmm_lines_sus: ext_pa_off { + ext_pri_tlmm_lines_sus: ext-pa-off { pinmux { function = "pri_mi2s"; pins = "gpio113", "gpio114", "gpio115", @@ -557,7 +605,7 @@ }; ext-pri-ws-line { - ext_pri_ws_act: ext_pa_on { + ext_pri_ws_act: ext-pa-on { pinmux { function = "pri_mi2s_ws"; pins = "gpio110"; @@ -569,7 +617,7 @@ }; }; - ext_pri_ws_sus: ext_pa_off { + ext_pri_ws_sus: ext-pa-off { pinmux { function = "pri_mi2s_ws"; pins = "gpio110"; @@ -583,7 +631,7 @@ }; ext-mclk-tlmm-lines { - ext_mclk_tlmm_lines_act: mclk_lines_on { + ext_mclk_tlmm_lines_act: mclk-lines-on { pinmux { function = "pri_mi2s"; pins = "gpio116"; @@ -594,7 +642,7 @@ bias-pull-none; }; }; - ext_mclk_tlmm_lines_sus: mclk_lines_off { + ext_mclk_tlmm_lines_sus: mclk-lines-off { pinmux { function = "pri_mi2s"; pins = "gpio116"; @@ -609,7 +657,7 @@ /* secondary Mi2S */ ext-sec-tlmm-lines { - ext_sec_tlmm_lines_act: tlmm_lines_on { + ext_sec_tlmm_lines_act: tlmm-lines-on { pinmux { function = "sec_mi2s"; pins = "gpio112", "gpio117", "gpio118", @@ -622,7 +670,7 @@ bias-pull-none; }; }; - ext_sec_tlmm_lines_sus: tlmm_lines_off { + ext_sec_tlmm_lines_sus: tlmm-lines-off { pinmux { function = "sec_mi2s"; pins = "gpio112", "gpio117", "gpio118", @@ -638,12 +686,12 @@ }; cdc-dmic-lines { - cdc_dmic_lines_act: dmic_lines_on { - pinmux_dmic0_clk { + cdc_dmic_lines_act: dmic-lines-on { + pinmux-dmic0-clk { function = "dmic0_clk"; pins = "gpio0"; }; - pinmux_dmic0_data { + pinmux-dmic0-data { function = "dmic0_data"; pins = "gpio1"; }; @@ -652,12 +700,12 @@ drive-strength = <8>; }; }; - cdc_dmic_lines_sus: dmic_lines_off { - pinmux_dmic0_clk { + cdc_dmic_lines_sus: dmic-lines-off { + pinmux-dmic0-clk { function = "dmic0_clk"; pins = "gpio0"; }; - pinmux_dmic0_data { + pinmux-dmic0-data { function = "dmic0_data"; pins = "gpio1"; }; @@ -674,7 +722,6 @@ pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; function = "wcss_wlan"; }; - pinconf { pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; drive-strength = <6>; @@ -682,7 +729,7 @@ }; }; - cci0_default: cci0_default { + cci0_default: cci0-default { pinmux { function = "cci_i2c"; pins = "gpio29", "gpio30"; @@ -694,64 +741,64 @@ }; }; - camera_front_default: camera_front_default { - pinmux_pwdn { + camera_front_default: camera-front-default { + pinmux-pwdn { function = "gpio"; pins = "gpio33"; }; - pinconf_pwdn { + pinconf-pwdn { pins = "gpio33"; drive-strength = <16>; bias-disable; }; - pinmux_rst { + pinmux-rst { function = "gpio"; pins = "gpio28"; }; - pinconf_rst { + pinconf-rst { pins = "gpio28"; drive-strength = <16>; bias-disable; }; - pinmux_mclk1 { + pinmux-mclk1 { function = "cam_mclk1"; pins = "gpio27"; }; - pinconf_mclk1 { + pinconf-mclk1 { pins = "gpio27"; drive-strength = <16>; bias-disable; }; }; - camera_rear_default: camera_rear_default { - pinmux_pwdn { + camera_rear_default: camera-rear-default { + pinmux-pwdn { function = "gpio"; pins = "gpio34"; }; - pinconf_pwdn { + pinconf-pwdn { pins = "gpio34"; drive-strength = <16>; bias-disable; }; - pinmux_rst { + pinmux-rst { function = "gpio"; pins = "gpio35"; }; - pinconf_rst { + pinconf-rst { pins = "gpio35"; drive-strength = <16>; bias-disable; }; - pinmux_mclk0 { + pinmux-mclk0 { function = "cam_mclk0"; pins = "gpio26"; }; - pinconf_mclk0 { + pinconf-mclk0 { pins = "gpio26"; drive-strength = <16>; bias-disable; diff --git a/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi b/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi index 43c5e0f882f1..ea52adf07a4b 100644 --- a/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi +++ b/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi @@ -72,32 +72,27 @@ }; }; + mdss@1a00000 { + dsi@1a98000 { + #address-cells = <1>; + #size-cells = <0>; + + vdda-supply = <&pm8916_l2>; + vddio-supply = <&pm8916_l6>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdss_default>; + pinctrl-1 = <&mdss_sleep>; + }; + + dsi-phy@1a98300 { + vddio-supply = <&pm8916_l6>; + }; + }; + wcnss@a21b000 { status = "okay"; }; - - /* - * Attempting to enable these devices causes a "synchronous - * external abort". Suspected cause is that the debug power - * domain is not enabled by default on this device. - * Disable these devices for now to avoid the crash. - * - * See: https://lore.kernel.org/linux-arm-msm/20190618202623.GA53651@gerhold.net/ - */ - tpiu@820000 { status = "disabled"; }; - funnel@821000 { status = "disabled"; }; - replicator@824000 { status = "disabled"; }; - etf@825000 { status = "disabled"; }; - etr@826000 { status = "disabled"; }; - funnel@841000 { status = "disabled"; }; - debug@850000 { status = "disabled"; }; - debug@852000 { status = "disabled"; }; - debug@854000 { status = "disabled"; }; - debug@856000 { status = "disabled"; }; - etm@85c000 { status = "disabled"; }; - etm@85d000 { status = "disabled"; }; - etm@85e000 { status = "disabled"; }; - etm@85f000 { status = "disabled"; }; }; gpio-keys { @@ -138,6 +133,19 @@ }; }; + reg_vdd_tsp: regulator-vdd-tsp { + compatible = "regulator-fixed"; + regulator-name = "vdd_tsp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&msmgpio 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&tsp_en_default>; + }; + i2c-muic { compatible = "i2c-gpio"; sda-gpios = <&msmgpio 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; @@ -160,7 +168,7 @@ }; &msmgpio { - gpio_keys_default: gpio_keys_default { + gpio_keys_default: gpio-keys-default { pinmux { function = "gpio"; pins = "gpio107", "gpio109"; @@ -172,7 +180,7 @@ }; }; - gpio_hall_sensor_default: gpio_hall_sensor_default { + gpio_hall_sensor_default: gpio-hall-sensor-default { pinmux { function = "gpio"; pins = "gpio52"; @@ -184,7 +192,7 @@ }; }; - muic_int_default: muic_int_default { + muic_int_default: muic-int-default { pinmux { function = "gpio"; pins = "gpio12"; @@ -195,6 +203,44 @@ bias-disable; }; }; + + tsp_en_default: tsp-en-default { + pinmux { + function = "gpio"; + pins = "gpio73"; + }; + pinconf { + pins = "gpio73"; + drive-strength = <2>; + bias-disable; + }; + }; + + pmx-mdss { + mdss_default: mdss-default { + pinmux { + function = "gpio"; + pins = "gpio25"; + }; + pinconf { + pins = "gpio25"; + drive-strength = <8>; + bias-disable; + }; + }; + + mdss_sleep: mdss-sleep { + pinmux { + function = "gpio"; + pins = "gpio25"; + }; + pinconf { + pins = "gpio25"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; }; &smd_rpm_regulators { diff --git a/src/arm64/qcom/msm8916-samsung-a3u-eur.dts b/src/arm64/qcom/msm8916-samsung-a3u-eur.dts index d10f7ac5089f..b46c87289033 100644 --- a/src/arm64/qcom/msm8916-samsung-a3u-eur.dts +++ b/src/arm64/qcom/msm8916-samsung-a3u-eur.dts @@ -7,4 +7,58 @@ / { model = "Samsung Galaxy A3U (EUR)"; compatible = "samsung,a3u-eur", "qcom,msm8916"; + + reg_panel_vdd3: regulator-panel-vdd3 { + compatible = "regulator-fixed"; + regulator-name = "panel_vdd3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&msmgpio 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_vdd3_default>; + }; +}; + +&dsi0 { + panel@0 { + reg = <0>; + + compatible = "samsung,s6e88a0-ams452ef01"; + + vdd3-supply = <®_panel_vdd3>; + vci-supply = <&pm8916_l17>; + reset-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + + ports { + port@1 { + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1>; + }; + }; + }; +}; + +&msmgpio { + panel_vdd3_default: panel-vdd3-default { + pinmux { + function = "gpio"; + pins = "gpio9"; + }; + pinconf { + pins = "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; }; diff --git a/src/arm64/qcom/msm8916-samsung-a5u-eur.dts b/src/arm64/qcom/msm8916-samsung-a5u-eur.dts index 6629a621139c..a555db8f6b34 100644 --- a/src/arm64/qcom/msm8916-samsung-a5u-eur.dts +++ b/src/arm64/qcom/msm8916-samsung-a5u-eur.dts @@ -9,8 +9,43 @@ compatible = "samsung,a5u-eur", "qcom,msm8916"; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen@48 { + compatible = "melfas,mms345l"; + + reg = <0x48>; + interrupt-parent = <&msmgpio>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + avdd-supply = <®_vdd_tsp>; + vdd-supply = <&pm8916_l6>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default>; + }; +}; + &pronto { iris { compatible = "qcom,wcn3680"; }; }; + +&msmgpio { + ts_int_default: ts-int-default { + pinmux { + function = "gpio"; + pins = "gpio13"; + }; + pinconf { + pins = "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; +}; diff --git a/src/arm64/qcom/msm8916.dtsi b/src/arm64/qcom/msm8916.dtsi index a88a15f2352b..32bd140ac9fd 100644 --- a/src/arm64/qcom/msm8916.dtsi +++ b/src/arm64/qcom/msm8916.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -165,6 +166,9 @@ min-residency-us = <2000>; local-timer-stop; }; + }; + + domain-idle-states { CLUSTER_RET: cluster-retention { compatible = "domain-idle-state"; @@ -188,31 +192,31 @@ compatible = "arm,psci-1.0"; method = "smc"; - CPU_PD0: cpu-pd0 { + CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&CPU_SLEEP_0>; }; - CPU_PD1: cpu-pd1 { + CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&CPU_SLEEP_0>; }; - CPU_PD2: cpu-pd2 { + CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&CPU_SLEEP_0>; }; - CPU_PD3: cpu-pd3 { + CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; domain-idle-states = <&CPU_SLEEP_0>; }; - CLUSTER_PD: cluster-pd { + CLUSTER_PD: power-domain-cluster { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; }; @@ -261,7 +265,7 @@ thermal-sensors = <&tsens 4>; trips { - cpu2_3_alert0: trip-point@0 { + cpu2_3_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -291,7 +295,7 @@ thermal-sensors = <&tsens 2>; trips { - gpu_alert0: trip-point@0 { + gpu_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -311,7 +315,7 @@ thermal-sensors = <&tsens 1>; trips { - cam_alert0: trip-point@0 { + cam_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "hot"; @@ -326,7 +330,7 @@ thermal-sensors = <&tsens 0>; trips { - modem_alert0: trip-point@0 { + modem_alert0: trip-point0 { temperature = <85000>; hysteresis = <2000>; type = "hot"; @@ -336,7 +340,7 @@ }; - cpu_opp_table: cpu_opp_table { + cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; @@ -354,17 +358,6 @@ }; }; - gpu_opp_table: opp_table { - compatible = "operating-points-v2"; - - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - }; - }; - timer { compatible = "arm,armv8-timer"; interrupts = , @@ -374,13 +367,13 @@ }; clocks { - xo_board: xo_board { + xo_board: xo-board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; }; - sleep_clk: sleep_clk { + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -608,6 +601,21 @@ status = "disabled"; }; + blsp_i2c1: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b5000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp_i2c2: i2c@78b6000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b6000 0x500>; @@ -638,6 +646,21 @@ status = "disabled"; }; + blsp_i2c5: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x500>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_default>; + pinctrl-1 = <&i2c5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp_i2c6: i2c@78ba000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078ba000 0x500>; @@ -955,6 +978,17 @@ power-domains = <&gcc OXILI_GDSC>; operating-points-v2 = <&gpu_opp_table>; iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + }; + }; }; mdss: mdss@1a00000 { @@ -1224,6 +1258,8 @@ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; + status = "disabled"; + in-ports { port { tpiu_in: endpoint { @@ -1240,6 +1276,8 @@ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; + status = "disabled"; + in-ports { #address-cells = <1>; #size-cells = <0>; @@ -1279,6 +1317,8 @@ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; + status = "disabled"; + out-ports { #address-cells = <1>; #size-cells = <0>; @@ -1313,6 +1353,8 @@ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; + status = "disabled"; + in-ports { port { etf_in: endpoint { @@ -1337,6 +1379,8 @@ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; + status = "disabled"; + in-ports { port { etr_in: endpoint { @@ -1353,6 +1397,8 @@ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; + status = "disabled"; + in-ports { #address-cells = <1>; #size-cells = <0>; @@ -1398,6 +1444,7 @@ clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU0>; + status = "disabled"; }; debug@852000 { @@ -1406,6 +1453,7 @@ clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU1>; + status = "disabled"; }; debug@854000 { @@ -1414,6 +1462,7 @@ clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU2>; + status = "disabled"; }; debug@856000 { @@ -1422,9 +1471,10 @@ clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; cpu = <&CPU3>; + status = "disabled"; }; - etm@85c000 { + etm0: etm@85c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85c000 0x1000>; @@ -1434,6 +1484,8 @@ cpu = <&CPU0>; + status = "disabled"; + out-ports { port { etm0_out: endpoint { @@ -1443,7 +1495,7 @@ }; }; - etm@85d000 { + etm1: etm@85d000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85d000 0x1000>; @@ -1453,6 +1505,8 @@ cpu = <&CPU1>; + status = "disabled"; + out-ports { port { etm1_out: endpoint { @@ -1462,7 +1516,7 @@ }; }; - etm@85e000 { + etm2: etm@85e000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85e000 0x1000>; @@ -1472,6 +1526,8 @@ cpu = <&CPU2>; + status = "disabled"; + out-ports { port { etm2_out: endpoint { @@ -1481,7 +1537,7 @@ }; }; - etm@85f000 { + etm3: etm@85f000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85f000 0x1000>; @@ -1491,6 +1547,8 @@ cpu = <&CPU3>; + status = "disabled"; + out-ports { port { etm3_out: endpoint { @@ -1500,6 +1558,93 @@ }; }; + /* System CTIs */ + /* CTI 0 - TMC connections */ + cti@810000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + /* CTI 1 - TPIU connections */ + cti@811000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x811000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + /* CTIs 2-11 - no information - not instantiated */ + + /* Core CTIs; CTIs 12-15 */ + /* CTI - CPU-0 */ + cti@858000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + arm,cs-dev-assoc = <&etm0>; + + status = "disabled"; + }; + + /* CTI - CPU-1 */ + cti@859000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x859000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; + + status = "disabled"; + }; + + /* CTI - CPU-2 */ + cti@85a000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85a000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + arm,cs-dev-assoc = <&etm2>; + + status = "disabled"; + }; + + /* CTI - CPU-3 */ + cti@85b000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x85b000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + arm,cs-dev-assoc = <&etm3>; + + status = "disabled"; + }; + + venus: video-codec@1d00000 { compatible = "qcom,msm8916-venus"; reg = <0x01d00000 0xff000>; @@ -1601,6 +1746,33 @@ #size-cells = <0>; }; }; + + cci: cci@1b0c000 { + compatible = "qcom,msm8916-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1b0c000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", "cci_ahb", + "cci", "camss_ahb"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, <19200000>; + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default>; + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; smd { @@ -1611,7 +1783,7 @@ qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - rpm_requests { + rpm-requests { compatible = "qcom,rpm-msm8916"; qcom,smd-channels = "rpm_requests"; diff --git a/src/arm64/qcom/msm8996.dtsi b/src/arm64/qcom/msm8996.dtsi index 98634d5c4440..9951286db775 100644 --- a/src/arm64/qcom/msm8996.dtsi +++ b/src/arm64/qcom/msm8996.dtsi @@ -639,7 +639,7 @@ "mem", "mem_iface"; - power-domains = <&mmcc GPU_GDSC>; + power-domains = <&mmcc GPU_GX_GDSC>; iommus = <&adreno_smmu 0>; nvmem-cells = <&gpu_speed_bin>; @@ -989,16 +989,16 @@ "csi_clk_mux", "vfe0", "vfe1"; - interrupts = , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + ; interrupt-names = "csiphy0", "csiphy1", "csiphy2", @@ -1093,6 +1093,43 @@ }; }; + cci: cci@a0c000 { + compatible = "qcom,msm8996-cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xa0c000 0x1000>; + interrupts = ; + power-domains = <&mmcc CAMSS_GDSC>; + clocks = <&mmcc CAMSS_TOP_AHB_CLK>, + <&mmcc CAMSS_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CLK>, + <&mmcc CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, + <&mmcc CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + pinctrl-names = "default"; + pinctrl-0 = <&cci0_default &cci1_default>; + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + adreno_smmu: iommu@b40000 { compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; reg = <0x00b40000 0x10000>; @@ -2180,7 +2217,7 @@ thermal-sensors = <&tsens0 3>; trips { - cpu0_alert0: trip-point@0 { + cpu0_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -2201,7 +2238,7 @@ thermal-sensors = <&tsens0 5>; trips { - cpu1_alert0: trip-point@0 { + cpu1_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -2222,7 +2259,7 @@ thermal-sensors = <&tsens0 8>; trips { - cpu2_alert0: trip-point@0 { + cpu2_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -2243,7 +2280,7 @@ thermal-sensors = <&tsens0 10>; trips { - cpu3_alert0: trip-point@0 { + cpu3_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -2264,7 +2301,7 @@ thermal-sensors = <&tsens1 6>; trips { - gpu1_alert0: trip-point@0 { + gpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2279,7 +2316,7 @@ thermal-sensors = <&tsens1 7>; trips { - gpu2_alert0: trip-point@0 { + gpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2294,7 +2331,7 @@ thermal-sensors = <&tsens0 1>; trips { - m4m_alert0: trip-point@0 { + m4m_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2309,7 +2346,7 @@ thermal-sensors = <&tsens0 2>; trips { - l3_or_venus_alert0: trip-point@0 { + l3_or_venus_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2324,7 +2361,7 @@ thermal-sensors = <&tsens0 7>; trips { - cluster0_l2_alert0: trip-point@0 { + cluster0_l2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2339,7 +2376,7 @@ thermal-sensors = <&tsens0 12>; trips { - cluster1_l2_alert0: trip-point@0 { + cluster1_l2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2354,7 +2391,7 @@ thermal-sensors = <&tsens1 1>; trips { - camera_alert0: trip-point@0 { + camera_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2369,7 +2406,7 @@ thermal-sensors = <&tsens1 2>; trips { - q6_dsp_alert0: trip-point@0 { + q6_dsp_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2384,7 +2421,7 @@ thermal-sensors = <&tsens1 3>; trips { - mem_alert0: trip-point@0 { + mem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -2399,7 +2436,7 @@ thermal-sensors = <&tsens1 4>; trips { - modemtx_alert0: trip-point@0 { + modemtx_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; diff --git a/src/arm64/qcom/msm8998.dtsi b/src/arm64/qcom/msm8998.dtsi index c07fee6fd7eb..c45870600909 100644 --- a/src/arm64/qcom/msm8998.dtsi +++ b/src/arm64/qcom/msm8998.dtsi @@ -500,7 +500,7 @@ thermal-sensors = <&tsens0 1>; trips { - cpu0_alert0: trip-point@0 { + cpu0_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -521,7 +521,7 @@ thermal-sensors = <&tsens0 2>; trips { - cpu1_alert0: trip-point@0 { + cpu1_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -542,7 +542,7 @@ thermal-sensors = <&tsens0 3>; trips { - cpu2_alert0: trip-point@0 { + cpu2_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -563,7 +563,7 @@ thermal-sensors = <&tsens0 4>; trips { - cpu3_alert0: trip-point@0 { + cpu3_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -584,7 +584,7 @@ thermal-sensors = <&tsens0 7>; trips { - cpu4_alert0: trip-point@0 { + cpu4_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -605,7 +605,7 @@ thermal-sensors = <&tsens0 8>; trips { - cpu5_alert0: trip-point@0 { + cpu5_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -626,7 +626,7 @@ thermal-sensors = <&tsens0 9>; trips { - cpu6_alert0: trip-point@0 { + cpu6_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -647,7 +647,7 @@ thermal-sensors = <&tsens0 10>; trips { - cpu7_alert0: trip-point@0 { + cpu7_alert0: trip-point0 { temperature = <75000>; hysteresis = <2000>; type = "passive"; @@ -668,7 +668,7 @@ thermal-sensors = <&tsens0 12>; trips { - gpu1_alert0: trip-point@0 { + gpu1_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -683,7 +683,7 @@ thermal-sensors = <&tsens0 13>; trips { - gpu2_alert0: trip-point@0 { + gpu2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -698,7 +698,7 @@ thermal-sensors = <&tsens0 5>; trips { - cluster0_mhm_alert0: trip-point@0 { + cluster0_mhm_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -713,7 +713,7 @@ thermal-sensors = <&tsens0 6>; trips { - cluster1_mhm_alert0: trip-point@0 { + cluster1_mhm_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -728,7 +728,7 @@ thermal-sensors = <&tsens0 11>; trips { - cluster1_l2_alert0: trip-point@0 { + cluster1_l2_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -743,7 +743,7 @@ thermal-sensors = <&tsens1 1>; trips { - modem_alert0: trip-point@0 { + modem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -758,7 +758,7 @@ thermal-sensors = <&tsens1 2>; trips { - mem_alert0: trip-point@0 { + mem_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -773,7 +773,7 @@ thermal-sensors = <&tsens1 3>; trips { - wlan_alert0: trip-point@0 { + wlan_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -788,7 +788,7 @@ thermal-sensors = <&tsens1 4>; trips { - q6_dsp_alert0: trip-point@0 { + q6_dsp_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -803,7 +803,7 @@ thermal-sensors = <&tsens1 5>; trips { - camera_alert0: trip-point@0 { + camera_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; @@ -818,7 +818,7 @@ thermal-sensors = <&tsens1 6>; trips { - multimedia_alert0: trip-point@0 { + multimedia_alert0: trip-point0 { temperature = <90000>; hysteresis = <2000>; type = "hot"; diff --git a/src/arm64/qcom/pm8150.dtsi b/src/arm64/qcom/pm8150.dtsi index b6e304748a57..c0b197458665 100644 --- a/src/arm64/qcom/pm8150.dtsi +++ b/src/arm64/qcom/pm8150.dtsi @@ -73,18 +73,8 @@ reg = <0xc000>; gpio-controller; #gpio-cells = <2>; - interrupts = <0x0 0xc0 0x0 IRQ_TYPE_NONE>, - <0x0 0xc1 0x0 IRQ_TYPE_NONE>, - <0x0 0xc2 0x0 IRQ_TYPE_NONE>, - <0x0 0xc3 0x0 IRQ_TYPE_NONE>, - <0x0 0xc4 0x0 IRQ_TYPE_NONE>, - <0x0 0xc5 0x0 IRQ_TYPE_NONE>, - <0x0 0xc6 0x0 IRQ_TYPE_NONE>, - <0x0 0xc7 0x0 IRQ_TYPE_NONE>, - <0x0 0xc8 0x0 IRQ_TYPE_NONE>, - <0x0 0xc9 0x0 IRQ_TYPE_NONE>, - <0x0 0xca 0x0 IRQ_TYPE_NONE>, - <0x0 0xcb 0x0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; }; diff --git a/src/arm64/qcom/pm8150b.dtsi b/src/arm64/qcom/pm8150b.dtsi index 322379d5c31f..40b5d75a4a1d 100644 --- a/src/arm64/qcom/pm8150b.dtsi +++ b/src/arm64/qcom/pm8150b.dtsi @@ -62,18 +62,8 @@ reg = <0xc000>; gpio-controller; #gpio-cells = <2>; - interrupts = <0x2 0xc0 0x0 IRQ_TYPE_NONE>, - <0x2 0xc1 0x0 IRQ_TYPE_NONE>, - <0x2 0xc2 0x0 IRQ_TYPE_NONE>, - <0x2 0xc3 0x0 IRQ_TYPE_NONE>, - <0x2 0xc4 0x0 IRQ_TYPE_NONE>, - <0x2 0xc5 0x0 IRQ_TYPE_NONE>, - <0x2 0xc6 0x0 IRQ_TYPE_NONE>, - <0x2 0xc7 0x0 IRQ_TYPE_NONE>, - <0x2 0xc8 0x0 IRQ_TYPE_NONE>, - <0x2 0xc9 0x0 IRQ_TYPE_NONE>, - <0x2 0xca 0x0 IRQ_TYPE_NONE>, - <0x2 0xcb 0x0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; }; diff --git a/src/arm64/qcom/pm8150l.dtsi b/src/arm64/qcom/pm8150l.dtsi index eb0e9a090e42..cf05e0685d10 100644 --- a/src/arm64/qcom/pm8150l.dtsi +++ b/src/arm64/qcom/pm8150l.dtsi @@ -56,18 +56,8 @@ reg = <0xc000>; gpio-controller; #gpio-cells = <2>; - interrupts = <0x4 0xc0 0x0 IRQ_TYPE_NONE>, - <0x4 0xc1 0x0 IRQ_TYPE_NONE>, - <0x4 0xc2 0x0 IRQ_TYPE_NONE>, - <0x4 0xc3 0x0 IRQ_TYPE_NONE>, - <0x4 0xc4 0x0 IRQ_TYPE_NONE>, - <0x4 0xc5 0x0 IRQ_TYPE_NONE>, - <0x4 0xc6 0x0 IRQ_TYPE_NONE>, - <0x4 0xc7 0x0 IRQ_TYPE_NONE>, - <0x4 0xc8 0x0 IRQ_TYPE_NONE>, - <0x4 0xc9 0x0 IRQ_TYPE_NONE>, - <0x4 0xca 0x0 IRQ_TYPE_NONE>, - <0x4 0xcb 0x0 IRQ_TYPE_NONE>; + interrupt-controller; + #interrupt-cells = <2>; }; }; diff --git a/src/arm64/qcom/pmi8994.dtsi b/src/arm64/qcom/pmi8994.dtsi index 21e05215abe4..e5ed28ab9b2d 100644 --- a/src/arm64/qcom/pmi8994.dtsi +++ b/src/arm64/qcom/pmi8994.dtsi @@ -26,5 +26,11 @@ reg = <0x3 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmi8994_spmi_regulators: regulators { + compatible = "qcom,pmi8994-regulators"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; diff --git a/src/arm64/qcom/qcs404-evb.dtsi b/src/arm64/qcom/qcs404-evb.dtsi index afe69e8f3114..6422cf9d5855 100644 --- a/src/arm64/qcom/qcs404-evb.dtsi +++ b/src/arm64/qcom/qcs404-evb.dtsi @@ -4,6 +4,8 @@ #include #include "qcs404.dtsi" #include "pms405.dtsi" +#include +#include / { aliases { @@ -31,6 +33,21 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + usb3_vbus_reg: regulator-usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_BOOST_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_vbus_boost_pin>; + vin-supply = <&vph_pwr>; + enable-active-high; + + /* TODO: Drop this when introducing role switching */ + regulator-always-on; + }; }; &blsp1_uart3 { @@ -186,7 +203,7 @@ }; vreg_l12_3p3: l12 { - regulator-min-microvolt = <2968000>; + regulator-min-microvolt = <3050000>; regulator-max-microvolt = <3300000>; }; @@ -270,6 +287,72 @@ bias-pull-down; }; }; + + usb3_id_pin: usb3-id-pin { + pinmux { + pins = "gpio116"; + function = "gpio"; + }; + + pinconf { + pins = "gpio116"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; +}; + +&pms405_gpios { + usb_vbus_boost_pin: usb-vbus-boost-pin { + pinconf { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = <1>; + }; + }; + usb3_vbus_pin: usb3-vbus-pin { + pinconf { + pins = "gpio12"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + power-source = <1>; + }; + }; +}; + +&usb2 { + status = "okay"; +}; + +&usb2_phy_sec { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + status = "okay"; +}; + +&usb3 { + status = "okay"; + + dwc3@7580000 { + dr_mode = "host"; + }; +}; + +&usb2_phy_prim { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + status = "okay"; +}; + +&usb3_phy { + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + status = "okay"; }; &wifi { diff --git a/src/arm64/qcom/qcs404.dtsi b/src/arm64/qcom/qcs404.dtsi index f149a538c1cc..c685a1664810 100644 --- a/src/arm64/qcom/qcs404.dtsi +++ b/src/arm64/qcom/qcs404.dtsi @@ -323,6 +323,48 @@ reg = <0x00060000 0x6000>; }; + usb3_phy: phy@78000 { + compatible = "qcom,usb-ss-28nm-phy"; + reg = <0x00078000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "ahb", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + status = "disabled"; + }; + + usb2_phy_prim: phy@7a000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0007a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "ahb", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + usb2_phy_sec: phy@7c000 { + compatible = "qcom,usb-hs-28nm-femtophy"; + reg = <0x0007c000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "ahb", "sleep"; + resets = <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + qfprom: qfprom@a4000 { compatible = "qcom,qfprom"; reg = <0x000a4000 0x1000>; @@ -486,6 +528,64 @@ }; }; + usb3: usb@7678800 { + compatible = "qcom,dwc3"; + reg = <0x07678800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + status = "disabled"; + + dwc3@7580000 { + compatible = "snps,dwc3"; + reg = <0x07580000 0xcd00>; + interrupts = ; + phys = <&usb2_phy_sec>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "otg"; + }; + }; + + usb2: usb@79b8800 { + compatible = "qcom,dwc3"; + reg = <0x079b8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, + <&gcc GCC_PCNOC_USB2_CLK>, + <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + status = "disabled"; + + dwc3@78c0000 { + compatible = "snps,dwc3"; + reg = <0x078c0000 0xcc00>; + interrupts = ; + phys = <&usb2_phy_prim>; + phy-names = "usb2-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "peripheral"; + }; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>, diff --git a/src/arm64/qcom/sc7180-idp.dts b/src/arm64/qcom/sc7180-idp.dts index 043c9b9b5024..4e9149d82d09 100644 --- a/src/arm64/qcom/sc7180-idp.dts +++ b/src/arm64/qcom/sc7180-idp.dts @@ -28,6 +28,59 @@ }; }; +/* + * Reserved memory changes + * + * Delete all unused memory nodes and define the peripheral memory regions + * required by the board dts. + * + */ + +/delete-node/ &hyp_mem; +/delete-node/ &xbl_mem; +/delete-node/ &aop_mem; +/delete-node/ &sec_apps_mem; +/delete-node/ &tz_mem; + +/* Increase the size from 2MB to 8MB */ +&rmtfs_mem { + reg = <0x0 0x84400000 0x0 0x800000>; +}; + +/ { + reserved-memory { + atf_mem: memory@80b00000 { + reg = <0x0 0x80b00000 0x0 0x100000>; + no-map; + }; + + mpss_mem: memory@86000000 { + reg = <0x0 0x86000000 0x0 0x8c00000>; + no-map; + }; + + camera_mem: memory@8ec00000 { + reg = <0x0 0x8ec00000 0x0 0x500000>; + no-map; + }; + + venus_mem: memory@8f600000 { + reg = <0 0x8f600000 0 0x500000>; + no-map; + }; + + wlan_mem: memory@94100000 { + reg = <0x0 0x94100000 0x0 0x200000>; + no-map; + }; + + mba_mem: memory@94400000 { + reg = <0x0 0x94400000 0x0 0x200000>; + no-map; + }; + }; +}; + &apps_rsc { pm6150-rpmh-regulators { compatible = "qcom,pm6150-rpmh-regulators"; @@ -256,6 +309,13 @@ status = "okay"; }; +&remoteproc_mpss { + status = "okay"; + compatible = "qcom,sc7180-mss-pil"; + iommus = <&apps_smmu 0x460 0x1>, <&apps_smmu 0x444 0x3>; + memory-region = <&mba_mem &mpss_mem>; +}; + &sdhc_1 { status = "okay"; @@ -310,9 +370,11 @@ vdda-pll-supply = <&vreg_l11a_1p8>; vdda-phy-dpdm-supply = <&vreg_l17a_3p0>; qcom,imp-res-offset-value = <8>; - qcom,hstx-trim-value = ; - qcom,preemphasis-level = ; + qcom,preemphasis-level = ; qcom,preemphasis-width = ; + qcom,bias-ctrl-value = <0x22>; + qcom,charge-ctrl-value = <3>; + qcom,hsdisc-trim-value = <0>; }; &usb_1_qmpphy { diff --git a/src/arm64/qcom/sc7180.dtsi b/src/arm64/qcom/sc7180.dtsi index 998f101ad623..31b9217bb5bf 100644 --- a/src/arm64/qcom/sc7180.dtsi +++ b/src/arm64/qcom/sc7180.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -69,9 +70,30 @@ #size-cells = <2>; ranges; + hyp_mem: memory@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_mem: memory@80600000 { + reg = <0x0 0x80600000 0x0 0x200000>; + no-map; + }; + + aop_mem: memory@80800000 { + reg = <0x0 0x80800000 0x0 0x20000>; + no-map; + }; + aop_cmd_db_mem: memory@80820000 { reg = <0x0 0x80820000 0x0 0x20000>; compatible = "qcom,cmd-db"; + no-map; + }; + + sec_apps_mem: memory@808ff000 { + reg = <0x0 0x808ff000 0x0 0x1000>; + no-map; }; smem_mem: memory@80900000 { @@ -79,10 +101,19 @@ no-map; }; - venus_mem: memory@8f600000 { - reg = <0 0x8f600000 0 0x500000>; + tz_mem: memory@80b00000 { + reg = <0x0 0x80b00000 0x0 0x3900000>; no-map; }; + + rmtfs_mem: memory@84400000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x84400000 0x0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; }; cpus { @@ -91,9 +122,12 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; @@ -110,9 +144,12 @@ CPU1: cpu@100 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_100>; @@ -126,9 +163,12 @@ CPU2: cpu@200 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x200>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_200>; @@ -142,9 +182,12 @@ CPU3: cpu@300 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x300>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_300>; @@ -158,9 +201,12 @@ CPU4: cpu@400 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x400>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_400>; @@ -174,9 +220,12 @@ CPU5: cpu@500 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x500>; enable-method = "psci"; + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_500>; @@ -190,9 +239,12 @@ CPU6: cpu@600 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x600>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <405>; next-level-cache = <&L2_600>; @@ -206,9 +258,12 @@ CPU7: cpu@700 { device_type = "cpu"; - compatible = "arm,armv8"; + compatible = "qcom,kryo468"; reg = <0x0 0x700>; enable-method = "psci"; + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; capacity-dmips-mhz = <1740>; dynamic-power-coefficient = <405>; next-level-cache = <&L2_700>; @@ -255,6 +310,60 @@ }; }; }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "little-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + local-timer-stop; + }; + + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "little-rail-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "big-power-down"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "big-rail-power-down"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + local-timer-stop; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "cluster-power-down"; + arm,psci-suspend-param = <0x40003444>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9926>; + local-timer-stop; + }; + }; }; memory@80000000 { @@ -352,6 +461,17 @@ interrupt-controller; #interrupt-cells = <2>; }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; }; psci { @@ -898,11 +1018,56 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + ipa: ipa@1e40000 { + compatible = "qcom,sc7180-ipa"; + + iommus = <&apps_smmu 0x440 0x3>; + reg = <0 0x1e40000 0 0x7000>, + <0 0x1e47000 0 0x2000>, + <0 0x1e04000 0 0x2c000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>, + <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_IPA &system_noc SLAVE_IMEM>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; + interconnect-names = "memory", + "imem", + "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + modem-remoteproc = <&remoteproc_mpss>; + + status = "disabled"; + }; + tcsr_mutex_regs: syscon@1f40000 { compatible = "syscon"; reg = <0 0x01f40000 0 0x40000>; }; + tcsr_regs: syscon@1fc0000 { + compatible = "syscon"; + reg = <0 0x01fc0000 0 0x40000>; + }; + tlmm: pinctrl@3500000 { compatible = "qcom,sc7180-pinctrl"; reg = <0 0x03500000 0 0x300000>, @@ -1294,6 +1459,652 @@ }; }; + gpu: gpu@5000000 { + compatible = "qcom,adreno-618.0", "qcom,adreno"; + #stream-id-cells = <16>; + reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, + <0 0x05061000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; + interrupts = ; + iommus = <&adreno_smmu 0>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = ; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = ; + }; + + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = ; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = ; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = ; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = ; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = ; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x05040000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bus", "iface"; + + power-domains = <&gpucc CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; + reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; + power-domain-names = "cx", "gx"; + iommus = <&adreno_smmu 5>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + + gpucc: clock-controller@5090000 { + compatible = "qcom,sc7180-gpucc"; + reg = <0 0x05090000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + stm@6002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0 0x06002000 0 0x1000>, + <0 0x16280000 0 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel0_in7>; + }; + }; + }; + }; + + funnel@6041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06041000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + funnel0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@6042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06042000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = <&merge_funnel_in1>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + funnel1_in4: endpoint { + remote-endpoint = <&apss_merge_funnel_out>; + }; + }; + }; + }; + + funnel@6045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06045000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = <&swao_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = <&funnel1_out>; + }; + }; + }; + }; + + replicator@6046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06046000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&swao_replicator_out>; + }; + }; + }; + }; + + etr@6048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06048000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out>; + }; + }; + }; + }; + + funnel@6b04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06b04000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + swao_funnel_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@7 { + reg = <7>; + swao_funnel_in: endpoint { + remote-endpoint = <&merge_funnel_out>; + }; + }; + }; + }; + + etf@6b05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x06b05000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&swao_replicator_in>; + }; + }; + }; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = <&swao_funnel_out>; + }; + }; + }; + }; + + replicator@6b06000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0 0x06b06000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + swao_replicator_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + + in-ports { + port { + swao_replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etm@7040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07040000 0 0x1000>; + + cpu = <&CPU0>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&apss_funnel_in0>; + }; + }; + }; + }; + + etm@7140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07140000 0 0x1000>; + + cpu = <&CPU1>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&apss_funnel_in1>; + }; + }; + }; + }; + + etm@7240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07240000 0 0x1000>; + + cpu = <&CPU2>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&apss_funnel_in2>; + }; + }; + }; + }; + + etm@7340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07340000 0 0x1000>; + + cpu = <&CPU3>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&apss_funnel_in3>; + }; + }; + }; + }; + + etm@7440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07440000 0 0x1000>; + + cpu = <&CPU4>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = <&apss_funnel_in4>; + }; + }; + }; + }; + + etm@7540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07540000 0 0x1000>; + + cpu = <&CPU5>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = <&apss_funnel_in5>; + }; + }; + }; + }; + + etm@7640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07640000 0 0x1000>; + + cpu = <&CPU6>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = <&apss_funnel_in6>; + }; + }; + }; + }; + + etm@7740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x07740000 0 0x1000>; + + cpu = <&CPU7>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = <&apss_funnel_in7>; + }; + }; + }; + }; + + funnel@7800000 { /* APSS Funnel */ + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07800000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_funnel_out: endpoint { + remote-endpoint = <&apss_merge_funnel_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + apss_funnel_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + apss_funnel_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + apss_funnel_in4: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + apss_funnel_in5: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + apss_funnel_in6: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + apss_funnel_in7: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + funnel@7810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x07810000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = <&funnel1_in4>; + }; + }; + }; + + in-ports { + port { + apss_merge_funnel_in: endpoint { + remote-endpoint = <&apss_funnel_out>; + }; + }; + }; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sc7180-mpss-pas"; + reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, + <&gcc GCC_MSS_NAV_AXI_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MFAB_AXIS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "bus", "nav", "snoc_axi", + "mnoc_axi", "xo"; + + power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, + <&rpmhpd SC7180_CX>, + <&rpmhpd SC7180_MX>, + <&rpmhpd SC7180_MSS>; + power-domain-names = "load_state", "cx", "mx", "mss"; + + memory-region = <&mpss_mem>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + qcom,spare-regs = <&tcsr_regs 0xb3e4>; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apss_shared 12>; + }; + }; + sdhc_2: sdhci@8804000 { compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x08804000 0 0x1000>; @@ -1312,20 +2123,6 @@ status = "disabled"; }; - gpucc: clock-controller@5090000 { - compatible = "qcom,sc7180-gpucc"; - reg = <0 0x05090000 0 0x9000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; - clock-names = "bi_tcxo", - "gcc_gpu_gpll0_clk_src", - "gcc_gpu_gpll0_div_clk_src"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - qspi: spi@88dc000 { compatible = "qcom,qspi-v1"; reg = <0 0x088dc000 0 0x600>; @@ -1339,7 +2136,7 @@ }; usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sc7180-qusb2-phy"; + compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; reg = <0 0x088e3000 0 0x400>; status = "disabled"; #phy-cells = <0>; @@ -1447,6 +2244,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre2_noc MASTER_USB3 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: dwc3@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xe000>; @@ -1475,6 +2276,9 @@ "vcodec0_core", "vcodec0_bus"; iommus = <&apps_smmu 0x0c00 0x60>; memory-region = <&venus_mem>; + interconnects = <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; + interconnect-names = "video-mem", "cpu-cfg"; video-decoder { compatible = "venus-decoder"; @@ -1544,8 +2348,12 @@ clock-names = "iface", "rot", "lut", "core", "vsync"; assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; assigned-clock-rates = <300000000>, + <19200000>, + <19200000>, <19200000>; interrupt-parent = <&mdss>; @@ -1657,8 +2465,7 @@ pdc: interrupt-controller@b220000 { compatible = "qcom,sc7180-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; - qcom,pdc-ranges = <0 480 15>, <17 497 98>, - <119 634 4>, <124 639 1>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; @@ -2011,8 +2818,8 @@ thermal-zones { cpu0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 1>; @@ -2059,8 +2866,8 @@ }; cpu1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 2>; @@ -2107,8 +2914,8 @@ }; cpu2-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 3>; @@ -2155,8 +2962,8 @@ }; cpu3-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 4>; @@ -2203,8 +3010,8 @@ }; cpu4-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 5>; @@ -2251,8 +3058,8 @@ }; cpu5-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 6>; @@ -2299,8 +3106,8 @@ }; cpu6-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 9>; @@ -2339,8 +3146,8 @@ }; cpu7-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 10>; @@ -2379,8 +3186,8 @@ }; cpu8-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 11>; @@ -2419,8 +3226,8 @@ }; cpu9-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 12>; @@ -2459,8 +3266,8 @@ }; aoss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 0>; @@ -2480,8 +3287,8 @@ }; cpuss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 7>; @@ -2500,8 +3307,8 @@ }; cpuss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 8>; @@ -2520,8 +3327,8 @@ }; gpuss0-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 13>; @@ -2541,8 +3348,8 @@ }; gpuss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens0 14>; @@ -2562,8 +3369,8 @@ }; aoss1-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 0>; @@ -2583,8 +3390,8 @@ }; cwlan-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 1>; @@ -2604,8 +3411,8 @@ }; audio-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 2>; @@ -2625,8 +3432,8 @@ }; ddr-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 3>; @@ -2646,8 +3453,8 @@ }; q6-hvx-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 4>; @@ -2667,8 +3474,8 @@ }; camera-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 5>; @@ -2688,8 +3495,8 @@ }; mdm-core-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 6>; @@ -2709,8 +3516,8 @@ }; mdm-dsp-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 7>; @@ -2730,8 +3537,8 @@ }; npu-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 8>; @@ -2751,8 +3558,8 @@ }; video-thermal { - polling-delay-passive = <250>; - polling-delay = <1000>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-sensors = <&tsens1 9>; diff --git a/src/arm64/qcom/sdm660-xiaomi-lavender.dts b/src/arm64/qcom/sdm660-xiaomi-lavender.dts new file mode 100644 index 000000000000..76533e8b2092 --- /dev/null +++ b/src/arm64/qcom/sdm660-xiaomi-lavender.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, Alexey Minnekhanov + */ + +/dts-v1/; + +#include "sdm660.dtsi" + +/ { + model = "Xiaomi Redmi Note 7"; + compatible = "xiaomi,lavender", "qcom,sdm660"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@a0000000 { + compatible = "ramoops"; + reg = <0x0 0xa0000000 0x0 0x400000>; + console-size = <0x20000>; + record-size = <0x20000>; + ftrace-size = <0x0>; + pmsg-size = <0x20000>; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart_console_active>; +}; + +&tlmm { + gpio-reserved-ranges = <8 4>; +}; diff --git a/src/arm64/qcom/sdm660.dtsi b/src/arm64/qcom/sdm660.dtsi new file mode 100644 index 000000000000..4abbdd03d1e7 --- /dev/null +++ b/src/arm64/qcom/sdm660.dtsi @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018, Craig Tatlor. + * Copyright (c) 2020, Alexey Minnekhanov + */ + +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + clock-output-names = "sleep_clk"; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + L1_I_100: l1-icache { + compatible = "cache"; + }; + L1_D_100: l1-dcache { + compatible = "cache"; + }; + }; + + CPU1: cpu@101 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + L1_I_101: l1-icache { + compatible = "cache"; + }; + L1_D_101: l1-dcache { + compatible = "cache"; + }; + }; + + CPU2: cpu@102 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + L1_I_102: l1-icache { + compatible = "cache"; + }; + L1_D_102: l1-dcache { + compatible = "cache"; + }; + }; + + CPU3: cpu@103 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + L1_I_103: l1-icache { + compatible = "cache"; + }; + L1_D_103: l1-dcache { + compatible = "cache"; + }; + }; + + CPU4: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <640>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + L1_I_0: l1-icache { + compatible = "cache"; + }; + L1_D_0: l1-dcache { + compatible = "cache"; + }; + }; + + CPU5: cpu@1 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <640>; + next-level-cache = <&L2_0>; + L1_I_1: l1-icache { + compatible = "cache"; + }; + L1_D_1: l1-dcache { + compatible = "cache"; + }; + }; + + CPU6: cpu@2 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <640>; + next-level-cache = <&L2_0>; + L1_I_2: l1-icache { + compatible = "cache"; + }; + L1_D_2: l1-dcache { + compatible = "cache"; + }; + }; + + CPU7: cpu@3 { + device_type = "cpu"; + compatible = "qcom,kryo260"; + reg = <0x0 0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <640>; + next-level-cache = <&L2_0>; + L1_I_3: l1-icache { + compatible = "cache"; + }; + L1_D_3: l1-dcache { + compatible = "cache"; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm"; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sdm660"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x00100000 0x94000>; + }; + + tlmm: pinctrl@3100000 { + compatible = "qcom,sdm660-pinctrl"; + reg = <0x03100000 0x400000>, + <0x03500000 0x400000>, + <0x03900000 0x400000>; + reg-names = "south", "center", "north"; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 114>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart_console_active: uart_console_active { + pinmux { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + }; + + pinconf { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + spmi_bus: spmi@800f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0800f000 0x1000>, + <0x08400000 0x1000000>, + <0x09400000 0x1000000>, + <0x0a400000 0x220000>, + <0x0800a000 0x3000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + + blsp1_uart2: serial@c170000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x0c170000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + timer@17920000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17920000 0x1000>; + + frame@17921000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17921000 0x1000>, + <0x17922000 0x1000>; + }; + + frame@17923000 { + frame-number = <1>; + interrupts = ; + reg = <0x17923000 0x1000>; + status = "disabled"; + }; + + frame@17924000 { + frame-number = <2>; + interrupts = ; + reg = <0x17924000 0x1000>; + status = "disabled"; + }; + + frame@17925000 { + frame-number = <3>; + interrupts = ; + reg = <0x17925000 0x1000>; + status = "disabled"; + }; + + frame@17926000 { + frame-number = <4>; + interrupts = ; + reg = <0x17926000 0x1000>; + status = "disabled"; + }; + + frame@17927000 { + frame-number = <5>; + interrupts = ; + reg = <0x17927000 0x1000>; + status = "disabled"; + }; + + frame@17928000 { + frame-number = <6>; + interrupts = ; + reg = <0x17928000 0x1000>; + status = "disabled"; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x17a00000 0x10000>, + <0x17b00000 0x100000>; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + interrupts = ; + }; + }; +}; diff --git a/src/arm64/qcom/sdm845-cheza.dtsi b/src/arm64/qcom/sdm845-cheza.dtsi index 9070be43a309..70466cc4b405 100644 --- a/src/arm64/qcom/sdm845-cheza.dtsi +++ b/src/arm64/qcom/sdm845-cheza.dtsi @@ -548,6 +548,8 @@ edp_brij_i2c: &i2c3 { clocks = <&rpmhcc RPMH_LN_BB_CLK2>; clock-names = "refclk"; + no-hpd; + ports { #address-cells = <1>; #size-cells = <0>; @@ -631,6 +633,11 @@ ap_ts_i2c: &i2c14 { status = "okay"; }; +&mss_pil { + iommus = <&apps_smmu 0x780 0x1>, + <&apps_smmu 0x724 0x3>; +}; + &pm8998_pwrkey { status = "disabled"; }; diff --git a/src/arm64/qcom/sdm845-db845c.dts b/src/arm64/qcom/sdm845-db845c.dts index 21fd6f8d5799..c00797bd3b07 100644 --- a/src/arm64/qcom/sdm845-db845c.dts +++ b/src/arm64/qcom/sdm845-db845c.dts @@ -112,6 +112,40 @@ // enable-active-high; }; + cam0_dvdd_1v2: reg_cam0_dvdd_1v2 { + compatible = "regulator-fixed"; + regulator-name = "CAM0_DVDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + enable-active-high; + gpio = <&pm8998_gpio 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_dvdd_1v2_en_default>; + vin-supply = <&vbat>; + }; + + cam0_avdd_2v8: reg_cam0_avdd_2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAM0_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + enable-active-high; + gpio = <&pm8998_gpio 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_avdd_2v8_en_default>; + vin-supply = <&vbat>; + }; + + /* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */ + cam3_avdd_2v8: reg_cam3_avdd_2v8 { + compatible = "regulator-fixed"; + regulator-name = "CAM3_AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + vin-supply = <&vbat>; + }; + pcie0_3p3v_dual: vldo-3v3-regulator { compatible = "regulator-fixed"; regulator-name = "VLDO_3V3"; @@ -412,6 +446,52 @@ }; &pm8998_gpio { + gpio-line-names = + "NC", + "NC", + "WLAN_SW_CTRL", + "NC", + "PM_GPIO5_BLUE_BT_LED", + "VOL_UP_N", + "NC", + "ADC_IN1", + "PM_GPIO9_YEL_WIFI_LED", + "CAM0_AVDD_EN", + "NC", + "CAM0_DVDD_EN", + "PM_GPIO13_GREEN_U4_LED", + "DIV_CLK2", + "NC", + "NC", + "NC", + "SMB_STAT", + "NC", + "NC", + "ADC_IN2", + "OPTION1", + "WCSS_PWR_REQ", + "PM845_GPIO24", + "OPTION2", + "PM845_SLB"; + + cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en { + pins = "gpio12"; + function = "normal"; + + bias-pull-up; + drive-push-pull; + qcom,drive-strength = ; + }; + + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en { + pins = "gpio10"; + function = "normal"; + + bias-pull-up; + drive-push-pull; + qcom,drive-strength = ; + }; + vol_up_pin_a: vol-up-active { pins = "gpio6"; function = "normal"; @@ -570,6 +650,42 @@ }; &tlmm { + cam0_default: cam0_default { + rst { + pins = "gpio9"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + + mclk0 { + pins = "gpio13"; + function = "cam_mclk"; + + drive-strength = <16>; + bias-disable; + }; + }; + + cam3_default: cam3_default { + rst { + function = "gpio"; + pins = "gpio21"; + + drive-strength = <16>; + bias-disable; + }; + + mclk3 { + function = "cam_mclk"; + pins = "gpio16"; + + drive-strength = <16>; + bias-disable; + }; + }; + pcie0_default_state: pcie0-default { clkreq { pins = "gpio36"; @@ -863,3 +979,97 @@ bias-pull-up; }; }; + +&pm8998_gpio { + +}; + +&cci { + status = "ok"; +}; + +&cci_i2c0 { + camera@10 { + compatible = "ovti,ov8856"; + reg = <0x10>; + + // CAM0_RST_N + reset-gpios = <&tlmm 9 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_default>; + gpios = <&tlmm 13 0>, + <&tlmm 9 0>; + + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "xvclk"; + clock-frequency = <19200000>; + + /* The &vreg_s4a_1p8 trace is powered on as a, + * so it is represented by a fixed regulator. + * + * The 2.8V vdda-supply and 1.2V vddd-supply regulators + * both have to be enabled through the power management + * gpios. + */ + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + dovdd-supply = <&vreg_lvs1a_1p8>; + avdd-supply = <&cam0_avdd_2v8>; + dvdd-supply = <&cam0_dvdd_1v2>; + + status = "disable"; + + port { + ov8856_ep: endpoint { + clock-lanes = <1>; + link-frequencies = /bits/ 64 + <360000000 180000000>; + data-lanes = <1 2 3 4>; +// remote-endpoint = <&csiphy0_ep>; + }; + }; + }; +}; + +&cci_i2c1 { + camera@60 { + compatible = "ovti,ov7251"; + + // I2C address as per ov7251.txt linux documentation + reg = <0x60>; + + // CAM3_RST_N + enable-gpios = <&tlmm 21 0>; + pinctrl-names = "default"; + pinctrl-0 = <&cam3_default>; + gpios = <&tlmm 16 0>, + <&tlmm 21 0>; + + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "xclk"; + clock-frequency = <24000000>; + + /* The &vreg_s4a_1p8 trace always powered on. + * + * The 2.8V vdda-supply regulator is enabled when the + * vreg_s4a_1p8 trace is pulled high. + * It too is represented by a fixed regulator. + * + * No 1.2V vddd-supply regulator is used. + */ + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + vdddo-supply = <&vreg_lvs1a_1p8>; + vdda-supply = <&cam3_avdd_2v8>; + + status = "disable"; + + port { + ov7251_ep: endpoint { + clock-lanes = <1>; + data-lanes = <0 1>; +// remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; diff --git a/src/arm64/qcom/sdm845-mtp.dts b/src/arm64/qcom/sdm845-mtp.dts index 023e8b04c7f6..1372fe8601f5 100644 --- a/src/arm64/qcom/sdm845-mtp.dts +++ b/src/arm64/qcom/sdm845-mtp.dts @@ -13,7 +13,7 @@ / { model = "Qualcomm Technologies, Inc. SDM845 MTP"; - compatible = "qcom,sdm845-mtp"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845"; aliases { serial0 = &uart9; diff --git a/src/arm64/qcom/sdm845.dtsi b/src/arm64/qcom/sdm845.dtsi index 8f926b5234d4..8eb5a31346d2 100644 --- a/src/arm64/qcom/sdm845.dtsi +++ b/src/arm64/qcom/sdm845.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -1761,6 +1762,8 @@ ipa: ipa@1e40000 { compatible = "qcom,sdm845-ipa"; + + iommus = <&apps_smmu 0x720 0x3>; reg = <0 0x1e40000 0 0x7000>, <0 0x1e47000 0 0x2000>, <0 0x1e04000 0 0x2c000>; @@ -1813,6 +1816,42 @@ gpio-ranges = <&tlmm 0 0 150>; wakeup-parent = <&pdc_intc>; + cci0_default: cci0-default { + /* SDA, SCL */ + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci0_sleep: cci0-sleep { + /* SDA, SCL */ + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + + cci1_default: cci1-default { + /* SDA, SCL */ + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci1_sleep: cci1-sleep { + /* SDA, SCL */ + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + qspi_clk: qspi-clk { pinmux { pins = "gpio95"; @@ -2970,7 +3009,7 @@ }; usb_1_hsphy: phy@88e2000 { - compatible = "qcom,sdm845-qusb2-phy"; + compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; reg = <0 0x088e2000 0 0x400>; status = "disabled"; #phy-cells = <0>; @@ -2985,7 +3024,7 @@ }; usb_2_hsphy: phy@88e3000 { - compatible = "qcom,sdm845-qusb2-phy"; + compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; reg = <0 0x088e3000 0 0x400>; status = "disabled"; #phy-cells = <0>; @@ -3097,6 +3136,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre2_noc MASTER_USB3_0 &mem_noc SLAVE_EBI1>, + <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_1_dwc3: dwc3@a600000 { compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; @@ -3141,6 +3184,10 @@ resets = <&gcc GCC_USB30_SEC_BCR>; + interconnects = <&aggre2_noc MASTER_USB3_1 &mem_noc SLAVE_EBI1>, + <&gladiator_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>; + interconnect-names = "usb-ddr", "apps-usb"; + usb_2_dwc3: dwc3@a800000 { compatible = "snps,dwc3"; reg = <0 0x0a800000 0 0xcd00>; @@ -3194,6 +3241,61 @@ #reset-cells = <1>; }; + cci: cci@ac4a000 { + compatible = "qcom,sdm845-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4a000 0 0x4000>; + interrupts = ; + power-domains = <&clock_camcc TITAN_TOP_GDSC>; + + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK_SRC>; + clock-names = "camnoc_axi", + "soc_ahb", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CCI_CLK>; + assigned-clock-rates = <80000000>, <37500000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-1 = <&cci0_sleep &cci1_sleep>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + clock_camcc: clock-controller@ad00000 { + compatible = "qcom,sdm845-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: mdss@ae00000 { compatible = "qcom,sdm845-mdss"; reg = <0 0x0ae00000 0 0x1000>; diff --git a/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts b/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts index 51a670ad15b2..d03ca3190746 100644 --- a/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts +++ b/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts @@ -480,6 +480,8 @@ &ufs_mem_hc { status = "okay"; + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l20a_2p95>; vcc-max-microamp = <600000>; }; @@ -577,3 +579,14 @@ }; }; }; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; +}; diff --git a/src/arm64/qcom/sm8250-mtp.dts b/src/arm64/qcom/sm8250-mtp.dts index 224d0f1ea6f9..cff7a85890ee 100644 --- a/src/arm64/qcom/sm8250-mtp.dts +++ b/src/arm64/qcom/sm8250-mtp.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "sm8250.dtsi" / { @@ -18,6 +19,336 @@ chosen { stdout-path = "serial0:115200n8"; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8150-s4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; + + vreg_s6c_0p88: smpc6-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s6c_0p88"; + + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; +}; + +&apps_rsc { + pm8150-rpmh-regulators { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>; + vdd-l2-l10-supply = <&vreg_bob>; + vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p95>; + vdd-l6-l9-supply = <&vreg_s8c_1p3>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>; + vdd-l13-l16-l17-supply = <&vreg_bob>; + + vreg_s5a_1p9: smps5 { + regulator-name = "vreg_s5a_1p9"; + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_s6a_0p95: smps6 { + regulator-name = "vreg_s6a_0p95"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + regulator-initial-mode = ; + }; + + vreg_l2a_3p1: ldo2 { + regulator-name = "vreg_l2a_3p1"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3a_0p9: ldo3 { + regulator-name = "vreg_l3a_0p9"; + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <932000>; + regulator-initial-mode = ; + }; + + vreg_l5a_0p875: ldo5 { + regulator-name = "vreg_l5a_0p875"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l6a_1p2: ldo6 { + regulator-name = "vreg_l6a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p7: ldo7 { + regulator-name = "vreg_l7a_1p7"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p2: ldo9 { + regulator-name = "vreg_l9a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p8: ldo10 { + regulator-name = "vreg_l10a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11a_0p75: ldo11 { + regulator-name = "vreg_l11a_0p75"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_ts_3p0: ldo13 { + regulator-name = "vreg_l13a_ts_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = ; + }; + + vreg_l15a_11ad_io_1p8: ldo15 { + regulator-name = "vreg_l15a_11ad_io_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-name = "vreg_l16a_2p7"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l17a_3p0: ldo17 { + regulator-name = "vreg_l17a_3p0"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + }; + + pm8150l-rpmh-regulators { + compatible = "qcom,pm8150l-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l8-supply = <&vreg_s4a_1p8>; + vdd-l2-l3-supply = <&vreg_s8c_1p3>; + vdd-l4-l5-l6-supply = <&vreg_bob>; + vdd-l7-l11-supply = <&vreg_bob>; + vdd-l9-l10-supply = <&vreg_bob>; + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <4000000>; + regulator-initial-mode = ; + }; + + vreg_s8c_1p3: smps8 { + regulator-name = "vreg_s8c_1p3"; + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p2: ldo2 { + regulator-name = "vreg_l2c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p92: ldo3 { + regulator-name = "vreg_l3c_0p92"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p7: ldo4 { + regulator-name = "vreg_l4c_1p7"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p9: ldo6 { + regulator-name = "vreg_l6c_2p9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7c_cam_vcm0_2p85: ldo7 { + regulator-name = "vreg_l7c_cam_vcm0_2p85"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p9: ldo9 { + regulator-name = "vreg_l9c_2p9"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10c_3p0: ldo10 { + regulator-name = "vreg_l10c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l11c_3p3: ldo11 { + regulator-name = "vreg_l11c_3p3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + }; + + pm8009-rpmh-regulators { + compatible = "qcom,pm8009-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vreg_bob>; + vdd-l2-supply = <&vreg_s8c_1p3>; + vdd-l5-l6-supply = <&vreg_bob>; + vdd-l7-supply = <&vreg_s4a_1p8>; + + vreg_l1f_cam_dvdd1_1p1: ldo1 { + regulator-name = "vreg_l1f_cam_dvdd1_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + }; + + vreg_l2f_cam_dvdd0_1p2: ldo2 { + regulator-name = "vreg_l2f_cam_dvdd0_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3f_cam_dvdd2_1p05: ldo3 { + regulator-name = "vreg_l3f_cam_dvdd2_1p05"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + }; + + vreg_l5f_cam_avdd0_2p85: ldo5 { + regulator-name = "vreg_l5f_cam_avdd0_2p85"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6f_cam_avdd1_2p85: ldo6 { + regulator-name = "vreg_l6f_cam_avdd1_2p85"; + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <2856000>; + regulator-initial-mode = ; + }; + + vreg_l7f_1p8: ldo7 { + regulator-name = "vreg_l7f_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; }; &qupv3_id_1 { @@ -27,3 +358,23 @@ &uart2 { status = "okay"; }; + +&ufs_mem_hc { + status = "okay"; + + vcc-supply = <&vreg_l17a_3p0>; + vcc-max-microamp = <750000>; + vccq-supply = <&vreg_l6a_1p2>; + vccq-max-microamp = <700000>; + vccq2-supply = <&vreg_s4a_1p8>; + vccq2-max-microamp = <750000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5a_0p875>; + vdda-max-microamp = <90200>; + vdda-pll-supply = <&vreg_l9a_1p2>; + vdda-pll-max-microamp = <19000>; +}; diff --git a/src/arm64/qcom/sm8250.dtsi b/src/arm64/qcom/sm8250.dtsi index 891d83b2afea..7050adba7995 100644 --- a/src/arm64/qcom/sm8250.dtsi +++ b/src/arm64/qcom/sm8250.dtsi @@ -4,7 +4,9 @@ */ #include +#include #include +#include #include / { @@ -304,6 +306,76 @@ }; }; + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sm8250-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <37500000 300000000>, + <0 0>, + <0 0>, + <37500000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm8250-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "ref", + "ref_aux"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + status = "disabled"; + + ufs_mem_phy_lanes: lanes@1d87400 { + reg = <0 0x01d87400 0 0x108>, + <0 0x01d87600 0 0x1e0>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x108>, + <0 0x01d87a00 0 0x1e0>; + #phy-cells = <0>; + }; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -314,8 +386,8 @@ }; pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8250-pdc"; - reg = <0x0b220000 0x30000>, <0x17c000f0 0x60>; + compatible = "qcom,sm8250-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 716 12>; #interrupt-cells = <2>; @@ -362,6 +434,56 @@ clock-names = "xo"; clocks = <&xo_board>; }; + + rpmhpd: power-controller { + compatible = "qcom,sm8250-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; }; tcsr_mutex_regs: syscon@1f40000 { diff --git a/src/arm64/realtek/rtd1293-ds418j.dts b/src/arm64/realtek/rtd1293-ds418j.dts index b2dd583146b4..b2e44c6c2d22 100644 --- a/src/arm64/realtek/rtd1293-ds418j.dts +++ b/src/arm64/realtek/rtd1293-ds418j.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) /* - * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2017-2019 Andreas Färber */ /dts-v1/; @@ -11,9 +11,9 @@ compatible = "synology,ds418j", "realtek,rtd1293"; model = "Synology DiskStation DS418j"; - memory@0 { + memory@1f000 { device_type = "memory"; - reg = <0x0 0x40000000>; + reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB */ }; aliases { diff --git a/src/arm64/realtek/rtd1293.dtsi b/src/arm64/realtek/rtd1293.dtsi index bd4e22723f7b..2d92b56ac94d 100644 --- a/src/arm64/realtek/rtd1293.dtsi +++ b/src/arm64/realtek/rtd1293.dtsi @@ -36,16 +36,20 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; }; &arm_pmu { interrupt-affinity = <&cpu0>, <&cpu1>; }; + +&gic { + interrupts = ; +}; diff --git a/src/arm64/realtek/rtd1295-mele-v9.dts b/src/arm64/realtek/rtd1295-mele-v9.dts index bd584e99fff9..cf4a57c012a8 100644 --- a/src/arm64/realtek/rtd1295-mele-v9.dts +++ b/src/arm64/realtek/rtd1295-mele-v9.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2017-2019 Andreas Färber * * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ @@ -12,9 +12,9 @@ compatible = "mele,v9", "realtek,rtd1295"; model = "MeLE V9"; - memory@0 { + memory@1f000 { device_type = "memory"; - reg = <0x0 0x80000000>; + reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ }; aliases { diff --git a/src/arm64/realtek/rtd1295-probox2-ava.dts b/src/arm64/realtek/rtd1295-probox2-ava.dts index 8e2b0e75298a..14161c3f304d 100644 --- a/src/arm64/realtek/rtd1295-probox2-ava.dts +++ b/src/arm64/realtek/rtd1295-probox2-ava.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2017-2019 Andreas Färber * * SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ @@ -12,9 +12,9 @@ compatible = "probox2,ava", "realtek,rtd1295"; model = "PROBOX2 AVA"; - memory@0 { + memory@1f000 { device_type = "memory"; - reg = <0x0 0x80000000>; + reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ }; aliases { diff --git a/src/arm64/realtek/rtd1295-xnano-x5.dts b/src/arm64/realtek/rtd1295-xnano-x5.dts new file mode 100644 index 000000000000..d7878ff942e6 --- /dev/null +++ b/src/arm64/realtek/rtd1295-xnano-x5.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2017-2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1295.dtsi" + +/ { + compatible = "xnano,x5", "realtek,rtd1295"; + model = "Xnano X5"; + + memory@1f000 { + device_type = "memory"; + reg = <0x1f000 0x3ffe1000>; /* boot ROM to 1 GiB or 2 GiB */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/src/arm64/realtek/rtd1295-zidoo-x9s.dts b/src/arm64/realtek/rtd1295-zidoo-x9s.dts index e98e508b9514..4beb37bb9522 100644 --- a/src/arm64/realtek/rtd1295-zidoo-x9s.dts +++ b/src/arm64/realtek/rtd1295-zidoo-x9s.dts @@ -11,9 +11,9 @@ compatible = "zidoo,x9s", "realtek,rtd1295"; model = "Zidoo X9S"; - memory@0 { + memory@1f000 { device_type = "memory"; - reg = <0x0 0x80000000>; + reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ }; aliases { diff --git a/src/arm64/realtek/rtd1295.dtsi b/src/arm64/realtek/rtd1295.dtsi index 93f0e1d97721..1402abe80ea1 100644 --- a/src/arm64/realtek/rtd1295.dtsi +++ b/src/arm64/realtek/rtd1295.dtsi @@ -2,7 +2,7 @@ /* * Realtek RTD1295 SoC * - * Copyright (c) 2016-2017 Andreas Färber + * Copyright (c) 2016-2019 Andreas Färber */ #include "rtd129x.dtsi" @@ -47,27 +47,16 @@ }; }; - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - tee@10100000 { - reg = <0x10100000 0xf00000>; - no-map; - }; - }; - timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/src/arm64/realtek/rtd1296-ds418.dts b/src/arm64/realtek/rtd1296-ds418.dts index 5a051a52bf88..cc706d13da8b 100644 --- a/src/arm64/realtek/rtd1296-ds418.dts +++ b/src/arm64/realtek/rtd1296-ds418.dts @@ -11,9 +11,9 @@ compatible = "synology,ds418", "realtek,rtd1296"; model = "Synology DiskStation DS418"; - memory@0 { + memory@1f000 { device_type = "memory"; - reg = <0x0 0x80000000>; + reg = <0x1f000 0x7ffe1000>; /* boot ROM to 2 GiB */ }; aliases { diff --git a/src/arm64/realtek/rtd1296.dtsi b/src/arm64/realtek/rtd1296.dtsi index 0f9e59cac086..fb864a139c97 100644 --- a/src/arm64/realtek/rtd1296.dtsi +++ b/src/arm64/realtek/rtd1296.dtsi @@ -50,13 +50,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; }; diff --git a/src/arm64/realtek/rtd129x.dtsi b/src/arm64/realtek/rtd129x.dtsi index 4433114476f5..39aefe66a794 100644 --- a/src/arm64/realtek/rtd129x.dtsi +++ b/src/arm64/realtek/rtd129x.dtsi @@ -2,14 +2,12 @@ /* * Realtek RTD1293/RTD1295/RTD1296 SoC * - * Copyright (c) 2016-2017 Andreas Färber + * Copyright (c) 2016-2019 Andreas Färber */ -/memreserve/ 0x0000000000000000 0x0000000000030000; -/memreserve/ 0x000000000001f000 0x0000000000001000; -/memreserve/ 0x0000000000030000 0x00000000000d0000; +/memreserve/ 0x0000000000000000 0x000000000001f000; +/memreserve/ 0x000000000001f000 0x00000000000e1000; /memreserve/ 0x0000000001b00000 0x00000000004be000; -/memreserve/ 0x0000000001ffe000 0x0000000000004000; #include #include @@ -19,6 +17,25 @@ #address-cells = <1>; #size-cells = <1>; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rpc_comm: rpc@1f000 { + reg = <0x1f000 0x1000>; + }; + + rpc_ringbuf: rpc@1ffe000 { + reg = <0x1ffe000 0x4000>; + }; + + tee: tee@10100000 { + reg = <0x10100000 0xf00000>; + no-map; + }; + }; + arm_pmu: arm-pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; @@ -35,73 +52,61 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - /* Exclude up to 2 GiB of RAM */ - ranges = <0x80000000 0x80000000 0x80000000>; + ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */ + /* Exclude up to 2 GiB of RAM */ + <0x80000000 0x80000000 0x80000000>; - reset1: reset-controller@98000000 { - compatible = "snps,dw-low-reset"; - reg = <0x98000000 0x4>; - #reset-cells = <1>; - }; + rbus: bus@98000000 { + compatible = "simple-bus"; + reg = <0x98000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000000 0x200000>; - reset2: reset-controller@98000004 { - compatible = "snps,dw-low-reset"; - reg = <0x98000004 0x4>; - #reset-cells = <1>; - }; + crt: syscon@0 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x1800>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1800>; + }; - reset3: reset-controller@98000008 { - compatible = "snps,dw-low-reset"; - reg = <0x98000008 0x4>; - #reset-cells = <1>; - }; + iso: syscon@7000 { + compatible = "syscon", "simple-mfd"; + reg = <0x7000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; + }; - reset4: reset-controller@98000050 { - compatible = "snps,dw-low-reset"; - reg = <0x98000050 0x4>; - #reset-cells = <1>; - }; + sb2: syscon@1a000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1a000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; - iso_reset: reset-controller@98007088 { - compatible = "snps,dw-low-reset"; - reg = <0x98007088 0x4>; - #reset-cells = <1>; - }; + misc: syscon@1b000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1b000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b000 0x1000>; + }; - wdt: watchdog@98007680 { - compatible = "realtek,rtd1295-watchdog"; - reg = <0x98007680 0x100>; - clocks = <&osc27M>; - }; - - uart0: serial@98007800 { - compatible = "snps,dw-apb-uart"; - reg = <0x98007800 0x400>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <27000000>; - resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; - status = "disabled"; - }; - - uart1: serial@9801b200 { - compatible = "snps,dw-apb-uart"; - reg = <0x9801b200 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR1>; - status = "disabled"; - }; - - uart2: serial@9801b400 { - compatible = "snps,dw-apb-uart"; - reg = <0x9801b400 0x100>; - reg-shift = <2>; - reg-io-width = <4>; - clock-frequency = <432000000>; - resets = <&reset2 RTD1295_RSTN_UR2>; - status = "disabled"; + scpu_wrapper: syscon@1d000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1d000 0x2000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1d000 0x2000>; + }; }; gic: interrupt-controller@ff011000 { @@ -116,3 +121,75 @@ }; }; }; + +&crt { + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; + + reset4: reset-controller@50 { + compatible = "snps,dw-low-reset"; + reg = <0x50 0x4>; + #reset-cells = <1>; + }; +}; + +&iso { + iso_reset: reset-controller@88 { + compatible = "snps,dw-low-reset"; + reg = <0x88 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@800 { + compatible = "snps,dw-apb-uart"; + reg = <0x800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + status = "disabled"; + }; +}; + +&misc { + uart1: serial@200 { + compatible = "snps,dw-apb-uart"; + reg = <0x200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR1>; + status = "disabled"; + }; + + uart2: serial@400 { + compatible = "snps,dw-apb-uart"; + reg = <0x400 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR2>; + status = "disabled"; + }; +}; diff --git a/src/arm64/realtek/rtd1395-bpi-m4.dts b/src/arm64/realtek/rtd1395-bpi-m4.dts new file mode 100644 index 000000000000..9891967d1315 --- /dev/null +++ b/src/arm64/realtek/rtd1395-bpi-m4.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1395.dtsi" + +/ { + compatible = "bananapi,bpi-m4", "realtek,rtd1395"; + model = "Banana Pi BPI-M4"; + + memory@2f000 { + device_type = "memory"; + reg = <0x2f000 0x3ffd1000>; /* boot ROM to 1 GiB or 2 GiB */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/src/arm64/realtek/rtd1395-lionskin.dts b/src/arm64/realtek/rtd1395-lionskin.dts new file mode 100644 index 000000000000..83f9b536cdea --- /dev/null +++ b/src/arm64/realtek/rtd1395-lionskin.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1395.dtsi" + +/ { + compatible = "realtek,lion-skin", "realtek,rtd1395"; + model = "Realtek Lion Skin EVB"; + + memory@2f000 { + device_type = "memory"; + reg = <0x2f000 0x3ffd1000>; /* boot ROM to 1 GiB or 2 GiB */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* debug console (J1) */ +&uart0 { + status = "okay"; +}; + +/* M.2 slot (CON1) */ +&uart1 { + status = "disabled"; +}; diff --git a/src/arm64/realtek/rtd1395.dtsi b/src/arm64/realtek/rtd1395.dtsi new file mode 100644 index 000000000000..05c9216a87ee --- /dev/null +++ b/src/arm64/realtek/rtd1395.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1395 SoC + * + * Copyright (c) 2019 Andreas Färber + */ + +#include "rtd139x.dtsi" + +/ { + compatible = "realtek,rtd1395"; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; +}; diff --git a/src/arm64/realtek/rtd139x.dtsi b/src/arm64/realtek/rtd139x.dtsi new file mode 100644 index 000000000000..a3c10ceeb586 --- /dev/null +++ b/src/arm64/realtek/rtd139x.dtsi @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1395 SoC family + * + * Copyright (c) 2019 Andreas Färber + */ + +/memreserve/ 0x0000000000000000 0x000000000002f000; +/memreserve/ 0x000000000002f000 0x00000000000d1000; + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rpc_comm: rpc@2f000 { + reg = <0x2f000 0x1000>; + }; + + rpc_ringbuf: rpc@1ffe000 { + reg = <0x1ffe000 0x4000>; + }; + + tee: tee@10100000 { + reg = <0x10100000 0xf00000>; + no-map; + }; + }; + + arm_pmu: arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + #clock-cells = <0>; + clock-output-names = "osc27M"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */ + <0x98000000 0x98000000 0x68000000>; + + rbus: bus@98000000 { + compatible = "simple-bus"; + reg = <0x98000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000000 0x200000>; + + crt: syscon@0 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + iso: syscon@7000 { + compatible = "syscon", "simple-mfd"; + reg = <0x7000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; + }; + + sb2: syscon@1a000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1a000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + + misc: syscon@1b000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1b000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b000 0x1000>; + }; + + scpu_wrapper: syscon@1d000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1d000 0x2000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1d000 0x2000>; + }; + }; + + gic: interrupt-controller@ff011000 { + compatible = "arm,gic-400"; + reg = <0xff011000 0x1000>, + <0xff012000 0x2000>, + <0xff014000 0x2000>, + <0xff016000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; + +&crt { + reset1: reset-controller@0 { + compatible = "snps,dw-low-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + }; + + reset2: reset-controller@4 { + compatible = "snps,dw-low-reset"; + reg = <0x4 0x4>; + #reset-cells = <1>; + }; + + reset3: reset-controller@8 { + compatible = "snps,dw-low-reset"; + reg = <0x8 0x4>; + #reset-cells = <1>; + }; + + reset4: reset-controller@50 { + compatible = "snps,dw-low-reset"; + reg = <0x50 0x4>; + #reset-cells = <1>; + }; +}; + +&iso { + iso_reset: reset-controller@88 { + compatible = "snps,dw-low-reset"; + reg = <0x88 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@680 { + compatible = "realtek,rtd1295-watchdog"; + reg = <0x680 0x100>; + clocks = <&osc27M>; + }; + + uart0: serial@800 { + compatible = "snps,dw-apb-uart"; + reg = <0x800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <27000000>; + resets = <&iso_reset RTD1295_ISO_RSTN_UR0>; + status = "disabled"; + }; +}; + +&misc { + uart1: serial@200 { + compatible = "snps,dw-apb-uart"; + reg = <0x200 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR1>; + status = "disabled"; + }; + + uart2: serial@400 { + compatible = "snps,dw-apb-uart"; + reg = <0x400 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <432000000>; + resets = <&reset2 RTD1295_RSTN_UR2>; + status = "disabled"; + }; +}; diff --git a/src/arm64/realtek/rtd1619-mjolnir.dts b/src/arm64/realtek/rtd1619-mjolnir.dts new file mode 100644 index 000000000000..90ed6681468f --- /dev/null +++ b/src/arm64/realtek/rtd1619-mjolnir.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Copyright (c) 2019 Realtek Semiconductor Corp. + * Copyright (c) 2019 Andreas Färber + */ + +/dts-v1/; + +#include "rtd1619.dtsi" + +/ { + compatible = "realtek,mjolnir", "realtek,rtd1619"; + model = "Realtek Mjolnir EVB"; + + memory@2e000 { + device_type = "memory"; + reg = <0x2e000 0x7ffd2000>; /* boot ROM to 2 GiB */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; +}; + +/* debug console (J1) */ +&uart0 { + status = "okay"; +}; + +/* M.2 slot (CON4) */ +&uart1 { + status = "disabled"; +}; + +/* GPIO connector (T1) */ +&uart2 { + status = "disabled"; +}; diff --git a/src/arm64/realtek/rtd1619.dtsi b/src/arm64/realtek/rtd1619.dtsi new file mode 100644 index 000000000000..e52bf708b04e --- /dev/null +++ b/src/arm64/realtek/rtd1619.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1619 SoC + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + */ + +#include "rtd16xx.dtsi" + +/ { + compatible = "realtek,rtd1619"; +}; diff --git a/src/arm64/realtek/rtd16xx.dtsi b/src/arm64/realtek/rtd16xx.dtsi new file mode 100644 index 000000000000..afba5f04c8ec --- /dev/null +++ b/src/arm64/realtek/rtd16xx.dtsi @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD16xx SoC family + * + * Copyright (c) 2019 Realtek Semiconductor Corp. + * Copyright (c) 2019 Andreas Färber + */ + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rpc_comm: rpc@2f000 { + reg = <0x2f000 0x1000>; + }; + + rpc_ringbuf: rpc@1ffe000 { + reg = <0x1ffe000 0x4000>; + }; + + tee: tee@10100000 { + reg = <0x10100000 0xf00000>; + no-map; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x400>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x500>; + enable-method = "psci"; + next-level-cache = <&l3>; + }; + + l2: l2-cache { + compatible = "cache"; + next-level-cache = <&l3>; + + }; + + l3: l3-cache { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + arm_pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, + <&cpu3>, <&cpu4>, <&cpu5>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + osc27M: osc { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "osc27M"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x0002e000>, /* boot ROM */ + <0x98000000 0x98000000 0x68000000>; + + rbus: bus@98000000 { + compatible = "simple-bus"; + reg = <0x98000000 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x98000000 0x200000>; + + crt: syscon@0 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1000>; + }; + + iso: syscon@7000 { + compatible = "syscon", "simple-mfd"; + reg = <0x7000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x1000>; + }; + + sb2: syscon@1a000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1a000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1a000 0x1000>; + }; + + misc: syscon@1b000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1b000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1b000 0x1000>; + }; + + scpu_wrapper: syscon@1d000 { + compatible = "syscon", "simple-mfd"; + reg = <0x1d000 0x1000>; + reg-io-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1d000 0x1000>; + }; + }; + + gic: interrupt-controller@ff100000 { + compatible = "arm,gic-v3"; + reg = <0xff100000 0x10000>, + <0xff140000 0xc0000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; + +&iso { + uart0: serial0@800 { + compatible = "snps,dw-apb-uart"; + reg = <0x800 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <27000000>; + status = "disabled"; + }; +}; + +&misc { + uart1: serial1@200 { + compatible = "snps,dw-apb-uart"; + reg = <0x200 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <432000000>; + status = "disabled"; + }; + + uart2: serial2@400 { + compatible = "snps,dw-apb-uart"; + reg = <0x400 0x400>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = ; + clock-frequency = <432000000>; + status = "disabled"; + }; +}; diff --git a/src/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi b/src/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi new file mode 100644 index 000000000000..dac6ff49020f --- /dev/null +++ b/src/arm64/renesas/aistarvision-mipi-adapter-2.1.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the AISTARVISION MIPI Adapter V2.1 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/ { + ov5645_vdddo_1v8: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vdddo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ov5645_vdda_2v8: 2p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vdda"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ov5645_vddd_1v5: 1p5v { + compatible = "regulator-fixed"; + regulator-name = "camera_vddd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + imx219_vana_2v8: 2p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vana"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + imx219_vdig_1v8: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vdig"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + imx219_vddl_1v2: 1p2v { + compatible = "regulator-fixed"; + regulator-name = "camera_vddl"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + osc25250_clk: osc25250_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&MIPI_PARENT_I2C { + ov5645: ov5645@3c { + compatible = "ovti,ov5645"; + reg = <0x3c>; + clock-names = "xclk"; + clocks = <&osc25250_clk>; + clock-frequency = <24000000>; + vdddo-supply = <&ov5645_vdddo_1v8>; + vdda-supply = <&ov5645_vdda_2v8>; + vddd-supply = <&ov5645_vddd_1v5>; + + port { + ov5645_ep: endpoint { + }; + }; + }; + + imx219: imx219@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&osc25250_clk>; + VANA-supply = <&imx219_vana_2v8>; + VDIG-supply = <&imx219_vdig_1v8>; + VDDL-supply = <&imx219_vddl_1v2>; + + port { + imx219_ep: endpoint { + }; + }; + }; +}; diff --git a/src/arm64/renesas/r8a774a1.dtsi b/src/arm64/renesas/r8a774a1.dtsi index 79023433a740..a603d947970e 100644 --- a/src/arm64/renesas/r8a774a1.dtsi +++ b/src/arm64/renesas/r8a774a1.dtsi @@ -1000,7 +1000,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -1008,7 +1008,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -1016,7 +1016,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -1024,7 +1024,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xe67b0000 0 0x1000>; interrupts = , @@ -1033,7 +1033,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -1041,7 +1041,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 5>; @@ -1049,7 +1049,7 @@ #iommu-cells = <1>; }; - ipmmu_pv1: mmu@fd950000 { + ipmmu_pv1: iommu@fd950000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfd950000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -1057,7 +1057,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 8>; @@ -1065,7 +1065,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a774a1"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 9>; diff --git a/src/arm64/renesas/r8a774b1.dtsi b/src/arm64/renesas/r8a774b1.dtsi index 3137f735974b..1e51855c7cd3 100644 --- a/src/arm64/renesas/r8a774b1.dtsi +++ b/src/arm64/renesas/r8a774b1.dtsi @@ -874,7 +874,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -882,7 +882,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -890,7 +890,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -898,7 +898,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xe67b0000 0 0x1000>; interrupts = , @@ -907,7 +907,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -915,7 +915,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -923,7 +923,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -931,7 +931,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -939,7 +939,7 @@ #iommu-cells = <1>; }; - ipmmu_vp0: mmu@fe990000 { + ipmmu_vp0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a774b1"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; diff --git a/src/arm64/renesas/r8a774c0-ek874-mipi-2.1.dts b/src/arm64/renesas/r8a774c0-ek874-mipi-2.1.dts new file mode 100644 index 000000000000..f0829e905506 --- /dev/null +++ b/src/arm64/renesas/r8a774c0-ek874-mipi-2.1.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Silicon Linux RZ/G2E 96board platform (CAT874) + * connected with aistarvision-mipi-v2-adapter board + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a774c0-ek874.dts" +#define MIPI_PARENT_I2C i2c3 +#include "aistarvision-mipi-adapter-2.1.dtsi" + +/ { + model = "Silicon Linux RZ/G2E evaluation kit EK874 (CAT874 + CAT875) with aistarvision-mipi-v2-adapter board"; + compatible = "si-linux,cat875", "si-linux,cat874", "renesas,r8a774c0"; +}; + +&i2c3 { + status = "okay"; +}; + +&vin4 { + status = "okay"; +}; + +&vin5 { + status = "okay"; +}; + +&csi40 { + status = "okay"; + + ports { + port { + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&ov5645_ep>; + }; + }; + }; +}; + +&ov5645 { + enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + + port { + ov5645_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi40_in>; + }; + }; +}; + +&imx219 { + port { + imx219_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + /* uncomment remote-endpoint property to tie imx219 to + * CSI2 also make sure remote-endpoint for ov5645 camera + * is commented and remote endpoint phandle in csi40_in + * is imx219_ep + */ + /* remote-endpoint = <&csi40_in>; */ + }; + }; +}; diff --git a/src/arm64/renesas/r8a774c0.dtsi b/src/arm64/renesas/r8a774c0.dtsi index 22785cbddff5..5c72a7efbb03 100644 --- a/src/arm64/renesas/r8a774c0.dtsi +++ b/src/arm64/renesas/r8a774c0.dtsi @@ -847,7 +847,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -855,7 +855,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -863,7 +863,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -871,7 +871,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xe67b0000 0 0x1000>; interrupts = , @@ -880,7 +880,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -888,7 +888,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -896,7 +896,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -904,7 +904,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -912,7 +912,7 @@ #iommu-cells = <1>; }; - ipmmu_vp0: mmu@fe990000 { + ipmmu_vp0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a774c0"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; diff --git a/src/arm64/renesas/r8a77950.dtsi b/src/arm64/renesas/r8a77950.dtsi index 3975eecd50c4..d716c4386ae9 100644 --- a/src/arm64/renesas/r8a77950.dtsi +++ b/src/arm64/renesas/r8a77950.dtsi @@ -77,7 +77,7 @@ /delete-node/ dma-controller@e6460000; /delete-node/ dma-controller@e6470000; - ipmmu_mp1: mmu@ec680000 { + ipmmu_mp1: iommu@ec680000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xec680000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 5>; @@ -85,7 +85,7 @@ #iommu-cells = <1>; }; - ipmmu_sy: mmu@e7730000 { + ipmmu_sy: iommu@e7730000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xe7730000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 8>; @@ -93,11 +93,11 @@ #iommu-cells = <1>; }; - /delete-node/ mmu@fd950000; - /delete-node/ mmu@fd960000; - /delete-node/ mmu@fd970000; - /delete-node/ mmu@febe0000; - /delete-node/ mmu@fe980000; + /delete-node/ iommu@fd950000; + /delete-node/ iommu@fd960000; + /delete-node/ iommu@fd970000; + /delete-node/ iommu@febe0000; + /delete-node/ iommu@fe980000; xhci1: usb@ee040000 { compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; diff --git a/src/arm64/renesas/r8a77951.dtsi b/src/arm64/renesas/r8a77951.dtsi index 52229546454c..61d67d9714ab 100644 --- a/src/arm64/renesas/r8a77951.dtsi +++ b/src/arm64/renesas/r8a77951.dtsi @@ -1073,7 +1073,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -1081,7 +1081,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -1089,7 +1089,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -1097,7 +1097,7 @@ #iommu-cells = <1>; }; - ipmmu_ir: mmu@ff8b0000 { + ipmmu_ir: iommu@ff8b0000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xff8b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 3>; @@ -1105,7 +1105,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xe67b0000 0 0x1000>; interrupts = , @@ -1114,7 +1114,7 @@ #iommu-cells = <1>; }; - ipmmu_mp0: mmu@ec670000 { + ipmmu_mp0: iommu@ec670000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -1122,7 +1122,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -1130,7 +1130,7 @@ #iommu-cells = <1>; }; - ipmmu_pv1: mmu@fd950000 { + ipmmu_pv1: iommu@fd950000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfd950000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 7>; @@ -1138,7 +1138,7 @@ #iommu-cells = <1>; }; - ipmmu_pv2: mmu@fd960000 { + ipmmu_pv2: iommu@fd960000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfd960000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 8>; @@ -1146,7 +1146,7 @@ #iommu-cells = <1>; }; - ipmmu_pv3: mmu@fd970000 { + ipmmu_pv3: iommu@fd970000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfd970000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 9>; @@ -1154,7 +1154,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 10>; @@ -1162,7 +1162,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -1170,7 +1170,7 @@ #iommu-cells = <1>; }; - ipmmu_vc1: mmu@fe6f0000 { + ipmmu_vc1: iommu@fe6f0000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfe6f0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 13>; @@ -1178,7 +1178,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -1186,7 +1186,7 @@ #iommu-cells = <1>; }; - ipmmu_vi1: mmu@febe0000 { + ipmmu_vi1: iommu@febe0000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfebe0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 15>; @@ -1194,7 +1194,7 @@ #iommu-cells = <1>; }; - ipmmu_vp0: mmu@fe990000 { + ipmmu_vp0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; @@ -1202,7 +1202,7 @@ #iommu-cells = <1>; }; - ipmmu_vp1: mmu@fe980000 { + ipmmu_vp1: iommu@fe980000 { compatible = "renesas,ipmmu-r8a7795"; reg = <0 0xfe980000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 17>; diff --git a/src/arm64/renesas/r8a77960.dtsi b/src/arm64/renesas/r8a77960.dtsi index 31282367d3ac..33bf62acffbb 100644 --- a/src/arm64/renesas/r8a77960.dtsi +++ b/src/arm64/renesas/r8a77960.dtsi @@ -997,7 +997,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -1005,7 +1005,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -1013,7 +1013,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -1021,7 +1021,7 @@ #iommu-cells = <1>; }; - ipmmu_ir: mmu@ff8b0000 { + ipmmu_ir: iommu@ff8b0000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xff8b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 3>; @@ -1029,7 +1029,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xe67b0000 0 0x1000>; interrupts = , @@ -1038,7 +1038,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -1046,7 +1046,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 5>; @@ -1054,7 +1054,7 @@ #iommu-cells = <1>; }; - ipmmu_pv1: mmu@fd950000 { + ipmmu_pv1: iommu@fd950000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xfd950000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -1062,7 +1062,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 7>; @@ -1070,7 +1070,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 8>; @@ -1078,7 +1078,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a7796"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 9>; diff --git a/src/arm64/renesas/r8a77961.dtsi b/src/arm64/renesas/r8a77961.dtsi index 0d96f2d3492b..760e738b75b3 100644 --- a/src/arm64/renesas/r8a77961.dtsi +++ b/src/arm64/renesas/r8a77961.dtsi @@ -626,21 +626,150 @@ status = "disabled"; }; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a77961", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a77961", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; reg = <0 0xe6550000 0 0x60>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a77961", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a77961", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a77961", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; }; hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a77961", + "renesas,rcar-gen3-usbhs"; reg = <0 0xe6590000 0 0x200>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 704>, <&cpg 703>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a77961-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a77961-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; }; usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a77961-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 328>; #phy-cells = <0>; - /* placeholder */ + status = "disabled"; }; arm_cc630p: crypto@e6601000 { @@ -799,15 +928,108 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; reg = <0 0xe6e31000 0 8>; #pwm-cells = <2>; - /* placeholder */ + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a77961", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; }; scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a77961", + "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6e68000 0 64>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; }; scif2: serial@e6e88000 { @@ -819,11 +1041,63 @@ <&cpg CPG_CORE R8A77961_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 310>; status = "disabled"; }; + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a77961", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a77961", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a77961", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A77961_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + vin0: video@e6ef0000 { reg = <0 0xe6ef0000 0 0x1000>; /* placeholder */ @@ -889,43 +1163,98 @@ }; xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a77961", + "renesas,rcar-gen3-xhci"; reg = <0 0xee000000 0 0xc00>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; }; usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a77961-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; reg = <0 0xee020000 0 0x400>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; }; ohci0: usb@ee080000 { + compatible = "generic-ohci"; reg = <0 0xee080000 0 0x100>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + status = "disabled"; }; ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; reg = <0 0xee0a0000 0 0x100>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; }; ehci0: usb@ee080100 { + compatible = "generic-ehci"; reg = <0 0xee080100 0 0x100>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + status = "disabled"; }; ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; reg = <0 0xee0a0100 0 0x100>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; }; usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a77961", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee080200 0 0x700>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + #phy-cells = <1>; + status = "disabled"; }; usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a77961", + "renesas,rcar-gen3-usb2-phy"; reg = <0 0xee0a0200 0 0x700>; - /* placeholder */ + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <1>; + status = "disabled"; }; sdhi0: sd@ee100000 { @@ -994,13 +1323,57 @@ }; pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a77961", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; }; pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a77961", + "renesas,pcie-rcar-gen3"; reg = <0 0xee800000 0 0x80000>; - /* placeholder */ + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, + <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, + <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; }; csi20: csi2@fea80000 { diff --git a/src/arm64/renesas/r8a77965.dtsi b/src/arm64/renesas/r8a77965.dtsi index d82dd4e67b62..6f7ab39fd282 100644 --- a/src/arm64/renesas/r8a77965.dtsi +++ b/src/arm64/renesas/r8a77965.dtsi @@ -867,7 +867,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -875,7 +875,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -883,7 +883,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -891,7 +891,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xe67b0000 0 0x1000>; interrupts = , @@ -900,7 +900,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -908,7 +908,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -916,7 +916,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 10>; @@ -924,7 +924,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -932,7 +932,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -940,7 +940,7 @@ #iommu-cells = <1>; }; - ipmmu_vp0: mmu@fe990000 { + ipmmu_vp0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a77965"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; diff --git a/src/arm64/renesas/r8a77970.dtsi b/src/arm64/renesas/r8a77970.dtsi index a009c0ebc8b4..bd95ecb1b40d 100644 --- a/src/arm64/renesas/r8a77970.dtsi +++ b/src/arm64/renesas/r8a77970.dtsi @@ -985,7 +985,7 @@ <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a77970"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -993,7 +993,7 @@ #iommu-cells = <1>; }; - ipmmu_ir: mmu@ff8b0000 { + ipmmu_ir: iommu@ff8b0000 { compatible = "renesas,ipmmu-r8a77970"; reg = <0 0xff8b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 3>; @@ -1001,7 +1001,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a77970"; reg = <0 0xe67b0000 0 0x1000>; interrupts = , @@ -1010,7 +1010,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a77970"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 7>; @@ -1018,7 +1018,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a77970"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 9>; diff --git a/src/arm64/renesas/r8a77980.dtsi b/src/arm64/renesas/r8a77980.dtsi index d672b320bc14..387e6d99f2f3 100644 --- a/src/arm64/renesas/r8a77980.dtsi +++ b/src/arm64/renesas/r8a77980.dtsi @@ -1266,7 +1266,7 @@ status = "disabled"; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -1274,7 +1274,7 @@ #iommu-cells = <1>; }; - ipmmu_ir: mmu@ff8b0000 { + ipmmu_ir: iommu@ff8b0000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xff8b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 3>; @@ -1282,7 +1282,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xe67b0000 0 0x1000>; interrupts = , @@ -1291,7 +1291,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 10>; @@ -1299,7 +1299,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe990000 { + ipmmu_vc0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -1307,7 +1307,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -1315,7 +1315,7 @@ #iommu-cells = <1>; }; - ipmmu_vip0: mmu@e7b00000 { + ipmmu_vip0: iommu@e7b00000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xe7b00000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -1323,7 +1323,7 @@ #iommu-cells = <1>; }; - ipmmu_vip1: mmu@e7960000 { + ipmmu_vip1: iommu@e7960000 { compatible = "renesas,ipmmu-r8a77980"; reg = <0 0xe7960000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 11>; diff --git a/src/arm64/renesas/r8a77990.dtsi b/src/arm64/renesas/r8a77990.dtsi index 1543f18e834f..cd11f24744d4 100644 --- a/src/arm64/renesas/r8a77990.dtsi +++ b/src/arm64/renesas/r8a77990.dtsi @@ -817,7 +817,7 @@ <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -825,7 +825,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -833,7 +833,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -841,7 +841,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xe67b0000 0 0x1000>; interrupts = , @@ -850,7 +850,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -858,7 +858,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -866,7 +866,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 10>; @@ -874,7 +874,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -882,7 +882,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -890,7 +890,7 @@ #iommu-cells = <1>; }; - ipmmu_vp0: mmu@fe990000 { + ipmmu_vp0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a77990"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; diff --git a/src/arm64/renesas/r8a77995.dtsi b/src/arm64/renesas/r8a77995.dtsi index e8d2290fe79d..e5617ec0f49c 100644 --- a/src/arm64/renesas/r8a77995.dtsi +++ b/src/arm64/renesas/r8a77995.dtsi @@ -507,7 +507,7 @@ <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; }; - ipmmu_ds0: mmu@e6740000 { + ipmmu_ds0: iommu@e6740000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xe6740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 0>; @@ -515,7 +515,7 @@ #iommu-cells = <1>; }; - ipmmu_ds1: mmu@e7740000 { + ipmmu_ds1: iommu@e7740000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xe7740000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 1>; @@ -523,7 +523,7 @@ #iommu-cells = <1>; }; - ipmmu_hc: mmu@e6570000 { + ipmmu_hc: iommu@e6570000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xe6570000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 2>; @@ -531,7 +531,7 @@ #iommu-cells = <1>; }; - ipmmu_mm: mmu@e67b0000 { + ipmmu_mm: iommu@e67b0000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xe67b0000 0 0x1000>; interrupts = , @@ -540,7 +540,7 @@ #iommu-cells = <1>; }; - ipmmu_mp: mmu@ec670000 { + ipmmu_mp: iommu@ec670000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xec670000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 4>; @@ -548,7 +548,7 @@ #iommu-cells = <1>; }; - ipmmu_pv0: mmu@fd800000 { + ipmmu_pv0: iommu@fd800000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xfd800000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 6>; @@ -556,7 +556,7 @@ #iommu-cells = <1>; }; - ipmmu_rt: mmu@ffc80000 { + ipmmu_rt: iommu@ffc80000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xffc80000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 10>; @@ -564,7 +564,7 @@ #iommu-cells = <1>; }; - ipmmu_vc0: mmu@fe6b0000 { + ipmmu_vc0: iommu@fe6b0000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xfe6b0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 12>; @@ -572,7 +572,7 @@ #iommu-cells = <1>; }; - ipmmu_vi0: mmu@febd0000 { + ipmmu_vi0: iommu@febd0000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xfebd0000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 14>; @@ -580,7 +580,7 @@ #iommu-cells = <1>; }; - ipmmu_vp0: mmu@fe990000 { + ipmmu_vp0: iommu@fe990000 { compatible = "renesas,ipmmu-r8a77995"; reg = <0 0xfe990000 0 0x1000>; renesas,ipmmu-main = <&ipmmu_mm 16>; diff --git a/src/arm64/rockchip/px30.dtsi b/src/arm64/rockchip/px30.dtsi index adc9b8bf5eaa..a6b8427156d5 100644 --- a/src/arm64/rockchip/px30.dtsi +++ b/src/arm64/rockchip/px30.dtsi @@ -931,6 +931,7 @@ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + bus-width = <4>; fifo-depth = <0x100>; max-frequency = <150000000>; pinctrl-names = "default"; @@ -946,6 +947,7 @@ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + bus-width = <4>; fifo-depth = <0x100>; max-frequency = <150000000>; pinctrl-names = "default"; @@ -961,6 +963,7 @@ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + bus-width = <8>; fifo-depth = <0x100>; max-frequency = <150000000>; pinctrl-names = "default"; diff --git a/src/arm64/rockchip/rk3308-roc-cc.dts b/src/arm64/rockchip/rk3308-roc-cc.dts index aa256350b18f..7a96be10eaf0 100644 --- a/src/arm64/rockchip/rk3308-roc-cc.dts +++ b/src/arm64/rockchip/rk3308-roc-cc.dts @@ -28,14 +28,14 @@ leds { compatible = "gpio-leds"; - power { + power_led: led-0 { label = "firefly:red:power"; linux,default-trigger = "ir-power-click"; default-state = "on"; gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; }; - user { + user_led: led-1 { label = "firefly:blue:user"; linux,default-trigger = "ir-user-click"; default-state = "off"; @@ -123,9 +123,7 @@ }; &emmc { - bus-width = <8>; cap-mmc-highspeed; - disable-wp; mmc-hs200-1_8v; non-removable; status = "okay"; @@ -171,7 +169,6 @@ }; &sdmmc { - bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; card-detect-delay = <300>; diff --git a/src/arm64/rockchip/rk3326-odroid-go2.dts b/src/arm64/rockchip/rk3326-odroid-go2.dts new file mode 100644 index 000000000000..b3a8f936578f --- /dev/null +++ b/src/arm64/rockchip/rk3326-odroid-go2.dts @@ -0,0 +1,557 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Hardkernel Co., Ltd + * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include +#include +#include +#include "rk3326.dtsi" + +/ { + model = "ODROID-GO Advance"; + compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc_bl>; + pwms = <&pwm1 0 25000 0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&btn_pins>; + + /* + * *** ODROIDGO2-Advance Switch layout *** + * |------------------------------------------------| + * | sw15 sw16 | + * |------------------------------------------------| + * | sw1 |-------------------| sw8 | + * | sw3 sw4 | | sw7 sw5 | + * | sw2 | LCD Display | sw6 | + * | | | | + * | |-------------------| | + * | sw9 sw10 sw11 sw12 sw13 sw14 | + * |------------------------------------------------| + */ + + sw1 { + gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; + label = "DPAD-UP"; + linux,code = ; + }; + sw2 { + gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + label = "DPAD-DOWN"; + linux,code = ; + }; + sw3 { + gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; + label = "DPAD-LEFT"; + linux,code = ; + }; + sw4 { + gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; + label = "DPAD-RIGHT"; + linux,code = ; + }; + sw5 { + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + label = "BTN-A"; + linux,code = ; + }; + sw6 { + gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; + label = "BTN-B"; + linux,code = ; + }; + sw7 { + gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + label = "BTN-Y"; + linux,code = ; + }; + sw8 { + gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; + label = "BTN-X"; + linux,code = ; + }; + sw9 { + gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; + label = "F1"; + linux,code = ; + }; + sw10 { + gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; + label = "F2"; + linux,code = ; + }; + sw11 { + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + label = "F3"; + linux,code = ; + }; + sw12 { + gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; + label = "F4"; + linux,code = ; + }; + sw13 { + gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>; + label = "F5"; + linux,code = ; + }; + sw14 { + gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>; + label = "F6"; + linux,code = ; + }; + sw15 { + gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; + label = "TOP-LEFT"; + linux,code = ; + }; + sw16 { + gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; + label = "TOP-RIGHT"; + linux,code = ; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&blue_led_pin>; + + blue_led: led-0 { + label = "blue:heartbeat"; + gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc_host { + compatible = "regulator-fixed"; + regulator-name = "vcc_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <&vccsys>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&cru { + assigned-clocks = <&cru PLL_NPLL>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>, + <&cru PLL_CPLL>; + + assigned-clock-rates = <1188000000>, + <200000000>, <200000000>, + <150000000>, <150000000>, + <100000000>, <200000000>, + <17000000>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + ports { + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + panel@0 { + compatible = "elida,kd35t133"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_lcd>; + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + vdd-supply = <&vcc_lcd>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_dphy { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <16>; + i2c-scl-rising-time-ns = <280>; + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "xin32k"; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vccsys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v3_pmu: LDO_REG4 { + regulator-name = "vcc3v3_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_bl: LDO_REG7 { + regulator-name = "vcc_bl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lcd: LDO_REG8 { + regulator-name = "vcc_lcd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc_cam: LDO_REG9 { + regulator-name = "vcc_cam"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; + }; +}; + +/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */ +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; + +/* I2S 1 Channel Used */ +&i2s1_2ch { + status = "okay"; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + card-detect-delay = <200>; + cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "disabled"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&pinctrl { + btns { + btn_pins: btn-pins { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + blue_led_pin: blue-led-pin { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dc_det: dc-det { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; + }; + }; +}; diff --git a/src/arm64/rockchip/rk3326.dtsi b/src/arm64/rockchip/rk3326.dtsi new file mode 100644 index 000000000000..2ba6da125137 --- /dev/null +++ b/src/arm64/rockchip/rk3326.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include "px30.dtsi" + +&display_subsystem { + ports = <&vopb_out>; +}; + +/delete-node/ &dsi_in_vopl; +/delete-node/ &lvds_vopl_in; +/delete-node/ &vopl; +/delete-node/ &vopl_mmu; diff --git a/src/arm64/rockchip/rk3328-a1.dts b/src/arm64/rockchip/rk3328-a1.dts index 797e90a3ac92..37f307cfa4cc 100644 --- a/src/arm64/rockchip/rk3328-a1.dts +++ b/src/arm64/rockchip/rk3328-a1.dts @@ -115,7 +115,7 @@ #address-cells = <1>; #size-cells = <0>; - rtl8211f: phy@0 { + rtl8211f: ethernet-phy@0 { reg = <0>; reset-assert-us = <10000>; reset-deassert-us = <30000>; diff --git a/src/arm64/rockchip/rk3328-roc-cc.dts b/src/arm64/rockchip/rk3328-roc-cc.dts index 8d553c92182a..34db48c274e5 100644 --- a/src/arm64/rockchip/rk3328-roc-cc.dts +++ b/src/arm64/rockchip/rk3328-roc-cc.dts @@ -86,7 +86,7 @@ leds { compatible = "gpio-leds"; - power { + power_led: led-0 { label = "firefly:blue:power"; linux,default-trigger = "heartbeat"; gpios = <&rk805 1 GPIO_ACTIVE_LOW>; @@ -94,7 +94,7 @@ mode = <0x23>; }; - user { + user_led: led-1 { label = "firefly:yellow:user"; linux,default-trigger = "mmc1"; gpios = <&rk805 0 GPIO_ACTIVE_LOW>; diff --git a/src/arm64/rockchip/rk3328-rock64.dts b/src/arm64/rockchip/rk3328-rock64.dts index ebf3eb222e1f..6e09c223ed57 100644 --- a/src/arm64/rockchip/rk3328-rock64.dts +++ b/src/arm64/rockchip/rk3328-rock64.dts @@ -73,12 +73,12 @@ leds { compatible = "gpio-leds"; - power { + power_led: led-0 { gpios = <&rk805 1 GPIO_ACTIVE_LOW>; linux,default-trigger = "mmc0"; }; - standby { + standby_led: led-1 { gpios = <&rk805 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; diff --git a/src/arm64/rockchip/rk3328.dtsi b/src/arm64/rockchip/rk3328.dtsi index a4d591d91533..d399883d4b75 100644 --- a/src/arm64/rockchip/rk3328.dtsi +++ b/src/arm64/rockchip/rk3328.dtsi @@ -934,7 +934,7 @@ #address-cells = <1>; #size-cells = <0>; - phy: phy@0 { + phy: ethernet-phy@0 { compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; reg = <0>; clocks = <&cru SCLK_MAC2PHY_OUT>; diff --git a/src/arm64/rockchip/rk3368-geekbox.dts b/src/arm64/rockchip/rk3368-geekbox.dts index 1d0778ff217c..46357d1d77cd 100644 --- a/src/arm64/rockchip/rk3368-geekbox.dts +++ b/src/arm64/rockchip/rk3368-geekbox.dts @@ -50,13 +50,13 @@ leds: gpio-leds { compatible = "gpio-leds"; - blue { + blue_led: led-0 { gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; label = "geekbox:blue:led"; default-state = "on"; }; - red { + red_led: led-1 { gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; label = "geekbox:red:led"; default-state = "off"; diff --git a/src/arm64/rockchip/rk3368-orion-r68-meta.dts b/src/arm64/rockchip/rk3368-orion-r68-meta.dts index 6cc310255da8..b058ce999e3b 100644 --- a/src/arm64/rockchip/rk3368-orion-r68-meta.dts +++ b/src/arm64/rockchip/rk3368-orion-r68-meta.dts @@ -50,7 +50,7 @@ leds: gpio-leds { compatible = "gpio-leds"; - red { + red_led: led-0 { gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; label = "orion:red:led"; pinctrl-names = "default"; @@ -58,7 +58,7 @@ default-state = "on"; }; - blue { + blue_led: led-1 { gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; label = "orion:blue:led"; pinctrl-names = "default"; diff --git a/src/arm64/rockchip/rk3368-r88.dts b/src/arm64/rockchip/rk3368-r88.dts index 006a1fb6a816..236ab0f1b206 100644 --- a/src/arm64/rockchip/rk3368-r88.dts +++ b/src/arm64/rockchip/rk3368-r88.dts @@ -43,7 +43,7 @@ leds: gpio-leds { compatible = "gpio-leds"; - work { + work_led: led-0 { gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; label = "r88:green:led"; pinctrl-names = "default"; diff --git a/src/arm64/rockchip/rk3399-ficus.dts b/src/arm64/rockchip/rk3399-ficus.dts index ebe2ee77ba1f..1ce85a5816e4 100644 --- a/src/arm64/rockchip/rk3399-ficus.dts +++ b/src/arm64/rockchip/rk3399-ficus.dts @@ -27,42 +27,43 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>, - <&user_led4>, <&wlan_led>, <&bt_led>; + pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>, + <&user_led3_pin>, <&user_led4_pin>, + <&wlan_led_pin>, <&bt_led_pin>; - user_led1 { + user_led1: led-1 { label = "red:user1"; gpios = <&gpio4 25 0>; linux,default-trigger = "heartbeat"; }; - user_led2 { + user_led2: led-2 { label = "red:user2"; gpios = <&gpio4 26 0>; linux,default-trigger = "mmc0"; }; - user_led3 { + user_led3: led-3 { label = "red:user3"; gpios = <&gpio4 30 0>; linux,default-trigger = "mmc1"; }; - user_led4 { + user_led4: led-4 { label = "red:user4"; gpios = <&gpio1 0 0>; panic-indicator; linux,default-trigger = "none"; }; - wlan_active_led { + wlan_active_led: led-5 { label = "red:wlan"; gpios = <&gpio1 1 0>; linux,default-trigger = "phy0tx"; default-state = "off"; }; - bt_active_led { + bt_active_led: led-6 { label = "red:bt"; gpios = <&gpio1 4 0>; linux,default-trigger = "hci0-power"; @@ -114,32 +115,32 @@ }; leds { - user_led1: user_led1 { + user_led1_pin: user-led1-pin { rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; }; - user_led2: user_led2 { + user_led2_pin: user-led2-pin { rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; - user_led3: user_led3 { + user_led3_pin: user-led3-pin { rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; }; - user_led4: user_led4 { + user_led4_pin: user-led4-pin { rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; }; - wlan_led: wlan_led { + wlan_led_pin: wlan-led-pin { rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; - bt_led: bt_led { + bt_led_pin: bt-led-pin { rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/src/arm64/rockchip/rk3399-firefly.dts b/src/arm64/rockchip/rk3399-firefly.dts index d63faf38cc81..20b5599f5e78 100644 --- a/src/arm64/rockchip/rk3399-firefly.dts +++ b/src/arm64/rockchip/rk3399-firefly.dts @@ -91,15 +91,15 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&work_led_gpio>, <&diy_led_gpio>; + pinctrl-0 = <&work_led_pin>, <&diy_led_pin>; - work-led { + work_led: led-0 { label = "work"; default-state = "on"; gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; }; - diy-led { + diy_led: led-1 { label = "diy"; default-state = "off"; gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; @@ -629,11 +629,11 @@ }; leds { - work_led_gpio: work_led-gpio { + work_led_pin: work-led-pin { rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; }; - diy_led_gpio: diy_led-gpio { + diy_led_pin: diy-led-pin { rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/src/arm64/rockchip/rk3399-hugsun-x99.dts b/src/arm64/rockchip/rk3399-hugsun-x99.dts index aee484a05181..bf87fa32d3b1 100644 --- a/src/arm64/rockchip/rk3399-hugsun-x99.dts +++ b/src/arm64/rockchip/rk3399-hugsun-x99.dts @@ -39,9 +39,9 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&power_led_gpio>; + pinctrl-0 = <&power_led_pin>; - led-0 { + power_led: led-0 { label = "blue:power"; gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; default-state = "on"; @@ -510,7 +510,7 @@ }; leds { - power_led_gpio: power-led-gpio { + power_led_pin: power-led-pin { rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @@ -633,7 +633,6 @@ &spdif { status = "okay"; pinctrl-0 = <&spdif_bus_1>; - #sound-dai-cells = <0>; }; &spi1 { diff --git a/src/arm64/rockchip/rk3399-nanopi4.dtsi b/src/arm64/rockchip/rk3399-nanopi4.dtsi index c88018a0ef35..1d246c2caa3c 100644 --- a/src/arm64/rockchip/rk3399-nanopi4.dtsi +++ b/src/arm64/rockchip/rk3399-nanopi4.dtsi @@ -182,7 +182,7 @@ #address-cells = <1>; #size-cells = <0>; - rtl8211e: phy@1 { + rtl8211e: ethernet-phy@1 { reg = <1>; interrupt-parent = <&gpio3>; interrupts = ; @@ -525,7 +525,7 @@ }; }; - phy { + gmac { phy_intb: phy-intb { rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; diff --git a/src/arm64/rockchip/rk3399-orangepi.dts b/src/arm64/rockchip/rk3399-orangepi.dts index f9f7246d4d2f..6163ae8063a7 100644 --- a/src/arm64/rockchip/rk3399-orangepi.dts +++ b/src/arm64/rockchip/rk3399-orangepi.dts @@ -214,7 +214,7 @@ #address-cells = <1>; #size-cells = <0>; - rtl8211e: phy@1 { + rtl8211e: ethernet-phy@1 { reg = <1>; interrupt-parent = <&gpio3>; interrupts = ; @@ -554,7 +554,7 @@ }; }; - phy { + gmac { phy_intb: phy-intb { rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; }; diff --git a/src/arm64/rockchip/rk3399-pinebook-pro.dts b/src/arm64/rockchip/rk3399-pinebook-pro.dts index c49982dfd8fc..cb0245d2226d 100644 --- a/src/arm64/rockchip/rk3399-pinebook-pro.dts +++ b/src/arm64/rockchip/rk3399-pinebook-pro.dts @@ -90,9 +90,9 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&pwrled_gpio &slpled_gpio>; + pinctrl-0 = <&pwr_led_pin &slp_led_pin>; - green-led { + green_led: led-0 { color = ; default-state = "on"; function = LED_FUNCTION_POWER; @@ -100,7 +100,7 @@ label = "green:power"; }; - red-led { + red_led: led-1 { color = ; default-state = "off"; function = LED_FUNCTION_STANDBY; @@ -744,7 +744,6 @@ }; &i2s1 { - #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2s_8ch_mclk_gpio>, <&i2s1_2ch_bus>; rockchip,capture-channels = <8>; @@ -826,11 +825,11 @@ }; leds { - pwrled_gpio: pwrled_gpio { + pwr_led_pin: pwr-led-pin { rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; }; - slpled_gpio: slpled_gpio { + slp_led_pin: slp-led-pin { rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/src/arm64/rockchip/rk3399-rock960.dts b/src/arm64/rockchip/rk3399-rock960.dts index 437a75f31ad4..c88295782e7b 100644 --- a/src/arm64/rockchip/rk3399-rock960.dts +++ b/src/arm64/rockchip/rk3399-rock960.dts @@ -17,42 +17,43 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>, - <&user_led4>, <&wlan_led>, <&bt_led>; + pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>, + <&user_led3_pin>, <&user_led4_pin>, + <&wlan_led_pin>, <&bt_led_pin>; - user_led1 { + user_led1: led-1 { label = "green:user1"; gpios = <&gpio4 RK_PC2 0>; linux,default-trigger = "heartbeat"; }; - user_led2 { + user_led2: led-2 { label = "green:user2"; gpios = <&gpio4 RK_PC6 0>; linux,default-trigger = "mmc0"; }; - user_led3 { + user_led3: led-3 { label = "green:user3"; gpios = <&gpio4 RK_PD0 0>; linux,default-trigger = "mmc1"; }; - user_led4 { + user_led4: led-4 { label = "green:user4"; gpios = <&gpio4 RK_PD4 0>; panic-indicator; linux,default-trigger = "none"; }; - wlan_active_led { + wlan_active_led: led-5 { label = "yellow:wlan"; gpios = <&gpio4 RK_PD5 0>; linux,default-trigger = "phy0tx"; default-state = "off"; }; - bt_active_led { + bt_active_led: led-6 { label = "blue:bt"; gpios = <&gpio4 RK_PD6 0>; linux,default-trigger = "hci0-power"; @@ -68,32 +69,32 @@ &pinctrl { leds { - user_led1: user_led1 { + user_led1_pin: user-led1-pin { rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; }; - user_led2: user_led2 { + user_led2_pin: user-led2-pin { rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; }; - user_led3: user_led3 { + user_led3_pin: user-led3-pin { rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; - user_led4: user_led4 { + user_led4_pin: user-led4-pin { rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; - wlan_led: wlan_led { + wlan_led_pin: wlan-led-pin { rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; - bt_led: bt_led { + bt_led_pin: bt-led-pin { rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; }; diff --git a/src/arm64/rockchip/rk3399-rockpro64.dtsi b/src/arm64/rockchip/rk3399-rockpro64.dtsi index 9bca25801260..6788ab28f89a 100644 --- a/src/arm64/rockchip/rk3399-rockpro64.dtsi +++ b/src/arm64/rockchip/rk3399-rockpro64.dtsi @@ -96,6 +96,24 @@ vin-supply = <&vcc_1v8>; }; + /* micro SD card power */ + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -603,6 +621,13 @@ }; }; + sdcard { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -661,6 +686,8 @@ max-frequency = <150000000>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; status = "okay"; }; diff --git a/src/arm64/rockchip/rk3399.dtsi b/src/arm64/rockchip/rk3399.dtsi index 1448f358ed0a..2581e9cc7a1d 100644 --- a/src/arm64/rockchip/rk3399.dtsi +++ b/src/arm64/rockchip/rk3399.dtsi @@ -1056,6 +1056,16 @@ clocks = <&cru HCLK_SDIO>; pm_qos = <&qos_sdioaudio>; }; + pd_tcpc0@RK3399_PD_TCPD0 { + reg = ; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + }; + pd_tcpc1@RK3399_PD_TCPD1 { + reg = ; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + }; pd_usb3@RK3399_PD_USB3 { reg = ; clocks = <&cru ACLK_USB3>; @@ -1088,16 +1098,6 @@ pm_qos = <&qos_isp1_m0>, <&qos_isp1_m1>; }; - pd_tcpc0@RK3399_PD_TCPC0 { - reg = ; - clocks = <&cru SCLK_UPHY0_TCPDCORE>, - <&cru SCLK_UPHY0_TCPDPHY_REF>; - }; - pd_tcpc1@RK3399_PD_TCPC1 { - reg = ; - clocks = <&cru SCLK_UPHY1_TCPDCORE>, - <&cru SCLK_UPHY1_TCPDPHY_REF>; - }; pd_vo@RK3399_PD_VO { reg = ; #address-cells = <1>; @@ -1269,6 +1269,18 @@ power-domains = <&power RK3399_PD_VCODEC>; }; + vdec: video-codec@ff660000 { + compatible = "rockchip,rk3399-vdec"; + reg = <0x0 0xff660000 0x0 0x400>; + interrupts = ; + interrupt-names = "vdpu"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, + <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + iommus = <&vdec_mmu>; + power-domains = <&power RK3399_PD_VDU>; + }; + vdec_mmu: iommu@ff660480 { compatible = "rockchip,iommu"; reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; @@ -1276,8 +1288,8 @@ interrupt-names = "vdec_mmu"; clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VDU>; #iommu-cells = <0>; - status = "disabled"; }; iep_mmu: iommu@ff670800 { diff --git a/src/arm64/socionext/uniphier-ld11-global.dts b/src/arm64/socionext/uniphier-ld11-global.dts index f72f048a0c9d..816ac25fa1eb 100644 --- a/src/arm64/socionext/uniphier-ld11-global.dts +++ b/src/arm64/socionext/uniphier-ld11-global.dts @@ -30,6 +30,7 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + ethernet0 = ð }; memory@80000000 { diff --git a/src/arm64/socionext/uniphier-ld11-ref.dts b/src/arm64/socionext/uniphier-ld11-ref.dts index b8f627348448..693171f82ff1 100644 --- a/src/arm64/socionext/uniphier-ld11-ref.dts +++ b/src/arm64/socionext/uniphier-ld11-ref.dts @@ -29,6 +29,7 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + ethernet0 = ð }; memory@80000000 { diff --git a/src/arm64/socionext/uniphier-ld11.dtsi b/src/arm64/socionext/uniphier-ld11.dtsi index 2ca2d3dc8d6c..15dcfc259854 100644 --- a/src/arm64/socionext/uniphier-ld11.dtsi +++ b/src/arm64/socionext/uniphier-ld11.dtsi @@ -129,6 +129,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -140,6 +142,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; @@ -566,6 +570,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-ld11-aidet"; reg = <0x5fc20000 0x200>; diff --git a/src/arm64/socionext/uniphier-ld20-akebi96.dts b/src/arm64/socionext/uniphier-ld20-akebi96.dts new file mode 100644 index 000000000000..816919b42d2e --- /dev/null +++ b/src/arm64/socionext/uniphier-ld20-akebi96.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Device Tree Source for Akebi96 Development Board +// +// Derived from uniphier-ld20-global.dts. +// +// Copyright (C) 2015-2017 Socionext Inc. +// Copyright (C) 2019-2020 Linaro Ltd. + +/dts-v1/; +#include +#include "uniphier-ld20.dtsi" + +/ { + model = "Akebi96"; + compatible = "socionext,uniphier-ld20-akebi96", + "socionext,uniphier-ld20"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + ethernet0 = ð + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0xc0000000>; + }; + + framebuffer@c0000000 { + compatible = "simple-framebuffer"; + reg = <0 0xc0000000 0 0x02000000>; + width = <1920>; + height = <1080>; + stride = <7680>; + format = "a8r8g8b8"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + memory@c0000000 { + reg = <0 0xc0000000 0 0x02000000>; + no-map; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "UniPhier LD20"; + dais = <&spdif_port0 + &comp_spdif_port0>; + }; + + spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port@0 { + spdif_tx: endpoint { + remote-endpoint = <&spdif_hiecout1>; + }; + }; + }; + + comp-spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port@0 { + comp_spdif_tx: endpoint { + remote-endpoint = <&comp_spdif_hiecout1>; + }; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&spi3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + usb-over-spi@0 { + compatible = "maxim,max3421-udc"; + reg = <0>; + spi-max-frequency = <12500000>; + interrupt-parent = <&gpio>; + interrupt-names = "udc"; + interrupts = <0 2>; + }; +}; + +&serial0 { + /* Onboard USB-UART */ + status = "okay"; +}; + +&serial2 { + /* LS connector UART1 */ + status = "okay"; +}; + +&serial3 { + /* LS connector UART0 */ + status = "okay"; +}; + +&spdif_hiecout1 { + remote-endpoint = <&spdif_tx>; +}; + +&comp_spdif_hiecout1 { + remote-endpoint = <&comp_spdif_tx>; +}; + +&i2c0 { + /* LS connector I2C0 */ + status = "okay"; +}; + +&i2c1 { + /* LS connector I2C1 */ + status = "okay"; +}; + +ð { + status = "okay"; + phy-handle = <ðphy>; +}; + +&mdio { + ethphy: ethphy@0 { + reg = <0>; + }; +}; + +&usb { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&gpio { + /* IRQs for Max3421 */ + xirq0 { + gpio-hog; + gpios = ; + input; + }; + xirq10 { + gpio-hog; + gpios = ; + input; + }; +}; + +&pinctrl_aout1 { + groups = "aout1b"; +}; + +&pinctrl_uart3 { + groups = "uart3", "uart3_ctsrts"; +}; diff --git a/src/arm64/socionext/uniphier-ld20-global.dts b/src/arm64/socionext/uniphier-ld20-global.dts index 9ca692ed1b2b..2c000082667c 100644 --- a/src/arm64/socionext/uniphier-ld20-global.dts +++ b/src/arm64/socionext/uniphier-ld20-global.dts @@ -30,6 +30,7 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + ethernet0 = ð }; memory@80000000 { diff --git a/src/arm64/socionext/uniphier-ld20-ref.dts b/src/arm64/socionext/uniphier-ld20-ref.dts index 406244a5c8e8..eeb976e7892d 100644 --- a/src/arm64/socionext/uniphier-ld20-ref.dts +++ b/src/arm64/socionext/uniphier-ld20-ref.dts @@ -29,6 +29,7 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + ethernet0 = ð }; memory@80000000 { diff --git a/src/arm64/socionext/uniphier-ld20.dtsi b/src/arm64/socionext/uniphier-ld20.dtsi index a93148c2088f..f4a56b208837 100644 --- a/src/arm64/socionext/uniphier-ld20.dtsi +++ b/src/arm64/socionext/uniphier-ld20.dtsi @@ -234,6 +234,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -245,6 +247,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; @@ -256,6 +260,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006200 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 229 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; @@ -267,6 +273,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006300 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 230 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi3>; @@ -664,6 +672,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-ld20-aidet"; reg = <0x5fc20000 0x200>; diff --git a/src/arm64/socionext/uniphier-pxs3-ref.dts b/src/arm64/socionext/uniphier-pxs3-ref.dts index 4d00ff9548e1..7c30c6b56b57 100644 --- a/src/arm64/socionext/uniphier-pxs3-ref.dts +++ b/src/arm64/socionext/uniphier-pxs3-ref.dts @@ -29,6 +29,8 @@ i2c6 = &i2c6; spi0 = &spi0; spi1 = &spi1; + ethernet0 = ð0; + ethernet1 = ð1; }; memory@80000000 { @@ -130,3 +132,19 @@ reg = <0>; }; }; + +&pinctrl_ether_rgmii { + tx { + pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1", + "RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL"; + drive-strength = <9>; + }; +}; + +&pinctrl_ether1_rgmii { + tx { + pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1", + "RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL"; + drive-strength = <9>; + }; +}; diff --git a/src/arm64/socionext/uniphier-pxs3.dtsi b/src/arm64/socionext/uniphier-pxs3.dtsi index 616835b38106..72f16881cf53 100644 --- a/src/arm64/socionext/uniphier-pxs3.dtsi +++ b/src/arm64/socionext/uniphier-pxs3.dtsi @@ -193,6 +193,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006000 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 39 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; @@ -204,6 +206,8 @@ compatible = "socionext,uniphier-scssi"; status = "disabled"; reg = <0x54006100 0x100>; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 216 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; @@ -498,6 +502,14 @@ }; }; + xdmac: dma-controller@5fc10000 { + compatible = "socionext,uniphier-xdmac"; + reg = <0x5fc10000 0x5300>; + interrupts = <0 188 4>; + dma-channels = <16>; + #dma-cells = <2>; + }; + aidet: interrupt-controller@5fc20000 { compatible = "socionext,uniphier-pxs3-aidet"; reg = <0x5fc20000 0x200>; diff --git a/src/arm64/sprd/sc9863a.dtsi b/src/arm64/sprd/sc9863a.dtsi index 2c590ca1d079..8cf4a6575980 100644 --- a/src/arm64/sprd/sc9863a.dtsi +++ b/src/arm64/sprd/sc9863a.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2019, Unisoc Inc. */ +#include #include #include "sharkl3.dtsi" @@ -159,6 +160,30 @@ interrupts = ; }; + ap_clk: clock-controller@21500000 { + compatible = "sprd,sc9863a-ap-clk"; + reg = <0 0x21500000 0 0x1000>; + clocks = <&ext_32k>, <&ext_26m>; + clock-names = "ext-32k", "ext-26m"; + #clock-cells = <1>; + }; + + aon_clk: clock-controller@402d0000 { + compatible = "sprd,sc9863a-aon-clk"; + reg = <0 0x402d0000 0 0x1000>; + clocks = <&ext_26m>, <&rco_100m>, + <&ext_32k>, <&ext_4m>; + clock-names = "ext-26m", "rco-100m", + "ext-32k", "ext-4m"; + #clock-cells = <1>; + }; + + mm_clk: clock-controller@60900000 { + compatible = "sprd,sc9863a-mm-clk"; + reg = <0 0x60900000 0 0x1000>; + #clock-cells = <1>; + }; + funnel@10001000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x10001000 0 0x1000>; @@ -519,5 +544,46 @@ }; }; }; + + ap-ahb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sdio0: sdio@20300000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20300000 0 0x1000>; + interrupts = ; + + clock-names = "sdio", "enable"; + clocks = <&aon_clk CLK_SDIO0_2X>, + <&apahb_gate CLK_SDIO0_EB>; + assigned-clocks = <&aon_clk CLK_SDIO0_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <4>; + no-sdio; + no-mmc; + }; + + sdio3: sdio@20600000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20600000 0 0x1000>; + interrupts = ; + + clock-names = "sdio", "enable"; + clocks = <&aon_clk CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>; + assigned-clocks = <&aon_clk CLK_EMMC_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + cap-mmc-hw-reset; + }; + }; }; }; diff --git a/src/arm64/sprd/sharkl3.dtsi b/src/arm64/sprd/sharkl3.dtsi index 0222128b10f7..206a4afdab1c 100644 --- a/src/arm64/sprd/sharkl3.dtsi +++ b/src/arm64/sprd/sharkl3.dtsi @@ -16,6 +16,149 @@ #size-cells = <2>; ranges; + ap_ahb_regs: syscon@20e00000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x20e00000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20e00000 0x4000>; + + apahb_gate: apahb-gate { + compatible = "sprd,sc9863a-apahb-gate"; + reg = <0x0 0x1020>; + #clock-cells = <1>; + }; + }; + + pmu_regs: syscon@402b0000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x402b0000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x402b0000 0x4000>; + + pmu_gate: pmu-gate { + compatible = "sprd,sc9863a-pmu-gate"; + reg = <0 0x1200>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + aon_apb_regs: syscon@402e0000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x402e0000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x402e0000 0x4000>; + + aonapb_gate: aonapb-gate { + compatible = "sprd,sc9863a-aonapb-gate"; + reg = <0 0x1100>; + #clock-cells = <1>; + }; + }; + + anlg_phy_g2_regs: syscon@40353000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x40353000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40353000 0x3000>; + + pll: pll { + compatible = "sprd,sc9863a-pll"; + reg = <0 0x100>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + anlg_phy_g4_regs: syscon@40359000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x40359000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40359000 0x3000>; + + mpll: mpll { + compatible = "sprd,sc9863a-mpll"; + reg = <0 0x100>; + #clock-cells = <1>; + }; + }; + + anlg_phy_g5_regs: syscon@4035c000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x4035c000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x4035c000 0x3000>; + + rpll: rpll { + compatible = "sprd,sc9863a-rpll"; + reg = <0 0x100>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + anlg_phy_g7_regs: syscon@40363000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x40363000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40363000 0x3000>; + + dpll: dpll { + compatible = "sprd,sc9863a-dpll"; + reg = <0 0x100>; + #clock-cells = <1>; + }; + }; + + mm_ahb_regs: syscon@60800000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x60800000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x60800000 0x3000>; + + mm_gate: mm-gate { + compatible = "sprd,sc9863a-mm-gate"; + reg = <0 0x1100>; + #clock-cells = <1>; + }; + }; + + ap_apb_regs: syscon@71300000 { + compatible = "sprd,sc9863a-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x71300000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x71300000 0x4000>; + + apapb_gate: apapb-gate { + compatible = "sprd,sc9863a-apapb-gate"; + reg = <0 0x1000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + apb@70000000 { compatible = "simple-bus"; #address-cells = <1>; @@ -75,4 +218,25 @@ clock-frequency = <26000000>; clock-output-names = "ext-26m"; }; + + ext_32k: ext-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ext-32k"; + }; + + ext_4m: ext-4m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <4000000>; + clock-output-names = "ext-4m"; + }; + + rco_100m: rco-100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "rco-100m"; + }; }; diff --git a/src/arm64/ti/k3-am65-main.dtsi b/src/arm64/ti/k3-am65-main.dtsi index 11887c72f23a..61815228e230 100644 --- a/src/arm64/ti/k3-am65-main.dtsi +++ b/src/arm64/ti/k3-am65-main.dtsi @@ -287,6 +287,17 @@ mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ <0x4090 0x3>; /* SERDES1 lane select */ }; + + dss_oldi_io_ctrl: dss_oldi_io_ctrl@41E0 { + compatible = "syscon"; + reg = <0x0000041E0 0x14>; + }; + + ehrpwm_tbclk: syscon@4140 { + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + }; }; dwc3_0: dwc3@4000000 { @@ -570,6 +581,28 @@ <0x5>; /* RX_CHAN */ ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */ }; + + cpts@310d0000 { + compatible = "ti,am65-cpts"; + reg = <0x0 0x310d0000 0x0 0x400>; + reg-names = "cpts"; + clocks = <&main_cpts_mux>; + clock-names = "cpts"; + interrupts-extended = <&intr_main_navss 163 0>; + interrupt-names = "cpts"; + ti,cpts-periodic-outputs = <6>; + ti,cpts-ext-ts-inputs = <8>; + + main_cpts_mux: refclk-mux { + #clock-cells = <0>; + clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, + <&k3_clks 118 6>, <&k3_clks 118 3>, + <&k3_clks 118 8>, <&k3_clks 118 14>, + <&k3_clks 120 3>, <&k3_clks 121 3>; + assigned-clocks = <&main_cpts_mux>; + assigned-clock-parents = <&k3_clks 118 5>; + }; + }; }; main_gpio0: main_gpio0@600000 { @@ -746,4 +779,97 @@ }; }; }; + + dss: dss@04a00000 { + compatible = "ti,am65x-dss"; + reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ + <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ + <0x0 0x04a06000 0x0 0x1000>, /* vid */ + <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ + <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ + <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ + <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2"; + + ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; + + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + + clocks = <&k3_clks 67 1>, + <&k3_clks 216 1>, + <&k3_clks 67 2>; + clock-names = "fck", "vp1", "vp2"; + + /* + * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via + * DIV1. See "Figure 12-3365. DSS Integration" + * in AM65x TRM for details. + */ + assigned-clocks = <&k3_clks 67 2>; + assigned-clock-parents = <&k3_clks 67 5>; + + interrupts = ; + + status = "disabled"; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + ehrpwm0: pwm@3000000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x3000000 0x0 0x100>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; + clock-names = "tbclk", "fck"; + }; + + ehrpwm1: pwm@3010000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x3010000 0x0 0x100>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; + clock-names = "tbclk", "fck"; + }; + + ehrpwm2: pwm@3020000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x3020000 0x0 0x100>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; + clock-names = "tbclk", "fck"; + }; + + ehrpwm3: pwm@3030000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x3030000 0x0 0x100>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; + clock-names = "tbclk", "fck"; + }; + + ehrpwm4: pwm@3040000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x3040000 0x0 0x100>; + power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; + clock-names = "tbclk", "fck"; + }; + + ehrpwm5: pwm@3050000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x3050000 0x0 0x100>; + power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; + clock-names = "tbclk", "fck"; + }; }; diff --git a/src/arm64/ti/k3-am65-mcu.dtsi b/src/arm64/ti/k3-am65-mcu.dtsi index 353d1e2532a7..ae5f813d0cac 100644 --- a/src/arm64/ti/k3-am65-mcu.dtsi +++ b/src/arm64/ti/k3-am65-mcu.dtsi @@ -247,5 +247,26 @@ clock-names = "fck"; bus_freq = <1000000>; }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&mcu_cpsw_cpts_mux>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + + mcu_cpsw_cpts_mux: refclk-mux { + #clock-cells = <0>; + clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, + <&k3_clks 118 6>, <&k3_clks 118 3>, + <&k3_clks 118 8>, <&k3_clks 118 14>, + <&k3_clks 120 3>, <&k3_clks 121 3>; + assigned-clocks = <&mcu_cpsw_cpts_mux>; + assigned-clock-parents = <&k3_clks 118 5>; + }; + }; }; }; diff --git a/src/arm64/ti/k3-am65-wakeup.dtsi b/src/arm64/ti/k3-am65-wakeup.dtsi index f4227e2743f2..54a133fa1bf2 100644 --- a/src/arm64/ti/k3-am65-wakeup.dtsi +++ b/src/arm64/ti/k3-am65-wakeup.dtsi @@ -89,4 +89,15 @@ clocks = <&k3_clks 59 0>; clock-names = "gpio"; }; + + wkup_vtm0: thermal@42050000 { + compatible = "ti,am654-vtm"; + reg = <0x42050000 0x25c>; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; + + thermal_zones: thermal-zones { + #include "k3-am654-industrial-thermal.dtsi" + }; }; diff --git a/src/arm64/ti/k3-am654-industrial-thermal.dtsi b/src/arm64/ti/k3-am654-industrial-thermal.dtsi new file mode 100644 index 000000000000..cdc3d40c3f60 --- /dev/null +++ b/src/arm64/ti/k3-am654-industrial-thermal.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +mpu0_thermal: mpu0_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + mpu0_crit: mpu0_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +mpu1_thermal: mpu1_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + mpu1_crit: mpu1_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +mcu_thermal: mcu_thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + mcu_crit: mcu_crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff --git a/src/arm64/ti/k3-j721e-common-proc-board.dts b/src/arm64/ti/k3-j721e-common-proc-board.dts index 98e5e17e3ff7..6df823aaa37c 100644 --- a/src/arm64/ti/k3-j721e-common-proc-board.dts +++ b/src/arm64/ti/k3-j721e-common-proc-board.dts @@ -472,3 +472,23 @@ phy-mode = "rgmii-rxid"; phy-handle = <&phy0>; }; + +&dss { + /* + * These clock assignments are chosen to enable the following outputs: + * + * VP0 - DisplayPort SST + * VP1 - DPI0 + * VP2 - DSI + * VP3 - DPI1 + */ + + assigned-clocks = <&k3_clks 152 1>, + <&k3_clks 152 4>, + <&k3_clks 152 9>, + <&k3_clks 152 13>; + assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */ + <&k3_clks 152 6>, /* PLL19_HSDIV0 */ + <&k3_clks 152 11>, /* PLL18_HSDIV0 */ + <&k3_clks 152 18>; /* PLL23_HSDIV0 */ +}; diff --git a/src/arm64/ti/k3-j721e-main.dtsi b/src/arm64/ti/k3-j721e-main.dtsi index 0b9d14b838a1..96c929da639d 100644 --- a/src/arm64/ti/k3-j721e-main.dtsi +++ b/src/arm64/ti/k3-j721e-main.dtsi @@ -254,6 +254,18 @@ <0x0c>; /* RX_UHCHAN */ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ }; + + cpts@310d0000 { + compatible = "ti,j721e-cpts"; + reg = <0x0 0x310d0000 0x0 0x400>; + reg-names = "cpts"; + clocks = <&k3_clks 201 1>; + clock-names = "cpts"; + interrupts-extended = <&main_navss_intr 201 0>; + interrupt-names = "cpts"; + ti,cpts-periodic-outputs = <6>; + ti,cpts-ext-ts-inputs = <8>; + }; }; main_pmx0: pinmux@11c000 { @@ -736,6 +748,63 @@ }; }; + dss: dss@04a00000 { + compatible = "ti,j721e-dss"; + reg = + <0x00 0x04a00000 0x00 0x10000>, /* common_m */ + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ + + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ + + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ + + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ + <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ + <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ + <0x00 0x04af0000 0x00 0x10000>; /* wb */ + + reg-names = "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + + clocks = <&k3_clks 152 0>, + <&k3_clks 152 1>, + <&k3_clks 152 4>, + <&k3_clks 152 9>, + <&k3_clks 152 13>; + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; + + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + + interrupts = , + , + , + ; + interrupt-names = "common_m", + "common_s0", + "common_s1", + "common_s2"; + + status = "disabled"; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + mcasp0: mcasp@2b00000 { compatible = "ti,am33xx-mcasp-audio"; reg = <0x0 0x02b00000 0x0 0x2000>, @@ -963,4 +1032,22 @@ status = "disabled"; }; + + watchdog0: watchdog@2200000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x0 0x2200000 0x0 0x100>; + clocks = <&k3_clks 252 1>; + power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 252 1>; + assigned-clock-parents = <&k3_clks 252 5>; + }; + + watchdog1: watchdog@2210000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x0 0x2210000 0x0 0x100>; + clocks = <&k3_clks 253 1>; + power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 253 1>; + assigned-clock-parents = <&k3_clks 253 5>; + }; }; diff --git a/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi b/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi index 3d6064125b40..dc31bd0434cb 100644 --- a/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi +++ b/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi @@ -338,5 +338,16 @@ clock-names = "fck"; bus_freq = <1000000>; }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&k3_clks 18 2>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; }; }; diff --git a/src/arm64/xilinx/zynqmp.dtsi b/src/arm64/xilinx/zynqmp.dtsi index 26d926eb1431..9174ddc76bdc 100644 --- a/src/arm64/xilinx/zynqmp.dtsi +++ b/src/arm64/xilinx/zynqmp.dtsi @@ -158,6 +158,10 @@ zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; }; + + xlnx_aes: zynqmp-aes { + compatible = "xlnx,zynqmp-aes"; + }; }; }; @@ -185,7 +189,7 @@ ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, diff --git a/src/mips/ingenic/ci20.dts b/src/mips/ingenic/ci20.dts index db0ca250bd1a..75f5bfbf2c37 100644 --- a/src/mips/ingenic/ci20.dts +++ b/src/mips/ingenic/ci20.dts @@ -386,6 +386,9 @@ interrupt-parent = <&gpe>; interrupts = <19 4>; + + nvmem-cells = <ð0_addr>; + nvmem-cell-names = "mac-address"; }; }; diff --git a/src/mips/ingenic/gcw0.dts b/src/mips/ingenic/gcw0.dts index f58d239c2058..bc72304a2440 100644 --- a/src/mips/ingenic/gcw0.dts +++ b/src/mips/ingenic/gcw0.dts @@ -4,6 +4,10 @@ #include "jz4770.dtsi" #include +#include +#include +#include + / { compatible = "gcw,zero", "ingenic,jz4770"; model = "GCW Zero"; @@ -15,20 +19,370 @@ serial3 = &uart3; }; + memory: memory { + device_type = "memory"; + reg = <0x0 0x10000000>, + <0x30000000 0x10000000>; + }; + chosen { stdout-path = "serial2:57600n8"; }; - board { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; + vcc: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vcc"; - otg_phy: otg-phy { - compatible = "usb-nop-xceiv"; - clocks = <&cgu JZ4770_CLK_OTG_PHY>; - clock-names = "main_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + mmc1_power: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "mmc1_vcc"; + gpio = <&gpe 9 0>; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc>; + }; + + headphones_amp: analog-amplifier@0 { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpf 3 GPIO_ACTIVE_LOW>; + enable-delay-ms = <50>; + + VCC-supply = <&ldo5>; + sound-name-prefix = "Headphones Amp"; + }; + + speaker_amp: analog-amplifier@1 { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpf 20 GPIO_ACTIVE_HIGH>; + + VCC-supply = <&ldo5>; + sound-name-prefix = "Speaker Amp"; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,name = "gcw0-audio"; + simple-audio-card,format = "i2s"; + + simple-audio-card,widgets = + "Speaker", "Speaker", + "Headphone", "Headphones", + "Line", "FM Radio", + "Microphone", "Built-in Mic"; + simple-audio-card,routing = + "Headphones Amp INL", "LHPOUT", + "Headphones Amp INR", "RHPOUT", + "Headphones", "Headphones Amp OUTL", + "Headphones", "Headphones Amp OUTR", + "Speaker Amp INL", "LOUT", + "Speaker Amp INR", "ROUT", + "Speaker", "Speaker Amp OUTL", + "Speaker", "Speaker Amp OUTR", + "LLINEIN", "FM Radio", + "RLINEIN", "FM Radio", + "Built-in Mic", "MICBIAS", + "MIC1P", "Built-in Mic", + "MIC1N", "Built-in Mic"; + simple-audio-card,pin-switches = "Speaker", "Headphones"; + + simple-audio-card,hp-det-gpio = <&gpf 21 GPIO_ACTIVE_LOW>; + simple-audio-card,aux-devs = <&speaker_amp>, <&headphones_amp>; + + simple-audio-card,bitclock-master = <&dai_codec>; + simple-audio-card,frame-master = <&dai_codec>; + + dai_cpu: simple-audio-card,cpu { + sound-dai = <&aic>; + }; + + dai_codec: simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + + rumble { + compatible = "pwm-vibrator"; + pwms = <&pwm 4 2000000 0>; + pwm-names = "enable"; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_pwm4>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 1 40000 0>; + power-supply = <&vcc>; + + brightness-levels = <0 16 32 48 64 80 96 112 128 + 144 160 176 192 208 224 240 255>; + default-brightness-level = <12>; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_pwm1>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + autorepeat; + + button@0 { + label = "D-pad up"; + linux,code = ; + linux,can-disable; + gpios = <&gpe 21 GPIO_ACTIVE_LOW>; + }; + + button@1 { + label = "D-pad down"; + linux,code = ; + linux,can-disable; + gpios = <&gpe 25 GPIO_ACTIVE_LOW>; + }; + + button@2 { + label = "D-pad left"; + linux,code = ; + linux,can-disable; + gpios = <&gpe 23 GPIO_ACTIVE_LOW>; + }; + + button@3 { + label = "D-pad right"; + linux,code = ; + linux,can-disable; + gpios = <&gpe 24 GPIO_ACTIVE_LOW>; + }; + + button@4 { + label = "Button A"; + linux,code = ; + linux,can-disable; + gpios = <&gpe 29 GPIO_ACTIVE_LOW>; + }; + + button@5 { + label = "Button B"; + linux,code = ; + linux,can-disable; + gpios = <&gpe 20 GPIO_ACTIVE_LOW>; + }; + + button@6 { + label = "Button Y"; + linux,code = ; + linux,can-disable; + gpios = <&gpe 27 GPIO_ACTIVE_LOW>; + }; + + button@7 { + label = "Button X"; + linux,code = ; + linux,can-disable; + gpios = <&gpe 28 GPIO_ACTIVE_LOW>; + }; + + button@8 { + label = "Left shoulder button"; + linux,code = ; + linux,can-disable; + gpios = <&gpb 20 GPIO_ACTIVE_LOW>; + }; + + button@9 { + label = "Right shoulder button"; + linux,code = ; + linux,can-disable; + gpios = <&gpe 26 GPIO_ACTIVE_LOW>; + }; + + button@10 { + label = "Start button"; + linux,code = ; + linux,can-disable; + gpios = <&gpb 21 GPIO_ACTIVE_LOW>; + }; + + button@11 { + label = "Select button"; + linux,code = ; + linux,can-disable; + /* + * This is the only button that is active high, + * since it doubles as BOOT_SEL1. + */ + gpios = <&gpd 18 GPIO_ACTIVE_HIGH>; + }; + + button@12 { + label = "Power slider"; + linux,code = ; + linux,can-disable; + gpios = <&gpa 30 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button@13 { + label = "Power hold"; + linux,code = ; + linux,can-disable; + gpios = <&gpf 11 GPIO_ACTIVE_LOW>; + }; + }; + + i2c3: i2c-controller@3 { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sda-gpios = <&gpd 5 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpd 4 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <2>; /* 250 kHz */ + + act8600: pmic@5a { + compatible = "active-semi,act8600"; + reg = <0x5a>; + + regulators { + /* USB OTG */ + otg_vbus: SUDCDC_REG4 { + /* + * 5.3V instead of 5.0V to compensate + * for the voltage drop of a diode + * between the regulator and the + * connector. + */ + regulator-min-microvolt = <5300000>; + regulator-max-microvolt = <5300000>; + inl-supply = <&vcc>; + }; + + /* + * When this is off, there is no sound, but also + * no USB networking. + */ + ldo5: LDO5 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + inl-supply = <&vcc>; + }; + + /* LCD panel and FM radio */ + ldo6: LDO6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + inl-supply = <&vcc>; + }; + + /* ??? */ + LDO7 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /*regulator-always-on;*/ + inl-supply = <&vcc>; + }; + + /* + * The colors on the LCD are wrong when this is + * off. Which is strange, since the LCD panel + * data sheet only mentions a 3.3V input. + */ + LDO8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + inl-supply = <&vcc>; + }; + + /* RTC fixed 3.3V */ + LDO_REG9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + inl-supply = <&vcc>; + }; + + /* Unused fixed 1.2V */ + LDO_REG10 { + inl-supply = <&vcc>; + }; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led { + gpios = <&gpb 30 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpe 15 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpe 17 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpe 16 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + nt39016@0 { + compatible = "kingdisplay,kd035g6-54nt"; + reg = <0>; + + spi-max-frequency = <3125000>; + spi-3wire; + spi-cs-high; + + reset-gpios = <&gpe 2 GPIO_ACTIVE_LOW>; + + backlight = <&backlight>; + power-supply = <&ldo6>; + + port { + panel_input: endpoint { + remote-endpoint = <&panel_output>; + }; + }; + }; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + label = "mini-USB"; + type = "mini"; + + /* + * USB OTG is not yet working reliably, the ID detection + * mechanism tends to fry easily for unknown reasons. + * Until this is fixed, disable OTG by not providing the + * ID GPIO to the driver. + */ + //id-gpios = <&gpf 18 GPIO_ACTIVE_LOW>; + + vbus-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; + vbus-supply = <&otg_vbus>; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_otg>; + + port { + usb_ep: endpoint { + remote-endpoint = <&usb_otg_ep>; + }; }; }; }; @@ -37,24 +391,86 @@ clock-frequency = <12000000>; }; +&pinctrl { + pins_lcd: lcd { + function = "lcd"; + groups = "lcd-24bit"; + }; + + pins_uart2: uart2 { + function = "uart2"; + groups = "uart2-data"; + }; + + pins_mmc0: mmc0 { + function = "mmc0"; + groups = "mmc0-1bit-a", "mmc0-4bit-a"; + }; + + pins_mmc1: mmc1 { + function = "mmc1"; + groups = "mmc1-1bit-d", "mmc1-4bit-d"; + }; + + pins_otg: otg { + otg-vbus-pin { + function = "otg"; + groups = "otg-vbus"; + }; + + vbus-pin { + pins = "PB5"; + bias-disable; + }; + }; + + pins_pwm1: pwm1 { + function = "pwm1"; + groups = "pwm1"; + }; + + pins_pwm4: pwm4 { + function = "pwm4"; + groups = "pwm4"; + }; +}; + &uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pins_uart2>; + status = "okay"; }; &cgu { - /* Put high-speed peripherals under PLL1, such that we can change the + /* + * Put high-speed peripherals under PLL1, such that we can change the * PLL0 frequency on demand without having to suspend peripherals. * We use a rate of 432 MHz, which is the least common multiple of * 27 MHz (required by TV encoder) and 48 MHz (required by USB host). + * Put the GPU under PLL0 since we want a higher frequency. + * Use the 32 kHz oscillator as the parent of the RTC for a higher + * precision. */ assigned-clocks = <&cgu JZ4770_CLK_PLL1>, - <&cgu JZ4770_CLK_UHC>; + <&cgu JZ4770_CLK_GPU>, + <&cgu JZ4770_CLK_RTC>, + <&cgu JZ4770_CLK_UHC>, + <&cgu JZ4770_CLK_LPCLK_MUX>, + <&cgu JZ4770_CLK_MMC0_MUX>, + <&cgu JZ4770_CLK_MMC1_MUX>; assigned-clock-parents = <0>, + <&cgu JZ4770_CLK_PLL0>, + <&cgu JZ4770_CLK_OSC32K>, + <&cgu JZ4770_CLK_PLL1>, + <&cgu JZ4770_CLK_PLL1>, + <&cgu JZ4770_CLK_PLL1>, <&cgu JZ4770_CLK_PLL1>; assigned-clock-rates = - <432000000>; + <432000000>, + <600000000>; }; &uhc { @@ -63,10 +479,69 @@ }; &tcu { - /* 750 kHz for the system timer and clocksource */ - assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>; - assigned-clock-rates = <750000>, <750000>; + /* + * 750 kHz for the system timer and clocksource, 12 MHz for the OST, + * and use RTC as the parent for the watchdog clock + */ + assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>, + <&tcu TCU_CLK_OST>, <&tcu TCU_CLK_WDT>; + assigned-clock-parents = <0>, <0>, <0>, <&cgu JZ4770_CLK_RTC>; + assigned-clock-rates = <750000>, <750000>, <12000000>; - /* PWM1 is in use, so reserve channel #2 for the clocksource */ + /* PWM1 is in use, so use channel #2 for the clocksource */ ingenic,pwm-channels-mask = <0xfa>; }; + +&usb_otg { + port { + usb_otg_ep: endpoint { + remote-endpoint = <&usb_ep>; + }; + }; +}; + +&otg_phy { + vcc-supply = <&ldo5>; +}; + +&rtc { + clocks = <&cgu JZ4770_CLK_RTC>; + clock-names = "rtc"; + + system-power-controller; +}; + +&mmc0 { + status = "okay"; + + bus-width = <4>; + max-frequency = <48000000>; + vmmc-supply = <&vcc>; + non-removable; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_mmc0>; +}; + +&mmc1 { + status = "okay"; + + bus-width = <4>; + max-frequency = <48000000>; + cd-gpios = <&gpb 2 GPIO_ACTIVE_LOW>; + vmmc-supply = <&mmc1_power>; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_mmc1>; +}; + +&lcd { + pinctrl-names = "default"; + pinctrl-0 = <&pins_lcd>; + + port { + panel_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; +}; diff --git a/src/mips/ingenic/gcw0_proto.dts b/src/mips/ingenic/gcw0_proto.dts new file mode 100644 index 000000000000..02df22f8ae0f --- /dev/null +++ b/src/mips/ingenic/gcw0_proto.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "gcw0.dts" + +/ { + model = "GCW Zero Prototype"; +}; + +&memory { + /* Prototype has only 256 MiB of RAM */ + reg = <0x0 0x10000000>; +}; diff --git a/src/mips/ingenic/jz4740.dtsi b/src/mips/ingenic/jz4740.dtsi index a3301bab9231..1520585c235c 100644 --- a/src/mips/ingenic/jz4740.dtsi +++ b/src/mips/ingenic/jz4740.dtsi @@ -55,10 +55,10 @@ #clock-cells = <1>; - clocks = <&cgu JZ4740_CLK_RTC - &cgu JZ4740_CLK_EXT - &cgu JZ4740_CLK_PCLK - &cgu JZ4740_CLK_TCU>; + clocks = <&cgu JZ4740_CLK_RTC>, + <&cgu JZ4740_CLK_EXT>, + <&cgu JZ4740_CLK_PCLK>, + <&cgu JZ4740_CLK_TCU>; clock-names = "rtc", "ext", "pclk", "tcu"; interrupt-controller; @@ -74,6 +74,20 @@ clocks = <&tcu TCU_CLK_WDT>; clock-names = "wdt"; }; + + pwm: pwm@40 { + compatible = "ingenic,jz4740-pwm"; + reg = <0x40 0x80>; + + #pwm-cells = <3>; + + clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, + <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>, + <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>; + clock-names = "timer0", "timer1", "timer2", "timer3", + "timer4", "timer5", "timer6", "timer7"; + }; }; rtc_dev: rtc@10003000 { @@ -241,10 +255,10 @@ reg = <0x13010000 0x54>; #address-cells = <2>; #size-cells = <1>; - ranges = <1 0 0x18000000 0x4000000 - 2 0 0x14000000 0x4000000 - 3 0 0x0c000000 0x4000000 - 4 0 0x08000000 0x4000000>; + ranges = <1 0 0x18000000 0x4000000>, + <2 0 0x14000000 0x4000000>, + <3 0 0x0c000000 0x4000000>, + <4 0 0x08000000 0x4000000>; clocks = <&cgu JZ4740_CLK_MCLK>; }; @@ -258,8 +272,7 @@ dmac: dma-controller@13020000 { compatible = "ingenic,jz4740-dma"; - reg = <0x13020000 0xbc - 0x13020300 0x14>; + reg = <0x13020000 0xbc>, <0x13020300 0x14>; #dma-cells = <2>; interrupt-parent = <&intc>; diff --git a/src/mips/ingenic/jz4770.dtsi b/src/mips/ingenic/jz4770.dtsi index 0bfb9edff3d0..fa11ac950499 100644 --- a/src/mips/ingenic/jz4770.dtsi +++ b/src/mips/ingenic/jz4770.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include / { #address-cells = <1>; @@ -37,13 +38,25 @@ }; cgu: jz4770-cgu@10000000 { - compatible = "ingenic,jz4770-cgu"; + compatible = "ingenic,jz4770-cgu", "simple-mfd"; reg = <0x10000000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10000000 0x100>; clocks = <&ext>, <&osc32k>; clock-names = "ext", "osc32k"; #clock-cells = <1>; + + otg_phy: usb-phy@3c { + compatible = "ingenic,jz4770-phy"; + reg = <0x3c 0x10>; + + clocks = <&cgu JZ4770_CLK_OTG_PHY>; + + #phy-cells = <0>; + }; }; tcu: timer@10002000 { @@ -55,9 +68,9 @@ #clock-cells = <1>; - clocks = <&cgu JZ4770_CLK_RTC - &cgu JZ4770_CLK_EXT - &cgu JZ4770_CLK_PCLK>; + clocks = <&cgu JZ4770_CLK_RTC>, + <&cgu JZ4770_CLK_EXT>, + <&cgu JZ4770_CLK_PCLK>; clock-names = "rtc", "ext", "pclk"; interrupt-controller; @@ -65,6 +78,47 @@ interrupt-parent = <&intc>; interrupts = <27 26 25>; + + watchdog: watchdog@0 { + compatible = "ingenic,jz4770-watchdog", + "ingenic,jz4740-watchdog"; + reg = <0x0 0xc>; + + clocks = <&tcu TCU_CLK_WDT>; + clock-names = "wdt"; + }; + + pwm: pwm@40 { + compatible = "ingenic,jz4770-pwm", "ingenic,jz4740-pwm"; + reg = <0x40 0x80>; + + #pwm-cells = <3>; + + clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, + <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>, + <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>; + clock-names = "timer0", "timer1", "timer2", "timer3", + "timer4", "timer5", "timer6", "timer7"; + }; + + ost: timer@e0 { + compatible = "ingenic,jz4770-ost"; + reg = <0xe0 0x20>; + + clocks = <&tcu TCU_CLK_OST>; + clock-names = "ost"; + + interrupts = <15>; + }; + }; + + rtc: rtc@10003000 { + compatible = "ingenic,jz4770-rtc", "ingenic,jz4760-rtc"; + reg = <0x10003000 0x40>; + + interrupt-parent = <&intc>; + interrupts = <32>; }; pinctrl: pin-controller@10010000 { @@ -165,6 +219,93 @@ }; }; + aic: audio-controller@10020000 { + compatible = "ingenic,jz4770-i2s"; + reg = <0x10020000 0x94>; + + #sound-dai-cells = <0>; + + clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>, + <&cgu JZ4770_CLK_EXT>, <&cgu JZ4770_CLK_PLL0>; + clock-names = "aic", "i2s", "ext", "pll half"; + + interrupt-parent = <&intc>; + interrupts = <34>; + + dmas = <&dmac0 25 0xffffffff>, <&dmac0 24 0xffffffff>; + dma-names = "rx", "tx"; + }; + + codec: audio-codec@100200a0 { + compatible = "ingenic,jz4770-codec"; + reg = <0x100200a4 0x8>; + + #sound-dai-cells = <0>; + + clocks = <&cgu JZ4770_CLK_AIC>; + clock-names = "aic"; + }; + + mmc0: mmc@10021000 { + compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc"; + reg = <0x10021000 0x1000>; + + clocks = <&cgu JZ4770_CLK_MMC0>; + clock-names = "mmc"; + + interrupt-parent = <&intc>; + interrupts = <37>; + + dmas = <&dmac1 27 0xffffffff>, <&dmac1 26 0xffffffff>; + dma-names = "rx", "tx"; + + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + + status = "disabled"; + }; + + mmc1: mmc@10022000 { + compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc"; + reg = <0x10022000 0x1000>; + + clocks = <&cgu JZ4770_CLK_MMC1>; + clock-names = "mmc"; + + interrupt-parent = <&intc>; + interrupts = <36>; + + dmas = <&dmac1 31 0xffffffff>, <&dmac1 30 0xffffffff>; + dma-names = "rx", "tx"; + + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + + status = "disabled"; + }; + + mmc2: mmc@10023000 { + compatible = "ingenic,jz4770-mmc", "ingenic,jz4760-mmc"; + reg = <0x10023000 0x1000>; + + clocks = <&cgu JZ4770_CLK_MMC2>; + clock-names = "mmc"; + + interrupt-parent = <&intc>; + interrupts = <35>; + + dmas = <&dmac1 37 0xffffffff>, <&dmac1 36 0xffffffff>; + dma-names = "rx", "tx"; + + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + + status = "disabled"; + }; + uart0: serial@10030000 { compatible = "ingenic,jz4770-uart"; reg = <0x10030000 0x100>; @@ -217,34 +358,63 @@ status = "disabled"; }; + adc: adc@10070000 { + compatible = "ingenic,jz4770-adc"; + reg = <0x10070000 0x30>; + + #io-channel-cells = <1>; + + clocks = <&cgu JZ4770_CLK_ADC>; + clock-names = "adc"; + + interrupt-parent = <&intc>; + interrupts = <18>; + }; + + gpu: gpu@13040000 { + compatible = "vivante,gc"; + reg = <0x13040000 0x10000>; + + clocks = <&cgu JZ4770_CLK_GPU>, + <&cgu JZ4770_CLK_GPU>, + <&cgu JZ4770_CLK_GPU>; + clock-names = "bus", "core", "shader"; + + interrupt-parent = <&intc>; + interrupts = <6>; + }; + + lcd: lcd-controller@13050000 { + compatible = "ingenic,jz4770-lcd"; + reg = <0x13050000 0x300>; + + interrupt-parent = <&intc>; + interrupts = <31>; + + clocks = <&cgu JZ4770_CLK_LPCLK_MUX>; + clock-names = "lcd_pclk"; + }; + dmac0: dma-controller@13420000 { compatible = "ingenic,jz4770-dma"; - reg = <0x13420000 0xC0 - 0x13420300 0x20>; + reg = <0x13420000 0xC0>, <0x13420300 0x20>; - #dma-cells = <1>; + #dma-cells = <2>; clocks = <&cgu JZ4770_CLK_DMA>; interrupt-parent = <&intc>; interrupts = <24>; - - /* Disable dmac0 until we have something that uses it */ - status = "disabled"; }; dmac1: dma-controller@13420100 { compatible = "ingenic,jz4770-dma"; - reg = <0x13420100 0xC0 - 0x13420400 0x20>; + reg = <0x13420100 0xC0>, <0x13420400 0x20>; - #dma-cells = <1>; + #dma-cells = <2>; clocks = <&cgu JZ4770_CLK_DMA>; interrupt-parent = <&intc>; interrupts = <23>; - - /* Disable dmac1 until we have something that uses it */ - status = "disabled"; }; uhc: uhc@13430000 { @@ -260,4 +430,29 @@ status = "disabled"; }; + + usb_otg: usb@13440000 { + compatible = "ingenic,jz4770-musb"; + reg = <0x13440000 0x10000>; + + clocks = <&cgu JZ4770_CLK_OTG>; + clock-names = "udc"; + + interrupt-parent = <&intc>; + interrupts = <21>; + interrupt-names = "mc"; + + phys = <&otg_phy>; + + usb-role-switch; + }; + + rom: memory@1fc00000 { + compatible = "mtd-rom"; + probe-type = "map_rom"; + reg = <0x1fc00000 0x2000>; + + bank-width = <4>; + device-width = <1>; + }; }; diff --git a/src/mips/ingenic/jz4780.dtsi b/src/mips/ingenic/jz4780.dtsi index bb89653d16a3..b7f409a7cf5d 100644 --- a/src/mips/ingenic/jz4780.dtsi +++ b/src/mips/ingenic/jz4780.dtsi @@ -58,9 +58,9 @@ #clock-cells = <1>; - clocks = <&cgu JZ4780_CLK_RTCLK - &cgu JZ4780_CLK_EXCLK - &cgu JZ4780_CLK_PCLK>; + clocks = <&cgu JZ4780_CLK_RTCLK>, + <&cgu JZ4780_CLK_EXCLK>, + <&cgu JZ4780_CLK_PCLK>; clock-names = "rtc", "ext", "pclk"; interrupt-controller; @@ -76,6 +76,30 @@ clocks = <&tcu TCU_CLK_WDT>; clock-names = "wdt"; }; + + pwm: pwm@40 { + compatible = "ingenic,jz4780-pwm", "ingenic,jz4740-pwm"; + reg = <0x40 0x80>; + + #pwm-cells = <3>; + + clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, + <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>, + <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>; + clock-names = "timer0", "timer1", "timer2", "timer3", + "timer4", "timer5", "timer6", "timer7"; + }; + + ost: timer@e0 { + compatible = "ingenic,jz4780-ost", "ingenic,jz4770-ost"; + reg = <0xe0 0x20>; + + clocks = <&tcu TCU_CLK_OST>; + clock-names = "ost"; + + interrupts = <15>; + }; }; rtc_dev: rtc@10003000 { @@ -196,8 +220,7 @@ gpio-miso = <&gpe 14 0>; gpio-sck = <&gpe 15 0>; gpio-mosi = <&gpe 17 0>; - cs-gpios = <&gpe 16 0 - &gpe 18 0>; + cs-gpios = <&gpe 16 0>, <&gpe 18 0>; spidev@0 { compatible = "spidev"; @@ -358,26 +381,40 @@ }; nemc: nemc@13410000 { - compatible = "ingenic,jz4780-nemc"; + compatible = "ingenic,jz4780-nemc", "simple-mfd"; reg = <0x13410000 0x10000>; #address-cells = <2>; #size-cells = <1>; - ranges = <1 0 0x1b000000 0x1000000 - 2 0 0x1a000000 0x1000000 - 3 0 0x19000000 0x1000000 - 4 0 0x18000000 0x1000000 - 5 0 0x17000000 0x1000000 - 6 0 0x16000000 0x1000000>; + ranges = <0 0 0x13410000 0x10000>, + <1 0 0x1b000000 0x1000000>, + <2 0 0x1a000000 0x1000000>, + <3 0 0x19000000 0x1000000>, + <4 0 0x18000000 0x1000000>, + <5 0 0x17000000 0x1000000>, + <6 0 0x16000000 0x1000000>; clocks = <&cgu JZ4780_CLK_NEMC>; status = "disabled"; + + efuse: efuse@d0 { + reg = <0 0xd0 0x30>; + compatible = "ingenic,jz4780-efuse"; + + clocks = <&cgu JZ4780_CLK_AHB2>; + + #address-cells = <1>; + #size-cells = <1>; + + eth0_addr: eth-mac-addr@0x22 { + reg = <0x22 0x6>; + }; + }; }; dma: dma@13420000 { compatible = "ingenic,jz4780-dma"; - reg = <0x13420000 0x400 - 0x13421000 0x40>; + reg = <0x13420000 0x400>, <0x13421000 0x40>; #dma-cells = <2>; interrupt-parent = <&intc>; diff --git a/src/mips/ingenic/x1000.dtsi b/src/mips/ingenic/x1000.dtsi index 147f7d5c243a..59a63a0985a8 100644 --- a/src/mips/ingenic/x1000.dtsi +++ b/src/mips/ingenic/x1000.dtsi @@ -58,9 +58,9 @@ #clock-cells = <1>; - clocks = <&cgu X1000_CLK_RTCLK - &cgu X1000_CLK_EXCLK - &cgu X1000_CLK_PCLK>; + clocks = <&cgu X1000_CLK_RTCLK>, + <&cgu X1000_CLK_EXCLK>, + <&cgu X1000_CLK_PCLK>; clock-names = "rtc", "ext", "pclk"; interrupt-controller; @@ -239,8 +239,7 @@ pdma: dma-controller@13420000 { compatible = "ingenic,x1000-dma"; - reg = <0x13420000 0x400 - 0x13421000 0x40>; + reg = <0x13420000 0x400>, <0x13421000 0x40>; #dma-cells = <2>; interrupt-parent = <&intc>; diff --git a/src/mips/loongson/rs780e-pch.dtsi b/src/mips/loongson/rs780e-pch.dtsi index 45c54d555fa4..d0d5d60a8697 100644 --- a/src/mips/loongson/rs780e-pch.dtsi +++ b/src/mips/loongson/rs780e-pch.dtsi @@ -9,6 +9,18 @@ 0 0x40000000 0 0x40000000 0 0x40000000 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>; + pci@1a000000 { + compatible = "loongson,rs780e-pci"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + reg = <0 0x1a000000 0 0x02000000>; + + ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x00004000>, + <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>; + }; + isa { compatible = "isa"; #address-cells = <2>; @@ -21,6 +33,11 @@ interrupts = <8>; interrupt-parent = <&htpic>; }; + + acpi@800 { + compatible = "loongson,rs780e-acpi"; + reg = <1 0x800 0x100>; + }; }; }; }; diff --git a/src/mips/mscc/ocelot.dtsi b/src/mips/mscc/ocelot.dtsi index 797d336db54d..f94e8a02ed06 100644 --- a/src/mips/mscc/ocelot.dtsi +++ b/src/mips/mscc/ocelot.dtsi @@ -214,7 +214,7 @@ miim1: miim1 { pins = "GPIO_14", "GPIO_15"; - function = "miim1"; + function = "miim"; }; }; diff --git a/src/mips/qca/ar9331.dtsi b/src/mips/qca/ar9331.dtsi index 8f5aed760abb..83b3c0ce135a 100644 --- a/src/mips/qca/ar9331.dtsi +++ b/src/mips/qca/ar9331.dtsi @@ -59,7 +59,7 @@ #qca,ddr-wb-channel-cells = <1>; }; - uart: uart@18020000 { + uart: serial@18020000 { compatible = "qca,ar9330-uart"; reg = <0x18020000 0x14>; diff --git a/src/mips/qca/ar9331_dpt_module.dts b/src/mips/qca/ar9331_dpt_module.dts index 0f2b20044834..7695d326df11 100644 --- a/src/mips/qca/ar9331_dpt_module.dts +++ b/src/mips/qca/ar9331_dpt_module.dts @@ -3,6 +3,7 @@ #include #include +#include #include "ar9331.dtsi" @@ -22,8 +23,9 @@ leds { compatible = "gpio-leds"; - system { - label = "dpt-module:green:system"; + led-0 { + function = LED_FUNCTION_STATUS; + color = ; gpios = <&gpio 27 GPIO_ACTIVE_LOW>; default-state = "off"; }; diff --git a/src/powerpc/ep405.dts b/src/powerpc/ep405.dts deleted file mode 100644 index 4ac9c5ab6e6b..000000000000 --- a/src/powerpc/ep405.dts +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Device Tree Source for EP405 - * - * Copyright 2007 IBM Corp. - * Benjamin Herrenschmidt - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "ep405"; - compatible = "ep405"; - dcr-parent = <&{/cpus/cpu@0}>; - - aliases { - ethernet0 = &EMAC; - serial0 = &UART0; - serial1 = &UART1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - model = "PowerPC,405GP"; - reg = <0x00000000>; - clock-frequency = <200000000>; /* Filled in by zImage */ - timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <32>; - d-cache-line-size = <32>; - i-cache-size = <16384>; - d-cache-size = <16384>; - dcr-controller; - dcr-access-method = "native"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x00000000>; /* Filled in by zImage */ - }; - - UIC0: interrupt-controller { - compatible = "ibm,uic"; - interrupt-controller; - cell-index = <0>; - dcr-reg = <0x0c0 0x009>; - #address-cells = <0>; - #size-cells = <0>; - #interrupt-cells = <2>; - }; - - plb { - compatible = "ibm,plb3"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clock-frequency = <0>; /* Filled in by zImage */ - - SDRAM0: memory-controller { - compatible = "ibm,sdram-405gp"; - dcr-reg = <0x010 0x002>; - }; - - MAL: mcmal { - compatible = "ibm,mcmal-405gp", "ibm,mcmal"; - dcr-reg = <0x180 0x062>; - num-tx-chans = <1>; - num-rx-chans = <1>; - interrupt-parent = <&UIC0>; - interrupts = < - 0xb 0x4 /* TXEOB */ - 0xc 0x4 /* RXEOB */ - 0xa 0x4 /* SERR */ - 0xd 0x4 /* TXDE */ - 0xe 0x4 /* RXDE */>; - }; - - POB0: opb { - compatible = "ibm,opb-405gp", "ibm,opb"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xef600000 0xef600000 0x00a00000>; - dcr-reg = <0x0a0 0x005>; - clock-frequency = <0>; /* Filled in by zImage */ - - UART0: serial@ef600300 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0xef600300 0x00000008>; - virtual-reg = <0xef600300>; - clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <9600>; - interrupt-parent = <&UIC0>; - interrupts = <0x0 0x4>; - }; - - UART1: serial@ef600400 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0xef600400 0x00000008>; - virtual-reg = <0xef600400>; - clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <9600>; - interrupt-parent = <&UIC0>; - interrupts = <0x1 0x4>; - }; - - IIC: i2c@ef600500 { - compatible = "ibm,iic-405gp", "ibm,iic"; - reg = <0xef600500 0x00000011>; - interrupt-parent = <&UIC0>; - interrupts = <0x2 0x4>; - }; - - GPIO: gpio@ef600700 { - compatible = "ibm,gpio-405gp"; - reg = <0xef600700 0x00000020>; - }; - - EMAC: ethernet@ef600800 { - linux,network-index = <0x0>; - device_type = "network"; - compatible = "ibm,emac-405gp", "ibm,emac"; - interrupt-parent = <&UIC0>; - interrupts = < - 0xf 0x4 /* Ethernet */ - 0x9 0x4 /* Ethernet Wake Up */>; - local-mac-address = [000000000000]; /* Filled in by zImage */ - reg = <0xef600800 0x00000070>; - mal-device = <&MAL>; - mal-tx-channel = <0>; - mal-rx-channel = <0>; - cell-index = <0>; - max-frame-size = <1500>; - rx-fifo-size = <4096>; - tx-fifo-size = <2048>; - phy-mode = "rmii"; - phy-map = <0x00000000>; - }; - - }; - - EBC0: ebc { - compatible = "ibm,ebc-405gp", "ibm,ebc"; - dcr-reg = <0x012 0x002>; - #address-cells = <2>; - #size-cells = <1>; - - - /* The ranges property is supplied by the bootwrapper - * and is based on the firmware's configuration of the - * EBC bridge - */ - clock-frequency = <0>; /* Filled in by zImage */ - - /* NVRAM and RTC */ - nvrtc@4,200000 { - compatible = "ds1742"; - reg = <0x00000004 0x00200000 0x00000000>; /* size fixed up by zImage */ - }; - - /* "BCSR" CPLD contains a PCI irq controller */ - bcsr@4,0 { - compatible = "ep405-bcsr"; - reg = <0x00000004 0x00000000 0x00000010>; - interrupt-controller; - /* Routing table */ - irq-routing = [ 00 /* SYSERR */ - 01 /* STTM */ - 01 /* RTC */ - 01 /* FENET */ - 02 /* NB PCIIRQ mux ? */ - 03 /* SB Winbond 8259 ? */ - 04 /* Serial Ring */ - 05 /* USB (ep405pc) */ - 06 /* XIRQ 0 */ - 06 /* XIRQ 1 */ - 06 /* XIRQ 2 */ - 06 /* XIRQ 3 */ - 06 /* XIRQ 4 */ - 06 /* XIRQ 5 */ - 06 /* XIRQ 6 */ - 07]; /* Reserved */ - }; - }; - - PCI0: pci@ec000000 { - device_type = "pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - compatible = "ibm,plb405gp-pci", "ibm,plb-pci"; - primary; - reg = <0xeec00000 0x00000008 /* Config space access */ - 0xeed80000 0x00000004 /* IACK */ - 0xeed80000 0x00000004 /* Special cycle */ - 0xef480000 0x00000040>; /* Internal registers */ - - /* Outbound ranges, one memory and one IO, - * later cannot be changed. Chip supports a second - * IO range but we don't use it for now - */ - ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000 - 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; - - /* Inbound 2GB range starting at 0 */ - dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; - - /* That's all I know about IRQs on that thing ... */ - interrupt-map-mask = <0xf800 0x0 0x0 0x0>; - interrupt-map = < - /* USB */ - 0x7000 0x0 0x0 0x0 &UIC0 0x1e 0x8 /* IRQ5 */ - >; - }; - }; - - chosen { - stdout-path = "/plb/opb/serial@ef600300"; - }; -}; diff --git a/src/powerpc/pcm032.dts b/src/powerpc/pcm032.dts index c259c6b3ac5a..780e13d99e7b 100644 --- a/src/powerpc/pcm032.dts +++ b/src/powerpc/pcm032.dts @@ -3,9 +3,7 @@ * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source * * Copyright (C) 2006-2009 Pengutronix - * Sascha Hauer - * Juergen Beisert - * Wolfram Sang + * Sascha Hauer, Juergen Beisert, Wolfram Sang */ /include/ "mpc5200b.dtsi" diff --git a/src/powerpc/virtex440-ml507.dts b/src/powerpc/virtex440-ml507.dts deleted file mode 100644 index 66f1c6312de6..000000000000 --- a/src/powerpc/virtex440-ml507.dts +++ /dev/null @@ -1,406 +0,0 @@ -/* - * This file supports the Xilinx ML507 board with the 440 processor. - * A reference design for the FPGA is provided at http://git.xilinx.com. - * - * (C) Copyright 2008 Xilinx, Inc. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - * - * --- - * - * Device Tree Generator version: 1.1 - * - * CAUTION: This file is automatically generated by libgen. - * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6 - * - * XPS project directory: ml507_ppc440_emb_ref - */ - -/dts-v1/; - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,virtex440"; - dcr-parent = <&ppc440_0>; - model = "testing"; - DDR2_SDRAM: memory@0 { - device_type = "memory"; - reg = < 0 0x10000000 >; - } ; - chosen { - bootargs = "console=ttyS0 root=/dev/ram"; - stdout-path = &RS232_Uart_1; - } ; - cpus { - #address-cells = <1>; - #cpus = <1>; - #size-cells = <0>; - ppc440_0: cpu@0 { - clock-frequency = <400000000>; - compatible = "PowerPC,440", "ibm,ppc440"; - d-cache-line-size = <0x20>; - d-cache-size = <0x8000>; - dcr-access-method = "native"; - dcr-controller ; - device_type = "cpu"; - i-cache-line-size = <0x20>; - i-cache-size = <0x8000>; - model = "PowerPC,440"; - reg = <0>; - timebase-frequency = <400000000>; - xlnx,apu-control = <1>; - xlnx,apu-udi-0 = <0>; - xlnx,apu-udi-1 = <0>; - xlnx,apu-udi-10 = <0>; - xlnx,apu-udi-11 = <0>; - xlnx,apu-udi-12 = <0>; - xlnx,apu-udi-13 = <0>; - xlnx,apu-udi-14 = <0>; - xlnx,apu-udi-15 = <0>; - xlnx,apu-udi-2 = <0>; - xlnx,apu-udi-3 = <0>; - xlnx,apu-udi-4 = <0>; - xlnx,apu-udi-5 = <0>; - xlnx,apu-udi-6 = <0>; - xlnx,apu-udi-7 = <0>; - xlnx,apu-udi-8 = <0>; - xlnx,apu-udi-9 = <0>; - xlnx,dcr-autolock-enable = <1>; - xlnx,dcu-rd-ld-cache-plb-prio = <0>; - xlnx,dcu-rd-noncache-plb-prio = <0>; - xlnx,dcu-rd-touch-plb-prio = <0>; - xlnx,dcu-rd-urgent-plb-prio = <0>; - xlnx,dcu-wr-flush-plb-prio = <0>; - xlnx,dcu-wr-store-plb-prio = <0>; - xlnx,dcu-wr-urgent-plb-prio = <0>; - xlnx,dma0-control = <0>; - xlnx,dma0-plb-prio = <0>; - xlnx,dma0-rxchannelctrl = <0x1010000>; - xlnx,dma0-rxirqtimer = <0x3ff>; - xlnx,dma0-txchannelctrl = <0x1010000>; - xlnx,dma0-txirqtimer = <0x3ff>; - xlnx,dma1-control = <0>; - xlnx,dma1-plb-prio = <0>; - xlnx,dma1-rxchannelctrl = <0x1010000>; - xlnx,dma1-rxirqtimer = <0x3ff>; - xlnx,dma1-txchannelctrl = <0x1010000>; - xlnx,dma1-txirqtimer = <0x3ff>; - xlnx,dma2-control = <0>; - xlnx,dma2-plb-prio = <0>; - xlnx,dma2-rxchannelctrl = <0x1010000>; - xlnx,dma2-rxirqtimer = <0x3ff>; - xlnx,dma2-txchannelctrl = <0x1010000>; - xlnx,dma2-txirqtimer = <0x3ff>; - xlnx,dma3-control = <0>; - xlnx,dma3-plb-prio = <0>; - xlnx,dma3-rxchannelctrl = <0x1010000>; - xlnx,dma3-rxirqtimer = <0x3ff>; - xlnx,dma3-txchannelctrl = <0x1010000>; - xlnx,dma3-txirqtimer = <0x3ff>; - xlnx,endian-reset = <0>; - xlnx,generate-plb-timespecs = <1>; - xlnx,icu-rd-fetch-plb-prio = <0>; - xlnx,icu-rd-spec-plb-prio = <0>; - xlnx,icu-rd-touch-plb-prio = <0>; - xlnx,interconnect-imask = <0xffffffff>; - xlnx,mplb-allow-lock-xfer = <1>; - xlnx,mplb-arb-mode = <0>; - xlnx,mplb-awidth = <0x20>; - xlnx,mplb-counter = <0x500>; - xlnx,mplb-dwidth = <0x80>; - xlnx,mplb-max-burst = <8>; - xlnx,mplb-native-dwidth = <0x80>; - xlnx,mplb-p2p = <0>; - xlnx,mplb-prio-dcur = <2>; - xlnx,mplb-prio-dcuw = <3>; - xlnx,mplb-prio-icu = <4>; - xlnx,mplb-prio-splb0 = <1>; - xlnx,mplb-prio-splb1 = <0>; - xlnx,mplb-read-pipe-enable = <1>; - xlnx,mplb-sync-tattribute = <0>; - xlnx,mplb-wdog-enable = <1>; - xlnx,mplb-write-pipe-enable = <1>; - xlnx,mplb-write-post-enable = <1>; - xlnx,num-dma = <1>; - xlnx,pir = <0xf>; - xlnx,ppc440mc-addr-base = <0>; - xlnx,ppc440mc-addr-high = <0xfffffff>; - xlnx,ppc440mc-arb-mode = <0>; - xlnx,ppc440mc-bank-conflict-mask = <0xc00000>; - xlnx,ppc440mc-control = <0xf810008f>; - xlnx,ppc440mc-max-burst = <8>; - xlnx,ppc440mc-prio-dcur = <2>; - xlnx,ppc440mc-prio-dcuw = <3>; - xlnx,ppc440mc-prio-icu = <4>; - xlnx,ppc440mc-prio-splb0 = <1>; - xlnx,ppc440mc-prio-splb1 = <0>; - xlnx,ppc440mc-row-conflict-mask = <0x3ffe00>; - xlnx,ppcdm-asyncmode = <0>; - xlnx,ppcds-asyncmode = <0>; - xlnx,user-reset = <0>; - DMA0: sdma@80 { - compatible = "xlnx,ll-dma-1.00.a"; - dcr-reg = < 0x80 0x11 >; - interrupt-parent = <&xps_intc_0>; - interrupts = < 10 2 11 2 >; - } ; - } ; - } ; - plb_v46_0: plb@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,plb-v46-1.03.a", "simple-bus"; - ranges ; - DIP_Switches_8Bit: gpio@81460000 { - compatible = "xlnx,xps-gpio-1.00.a"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 7 2 >; - reg = < 0x81460000 0x10000 >; - xlnx,all-inputs = <1>; - xlnx,all-inputs-2 = <0>; - xlnx,dout-default = <0>; - xlnx,dout-default-2 = <0>; - xlnx,family = "virtex5"; - xlnx,gpio-width = <8>; - xlnx,interrupt-present = <1>; - xlnx,is-bidir = <1>; - xlnx,is-bidir-2 = <1>; - xlnx,is-dual = <0>; - xlnx,tri-default = <0xffffffff>; - xlnx,tri-default-2 = <0xffffffff>; - } ; - FLASH: flash@fc000000 { - bank-width = <2>; - compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash"; - reg = < 0xfc000000 0x2000000 >; - xlnx,family = "virtex5"; - xlnx,include-datawidth-matching-0 = <0x1>; - xlnx,include-datawidth-matching-1 = <0x0>; - xlnx,include-datawidth-matching-2 = <0x0>; - xlnx,include-datawidth-matching-3 = <0x0>; - xlnx,include-negedge-ioregs = <0x0>; - xlnx,include-plb-ipif = <0x1>; - xlnx,include-wrbuf = <0x1>; - xlnx,max-mem-width = <0x10>; - xlnx,mch-native-dwidth = <0x20>; - xlnx,mch-plb-clk-period-ps = <0x2710>; - xlnx,mch-splb-awidth = <0x20>; - xlnx,mch0-accessbuf-depth = <0x10>; - xlnx,mch0-protocol = <0x0>; - xlnx,mch0-rddatabuf-depth = <0x10>; - xlnx,mch1-accessbuf-depth = <0x10>; - xlnx,mch1-protocol = <0x0>; - xlnx,mch1-rddatabuf-depth = <0x10>; - xlnx,mch2-accessbuf-depth = <0x10>; - xlnx,mch2-protocol = <0x0>; - xlnx,mch2-rddatabuf-depth = <0x10>; - xlnx,mch3-accessbuf-depth = <0x10>; - xlnx,mch3-protocol = <0x0>; - xlnx,mch3-rddatabuf-depth = <0x10>; - xlnx,mem0-width = <0x10>; - xlnx,mem1-width = <0x20>; - xlnx,mem2-width = <0x20>; - xlnx,mem3-width = <0x20>; - xlnx,num-banks-mem = <0x1>; - xlnx,num-channels = <0x2>; - xlnx,priority-mode = <0x0>; - xlnx,synch-mem-0 = <0x0>; - xlnx,synch-mem-1 = <0x0>; - xlnx,synch-mem-2 = <0x0>; - xlnx,synch-mem-3 = <0x0>; - xlnx,synch-pipedelay-0 = <0x2>; - xlnx,synch-pipedelay-1 = <0x2>; - xlnx,synch-pipedelay-2 = <0x2>; - xlnx,synch-pipedelay-3 = <0x2>; - xlnx,tavdv-ps-mem-0 = <0x1adb0>; - xlnx,tavdv-ps-mem-1 = <0x3a98>; - xlnx,tavdv-ps-mem-2 = <0x3a98>; - xlnx,tavdv-ps-mem-3 = <0x3a98>; - xlnx,tcedv-ps-mem-0 = <0x1adb0>; - xlnx,tcedv-ps-mem-1 = <0x3a98>; - xlnx,tcedv-ps-mem-2 = <0x3a98>; - xlnx,tcedv-ps-mem-3 = <0x3a98>; - xlnx,thzce-ps-mem-0 = <0x88b8>; - xlnx,thzce-ps-mem-1 = <0x1b58>; - xlnx,thzce-ps-mem-2 = <0x1b58>; - xlnx,thzce-ps-mem-3 = <0x1b58>; - xlnx,thzoe-ps-mem-0 = <0x1b58>; - xlnx,thzoe-ps-mem-1 = <0x1b58>; - xlnx,thzoe-ps-mem-2 = <0x1b58>; - xlnx,thzoe-ps-mem-3 = <0x1b58>; - xlnx,tlzwe-ps-mem-0 = <0x88b8>; - xlnx,tlzwe-ps-mem-1 = <0x0>; - xlnx,tlzwe-ps-mem-2 = <0x0>; - xlnx,tlzwe-ps-mem-3 = <0x0>; - xlnx,twc-ps-mem-0 = <0x2af8>; - xlnx,twc-ps-mem-1 = <0x3a98>; - xlnx,twc-ps-mem-2 = <0x3a98>; - xlnx,twc-ps-mem-3 = <0x3a98>; - xlnx,twp-ps-mem-0 = <0x11170>; - xlnx,twp-ps-mem-1 = <0x2ee0>; - xlnx,twp-ps-mem-2 = <0x2ee0>; - xlnx,twp-ps-mem-3 = <0x2ee0>; - xlnx,xcl0-linesize = <0x4>; - xlnx,xcl0-writexfer = <0x1>; - xlnx,xcl1-linesize = <0x4>; - xlnx,xcl1-writexfer = <0x1>; - xlnx,xcl2-linesize = <0x4>; - xlnx,xcl2-writexfer = <0x1>; - xlnx,xcl3-linesize = <0x4>; - xlnx,xcl3-writexfer = <0x1>; - } ; - Hard_Ethernet_MAC: xps-ll-temac@81c00000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,compound"; - ethernet@81c00000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "xlnx,xps-ll-temac-1.01.b"; - device_type = "network"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 5 2 >; - llink-connected = <&DMA0>; - local-mac-address = [ 02 00 00 00 00 00 ]; - reg = < 0x81c00000 0x40 >; - xlnx,bus2core-clk-ratio = <1>; - xlnx,phy-type = <1>; - xlnx,phyaddr = <1>; - xlnx,rxcsum = <1>; - xlnx,rxfifo = <0x1000>; - xlnx,temac-type = <0>; - xlnx,txcsum = <1>; - xlnx,txfifo = <0x1000>; - phy-handle = <&phy7>; - clock-frequency = <100000000>; - phy7: phy@7 { - compatible = "marvell,88e1111"; - reg = <7>; - } ; - } ; - } ; - IIC_EEPROM: i2c@81600000 { - compatible = "xlnx,xps-iic-2.00.a"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 6 2 >; - reg = < 0x81600000 0x10000 >; - xlnx,clk-freq = <0x5f5e100>; - xlnx,family = "virtex5"; - xlnx,gpo-width = <0x1>; - xlnx,iic-freq = <0x186a0>; - xlnx,scl-inertial-delay = <0x0>; - xlnx,sda-inertial-delay = <0x0>; - xlnx,ten-bit-adr = <0x0>; - } ; - LEDs_8Bit: gpio@81400000 { - compatible = "xlnx,xps-gpio-1.00.a"; - reg = < 0x81400000 0x10000 >; - xlnx,all-inputs = <0>; - xlnx,all-inputs-2 = <0>; - xlnx,dout-default = <0>; - xlnx,dout-default-2 = <0>; - xlnx,family = "virtex5"; - xlnx,gpio-width = <8>; - xlnx,interrupt-present = <0>; - xlnx,is-bidir = <1>; - xlnx,is-bidir-2 = <1>; - xlnx,is-dual = <0>; - xlnx,tri-default = <0xffffffff>; - xlnx,tri-default-2 = <0xffffffff>; - } ; - LEDs_Positions: gpio@81420000 { - compatible = "xlnx,xps-gpio-1.00.a"; - reg = < 0x81420000 0x10000 >; - xlnx,all-inputs = <0>; - xlnx,all-inputs-2 = <0>; - xlnx,dout-default = <0>; - xlnx,dout-default-2 = <0>; - xlnx,family = "virtex5"; - xlnx,gpio-width = <5>; - xlnx,interrupt-present = <0>; - xlnx,is-bidir = <1>; - xlnx,is-bidir-2 = <1>; - xlnx,is-dual = <0>; - xlnx,tri-default = <0xffffffff>; - xlnx,tri-default-2 = <0xffffffff>; - } ; - Push_Buttons_5Bit: gpio@81440000 { - compatible = "xlnx,xps-gpio-1.00.a"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 8 2 >; - reg = < 0x81440000 0x10000 >; - xlnx,all-inputs = <1>; - xlnx,all-inputs-2 = <0>; - xlnx,dout-default = <0>; - xlnx,dout-default-2 = <0>; - xlnx,family = "virtex5"; - xlnx,gpio-width = <5>; - xlnx,interrupt-present = <1>; - xlnx,is-bidir = <1>; - xlnx,is-bidir-2 = <1>; - xlnx,is-dual = <0>; - xlnx,tri-default = <0xffffffff>; - xlnx,tri-default-2 = <0xffffffff>; - } ; - RS232_Uart_1: serial@83e00000 { - clock-frequency = <100000000>; - compatible = "xlnx,xps-uart16550-2.00.b", "ns16550"; - current-speed = <9600>; - device_type = "serial"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 9 2 >; - reg = < 0x83e00000 0x10000 >; - reg-offset = <0x1003>; - reg-shift = <2>; - xlnx,family = "virtex5"; - xlnx,has-external-rclk = <0>; - xlnx,has-external-xin = <0>; - xlnx,is-a-16550 = <1>; - } ; - SysACE_CompactFlash: sysace@83600000 { - compatible = "xlnx,xps-sysace-1.00.a"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 4 2 >; - reg = < 0x83600000 0x10000 >; - xlnx,family = "virtex5"; - xlnx,mem-width = <0x10>; - } ; - xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 { - compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; - reg = < 0xffff0000 0x10000 >; - xlnx,family = "virtex5"; - } ; - xps_intc_0: interrupt-controller@81800000 { - #interrupt-cells = <2>; - compatible = "xlnx,xps-intc-1.00.a"; - interrupt-controller ; - reg = < 0x81800000 0x10000 >; - xlnx,num-intr-inputs = <0xc>; - } ; - xps_timebase_wdt_1: xps-timebase-wdt@83a00000 { - compatible = "xlnx,xps-timebase-wdt-1.00.b"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 2 0 1 2 >; - reg = < 0x83a00000 0x10000 >; - xlnx,family = "virtex5"; - xlnx,wdt-enable-once = <0>; - xlnx,wdt-interval = <0x1e>; - } ; - xps_timer_1: timer@83c00000 { - compatible = "xlnx,xps-timer-1.00.a"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 3 2 >; - reg = < 0x83c00000 0x10000 >; - xlnx,count-width = <0x20>; - xlnx,family = "virtex5"; - xlnx,gen0-assert = <1>; - xlnx,gen1-assert = <1>; - xlnx,one-timer-only = <1>; - xlnx,trig0-assert = <1>; - xlnx,trig1-assert = <1>; - } ; - } ; -} ; diff --git a/src/powerpc/virtex440-ml510.dts b/src/powerpc/virtex440-ml510.dts deleted file mode 100644 index 3b736ca26ddc..000000000000 --- a/src/powerpc/virtex440-ml510.dts +++ /dev/null @@ -1,466 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Xilinx ML510 Reference Design support - * - * This DTS file was created for the ml510_bsb1_pcores_ppc440 reference design. - * The reference design contains a bug which prevent PCI DMA from working - * properly. A description of the bug is given in the plbv46_pci section. It - * needs to be fixed by the user until Xilinx updates their reference design. - * - * Copyright 2009, Roderick Colenbrander - */ - -/dts-v1/; -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,ml510-ref-design", "xlnx,virtex440"; - dcr-parent = <&ppc440_0>; - DDR2_SDRAM_DIMM0: memory@0 { - device_type = "memory"; - reg = < 0x0 0x20000000 >; - } ; - alias { - ethernet0 = &Hard_Ethernet_MAC; - serial0 = &RS232_Uart_1; - } ; - chosen { - bootargs = "console=ttyS0 root=/dev/ram"; - stdout-path = "/plb@0/serial@83e00000"; - } ; - cpus { - #address-cells = <1>; - #cpus = <0x1>; - #size-cells = <0>; - ppc440_0: cpu@0 { - #address-cells = <1>; - #size-cells = <1>; - clock-frequency = <300000000>; - compatible = "PowerPC,440", "ibm,ppc440"; - d-cache-line-size = <0x20>; - d-cache-size = <0x8000>; - dcr-access-method = "native"; - dcr-controller ; - device_type = "cpu"; - i-cache-line-size = <0x20>; - i-cache-size = <0x8000>; - model = "PowerPC,440"; - reg = <0>; - timebase-frequency = <300000000>; - xlnx,apu-control = <0x2000>; - xlnx,apu-udi-0 = <0x0>; - xlnx,apu-udi-1 = <0x0>; - xlnx,apu-udi-10 = <0x0>; - xlnx,apu-udi-11 = <0x0>; - xlnx,apu-udi-12 = <0x0>; - xlnx,apu-udi-13 = <0x0>; - xlnx,apu-udi-14 = <0x0>; - xlnx,apu-udi-15 = <0x0>; - xlnx,apu-udi-2 = <0x0>; - xlnx,apu-udi-3 = <0x0>; - xlnx,apu-udi-4 = <0x0>; - xlnx,apu-udi-5 = <0x0>; - xlnx,apu-udi-6 = <0x0>; - xlnx,apu-udi-7 = <0x0>; - xlnx,apu-udi-8 = <0x0>; - xlnx,apu-udi-9 = <0x0>; - xlnx,dcr-autolock-enable = <0x1>; - xlnx,dcu-rd-ld-cache-plb-prio = <0x0>; - xlnx,dcu-rd-noncache-plb-prio = <0x0>; - xlnx,dcu-rd-touch-plb-prio = <0x0>; - xlnx,dcu-rd-urgent-plb-prio = <0x0>; - xlnx,dcu-wr-flush-plb-prio = <0x0>; - xlnx,dcu-wr-store-plb-prio = <0x0>; - xlnx,dcu-wr-urgent-plb-prio = <0x0>; - xlnx,dma0-control = <0x0>; - xlnx,dma0-plb-prio = <0x0>; - xlnx,dma0-rxchannelctrl = <0x1010000>; - xlnx,dma0-rxirqtimer = <0x3ff>; - xlnx,dma0-txchannelctrl = <0x1010000>; - xlnx,dma0-txirqtimer = <0x3ff>; - xlnx,dma1-control = <0x0>; - xlnx,dma1-plb-prio = <0x0>; - xlnx,dma1-rxchannelctrl = <0x1010000>; - xlnx,dma1-rxirqtimer = <0x3ff>; - xlnx,dma1-txchannelctrl = <0x1010000>; - xlnx,dma1-txirqtimer = <0x3ff>; - xlnx,dma2-control = <0x0>; - xlnx,dma2-plb-prio = <0x0>; - xlnx,dma2-rxchannelctrl = <0x1010000>; - xlnx,dma2-rxirqtimer = <0x3ff>; - xlnx,dma2-txchannelctrl = <0x1010000>; - xlnx,dma2-txirqtimer = <0x3ff>; - xlnx,dma3-control = <0x0>; - xlnx,dma3-plb-prio = <0x0>; - xlnx,dma3-rxchannelctrl = <0x1010000>; - xlnx,dma3-rxirqtimer = <0x3ff>; - xlnx,dma3-txchannelctrl = <0x1010000>; - xlnx,dma3-txirqtimer = <0x3ff>; - xlnx,endian-reset = <0x0>; - xlnx,generate-plb-timespecs = <0x1>; - xlnx,icu-rd-fetch-plb-prio = <0x0>; - xlnx,icu-rd-spec-plb-prio = <0x0>; - xlnx,icu-rd-touch-plb-prio = <0x0>; - xlnx,interconnect-imask = <0xffffffff>; - xlnx,mplb-allow-lock-xfer = <0x1>; - xlnx,mplb-arb-mode = <0x0>; - xlnx,mplb-awidth = <0x20>; - xlnx,mplb-counter = <0x500>; - xlnx,mplb-dwidth = <0x80>; - xlnx,mplb-max-burst = <0x8>; - xlnx,mplb-native-dwidth = <0x80>; - xlnx,mplb-p2p = <0x0>; - xlnx,mplb-prio-dcur = <0x2>; - xlnx,mplb-prio-dcuw = <0x3>; - xlnx,mplb-prio-icu = <0x4>; - xlnx,mplb-prio-splb0 = <0x1>; - xlnx,mplb-prio-splb1 = <0x0>; - xlnx,mplb-read-pipe-enable = <0x1>; - xlnx,mplb-sync-tattribute = <0x0>; - xlnx,mplb-wdog-enable = <0x1>; - xlnx,mplb-write-pipe-enable = <0x1>; - xlnx,mplb-write-post-enable = <0x1>; - xlnx,num-dma = <0x0>; - xlnx,pir = <0xf>; - xlnx,ppc440mc-addr-base = <0x0>; - xlnx,ppc440mc-addr-high = <0x1fffffff>; - xlnx,ppc440mc-arb-mode = <0x0>; - xlnx,ppc440mc-bank-conflict-mask = <0x1800000>; - xlnx,ppc440mc-control = <0xf810008f>; - xlnx,ppc440mc-max-burst = <0x8>; - xlnx,ppc440mc-prio-dcur = <0x2>; - xlnx,ppc440mc-prio-dcuw = <0x3>; - xlnx,ppc440mc-prio-icu = <0x4>; - xlnx,ppc440mc-prio-splb0 = <0x1>; - xlnx,ppc440mc-prio-splb1 = <0x0>; - xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>; - xlnx,ppcdm-asyncmode = <0x0>; - xlnx,ppcds-asyncmode = <0x0>; - xlnx,user-reset = <0x0>; - } ; - } ; - plb_v46_0: plb@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,plb-v46-1.03.a", "simple-bus"; - ranges ; - FLASH: flash@fc000000 { - bank-width = <2>; - compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash"; - reg = < 0xfc000000 0x2000000 >; - xlnx,family = "virtex5"; - xlnx,include-datawidth-matching-0 = <0x1>; - xlnx,include-datawidth-matching-1 = <0x0>; - xlnx,include-datawidth-matching-2 = <0x0>; - xlnx,include-datawidth-matching-3 = <0x0>; - xlnx,include-negedge-ioregs = <0x0>; - xlnx,include-plb-ipif = <0x1>; - xlnx,include-wrbuf = <0x1>; - xlnx,max-mem-width = <0x10>; - xlnx,mch-native-dwidth = <0x20>; - xlnx,mch-plb-clk-period-ps = <0x2710>; - xlnx,mch-splb-awidth = <0x20>; - xlnx,mch0-accessbuf-depth = <0x10>; - xlnx,mch0-protocol = <0x0>; - xlnx,mch0-rddatabuf-depth = <0x10>; - xlnx,mch1-accessbuf-depth = <0x10>; - xlnx,mch1-protocol = <0x0>; - xlnx,mch1-rddatabuf-depth = <0x10>; - xlnx,mch2-accessbuf-depth = <0x10>; - xlnx,mch2-protocol = <0x0>; - xlnx,mch2-rddatabuf-depth = <0x10>; - xlnx,mch3-accessbuf-depth = <0x10>; - xlnx,mch3-protocol = <0x0>; - xlnx,mch3-rddatabuf-depth = <0x10>; - xlnx,mem0-width = <0x10>; - xlnx,mem1-width = <0x20>; - xlnx,mem2-width = <0x20>; - xlnx,mem3-width = <0x20>; - xlnx,num-banks-mem = <0x1>; - xlnx,num-channels = <0x2>; - xlnx,priority-mode = <0x0>; - xlnx,synch-mem-0 = <0x0>; - xlnx,synch-mem-1 = <0x0>; - xlnx,synch-mem-2 = <0x0>; - xlnx,synch-mem-3 = <0x0>; - xlnx,synch-pipedelay-0 = <0x2>; - xlnx,synch-pipedelay-1 = <0x2>; - xlnx,synch-pipedelay-2 = <0x2>; - xlnx,synch-pipedelay-3 = <0x2>; - xlnx,tavdv-ps-mem-0 = <0x1adb0>; - xlnx,tavdv-ps-mem-1 = <0x3a98>; - xlnx,tavdv-ps-mem-2 = <0x3a98>; - xlnx,tavdv-ps-mem-3 = <0x3a98>; - xlnx,tcedv-ps-mem-0 = <0x1adb0>; - xlnx,tcedv-ps-mem-1 = <0x3a98>; - xlnx,tcedv-ps-mem-2 = <0x3a98>; - xlnx,tcedv-ps-mem-3 = <0x3a98>; - xlnx,thzce-ps-mem-0 = <0x88b8>; - xlnx,thzce-ps-mem-1 = <0x1b58>; - xlnx,thzce-ps-mem-2 = <0x1b58>; - xlnx,thzce-ps-mem-3 = <0x1b58>; - xlnx,thzoe-ps-mem-0 = <0x1b58>; - xlnx,thzoe-ps-mem-1 = <0x1b58>; - xlnx,thzoe-ps-mem-2 = <0x1b58>; - xlnx,thzoe-ps-mem-3 = <0x1b58>; - xlnx,tlzwe-ps-mem-0 = <0x88b8>; - xlnx,tlzwe-ps-mem-1 = <0x0>; - xlnx,tlzwe-ps-mem-2 = <0x0>; - xlnx,tlzwe-ps-mem-3 = <0x0>; - xlnx,twc-ps-mem-0 = <0x1adb0>; - xlnx,twc-ps-mem-1 = <0x3a98>; - xlnx,twc-ps-mem-2 = <0x3a98>; - xlnx,twc-ps-mem-3 = <0x3a98>; - xlnx,twp-ps-mem-0 = <0x11170>; - xlnx,twp-ps-mem-1 = <0x2ee0>; - xlnx,twp-ps-mem-2 = <0x2ee0>; - xlnx,twp-ps-mem-3 = <0x2ee0>; - xlnx,xcl0-linesize = <0x4>; - xlnx,xcl0-writexfer = <0x1>; - xlnx,xcl1-linesize = <0x4>; - xlnx,xcl1-writexfer = <0x1>; - xlnx,xcl2-linesize = <0x4>; - xlnx,xcl2-writexfer = <0x1>; - xlnx,xcl3-linesize = <0x4>; - xlnx,xcl3-writexfer = <0x1>; - } ; - Hard_Ethernet_MAC: xps-ll-temac@81c00000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "xlnx,compound"; - ethernet@81c00000 { - compatible = "xlnx,xps-ll-temac-1.01.b"; - device_type = "network"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 8 2 >; - llink-connected = <&Hard_Ethernet_MAC_fifo>; - local-mac-address = [ 02 00 00 00 00 00 ]; - reg = < 0x81c00000 0x40 >; - xlnx,bus2core-clk-ratio = <0x1>; - xlnx,phy-type = <0x3>; - xlnx,phyaddr = <0x1>; - xlnx,rxcsum = <0x0>; - xlnx,rxfifo = <0x8000>; - xlnx,temac-type = <0x0>; - xlnx,txcsum = <0x0>; - xlnx,txfifo = <0x8000>; - } ; - } ; - Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 { - compatible = "xlnx,xps-ll-fifo-1.01.a"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 6 2 >; - reg = < 0x81a00000 0x10000 >; - xlnx,family = "virtex5"; - } ; - IIC_EEPROM: i2c@81600000 { - compatible = "xlnx,xps-iic-2.00.a"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 9 2 >; - reg = < 0x81600000 0x10000 >; - xlnx,clk-freq = <0x5f5e100>; - xlnx,family = "virtex5"; - xlnx,gpo-width = <0x1>; - xlnx,iic-freq = <0x186a0>; - xlnx,scl-inertial-delay = <0x5>; - xlnx,sda-inertial-delay = <0x5>; - xlnx,ten-bit-adr = <0x0>; - } ; - LCD_OPTIONAL: gpio@81420000 { - compatible = "xlnx,xps-gpio-1.00.a"; - reg = < 0x81420000 0x10000 >; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,dout-default = <0x0>; - xlnx,dout-default-2 = <0x0>; - xlnx,family = "virtex5"; - xlnx,gpio-width = <0xb>; - xlnx,interrupt-present = <0x0>; - xlnx,is-bidir = <0x1>; - xlnx,is-bidir-2 = <0x1>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xffffffff>; - xlnx,tri-default-2 = <0xffffffff>; - } ; - LEDs_4Bit: gpio@81400000 { - compatible = "xlnx,xps-gpio-1.00.a"; - reg = < 0x81400000 0x10000 >; - xlnx,all-inputs = <0x0>; - xlnx,all-inputs-2 = <0x0>; - xlnx,dout-default = <0x0>; - xlnx,dout-default-2 = <0x0>; - xlnx,family = "virtex5"; - xlnx,gpio-width = <0x4>; - xlnx,interrupt-present = <0x0>; - xlnx,is-bidir = <0x1>; - xlnx,is-bidir-2 = <0x1>; - xlnx,is-dual = <0x0>; - xlnx,tri-default = <0xffffffff>; - xlnx,tri-default-2 = <0xffffffff>; - } ; - RS232_Uart_1: serial@83e00000 { - clock-frequency = <100000000>; - compatible = "xlnx,xps-uart16550-2.00.b", "ns16550"; - current-speed = <9600>; - device_type = "serial"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 11 2 >; - reg = < 0x83e00000 0x10000 >; - reg-offset = <0x1003>; - reg-shift = <2>; - xlnx,family = "virtex5"; - xlnx,has-external-rclk = <0x0>; - xlnx,has-external-xin = <0x0>; - xlnx,is-a-16550 = <0x1>; - } ; - SPI_EEPROM: xps-spi@feff8000 { - compatible = "xlnx,xps-spi-2.00.b"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 10 2 >; - reg = < 0xfeff8000 0x80 >; - xlnx,family = "virtex5"; - xlnx,fifo-exist = <0x1>; - xlnx,num-ss-bits = <0x1>; - xlnx,num-transfer-bits = <0x8>; - xlnx,sck-ratio = <0x80>; - } ; - SysACE_CompactFlash: sysace@83600000 { - compatible = "xlnx,xps-sysace-1.00.a"; - interrupt-parent = <&xps_intc_0>; - interrupts = < 7 2 >; - reg = < 0x83600000 0x10000 >; - xlnx,family = "virtex5"; - xlnx,mem-width = <0x10>; - } ; - plbv46_pci_0: plbv46-pci@85e00000 { - #size-cells = <2>; - #address-cells = <3>; - compatible = "xlnx,plbv46-pci-1.03.a"; - device_type = "pci"; - reg = < 0x85e00000 0x10000 >; - - /* - * The default ML510 BSB has C_IPIFBAR2PCIBAR_0 set to - * 0 which means that a read/write to the memory mapped - * i/o region (which starts at 0xa0000000) for pci - * bar 0 on the plb side translates to 0. - * It is important to set this value to 0xa0000000, so - * that inbound and outbound pci transactions work - * properly including DMA. - */ - ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000 - 0x01000000 0 0x00000000 0xf0000000 0 0x00010000>; - - #interrupt-cells = <1>; - interrupt-parent = <&xps_intc_0>; - interrupt-map-mask = <0xff00 0x0 0x0 0x7>; - interrupt-map = < - /* IRQ mapping for pci slots and ALI M1533 - * periperhals. In total there are 5 interrupt - * lines connected to a xps_intc controller. - * Four of them are PCI IRQ A, B, C, D and - * which correspond to respectively xpx_intc - * 5, 4, 3 and 2. The fifth interrupt line is - * connected to the south bridge and this one - * uses irq 1 and is active high instead of - * active low. - * - * The M1533 contains various peripherals - * including AC97 audio, a modem, USB, IDE and - * some power management stuff. The modem - * isn't connected on the ML510 and the power - * management core also isn't used. - */ - - /* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */ - 0x3000 0 0 1 &xps_intc_0 3 2 - 0x3000 0 0 2 &xps_intc_0 2 2 - 0x3000 0 0 3 &xps_intc_0 5 2 - 0x3000 0 0 4 &xps_intc_0 4 2 - - /* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */ - /* - 0x11800 0 0 1 &xps_intc_0 5 0 2 - 0x11800 0 0 2 &xps_intc_0 4 0 2 - 0x11800 0 0 3 &xps_intc_0 3 0 2 - 0x11800 0 0 4 &xps_intc_0 2 0 2 - */ - - /* According to the datasheet + schematic - * ABCD [FPGA] of slot 5 is mapped to DABC. - * Testing showed that at least A maps to B, - * the mapping of the other pins is a guess - * and for that reason the lines have been - * commented out. - */ - /* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */ - 0x2800 0 0 1 &xps_intc_0 4 2 - /* - 0x2800 0 0 2 &xps_intc_0 3 2 - 0x2800 0 0 3 &xps_intc_0 2 2 - 0x2800 0 0 4 &xps_intc_0 5 2 - */ - - /* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */ - /* - 0x11000 0 0 1 &xps_intc_0 4 0 2 - 0x11000 0 0 2 &xps_intc_0 3 0 2 - 0x11000 0 0 3 &xps_intc_0 2 0 2 - 0x11000 0 0 4 &xps_intc_0 5 0 2 - */ - - /* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */ - 0x0800 0 0 1 &i8259 7 2 - - /* IDSEL 0x1b / dev=11, bus=0 / IDE */ - 0x5800 0 0 1 &i8259 14 2 - - /* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */ - 0x7800 0 0 1 &i8259 7 2 - >; - ali_m1533 { - #size-cells = <1>; - #address-cells = <2>; - i8259: interrupt-controller@20 { - reg = <1 0x20 2 - 1 0xa0 2 - 1 0x4d0 2>; - interrupt-controller; - device_type = "interrupt-controller"; - #address-cells = <0>; - #interrupt-cells = <2>; - compatible = "chrp,iic"; - - /* south bridge irq is active high */ - interrupts = <1 3>; - interrupt-parent = <&xps_intc_0>; - }; - }; - } ; - xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 { - compatible = "xlnx,xps-bram-if-cntlr-1.00.a"; - reg = < 0xffff0000 0x10000 >; - xlnx,family = "virtex5"; - } ; - xps_intc_0: interrupt-controller@81800000 { - #interrupt-cells = <0x2>; - compatible = "xlnx,xps-intc-1.00.a"; - interrupt-controller ; - reg = < 0x81800000 0x10000 >; - xlnx,num-intr-inputs = <0xc>; - } ; - xps_tft_0: tft@86e00000 { - compatible = "xlnx,xps-tft-1.00.a"; - reg = < 0x86e00000 0x10000 >; - xlnx,dcr-splb-slave-if = <0x1>; - xlnx,default-tft-base-addr = <0x0>; - xlnx,family = "virtex5"; - xlnx,i2c-slave-addr = <0x76>; - xlnx,mplb-awidth = <0x20>; - xlnx,mplb-dwidth = <0x80>; - xlnx,mplb-native-dwidth = <0x40>; - xlnx,mplb-smallest-slave = <0x20>; - xlnx,tft-interface = <0x1>; - } ; - } ; -} ; diff --git a/src/powerpc/walnut.dts b/src/powerpc/walnut.dts deleted file mode 100644 index 0872862c9363..000000000000 --- a/src/powerpc/walnut.dts +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Device Tree Source for IBM Walnut - * - * Copyright 2007 IBM Corp. - * Josh Boyer - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without - * any warranty of any kind, whether express or implied. - */ - -/dts-v1/; - -/ { - #address-cells = <1>; - #size-cells = <1>; - model = "ibm,walnut"; - compatible = "ibm,walnut"; - dcr-parent = <&{/cpus/cpu@0}>; - - aliases { - ethernet0 = &EMAC; - serial0 = &UART0; - serial1 = &UART1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - model = "PowerPC,405GP"; - reg = <0x00000000>; - clock-frequency = <200000000>; /* Filled in by zImage */ - timebase-frequency = <0>; /* Filled in by zImage */ - i-cache-line-size = <32>; - d-cache-line-size = <32>; - i-cache-size = <16384>; - d-cache-size = <16384>; - dcr-controller; - dcr-access-method = "native"; - }; - }; - - memory { - device_type = "memory"; - reg = <0x00000000 0x00000000>; /* Filled in by zImage */ - }; - - UIC0: interrupt-controller { - compatible = "ibm,uic"; - interrupt-controller; - cell-index = <0>; - dcr-reg = <0x0c0 0x009>; - #address-cells = <0>; - #size-cells = <0>; - #interrupt-cells = <2>; - }; - - plb { - compatible = "ibm,plb3"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - clock-frequency = <0>; /* Filled in by zImage */ - - SDRAM0: memory-controller { - compatible = "ibm,sdram-405gp"; - dcr-reg = <0x010 0x002>; - }; - - MAL: mcmal { - compatible = "ibm,mcmal-405gp", "ibm,mcmal"; - dcr-reg = <0x180 0x062>; - num-tx-chans = <1>; - num-rx-chans = <1>; - interrupt-parent = <&UIC0>; - interrupts = < - 0xb 0x4 /* TXEOB */ - 0xc 0x4 /* RXEOB */ - 0xa 0x4 /* SERR */ - 0xd 0x4 /* TXDE */ - 0xe 0x4 /* RXDE */>; - }; - - POB0: opb { - compatible = "ibm,opb-405gp", "ibm,opb"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0xef600000 0xef600000 0x00a00000>; - dcr-reg = <0x0a0 0x005>; - clock-frequency = <0>; /* Filled in by zImage */ - - UART0: serial@ef600300 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0xef600300 0x00000008>; - virtual-reg = <0xef600300>; - clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <9600>; - interrupt-parent = <&UIC0>; - interrupts = <0x0 0x4>; - }; - - UART1: serial@ef600400 { - device_type = "serial"; - compatible = "ns16550"; - reg = <0xef600400 0x00000008>; - virtual-reg = <0xef600400>; - clock-frequency = <0>; /* Filled in by zImage */ - current-speed = <9600>; - interrupt-parent = <&UIC0>; - interrupts = <0x1 0x4>; - }; - - IIC: i2c@ef600500 { - compatible = "ibm,iic-405gp", "ibm,iic"; - reg = <0xef600500 0x00000011>; - interrupt-parent = <&UIC0>; - interrupts = <0x2 0x4>; - }; - - GPIO: gpio@ef600700 { - compatible = "ibm,gpio-405gp"; - reg = <0xef600700 0x00000020>; - }; - - EMAC: ethernet@ef600800 { - device_type = "network"; - compatible = "ibm,emac-405gp", "ibm,emac"; - interrupt-parent = <&UIC0>; - interrupts = < - 0xf 0x4 /* Ethernet */ - 0x9 0x4 /* Ethernet Wake Up */>; - local-mac-address = [000000000000]; /* Filled in by zImage */ - reg = <0xef600800 0x00000070>; - mal-device = <&MAL>; - mal-tx-channel = <0>; - mal-rx-channel = <0>; - cell-index = <0>; - max-frame-size = <1500>; - rx-fifo-size = <4096>; - tx-fifo-size = <2048>; - phy-mode = "rmii"; - phy-map = <0x00000001>; - }; - - }; - - EBC0: ebc { - compatible = "ibm,ebc-405gp", "ibm,ebc"; - dcr-reg = <0x012 0x002>; - #address-cells = <2>; - #size-cells = <1>; - /* The ranges property is supplied by the bootwrapper - * and is based on the firmware's configuration of the - * EBC bridge - */ - clock-frequency = <0>; /* Filled in by zImage */ - - sram@0,0 { - reg = <0x00000000 0x00000000 0x00080000>; - }; - - flash@0,80000 { - compatible = "jedec-flash"; - bank-width = <1>; - reg = <0x00000000 0x00080000 0x00080000>; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "OpenBIOS"; - reg = <0x00000000 0x00080000>; - read-only; - }; - }; - - nvram@1,0 { - /* NVRAM and RTC */ - compatible = "ds1743-nvram"; - #bytes = <0x2000>; - reg = <0x00000001 0x00000000 0x00002000>; - }; - - keyboard@2,0 { - compatible = "intel,82C42PC"; - reg = <0x00000002 0x00000000 0x00000002>; - }; - - ir@3,0 { - compatible = "ti,TIR2000PAG"; - reg = <0x00000003 0x00000000 0x00000010>; - }; - - fpga@7,0 { - compatible = "Walnut-FPGA"; - reg = <0x00000007 0x00000000 0x00000010>; - virtual-reg = <0xf0300005>; - }; - }; - - PCI0: pci@ec000000 { - device_type = "pci"; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - compatible = "ibm,plb405gp-pci", "ibm,plb-pci"; - primary; - reg = <0xeec00000 0x00000008 /* Config space access */ - 0xeed80000 0x00000004 /* IACK */ - 0xeed80000 0x00000004 /* Special cycle */ - 0xef480000 0x00000040>; /* Internal registers */ - - /* Outbound ranges, one memory and one IO, - * later cannot be changed. Chip supports a second - * IO range but we don't use it for now - */ - ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000 - 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>; - - /* Inbound 2GB range starting at 0 */ - dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>; - - /* Walnut has all 4 IRQ pins tied together per slot */ - interrupt-map-mask = <0xf800 0x0 0x0 0x0>; - interrupt-map = < - /* IDSEL 1 */ - 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8 - - /* IDSEL 2 */ - 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8 - - /* IDSEL 3 */ - 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8 - - /* IDSEL 4 */ - 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8 - >; - }; - }; - - chosen { - stdout-path = "/plb/opb/serial@ef600300"; - }; -}; From f0f2014387364ba341d66600d6528a8a19ecb9d3 Mon Sep 17 00:00:00 2001 From: Alexander Motin Date: Tue, 4 Aug 2020 19:27:03 +0000 Subject: [PATCH 062/141] Remove extra memset() left after r342388. This memset() wiped MPI2_FUNCTION_SCSI_TASK_MGMT set by mprsas_alloc_tm(), that broke target reset on device removal, making later re-insertion into the same slot impossible, since firmware was still waiting for the driver to finish with the removed device. MFC after: 1 week Sponsored by: iXsystems, Inc. --- sys/dev/mpr/mpr_sas.c | 1 - sys/dev/mps/mps_sas.c | 1 - 2 files changed, 2 deletions(-) diff --git a/sys/dev/mpr/mpr_sas.c b/sys/dev/mpr/mpr_sas.c index 0e31f0c4d21e..efd8986263e8 100644 --- a/sys/dev/mpr/mpr_sas.c +++ b/sys/dev/mpr/mpr_sas.c @@ -515,7 +515,6 @@ mprsas_prepare_remove(struct mprsas_softc *sassc, uint16_t handle) mprsas_rescan_target(sc, targ); req = (MPI2_SCSI_TASK_MANAGE_REQUEST *)tm->cm_req; - memset(req, 0, sizeof(*req)); req->DevHandle = htole16(targ->handle); req->TaskType = MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET; diff --git a/sys/dev/mps/mps_sas.c b/sys/dev/mps/mps_sas.c index 74fced8abfab..606c9fdddc55 100644 --- a/sys/dev/mps/mps_sas.c +++ b/sys/dev/mps/mps_sas.c @@ -515,7 +515,6 @@ mpssas_prepare_remove(struct mpssas_softc *sassc, uint16_t handle) mpssas_rescan_target(sc, targ); req = (MPI2_SCSI_TASK_MANAGE_REQUEST *)cm->cm_req; - memset(req, 0, sizeof(*req)); req->DevHandle = htole16(targ->handle); req->TaskType = MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET; From 3211e783e3c24a7b0655101774fc939147a453b0 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 4 Aug 2020 19:52:16 +0000 Subject: [PATCH 063/141] rms: add a comment explaining performance deficiencies of write locking --- sys/kern/kern_rmlock.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sys/kern/kern_rmlock.c b/sys/kern/kern_rmlock.c index e7076a19aecc..e4679c07e119 100644 --- a/sys/kern/kern_rmlock.c +++ b/sys/kern/kern_rmlock.c @@ -872,6 +872,10 @@ db_show_rm(const struct lock_object *lock) * Neither rms_rlock nor rms_runlock use fences. Instead compiler barriers are * inserted to prevert reordering of generated code. Execution ordering is * provided with the use of an IPI handler. + * + * No attempt is made to track which CPUs read locked at least once, + * consequently write locking sends IPIs to all of them. This will become a + * problem at some point. The easiest way to lessen it is to provide a bitmamp. */ void From 0311b05fecd8cbd9350ae29fc31f227a6167f042 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 4 Aug 2020 19:52:52 +0000 Subject: [PATCH 064/141] cache: add missing numcache detrement on insertion failure --- sys/kern/vfs_cache.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 24638d39ee18..81ad03c9fd84 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -2001,6 +2001,7 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp, return; out_unlock_free: cache_enter_unlock(&cel); + atomic_add_long(&numcache, -1); cache_free(ncp); return; } From 17a66c708722f61f09c551eb5a4343c87125c97a Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 4 Aug 2020 19:54:10 +0000 Subject: [PATCH 065/141] vfs: add vfs_op_thread_enter/exit _crit variants and employ them in the namecache. Eliminates all spurious checks for preemption. --- sys/kern/vfs_cache.c | 16 ++++++++-------- sys/sys/mount.h | 25 +++++++++++++++++++------ 2 files changed, 27 insertions(+), 14 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 81ad03c9fd84..d457b199c6ce 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -3484,29 +3484,29 @@ cache_fplookup_climb_mount(struct cache_fpl *fpl) prev_mp = NULL; for (;;) { - if (!vfs_op_thread_enter(mp)) { + if (!vfs_op_thread_enter_crit(mp)) { if (prev_mp != NULL) - vfs_op_thread_exit(prev_mp); + vfs_op_thread_exit_crit(prev_mp); return (cache_fpl_partial(fpl)); } if (prev_mp != NULL) - vfs_op_thread_exit(prev_mp); + vfs_op_thread_exit_crit(prev_mp); if (!vn_seqc_consistent(vp, vp_seqc)) { - vfs_op_thread_exit(mp); + vfs_op_thread_exit_crit(mp); return (cache_fpl_partial(fpl)); } if (!cache_fplookup_mp_supported(mp)) { - vfs_op_thread_exit(mp); + vfs_op_thread_exit_crit(mp); return (cache_fpl_partial(fpl)); } vp = atomic_load_ptr(&mp->mnt_rootvnode); if (vp == NULL || VN_IS_DOOMED(vp)) { - vfs_op_thread_exit(mp); + vfs_op_thread_exit_crit(mp); return (cache_fpl_partial(fpl)); } vp_seqc = vn_seqc_read_any(vp); if (seqc_in_modify(vp_seqc)) { - vfs_op_thread_exit(mp); + vfs_op_thread_exit_crit(mp); return (cache_fpl_partial(fpl)); } prev_mp = mp; @@ -3515,7 +3515,7 @@ cache_fplookup_climb_mount(struct cache_fpl *fpl) break; } - vfs_op_thread_exit(prev_mp); + vfs_op_thread_exit_crit(prev_mp); fpl->tvp = vp; fpl->tvp_seqc = vp_seqc; return (0); diff --git a/sys/sys/mount.h b/sys/sys/mount.h index a3bc0518a7ea..f2ce078f2f81 100644 --- a/sys/sys/mount.h +++ b/sys/sys/mount.h @@ -1023,23 +1023,36 @@ int vfs_mount_fetch_counter(struct mount *, enum mount_counter); *zpcpu_get(mp->mnt_thread_in_ops_pcpu) == 1; \ }) -#define vfs_op_thread_enter(mp) ({ \ - bool _retval = true; \ - critical_enter(); \ +#define vfs_op_thread_enter_crit(mp) ({ \ + bool _retval_crit = true; \ + MPASS(curthread->td_critnest > 0); \ MPASS(!vfs_op_thread_entered(mp)); \ zpcpu_set_protected(mp->mnt_thread_in_ops_pcpu, 1); \ __compiler_membar(); \ if (__predict_false(mp->mnt_vfs_ops > 0)) { \ - vfs_op_thread_exit(mp); \ - _retval = false; \ + vfs_op_thread_exit_crit(mp); \ + _retval_crit = false; \ } \ + _retval_crit; \ +}) + +#define vfs_op_thread_enter(mp) ({ \ + bool _retval; \ + critical_enter(); \ + _retval = vfs_op_thread_enter_crit(mp); \ + if (__predict_false(!_retval)) \ + critical_exit(); \ _retval; \ }) -#define vfs_op_thread_exit(mp) do { \ +#define vfs_op_thread_exit_crit(mp) do { \ MPASS(vfs_op_thread_entered(mp)); \ __compiler_membar(); \ zpcpu_set_protected(mp->mnt_thread_in_ops_pcpu, 0); \ +} while (0) + +#define vfs_op_thread_exit(mp) do { \ + vfs_op_thread_exit_crit(mp); \ critical_exit(); \ } while (0) From 18bd02e2cebef09f48ca932da2dc5cd5cfcae235 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 4 Aug 2020 19:54:37 +0000 Subject: [PATCH 066/141] cache: factor away lockless dot lookup and add missing stat + sdt probe --- sys/kern/vfs_cache.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index d457b199c6ce..9e19033dc65c 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -3356,6 +3356,25 @@ cache_fplookup_final(struct cache_fpl *fpl) return (cache_fplookup_final_child(fpl, tvs)); } +static int __noinline +cache_fplookup_dot(struct cache_fpl *fpl) +{ + struct vnode *dvp; + + dvp = fpl->dvp; + + fpl->tvp = dvp; + fpl->tvp_seqc = vn_seqc_read_any(dvp); + if (seqc_in_modify(fpl->tvp_seqc)) { + return (cache_fpl_aborted(fpl)); + } + + counter_u64_add(dothits, 1); + SDT_PROBE3(vfs, namecache, lookup, hit, dvp, ".", dvp); + + return (0); +} + static int cache_fplookup_next(struct cache_fpl *fpl) { @@ -3371,12 +3390,7 @@ cache_fplookup_next(struct cache_fpl *fpl) dvp = fpl->dvp; if (__predict_false(cnp->cn_namelen == 1 && cnp->cn_nameptr[0] == '.')) { - fpl->tvp = dvp; - fpl->tvp_seqc = vn_seqc_read_any(dvp); - if (seqc_in_modify(fpl->tvp_seqc)) { - return (cache_fpl_aborted(fpl)); - } - return (0); + return (cache_fplookup_dot(fpl)); } hash = cache_get_hash(cnp->cn_nameptr, cnp->cn_namelen, dvp); From 0439b00ea8612d2e57a90b1f1b5acd900157d216 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 4 Aug 2020 19:55:00 +0000 Subject: [PATCH 067/141] cache: assorted tidy ups --- sys/kern/vfs_cache.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 9e19033dc65c..75b2cfe088d9 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -1513,7 +1513,7 @@ cache_lookup(struct vnode *dvp, struct vnode **vpp, struct componentname *cnp, } vs = vget_prep_smr(*vpp); vfs_smr_exit(); - if (vs == VGET_NONE) { + if (__predict_false(vs == VGET_NONE)) { *vpp = NULL; goto retry; } @@ -3199,7 +3199,7 @@ cache_fplookup_partial_setup(struct cache_fpl *fpl) dvp_seqc = fpl->dvp_seqc; dvs = vget_prep_smr(dvp); - if (dvs == VGET_NONE) { + if (__predict_false(dvs == VGET_NONE)) { cache_fpl_smr_exit(fpl); return (cache_fpl_aborted(fpl)); } @@ -3220,6 +3220,7 @@ cache_fplookup_partial_setup(struct cache_fpl *fpl) } fpl->ndp->ni_startdir = dvp; + return (0); } @@ -3258,8 +3259,8 @@ cache_fplookup_final_child(struct cache_fpl *fpl, enum vgetstate tvs) static int __noinline cache_fplookup_final_withparent(struct cache_fpl *fpl) { - enum vgetstate dvs, tvs; struct componentname *cnp; + enum vgetstate dvs, tvs; struct vnode *dvp, *tvp; seqc_t dvp_seqc, tvp_seqc; int error; @@ -3276,11 +3277,11 @@ cache_fplookup_final_withparent(struct cache_fpl *fpl) * This is less efficient than it can be for simplicity. */ dvs = vget_prep_smr(dvp); - if (dvs == VGET_NONE) { + if (__predict_false(dvs == VGET_NONE)) { return (cache_fpl_aborted(fpl)); } tvs = vget_prep_smr(tvp); - if (tvs == VGET_NONE) { + if (__predict_false(tvs == VGET_NONE)) { cache_fpl_smr_exit(fpl); vget_abort(dvp, dvs); return (cache_fpl_aborted(fpl)); @@ -3342,7 +3343,7 @@ cache_fplookup_final(struct cache_fpl *fpl) return (cache_fplookup_final_withparent(fpl)); tvs = vget_prep_smr(tvp); - if (tvs == VGET_NONE) { + if (__predict_false(tvs == VGET_NONE)) { return (cache_fpl_partial(fpl)); } @@ -3586,7 +3587,7 @@ cache_fplookup_parse(struct cache_fpl *fpl) for (cp = cnp->cn_nameptr; *cp != 0 && *cp != '/'; cp++) continue; cnp->cn_namelen = cp - cnp->cn_nameptr; - if (cnp->cn_namelen > NAME_MAX) { + if (__predict_false(cnp->cn_namelen > NAME_MAX)) { cache_fpl_smr_exit(fpl); return (cache_fpl_handled(fpl, ENAMETOOLONG)); } @@ -3779,6 +3780,7 @@ cache_fplookup_impl(struct vnode *dvp, struct cache_fpl *fpl) cache_fpl_smr_exit(fpl); return (CACHE_FPL_FAILED); case CACHE_FPL_STATUS_HANDLED: + MPASS(error != CACHE_FPL_FAILED); cache_fpl_smr_assert_not_entered(fpl); if (__predict_false(error != 0)) { ndp->ni_dvp = NULL; From 1164f7a5669a4e8a9788451a4acbad3d086c92c5 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 4 Aug 2020 19:55:26 +0000 Subject: [PATCH 068/141] cache: factor away failed vexec handling --- sys/kern/vfs_cache.c | 45 +++++++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 17 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 75b2cfe088d9..5e75103cdf5f 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -3668,6 +3668,33 @@ cache_fplookup_parse_advance(struct cache_fpl *fpl) } } +static int __noinline +cache_fplookup_failed_vexec(struct cache_fpl *fpl, int error) +{ + + switch (error) { + case EAGAIN: + /* + * Can happen when racing against vgone. + * */ + case EOPNOTSUPP: + cache_fpl_partial(fpl); + break; + default: + /* + * See the API contract for VOP_FPLOOKUP_VEXEC. + */ + if (!vn_seqc_consistent(fpl->dvp, fpl->dvp_seqc)) { + error = cache_fpl_aborted(fpl); + } else { + cache_fpl_smr_exit(fpl); + cache_fpl_handled(fpl, error); + } + break; + } + return (error); +} + static int cache_fplookup_impl(struct vnode *dvp, struct cache_fpl *fpl) { @@ -3715,23 +3742,7 @@ cache_fplookup_impl(struct vnode *dvp, struct cache_fpl *fpl) error = VOP_FPLOOKUP_VEXEC(fpl->dvp, cnp->cn_cred, cnp->cn_thread); if (__predict_false(error != 0)) { - switch (error) { - case EAGAIN: - case EOPNOTSUPP: /* can happen when racing against vgone */ - cache_fpl_partial(fpl); - break; - default: - /* - * See the API contract for VOP_FPLOOKUP_VEXEC. - */ - if (!vn_seqc_consistent(fpl->dvp, fpl->dvp_seqc)) { - error = cache_fpl_aborted(fpl); - } else { - cache_fpl_smr_exit(fpl); - cache_fpl_handled(fpl, error); - } - break; - } + error = cache_fplookup_failed_vexec(fpl, error); break; } From 25f965fdaac3722f2cfaf1b698737fb5fbef3421 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 4 Aug 2020 20:00:21 +0000 Subject: [PATCH 069/141] mmccam: mmc_xpt: We're only interested about losing the device Remove all the uneeded printfs Reviewed by: imp, kibab Differential Revision: https://reviews.freebsd.org/D25948 --- sys/cam/mmc/mmc_xpt.c | 28 +++++----------------------- 1 file changed, 5 insertions(+), 23 deletions(-) diff --git a/sys/cam/mmc/mmc_xpt.c b/sys/cam/mmc/mmc_xpt.c index cf4a96e29d1c..d91ee4e4f190 100644 --- a/sys/cam/mmc/mmc_xpt.c +++ b/sys/cam/mmc/mmc_xpt.c @@ -199,11 +199,6 @@ mmc_dev_async(u_int32_t async_code, struct cam_eb *bus, struct cam_et *target, struct cam_ed *device, void *async_arg) { - printf("mmc_dev_async(async_code=0x%x, path_id=%d, target_id=%x, lun_id=%" SCNx64 "\n", - async_code, - bus->path_id, - target->target_id, - device->lun_id); /* * We only need to handle events for real devices. */ @@ -211,24 +206,11 @@ mmc_dev_async(u_int32_t async_code, struct cam_eb *bus, struct cam_et *target, || device->lun_id == CAM_LUN_WILDCARD) return; - if (async_code == AC_LOST_DEVICE) { - if ((device->flags & CAM_DEV_UNCONFIGURED) == 0) { - printf("AC_LOST_DEVICE -> set to unconfigured\n"); - device->flags |= CAM_DEV_UNCONFIGURED; - xpt_release_device(device); - } else { - printf("AC_LOST_DEVICE on unconfigured device\n"); - } - } else if (async_code == AC_FOUND_DEVICE) { - printf("Got AC_FOUND_DEVICE -- whatever...\n"); - } else if (async_code == AC_PATH_REGISTERED) { - printf("Got AC_PATH_REGISTERED -- whatever...\n"); - } else if (async_code == AC_PATH_DEREGISTERED ) { - printf("Got AC_PATH_DEREGISTERED -- whatever...\n"); - } else if (async_code == AC_UNIT_ATTENTION) { - printf("Got interrupt generated by the card and ignored it\n"); - } else - panic("Unknown async code\n"); + if (async_code == AC_LOST_DEVICE && + (device->flags & CAM_DEV_UNCONFIGURED) == 0) { + device->flags |= CAM_DEV_UNCONFIGURED; + xpt_release_device(device); + } } /* Taken from nvme_scan_lun, thanks to bsdimp@ */ From cd2f74af6f191eb2d803abdb4199ff7f063704eb Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 4 Aug 2020 20:02:23 +0000 Subject: [PATCH 070/141] mmcam: Use a static length sbuf buffer We cannot sleep during cam proto_announce and sbuf sleeps so use a static length buffer like nvme(4) Reviewed by: kibab Differential Revision: https://reviews.freebsd.org/D25949 --- sys/cam/mmc/mmc_all.h | 1 - sys/cam/mmc/mmc_xpt.c | 17 +++++++++++------ 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/sys/cam/mmc/mmc_all.h b/sys/cam/mmc/mmc_all.h index dd7cd25453a8..cb8c1bc7ae2b 100644 --- a/sys/cam/mmc/mmc_all.h +++ b/sys/cam/mmc/mmc_all.h @@ -68,7 +68,6 @@ #include #include -void mmc_print_ident(struct mmc_params *ident_data); struct ccb_pathinq; struct cam_sim; void mmc_path_inq(struct ccb_pathinq *cpi, const char *hba, diff --git a/sys/cam/mmc/mmc_xpt.c b/sys/cam/mmc/mmc_xpt.c index d91ee4e4f190..a4389f1eabb2 100644 --- a/sys/cam/mmc/mmc_xpt.c +++ b/sys/cam/mmc/mmc_xpt.c @@ -411,13 +411,11 @@ mmccam_start_discovery(struct cam_sim *sim) { } /* This func is called per attached device :-( */ -void -mmc_print_ident(struct mmc_params *ident_data) +static void +mmc_print_ident(struct mmc_params *ident_data, struct sbuf *sb) { - struct sbuf *sb; bool space = false; - sb = sbuf_new_auto(); sbuf_printf(sb, "Relative addr: %08x\n", ident_data->card_rca); sbuf_printf(sb, "Card features: <"); if (ident_data->card_features & CARD_FEATURE_MMC) { @@ -463,13 +461,20 @@ mmc_print_ident(struct mmc_params *ident_data) static void mmc_proto_announce(struct cam_ed *device) { - mmc_print_ident(&device->mmc_ident_data); + struct sbuf sb; + char buffer[256]; + + sbuf_new(&sb, buffer, sizeof(buffer), SBUF_FIXEDLEN); + mmc_print_ident(&device->mmc_ident_data, &sb); + sbuf_finish(&sb); + sbuf_putbuf(&sb); } static void mmc_proto_denounce(struct cam_ed *device) { - mmc_print_ident(&device->mmc_ident_data); + + mmc_proto_announce(device); } static void From f2df51ecc5b116791967a368d13f59c5c8a9284b Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Tue, 4 Aug 2020 20:04:00 +0000 Subject: [PATCH 071/141] mmccam: Hold the periph during init We need to sleep during this routine so acquire the cam hold too. Reviewed by: imp Differential Revision: https://reviews.freebsd.org/D25946 --- sys/cam/mmc/mmc_da.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sys/cam/mmc/mmc_da.c b/sys/cam/mmc/mmc_da.c index 6c00283eb2db..b09c29387693 100644 --- a/sys/cam/mmc/mmc_da.c +++ b/sys/cam/mmc/mmc_da.c @@ -1109,7 +1109,9 @@ sdda_start_init_task(void *context, int pending) { CAM_PRIORITY_NONE); cam_periph_lock(periph); + cam_periph_hold(periph, PRIBIO|PCATCH); sdda_start_init(context, new_ccb); + cam_periph_unhold(periph); cam_periph_unlock(periph); xpt_free_ccb(new_ccb); } From 8541ae04b4e0e349e8166f050b2743111c6066ec Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 4 Aug 2020 20:31:03 +0000 Subject: [PATCH 072/141] rms: fix typo: bitmamp -> bitmap Reported by: kib --- sys/kern/kern_rmlock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/kern/kern_rmlock.c b/sys/kern/kern_rmlock.c index e4679c07e119..28927f6f84f8 100644 --- a/sys/kern/kern_rmlock.c +++ b/sys/kern/kern_rmlock.c @@ -875,7 +875,7 @@ db_show_rm(const struct lock_object *lock) * * No attempt is made to track which CPUs read locked at least once, * consequently write locking sends IPIs to all of them. This will become a - * problem at some point. The easiest way to lessen it is to provide a bitmamp. + * problem at some point. The easiest way to lessen it is to provide a bitmap. */ void From 78b517543b2cfbcce13c5c169145c29557514aaf Mon Sep 17 00:00:00 2001 From: Ruslan Bukin Date: Tue, 4 Aug 2020 20:51:05 +0000 Subject: [PATCH 073/141] Add a few macroses for conversion between DMAR unit, domain, ctx and IOMMU unit, domain, ctx. Reviewed by: kib Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D25926 --- sys/x86/iommu/intel_ctx.c | 70 +++++++++++++++++------------------ sys/x86/iommu/intel_dmar.h | 16 ++++++++ sys/x86/iommu/intel_drv.c | 7 ++-- sys/x86/iommu/intel_idpgtbl.c | 6 +-- sys/x86/iommu/intel_quirks.c | 2 +- 5 files changed, 56 insertions(+), 45 deletions(-) diff --git a/sys/x86/iommu/intel_ctx.c b/sys/x86/iommu/intel_ctx.c index 2f02bd1cdf2c..c905b1cbc1fd 100644 --- a/sys/x86/iommu/intel_ctx.c +++ b/sys/x86/iommu/intel_ctx.c @@ -117,7 +117,7 @@ dmar_map_ctx_entry(struct dmar_ctx *ctx, struct sf_buf **sfp) struct dmar_unit *dmar; dmar_ctx_entry_t *ctxp; - dmar = (struct dmar_unit *)ctx->context.domain->iommu; + dmar = CTX2DMAR(ctx); ctxp = dmar_map_pgtbl(dmar->ctx_obj, 1 + PCI_RID2BUS(ctx->rid), IOMMU_PGF_NOALLOC | IOMMU_PGF_WAITOK, sfp); @@ -131,7 +131,7 @@ device_tag_init(struct dmar_ctx *ctx, device_t dev) struct dmar_domain *domain; bus_addr_t maxaddr; - domain = (struct dmar_domain *)ctx->context.domain; + domain = CTX2DOM(ctx); maxaddr = MIN(domain->iodom.end, BUS_SPACE_MAXADDR); ctx->context.tag->common.ref_count = 1; /* Prevent free */ ctx->context.tag->common.impl = &bus_dma_iommu_impl; @@ -141,7 +141,7 @@ device_tag_init(struct dmar_ctx *ctx, device_t dev) ctx->context.tag->common.maxsize = maxaddr; ctx->context.tag->common.nsegments = BUS_SPACE_UNRESTRICTED; ctx->context.tag->common.maxsegsz = maxaddr; - ctx->context.tag->ctx = (struct iommu_ctx *)ctx; + ctx->context.tag->ctx = CTX2IOCTX(ctx); ctx->context.tag->owner = dev; } @@ -178,8 +178,8 @@ ctx_id_entry_init(struct dmar_ctx *ctx, dmar_ctx_entry_t *ctxp, bool move, vm_page_t ctx_root; int i; - domain = (struct dmar_domain *)ctx->context.domain; - unit = (struct dmar_unit *)domain->iodom.iommu; + domain = CTX2DOM(ctx); + unit = DOM2DMAR(domain); KASSERT(move || (ctxp->ctx1 == 0 && ctxp->ctx2 == 0), ("dmar%d: initialized ctx entry %d:%d:%d 0x%jx 0x%jx", unit->iommu.unit, busno, pci_get_slot(ctx->context.tag->owner), @@ -196,7 +196,7 @@ ctx_id_entry_init(struct dmar_ctx *ctx, dmar_ctx_entry_t *ctxp, bool move, IOMMU_PGF_NOALLOC); } - if (iommu_is_buswide_ctx((struct iommu_unit *)unit, busno)) { + if (iommu_is_buswide_ctx(DMAR2IOMMU(unit), busno)) { MPASS(!move); for (i = 0; i <= PCI_BUSMAX; i++) { ctx_id_entry_init_one(&ctxp[i], domain, ctx_root); @@ -283,8 +283,7 @@ domain_init_rmrr(struct dmar_domain *domain, device_t dev, int bus, ma[i] = vm_page_getfake(entry->start + PAGE_SIZE * i, VM_MEMATTR_DEFAULT); } - error1 = iommu_gas_map_region((struct iommu_domain *)domain, - entry, + error1 = iommu_gas_map_region(DOM2IODOM(domain), entry, IOMMU_MAP_ENTRY_READ | IOMMU_MAP_ENTRY_WRITE, IOMMU_MF_CANWAIT | IOMMU_MF_RMRR, ma); /* @@ -310,8 +309,7 @@ domain_init_rmrr(struct dmar_domain *domain, device_t dev, int bus, error = error1; } TAILQ_REMOVE(&rmrr_entries, entry, unroll_link); - iommu_gas_free_entry((struct iommu_domain *)domain, - entry); + iommu_gas_free_entry(DOM2IODOM(domain), entry); } for (i = 0; i < size; i++) vm_page_putfake(ma[i]); @@ -331,7 +329,7 @@ dmar_domain_alloc(struct dmar_unit *dmar, bool id_mapped) if (id == -1) return (NULL); domain = malloc(sizeof(*domain), M_DMAR_DOMAIN, M_WAITOK | M_ZERO); - iodom = (struct iommu_domain *)domain; + iodom = DOM2IODOM(domain); domain->domain = id; LIST_INIT(&domain->contexts); RB_INIT(&domain->iodom.rb_root); @@ -358,7 +356,7 @@ dmar_domain_alloc(struct dmar_unit *dmar, bool id_mapped) /* Use all supported address space for remapping. */ domain->iodom.end = 1ULL << (domain->agaw - 1); - iommu_gas_init_domain((struct iommu_domain *)domain); + iommu_gas_init_domain(DOM2IODOM(domain)); if (id_mapped) { if ((dmar->hw_ecap & DMAR_ECAP_PT) == 0) { @@ -389,7 +387,7 @@ dmar_ctx_alloc(struct dmar_domain *domain, uint16_t rid) struct dmar_ctx *ctx; ctx = malloc(sizeof(*ctx), M_DMAR_CTX, M_WAITOK | M_ZERO); - ctx->context.domain = (struct iommu_domain *)domain; + ctx->context.domain = DOM2IODOM(domain); ctx->context.tag = malloc(sizeof(struct bus_dma_tag_iommu), M_DMAR_CTX, M_WAITOK | M_ZERO); ctx->rid = rid; @@ -402,7 +400,7 @@ dmar_ctx_link(struct dmar_ctx *ctx) { struct dmar_domain *domain; - domain = (struct dmar_domain *)ctx->context.domain; + domain = CTX2DOM(ctx); IOMMU_ASSERT_LOCKED(domain->iodom.iommu); KASSERT(domain->refs >= domain->ctx_cnt, ("dom %p ref underflow %d %d", domain, domain->refs, @@ -417,7 +415,7 @@ dmar_ctx_unlink(struct dmar_ctx *ctx) { struct dmar_domain *domain; - domain = (struct dmar_domain *)ctx->context.domain; + domain = CTX2DOM(ctx); IOMMU_ASSERT_LOCKED(domain->iodom.iommu); KASSERT(domain->refs > 0, ("domain %p ctx dtr refs %d", domain, domain->refs)); @@ -444,7 +442,7 @@ dmar_domain_destroy(struct dmar_domain *domain) ("destroying dom %p with refs %d", domain, domain->refs)); if ((domain->iodom.flags & IOMMU_DOMAIN_GAS_INITED) != 0) { DMAR_DOMAIN_LOCK(domain); - iommu_gas_fini_domain((struct iommu_domain *)domain); + iommu_gas_fini_domain(DOM2IODOM(domain)); DMAR_DOMAIN_UNLOCK(domain); } if ((domain->iodom.flags & IOMMU_DOMAIN_PGTBL_INITED) != 0) { @@ -453,7 +451,7 @@ dmar_domain_destroy(struct dmar_domain *domain) domain_free_pgtbl(domain); } mtx_destroy(&domain->iodom.lock); - dmar = (struct dmar_unit *)domain->iodom.iommu; + dmar = DOM2DMAR(domain); free_unr(dmar->domids, domain->domain); free(domain, M_DMAR_DOMAIN); } @@ -482,7 +480,7 @@ dmar_get_ctx_for_dev1(struct dmar_unit *dmar, device_t dev, uint16_t rid, } enable = false; TD_PREP_PINNED_ASSERT; - unit = (struct iommu_unit *)dmar; + unit = DMAR2IOMMU(dmar); DMAR_LOCK(dmar); KASSERT(!iommu_is_buswide_ctx(unit, bus) || (slot == 0 && func == 0), ("iommu%d pci%d:%d:%d get_ctx for buswide", dmar->iommu.unit, bus, @@ -550,11 +548,11 @@ dmar_get_ctx_for_dev1(struct dmar_unit *dmar, device_t dev, uint16_t rid, dmar_domain_destroy(domain1); /* Nothing needs to be done to destroy ctx1. */ free(ctx1, M_DMAR_CTX); - domain = (struct dmar_domain *)ctx->context.domain; + domain = CTX2DOM(ctx); ctx->refs++; /* tag referenced us */ } } else { - domain = (struct dmar_domain *)ctx->context.domain; + domain = CTX2DOM(ctx); if (ctx->context.tag->owner == NULL) ctx->context.tag->owner = dev; ctx->refs++; /* tag referenced us */ @@ -627,7 +625,7 @@ dmar_move_ctx_to_domain(struct dmar_domain *domain, struct dmar_ctx *ctx) int error; dmar = domain->dmar; - old_domain = (struct dmar_domain *)ctx->context.domain; + old_domain = CTX2DOM(ctx); if (domain == old_domain) return (0); KASSERT(old_domain->iodom.iommu == domain->iodom.iommu, @@ -748,7 +746,7 @@ dmar_free_ctx_locked(struct dmar_unit *dmar, struct dmar_ctx *ctx) dmar_inv_iotlb_glob(dmar); } dmar_unmap_pgtbl(sf); - domain = (struct dmar_domain *)ctx->context.domain; + domain = CTX2DOM(ctx); dmar_ctx_unlink(ctx); free(ctx->context.tag, M_DMAR_CTX); free(ctx, M_DMAR_CTX); @@ -761,7 +759,7 @@ dmar_free_ctx(struct dmar_ctx *ctx) { struct dmar_unit *dmar; - dmar = (struct dmar_unit *)ctx->context.domain->iommu; + dmar = CTX2DMAR(ctx); DMAR_LOCK(dmar); dmar_free_ctx_locked(dmar, ctx); } @@ -810,11 +808,11 @@ dmar_domain_unload_entry(struct iommu_map_entry *entry, bool free) struct dmar_domain *domain; struct dmar_unit *unit; - domain = (struct dmar_domain *)entry->domain; - unit = (struct dmar_unit *)domain->iodom.iommu; + domain = IODOM2DOM(entry->domain); + unit = DOM2DMAR(domain); if (unit->qi_enabled) { DMAR_LOCK(unit); - dmar_qi_invalidate_locked((struct dmar_domain *)entry->domain, + dmar_qi_invalidate_locked(IODOM2DOM(entry->domain), entry->start, entry->end - entry->start, &entry->gseq, true); if (!free) @@ -822,7 +820,7 @@ dmar_domain_unload_entry(struct iommu_map_entry *entry, bool free) TAILQ_INSERT_TAIL(&unit->tlb_flush_entries, entry, dmamap_link); DMAR_UNLOCK(unit); } else { - domain_flush_iotlb_sync((struct dmar_domain *)entry->domain, + domain_flush_iotlb_sync(IODOM2DOM(entry->domain), entry->start, entry->end - entry->start); dmar_domain_free_entry(entry, free); } @@ -847,8 +845,8 @@ dmar_domain_unload(struct dmar_domain *domain, struct iommu_map_entry *entry, *entry1; int error; - iodom = (struct iommu_domain *)domain; - unit = (struct dmar_unit *)domain->iodom.iommu; + iodom = DOM2IODOM(domain); + unit = DOM2DMAR(domain); TAILQ_FOREACH_SAFE(entry, entries, dmamap_link, entry1) { KASSERT((entry->flags & IOMMU_MAP_ENTRY_MAP) != 0, @@ -904,11 +902,11 @@ iommu_get_ctx(struct iommu_unit *iommu, device_t dev, uint16_t rid, struct dmar_unit *dmar; struct dmar_ctx *ret; - dmar = (struct dmar_unit *)iommu; + dmar = IOMMU2DMAR(iommu); ret = dmar_get_ctx_for_dev(dmar, dev, rid, id_mapped, rmrr_init); - return ((struct iommu_ctx *)ret); + return (CTX2IOCTX(ret)); } void @@ -917,8 +915,8 @@ iommu_free_ctx_locked(struct iommu_unit *iommu, struct iommu_ctx *context) struct dmar_unit *dmar; struct dmar_ctx *ctx; - dmar = (struct dmar_unit *)iommu; - ctx = (struct dmar_ctx *)context; + dmar = IOMMU2DMAR(iommu); + ctx = IOCTX2CTX(context); dmar_free_ctx_locked(dmar, ctx); } @@ -926,11 +924,9 @@ iommu_free_ctx_locked(struct iommu_unit *iommu, struct iommu_ctx *context) void iommu_free_ctx(struct iommu_ctx *context) { - struct dmar_unit *dmar; struct dmar_ctx *ctx; - ctx = (struct dmar_ctx *)context; - dmar = (struct dmar_unit *)ctx->context.domain->iommu; + ctx = IOCTX2CTX(context); dmar_free_ctx(ctx); } @@ -948,7 +944,7 @@ iommu_domain_unload(struct iommu_domain *iodom, { struct dmar_domain *domain; - domain = (struct dmar_domain *)iodom; + domain = IODOM2DOM(iodom); dmar_domain_unload(domain, entries, cansleep); } diff --git a/sys/x86/iommu/intel_dmar.h b/sys/x86/iommu/intel_dmar.h index 23cffe6f6fb6..ae9dd282e567 100644 --- a/sys/x86/iommu/intel_dmar.h +++ b/sys/x86/iommu/intel_dmar.h @@ -91,6 +91,22 @@ struct dmar_ctx { #define DMAR_DOMAIN_UNLOCK(dom) mtx_unlock(&(dom)->iodom.lock) #define DMAR_DOMAIN_ASSERT_LOCKED(dom) mtx_assert(&(dom)->iodom.lock, MA_OWNED) +#define DMAR2IOMMU(dmar) &((dmar)->iommu) +#define IOMMU2DMAR(dmar) \ + __containerof((dmar), struct dmar_unit, iommu) + +#define DOM2IODOM(domain) &((domain)->iodom) +#define IODOM2DOM(domain) \ + __containerof((domain), struct dmar_domain, iodom) + +#define CTX2IOCTX(ctx) &((ctx)->context) +#define IOCTX2CTX(ctx) \ + __containerof((ctx), struct dmar_ctx, context) + +#define CTX2DOM(ctx) IODOM2DOM((ctx)->context.domain) +#define CTX2DMAR(ctx) (CTX2DOM(ctx)->dmar) +#define DOM2DMAR(domain) ((domain)->dmar) + struct dmar_msi_data { int irq; int irq_rid; diff --git a/sys/x86/iommu/intel_drv.c b/sys/x86/iommu/intel_drv.c index 17fea13d1387..e16fa2bbb697 100644 --- a/sys/x86/iommu/intel_drv.c +++ b/sys/x86/iommu/intel_drv.c @@ -919,8 +919,7 @@ dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg) match = dmar_match_devscope(devscope, ria->dev_busno, ria->dev_path, ria->dev_path_len); if (match == 1) { - entry = iommu_gas_alloc_entry( - (struct iommu_domain *)ria->domain, + entry = iommu_gas_alloc_entry(DOM2IODOM(ria->domain), IOMMU_PGF_WAITOK); entry->start = resmem->BaseAddress; /* The RMRR entry end address is inclusive. */ @@ -1056,7 +1055,7 @@ dmar_instantiate_rmrr_ctxs(struct iommu_unit *unit) struct inst_rmrr_iter_args iria; int error; - dmar = (struct dmar_unit *)unit; + dmar = IOMMU2DMAR(unit); if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR)) return (0); @@ -1131,7 +1130,7 @@ dmar_print_domain(struct dmar_domain *domain, bool show_mappings) struct iommu_map_entry *entry; struct dmar_ctx *ctx; - iodom = (struct iommu_domain *)domain; + iodom = DOM2IODOM(domain); db_printf( " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n" diff --git a/sys/x86/iommu/intel_idpgtbl.c b/sys/x86/iommu/intel_idpgtbl.c index 9e4beea9031b..910e135f30e5 100644 --- a/sys/x86/iommu/intel_idpgtbl.c +++ b/sys/x86/iommu/intel_idpgtbl.c @@ -512,7 +512,7 @@ domain_map_buf(struct iommu_domain *iodom, iommu_gaddr_t base, ((eflags & IOMMU_MAP_ENTRY_SNOOP) != 0 ? DMAR_PTE_SNP : 0) | ((eflags & IOMMU_MAP_ENTRY_TM) != 0 ? DMAR_PTE_TM : 0); - domain = (struct dmar_domain *)iodom; + domain = IODOM2DOM(iodom); unit = domain->dmar; KASSERT((domain->iodom.flags & IOMMU_DOMAIN_IDMAP) == 0, @@ -691,7 +691,7 @@ domain_unmap_buf(struct iommu_domain *iodom, iommu_gaddr_t base, struct dmar_domain *domain; int error; - domain = (struct dmar_domain *)iodom; + domain = IODOM2DOM(iodom); DMAR_DOMAIN_PGLOCK(domain); error = domain_unmap_buf_locked(domain, base, size, flags); @@ -823,6 +823,6 @@ domain_pgtbl_init(struct dmar_domain *domain) { struct iommu_domain *iodom; - iodom = (struct iommu_domain *)domain; + iodom = DOM2IODOM(domain); iodom->ops = &dmar_domain_map_ops; } diff --git a/sys/x86/iommu/intel_quirks.c b/sys/x86/iommu/intel_quirks.c index 1a025b3419eb..84626936eb81 100644 --- a/sys/x86/iommu/intel_quirks.c +++ b/sys/x86/iommu/intel_quirks.c @@ -226,7 +226,7 @@ dmar_quirks_pre_use(struct iommu_unit *unit) { struct dmar_unit *dmar; - dmar = (struct dmar_unit *)unit; + dmar = IOMMU2DMAR(unit); if (!dmar_barrier_enter(dmar, DMAR_BARRIER_USEQ)) return; From b64dca2b6f1e2d670c6aaa4f592e6424eb80b7b4 Mon Sep 17 00:00:00 2001 From: Ruslan Bukin Date: Tue, 4 Aug 2020 20:54:12 +0000 Subject: [PATCH 074/141] Remove unneeded cast to struct iommu_domain *. Sponsored by: DARPA, AFRL --- sys/dev/iommu/iommu_gas.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sys/dev/iommu/iommu_gas.c b/sys/dev/iommu/iommu_gas.c index fe5d59329b9d..0baf996bf416 100644 --- a/sys/dev/iommu/iommu_gas.c +++ b/sys/dev/iommu/iommu_gas.c @@ -111,7 +111,7 @@ void iommu_gas_free_entry(struct iommu_domain *domain, struct iommu_map_entry *entry) { - KASSERT(domain == (struct iommu_domain *)entry->domain, + KASSERT(domain == entry->domain, ("mismatched free domain %p entry %p entry->domain %p", domain, entry, entry->domain)); atomic_subtract_int(&domain->entries_cnt, 1); @@ -174,7 +174,7 @@ iommu_gas_check_free(struct iommu_domain *domain) iommu_gaddr_t v; RB_FOREACH(entry, iommu_gas_entries_tree, &domain->rb_root) { - KASSERT(domain == (struct iommu_domain *)entry->domain, + KASSERT(domain == entry->domain, ("mismatched free domain %p entry %p entry->domain %p", domain, entry, entry->domain)); l = RB_LEFT(entry, rb_entry); From 32592d86dfad2781a260387082ccdf251bc45abd Mon Sep 17 00:00:00 2001 From: Eric van Gyzen Date: Tue, 4 Aug 2020 21:05:53 +0000 Subject: [PATCH 075/141] devinfo: fix memory leak on error paths Refactor to create devinfo_free_dev(). Call it to plug a memory leak on two error paths in devinfo_init_devices(). Reported by: Coverity MFC after: 2 weeks Sponsored by: Dell EMC Isilon --- lib/libdevinfo/devinfo.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/lib/libdevinfo/devinfo.c b/lib/libdevinfo/devinfo.c index c4cd8d78ba94..581d3464cd0e 100644 --- a/lib/libdevinfo/devinfo.c +++ b/lib/libdevinfo/devinfo.c @@ -76,6 +76,7 @@ __FBSDID("$FreeBSD$"); static int devinfo_init_devices(int generation); static int devinfo_init_resources(int generation); +static void devinfo_free_dev(struct devinfo_i_dev *dd); TAILQ_HEAD(,devinfo_i_dev) devinfo_dev; TAILQ_HEAD(,devinfo_i_rman) devinfo_rman; @@ -225,7 +226,7 @@ devinfo_init_devices(int generation) rlen, sizeof(udev)); return (EINVAL); } - if ((dd = malloc(sizeof(*dd))) == NULL) + if ((dd = calloc(1, sizeof(*dd))) == NULL) return(ENOMEM); dd->dd_dev.dd_handle = udev.dv_handle; dd->dd_dev.dd_parent = udev.dv_parent; @@ -242,10 +243,14 @@ devinfo_init_devices(int generation) dd->dd_location = NULL; #define UNPACK(x) \ dd->dd_dev.x = dd->x = strdup(walker); \ - if (dd->x == NULL) \ + if (dd->x == NULL) { \ + devinfo_free_dev(dd); \ return(ENOMEM); \ - if (walker + strnlen(walker, ep - walker) >= ep) \ + } \ + if (walker + strnlen(walker, ep - walker) >= ep) { \ + devinfo_free_dev(dd); \ return(EINVAL); \ + } \ walker += strlen(walker) + 1; UNPACK(dd_name); @@ -364,6 +369,20 @@ devinfo_init_resources(int generation) return(0); } +/* + * Free an individual dev. + */ +static void +devinfo_free_dev(struct devinfo_i_dev *dd) +{ + free(dd->dd_name); + free(dd->dd_desc); + free(dd->dd_drivername); + free(dd->dd_pnpinfo); + free(dd->dd_location); + free(dd); +} + /* * Free the list contents. */ @@ -376,12 +395,7 @@ devinfo_free(void) while ((dd = TAILQ_FIRST(&devinfo_dev)) != NULL) { TAILQ_REMOVE(&devinfo_dev, dd, dd_link); - free(dd->dd_name); - free(dd->dd_desc); - free(dd->dd_drivername); - free(dd->dd_pnpinfo); - free(dd->dd_location); - free(dd); + devinfo_free_dev(dd); } while ((dm = TAILQ_FIRST(&devinfo_rman)) != NULL) { TAILQ_REMOVE(&devinfo_rman, dm, dm_link); From d7e515ff26d005e3dac9615e660d074d1bc0a069 Mon Sep 17 00:00:00 2001 From: Eric van Gyzen Date: Tue, 4 Aug 2020 21:09:36 +0000 Subject: [PATCH 076/141] devinfo: add man page links Add man page links for all functions in devinfo(3). Reported by: vim MFC after: 2 weeks Sponsored by: Dell EMC Isilon --- lib/libdevinfo/Makefile | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/lib/libdevinfo/Makefile b/lib/libdevinfo/Makefile index 8b67ab4c372a..7995660fb7fd 100644 --- a/lib/libdevinfo/Makefile +++ b/lib/libdevinfo/Makefile @@ -5,6 +5,16 @@ SRCS= devinfo.c INCS= devinfo.h MAN= devinfo.3 +MLINKS+=devinfo.3 devinfo_init.3 +MLINKS+=devinfo.3 devinfo_free.3 +MLINKS+=devinfo.3 devinfo_handle_to_device.3 +MLINKS+=devinfo.3 devinfo_handle_to_resource.3 +MLINKS+=devinfo.3 devinfo_handle_to_rman.3 +MLINKS+=devinfo.3 devinfo_foreach_device_child.3 +MLINKS+=devinfo.3 devinfo_foreach_device_resource.3 +MLINKS+=devinfo.3 devinfo_foreach_rman_resource.3 +MLINKS+=devinfo.3 devinfo_foreach_rman.3 + SHLIB_MAJOR= 6 WARNS?= 3 From 784d8d8db08b11101b0278fc22bb232665c3b1b1 Mon Sep 17 00:00:00 2001 From: Olivier Cochard Date: Tue, 4 Aug 2020 21:34:13 +0000 Subject: [PATCH 077/141] Skip sbin/route tests if jail not installed (WITHOUT_JAIL). Approved by: kp Sponsored by: Netflix Differential Revision: https://reviews.freebsd.org/D25935 --- sbin/route/tests/basic.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sbin/route/tests/basic.sh b/sbin/route/tests/basic.sh index 6141097a09ec..370a96a25892 100644 --- a/sbin/route/tests/basic.sh +++ b/sbin/route/tests/basic.sh @@ -34,7 +34,7 @@ basic_v4_head() { atf_set descr 'add/change/delete route test for v4' atf_set require.user root - atf_set require.progs jq + atf_set require.progs jail jq } basic_v4_body() @@ -79,7 +79,7 @@ basic_v6_head() { atf_set descr 'add/change/delete route test for v6' atf_set require.user root - atf_set require.progs jq + atf_set require.progs jail jq } basic_v6_body() From 0bc1c0786b26b9ec564a463bacddb66793f75aa0 Mon Sep 17 00:00:00 2001 From: Kyle Evans Date: Tue, 4 Aug 2020 21:49:13 +0000 Subject: [PATCH 078/141] makesyscalls.lua: improve syscall ordering validation There were two separate issues here: 1.) #if/#else wasn't taken into account at all for maxsyscall figures, but 2.) We didn't validate contiguous syscall numbers anyways... This kind of inconsistency is bad as we don't currently ensure explicit indexing of, e.g., the sysent array if one syscall is unimplemented/missing. This could be fixed and might be more robust, but it's also good to have the "documentation" that comes from being explicit as to what the missing syscalls are. The new version looks much like the awk version; stash off the current 'last highest syscall seen' if we hit an #if, restore to that if we hit an #else, and make sure that we're explicitly always defining the next syscall. The logic at the tail end of process_syscall_def that moves maxsyscall has been 'cleaned up' a little since we're now ensuring that it's monotonically increasing earlier in the function. At the moment I think it's unlikely we'd see range-definitions that are not UNIMPL, but there's no reason to specifically handle that case for bumping maxsyscall there. This change was provoked by reading the commit message for r363832 and realizing that this validation hadn't been included in the initial rewrite to lua. Reviewed by: brooks Differential Revision: https://reviews.freebsd.org/D25945 --- sys/tools/makesyscalls.lua | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/sys/tools/makesyscalls.lua b/sys/tools/makesyscalls.lua index 286230cb13a1..276594f4f6ac 100644 --- a/sys/tools/makesyscalls.lua +++ b/sys/tools/makesyscalls.lua @@ -35,7 +35,8 @@ local lfs = require("lfs") local unistd = require("posix.unistd") -local maxsyscall = 0 +local savesyscall = -1 +local maxsyscall = -1 local generated_tag = "@" .. "generated" -- Default configuration; any of these may get replaced by a configuration file @@ -442,6 +443,11 @@ local pattern_table = { dump_prevline = true, pattern = "^#", process = function(line) + if line:find("^#%s*if") then + savesyscall = maxsyscall + elseif line:find("^#%s*else") then + maxsyscall = savesyscall + end line = line .. "\n" write_line('sysent', line) write_line('sysdcl', line) @@ -916,6 +922,16 @@ process_syscall_def = function(line) sysnum = nil sysstart = tonumber(sysstart) sysend = tonumber(sysend) + if sysstart ~= maxsyscall + 1 then + abort(1, "syscall number out of sync, missing " .. + maxsyscall + 1) + end + else + sysnum = tonumber(sysnum) + if sysnum ~= maxsyscall + 1 then + abort(1, "syscall number out of sync, missing " .. + maxsyscall + 1) + end end -- Split flags @@ -1093,15 +1109,14 @@ process_syscall_def = function(line) handle_obsol(sysnum, funcname, funcomment) elseif flags & known_flags["UNIMPL"] ~= 0 then handle_unimpl(sysnum, sysstart, sysend, funcomment) - if sysend ~= nil and sysend > maxsyscall then - maxsyscall = sysend - end else abort(1, "Bad flags? " .. line) end - if sysnum ~= nil and tonumber(sysnum) > maxsyscall then - maxsyscall = tonumber(sysnum) + if sysend ~= nil then + maxsyscall = sysend + elseif sysnum ~= nil then + maxsyscall = sysnum end end From 9ea72650667f023faf33c2cfb6a9389abba37178 Mon Sep 17 00:00:00 2001 From: Ilya Bakulin Date: Tue, 4 Aug 2020 21:58:43 +0000 Subject: [PATCH 079/141] Minor cleanups in mmc_xpt.c * Downgrade some CAM debug messages from _INFO to _DEBUG level; * Add KASSERT for the case when we suspect incorrect CAM SIM initialization (using cam_sim_alloc() instead of cam_sim_alloc_dev()); * Use waiting version of xpt_alloc_ccb(), we are not in hurry; * With the waiting version we cannot get NULL return, so remove the NULL check; * In some csses, the name of mmcprobe_done has been written as mmc_probedone(); * Send AC_LOST_DEVICE if we, well, lost the device; * Misc style(9) fixes. Reviewed by: manu Approved by: imp (mentor) Differential Revision: https://reviews.freebsd.org/D25843 --- sys/cam/mmc/mmc_xpt.c | 47 ++++++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/sys/cam/mmc/mmc_xpt.c b/sys/cam/mmc/mmc_xpt.c index a4389f1eabb2..ea0426dbc478 100644 --- a/sys/cam/mmc/mmc_xpt.c +++ b/sys/cam/mmc/mmc_xpt.c @@ -374,8 +374,7 @@ mmc_announce_periph(struct cam_periph *periph) cam_periph_assert(periph, MA_OWNED); - CAM_DEBUG(periph->path, CAM_DEBUG_INFO, - ("mmc_announce_periph: called\n")); + CAM_DEBUG(periph->path, CAM_DEBUG_TRACE, ("mmc_announce_periph")); xpt_setup_ccb(&cts.ccb_h, path, CAM_PRIORITY_NORMAL); cts.ccb_h.func_code = XPT_GET_TRAN_SETTINGS; @@ -388,15 +387,15 @@ mmc_announce_periph(struct cam_periph *periph) } void -mmccam_start_discovery(struct cam_sim *sim) { +mmccam_start_discovery(struct cam_sim *sim) +{ union ccb *ccb; uint32_t pathid; + KASSERT(sim->sim_dev != NULL, ("mmccam_start_discovery(%s): sim_dev is not initialized," + " has cam_sim_alloc_dev() been used?", cam_sim_name(sim))); pathid = cam_sim_path(sim); - ccb = xpt_alloc_ccb_nowait(); - if (ccb == NULL) { - return; - } + ccb = xpt_alloc_ccb(); /* * We create a rescan request for BUS:0:0, since the card @@ -806,7 +805,7 @@ mmcprobe_done(struct cam_periph *periph, union ccb *done_ccb) struct ccb_mmcio *mmcio; u_int32_t priority; - CAM_DEBUG(done_ccb->ccb_h.path, CAM_DEBUG_PROBE, ("mmcprobe_done\n")); + CAM_DEBUG(done_ccb->ccb_h.path, CAM_DEBUG_TRACE, ("mmcprobe_done\n")); softc = (mmcprobe_softc *)periph->softc; path = done_ccb->ccb_h.path; priority = done_ccb->ccb_h.pinfo.priority; @@ -827,6 +826,9 @@ mmcprobe_done(struct cam_periph *periph, union ccb *done_ccb) /* There was a device there, but now it's gone... */ if ((path->device->flags & CAM_DEV_UNCONFIGURED) == 0) { + CAM_DEBUG(done_ccb->ccb_h.path, CAM_DEBUG_PROBE, + ("Device lost!\n")); + xpt_async(AC_LOST_DEVICE, path, NULL); } PROBE_SET_ACTION(softc, PROBE_INVALID); @@ -896,7 +898,7 @@ mmcprobe_done(struct cam_periph *periph, union ccb *done_ccb) ("SDIO card: %d functions\n", mmcp->sdio_func_count)); if (io_ocr == 0) { CAM_DEBUG(done_ccb->ccb_h.path, CAM_DEBUG_PROBE, - ("SDIO OCR invalid?!\n")); + ("SDIO OCR invalid, retrying\n")); break; /* Retry */ } @@ -1120,22 +1122,21 @@ mmcprobe_done(struct cam_periph *periph, union ccb *done_ccb) } default: CAM_DEBUG(done_ccb->ccb_h.path, CAM_DEBUG_PROBE, - ("mmc_probedone: invalid action state 0x%x\n", softc->action)); + ("mmcprobe_done: invalid action state 0x%x\n", softc->action)); panic("default: case in mmc_probe_done()"); } - if (softc->action == PROBE_INVALID && - (path->device->flags & CAM_DEV_UNCONFIGURED) == 0) { - CAM_DEBUG(done_ccb->ccb_h.path, CAM_DEBUG_PROBE, - ("mmc_probedone: Should send AC_LOST_DEVICE but won't for now\n")); - //xpt_async(AC_LOST_DEVICE, path, NULL); - } + if (softc->action == PROBE_INVALID && + (path->device->flags & CAM_DEV_UNCONFIGURED) == 0) { + xpt_async(AC_LOST_DEVICE, path, NULL); + } - if (softc->action != PROBE_INVALID) - xpt_schedule(periph, priority); + if (softc->action != PROBE_INVALID) + xpt_schedule(periph, priority); /* Drop freeze taken due to CAM_DEV_QFREEZE flag set. */ int frozen = cam_release_devq(path, 0, 0, 0, FALSE); - CAM_DEBUG(done_ccb->ccb_h.path, CAM_DEBUG_PROBE, ("mmc_probedone: remaining freezecnt %d\n", frozen)); + CAM_DEBUG(done_ccb->ccb_h.path, CAM_DEBUG_PROBE, + ("mmcprobe_done: remaining freeze count %d\n", frozen)); if (softc->action == PROBE_DONE) { /* Notify the system that the device is found! */ @@ -1148,10 +1149,10 @@ mmcprobe_done(struct cam_periph *periph, union ccb *done_ccb) } } xpt_release_ccb(done_ccb); - if (softc->action == PROBE_DONE || softc->action == PROBE_INVALID) { - cam_periph_invalidate(periph); - cam_periph_release_locked(periph); - } + if (softc->action == PROBE_DONE || softc->action == PROBE_INVALID) { + cam_periph_invalidate(periph); + cam_periph_release_locked(periph); + } } void From bd66a0750f7ad8c13d4904fa976a03601a560cbf Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 4 Aug 2020 23:00:00 +0000 Subject: [PATCH 080/141] mtx: add mtx_wait_unlocked --- sys/kern/kern_mutex.c | 29 +++++++++++++++++++++++++++++ sys/sys/mutex.h | 1 + 2 files changed, 30 insertions(+) diff --git a/sys/kern/kern_mutex.c b/sys/kern/kern_mutex.c index 13a04a5c8d12..0530a99ce40d 100644 --- a/sys/kern/kern_mutex.c +++ b/sys/kern/kern_mutex.c @@ -1275,6 +1275,35 @@ mtx_spin_wait_unlocked(struct mtx *m) } } +void +mtx_wait_unlocked(struct mtx *m) +{ + struct thread *owner; + uintptr_t v; + + KASSERT(m->mtx_lock != MTX_DESTROYED, + ("%s() of destroyed mutex %p", __func__, m)); + KASSERT(LOCK_CLASS(&m->lock_object) == &lock_class_mtx_sleep, + ("%s() not a sleep mutex %p (%s)", __func__, m, + m->lock_object.lo_name)); + KASSERT(!mtx_owned(m), ("%s() waiting on myself on lock %p (%s)", __func__, m, + m->lock_object.lo_name)); + + for (;;) { + v = atomic_load_acq_ptr(&m->mtx_lock); + if (v == MTX_UNOWNED) { + break; + } + owner = lv_mtx_owner(v); + if (!TD_IS_RUNNING(owner)) { + mtx_lock(m); + mtx_unlock(m); + break; + } + cpu_spinwait(); + } +} + #ifdef DDB void db_show_mtx(const struct lock_object *lock) diff --git a/sys/sys/mutex.h b/sys/sys/mutex.h index caacf2ef4274..35257ce97038 100644 --- a/sys/sys/mutex.h +++ b/sys/sys/mutex.h @@ -106,6 +106,7 @@ void __mtx_unlock_sleep(volatile uintptr_t *c, uintptr_t v, int opts, void __mtx_lock_sleep(volatile uintptr_t *c, uintptr_t v); void __mtx_unlock_sleep(volatile uintptr_t *c, uintptr_t v); #endif +void mtx_wait_unlocked(struct mtx *m); #ifdef SMP #if LOCK_DEBUG > 0 From 6e10434c0235f65b530de51cc636855bcada1cee Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 4 Aug 2020 23:04:29 +0000 Subject: [PATCH 081/141] cache: add cache_purge_vgone cache_purge locklessly checks whether the vnode at hand has any namecache entries. This can race with a concurrent purge which managed to remove the last entry, but may not be done touching the vnode. Make sure we observe the relevant vnode lock as not taken before proceeding with vgone. Paired with the fact that doomed vnodes cannnot receive entries this restores the invariant that there are no namecache-related writing users past cache_purge in vgone. Reported by: pho --- sys/kern/vfs_cache.c | 58 ++++++++++++++++++++++++++++++++++++++------ sys/kern/vfs_subr.c | 2 +- sys/sys/vnode.h | 1 + 3 files changed, 52 insertions(+), 9 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 5e75103cdf5f..5bdcff8aa35f 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -2138,22 +2138,17 @@ cache_changesize(u_long newmaxvnodes) /* * Invalidate all entries from and to a particular vnode. */ -void -cache_purge(struct vnode *vp) +static void +cache_purge_impl(struct vnode *vp) { TAILQ_HEAD(, namecache) ncps; struct namecache *ncp, *nnp; struct mtx *vlp, *vlp2; - CTR1(KTR_VFS, "cache_purge(%p)", vp); - SDT_PROBE1(vfs, namecache, purge, done, vp); - if (LIST_EMPTY(&vp->v_cache_src) && TAILQ_EMPTY(&vp->v_cache_dst) && - vp->v_cache_dd == NULL) - return; TAILQ_INIT(&ncps); vlp = VP2VNODELOCK(vp); vlp2 = NULL; - mtx_lock(vlp); + mtx_assert(vlp, MA_OWNED); retry: while (!LIST_EMPTY(&vp->v_cache_src)) { ncp = LIST_FIRST(&vp->v_cache_src); @@ -2184,6 +2179,53 @@ cache_purge(struct vnode *vp) } } +void +cache_purge(struct vnode *vp) +{ + struct mtx *vlp; + + SDT_PROBE1(vfs, namecache, purge, done, vp); + if (LIST_EMPTY(&vp->v_cache_src) && TAILQ_EMPTY(&vp->v_cache_dst) && + vp->v_cache_dd == NULL) + return; + vlp = VP2VNODELOCK(vp); + mtx_lock(vlp); + cache_purge_impl(vp); +} + +/* + * Only to be used by vgone. + */ +void +cache_purge_vgone(struct vnode *vp) +{ + struct mtx *vlp; + + VNPASS(VN_IS_DOOMED(vp), vp); + vlp = VP2VNODELOCK(vp); + if (!(LIST_EMPTY(&vp->v_cache_src) && TAILQ_EMPTY(&vp->v_cache_dst) && + vp->v_cache_dd == NULL)) { + mtx_lock(vlp); + cache_purge_impl(vp); + mtx_assert(vlp, MA_NOTOWNED); + return; + } + + /* + * All the NULL pointer state we found above may be transient. + * Serialize against a possible thread doing cache_purge. + */ + mtx_wait_unlocked(vlp); + if (!(LIST_EMPTY(&vp->v_cache_src) && TAILQ_EMPTY(&vp->v_cache_dst) && + vp->v_cache_dd == NULL)) { + mtx_lock(vlp); + cache_purge_impl(vp); + mtx_assert(vlp, MA_NOTOWNED); + return; + } + return; +} + /* * Invalidate all negative entries for a particular directory vnode. */ diff --git a/sys/kern/vfs_subr.c b/sys/kern/vfs_subr.c index a34f83c09860..0ce9dd785213 100644 --- a/sys/kern/vfs_subr.c +++ b/sys/kern/vfs_subr.c @@ -4146,7 +4146,7 @@ vgonel(struct vnode *vp) * Delete from old mount point vnode list. */ delmntque(vp); - cache_purge(vp); + cache_purge_vgone(vp); /* * Done with purge, reset to the standard lock and invalidate * the vnode. diff --git a/sys/sys/vnode.h b/sys/sys/vnode.h index bed5c0f4086f..f754b2b52724 100644 --- a/sys/sys/vnode.h +++ b/sys/sys/vnode.h @@ -638,6 +638,7 @@ int cache_lookup(struct vnode *dvp, struct vnode **vpp, struct componentname *cnp, struct timespec *tsp, int *ticksp); void cache_vnode_init(struct vnode *vp); void cache_purge(struct vnode *vp); +void cache_purge_vgone(struct vnode *vp); void cache_purge_negative(struct vnode *vp); void cache_purgevfs(struct mount *mp, bool force); int change_dir(struct vnode *vp, struct thread *td); From b403aa126e47c8702138ab66c1a8918cbc7a6c4b Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 4 Aug 2020 23:07:00 +0000 Subject: [PATCH 082/141] cache: add NCF_WIP flag This allows making half-constructed entries visible to the lockless lookup, which now can check for either "not yet fully constructed" and "no longer valid" state. This will be used for .. lookup. --- sys/kern/vfs_cache.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 5bdcff8aa35f..721779df7aef 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -162,6 +162,7 @@ struct namecache_ts { #define NCF_DVDROP 0x10 #define NCF_NEGATIVE 0x20 #define NCF_INVALID 0x40 +#define NCF_WIP 0x80 /* * Flags in negstate.neg_flag @@ -179,22 +180,22 @@ cache_ncp_invalidate(struct namecache *ncp) KASSERT((ncp->nc_flag & NCF_INVALID) == 0, ("%s: entry %p already invalid", __func__, ncp)); - ncp->nc_flag |= NCF_INVALID; + atomic_store_char(&ncp->nc_flag, ncp->nc_flag | NCF_INVALID); atomic_thread_fence_rel(); } /* - * Verify validity of an entry. + * Check whether the entry can be safely used. * * All places which elide locks are supposed to call this after they are * done with reading from an entry. */ static bool -cache_ncp_invalid(struct namecache *ncp) +cache_ncp_canuse(struct namecache *ncp) { atomic_thread_fence_acq(); - return ((ncp->nc_flag & NCF_INVALID) != 0); + return ((atomic_load_char(&ncp->nc_flag) & (NCF_INVALID | NCF_WIP)) == 0); } /* @@ -1506,7 +1507,7 @@ cache_lookup(struct vnode *dvp, struct vnode **vpp, struct componentname *cnp, VOP_UNLOCK(dvp); } if (doing_smr) { - if (cache_ncp_invalid(ncp)) { + if (!cache_ncp_canuse(ncp)) { vfs_smr_exit(); *vpp = NULL; goto retry; @@ -1560,7 +1561,7 @@ cache_lookup(struct vnode *dvp, struct vnode **vpp, struct componentname *cnp, */ negstate = NCP2NEGSTATE(ncp); if ((negstate->neg_flag & NEG_HOT) == 0 || - cache_ncp_invalid(ncp)) { + !cache_ncp_canuse(ncp)) { vfs_smr_exit(); doing_smr = false; goto retry_hashed; @@ -1884,7 +1885,7 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp, * namecache entry as possible before acquiring the lock. */ ncp = cache_alloc(cnp->cn_namelen, tsp != NULL); - ncp->nc_flag = flag; + ncp->nc_flag = flag | NCF_WIP; ncp->nc_vp = vp; if (vp == NULL) cache_negative_init(ncp); @@ -1987,13 +1988,19 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp, ncp->nc_name); } - atomic_thread_fence_rel(); /* * Insert the new namecache entry into the appropriate chain * within the cache entries table. */ CK_LIST_INSERT_HEAD(ncpp, ncp, nc_hash); + atomic_thread_fence_rel(); + /* + * Mark the entry as fully constructed. + * It is immutable past this point until its removal. + */ + atomic_store_char(&ncp->nc_flag, ncp->nc_flag & ~NCF_WIP); + cache_enter_unlock(&cel); if (numneg * ncnegfactor > lnumcache) cache_negative_zap_one(); @@ -3197,7 +3204,7 @@ cache_fplookup_negative_promote(struct cache_fpl *fpl, struct namecache *oncp, goto out_abort; } - if (__predict_false(cache_ncp_invalid(ncp))) { + if (__predict_false(!cache_ncp_canuse(ncp))) { goto out_abort; } @@ -3458,7 +3465,7 @@ cache_fplookup_next(struct cache_fpl *fpl) if ((nc_flag & NCF_NEGATIVE) != 0) { negstate = NCP2NEGSTATE(ncp); neg_hot = ((negstate->neg_flag & NEG_HOT) != 0); - if (__predict_false(cache_ncp_invalid(ncp))) { + if (__predict_false(!cache_ncp_canuse(ncp))) { return (cache_fpl_partial(fpl)); } if (__predict_false((nc_flag & NCF_WHITE) != 0)) { @@ -3474,7 +3481,7 @@ cache_fplookup_next(struct cache_fpl *fpl) return (cache_fpl_handled(fpl, ENOENT)); } - if (__predict_false(cache_ncp_invalid(ncp))) { + if (__predict_false(!cache_ncp_canuse(ncp))) { return (cache_fpl_partial(fpl)); } From db99ec5656363acc0bd3df133f57639fb839bf5f Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 4 Aug 2020 23:07:42 +0000 Subject: [PATCH 083/141] vfs: support lockless dotdot lookup Tested by: pho --- sys/kern/vfs_cache.c | 124 +++++++++++++++++++++++++++++++++++++------ sys/kern/vfs_subr.c | 29 ++++++++-- sys/sys/vnode.h | 2 + 3 files changed, 134 insertions(+), 21 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 721779df7aef..a27f475f6615 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -51,6 +51,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include @@ -957,16 +958,22 @@ cache_zap_locked(struct namecache *ncp) SDT_PROBE3(vfs, namecache, zap, done, ncp->nc_dvp, ncp->nc_name, ncp->nc_vp); TAILQ_REMOVE(&ncp->nc_vp->v_cache_dst, ncp, nc_dst); - if (ncp == ncp->nc_vp->v_cache_dd) + if (ncp == ncp->nc_vp->v_cache_dd) { + vn_seqc_write_begin_unheld(ncp->nc_vp); ncp->nc_vp->v_cache_dd = NULL; + vn_seqc_write_end(ncp->nc_vp); + } } else { SDT_PROBE2(vfs, namecache, zap_negative, done, ncp->nc_dvp, ncp->nc_name); cache_negative_remove(ncp); } if (ncp->nc_flag & NCF_ISDOTDOT) { - if (ncp == ncp->nc_dvp->v_cache_dd) + if (ncp == ncp->nc_dvp->v_cache_dd) { + vn_seqc_write_begin_unheld(ncp->nc_dvp); ncp->nc_dvp->v_cache_dd = NULL; + vn_seqc_write_end(ncp->nc_dvp); + } } else { LIST_REMOVE(ncp, nc_src); if (LIST_EMPTY(&ncp->nc_dvp->v_cache_src)) { @@ -1306,7 +1313,9 @@ cache_lookup_nomakeentry(struct vnode *dvp, struct vnode **vpp, mtx_unlock(dvlp2); cache_free(ncp); } else { + vn_seqc_write_begin(dvp); dvp->v_cache_dd = NULL; + vn_seqc_write_end(dvp); mtx_unlock(dvlp); if (dvlp2 != NULL) mtx_unlock(dvlp2); @@ -1817,6 +1826,7 @@ cache_enter_dotdot_prep(struct vnode *dvp, struct vnode *vp, cache_celockstate_init(&cel); hash = cache_get_hash(cnp->cn_nameptr, len, dvp); cache_enter_lock_dd(&cel, dvp, vp, hash); + vn_seqc_write_begin(dvp); ncp = dvp->v_cache_dd; if (ncp != NULL && (ncp->nc_flag & NCF_ISDOTDOT)) { KASSERT(ncp->nc_dvp == dvp, ("wrong isdotdot parent")); @@ -1825,6 +1835,7 @@ cache_enter_dotdot_prep(struct vnode *dvp, struct vnode *vp, ncp = NULL; } dvp->v_cache_dd = NULL; + vn_seqc_write_end(dvp); cache_enter_unlock(&cel); cache_free(ncp); } @@ -1939,7 +1950,9 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp, goto out_unlock_free; KASSERT(vp == NULL || vp->v_type == VDIR, ("wrong vnode type %p", vp)); + vn_seqc_write_begin(dvp); dvp->v_cache_dd = ncp; + vn_seqc_write_end(dvp); } if (vp != NULL) { @@ -1950,6 +1963,7 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp, * directory name in it and the name ".." for the * directory's parent. */ + vn_seqc_write_begin(vp); if ((ndd = vp->v_cache_dd) != NULL) { if ((ndd->nc_flag & NCF_ISDOTDOT) != 0) cache_zap_locked(ndd); @@ -1957,9 +1971,14 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp, ndd = NULL; } vp->v_cache_dd = ncp; + vn_seqc_write_end(vp); } } else { - vp->v_cache_dd = NULL; + if (vp->v_cache_dd != NULL) { + vn_seqc_write_begin(vp); + vp->v_cache_dd = NULL; + vn_seqc_write_end(vp); + } } } @@ -3425,6 +3444,75 @@ cache_fplookup_dot(struct cache_fpl *fpl) return (0); } +static int __noinline +cache_fplookup_dotdot(struct cache_fpl *fpl) +{ + struct nameidata *ndp; + struct componentname *cnp; + struct namecache *ncp; + struct vnode *dvp; + struct prison *pr; + u_char nc_flag; + + ndp = fpl->ndp; + cnp = fpl->cnp; + dvp = fpl->dvp; + + /* + * XXX this is racy the same way regular lookup is + */ + for (pr = cnp->cn_cred->cr_prison; pr != NULL; + pr = pr->pr_parent) + if (dvp == pr->pr_root) + break; + + if (dvp == ndp->ni_rootdir || + dvp == ndp->ni_topdir || + dvp == rootvnode || + pr != NULL) { + fpl->tvp = dvp; + fpl->tvp_seqc = vn_seqc_read_any(dvp); + if (seqc_in_modify(fpl->tvp_seqc)) { + return (cache_fpl_aborted(fpl)); + } + return (0); + } + + if ((dvp->v_vflag & VV_ROOT) != 0) { + /* + * TODO + * The opposite of climb mount is needed here. + */ + return (cache_fpl_aborted(fpl)); + } + + ncp = atomic_load_ptr(&dvp->v_cache_dd); + if (ncp == NULL) { + return (cache_fpl_aborted(fpl)); + } + + nc_flag = atomic_load_char(&ncp->nc_flag); + if ((nc_flag & NCF_ISDOTDOT) != 0) { + if ((nc_flag & NCF_NEGATIVE) != 0) + return (cache_fpl_aborted(fpl)); + fpl->tvp = ncp->nc_vp; + } else { + fpl->tvp = ncp->nc_dvp; + } + + if (__predict_false(!cache_ncp_canuse(ncp))) { + return (cache_fpl_aborted(fpl)); + } + + fpl->tvp_seqc = vn_seqc_read_any(fpl->tvp); + if (seqc_in_modify(fpl->tvp_seqc)) { + return (cache_fpl_partial(fpl)); + } + + counter_u64_add(dotdothits, 1); + return (0); +} + static int cache_fplookup_next(struct cache_fpl *fpl) { @@ -3782,11 +3870,6 @@ cache_fplookup_impl(struct vnode *dvp, struct cache_fpl *fpl) break; } - if (cnp->cn_flags & ISDOTDOT) { - error = cache_fpl_partial(fpl); - break; - } - VNPASS(cache_fplookup_vnode_supported(fpl->dvp), fpl->dvp); error = VOP_FPLOOKUP_VEXEC(fpl->dvp, cnp->cn_cred, cnp->cn_thread); @@ -3795,18 +3878,25 @@ cache_fplookup_impl(struct vnode *dvp, struct cache_fpl *fpl) break; } - error = cache_fplookup_next(fpl); - if (__predict_false(error != 0)) { - break; - } - - VNPASS(!seqc_in_modify(fpl->tvp_seqc), fpl->tvp); - - if (cache_fplookup_need_climb_mount(fpl)) { - error = cache_fplookup_climb_mount(fpl); + if (__predict_false(cnp->cn_flags & ISDOTDOT)) { + error = cache_fplookup_dotdot(fpl); if (__predict_false(error != 0)) { break; } + } else { + error = cache_fplookup_next(fpl); + if (__predict_false(error != 0)) { + break; + } + + VNPASS(!seqc_in_modify(fpl->tvp_seqc), fpl->tvp); + + if (cache_fplookup_need_climb_mount(fpl)) { + error = cache_fplookup_climb_mount(fpl); + if (__predict_false(error != 0)) { + break; + } + } } VNPASS(!seqc_in_modify(fpl->tvp_seqc), fpl->tvp); diff --git a/sys/kern/vfs_subr.c b/sys/kern/vfs_subr.c index 0ce9dd785213..d13150c2c7cf 100644 --- a/sys/kern/vfs_subr.c +++ b/sys/kern/vfs_subr.c @@ -6881,16 +6881,28 @@ vn_dir_check_exec(struct vnode *vp, struct componentname *cnp) return (VOP_ACCESS(vp, VEXEC, cnp->cn_cred, cnp->cn_thread)); } +/* + * Do not use this variant unless you have means other than the hold count + * to prevent the vnode from getting freed. + */ +void +vn_seqc_write_begin_unheld_locked(struct vnode *vp) +{ + + ASSERT_VI_LOCKED(vp, __func__); + VNPASS(vp->v_seqc_users >= 0, vp); + vp->v_seqc_users++; + if (vp->v_seqc_users == 1) + seqc_sleepable_write_begin(&vp->v_seqc); +} + void vn_seqc_write_begin_locked(struct vnode *vp) { ASSERT_VI_LOCKED(vp, __func__); VNPASS(vp->v_holdcnt > 0, vp); - VNPASS(vp->v_seqc_users >= 0, vp); - vp->v_seqc_users++; - if (vp->v_seqc_users == 1) - seqc_sleepable_write_begin(&vp->v_seqc); + vn_seqc_write_begin_unheld_locked(vp); } void @@ -6902,6 +6914,15 @@ vn_seqc_write_begin(struct vnode *vp) VI_UNLOCK(vp); } +void +vn_seqc_write_begin_unheld(struct vnode *vp) +{ + + VI_LOCK(vp); + vn_seqc_write_begin_unheld_locked(vp); + VI_UNLOCK(vp); +} + void vn_seqc_write_end_locked(struct vnode *vp) { diff --git a/sys/sys/vnode.h b/sys/sys/vnode.h index f754b2b52724..398fb088d7f1 100644 --- a/sys/sys/vnode.h +++ b/sys/sys/vnode.h @@ -764,6 +764,8 @@ int vn_io_fault_uiomove(char *data, int xfersize, struct uio *uio); int vn_io_fault_pgmove(vm_page_t ma[], vm_offset_t offset, int xfersize, struct uio *uio); +void vn_seqc_write_begin_unheld_locked(struct vnode *vp); +void vn_seqc_write_begin_unheld(struct vnode *vp); void vn_seqc_write_begin_locked(struct vnode *vp); void vn_seqc_write_begin(struct vnode *vp); void vn_seqc_write_end_locked(struct vnode *vp); From e5e10c82ec5768a168d2b62251ddbe9f3c45de0f Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Tue, 4 Aug 2020 23:09:15 +0000 Subject: [PATCH 084/141] ufs: only pass LK_ADAPTIVE if LK_NODDLKTREAT is set This restores the pre-adaptive spinning state for SU which livelocks otherwise. Note this is a bug in SU. Reported by: pho --- sys/ufs/ffs/ffs_vnops.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/sys/ufs/ffs/ffs_vnops.c b/sys/ufs/ffs/ffs_vnops.c index c363f4bbb094..6e3cdfeb7d7d 100644 --- a/sys/ufs/ffs/ffs_vnops.c +++ b/sys/ufs/ffs/ffs_vnops.c @@ -445,7 +445,13 @@ ffs_lock(ap) struct lock *lkp; int result; - ap->a_flags |= LK_ADAPTIVE; + /* + * Adaptive spinning mixed with SU leads to trouble. use a giant hammer + * and only use it when LK_NODDLKTREAT is set. Currently this means it + * is only used during path lookup. + */ + if ((ap->a_flags & LK_NODDLKTREAT) != 0) + ap->a_flags |= LK_ADAPTIVE; switch (ap->a_flags & LK_TYPE_MASK) { case LK_SHARED: case LK_UPGRADE: @@ -483,7 +489,11 @@ ffs_lock(ap) } return (result); #else - ap->a_flags |= LK_ADAPTIVE; + /* + * See above for an explanation. + */ + if ((ap->a_flags & LK_NODDLKTREAT) != 0) + ap->a_flags |= LK_ADAPTIVE; return (VOP_LOCK1_APV(&ufs_vnodeops, ap)); #endif } From 096761378ce49cd7c94e1f1bc7a84babfb36c765 Mon Sep 17 00:00:00 2001 From: Li-Wen Hsu Date: Wed, 5 Aug 2020 05:58:25 +0000 Subject: [PATCH 085/141] Appease gcc's -Wparentheses (and -Werror) Sponsored by: The FreeBSD Foundation --- sys/dev/safexcel/safexcel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/dev/safexcel/safexcel.c b/sys/dev/safexcel/safexcel.c index 2f7f2c04cc8e..2ed6bed64136 100644 --- a/sys/dev/safexcel/safexcel.c +++ b/sys/dev/safexcel/safexcel.c @@ -1635,7 +1635,7 @@ safexcel_instr_ccm(struct safexcel_request *req, struct safexcel_instr *instr, b0 = (uint8_t *)instr; memset(b0, 0, blen); b0[0] = - L - 1 | /* payload length size */ + (L - 1) | /* payload length size */ ((CCM_CBC_MAX_DIGEST_LEN - 2) / 2) << 3 /* digest length */ | (crp->crp_aad_length > 0 ? 1 : 0) << 6 /* AAD present bit */; memcpy(&b0[1], req->iv, AES_CCM_IV_LEN); From 9c9f7b7c95061590fb2395f65930915357cd060d Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 07:28:51 +0000 Subject: [PATCH 086/141] vfs: prefill nameidata with garbage on debug kernels --- sys/sys/namei.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/sys/sys/namei.h b/sys/sys/namei.h index 05a5239b36e3..0f49ef684546 100644 --- a/sys/sys/namei.h +++ b/sys/sys/namei.h @@ -196,11 +196,21 @@ int cache_fplookup(struct nameidata *ndp, enum cache_fpl_status *status, #define NDINIT_ATVP(ndp, op, flags, segflg, namep, vp, td) \ NDINIT_ALL(ndp, op, flags, segflg, namep, AT_FDCWD, vp, &cap_no_rights, td) +/* + * Note the constant pattern may *hide* bugs. + */ +#ifdef INVARIANTS +#define NDINIT_PREFILL(arg) memset(arg, 0xff, sizeof(*arg)) +#else +#define NDINIT_PREFILL(arg) do { } while (0) +#endif + #define NDINIT_ALL(ndp, op, flags, segflg, namep, dirfd, startdir, rightsp, td) \ do { \ struct nameidata *_ndp = (ndp); \ cap_rights_t *_rightsp = (rightsp); \ MPASS(_rightsp != NULL); \ + NDINIT_PREFILL(_ndp); \ _ndp->ni_cnd.cn_nameiop = op; \ _ndp->ni_cnd.cn_flags = flags; \ _ndp->ni_segflg = segflg; \ From 27c4618df51d5aa72414455b055bceeaf8eb6490 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 07:30:17 +0000 Subject: [PATCH 087/141] cache: stop messing with cn_flags This removes flag setting/unsetting carried over from regular lookup. Flags still get for compatibility when falling back. Note .. and . handling can get partially folded together. --- sys/kern/vfs_cache.c | 56 ++++++++++++++++++++++++++++++-------------- 1 file changed, 39 insertions(+), 17 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index a27f475f6615..de1ff2b4e6e7 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -3098,6 +3098,29 @@ cache_fpl_handled_impl(struct cache_fpl *fpl, int error, int line) (LOCKLEAF | LOCKPARENT | WANTPARENT | FOLLOW | LOCKSHARED | SAVENAME | \ ISOPEN | NOMACCHECK | AUDITVNODE1 | AUDITVNODE2) +#define CACHE_FPL_INTERNAL_CN_FLAGS \ + (ISDOTDOT | MAKEENTRY | ISLASTCN) + +_Static_assert((CACHE_FPL_SUPPORTED_CN_FLAGS & CACHE_FPL_INTERNAL_CN_FLAGS) == 0, + "supported and internal flags overlap"); + +static bool +cache_fpl_islastcn(struct nameidata *ndp) +{ + + return (*ndp->ni_next == 0); +} + +static bool +cache_fpl_isdotdot(struct componentname *cnp) +{ + + if (cnp->cn_namelen == 2 && + cnp->cn_nameptr[1] == '.' && cnp->cn_nameptr[0] == '.') + return (true); + return (false); +} + static bool cache_can_fplookup(struct cache_fpl *fpl) { @@ -3253,15 +3276,17 @@ cache_fplookup_negative_promote(struct cache_fpl *fpl, struct namecache *oncp, /* * The target vnode is not supported, prepare for the slow path to take over. */ -static int +static int __noinline cache_fplookup_partial_setup(struct cache_fpl *fpl) { + struct nameidata *ndp; struct componentname *cnp; enum vgetstate dvs; struct vnode *dvp; struct pwd *pwd; seqc_t dvp_seqc; + ndp = fpl->ndp; cnp = fpl->cnp; dvp = fpl->dvp; dvp_seqc = fpl->dvp_seqc; @@ -3287,7 +3312,14 @@ cache_fplookup_partial_setup(struct cache_fpl *fpl) return (cache_fpl_aborted(fpl)); } - fpl->ndp->ni_startdir = dvp; + cache_fpl_restore(fpl, &fpl->snd); + + ndp->ni_startdir = dvp; + cnp->cn_flags |= MAKEENTRY; + if (cache_fpl_islastcn(ndp)) + cnp->cn_flags |= ISLASTCN; + if (cache_fpl_isdotdot(cnp)) + cnp->cn_flags |= ISDOTDOT; return (0); } @@ -3763,18 +3795,6 @@ cache_fplookup_parse(struct cache_fpl *fpl) } ndp->ni_next = cp; - cnp->cn_flags |= MAKEENTRY; - - if (cnp->cn_namelen == 2 && - cnp->cn_nameptr[1] == '.' && cnp->cn_nameptr[0] == '.') - cnp->cn_flags |= ISDOTDOT; - else - cnp->cn_flags &= ~ISDOTDOT; - if (*ndp->ni_next == 0) - cnp->cn_flags |= ISLASTCN; - else - cnp->cn_flags &= ~ISLASTCN; - /* * Check for degenerate name (e.g. / or "") * which is a way of talking about a directory, @@ -3878,7 +3898,7 @@ cache_fplookup_impl(struct vnode *dvp, struct cache_fpl *fpl) break; } - if (__predict_false(cnp->cn_flags & ISDOTDOT)) { + if (__predict_false(cache_fpl_isdotdot(cnp))) { error = cache_fplookup_dotdot(fpl); if (__predict_false(error != 0)) { break; @@ -3901,7 +3921,7 @@ cache_fplookup_impl(struct vnode *dvp, struct cache_fpl *fpl) VNPASS(!seqc_in_modify(fpl->tvp_seqc), fpl->tvp); - if (cnp->cn_flags & ISLASTCN) { + if (cache_fpl_islastcn(ndp)) { error = cache_fplookup_final(fpl); break; } @@ -4082,7 +4102,9 @@ cache_fplookup(struct nameidata *ndp, enum cache_fpl_status *status, break; case CACHE_FPL_STATUS_PARTIAL: *pwdp = fpl.pwd; - cache_fpl_restore(&fpl, &fpl.snd); + /* + * Status restored by cache_fplookup_partial_setup. + */ break; case CACHE_FPL_STATUS_ABORTED: cache_fpl_restore(&fpl, &orig); From 8ccf01e0e2167607ad40b3c2c517871ed6edd607 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 07:30:57 +0000 Subject: [PATCH 088/141] cache: stop messing with cn_lkflags See r363882. --- sys/kern/vfs_cache.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index de1ff2b4e6e7..52ffebefe06b 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -3330,14 +3330,17 @@ cache_fplookup_final_child(struct cache_fpl *fpl, enum vgetstate tvs) struct componentname *cnp; struct vnode *tvp; seqc_t tvp_seqc; - int error; + int error, lkflags; cnp = fpl->cnp; tvp = fpl->tvp; tvp_seqc = fpl->tvp_seqc; if ((cnp->cn_flags & LOCKLEAF) != 0) { - error = vget_finish(tvp, cnp->cn_lkflags, tvs); + lkflags = LK_SHARED; + if ((cnp->cn_flags & LOCKSHARED) == 0) + lkflags = LK_EXCLUSIVE; + error = vget_finish(tvp, lkflags, tvs); if (error != 0) { return (cache_fpl_aborted(fpl)); } @@ -3864,9 +3867,6 @@ cache_fplookup_impl(struct vnode *dvp, struct cache_fpl *fpl) ndp = fpl->ndp; ndp->ni_lcf = 0; cnp = fpl->cnp; - cnp->cn_lkflags = LK_SHARED; - if ((cnp->cn_flags & LOCKSHARED) == 0) - cnp->cn_lkflags = LK_EXCLUSIVE; cache_fpl_checkpoint(fpl, &fpl->snd); From 2840f07d4f581c8cfafbfb003ea37e004ab865c6 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 07:32:26 +0000 Subject: [PATCH 089/141] cache: cleanup lockless entry point - remove spurious bzero - assert ni_lcf, it has to be set by namei by this point --- sys/kern/vfs_cache.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 52ffebefe06b..a12da7d35635 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -3033,6 +3033,12 @@ cache_fpl_restore(struct cache_fpl *fpl, struct nameidata_saved *snd) #define cache_fpl_smr_assert_not_entered(fpl) do { } while (0) #endif +#define cache_fpl_smr_enter_initial(fpl) ({ \ + struct cache_fpl *_fpl = (fpl); \ + vfs_smr_enter(); \ + _fpl->in_smr = true; \ +}) + #define cache_fpl_smr_enter(fpl) ({ \ struct cache_fpl *_fpl = (fpl); \ MPASS(_fpl->in_smr == false); \ @@ -3865,7 +3871,6 @@ cache_fplookup_impl(struct vnode *dvp, struct cache_fpl *fpl) error = CACHE_FPL_FAILED; ndp = fpl->ndp; - ndp->ni_lcf = 0; cnp = fpl->cnp; cache_fpl_checkpoint(fpl, &fpl->snd); @@ -4055,8 +4060,8 @@ cache_fplookup(struct nameidata *ndp, enum cache_fpl_status *status, struct nameidata_saved orig; int error; - *status = CACHE_FPL_STATUS_UNSET; - bzero(&fpl, sizeof(fpl)); + MPASS(ndp->ni_lcf == 0); + fpl.status = CACHE_FPL_STATUS_UNSET; fpl.ndp = ndp; fpl.cnp = &ndp->ni_cnd; @@ -4070,7 +4075,7 @@ cache_fplookup(struct nameidata *ndp, enum cache_fpl_status *status, cache_fpl_checkpoint(&fpl, &orig); - cache_fpl_smr_enter(&fpl); + cache_fpl_smr_enter_initial(&fpl); pwd = pwd_get_smr(); fpl.pwd = pwd; ndp->ni_rootdir = pwd->pwd_rdir; From 158ab70c249a73da0eabea685cffb2615cabed99 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 07:33:39 +0000 Subject: [PATCH 090/141] vfs: tidy up namei entry point - predict for string copy errors - reshuffle inititalistion of vars which are not needed --- sys/kern/vfs_lookup.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/sys/kern/vfs_lookup.c b/sys/kern/vfs_lookup.c index 2b37bda9ee3b..54ae088f4b74 100644 --- a/sys/kern/vfs_lookup.c +++ b/sys/kern/vfs_lookup.c @@ -297,6 +297,7 @@ namei_setup(struct nameidata *ndp, struct vnode **dpp, struct pwd **pwdp) startdir_used = false; *pwdp = NULL; + *dpp = NULL; #ifdef CAPABILITY_MODE /* @@ -470,7 +471,6 @@ namei(struct nameidata *ndp) struct iovec aiov; /* uio for reading symbolic links */ struct componentname *cnp; struct thread *td; - struct proc *p; struct pwd *pwd; struct uio auio; int error, linklen; @@ -478,23 +478,19 @@ namei(struct nameidata *ndp) cnp = &ndp->ni_cnd; td = cnp->cn_thread; - p = td->td_proc; ndp->ni_cnd.cn_cred = ndp->ni_cnd.cn_thread->td_ucred; - KASSERT(cnp->cn_cred && p, ("namei: bad cred/proc")); + KASSERT(cnp->cn_cred && td->td_proc, ("namei: bad cred/proc")); KASSERT((cnp->cn_nameiop & (~OPMASK)) == 0, ("namei: nameiop contaminated with flags")); KASSERT((cnp->cn_flags & OPMASK) == 0, ("namei: flags contaminated with nameiops")); MPASS(ndp->ni_startdir == NULL || ndp->ni_startdir->v_type == VDIR || ndp->ni_startdir->v_type == VBAD); - TAILQ_INIT(&ndp->ni_cap_tracker); - ndp->ni_lcf = 0; - ndp->ni_loopcnt = 0; - dp = NULL; /* We will set this ourselves if we need it. */ cnp->cn_flags &= ~TRAILINGSLASH; + ndp->ni_lcf = 0; ndp->ni_vp = NULL; /* @@ -510,17 +506,15 @@ namei(struct nameidata *ndp) error = copyinstr(ndp->ni_dirp, cnp->cn_pnbuf, MAXPATHLEN, &ndp->ni_pathlen); - if (error != 0) { + if (__predict_false(error != 0)) { namei_cleanup_cnp(cnp); return (error); } - cnp->cn_nameptr = cnp->cn_pnbuf; - /* * Don't allow empty pathnames. */ - if (*cnp->cn_pnbuf == '\0') { + if (__predict_false(*cnp->cn_pnbuf == '\0')) { namei_cleanup_cnp(cnp); return (ENOENT); } @@ -533,6 +527,8 @@ namei(struct nameidata *ndp) } #endif + cnp->cn_nameptr = cnp->cn_pnbuf; + /* * First try looking up the target without locking any vnodes. * @@ -546,9 +542,11 @@ namei(struct nameidata *ndp) case CACHE_FPL_STATUS_HANDLED: return (error); case CACHE_FPL_STATUS_PARTIAL: + TAILQ_INIT(&ndp->ni_cap_tracker); dp = ndp->ni_startdir; break; case CACHE_FPL_STATUS_ABORTED: + TAILQ_INIT(&ndp->ni_cap_tracker); error = namei_setup(ndp, &dp, &pwd); if (error != 0) { namei_cleanup_cnp(cnp); @@ -557,6 +555,8 @@ namei(struct nameidata *ndp) break; } + ndp->ni_loopcnt = 0; + /* * Locked lookup. */ From 18f67bc413e8a4e6b313c023e8612603f1ea17c0 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 07:34:45 +0000 Subject: [PATCH 091/141] vfs: add a cheaper entry for mac_vnode_check_access --- sys/security/mac/mac_framework.c | 3 +++ sys/security/mac/mac_framework.h | 14 +++++++++++++- sys/security/mac/mac_vfs.c | 2 +- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/sys/security/mac/mac_framework.c b/sys/security/mac/mac_framework.c index 41c0779fa78e..60431b020782 100644 --- a/sys/security/mac/mac_framework.c +++ b/sys/security/mac/mac_framework.c @@ -140,6 +140,7 @@ FPFLAG(vnode_check_write); FPFLAG(vnode_check_mmap); FPFLAG_RARE(vnode_check_poll); FPFLAG_RARE(vnode_check_rename_from); +FPFLAG_RARE(vnode_check_access); #undef FPFLAG #undef FPFLAG_RARE @@ -430,6 +431,8 @@ struct mac_policy_fastpath_elem mac_policy_fastpath_array[] = { .flag = &mac_vnode_check_poll_fp_flag }, { .offset = FPO(vnode_check_rename_from), .flag = &mac_vnode_check_rename_from_fp_flag }, + { .offset = FPO(vnode_check_access), + .flag = &mac_vnode_check_access_fp_flag }, }; static void diff --git a/sys/security/mac/mac_framework.h b/sys/security/mac/mac_framework.h index 6ae634bd2dfe..70a7aad44757 100644 --- a/sys/security/mac/mac_framework.h +++ b/sys/security/mac/mac_framework.h @@ -406,8 +406,20 @@ void mac_vnode_assert_locked(struct vnode *vp, const char *func); int mac_vnode_associate_extattr(struct mount *mp, struct vnode *vp); void mac_vnode_associate_singlelabel(struct mount *mp, struct vnode *vp); -int mac_vnode_check_access(struct ucred *cred, struct vnode *vp, +int mac_vnode_check_access_impl(struct ucred *cred, struct vnode *dvp, accmode_t accmode); +extern bool mac_vnode_check_access_fp_flag; +#define mac_vnode_check_access_enabled() __predict_false(mac_vnode_check_access_fp_flag) +static inline int +mac_vnode_check_access(struct ucred *cred, struct vnode *dvp, + accmode_t accmode) +{ + + mac_vnode_assert_locked(dvp, "mac_vnode_check_access"); + if (mac_vnode_check_access_enabled()) + return (mac_vnode_check_access_impl(cred, dvp, accmode)); + return (0); +} int mac_vnode_check_chdir(struct ucred *cred, struct vnode *dvp); int mac_vnode_check_chroot(struct ucred *cred, struct vnode *dvp); int mac_vnode_check_create(struct ucred *cred, struct vnode *dvp, diff --git a/sys/security/mac/mac_vfs.c b/sys/security/mac/mac_vfs.c index 7b8489d48103..ec492ba243e6 100644 --- a/sys/security/mac/mac_vfs.c +++ b/sys/security/mac/mac_vfs.c @@ -372,7 +372,7 @@ MAC_CHECK_PROBE_DEFINE3(vnode_check_access, "struct ucred *", "struct vnode *", "accmode_t"); int -mac_vnode_check_access(struct ucred *cred, struct vnode *vp, accmode_t accmode) +mac_vnode_check_access_impl(struct ucred *cred, struct vnode *vp, accmode_t accmode) { int error; From 738fc84a7a946937fd3579fb94264973459cda52 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Wed, 5 Aug 2020 08:31:26 +0000 Subject: [PATCH 092/141] allwinner: clk: Fix nm clock calculation Use the right factor when finding the best frequency and compare the absolute value of the result. Submitted by: kibab MFC after: 3 days --- sys/arm/allwinner/clkng/aw_clk_nm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sys/arm/allwinner/clkng/aw_clk_nm.c b/sys/arm/allwinner/clkng/aw_clk_nm.c index dc560cca5622..27caf3374266 100644 --- a/sys/arm/allwinner/clkng/aw_clk_nm.c +++ b/sys/arm/allwinner/clkng/aw_clk_nm.c @@ -151,7 +151,7 @@ aw_clk_nm_find_best(struct aw_clk_nm_sc *sc, uint64_t fparent, uint64_t *fout, min_n = aw_clk_factor_get_min(&sc->n); for (m = min_m; m <= max_m; ) { - for (n = min_m; n <= max_n; ) { + for (n = min_n; n <= max_n; ) { cur = fparent / n / m; if (abs(*fout - cur) < abs(*fout - best)) { best = cur; @@ -196,7 +196,7 @@ aw_clk_nm_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout, clknode_get_freq(p_clk, &fparent); cur = aw_clk_nm_find_best(sc, fparent, fout, &n, &m); - if ((*fout - cur) < (*fout - best)) { + if (abs((*fout - cur)) < abs((*fout - best))) { best = cur; best_parent = p_idx; best_n = n; From aaef76e1fd8c94849324c557a204da2a84a305e3 Mon Sep 17 00:00:00 2001 From: "Andrey V. Elsukov" Date: Wed, 5 Aug 2020 09:16:35 +0000 Subject: [PATCH 093/141] Handle delayed checksums if needed in NAT64. Upper level protocols defer checksums calculation in hope we have checksums offloading in a network card. CSUM_DELAY_DATA flag is used to determine that checksum calculation was deferred. And IP output routine checks for this flag before pass mbuf to lower layer. Forwarded packets have not this flag. NAT64 uses checksums adjustment when it translates IP headers. In most cases NAT64 is used for forwarded packets, but in case when it handles locally originated packets we need to finish checksum calculation that was deferred to correctly adjust it. Add check for presence of CSUM_DELAY_DATA flag and finish checksum calculation before adjustment. Reported and tested by: Evgeniy Khramtsov MFC after: 1 week --- sys/netpfil/ipfw/nat64/nat64_translate.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/sys/netpfil/ipfw/nat64/nat64_translate.c b/sys/netpfil/ipfw/nat64/nat64_translate.c index c7c83858b3cc..87cef07feefc 100644 --- a/sys/netpfil/ipfw/nat64/nat64_translate.c +++ b/sys/netpfil/ipfw/nat64/nat64_translate.c @@ -1294,6 +1294,12 @@ nat64_do_handle_ip4(struct mbuf *m, struct in6_addr *saddr, ip6.ip6_hlim -= IPTTLDEC; ip6.ip6_plen = htons(plen); ip6.ip6_nxt = (proto == IPPROTO_ICMP) ? IPPROTO_ICMPV6: proto; + + /* Handle delayed checksums if needed. */ + if (m->m_pkthdr.csum_flags & CSUM_DELAY_DATA) { + in_delayed_cksum(m); + m->m_pkthdr.csum_flags &= ~CSUM_DELAY_DATA; + } /* Convert checksums. */ switch (proto) { case IPPROTO_TCP: @@ -1665,6 +1671,12 @@ nat64_do_handle_ip6(struct mbuf *m, uint32_t aaddr, uint16_t aport, return (NAT64RETURN); } nat64_init_ip4hdr(ip6, frag, plen, proto, &ip); + + /* Handle delayed checksums if needed. */ + if (m->m_pkthdr.csum_flags & CSUM_DELAY_DATA_IPV6) { + in6_delayed_cksum(m, plen, hlen); + m->m_pkthdr.csum_flags &= ~CSUM_DELAY_DATA_IPV6; + } /* Convert checksums. */ switch (proto) { case IPPROTO_TCP: From dca51295b2080e6aca9d00a6a656433d8577bae5 Mon Sep 17 00:00:00 2001 From: Eugene Grosbein Date: Wed, 5 Aug 2020 09:19:41 +0000 Subject: [PATCH 094/141] bsnmptools: make it print protocol errors to stderr instead of stdout Reviewed by: syrinx, bz MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D25911 --- usr.sbin/bsnmpd/tools/libbsnmptools/bsnmptools.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/usr.sbin/bsnmpd/tools/libbsnmptools/bsnmptools.c b/usr.sbin/bsnmpd/tools/libbsnmptools/bsnmptools.c index 36b9917581fd..bd2034a0f156 100644 --- a/usr.sbin/bsnmpd/tools/libbsnmptools/bsnmptools.c +++ b/usr.sbin/bsnmpd/tools/libbsnmptools/bsnmptools.c @@ -1828,11 +1828,11 @@ snmp_output_numval(struct snmp_toolinfo *snmptoolctx, struct snmp_value *val, break; case SNMP_SYNTAX_NOSUCHOBJECT: - fprintf(stdout, "No Such Object\n"); + fprintf(stderr, "No Such Object\n"); return (val->syntax); case SNMP_SYNTAX_NOSUCHINSTANCE: - fprintf(stdout, "No Such Instance\n"); + fprintf(stderr, "No Such Instance\n"); return (val->syntax); case SNMP_SYNTAX_ENDOFMIBVIEW: @@ -1841,12 +1841,12 @@ snmp_output_numval(struct snmp_toolinfo *snmptoolctx, struct snmp_value *val, case SNMP_SYNTAX_NULL: /* NOTREACHED */ - fprintf(stdout, "agent returned NULL Syntax\n"); + fprintf(stderr, "agent returned NULL Syntax\n"); return (val->syntax); default: /* NOTREACHED - If here - then all went completely wrong. */ - fprintf(stdout, "agent returned unknown syntax\n"); + fprintf(stderr, "agent returned unknown syntax\n"); return (-1); } From d61ce7ef50c770c20bcc8698209e331e51c59a70 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 09:24:00 +0000 Subject: [PATCH 095/141] cache: convert ncnegnash into a macro It is a read-only var with value known at compilation time. --- sys/kern/vfs_cache.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index a12da7d35635..252984849d90 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -284,8 +284,8 @@ static struct neglist __read_mostly *neglists; static struct neglist ncneg_hot; static u_long numhotneg; -#define numneglists (ncneghash + 1) -static u_int __read_mostly ncneghash; +#define ncneghash 3 +#define numneglists (ncneghash + 1) static inline struct neglist * NCP2NEGLIST(struct namecache *ncp) { @@ -2091,7 +2091,6 @@ nchinit(void *dummy __unused) mtx_init(&vnodelocks[i], "ncvn", NULL, MTX_DUPOK | MTX_RECURSE); ncpurgeminvnodes = numbucketlocks * 2; - ncneghash = 3; neglists = malloc(sizeof(*neglists) * numneglists, M_VFSCACHE, M_WAITOK | M_ZERO); for (i = 0; i < numneglists; i++) { From cf8ac0de81506bd040b64f4c5fbe96c3109f802b Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 09:24:38 +0000 Subject: [PATCH 096/141] cache: reduce zone alignment to 8 bytes It used to be sizeof of the given struct to accomodate for 32 bit mips doing 64 bit loads, but the same can be achieved with requireing just 64 bit alignment. While here reorder struct namecache so that most commonly used fields are closer. --- sys/kern/vfs_cache.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 252984849d90..fd8c36b07403 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -122,9 +122,9 @@ _Static_assert(sizeof(struct negstate) <= sizeof(struct vnode *), "the state must fit in a union with a pointer without growing it"); struct namecache { - CK_LIST_ENTRY(namecache) nc_hash;/* hash chain */ LIST_ENTRY(namecache) nc_src; /* source vnode list */ TAILQ_ENTRY(namecache) nc_dst; /* destination vnode list */ + CK_LIST_ENTRY(namecache) nc_hash;/* hash chain */ struct vnode *nc_dvp; /* vnode of parent of name */ union { struct vnode *nu_vp; /* vnode the name refers to */ @@ -142,6 +142,8 @@ struct namecache { * to be stored. The nc_dotdottime field is used when a cache entry is mapping * both a non-dotdot directory name plus dotdot for the directory's * parent. + * + * See below for alignment requirement. */ struct namecache_ts { struct timespec nc_time; /* timespec provided by fs */ @@ -150,6 +152,14 @@ struct namecache_ts { struct namecache nc_nc; }; +/* + * At least mips n32 performs 64-bit accesses to timespec as found + * in namecache_ts and requires them to be aligned. Since others + * may be in the same spot suffer a little bit and enforce the + * alignment for everyone. Note this is a nop for 64-bit platforms. + */ +#define CACHE_ZONE_ALIGNMENT UMA_ALIGNOF(time_t) + #define nc_vp n_un.nu_vp #define nc_neg n_un.nu_neg @@ -2053,19 +2063,19 @@ nchinit(void *dummy __unused) cache_zone_small = uma_zcreate("S VFS Cache", sizeof(struct namecache) + CACHE_PATH_CUTOFF + 1, - NULL, NULL, NULL, NULL, UMA_ALIGNOF(struct namecache), + NULL, NULL, NULL, NULL, CACHE_ZONE_ALIGNMENT, UMA_ZONE_ZINIT); cache_zone_small_ts = uma_zcreate("STS VFS Cache", sizeof(struct namecache_ts) + CACHE_PATH_CUTOFF + 1, - NULL, NULL, NULL, NULL, UMA_ALIGNOF(struct namecache_ts), + NULL, NULL, NULL, NULL, CACHE_ZONE_ALIGNMENT, UMA_ZONE_ZINIT); cache_zone_large = uma_zcreate("L VFS Cache", sizeof(struct namecache) + NAME_MAX + 1, - NULL, NULL, NULL, NULL, UMA_ALIGNOF(struct namecache), + NULL, NULL, NULL, NULL, CACHE_ZONE_ALIGNMENT, UMA_ZONE_ZINIT); cache_zone_large_ts = uma_zcreate("LTS VFS Cache", sizeof(struct namecache_ts) + NAME_MAX + 1, - NULL, NULL, NULL, NULL, UMA_ALIGNOF(struct namecache_ts), + NULL, NULL, NULL, NULL, CACHE_ZONE_ALIGNMENT, UMA_ZONE_ZINIT); VFS_SMR_ZONE_SET(cache_zone_small); From 2b86f9d6d013a9ad8b1f8d03286018e785d5b3f6 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 09:25:59 +0000 Subject: [PATCH 097/141] cache: convert the hash from LIST to SLIST This reduces struct namecache by sizeof(void *). Negative side is that we have to find the previous element (if any) when removing an entry, but since we normally don't expect collisions it should be fine. Note this adds cache_get_hash calls which can be eliminated. --- sys/kern/vfs_cache.c | 75 +++++++++++++++++++++++++++++++------------- 1 file changed, 54 insertions(+), 21 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index fd8c36b07403..8f995c82b9e8 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -124,7 +124,7 @@ _Static_assert(sizeof(struct negstate) <= sizeof(struct vnode *), struct namecache { LIST_ENTRY(namecache) nc_src; /* source vnode list */ TAILQ_ENTRY(namecache) nc_dst; /* destination vnode list */ - CK_LIST_ENTRY(namecache) nc_hash;/* hash chain */ + CK_SLIST_ENTRY(namecache) nc_hash;/* hash chain */ struct vnode *nc_dvp; /* vnode of parent of name */ union { struct vnode *nu_vp; /* vnode the name refers to */ @@ -264,7 +264,7 @@ VFS_SMR_DECLARE; */ #define NCHHASH(hash) \ (&nchashtbl[(hash) & nchash]) -static __read_mostly CK_LIST_HEAD(nchashhead, namecache) *nchashtbl;/* Hash Table */ +static __read_mostly CK_SLIST_HEAD(nchashhead, namecache) *nchashtbl;/* Hash Table */ static u_long __read_mostly nchash; /* size of hash table */ SYSCTL_ULONG(_debug, OID_AUTO, nchash, CTLFLAG_RD, &nchash, 0, "Size of namecache hash table"); @@ -520,6 +520,15 @@ cache_get_hash(char *name, u_char len, struct vnode *dvp) return (fnv_32_buf(name, len, dvp->v_nchash)); } +static inline struct nchashhead * +NCP2BUCKET(struct namecache *ncp) +{ + uint32_t hash; + + hash = cache_get_hash(ncp->nc_name, ncp->nc_nlen, ncp->nc_dvp); + return (NCHHASH(hash)); +} + static inline struct rwlock * NCP2BUCKETLOCK(struct namecache *ncp) { @@ -687,7 +696,7 @@ sysctl_debug_hashstat_rawnchash(SYSCTL_HANDLER_ARGS) } /* Scan hash tables counting entries */ for (ncpp = nchashtbl, i = 0; i < n_nchash; ncpp++, i++) - CK_LIST_FOREACH(ncp, ncpp, nc_hash) + CK_SLIST_FOREACH(ncp, ncpp, nc_hash) cntbuf[i]++; cache_unlock_all_buckets(); for (error = 0, i = 0; i < n_nchash; i++) @@ -720,7 +729,7 @@ sysctl_debug_hashstat_nchash(SYSCTL_HANDLER_ARGS) /* Scan hash tables for applicable entries */ for (ncpp = nchashtbl; n_nchash > 0; n_nchash--, ncpp++) { count = 0; - CK_LIST_FOREACH(ncp, ncpp, nc_hash) { + CK_SLIST_FOREACH(ncp, ncpp, nc_hash) { count++; } if (count) @@ -952,6 +961,7 @@ cache_negative_zap_one(void) static void cache_zap_locked(struct namecache *ncp) { + struct nchashhead *ncpp; if (!(ncp->nc_flag & NCF_NEGATIVE)) cache_assert_vnode_locked(ncp->nc_vp); @@ -963,7 +973,8 @@ cache_zap_locked(struct namecache *ncp) cache_ncp_invalidate(ncp); - CK_LIST_REMOVE(ncp, nc_hash); + ncpp = NCP2BUCKET(ncp); + CK_SLIST_REMOVE(ncpp, ncp, namecache, nc_hash); if (!(ncp->nc_flag & NCF_NEGATIVE)) { SDT_PROBE3(vfs, namecache, zap, done, ncp->nc_dvp, ncp->nc_name, ncp->nc_vp); @@ -1122,7 +1133,7 @@ cache_zap_unlocked_bucket(struct namecache *ncp, struct componentname *cnp, cache_sort_vnodes(&dvlp, &vlp); cache_lock_vnodes(dvlp, vlp); rw_wlock(blp); - CK_LIST_FOREACH(rncp, (NCHHASH(hash)), nc_hash) { + CK_SLIST_FOREACH(rncp, (NCHHASH(hash)), nc_hash) { if (rncp == ncp && rncp->nc_dvp == dvp && rncp->nc_nlen == cnp->cn_namelen && !bcmp(rncp->nc_name, cnp->cn_nameptr, rncp->nc_nlen)) @@ -1336,12 +1347,12 @@ cache_lookup_nomakeentry(struct vnode *dvp, struct vnode **vpp, hash = cache_get_hash(cnp->cn_nameptr, cnp->cn_namelen, dvp); blp = HASH2BUCKETLOCK(hash); retry: - if (CK_LIST_EMPTY(NCHHASH(hash))) + if (CK_SLIST_EMPTY(NCHHASH(hash))) goto out_no_entry; rw_wlock(blp); - CK_LIST_FOREACH(ncp, (NCHHASH(hash)), nc_hash) { + CK_SLIST_FOREACH(ncp, (NCHHASH(hash)), nc_hash) { if (ncp->nc_dvp == dvp && ncp->nc_nlen == cnp->cn_namelen && !bcmp(ncp->nc_name, cnp->cn_nameptr, ncp->nc_nlen)) break; @@ -1485,7 +1496,7 @@ cache_lookup(struct vnode *dvp, struct vnode **vpp, struct componentname *cnp, rw_rlock(blp); } - CK_LIST_FOREACH(ncp, (NCHHASH(hash)), nc_hash) { + CK_SLIST_FOREACH(ncp, (NCHHASH(hash)), nc_hash) { if (ncp->nc_dvp == dvp && ncp->nc_nlen == cnp->cn_namelen && !bcmp(ncp->nc_name, cnp->cn_nameptr, ncp->nc_nlen)) break; @@ -1932,7 +1943,7 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp, * the same path name. */ ncpp = NCHHASH(hash); - CK_LIST_FOREACH(n2, ncpp, nc_hash) { + CK_SLIST_FOREACH(n2, ncpp, nc_hash) { if (n2->nc_dvp == dvp && n2->nc_nlen == cnp->cn_namelen && !bcmp(n2->nc_name, cnp->cn_nameptr, n2->nc_nlen)) { @@ -2021,7 +2032,7 @@ cache_enter_time(struct vnode *dvp, struct vnode *vp, struct componentname *cnp, * Insert the new namecache entry into the appropriate chain * within the cache entries table. */ - CK_LIST_INSERT_HEAD(ncpp, ncp, nc_hash); + CK_SLIST_INSERT_HEAD(ncpp, ncp, nc_hash); atomic_thread_fence_rel(); /* @@ -2053,6 +2064,28 @@ cache_roundup_2(u_int val) return (res); } +static struct nchashhead * +nchinittbl(u_long elements, u_long *hashmask) +{ + struct nchashhead *hashtbl; + u_long hashsize, i; + + hashsize = cache_roundup_2(desiredvnodes * 2) / 2; + + hashtbl = malloc((u_long)hashsize * sizeof(*hashtbl), M_VFSCACHE, M_WAITOK); + for (i = 0; i < hashsize; i++) + CK_SLIST_INIT(&hashtbl[i]); + *hashmask = hashsize - 1; + return (hashtbl); +} + +static void +ncfreetbl(struct nchashhead *hashtbl) +{ + + free(hashtbl, M_VFSCACHE); +} + /* * Name cache initialization, from vfs_init() when we are booting */ @@ -2084,7 +2117,7 @@ nchinit(void *dummy __unused) VFS_SMR_ZONE_SET(cache_zone_large_ts); ncsize = desiredvnodes * ncsizefactor; - nchashtbl = hashinit(desiredvnodes * 2, M_VFSCACHE, &nchash); + nchashtbl = nchinittbl(desiredvnodes * 2, &nchash); ncbuckethash = cache_roundup_2(mp_ncpus * mp_ncpus) - 1; if (ncbuckethash < 7) /* arbitrarily chosen to avoid having one lock */ ncbuckethash = 7; @@ -2139,10 +2172,10 @@ cache_changesize(u_long newmaxvnodes) if (newmaxvnodes < numbucketlocks) newmaxvnodes = numbucketlocks; - new_nchashtbl = hashinit(newmaxvnodes, M_VFSCACHE, &new_nchash); + new_nchashtbl = nchinittbl(newmaxvnodes, &new_nchash); /* If same hash table size, nothing to do */ if (nchash == new_nchash) { - free(new_nchashtbl, M_VFSCACHE); + ncfreetbl(new_nchashtbl); return; } /* @@ -2157,17 +2190,17 @@ cache_changesize(u_long newmaxvnodes) nchashtbl = new_nchashtbl; nchash = new_nchash; for (i = 0; i <= old_nchash; i++) { - while ((ncp = CK_LIST_FIRST(&old_nchashtbl[i])) != NULL) { + while ((ncp = CK_SLIST_FIRST(&old_nchashtbl[i])) != NULL) { hash = cache_get_hash(ncp->nc_name, ncp->nc_nlen, ncp->nc_dvp); - CK_LIST_REMOVE(ncp, nc_hash); - CK_LIST_INSERT_HEAD(NCHHASH(hash), ncp, nc_hash); + CK_SLIST_REMOVE(&old_nchashtbl[i], ncp, namecache, nc_hash); + CK_SLIST_INSERT_HEAD(NCHHASH(hash), ncp, nc_hash); } } ncsize = newncsize; cache_unlock_all_buckets(); cache_unlock_all_vnodes(); - free(old_nchashtbl, M_VFSCACHE); + ncfreetbl(old_nchashtbl); } /* @@ -2317,7 +2350,7 @@ cache_purgevfs(struct mount *mp, bool force) for (j = i; j < n_nchash; j += numbucketlocks) { retry: bucket = &nchashtbl[j]; - CK_LIST_FOREACH_SAFE(ncp, bucket, nc_hash, nnp) { + CK_SLIST_FOREACH_SAFE(ncp, bucket, nc_hash, nnp) { cache_assert_bucket_locked(ncp, RA_WLOCKED); if (ncp->nc_dvp->v_mount != mp) continue; @@ -3233,7 +3266,7 @@ cache_fplookup_negative_promote(struct cache_fpl *fpl, struct namecache *oncp, * In particular at this point there can be a new ncp which matches the * search but hashes to a different neglist. */ - CK_LIST_FOREACH(ncp, (NCHHASH(hash)), nc_hash) { + CK_SLIST_FOREACH(ncp, (NCHHASH(hash)), nc_hash) { if (ncp == oncp) break; } @@ -3583,7 +3616,7 @@ cache_fplookup_next(struct cache_fpl *fpl) hash = cache_get_hash(cnp->cn_nameptr, cnp->cn_namelen, dvp); - CK_LIST_FOREACH(ncp, (NCHHASH(hash)), nc_hash) { + CK_SLIST_FOREACH(ncp, (NCHHASH(hash)), nc_hash) { if (ncp->nc_dvp == dvp && ncp->nc_nlen == cnp->cn_namelen && !bcmp(ncp->nc_name, cnp->cn_nameptr, ncp->nc_nlen)) break; From d292b1940c9cc327810627c486cbcfa7e12ce8ad Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 09:27:03 +0000 Subject: [PATCH 098/141] vfs: remove the obsolete privused argument from vaccess This brings argument count down to 6, which is passable without the stack on amd64. --- .../opensolaris/uts/common/fs/zfs/zfs_vnops.c | 2 +- sys/fs/cd9660/cd9660_vnops.c | 2 +- sys/fs/devfs/devfs_vnops.c | 2 +- sys/fs/ext2fs/ext2_vnops.c | 2 +- sys/fs/fuse/fuse_internal.c | 2 +- sys/fs/msdosfs/msdosfs_vnops.c | 2 +- sys/fs/nfsclient/nfs_clvnops.c | 4 ++-- sys/fs/pseudofs/pseudofs_vnops.c | 4 ++-- sys/fs/smbfs/smbfs_vnops.c | 2 +- sys/fs/tmpfs/tmpfs_vnops.c | 4 ++-- sys/fs/udf/udf_vnops.c | 2 +- sys/kern/subr_acl_nfs4.c | 8 +------- sys/kern/subr_acl_posix1e.c | 14 +------------- sys/kern/uipc_mqueue.c | 8 ++++---- sys/kern/uipc_sem.c | 4 ++-- sys/kern/uipc_shm.c | 6 +++--- sys/kern/vfs_subr.c | 14 +++----------- sys/sys/vnode.h | 8 +++----- sys/ufs/ufs/ufs_vnops.c | 10 +++++----- 19 files changed, 36 insertions(+), 64 deletions(-) diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c index 13f3412e96f5..9ac9503d2f77 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c @@ -4941,7 +4941,7 @@ zfs_freebsd_access(ap) accmode = ap->a_accmode & ~(VREAD|VWRITE|VEXEC|VAPPEND); if (accmode != 0) { error = vaccess(vp->v_type, zp->z_mode, zp->z_uid, - zp->z_gid, accmode, ap->a_cred, NULL); + zp->z_gid, accmode, ap->a_cred); } } diff --git a/sys/fs/cd9660/cd9660_vnops.c b/sys/fs/cd9660/cd9660_vnops.c index 43bb900efff8..92af83db0abb 100644 --- a/sys/fs/cd9660/cd9660_vnops.c +++ b/sys/fs/cd9660/cd9660_vnops.c @@ -158,7 +158,7 @@ cd9660_access(ap) } return (vaccess(vp->v_type, ip->inode.iso_mode, ip->inode.iso_uid, - ip->inode.iso_gid, ap->a_accmode, ap->a_cred, NULL)); + ip->inode.iso_gid, ap->a_accmode, ap->a_cred)); } static int diff --git a/sys/fs/devfs/devfs_vnops.c b/sys/fs/devfs/devfs_vnops.c index c21c1128543e..0605fad13cf5 100644 --- a/sys/fs/devfs/devfs_vnops.c +++ b/sys/fs/devfs/devfs_vnops.c @@ -533,7 +533,7 @@ devfs_access(struct vop_access_args *ap) de = de->de_dir; error = vaccess(vp->v_type, de->de_mode, de->de_uid, de->de_gid, - ap->a_accmode, ap->a_cred, NULL); + ap->a_accmode, ap->a_cred); if (error == 0) return (0); if (error != EACCES) diff --git a/sys/fs/ext2fs/ext2_vnops.c b/sys/fs/ext2fs/ext2_vnops.c index b98f8289e05c..0944889c3cce 100644 --- a/sys/fs/ext2fs/ext2_vnops.c +++ b/sys/fs/ext2fs/ext2_vnops.c @@ -348,7 +348,7 @@ ext2_access(struct vop_access_args *ap) return (EPERM); error = vaccess(vp->v_type, ip->i_mode, ip->i_uid, ip->i_gid, - ap->a_accmode, ap->a_cred, NULL); + ap->a_accmode, ap->a_cred); return (error); } diff --git a/sys/fs/fuse/fuse_internal.c b/sys/fs/fuse/fuse_internal.c index 22bc2d630971..2c4f90d1ece2 100644 --- a/sys/fs/fuse/fuse_internal.c +++ b/sys/fs/fuse/fuse_internal.c @@ -208,7 +208,7 @@ fuse_internal_access(struct vnode *vp, fuse_internal_getattr(vp, &va, cred, td); return vaccess(vp->v_type, va.va_mode, va.va_uid, - va.va_gid, mode, cred, NULL); + va.va_gid, mode, cred); } if (mode & VADMIN) { diff --git a/sys/fs/msdosfs/msdosfs_vnops.c b/sys/fs/msdosfs/msdosfs_vnops.c index d5df4f7ff4a7..11d26386f645 100644 --- a/sys/fs/msdosfs/msdosfs_vnops.c +++ b/sys/fs/msdosfs/msdosfs_vnops.c @@ -250,7 +250,7 @@ msdosfs_access(struct vop_access_args *ap) } return (vaccess(vp->v_type, file_mode, pmp->pm_uid, pmp->pm_gid, - ap->a_accmode, ap->a_cred, NULL)); + ap->a_accmode, ap->a_cred)); } static int diff --git a/sys/fs/nfsclient/nfs_clvnops.c b/sys/fs/nfsclient/nfs_clvnops.c index fd8e76ef028a..e93720f1a137 100644 --- a/sys/fs/nfsclient/nfs_clvnops.c +++ b/sys/fs/nfsclient/nfs_clvnops.c @@ -3393,8 +3393,8 @@ nfsspec_access(struct vop_access_args *ap) error = VOP_GETATTR(vp, vap, cred); if (error) goto out; - error = vaccess(vp->v_type, vap->va_mode, vap->va_uid, vap->va_gid, - accmode, cred, NULL); + error = vaccess(vp->v_type, vap->va_mode, vap->va_uid, vap->va_gid, + accmode, cred); out: return error; } diff --git a/sys/fs/pseudofs/pseudofs_vnops.c b/sys/fs/pseudofs/pseudofs_vnops.c index f4a0c3371088..75981d8b5350 100644 --- a/sys/fs/pseudofs/pseudofs_vnops.c +++ b/sys/fs/pseudofs/pseudofs_vnops.c @@ -167,8 +167,8 @@ pfs_access(struct vop_access_args *va) error = VOP_GETATTR(vn, &vattr, va->a_cred); if (error) PFS_RETURN (error); - error = vaccess(vn->v_type, vattr.va_mode, vattr.va_uid, - vattr.va_gid, va->a_accmode, va->a_cred, NULL); + error = vaccess(vn->v_type, vattr.va_mode, vattr.va_uid, vattr.va_gid, + va->a_accmode, va->a_cred); PFS_RETURN (error); } diff --git a/sys/fs/smbfs/smbfs_vnops.c b/sys/fs/smbfs/smbfs_vnops.c index 026fab8d000c..674ca7ede798 100644 --- a/sys/fs/smbfs/smbfs_vnops.c +++ b/sys/fs/smbfs/smbfs_vnops.c @@ -141,7 +141,7 @@ smbfs_access(ap) } mpmode = vp->v_type == VREG ? smp->sm_file_mode : smp->sm_dir_mode; return (vaccess(vp->v_type, mpmode, smp->sm_uid, - smp->sm_gid, ap->a_accmode, ap->a_cred, NULL)); + smp->sm_gid, ap->a_accmode, ap->a_cred)); } /* ARGSUSED */ diff --git a/sys/fs/tmpfs/tmpfs_vnops.c b/sys/fs/tmpfs/tmpfs_vnops.c index c0d970edeb94..0e414a46c701 100644 --- a/sys/fs/tmpfs/tmpfs_vnops.c +++ b/sys/fs/tmpfs/tmpfs_vnops.c @@ -396,8 +396,8 @@ tmpfs_access(struct vop_access_args *v) goto out; } - error = vaccess(vp->v_type, node->tn_mode, node->tn_uid, - node->tn_gid, accmode, cred, NULL); + error = vaccess(vp->v_type, node->tn_mode, node->tn_uid, node->tn_gid, + accmode, cred); out: MPASS(VOP_ISLOCKED(vp)); diff --git a/sys/fs/udf/udf_vnops.c b/sys/fs/udf/udf_vnops.c index 4a13c0c272c1..56a7613ad5a2 100644 --- a/sys/fs/udf/udf_vnops.c +++ b/sys/fs/udf/udf_vnops.c @@ -180,7 +180,7 @@ udf_access(struct vop_access_args *a) mode = udf_permtomode(node); return (vaccess(vp->v_type, mode, node->fentry->uid, node->fentry->gid, - accmode, a->a_cred, NULL)); + accmode, a->a_cred)); } static int diff --git a/sys/kern/subr_acl_nfs4.c b/sys/kern/subr_acl_nfs4.c index 05a4b653757b..4d36506ffa2f 100644 --- a/sys/kern/subr_acl_nfs4.c +++ b/sys/kern/subr_acl_nfs4.c @@ -172,7 +172,7 @@ _acl_denies(const struct acl *aclp, int access_mask, struct ucred *cred, int vaccess_acl_nfs4(enum vtype type, uid_t file_uid, gid_t file_gid, - struct acl *aclp, accmode_t accmode, struct ucred *cred, int *privused) + struct acl *aclp, accmode_t accmode, struct ucred *cred) { accmode_t priv_granted = 0; int denied, explicitly_denied, access_mask, is_directory, @@ -187,9 +187,6 @@ vaccess_acl_nfs4(enum vtype type, uid_t file_uid, gid_t file_gid, KASSERT((accmode & VAPPEND) == 0 || (accmode & VWRITE), ("VAPPEND without VWRITE")); - if (privused != NULL) - *privused = 0; - if (accmode & VADMIN) must_be_owner = 1; @@ -289,9 +286,6 @@ vaccess_acl_nfs4(enum vtype type, uid_t file_uid, gid_t file_gid, priv_granted |= VSTAT_PERMS; if ((accmode & priv_granted) == accmode) { - if (privused != NULL) - *privused = 1; - return (0); } diff --git a/sys/kern/subr_acl_posix1e.c b/sys/kern/subr_acl_posix1e.c index 5fd0aeefbc33..775957f9ef6f 100644 --- a/sys/kern/subr_acl_posix1e.c +++ b/sys/kern/subr_acl_posix1e.c @@ -57,7 +57,7 @@ __FBSDID("$FreeBSD$"); */ int vaccess_acl_posix1e(enum vtype type, uid_t file_uid, gid_t file_gid, - struct acl *acl, accmode_t accmode, struct ucred *cred, int *privused) + struct acl *acl, accmode_t accmode, struct ucred *cred) { struct acl_entry *acl_other, *acl_mask; accmode_t dac_granted; @@ -77,8 +77,6 @@ vaccess_acl_posix1e(enum vtype type, uid_t file_uid, gid_t file_gid, * privileges to use may be ambiguous due to "best match", in which * case fall back on first match for the time being. */ - if (privused != NULL) - *privused = 0; /* * Determine privileges now, but don't apply until we've found a DAC @@ -142,8 +140,6 @@ vaccess_acl_posix1e(enum vtype type, uid_t file_uid, gid_t file_gid, */ if ((accmode & (dac_granted | priv_granted)) == accmode) { - if (privused != NULL) - *privused = 1; return (0); } goto error; @@ -220,8 +216,6 @@ vaccess_acl_posix1e(enum vtype type, uid_t file_uid, gid_t file_gid, accmode) goto error; - if (privused != NULL) - *privused = 1; return (0); } } @@ -303,8 +297,6 @@ vaccess_acl_posix1e(enum vtype type, uid_t file_uid, gid_t file_gid, != accmode) break; - if (privused != NULL) - *privused = 1; return (0); case ACL_GROUP: @@ -327,8 +319,6 @@ vaccess_acl_posix1e(enum vtype type, uid_t file_uid, gid_t file_gid, != accmode) break; - if (privused != NULL) - *privused = 1; return (0); default: @@ -359,8 +349,6 @@ vaccess_acl_posix1e(enum vtype type, uid_t file_uid, gid_t file_gid, * XXXRW: Do privilege lookup here. */ if ((accmode & (dac_granted | priv_granted)) == accmode) { - if (privused != NULL) - *privused = 1; return (0); } diff --git a/sys/kern/uipc_mqueue.c b/sys/kern/uipc_mqueue.c index 5a4054df09f5..018630ca7dad 100644 --- a/sys/kern/uipc_mqueue.c +++ b/sys/kern/uipc_mqueue.c @@ -1178,8 +1178,8 @@ mqfs_access(struct vop_access_args *ap) error = VOP_GETATTR(vp, &vattr, ap->a_cred); if (error) return (error); - error = vaccess(vp->v_type, vattr.va_mode, vattr.va_uid, - vattr.va_gid, ap->a_accmode, ap->a_cred, NULL); + error = vaccess(vp->v_type, vattr.va_mode, vattr.va_uid, vattr.va_gid, + ap->a_accmode, ap->a_cred); return (error); } @@ -2088,7 +2088,7 @@ kern_kmq_open(struct thread *td, const char *upath, int flags, mode_t mode, if (flags & FWRITE) accmode |= VWRITE; error = vaccess(VREG, pn->mn_mode, pn->mn_uid, - pn->mn_gid, accmode, td->td_ucred, NULL); + pn->mn_gid, accmode, td->td_ucred); } } @@ -2566,7 +2566,7 @@ mqf_chmod(struct file *fp, mode_t mode, struct ucred *active_cred, pn = fp->f_data; sx_xlock(&mqfs_data.mi_lock); error = vaccess(VREG, pn->mn_mode, pn->mn_uid, pn->mn_gid, VADMIN, - active_cred, NULL); + active_cred); if (error != 0) goto out; pn->mn_mode = mode & ACCESSPERMS; diff --git a/sys/kern/uipc_sem.c b/sys/kern/uipc_sem.c index 27f586119c77..4d7c8ff03773 100644 --- a/sys/kern/uipc_sem.c +++ b/sys/kern/uipc_sem.c @@ -212,7 +212,7 @@ ksem_chmod(struct file *fp, mode_t mode, struct ucred *active_cred, goto out; #endif error = vaccess(VREG, ks->ks_mode, ks->ks_uid, ks->ks_gid, VADMIN, - active_cred, NULL); + active_cred); if (error != 0) goto out; ks->ks_mode = mode & ACCESSPERMS; @@ -362,7 +362,7 @@ ksem_access(struct ksem *ks, struct ucred *ucred) int error; error = vaccess(VREG, ks->ks_mode, ks->ks_uid, ks->ks_gid, - VREAD | VWRITE, ucred, NULL); + VREAD | VWRITE, ucred); if (error) error = priv_check_cred(ucred, PRIV_SEM_WRITE); return (error); diff --git a/sys/kern/uipc_shm.c b/sys/kern/uipc_shm.c index a8af8c815492..796c2b08582a 100644 --- a/sys/kern/uipc_shm.c +++ b/sys/kern/uipc_shm.c @@ -679,7 +679,7 @@ shm_access(struct shmfd *shmfd, struct ucred *ucred, int flags) accmode |= VWRITE; mtx_lock(&shm_timestamp_lock); error = vaccess(VREG, shmfd->shm_mode, shmfd->shm_uid, shmfd->shm_gid, - accmode, ucred, NULL); + accmode, ucred); mtx_unlock(&shm_timestamp_lock); return (error); } @@ -1240,8 +1240,8 @@ shm_chmod(struct file *fp, mode_t mode, struct ucred *active_cred, if (error != 0) goto out; #endif - error = vaccess(VREG, shmfd->shm_mode, shmfd->shm_uid, - shmfd->shm_gid, VADMIN, active_cred, NULL); + error = vaccess(VREG, shmfd->shm_mode, shmfd->shm_uid, shmfd->shm_gid, + VADMIN, active_cred); if (error != 0) goto out; shmfd->shm_mode = mode & ACCESSPERMS; diff --git a/sys/kern/vfs_subr.c b/sys/kern/vfs_subr.c index d13150c2c7cf..8b1e6553452f 100644 --- a/sys/kern/vfs_subr.c +++ b/sys/kern/vfs_subr.c @@ -5299,14 +5299,12 @@ vaccess_vexec_smr(mode_t file_mode, uid_t file_uid, gid_t file_gid, struct ucred /* * Common filesystem object access control check routine. Accepts a - * vnode's type, "mode", uid and gid, requested access mode, credentials, - * and optional call-by-reference privused argument allowing vaccess() - * to indicate to the caller whether privilege was used to satisfy the - * request (obsoleted). Returns 0 on success, or an errno on failure. + * vnode's type, "mode", uid and gid, requested access mode, and credentials. + * Returns 0 on success, or an errno on failure. */ int vaccess(enum vtype type, mode_t file_mode, uid_t file_uid, gid_t file_gid, - accmode_t accmode, struct ucred *cred, int *privused) + accmode_t accmode, struct ucred *cred) { accmode_t dac_granted; accmode_t priv_granted; @@ -5321,9 +5319,6 @@ vaccess(enum vtype type, mode_t file_mode, uid_t file_uid, gid_t file_gid, * as requested. If it exists, go with that. */ - if (privused != NULL) - *privused = 0; - dac_granted = 0; /* Check the owner. */ @@ -5409,9 +5404,6 @@ vaccess(enum vtype type, mode_t file_mode, uid_t file_uid, gid_t file_gid, priv_granted |= VADMIN; if ((accmode & (priv_granted | dac_granted)) == accmode) { - /* XXX audit: privilege used */ - if (privused != NULL) - *privused = 1; return (0); } diff --git a/sys/sys/vnode.h b/sys/sys/vnode.h index 398fb088d7f1..5d9e3496d12e 100644 --- a/sys/sys/vnode.h +++ b/sys/sys/vnode.h @@ -667,16 +667,14 @@ int vn_commname(struct vnode *vn, char *buf, u_int buflen); int vn_path_to_global_path(struct thread *td, struct vnode *vp, char *path, u_int pathlen); int vaccess(enum vtype type, mode_t file_mode, uid_t file_uid, - gid_t file_gid, accmode_t accmode, struct ucred *cred, - int *privused); + gid_t file_gid, accmode_t accmode, struct ucred *cred); int vaccess_vexec_smr(mode_t file_mode, uid_t file_uid, gid_t file_gid, struct ucred *cred); int vaccess_acl_nfs4(enum vtype type, uid_t file_uid, gid_t file_gid, - struct acl *aclp, accmode_t accmode, struct ucred *cred, - int *privused); + struct acl *aclp, accmode_t accmode, struct ucred *cred); int vaccess_acl_posix1e(enum vtype type, uid_t file_uid, gid_t file_gid, struct acl *acl, accmode_t accmode, - struct ucred *cred, int *privused); + struct ucred *cred); void vattr_null(struct vattr *vap); int vcount(struct vnode *vp); void vlazy(struct vnode *); diff --git a/sys/ufs/ufs/ufs_vnops.c b/sys/ufs/ufs/ufs_vnops.c index 70dd7dbe86c1..25c75e1d584f 100644 --- a/sys/ufs/ufs/ufs_vnops.c +++ b/sys/ufs/ufs/ufs_vnops.c @@ -390,12 +390,12 @@ ufs_accessx(ap) case 0: if (type == ACL_TYPE_NFS4) { error = vaccess_acl_nfs4(vp->v_type, ip->i_uid, - ip->i_gid, acl, accmode, ap->a_cred, NULL); + ip->i_gid, acl, accmode, ap->a_cred); } else { error = vfs_unixify_accmode(&accmode); if (error == 0) error = vaccess_acl_posix1e(vp->v_type, ip->i_uid, - ip->i_gid, acl, accmode, ap->a_cred, NULL); + ip->i_gid, acl, accmode, ap->a_cred); } break; default: @@ -410,8 +410,8 @@ ufs_accessx(ap) */ error = vfs_unixify_accmode(&accmode); if (error == 0) - error = vaccess(vp->v_type, ip->i_mode, ip->i_uid, - ip->i_gid, accmode, ap->a_cred, NULL); + error = vaccess(vp->v_type, ip->i_mode, + ip->i_uid, ip->i_gid, accmode, ap->a_cred); } acl_free(acl); @@ -421,7 +421,7 @@ ufs_accessx(ap) error = vfs_unixify_accmode(&accmode); if (error == 0) error = vaccess(vp->v_type, ip->i_mode, ip->i_uid, ip->i_gid, - accmode, ap->a_cred, NULL); + accmode, ap->a_cred); return (error); } From c36edafbd4c315106075b59fff4a252e7d093f1e Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 09:27:53 +0000 Subject: [PATCH 099/141] Bump __FreeBSD_version after vaccess() change --- sys/sys/param.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/sys/param.h b/sys/sys/param.h index cc2aae21f3ca..cdb5495ed335 100644 --- a/sys/sys/param.h +++ b/sys/sys/param.h @@ -60,7 +60,7 @@ * in the range 5 to 9. */ #undef __FreeBSD_version -#define __FreeBSD_version 1300104 /* Master, propagated to newvers */ +#define __FreeBSD_version 1300105 /* Master, propagated to newvers */ /* * __FreeBSD_kernel__ indicates that this system uses the kernel of FreeBSD, From e1b1971c054076fab2ec2b61b00ea8566d769308 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 09:38:02 +0000 Subject: [PATCH 100/141] cache: don't ignore size passed to nchinittbl --- sys/kern/vfs_cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 8f995c82b9e8..25d10c824ced 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -2070,7 +2070,7 @@ nchinittbl(u_long elements, u_long *hashmask) struct nchashhead *hashtbl; u_long hashsize, i; - hashsize = cache_roundup_2(desiredvnodes * 2) / 2; + hashsize = cache_roundup_2(elements) / 2; hashtbl = malloc((u_long)hashsize * sizeof(*hashtbl), M_VFSCACHE, M_WAITOK); for (i = 0; i < hashsize; i++) From 592e97f5f6ed46b0e508b0be5511780ad9b336f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Stefan=20E=C3=9Fer?= Date: Wed, 5 Aug 2020 10:07:43 +0000 Subject: [PATCH 101/141] Upgrade to version 3.1.5 This version fixes a bug that only occurs when with chinese locale settings. --- Makefile.in | 2 +- NEWS.md | 8 ++++++++ locales/zh_CN.GB18030.msg | 9 +++------ locales/zh_CN.GB2312.msg | 9 +++------ locales/zh_CN.GBK.msg | 9 +++------ locales/zh_CN.UTF-8.msg | 13 +++++-------- locales/zh_CN.eucCN.msg | 9 +++------ src/program.c | 7 ++++--- src/vm.c | 2 +- 9 files changed, 31 insertions(+), 37 deletions(-) diff --git a/Makefile.in b/Makefile.in index fa087ad67aff..3edc9ef16ec1 100644 --- a/Makefile.in +++ b/Makefile.in @@ -29,7 +29,7 @@ # .POSIX: -VERSION = 3.1.4 +VERSION = 3.1.5 SRC = %%SRC%% OBJ = %%OBJ%% diff --git a/NEWS.md b/NEWS.md index ba528dbe907b..6d36f300d2b8 100644 --- a/NEWS.md +++ b/NEWS.md @@ -1,5 +1,13 @@ # News +## 3.1.5 + +This is a production release that fixes the Chinese locales (which caused `bc` +to crash) and a crash caused by `bc` executing code when it should not have been +able to. + +***ALL USERS SHOULD UPGRADE.*** + ## 3.1.4 This is a production release that fixes one bug, changes two behaviors, and diff --git a/locales/zh_CN.GB18030.msg b/locales/zh_CN.GB18030.msg index e305f0d93471..36b150b2bcbf 100644 --- a/locales/zh_CN.GB18030.msg +++ b/locales/zh_CN.GB18030.msg @@ -103,9 +103,6 @@ $set 6 3 "ÎÞ·¨´ò¿ªÎļþ¡£%s" 4 "Îļþ²»ÊÇASCII: %s" 5 "·¾¶ÊÇÒ»¸öĿ¼£º%s" -6 "ÎÞЧµÄÃüÁîÐÐÑ¡Ï'%c'(\"%s\")" - -$set 7 - -1 "Ñ¡ÏîÐèÒªÒ»¸ö²ÎÊý£º'%c'(\"%s\")" -2 "Ñ¡Ïî²»ÐèÒª²ÎÊý¡£'%c'(\"%s\")" +6 "ÎÞЧµÄÃüÁîÐÐÑ¡Ï\"%s\"" +7 "Ñ¡ÏîÐèÒªÒ»¸ö²ÎÊý£º'%c'(\"%s\")" +8 "Ñ¡Ïî²»ÐèÒª²ÎÊý¡£'%c'(\"%s\")" diff --git a/locales/zh_CN.GB2312.msg b/locales/zh_CN.GB2312.msg index e305f0d93471..36b150b2bcbf 100644 --- a/locales/zh_CN.GB2312.msg +++ b/locales/zh_CN.GB2312.msg @@ -103,9 +103,6 @@ $set 6 3 "ÎÞ·¨´ò¿ªÎļþ¡£%s" 4 "Îļþ²»ÊÇASCII: %s" 5 "·¾¶ÊÇÒ»¸öĿ¼£º%s" -6 "ÎÞЧµÄÃüÁîÐÐÑ¡Ï'%c'(\"%s\")" - -$set 7 - -1 "Ñ¡ÏîÐèÒªÒ»¸ö²ÎÊý£º'%c'(\"%s\")" -2 "Ñ¡Ïî²»ÐèÒª²ÎÊý¡£'%c'(\"%s\")" +6 "ÎÞЧµÄÃüÁîÐÐÑ¡Ï\"%s\"" +7 "Ñ¡ÏîÐèÒªÒ»¸ö²ÎÊý£º'%c'(\"%s\")" +8 "Ñ¡Ïî²»ÐèÒª²ÎÊý¡£'%c'(\"%s\")" diff --git a/locales/zh_CN.GBK.msg b/locales/zh_CN.GBK.msg index e305f0d93471..36b150b2bcbf 100644 --- a/locales/zh_CN.GBK.msg +++ b/locales/zh_CN.GBK.msg @@ -103,9 +103,6 @@ $set 6 3 "ÎÞ·¨´ò¿ªÎļþ¡£%s" 4 "Îļþ²»ÊÇASCII: %s" 5 "·¾¶ÊÇÒ»¸öĿ¼£º%s" -6 "ÎÞЧµÄÃüÁîÐÐÑ¡Ï'%c'(\"%s\")" - -$set 7 - -1 "Ñ¡ÏîÐèÒªÒ»¸ö²ÎÊý£º'%c'(\"%s\")" -2 "Ñ¡Ïî²»ÐèÒª²ÎÊý¡£'%c'(\"%s\")" +6 "ÎÞЧµÄÃüÁîÐÐÑ¡Ï\"%s\"" +7 "Ñ¡ÏîÐèÒªÒ»¸ö²ÎÊý£º'%c'(\"%s\")" +8 "Ñ¡Ïî²»ÐèÒª²ÎÊý¡£'%c'(\"%s\")" diff --git a/locales/zh_CN.UTF-8.msg b/locales/zh_CN.UTF-8.msg index b2d0389f9fd6..4ca46786fc94 100644 --- a/locales/zh_CN.UTF-8.msg +++ b/locales/zh_CN.UTF-8.msg @@ -91,7 +91,7 @@ $set 5 5 "递归读å–()调用" 6 "å˜é‡æˆ–数组元素是错误的类型" 7 "堆栈的元素太少" -8 "å‚æ•°æ•°é‡é”™è¯¯ï¼›éœ€è¦%zu，有%zu" +8 "å‚æ•°æ•°é‡é”™è¯¯ï¼šéœ€è¦%zu，有%zu" 9 "未定义的函数：%s()" 10 “ä¸èƒ½åœ¨è¡¨è¾¾å¼ä¸­ä½¿ç”¨ç©ºå€¼â€ @@ -100,12 +100,9 @@ $set 6 1 "内存分é…失败" 2 "I/O错误" -3 "无法打开文件。%s" +3 "无法打开文件：%s" 4 "文件ä¸æ˜¯ASCII: %s" 5 "路径是一个目录：%s" -6 "无效的命令行选项：'%c'(\"%s\")" - -$set 7 - -1 "选项需è¦ä¸€ä¸ªå‚数：'%c'(\"%s\")" -2 "选项ä¸éœ€è¦å‚数。'%c'(\"%s\")" +6 "无效的命令行选项：\"%s\"" +7 "选项需è¦ä¸€ä¸ªå‚数：'%c'(\"%s\")" +8 "选项ä¸éœ€è¦å‚数。'%c'(\"%s\")" diff --git a/locales/zh_CN.eucCN.msg b/locales/zh_CN.eucCN.msg index e305f0d93471..36b150b2bcbf 100644 --- a/locales/zh_CN.eucCN.msg +++ b/locales/zh_CN.eucCN.msg @@ -103,9 +103,6 @@ $set 6 3 "ÎÞ·¨´ò¿ªÎļþ¡£%s" 4 "Îļþ²»ÊÇASCII: %s" 5 "·¾¶ÊÇÒ»¸öĿ¼£º%s" -6 "ÎÞЧµÄÃüÁîÐÐÑ¡Ï'%c'(\"%s\")" - -$set 7 - -1 "Ñ¡ÏîÐèÒªÒ»¸ö²ÎÊý£º'%c'(\"%s\")" -2 "Ñ¡Ïî²»ÐèÒª²ÎÊý¡£'%c'(\"%s\")" +6 "ÎÞЧµÄÃüÁîÐÐÑ¡Ï\"%s\"" +7 "Ñ¡ÏîÐèÒªÒ»¸ö²ÎÊý£º'%c'(\"%s\")" +8 "Ñ¡Ïî²»ÐèÒª²ÎÊý¡£'%c'(\"%s\")" diff --git a/src/program.c b/src/program.c index 1a8176c76f96..3c2544f8a61f 100644 --- a/src/program.c +++ b/src/program.c @@ -1271,12 +1271,13 @@ static void bc_program_divmod(BcProgram *p) { BcNum *n1, *n2; size_t req; + bc_vec_expand(&p->results, p->results.len + 2); + + // We don't need to update the pointer because + // the capacity is enough due to the line above. res2 = bc_program_prepResult(p); res = bc_program_prepResult(p); - // Update the pointer, just in case. - res2 = bc_vec_item_rev(&p->results, 1); - bc_program_binOpPrep(p, &opd1, &n1, &opd2, &n2, 2); req = bc_num_mulReq(n1, n2, BC_PROG_SCALE(p)); diff --git a/src/vm.c b/src/vm.c index 9818ce4f35f4..e15b1398734e 100644 --- a/src/vm.c +++ b/src/vm.c @@ -464,7 +464,7 @@ static void bc_vm_process(const char *text) { while (BC_PARSE_CAN_PARSE(vm.prs)) vm.parse(&vm.prs); - bc_program_exec(&vm.prog); + if(BC_IS_DC || !BC_PARSE_NO_EXEC(&vm.prs)) bc_program_exec(&vm.prog); assert(BC_IS_DC || vm.prog.results.len == 0); From ce8875b6c425399f6670ad2ee29e2795b34a6ea9 Mon Sep 17 00:00:00 2001 From: "Andrey V. Elsukov" Date: Wed, 5 Aug 2020 10:27:11 +0000 Subject: [PATCH 102/141] Fix typo. Submitted by: Evgeniy Khramtsov MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D25932 --- sys/netinet6/in6_proto.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/netinet6/in6_proto.c b/sys/netinet6/in6_proto.c index 5e4898b3736f..ea7a468ac72b 100644 --- a/sys/netinet6/in6_proto.c +++ b/sys/netinet6/in6_proto.c @@ -586,7 +586,7 @@ SYSCTL_INT(_net_inet6_icmp6, ICMPV6CTL_ND6_USELOOPBACK, nd6_useloopback, "Create a loopback route when configuring an IPv6 address"); SYSCTL_INT(_net_inet6_icmp6, ICMPV6CTL_NODEINFO, nodeinfo, CTLFLAG_VNET | CTLFLAG_RW, &VNET_NAME(icmp6_nodeinfo), 0, - "Mask of enabled RF4620 node information query types"); + "Mask of enabled RFC4620 node information query types"); SYSCTL_INT(_net_inet6_icmp6, ICMPV6CTL_NODEINFO_OLDMCPREFIX, nodeinfo_oldmcprefix, CTLFLAG_VNET | CTLFLAG_RW, &VNET_NAME(icmp6_nodeinfo_oldmcprefix), 0, From b9615c3c00bedbdb8b1fef8de750aca401088d8f Mon Sep 17 00:00:00 2001 From: Mateusz Piotrowski <0mp@FreeBSD.org> Date: Wed, 5 Aug 2020 11:26:14 +0000 Subject: [PATCH 103/141] Do not describe portsnap(8) as a way to manage /usr/ports --- share/man/man7/build.7 | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/share/man/man7/build.7 b/share/man/man7/build.7 index 73d09a403428..3f3af710d97d 100644 --- a/share/man/man7/build.7 +++ b/share/man/man7/build.7 @@ -24,7 +24,7 @@ .\" .\" $FreeBSD$ .\" -.Dd May 3, 2020 +.Dd August 5, 2020 .Dt BUILD 7 .Os .Sh NAME @@ -41,10 +41,8 @@ and .Pa /usr/ports . These directories may be initially empty or non-existent until updated with .Xr svn 1 -or -.Xr svnlite 1 -or -.Xr portsnap 8 . +(or +.Xr svnlite 1 ) . Directory .Pa /usr/src contains the @@ -852,7 +850,6 @@ manpage first appeared in .Xr tests 7 , .Xr config 8 , .Xr mergemaster 8 , -.Xr portsnap 8 , .Xr reboot 8 , .Xr shutdown 8 .Sh AUTHORS From 2403d47744568f6ad99fc2e40d05c686a6f9010d Mon Sep 17 00:00:00 2001 From: "Andrey V. Elsukov" Date: Wed, 5 Aug 2020 11:26:49 +0000 Subject: [PATCH 104/141] Fix SIGSEGV in ipfw(8) when NAT64 prefix length is omitted. Submitted by: Evgeniy Khramtsov MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D25734 --- sbin/ipfw/nat64clat.c | 3 +++ sbin/ipfw/nat64stl.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/sbin/ipfw/nat64clat.c b/sbin/ipfw/nat64clat.c index 081d199bd59d..962fe7064f8d 100644 --- a/sbin/ipfw/nat64clat.c +++ b/sbin/ipfw/nat64clat.c @@ -303,6 +303,9 @@ nat64clat_config(const char *name, uint8_t set, int ac, char **av) if ((p = strchr(*av, '/')) != NULL) *p++ = '\0'; + else + errx(EX_USAGE, + "Prefix length required: %s", *av); if (inet_pton(AF_INET6, *av, &prefix) != 1) errx(EX_USAGE, "Bad prefix: %s", *av); diff --git a/sbin/ipfw/nat64stl.c b/sbin/ipfw/nat64stl.c index 44e0cbafbf3e..e82ec202b5c6 100644 --- a/sbin/ipfw/nat64stl.c +++ b/sbin/ipfw/nat64stl.c @@ -249,6 +249,9 @@ nat64stl_create(const char *name, uint8_t set, int ac, char *av[]) NEED1("IPv6 prefix6 required"); if ((p = strchr(*av, '/')) != NULL) *p++ = '\0'; + else + errx(EX_USAGE, + "Prefix length required: %s", *av); if (inet_pton(AF_INET6, *av, &cfg->prefix6) != 1) errx(EX_USAGE, "Bad prefix: %s", *av); From 75050aa9af786305be9e70a1ac79cdcc031641f5 Mon Sep 17 00:00:00 2001 From: Andriy Gapon Date: Wed, 5 Aug 2020 11:38:33 +0000 Subject: [PATCH 105/141] gpiokeys: add a basic manual page Reviewed by: manu, bjk, 0mp MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D25939 --- share/man/man4/gpiokeys.4 | 152 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 152 insertions(+) create mode 100644 share/man/man4/gpiokeys.4 diff --git a/share/man/man4/gpiokeys.4 b/share/man/man4/gpiokeys.4 new file mode 100644 index 000000000000..5af11cedb7e0 --- /dev/null +++ b/share/man/man4/gpiokeys.4 @@ -0,0 +1,152 @@ +.\" +.\" SPDX-License-Identifier: BSD-2-Clause-FreeBSD +.\" +.\" Copyright (c) 2020 Andriy Gapon +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd August 5, 2020 +.Dt GPIOKEYS 4 +.Os +.Sh NAME +.Nm gpiokeys +.Nd GPIO keys device driver +.Sh SYNOPSIS +To compile this driver into the kernel, +place the following lines in your +kernel configuration file: +.Bd -ragged -offset indent +.Cd "options FDT" +.Cd "device gpio" +.Cd "device gpiokeys" +.Ed +.Pp +Alternatively, to load the driver as a +module at boot time, place the following line in +.Xr loader.conf 5 : +.Bd -literal -offset indent +gpiokeys_load="YES" +.Ed +.Sh DESCRIPTION +The +.Nm +driver provides a way to represent a set of general purpose inputs as a +.Xr keyboard 4 +device. +At the moment the driver supports only +.Xr FDT 4 +based systems. +The DTS determines what pins are mapped to buttons and what key codes are +generated for each virtual button. +The +.Xr keyboard 4 +device can be used from userland to monitor for input changes. +.Pp +On an +.Xr FDT 4 +based system +the DTS part for a +.Nm +device usually looks like: +.Bd -literal +/ { + + ... + + gpio_keys { + compatible = "gpio-keys"; + + btn1 { + label = "button1"; + linux,code = ; + gpios = <&gpio 0 3 GPIO_ACTIVE_LOW> + }; + + btn2 { + label = "button2"; + linux,code = ; + gpios = <&gpio 0 4 GPIO_ACTIVE_LOW> + }; + }; +}; +.Ed +.Pp +For more details about the +.Va gpios +property, please consult +.Pa /usr/src/sys/dts/bindings-gpio.txt . +.Pp +The +.Nm +driver supports two properties for specifying a key code. +.Pp +The property +.Va freebsd,code +specifies a +.Fx +native scancode compatible with +.Xr kbdmap 5 +keyboard maps. +.Pp +The property +.Va linux,code +specifies an evdev scancode. +That scancode is internally translated to a native scancode. +Note that not all evdev scancodes have corresponding native scancodes. +If a scancode cannot be translated, then a diagnostic message is printed +and the input is ignored. +.Pp +The property +.Va label +is a descriptive name of a button. +It is used for diagnostic messages only. +This property is optional. +If not set, the node name is used in its place. +.Pp +The property +.Va autorepeat +determines whether autorepeat is enabled for a button. +.Pp +The property +.Va debounce-interval +defines debouncing interval time in milliseconds. +If not specified the interval defaults to 5. +.Sh SEE ALSO +.Xr fdt 4 , +.Xr gpio 4 , +.Xr keyboard 4 , +.Xr kbdmap 5 +.Sh HISTORY +The +.Nm +manual page first appeared in +.Fx 12.2 . +.Sh AUTHORS +The +.Nm +driver was written by +.An Oleksandr Tymoshenko Aq Mt gonzo@FreeBSD.org . +This +manual page was written by +.An Andriy Gapon Aq Mt avg@FreeBSD.org . From edde7a538b36273c9a61c28c00fb9463fa31838b Mon Sep 17 00:00:00 2001 From: "Andrey V. Elsukov" Date: Wed, 5 Aug 2020 11:39:09 +0000 Subject: [PATCH 106/141] Add m__getjcl SDT probe. Obtained from: Yandex LLC MFC after: 1 week Sponsored by: Yandex LLC --- sys/kern/kern_mbuf.c | 1 + sys/kern/uipc_mbuf.c | 7 +++++++ sys/sys/mbuf.h | 1 + 3 files changed, 9 insertions(+) diff --git a/sys/kern/kern_mbuf.c b/sys/kern/kern_mbuf.c index 707633150671..5fa614e73485 100644 --- a/sys/kern/kern_mbuf.c +++ b/sys/kern/kern_mbuf.c @@ -1397,6 +1397,7 @@ m_getjcl(int how, short type, int flags, int size) uma_zfree(zone_mbuf, m); return (NULL); } + MBUF_PROBE5(m__getjcl, how, type, flags, size, m); return (m); } diff --git a/sys/kern/uipc_mbuf.c b/sys/kern/uipc_mbuf.c index d645af6e55f0..5064c7519228 100644 --- a/sys/kern/uipc_mbuf.c +++ b/sys/kern/uipc_mbuf.c @@ -78,6 +78,13 @@ SDT_PROBE_DEFINE4_XLATE(sdt, , , m__getcl, "uint32_t", "uint32_t", "struct mbuf *", "mbufinfo_t *"); +SDT_PROBE_DEFINE5_XLATE(sdt, , , m__getjcl, + "uint32_t", "uint32_t", + "uint16_t", "uint16_t", + "uint32_t", "uint32_t", + "uint32_t", "uint32_t", + "struct mbuf *", "mbufinfo_t *"); + SDT_PROBE_DEFINE3_XLATE(sdt, , , m__clget, "struct mbuf *", "mbufinfo_t *", "uint32_t", "uint32_t", diff --git a/sys/sys/mbuf.h b/sys/sys/mbuf.h index 918fc2699ff4..8243e6cd1295 100644 --- a/sys/sys/mbuf.h +++ b/sys/sys/mbuf.h @@ -65,6 +65,7 @@ SDT_PROBE_DECLARE(sdt, , , m__init); SDT_PROBE_DECLARE(sdt, , , m__gethdr); SDT_PROBE_DECLARE(sdt, , , m__get); SDT_PROBE_DECLARE(sdt, , , m__getcl); +SDT_PROBE_DECLARE(sdt, , , m__getjcl); SDT_PROBE_DECLARE(sdt, , , m__clget); SDT_PROBE_DECLARE(sdt, , , m__cljget); SDT_PROBE_DECLARE(sdt, , , m__cljset); From 6d34415f672536be64cd5f6c2c6c542e9fa9f7f7 Mon Sep 17 00:00:00 2001 From: Gordon Bergling Date: Wed, 5 Aug 2020 11:41:41 +0000 Subject: [PATCH 107/141] environ(7): Update the description and include some more environment variables - Add a better introduction to the DESCRIPTION section - Add a description for MANPATH and POSIXLY_CORRECT - Asorted improvements for the usage of some macros PR: 43823 Submitted by: Lyndon Nerenberg Reviewed by: 0mp, bcr Approved by: 0mp, bcr MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D25912 --- share/man/man7/environ.7 | 74 +++++++++++++++++++++++++++++++++------- 1 file changed, 62 insertions(+), 12 deletions(-) diff --git a/share/man/man7/environ.7 b/share/man/man7/environ.7 index 2d22afbad90a..9a77100ff6d3 100644 --- a/share/man/man7/environ.7 +++ b/share/man/man7/environ.7 @@ -28,7 +28,7 @@ .\" @(#)environ.7 8.3 (Berkeley) 4/19/94 .\" $FreeBSD$ .\" -.Dd February 14, 2020 +.Dd August 5, 2020 .Dt ENVIRON 7 .Os .Sh NAME @@ -37,21 +37,59 @@ .Sh SYNOPSIS .Ar extern char **environ ; .Sh DESCRIPTION -An array of strings called the +An array of strings, called the .Ar environment -is made available by +is made available to each process by .Xr execve 2 when a process begins. By convention these strings have the form -.Dq Ar name=value . -The following names are used by various commands: -.Bl -tag -width LC_MONETARY +.Va name Ns No = Ns Ar value , +and are referred to as +.Dq environment variables . +A process can query, update, and delete these strings using the +.Xr getenv 3 , +.Xr setenv 3 , +and +.Xr unsetenv 3 +functions, respectively. +The shells also provide commands to manipulate the environment; +they are described in the respective shell manual pages. +.Pp +What follows is a list of environment variables typically +seen on a +.Ux +system. +It includes only those variables that a user can expect to see during their +day-to-day use of the system, and is far from complete. +Environment variables specific to a particular program or library function +are documented in the +.Sx ENVIRONMENT +section of the appropriate manual page. +.Sh ENVIRONMENT +.Bl -tag -width LD_LIBRARY_PATH .It Ev BLOCKSIZE -The size of the block units used by several commands, most notably +The size of the block units used by several disk-related commands, +most notably .Xr df 1 , .Xr du 1 and .Xr ls 1 . +.Ev BLOCKSIZE +may be specified in units of a byte by specifying a number, +in units of a kilobyte by specifying a number followed by +.Ql K +or +.Ql k , +in units of a megabyte by specifying a number followed by +.Ql M +or +.Ql m , +and in units of a gigabyte by specifying a number followed +by +.Ql G +or +.Ql g . +Sizes less than 512 bytes or greater than a gigabyte are ignored. This variable is processed by the .Xr getbsize 3 function. @@ -117,6 +155,10 @@ used by .Xr mail 1 , .Xr sh 1 , and many other mail clients. +.It Ev MANPATH +The sequence of directories, separated by colons, searched by +.Xr man 1 +when looking for manual pages. .It Ev NLSPATH List of directories to be searched for the message catalog referred to by .Ev LC_MESSAGES . @@ -139,6 +181,9 @@ etc, when looking for an executable file. .Ev PATH is set to ``/usr/bin:/bin'' initially by .Xr login 1 . +.It Ev POSIXLY_CORRECT +When set to any value, this environment variable modifies the behaviour +of certain commands to (mostly) execute in a strictly POSIX-compliant manner. .It Ev PRINTER The name of the default printer to be used by .Xr lpr 1 , @@ -178,7 +223,7 @@ no is equivalent to a .Ev TERMPATH of -.Dq Pa $HOME/.termcap:/etc/termcap . +.Pa $HOME/.termcap:/etc/termcap . .Ev TERMPATH is ignored if .Ev TERMCAP @@ -186,22 +231,27 @@ contains a full pathname. .It Ev TMPDIR The directory in which to store temporary files. Most applications use either -.Dq /tmp +.Pa /tmp or -.Dq /var/tmp . +.Pa /var/tmp . Setting this variable will make them use another directory. .It Ev TZ The timezone to use when displaying dates. The normal format is a pathname relative to -.Dq Pa /usr/share/zoneinfo . +.Pa /usr/share/zoneinfo . For example, the command -.Dq env TZ=America/Los_Angeles date +.Pp +.Dl env TZ=America/Los_Angeles date +.Pp displays the current time in California. See .Xr tzset 3 for more information. .It Ev USER The login name of the user. +It is recommended that portable applications use +.Ev LOGNAME +instead. .El .Pp Further names may be placed in the environment by the From a134ebd6e63f658f2d3d04ac0c60d23bcaa86dd7 Mon Sep 17 00:00:00 2001 From: "Andrey V. Elsukov" Date: Wed, 5 Aug 2020 11:54:02 +0000 Subject: [PATCH 108/141] Synchronize definitions in mbuf.d with values from mbuf.h Obtained from: Yandex LLC Sponsored by: Yandex LLC --- share/dtrace/mbuf.d | 68 ++++++++++++++++++++++++--------------------- 1 file changed, 37 insertions(+), 31 deletions(-) diff --git a/share/dtrace/mbuf.d b/share/dtrace/mbuf.d index b172daeb413a..0e2f47495472 100644 --- a/share/dtrace/mbuf.d +++ b/share/dtrace/mbuf.d @@ -53,37 +53,41 @@ inline int M_MCAST = 0x00000020; /* send/received as link-level multicast */ inline int M_PROMISC = 0x00000040; /* packet was not for us */ #pragma D binding "1.6.3" M_VLANTAG inline int M_VLANTAG = 0x00000080; /* ether_vtag is valid */ -#pragma D binding "1.6.3" M_UNUSED_8 -inline int M_UNUSED_8 = 0x00000100; /* --available-- */ +#pragma D binding "1.13" M_EXTPG +inline int M_EXTPG = 0x00000100; /* has array of unmapped pages and TLS */ #pragma D binding "1.6.3" M_NOFREE inline int M_NOFREE = 0x00000200; /* do not free mbuf, embedded in cluster */ +#pragma D binding "1.13" M_TSTMP +inline int M_TSTMP = 0x00000400; /* rcv_tstmp field is valid */ +#pragma D binding "1.13" M_TSTMP_HPREC +inline int M_TSTMP_HPREC = 0x00000800; /* rcv_tstmp is high-prec */ +#pragma D binding "1.13" M_TSTMP_LRO +inline int M_TSTMP_LRO = 0x00001000; /* Time LRO pushed in pkt is valid */ + +#pragma D binding "1.13" M_PROTO1 +inline int M_PROTO1 = 0x00002000; /* protocol-specific */ +#pragma D binding "1.13" M_PROTO2 +inline int M_PROTO2 = 0x00004000; /* protocol-specific */ +#pragma D binding "1.13" M_PROTO3 +inline int M_PROTO3 = 0x00008000; /* protocol-specific */ +#pragma D binding "1.13" M_PROTO4 +inline int M_PROTO4 = 0x00010000; /* protocol-specific */ +#pragma D binding "1.13" M_PROTO5 +inline int M_PROTO5 = 0x00020000; /* protocol-specific */ +#pragma D binding "1.13" M_PROTO6 +inline int M_PROTO6 = 0x00040000; /* protocol-specific */ +#pragma D binding "1.13" M_PROTO7 +inline int M_PROTO7 = 0x00080000; /* protocol-specific */ +#pragma D binding "1.13" M_PROTO8 +inline int M_PROTO8 = 0x00100000; /* protocol-specific */ +#pragma D binding "1.13" M_PROTO9 +inline int M_PROTO9 = 0x00200000; /* protocol-specific */ +#pragma D binding "1.13" M_PROTO10 +inline int M_PROTO10 = 0x00400000; /* protocol-specific */ +#pragma D binding "1.13" M_PROTO11 +inline int M_PROTO11 = 0x00800000; /* protocol-specific */ -#pragma D binding "1.6.3" M_PROTO1 -inline int M_PROTO1 = 0x00001000; /* protocol-specific */ -#pragma D binding "1.6.3" M_PROTO2 -inline int M_PROTO2 = 0x00002000; /* protocol-specific */ -#pragma D binding "1.6.3" M_PROTO3 -inline int M_PROTO3 = 0x00004000; /* protocol-specific */ -#pragma D binding "1.6.3" M_PROTO4 -inline int M_PROTO4 = 0x00008000; /* protocol-specific */ -#pragma D binding "1.6.3" M_PROTO5 -inline int M_PROTO5 = 0x00010000; /* protocol-specific */ -#pragma D binding "1.6.3" M_PROTO6 -inline int M_PROTO6 = 0x00020000; /* protocol-specific */ -#pragma D binding "1.6.3" M_PROTO7 -inline int M_PROTO7 = 0x00040000; /* protocol-specific */ -#pragma D binding "1.6.3" M_PROTO8 -inline int M_PROTO8 = 0x00080000; /* protocol-specific */ -#pragma D binding "1.6.3" M_PROTO9 -inline int M_PROTO9 = 0x00100000; /* protocol-specific */ -#pragma D binding "1.6.3" M_PROTO10 -inline int M_PROTO10 = 0x00200000; /* protocol-specific */ -#pragma D binding "1.6.3" M_PROTO11 -inline int M_PROTO11 = 0x00400000; /* protocol-specific */ -#pragma D binding "1.6.3" M_PROTO12 -inline int M_PROTO12 = 0x00800000; /* protocol-specific */ - -#pragma D binding "1.6.3" mbufflags_string +#pragma D binding "1.13" mbufflags_string inline string mbufflags_string[uint32_t flags] = flags & M_EXT ? "M_EXT" : flags & M_PKTHDR ? "M_PKTHDR" : @@ -93,8 +97,11 @@ inline string mbufflags_string[uint32_t flags] = flags & M_MCAST ? "M_MCAST" : flags & M_PROMISC ? "M_PROMISC" : flags & M_VLANTAG ? "M_VLANTAG" : - flags & M_UNUSED_8 ? "M_UNUSED_8" : - flags & M_NOFREE ? "M_NOFREE" : + flags & M_EXTPG ? "M_EXTPG" : + flags & M_NOFREE ? "M_NOFREE" : + flags & M_TSTMP ? "M_TSTMP" : + flags & M_TSTMP_HPREC ? "M_TSTMP_HPREC" : + flags & M_TSTMP_LRO ? "M_TSTMP_LRO" : flags & M_PROTO1 ? "M_PROTO1" : flags & M_PROTO2 ? "M_PROTO2" : flags & M_PROTO3 ? "M_PROTO3" : @@ -106,7 +113,6 @@ inline string mbufflags_string[uint32_t flags] = flags & M_PROTO9 ? "M_PROTO9" : flags & M_PROTO10 ? "M_PROTO10" : flags & M_PROTO11 ? "M_PROTO11" : - flags & M_PROTO12 ? "M_PROTO12" : "none" ; typedef struct mbufinfo { From c085d2ea97f4427be3204720032ead3a21cb2c94 Mon Sep 17 00:00:00 2001 From: Andrew Turner Date: Wed, 5 Aug 2020 11:54:51 +0000 Subject: [PATCH 109/141] Add DDB_CTF to the arm64 and riscv kernel configs This allows DTrace fbt probes to find arguments. Sponsored by: Innovate UK --- sys/arm64/conf/GENERIC | 1 + sys/riscv/conf/GENERIC | 1 + 2 files changed, 2 insertions(+) diff --git a/sys/arm64/conf/GENERIC b/sys/arm64/conf/GENERIC index 311a1ae0dbbc..7cf5831a39fa 100644 --- a/sys/arm64/conf/GENERIC +++ b/sys/arm64/conf/GENERIC @@ -72,6 +72,7 @@ options CAPABILITIES # Capsicum capabilities options MAC # TrustedBSD MAC Framework options KDTRACE_FRAME # Ensure frames are compiled in options KDTRACE_HOOKS # Kernel DTrace hooks +options DDB_CTF # Kernel ELF linker loads CTF data options VFP # Floating-point support options RACCT # Resource accounting framework options RACCT_DEFAULT_TO_DISABLED # Set kern.racct.enable=0 by default diff --git a/sys/riscv/conf/GENERIC b/sys/riscv/conf/GENERIC index 7caee97e7912..377420183177 100644 --- a/sys/riscv/conf/GENERIC +++ b/sys/riscv/conf/GENERIC @@ -67,6 +67,7 @@ options CAPABILITIES # Capsicum capabilities options MAC # TrustedBSD MAC Framework options KDTRACE_FRAME # Ensure frames are compiled in options KDTRACE_HOOKS # Kernel DTrace hooks +options DDB_CTF # Kernel ELF linker loads CTF data options FPE # Floating-point extension support options RACCT # Resource accounting framework options RACCT_DEFAULT_TO_DISABLED # Set kern.racct.enable=0 by default From 491ceb65ec22261b9060b42edeb910881d4fe347 Mon Sep 17 00:00:00 2001 From: Toomas Soome Date: Wed, 5 Aug 2020 14:08:44 +0000 Subject: [PATCH 110/141] zfs_keys_nextboot array is missing ZPOOL_CONFIG_POOL_GUID and ZPOOL_CONFIG_GUID As we do check the incomint nvlist, we either need to list all possible keys or use wildcard. PR: 248462 Reported by: larafercue@gmail.com Sponsored by: Netflix, Klara Inc. --- sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c index 46dbb9f5cf1c..3cb58c5d4360 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c @@ -3656,7 +3656,9 @@ zfs_ioc_log_history(const char *unused, nvlist_t *innvl, nvlist_t *outnvl) #ifdef __FreeBSD__ static const zfs_ioc_key_t zfs_keys_nextboot[] = { - {"command", DATA_TYPE_STRING, 0}, + {"command", DATA_TYPE_STRING, 0}, + {ZPOOL_CONFIG_POOL_GUID, DATA_TYPE_UINT64, 0}, + {ZPOOL_CONFIG_GUID, DATA_TYPE_UINT64, 0} }; static int From 722c2b4acaa88c0e6f41c30c5d5c355260b2a4b2 Mon Sep 17 00:00:00 2001 From: Toomas Soome Date: Wed, 5 Aug 2020 14:32:20 +0000 Subject: [PATCH 111/141] MFOpenZFS: Add support for boot environment data to be stored in the label We are building new bootonce mechanism (previously zfs bootnext) and it is based on this OpenZFS change. Since this patch is nicely self contained, I am commiting it as is, and we can stack our changes. Original patch description follows: Modern bootloaders leverage data stored in the root filesystem to enable some of their powerful features. GRUB specifically has a grubenv file which can store large amounts of configuration data that can be read and written at boot time and during normal operation. This allows sysadmins to configure useful features like automated failover after failed boot attempts. Unfortunately, due to the Copy-on-Write nature of ZFS, the standard behavior of these tools cannot handle writing to ZFS files safely at boot time. We need an alternative way to store data that allows the bootloader to make changes to the data. This work is very similar to work that was done on Illumos to enable similar functionality in the FreeBSD bootloader. This patch is different in that the data being stored is a raw grubenv file; this file can store arbitrary variables and values, and the scripting provided by grub is powerful enough that special structures are not required to implement advanced behavior. We repurpose the second padding area in each label to store the grubenv file, protected by an embedded checksum. We add two ioctls to get and set this data, and libzfs_core and libzfs functions to access them more easily. There are no direct command line interfaces to these functions; these will be added directly to the bootloader utilities. Reviewed-by: Pavel Zakharov Reviewed-by: Matthew Ahrens Reviewed-by: Brian Behlendorf Signed-off-by: Paul Dagnelie Closes #10009 Obtained from: OpenZFS Sponsored by: Netflix, Klara Inc. --- .../opensolaris/cmd/zinject/translate.c | 4 +- .../opensolaris/lib/libzfs/common/libzfs.h | 2 + .../lib/libzfs/common/libzfs_pool.c | 40 ++++- .../lib/libzfs_core/common/libzfs_core.c | 24 ++- .../lib/libzfs_core/common/libzfs_core.h | 4 +- .../opensolaris/uts/common/fs/zfs/sys/vdev.h | 4 +- .../uts/common/fs/zfs/sys/vdev_impl.h | 26 ++- .../opensolaris/uts/common/fs/zfs/vdev.c | 2 +- .../uts/common/fs/zfs/vdev_label.c | 158 +++++++++++++++++- .../opensolaris/uts/common/fs/zfs/zfs_ioctl.c | 62 +++++++ .../opensolaris/uts/common/sys/fs/zfs.h | 4 +- 11 files changed, 310 insertions(+), 20 deletions(-) diff --git a/cddl/contrib/opensolaris/cmd/zinject/translate.c b/cddl/contrib/opensolaris/cmd/zinject/translate.c index af25d3c3c17d..99a3d0ca4ff3 100644 --- a/cddl/contrib/opensolaris/cmd/zinject/translate.c +++ b/cddl/contrib/opensolaris/cmd/zinject/translate.c @@ -20,7 +20,7 @@ */ /* * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012 by Delphix. All rights reserved. + * Copyright (c) 2012, 2020 by Delphix. All rights reserved. */ #include @@ -484,7 +484,7 @@ translate_device(const char *pool, const char *device, err_type_t label_type, record->zi_end = record->zi_start + VDEV_PAD_SIZE - 1; break; case TYPE_LABEL_PAD2: - record->zi_start = offsetof(vdev_label_t, vl_pad2); + record->zi_start = offsetof(vdev_label_t, vl_be); record->zi_end = record->zi_start + VDEV_PAD_SIZE - 1; break; } diff --git a/cddl/contrib/opensolaris/lib/libzfs/common/libzfs.h b/cddl/contrib/opensolaris/lib/libzfs/common/libzfs.h index 469d61f5e773..1899e318d53e 100644 --- a/cddl/contrib/opensolaris/lib/libzfs/common/libzfs.h +++ b/cddl/contrib/opensolaris/lib/libzfs/common/libzfs.h @@ -837,6 +837,8 @@ extern int zpool_in_use(libzfs_handle_t *, int, pool_state_t *, char **, extern int zpool_read_label(int, nvlist_t **); extern int zpool_read_all_labels(int, nvlist_t **); extern int zpool_clear_label(int); +extern int zpool_set_bootenv(zpool_handle_t *, const char *); +extern int zpool_get_bootenv(zpool_handle_t *, char *, size_t, off_t); /* is this zvol valid for use as a dump device? */ extern int zvol_check_dump_config(char *); diff --git a/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_pool.c b/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_pool.c index 39b6c35f6fbd..434f77e27da9 100644 --- a/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_pool.c +++ b/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_pool.c @@ -21,7 +21,7 @@ /* * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2011, 2017 by Delphix. All rights reserved. + * Copyright (c) 2011, 2020 by Delphix. All rights reserved. * Copyright (c) 2013, Joyent, Inc. All rights reserved. * Copyright 2016 Nexenta Systems, Inc. * Copyright 2016 Igor Kozhukhov @@ -395,7 +395,7 @@ zpool_get_prop(zpool_handle_t *zhp, zpool_prop_t prop, char *buf, size_t len, * Assuming bootfs is a valid dataset name. */ static boolean_t -bootfs_name_valid(const char *pool, char *bootfs) +bootfs_name_valid(const char *pool, const char *bootfs) { int len = strlen(pool); @@ -4233,6 +4233,42 @@ zpool_obj_to_path(zpool_handle_t *zhp, uint64_t dsobj, uint64_t obj, free(mntpnt); } +int +zpool_set_bootenv(zpool_handle_t *zhp, const char *envmap) +{ + int error = lzc_set_bootenv(zhp->zpool_name, envmap); + if (error != 0) { + (void) zpool_standard_error_fmt(zhp->zpool_hdl, error, + dgettext(TEXT_DOMAIN, + "error setting bootenv in pool '%s'"), zhp->zpool_name); + } + + return (error); +} + +int +zpool_get_bootenv(zpool_handle_t *zhp, char *outbuf, size_t size, off_t offset) +{ + nvlist_t *nvl; + int error = lzc_get_bootenv(zhp->zpool_name, &nvl);; + if (error != 0) { + (void) zpool_standard_error_fmt(zhp->zpool_hdl, error, + dgettext(TEXT_DOMAIN, + "error getting bootenv in pool '%s'"), zhp->zpool_name); + return (-1); + } + char *envmap = fnvlist_lookup_string(nvl, "envmap"); + if (offset >= strlen(envmap)) { + fnvlist_free(nvl); + return (0); + } + + strlcpy(outbuf, envmap + offset, size); + int bytes = MIN(strlen(envmap + offset), size); + fnvlist_free(nvl); + return (bytes); +} + #ifdef illumos /* * Read the EFI label from the config, if a label does not exist then diff --git a/cddl/contrib/opensolaris/lib/libzfs_core/common/libzfs_core.c b/cddl/contrib/opensolaris/lib/libzfs_core/common/libzfs_core.c index f4ed52a29232..2a6b5cc5927c 100644 --- a/cddl/contrib/opensolaris/lib/libzfs_core/common/libzfs_core.c +++ b/cddl/contrib/opensolaris/lib/libzfs_core/common/libzfs_core.c @@ -20,7 +20,7 @@ */ /* - * Copyright (c) 2012, 2018 by Delphix. All rights reserved. + * Copyright (c) 2012, 2020 by Delphix. All rights reserved. * Copyright (c) 2013 Steven Hartland. All rights reserved. * Copyright (c) 2014 Integros [integros.com] * Copyright 2017 RackTop Systems. @@ -1210,3 +1210,25 @@ lzc_initialize(const char *poolname, pool_initialize_func_t cmd_type, return (error); } + +/* + * Set the bootenv contents for the given pool. + */ +int +lzc_set_bootenv(const char *pool, const char *env) +{ + nvlist_t *args = fnvlist_alloc(); + fnvlist_add_string(args, "envmap", env); + int error = lzc_ioctl(ZFS_IOC_SET_BOOTENV, pool, args, NULL); + fnvlist_free(args); + return (error); +} + +/* + * Get the contents of the bootenv of the given pool. + */ +int +lzc_get_bootenv(const char *pool, nvlist_t **outnvl) +{ + return (lzc_ioctl(ZFS_IOC_GET_BOOTENV, pool, NULL, outnvl)); +} diff --git a/cddl/contrib/opensolaris/lib/libzfs_core/common/libzfs_core.h b/cddl/contrib/opensolaris/lib/libzfs_core/common/libzfs_core.h index 97d7ce81d8ab..76c4fa1bf6b4 100644 --- a/cddl/contrib/opensolaris/lib/libzfs_core/common/libzfs_core.h +++ b/cddl/contrib/opensolaris/lib/libzfs_core/common/libzfs_core.h @@ -20,7 +20,7 @@ */ /* - * Copyright (c) 2012, 2016 by Delphix. All rights reserved. + * Copyright (c) 2012, 2020 by Delphix. All rights reserved. * Copyright (c) 2013 by Martin Matuska . All rights reserved. * Copyright 2017 RackTop Systems. * Copyright (c) 2017 Datto Inc. @@ -105,6 +105,8 @@ int lzc_channel_program_nosync(const char *, const char *, uint64_t, int lzc_pool_checkpoint(const char *); int lzc_pool_checkpoint_discard(const char *); +int lzc_set_bootenv(const char *, const char *); +int lzc_get_bootenv(const char *, nvlist_t **); #ifdef __cplusplus } #endif diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/vdev.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/vdev.h index f1a39ef48ecc..0bb266873c6c 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/vdev.h +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/vdev.h @@ -21,7 +21,7 @@ /* * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2011, 2017 by Delphix. All rights reserved. + * Copyright (c) 2011, 2020 by Delphix. All rights reserved. * Copyright (c) 2017, Intel Corporation. */ @@ -173,6 +173,8 @@ extern nvlist_t *vdev_label_read_config(vdev_t *vd, uint64_t txg); extern void vdev_uberblock_load(vdev_t *, struct uberblock *, nvlist_t **); extern void vdev_label_write(zio_t *zio, vdev_t *vd, int l, abd_t *buf, uint64_t offset, uint64_t size, zio_done_func_t *done, void *priv, int flags); +extern int vdev_label_read_bootenv(vdev_t *, nvlist_t *); +extern int vdev_label_write_bootenv(vdev_t *, char *); typedef enum { VDEV_LABEL_CREATE, /* create/add a new device */ diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/vdev_impl.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/vdev_impl.h index 5baac4852116..e40335fc73ae 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/vdev_impl.h +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/vdev_impl.h @@ -20,7 +20,7 @@ */ /* * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2011, 2018 by Delphix. All rights reserved. + * Copyright (c) 2011, 2020 by Delphix. All rights reserved. * Copyright (c) 2017, Intel Corporation. */ @@ -392,7 +392,7 @@ struct vdev { #define VDEV_RAIDZ_MAXPARITY 3 #define VDEV_PAD_SIZE (8 << 10) -/* 2 padding areas (vl_pad1 and vl_pad2) to skip */ +/* 2 padding areas (vl_pad1 and vl_be) to skip */ #define VDEV_SKIP_SIZE VDEV_PAD_SIZE * 2 #define VDEV_PHYS_SIZE (112 << 10) #define VDEV_UBERBLOCK_RING (128 << 10) @@ -419,9 +419,29 @@ typedef struct vdev_phys { zio_eck_t vp_zbt; } vdev_phys_t; +typedef enum vbe_vers { + /* The bootenv file is stored as ascii text in the envblock */ + VB_RAW = 0, + + /* + * The bootenv file is converted to an nvlist and then packed into the + * envblock. + */ + VB_NVLIST = 1 +} vbe_vers_t; + +typedef struct vdev_boot_envblock { + uint64_t vbe_version; + char vbe_bootenv[VDEV_PAD_SIZE - sizeof (uint64_t) - + sizeof (zio_eck_t)]; + zio_eck_t vbe_zbt; +} vdev_boot_envblock_t; + +CTASSERT(sizeof (vdev_boot_envblock_t) == VDEV_PAD_SIZE); + typedef struct vdev_label { char vl_pad1[VDEV_PAD_SIZE]; /* 8K */ - char vl_pad2[VDEV_PAD_SIZE]; /* 8K */ + vdev_boot_envblock_t vl_be; /* 8K */ vdev_phys_t vl_vdev_phys; /* 112K */ char vl_uberblock[VDEV_UBERBLOCK_RING]; /* 128K */ } vdev_label_t; /* 256K total */ diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev.c index c1b2ebc1db1a..6043adee0241 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev.c @@ -1566,7 +1566,7 @@ vdev_probe(vdev_t *vd, zio_t *zio) for (int l = 1; l < VDEV_LABELS; l++) { zio_nowait(zio_read_phys(pio, vd, vdev_label_offset(vd->vdev_psize, l, - offsetof(vdev_label_t, vl_pad2)), VDEV_PAD_SIZE, + offsetof(vdev_label_t, vl_be)), VDEV_PAD_SIZE, abd_alloc_for_io(VDEV_PAD_SIZE, B_TRUE), ZIO_CHECKSUM_OFF, vdev_probe_done, vps, ZIO_PRIORITY_SYNC_READ, vps->vps_flags, B_TRUE)); diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c index fcb5241f3fcc..0b777c8870c5 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c @@ -21,7 +21,7 @@ /* * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2012, 2018 by Delphix. All rights reserved. + * Copyright (c) 2012, 2020 by Delphix. All rights reserved. * Copyright (c) 2017, Intel Corporation. * Copyright 2019 Joyent, Inc. */ @@ -781,7 +781,7 @@ vdev_label_init(vdev_t *vd, uint64_t crtxg, vdev_labeltype_t reason) nvlist_t *label; vdev_phys_t *vp; abd_t *vp_abd; - abd_t *pad2; + abd_t *bootenv; uberblock_t *ub; abd_t *ub_abd; zio_t *zio; @@ -956,8 +956,8 @@ vdev_label_init(vdev_t *vd, uint64_t crtxg, vdev_labeltype_t reason) ub->ub_txg = 0; /* Initialize the 2nd padding area. */ - pad2 = abd_alloc_for_io(VDEV_PAD_SIZE, B_TRUE); - abd_zero(pad2, VDEV_PAD_SIZE); + bootenv = abd_alloc_for_io(VDEV_PAD_SIZE, B_TRUE); + abd_zero(bootenv, VDEV_PAD_SIZE); /* * Write everything in parallel. @@ -976,8 +976,8 @@ vdev_label_init(vdev_t *vd, uint64_t crtxg, vdev_labeltype_t reason) * Zero out the 2nd padding area where it might have * left over data from previous filesystem format. */ - vdev_label_write(zio, vd, l, pad2, - offsetof(vdev_label_t, vl_pad2), + vdev_label_write(zio, vd, l, bootenv, + offsetof(vdev_label_t, vl_be), VDEV_PAD_SIZE, NULL, NULL, flags); vdev_label_write(zio, vd, l, ub_abd, @@ -993,7 +993,7 @@ vdev_label_init(vdev_t *vd, uint64_t crtxg, vdev_labeltype_t reason) } nvlist_free(label); - abd_free(pad2); + abd_free(bootenv); abd_free(ub_abd); abd_free(vp_abd); @@ -1016,6 +1016,148 @@ vdev_label_init(vdev_t *vd, uint64_t crtxg, vdev_labeltype_t reason) return (error); } +/* + * Done callback for vdev_label_read_bootenv_impl. If this is the first + * callback to finish, store our abd in the callback pointer. Otherwise, we + * just free our abd and return. + */ +static void +vdev_label_read_bootenv_done(zio_t *zio) +{ + zio_t *rio = zio->io_private; + abd_t **cbp = rio->io_private; + + ASSERT3U(zio->io_size, ==, VDEV_PAD_SIZE); + + if (zio->io_error == 0) { + mutex_enter(&rio->io_lock); + if (*cbp == NULL) { + /* Will free this buffer in vdev_label_read_bootenv. */ + *cbp = zio->io_abd; + } else { + abd_free(zio->io_abd); + } + mutex_exit(&rio->io_lock); + } else { + abd_free(zio->io_abd); + } +} + +static void +vdev_label_read_bootenv_impl(zio_t *zio, vdev_t *vd, int flags) +{ + for (int c = 0; c < vd->vdev_children; c++) + vdev_label_read_bootenv_impl(zio, vd->vdev_child[c], flags); + + /* + * We just use the first label that has a correct checksum; the + * bootloader should have rewritten them all to be the same on boot, + * and any changes we made since boot have been the same across all + * labels. + * + * While grub supports writing to all four labels, other bootloaders + * don't, so we only use the first two labels to store boot + * information. + */ + if (vd->vdev_ops->vdev_op_leaf && vdev_readable(vd)) { + for (int l = 0; l < VDEV_LABELS / 2; l++) { + vdev_label_read(zio, vd, l, + abd_alloc_linear(VDEV_PAD_SIZE, B_FALSE), + offsetof(vdev_label_t, vl_be), VDEV_PAD_SIZE, + vdev_label_read_bootenv_done, zio, flags); + } + } +} + +int +vdev_label_read_bootenv(vdev_t *rvd, nvlist_t *command) +{ + spa_t *spa = rvd->vdev_spa; + abd_t *abd = NULL; + int flags = ZIO_FLAG_CONFIG_WRITER | ZIO_FLAG_CANFAIL | + ZIO_FLAG_SPECULATIVE | ZIO_FLAG_TRYHARD; + + ASSERT(command); + ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL); + + zio_t *zio = zio_root(spa, NULL, &abd, flags); + vdev_label_read_bootenv_impl(zio, rvd, flags); + int err = zio_wait(zio); + + if (abd != NULL) { + vdev_boot_envblock_t *vbe = abd_to_buf(abd); + if (vbe->vbe_version != VB_RAW) { + abd_free(abd); + return (SET_ERROR(ENOTSUP)); + } + vbe->vbe_bootenv[sizeof (vbe->vbe_bootenv) - 1] = '\0'; + fnvlist_add_string(command, "envmap", vbe->vbe_bootenv); + /* abd was allocated in vdev_label_read_bootenv_impl() */ + abd_free(abd); + /* If we managed to read any successfully, return success. */ + return (0); + } + return (err); +} + +int +vdev_label_write_bootenv(vdev_t *vd, char *envmap) +{ + zio_t *zio; + spa_t *spa = vd->vdev_spa; + vdev_boot_envblock_t *bootenv; + int flags = ZIO_FLAG_CONFIG_WRITER | ZIO_FLAG_CANFAIL; + int error = ENXIO; + + if (strlen(envmap) >= sizeof (bootenv->vbe_bootenv)) { + return (SET_ERROR(E2BIG)); + } + + ASSERT(spa_config_held(spa, SCL_ALL, RW_WRITER) == SCL_ALL); + + for (int c = 0; c < vd->vdev_children; c++) { + int child_err = vdev_label_write_bootenv(vd->vdev_child[c], + envmap); + /* + * As long as any of the disks managed to write all of their + * labels successfully, return success. + */ + if (child_err == 0) + error = child_err; + } + + if (!vd->vdev_ops->vdev_op_leaf || vdev_is_dead(vd) || + !vdev_writeable(vd)) { + return (error); + } + ASSERT3U(sizeof (*bootenv), ==, VDEV_PAD_SIZE); + abd_t *abd = abd_alloc_for_io(VDEV_PAD_SIZE, B_TRUE); + abd_zero(abd, VDEV_PAD_SIZE); + bootenv = abd_borrow_buf_copy(abd, VDEV_PAD_SIZE); + + char *buf = bootenv->vbe_bootenv; + (void) strlcpy(buf, envmap, sizeof (bootenv->vbe_bootenv)); + bootenv->vbe_version = VB_RAW; + abd_return_buf_copy(abd, bootenv, VDEV_PAD_SIZE); + +retry: + zio = zio_root(spa, NULL, NULL, flags); + for (int l = 0; l < VDEV_LABELS / 2; l++) { + vdev_label_write(zio, vd, l, abd, + offsetof(vdev_label_t, vl_be), + VDEV_PAD_SIZE, NULL, NULL, flags); + } + + error = zio_wait(zio); + if (error != 0 && !(flags & ZIO_FLAG_TRYHARD)) { + flags |= ZIO_FLAG_TRYHARD; + goto retry; + } + + abd_free(abd); + return (error); +} + int vdev_label_write_pad2(vdev_t *vd, const char *buf, size_t size) { @@ -1042,7 +1184,7 @@ vdev_label_write_pad2(vdev_t *vd, const char *buf, size_t size) retry: zio = zio_root(spa, NULL, NULL, flags); vdev_label_write(zio, vd, 0, pad2, - offsetof(vdev_label_t, vl_pad2), + offsetof(vdev_label_t, vl_be), VDEV_PAD_SIZE, NULL, NULL, flags); error = zio_wait(zio); if (error != 0 && !(flags & ZIO_FLAG_TRYHARD)) { diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c index 3cb58c5d4360..a7e2aff6e683 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c +++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c @@ -3654,6 +3654,58 @@ zfs_ioc_log_history(const char *unused, nvlist_t *innvl, nvlist_t *outnvl) return (error); } +/* + * This ioctl is used to set the bootenv configuration on the current + * pool. This configuration is stored in the second padding area of the label, + * and it is used by the GRUB bootloader used on Linux to store the contents + * of the grubenv file. The file is stored as raw ASCII, and is protected by + * an embedded checksum. By default, GRUB will check if the boot filesystem + * supports storing the environment data in a special location, and if so, + * will invoke filesystem specific logic to retrieve it. This can be overriden + * by a variable, should the user so desire. + */ +/* ARGSUSED */ +static const zfs_ioc_key_t zfs_keys_set_bootenv[] = { + {"envmap", DATA_TYPE_STRING, 0}, +}; + +static int +zfs_ioc_set_bootenv(const char *name, nvlist_t *innvl, nvlist_t *outnvl) +{ + char *envmap; + int error; + spa_t *spa; + + envmap = fnvlist_lookup_string(innvl, "envmap"); + if ((error = spa_open(name, &spa, FTAG)) != 0) + return (error); + spa_vdev_state_enter(spa, SCL_ALL); + error = vdev_label_write_bootenv(spa->spa_root_vdev, envmap); + (void) spa_vdev_state_exit(spa, NULL, 0); + spa_close(spa, FTAG); + return (error); +} + +static const zfs_ioc_key_t zfs_keys_get_bootenv[] = { + /* no nvl keys */ +}; + + /* ARGSUSED */ +static int +zfs_ioc_get_bootenv(const char *name, nvlist_t *innvl, nvlist_t *outnvl) +{ + spa_t *spa; + int error; + + if ((error = spa_open(name, &spa, FTAG)) != 0) + return (error); + spa_vdev_state_enter(spa, SCL_ALL); + error = vdev_label_read_bootenv(spa->spa_root_vdev, outnvl); + (void) spa_vdev_state_exit(spa, NULL, 0); + spa_close(spa, FTAG); + return (error); +} + #ifdef __FreeBSD__ static const zfs_ioc_key_t zfs_keys_nextboot[] = { {"command", DATA_TYPE_STRING, 0}, @@ -6567,6 +6619,16 @@ zfs_ioctl_init(void) zfs_secpolicy_config, POOL_NAME, POOL_CHECK_SUSPENDED, B_TRUE, B_TRUE, zfs_keys_pool_reopen, ARRAY_SIZE(zfs_keys_pool_reopen)); + zfs_ioctl_register("set_bootenv", ZFS_IOC_SET_BOOTENV, + zfs_ioc_set_bootenv, zfs_secpolicy_config, POOL_NAME, + POOL_CHECK_SUSPENDED | POOL_CHECK_READONLY, B_FALSE, B_TRUE, + zfs_keys_set_bootenv, ARRAY_SIZE(zfs_keys_set_bootenv)); + + zfs_ioctl_register("get_bootenv", ZFS_IOC_GET_BOOTENV, + zfs_ioc_get_bootenv, zfs_secpolicy_none, POOL_NAME, + POOL_CHECK_SUSPENDED, B_FALSE, B_TRUE, + zfs_keys_get_bootenv, ARRAY_SIZE(zfs_keys_get_bootenv)); + /* IOCTLS that use the legacy function signature */ zfs_ioctl_register_legacy(ZFS_IOC_POOL_FREEZE, zfs_ioc_pool_freeze, diff --git a/sys/cddl/contrib/opensolaris/uts/common/sys/fs/zfs.h b/sys/cddl/contrib/opensolaris/uts/common/sys/fs/zfs.h index 8a6e534a421d..db23bbe01b9f 100644 --- a/sys/cddl/contrib/opensolaris/uts/common/sys/fs/zfs.h +++ b/sys/cddl/contrib/opensolaris/uts/common/sys/fs/zfs.h @@ -21,7 +21,7 @@ /* * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. - * Copyright (c) 2011, 2018 by Delphix. All rights reserved. + * Copyright (c) 2011, 2020 by Delphix. All rights reserved. * Copyright 2011 Nexenta Systems, Inc. All rights reserved. * Copyright (c) 2012, Martin Matuska . All rights reserved. * Copyright (c) 2014 Integros [integros.com] @@ -1057,6 +1057,8 @@ typedef enum zfs_ioc { ZFS_IOC_POOL_DISCARD_CHECKPOINT, ZFS_IOC_POOL_INITIALIZE, ZFS_IOC_POOL_SYNC, + ZFS_IOC_SET_BOOTENV, + ZFS_IOC_GET_BOOTENV, ZFS_IOC_LAST } zfs_ioc_t; From a5849fa4abcd508792b00400320b39c1499150b0 Mon Sep 17 00:00:00 2001 From: Cy Schubert Date: Wed, 5 Aug 2020 15:33:32 +0000 Subject: [PATCH 112/141] Continued ipfilter #ifdef cleanup. The r343701 log entry contains a complete description. MFC after: 1 week --- contrib/ipfilter/iplang/iplang_y.y | 30 ------------------------------ 1 file changed, 30 deletions(-) diff --git a/contrib/ipfilter/iplang/iplang_y.y b/contrib/ipfilter/iplang/iplang_y.y index f223b1eb8b32..b4570d390530 100644 --- a/contrib/ipfilter/iplang/iplang_y.y +++ b/contrib/ipfilter/iplang/iplang_y.y @@ -30,11 +30,9 @@ #include #include #include -#ifndef linux # include # include # include -#endif #include #include #include @@ -589,28 +587,6 @@ struct statetoopt tosecopts[] = { { 0, 0 } }; -#ifdef bsdi -struct ether_addr * -ether_aton(s) - char *s; -{ - static struct ether_addr n; - u_int i[6]; - - if (sscanf(s, " %x:%x:%x:%x:%x:%x ", &i[0], &i[1], - &i[2], &i[3], &i[4], &i[5]) == 6) { - n.ether_addr_octet[0] = (u_char)i[0]; - n.ether_addr_octet[1] = (u_char)i[1]; - n.ether_addr_octet[2] = (u_char)i[2]; - n.ether_addr_octet[3] = (u_char)i[3]; - n.ether_addr_octet[4] = (u_char)i[4]; - n.ether_addr_octet[5] = (u_char)i[5]; - return &n; - } - return NULL; -} -#endif - struct in_addr getipv4addr(arg) char *arg; @@ -645,7 +621,6 @@ struct ether_addr *buf; { struct ether_addr *e; -#if !defined(hpux) && !defined(linux) e = ether_aton(arg); if (!e) fprintf(stderr, "Invalid ethernet address: %s\n", arg); @@ -657,9 +632,6 @@ struct ether_addr *buf; sizeof(e->ether_addr_octet)); # endif return e; -#else - return NULL; -#endif } @@ -1584,9 +1556,7 @@ int arg; void set_icmpmtu(arg) int arg; { -#if BSD >= 199306 icmp->icmp_nextmtu = htons(arg); -#endif } From 1b1428dcc82b54b7a2c332680d2f66945bf9899b Mon Sep 17 00:00:00 2001 From: Mark Johnston Date: Wed, 5 Aug 2020 17:06:14 +0000 Subject: [PATCH 113/141] Fix a TOCTOU vulnerability in freebsd32_copyin_control(). PR: 248257 Reported by: m00nbsd working with Trend Micro Zero Day Initiative Reviewed by: kib Security: SA-20:23.sendmsg Security: CVE-2020-7460 Security: ZDI-CAN-11543 --- sys/compat/freebsd32/freebsd32_misc.c | 130 ++++++++++++++------------ 1 file changed, 71 insertions(+), 59 deletions(-) diff --git a/sys/compat/freebsd32/freebsd32_misc.c b/sys/compat/freebsd32/freebsd32_misc.c index e16ca1e7e055..7b5671143f52 100644 --- a/sys/compat/freebsd32/freebsd32_misc.c +++ b/sys/compat/freebsd32/freebsd32_misc.c @@ -1449,78 +1449,90 @@ freebsd32_recvmsg(td, uap) static int freebsd32_copyin_control(struct mbuf **mp, caddr_t buf, u_int buflen) { + struct cmsghdr *cm; struct mbuf *m; - void *md; - u_int idx, len, msglen; + void *in, *in1, *md; + u_int msglen, outlen; int error; - buflen = FREEBSD32_ALIGN(buflen); - if (buflen > MCLBYTES) return (EINVAL); + in = malloc(buflen, M_TEMP, M_WAITOK); + error = copyin(buf, in, buflen); + if (error != 0) + goto out; + /* - * Iterate over the buffer and get the length of each message - * in there. This has 32-bit alignment and padding. Use it to - * determine the length of these messages when using 64-bit - * alignment and padding. + * Make a pass over the input buffer to determine the amount of space + * required for 64 bit-aligned copies of the control messages. */ - idx = 0; - len = 0; - while (idx < buflen) { - error = copyin(buf + idx, &msglen, sizeof(msglen)); - if (error) - return (error); - if (msglen < sizeof(struct cmsghdr)) - return (EINVAL); - msglen = FREEBSD32_ALIGN(msglen); - if (idx + msglen > buflen) - return (EINVAL); - idx += msglen; - msglen += CMSG_ALIGN(sizeof(struct cmsghdr)) - - FREEBSD32_ALIGN(sizeof(struct cmsghdr)); - len += CMSG_ALIGN(msglen); - } - - if (len > MCLBYTES) - return (EINVAL); - - m = m_get(M_WAITOK, MT_CONTROL); - if (len > MLEN) - MCLGET(m, M_WAITOK); - m->m_len = len; - - md = mtod(m, void *); + in1 = in; + outlen = 0; while (buflen > 0) { - error = copyin(buf, md, sizeof(struct cmsghdr)); - if (error) + if (buflen < sizeof(*cm)) { + error = EINVAL; break; - msglen = *(u_int *)md; - msglen = FREEBSD32_ALIGN(msglen); - - /* Modify the message length to account for alignment. */ - *(u_int *)md = msglen + CMSG_ALIGN(sizeof(struct cmsghdr)) - - FREEBSD32_ALIGN(sizeof(struct cmsghdr)); - - md = (char *)md + CMSG_ALIGN(sizeof(struct cmsghdr)); - buf += FREEBSD32_ALIGN(sizeof(struct cmsghdr)); - buflen -= FREEBSD32_ALIGN(sizeof(struct cmsghdr)); - - msglen -= FREEBSD32_ALIGN(sizeof(struct cmsghdr)); - if (msglen > 0) { - error = copyin(buf, md, msglen); - if (error) - break; - md = (char *)md + CMSG_ALIGN(msglen); - buf += msglen; - buflen -= msglen; } + cm = (struct cmsghdr *)in1; + if (cm->cmsg_len < FREEBSD32_ALIGN(sizeof(*cm))) { + error = EINVAL; + break; + } + msglen = FREEBSD32_ALIGN(cm->cmsg_len); + if (msglen > buflen || msglen < cm->cmsg_len) { + error = EINVAL; + break; + } + buflen -= msglen; + + in1 = (char *)in1 + msglen; + outlen += CMSG_ALIGN(sizeof(*cm)) + + CMSG_ALIGN(msglen - FREEBSD32_ALIGN(sizeof(*cm))); + } + if (error == 0 && outlen > MCLBYTES) { + /* + * XXXMJ This implies that the upper limit on 32-bit aligned + * control messages is less than MCLBYTES, and so we are not + * perfectly compatible. However, there is no platform + * guarantee that mbuf clusters larger than MCLBYTES can be + * allocated. + */ + error = EINVAL; + } + if (error != 0) + goto out; + + m = m_get2(outlen, M_WAITOK, MT_CONTROL, 0); + m->m_len = outlen; + md = mtod(m, void *); + + /* + * Make a second pass over input messages, copying them into the output + * buffer. + */ + in1 = in; + while (outlen > 0) { + /* Copy the message header and align the length field. */ + cm = md; + memcpy(cm, in1, sizeof(*cm)); + msglen = cm->cmsg_len - FREEBSD32_ALIGN(sizeof(*cm)); + cm->cmsg_len = CMSG_ALIGN(sizeof(*cm)) + msglen; + + /* Copy the message body. */ + in1 = (char *)in1 + FREEBSD32_ALIGN(sizeof(*cm)); + md = (char *)md + CMSG_ALIGN(sizeof(*cm)); + memcpy(md, in1, msglen); + in1 = (char *)in1 + FREEBSD32_ALIGN(msglen); + md = (char *)md + CMSG_ALIGN(msglen); + KASSERT(outlen >= CMSG_ALIGN(sizeof(*cm)) + CMSG_ALIGN(msglen), + ("outlen %u underflow, msglen %u", outlen, msglen)); + outlen -= CMSG_ALIGN(sizeof(*cm)) + CMSG_ALIGN(msglen); } - if (error) - m_free(m); - else - *mp = m; + *mp = m; +out: + free(in, M_TEMP); return (error); } From 36cc9d5ca5041c1d0748c04bff0c71597827ec66 Mon Sep 17 00:00:00 2001 From: Mark Johnston Date: Wed, 5 Aug 2020 17:26:20 +0000 Subject: [PATCH 114/141] Fix the smrstress build after r358400. Reported by: pho --- tools/uma/smrstress/smrstress.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/uma/smrstress/smrstress.c b/tools/uma/smrstress/smrstress.c index 0e4dcfeddf47..7e7ee4ea065c 100644 --- a/tools/uma/smrstress/smrstress.c +++ b/tools/uma/smrstress/smrstress.c @@ -68,7 +68,7 @@ smrs_error(struct smrs *smrs, const char *fmt, ...) atomic_add_int(&smrs_failures, 1); printf("SMR ERROR: wr_seq %d, rd_seq %d, c_seq %d, generation %d, count %d ", - smrs_smr->c_shared->s_wr_seq, smrs_smr->c_shared->s_rd_seq, + smrs_smr->c_shared->s_wr.seq, smrs_smr->c_shared->s_rd_seq, zpcpu_get(smrs_smr)->c_seq, smrs->generation, smrs->count); va_start(ap, fmt); (void)vprintf(fmt, ap); From ff06230e67f1eaa0fc315b717f2003db44a0efe7 Mon Sep 17 00:00:00 2001 From: Oleksandr Tymoshenko Date: Wed, 5 Aug 2020 18:21:22 +0000 Subject: [PATCH 115/141] Add flag for SYSCON-controlled clocks on Rockhip platform Ethernet clocks on RK3328 are controlled by SYSCON registers, so add RK_CLK_COMPOSITE_GRF flag to indicate that clock node should access grf registers instead of CRU's Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D25918 --- sys/arm64/rockchip/clk/rk_clk_composite.c | 57 ++++++++++++++++++++++- sys/arm64/rockchip/clk/rk_clk_composite.h | 1 + 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/sys/arm64/rockchip/clk/rk_clk_composite.c b/sys/arm64/rockchip/clk/rk_clk_composite.c index bf1c7df3b404..17d258e02985 100644 --- a/sys/arm64/rockchip/clk/rk_clk_composite.c +++ b/sys/arm64/rockchip/clk/rk_clk_composite.c @@ -35,10 +35,12 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include "clkdev_if.h" +#include "syscon_if.h" struct rk_clk_composite_sc { uint32_t muxdiv_offset; @@ -54,12 +56,14 @@ struct rk_clk_composite_sc { uint32_t gate_shift; uint32_t flags; + + struct syscon *grf; }; #define WRITE4(_clk, off, val) \ - CLKDEV_WRITE_4(clknode_get_device(_clk), off, val) + rk_clk_composite_write_4(_clk, off, val) #define READ4(_clk, off, val) \ - CLKDEV_READ_4(clknode_get_device(_clk), off, val) + rk_clk_composite_read_4(_clk, off, val) #define DEVICE_LOCK(_clk) \ CLKDEV_DEVICE_LOCK(clknode_get_device(_clk)) #define DEVICE_UNLOCK(_clk) \ @@ -74,6 +78,49 @@ struct rk_clk_composite_sc { #define dprintf(format, arg...) #endif +static void +rk_clk_composite_read_4(struct clknode *clk, bus_addr_t addr, uint32_t *val) +{ + struct rk_clk_composite_sc *sc; + + sc = clknode_get_softc(clk); + if (sc->grf) + *val = SYSCON_READ_4(sc->grf, addr); + else + CLKDEV_READ_4(clknode_get_device(clk), addr, val); +} + +static void +rk_clk_composite_write_4(struct clknode *clk, bus_addr_t addr, uint32_t val) +{ + struct rk_clk_composite_sc *sc; + + sc = clknode_get_softc(clk); + if (sc->grf) + SYSCON_WRITE_4(sc->grf, addr, val | (0xffff << 16)); + else + CLKDEV_WRITE_4(clknode_get_device(clk), addr, val); +} + +static struct syscon * +rk_clk_composite_get_grf(struct clknode *clk) +{ + device_t dev; + phandle_t node; + struct syscon *grf; + + grf = NULL; + dev = clknode_get_device(clk); + node = ofw_bus_get_node(dev); + if (OF_hasprop(node, "rockchip,grf") && + syscon_get_by_ofw_property(dev, node, + "rockchip,grf", &grf) != 0) { + return (NULL); + } + + return (grf); +} + static int rk_clk_composite_init(struct clknode *clk, device_t dev) { @@ -81,6 +128,12 @@ rk_clk_composite_init(struct clknode *clk, device_t dev) uint32_t val, idx; sc = clknode_get_softc(clk); + if ((sc->flags & RK_CLK_COMPOSITE_GRF) != 0) { + sc->grf = rk_clk_composite_get_grf(clk); + if (sc->grf == NULL) + panic("clock %s has GRF flag set but no syscon is available", + clknode_get_name(clk)); + } idx = 0; if ((sc->flags & RK_CLK_COMPOSITE_HAVE_MUX) != 0) { diff --git a/sys/arm64/rockchip/clk/rk_clk_composite.h b/sys/arm64/rockchip/clk/rk_clk_composite.h index 9c899baa1dee..3f221572bcb9 100644 --- a/sys/arm64/rockchip/clk/rk_clk_composite.h +++ b/sys/arm64/rockchip/clk/rk_clk_composite.h @@ -53,6 +53,7 @@ struct rk_clk_composite_def { #define RK_CLK_COMPOSITE_HAVE_GATE 0x0002 #define RK_CLK_COMPOSITE_DIV_EXP 0x0004 /* Register 0, 1, 2, 2, ... */ /* Divider 1, 2, 4, 8, ... */ +#define RK_CLK_COMPOSITE_GRF 0x0008 /* Use syscon registers instead of CRU's */ int rk_clk_composite_register(struct clkdom *clkdom, struct rk_clk_composite_def *clkdef); From 5414a8285faa844f925159b890c676c25f8a8c1c Mon Sep 17 00:00:00 2001 From: Oleksandr Tymoshenko Date: Wed, 5 Aug 2020 18:22:24 +0000 Subject: [PATCH 116/141] Add clocks for ethernet controllers on RK3328 Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D25918 --- sys/arm64/rockchip/clk/rk3328_cru.c | 286 ++++++++++++++++++++++++++++ 1 file changed, 286 insertions(+) diff --git a/sys/arm64/rockchip/clk/rk3328_cru.c b/sys/arm64/rockchip/clk/rk3328_cru.c index 7e53c54fa2b7..69ad2dac873c 100644 --- a/sys/arm64/rockchip/clk/rk3328_cru.c +++ b/sys/arm64/rockchip/clk/rk3328_cru.c @@ -49,10 +49,31 @@ __FBSDID("$FreeBSD$"); #include +/* Registers */ +#define RK3328_GRF_SOC_CON4 0x410 +#define RK3328_GRF_MAC_CON1 0x904 +#define RK3328_GRF_MAC_CON2 0x908 + /* GATES */ +#define SCLK_MAC2PHY_RXTX 83 +#define SCLK_MAC2PHY_SRC 84 +#define SCLK_MAC2PHY_REF 85 +#define SCLK_MAC2PHY_OUT 86 +#define SCLK_MAC2IO_RX 87 +#define SCLK_MAC2IO_TX 88 +#define SCLK_MAC2IO_REFOUT 89 +#define SCLK_MAC2IO_REF 90 +#define SCLK_MAC2IO_OUT 91 #define SCLK_USB3OTG_REF 96 +#define SCLK_MAC2IO_SRC 99 +#define SCLK_MAC2IO 100 +#define SCLK_MAC2PHY 101 +#define SCLK_MAC2IO_EXT 102 #define ACLK_USB3OTG 132 +#define ACLK_GMAC 146 +#define ACLK_MAC2PHY 149 +#define ACLK_MAC2IO 150 #define ACLK_PERI 153 #define PCLK_GPIO0 200 #define PCLK_GPIO1 201 @@ -63,6 +84,9 @@ __FBSDID("$FreeBSD$"); #define PCLK_I2C2 207 #define PCLK_I2C3 208 #define PCLK_TSADC 213 +#define PCLK_GMAC 220 +#define PCLK_MAC2PHY 222 +#define PCLK_MAC2IO 223 #define PCLK_USB3PHY_OTG 224 #define PCLK_USB3PHY_PIPE 225 #define PCLK_USB3_GRF 226 @@ -87,6 +111,14 @@ static struct rk_cru_gate rk3328_gates[] = { CRU_GATE(0, "pclk_bus", "pclk_bus_pre", 0x220, 3) CRU_GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0x220, 4) + /* CRU_CLKGATE_CON8 */ + CRU_GATE(SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0x224, 7) + CRU_GATE(SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0x224, 6) + CRU_GATE(SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0x224, 5) + CRU_GATE(SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0x224, 4) + CRU_GATE(SCLK_MAC2PHY_REF, "clk_mac2phy_ref", "clk_mac2phy", 0x224, 3) + CRU_GATE(SCLK_MAC2PHY_RXTX, "clk_mac2phy_rxtx", "clk_mac2phy", 0x224, 1) + /* CRU_CLKGATE_CON10 */ CRU_GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0x228, 0) @@ -116,6 +148,12 @@ static struct rk_cru_gate rk3328_gates[] = { CRU_GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0x24C, 14) CRU_GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0x24C, 15) + /* CRU_CLKGATE_CON26 */ + CRU_GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0x268, 0) + CRU_GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0x268, 1) + CRU_GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0x268, 2) + CRU_GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0x268, 3) + /* CRU_CLKGATE_CON28 */ CRU_GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0x270, 1) CRU_GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0x270, 2) @@ -1077,6 +1115,210 @@ static struct rk_clk_composite_def ref_usb3otg_src = { .flags = RK_CLK_COMPOSITE_HAVE_GATE, }; +static const char *mac2io_src_parents[] = { "cpll", "gpll" }; + +static struct rk_clk_composite_def mac2io_src = { + .clkdef = { + .id = SCLK_MAC2IO_SRC, + .name = "clk_mac2io_src", + .parent_names = mac2io_src_parents, + .parent_cnt = nitems(mac2io_src_parents), + }, + /* CRU_CLKSEL_CON27 */ + .muxdiv_offset = 0x16c, + + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 5, + + /* CRU_CLKGATE_CON3 */ + .gate_offset = 0x20c, + .gate_shift = 1, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE | RK_CLK_COMPOSITE_HAVE_MUX, +}; + +static const char *mac2io_out_parents[] = { "cpll", "gpll" }; + +static struct rk_clk_composite_def mac2io_out = { + .clkdef = { + .id = SCLK_MAC2IO_OUT, + .name = "clk_mac2io_out", + .parent_names = mac2io_out_parents, + .parent_cnt = nitems(mac2io_out_parents), + }, + /* CRU_CLKSEL_CON27 */ + .muxdiv_offset = 0x16c, + + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 8, + .div_width = 5, + + /* CRU_CLKGATE_CON3 */ + .gate_offset = 0x20c, + .gate_shift = 5, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE | RK_CLK_COMPOSITE_HAVE_MUX, +}; + +static const char *mac2io_parents[] = { "clk_mac2io_src", "gmac_clkin" }; + +static struct rk_clk_composite_def mac2io = { + .clkdef = { + .id = SCLK_MAC2IO, + .name = "clk_mac2io", + .parent_names = mac2io_parents, + .parent_cnt = nitems(mac2io_parents), + }, + .muxdiv_offset = RK3328_GRF_MAC_CON1, + + .mux_shift = 10, + .mux_width = 1, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_GRF +}; + +static const char *mac2io_ext_parents[] = { "clk_mac2io", "gmac_clkin" }; + +static struct rk_clk_composite_def mac2io_ext = { + .clkdef = { + .id = SCLK_MAC2IO_EXT, + .name = "clk_mac2io_ext", + .parent_names = mac2io_ext_parents, + .parent_cnt = nitems(mac2io_ext_parents), + }, + .muxdiv_offset = RK3328_GRF_SOC_CON4, + + .mux_shift = 14, + .mux_width = 1, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_GRF +}; + +static const char *mac2phy_src_parents[] = { "cpll", "gpll" }; + +static struct rk_clk_composite_def mac2phy_src = { + .clkdef = { + .id = SCLK_MAC2PHY_SRC, + .name = "clk_mac2phy_src", + .parent_names = mac2phy_src_parents, + .parent_cnt = nitems(mac2phy_src_parents), + }, + /* CRU_CLKSEL_CON26 */ + .muxdiv_offset = 0x168, + + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 5, + + /* CRU_CLKGATE_CON3 */ + .gate_offset = 0x20c, + .gate_shift = 0, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE | RK_CLK_COMPOSITE_HAVE_MUX, +}; + +static const char *mac2phy_parents[] = { "clk_mac2phy_src", "phy_50m_out" }; + +static struct rk_clk_composite_def mac2phy = { + .clkdef = { + .id = SCLK_MAC2PHY, + .name = "clk_mac2phy", + .parent_names = mac2phy_parents, + .parent_cnt = nitems(mac2phy_parents), + }, + .muxdiv_offset = RK3328_GRF_MAC_CON2, + + .mux_shift = 10, + .mux_width = 1, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_GRF +}; + +static const char *mac2phy_out_parents[] = { "clk_mac2phy" }; + +static struct rk_clk_composite_def mac2phy_out = { + .clkdef = { + .id = SCLK_MAC2PHY_OUT, + .name = "clk_mac2phy_out", + .parent_names = mac2phy_out_parents, + .parent_cnt = nitems(mac2phy_out_parents), + }, + /* CRU_CLKSEL_CON26 */ + .muxdiv_offset = 0x168, + + .div_shift = 8, + .div_width = 2, + + /* CRU_CLKGATE_CON9 */ + .gate_offset = 0x224, + .gate_shift = 2, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE +}; + +static struct clk_fixed_def phy_50m_out = { + .clkdef.name = "phy_50m_out", + .freq = 50000000, +}; + +static struct clk_link_def gmac_clkin = { + .clkdef.name = "gmac_clkin", +}; + +static const char *aclk_gmac_parents[] = { "cpll", "gpll" }; + +static struct rk_clk_composite_def aclk_gmac = { + .clkdef = { + .id = ACLK_GMAC, + .name = "aclk_gmac", + .parent_names = aclk_gmac_parents, + .parent_cnt = nitems(aclk_gmac_parents), + }, + /* CRU_CLKSEL_CON35 */ + .muxdiv_offset = 0x18c, + + .mux_shift = 6, + .mux_width = 2, + + .div_shift = 0, + .div_width = 5, + + /* CRU_CLKGATE_CON3 */ + .gate_offset = 0x20c, + .gate_shift = 2, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE | RK_CLK_COMPOSITE_HAVE_MUX, +}; + +static const char *pclk_gmac_parents[] = { "aclk_gmac" }; + +static struct rk_clk_composite_def pclk_gmac = { + .clkdef = { + .id = PCLK_GMAC, + .name = "pclk_gmac", + .parent_names = pclk_gmac_parents, + .parent_cnt = nitems(pclk_gmac_parents), + }, + /* CRU_CLKSEL_CON25 */ + .muxdiv_offset = 0x164, + + .div_shift = 8, + .div_width = 3, + + /* CRU_CLKGATE_CON9 */ + .gate_offset = 0x224, + .gate_shift = 0, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE +}; + static struct rk_clk rk3328_clks[] = { { .type = RK3328_CLK_PLL, @@ -1175,6 +1417,50 @@ static struct rk_clk rk3328_clks[] = { .type = RK_CLK_COMPOSITE, .clk.composite = &usb3otg_suspend }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2io_src + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2io + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2io_out + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2io_ext + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2phy_src + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2phy + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &mac2phy_out + }, + { + .type = RK_CLK_FIXED, + .clk.fixed = &phy_50m_out + }, + { + .type = RK_CLK_LINK, + .clk.link = &gmac_clkin + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &aclk_gmac + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &pclk_gmac + }, }; static int From 94e9ef85c594951f9d9d0e4cd7595e9cd2f792da Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 19:05:49 +0000 Subject: [PATCH 117/141] pmcstat: implement showing offsets into symbols in top mode The -I option (and hotkey) is reused for this. Skipping symbol resolution is moved to the new -A option (and hotkey). While arguably this violates POLA I think it's a change for the better. ALso note the -I option was added in head. Differential Revision: https://reviews.freebsd.org/D21658 --- lib/libpmcstat/libpmcstat.h | 3 ++- usr.sbin/pmcstat/pmcpl_callgraph.c | 41 ++++++++++++++++++++---------- usr.sbin/pmcstat/pmcstat.8 | 15 ++++++----- usr.sbin/pmcstat/pmcstat.c | 13 +++++++--- usr.sbin/pmcstat/pmcstat_log.c | 12 +++++++++ 5 files changed, 60 insertions(+), 24 deletions(-) diff --git a/lib/libpmcstat/libpmcstat.h b/lib/libpmcstat/libpmcstat.h index 3f5f2689f6b3..8e8d94b116d8 100644 --- a/lib/libpmcstat/libpmcstat.h +++ b/lib/libpmcstat/libpmcstat.h @@ -107,8 +107,9 @@ struct pmcstat_args { #define FLAGS_HAS_CPUMASK 0x00040000 /* -c */ #define FLAG_HAS_DURATION 0x00080000 /* -l secs */ #define FLAG_DO_WIDE_GPROF_HC 0x00100000 /* -e */ -#define FLAG_SKIP_TOP_FN_RES 0x00200000 /* -I */ +#define FLAG_SKIP_TOP_FN_RES 0x00200000 /* -A */ #define FLAG_FILTER_THREAD_ID 0x00400000 /* -L */ +#define FLAG_SHOW_OFFSET 0x00800000 /* -I */ int pa_required; /* required features */ int pa_pplugin; /* pre-processing plugin */ diff --git a/usr.sbin/pmcstat/pmcpl_callgraph.c b/usr.sbin/pmcstat/pmcpl_callgraph.c index 8b5570336c3e..4cae6437486c 100644 --- a/usr.sbin/pmcstat/pmcpl_callgraph.c +++ b/usr.sbin/pmcstat/pmcpl_callgraph.c @@ -152,10 +152,12 @@ pmcstat_cgnode_hash_lookup_pc(struct pmcstat_process *pp, pmc_id_t pmcid, * Try determine the function at this offset. If we can't * find a function round leave the `pc' value alone. */ - if ((sym = pmcstat_symbol_search(image, pc)) != NULL) - pc = sym->ps_start; - else - pmcstat_stats.ps_samples_unknown_function++; + if (!(args.pa_flags & (FLAG_SKIP_TOP_FN_RES | FLAG_SHOW_OFFSET))) { + if ((sym = pmcstat_symbol_search(image, pc)) != NULL) + pc = sym->ps_start; + else + pmcstat_stats.ps_samples_unknown_function++; + } for (hash = i = 0; i < sizeof(uintfptr_t); i++) hash += (pc >> i) & 0xFF; @@ -485,22 +487,35 @@ pmcstat_cgnode_topprint(struct pmcstat_cgnode *cg, v = PMCPL_CG_COUNTP(cg); snprintf(vs, sizeof(vs), "%.1f", v); v_attrs = PMCSTAT_ATTRPERCENT(v); - sym = NULL; /* Format name. */ - if (!(args.pa_flags & FLAG_SKIP_TOP_FN_RES)) - sym = pmcstat_symbol_search(cg->pcg_image, cg->pcg_func); - if (sym != NULL) { - snprintf(ns, sizeof(ns), "%s", - pmcstat_string_unintern(sym->ps_name)); - } else + sym = pmcstat_symbol_search(cg->pcg_image, cg->pcg_func); + if (sym == NULL) { snprintf(ns, sizeof(ns), "%p", (void *)(cg->pcg_image->pi_vaddr + cg->pcg_func)); + } else { + switch (args.pa_flags & (FLAG_SKIP_TOP_FN_RES | FLAG_SHOW_OFFSET)) { + case FLAG_SKIP_TOP_FN_RES | FLAG_SHOW_OFFSET: + case FLAG_SKIP_TOP_FN_RES: + snprintf(ns, sizeof(ns), "%p", + (void *)(cg->pcg_image->pi_vaddr + cg->pcg_func)); + break; + case FLAG_SHOW_OFFSET: + snprintf(ns, sizeof(ns), "%s+%#0lx", + pmcstat_string_unintern(sym->ps_name), + cg->pcg_func - sym->ps_start); + break; + default: + snprintf(ns, sizeof(ns), "%s", + pmcstat_string_unintern(sym->ps_name)); + break; + } + } PMCSTAT_ATTRON(v_attrs); PMCSTAT_PRINTW("%5.5s", vs); PMCSTAT_ATTROFF(v_attrs); - PMCSTAT_PRINTW(" %-10.10s %-20.20s", + PMCSTAT_PRINTW(" %-10.10s %-30.30s", pmcstat_string_unintern(cg->pcg_image->pi_name), ns); @@ -624,7 +639,7 @@ pmcpl_cg_topdisplay(void) qsort(sortbuffer, nentries, sizeof(struct pmcstat_cgnode *), pmcstat_cgnode_compare); - PMCSTAT_PRINTW("%5.5s %-10.10s %-20.20s %s\n", + PMCSTAT_PRINTW("%5.5s %-10.10s %-30.30s %s\n", "%SAMP", "IMAGE", "FUNCTION", "CALLERS"); nentries = min(pmcstat_displayheight - 2, nentries); diff --git a/usr.sbin/pmcstat/pmcstat.8 b/usr.sbin/pmcstat/pmcstat.8 index 1291347f8060..86d48db5a8de 100644 --- a/usr.sbin/pmcstat/pmcstat.8 +++ b/usr.sbin/pmcstat/pmcstat.8 @@ -25,7 +25,7 @@ .\" .\" $FreeBSD$ .\" -.Dd May 25, 2018 +.Dd August 5, 2020 .Dt PMCSTAT 8 .Os .Sh NAME @@ -33,6 +33,7 @@ .Nd "performance measurement with performance monitoring hardware" .Sh SYNOPSIS .Nm +.Op Fl A .Op Fl C .Op Fl D Ar pathname .Op Fl E @@ -123,6 +124,8 @@ process' current and future children. .Sh OPTIONS The following options are available: .Bl -tag -width indent +.It Fl A +Skip symbol lookup and display address instead. .It Fl C Toggle between showing cumulative or incremental counts for subsequent counting mode PMCs specified on the command line. @@ -161,7 +164,7 @@ this information is sent to the output file specified by the .Fl o option. .It Fl I -Skip symbol lookup and display address instead. +Show the offset of the instruction pointer into the symbol. .It Fl L List all event names. .It Fl M Ar mapfilename @@ -222,10 +225,10 @@ specified in .Ar event-spec . .It Fl T Use a top like mode for sampling PMCs. The following hotkeys -can be used: 'c+a' switch to accumulative mode, 'c+d' switch -to delta mode, 'm' merge PMCs, 'n' change view, 'p' show next -PMC, ' ' pause, 'q' quit. calltree only: 'f' cost under threshold -is seen as a dot. +can be used: 'A' toggle symbol resolution, 'c+a' switch to accumulative mode, 'c+d' +switch to delta mode, 'I' toggle showing offsets into symbols, 'm' merge PMCs, 'n' +change view, 'p' show next PMC, ' ' pause, 'q' quit. calltree only: 'f' cost under +threshold is seen as a dot. .It Fl U Toggle capturing user-space call traces while in kernel mode. The default is for sampling PMCs to capture user-space callchain information diff --git a/usr.sbin/pmcstat/pmcstat.c b/usr.sbin/pmcstat/pmcstat.c index 838e8cac58b4..2524a76de6f8 100644 --- a/usr.sbin/pmcstat/pmcstat.c +++ b/usr.sbin/pmcstat/pmcstat.c @@ -511,8 +511,12 @@ main(int argc, char **argv) CPU_COPY(&rootmask, &cpumask); while ((option = getopt(argc, argv, - "CD:EF:G:ILM:NO:P:R:S:TUWZa:c:def:gi:k:l:m:n:o:p:qr:s:t:u:vw:z:")) != -1) + "ACD:EF:G:ILM:NO:P:R:S:TUWZa:c:def:gi:k:l:m:n:o:p:qr:s:t:u:vw:z:")) != -1) switch (option) { + case 'A': + args.pa_flags |= FLAG_SKIP_TOP_FN_RES; + break; + case 'a': /* Annotate + callgraph */ args.pa_flags |= FLAG_DO_ANNOTATE; args.pa_plugin = PMCSTAT_PL_ANNOTATE_CG; @@ -586,14 +590,15 @@ main(int argc, char **argv) args.pa_plugin = PMCSTAT_PL_GPROF; break; - case 'I': - args.pa_flags |= FLAG_SKIP_TOP_FN_RES; - break; case 'i': args.pa_flags |= FLAG_FILTER_THREAD_ID; args.pa_tid = strtol(optarg, &end, 0); break; + case 'I': + args.pa_flags |= FLAG_SHOW_OFFSET; + break; + case 'k': /* pathname to the kernel */ free(args.pa_kernel); args.pa_kernel = strdup(optarg); diff --git a/usr.sbin/pmcstat/pmcstat_log.c b/usr.sbin/pmcstat/pmcstat_log.c index 5f88d274f393..4f58ffb2eb65 100644 --- a/usr.sbin/pmcstat/pmcstat_log.c +++ b/usr.sbin/pmcstat/pmcstat_log.c @@ -612,6 +612,12 @@ pmcstat_keypress_log(void) c = wgetch(w); wprintw(w, "Key: %c => ", c); switch (c) { + case 'A': + if (args.pa_flags & FLAG_SKIP_TOP_FN_RES) + args.pa_flags &= ~FLAG_SKIP_TOP_FN_RES; + else + args.pa_flags |= FLAG_SKIP_TOP_FN_RES; + break; case 'c': wprintw(w, "enter mode 'd' or 'a' => "); c = wgetch(w); @@ -623,6 +629,12 @@ pmcstat_keypress_log(void) wprintw(w, "switching to accumulation mode"); } break; + case 'I': + if (args.pa_flags & FLAG_SHOW_OFFSET) + args.pa_flags &= ~FLAG_SHOW_OFFSET; + else + args.pa_flags |= FLAG_SHOW_OFFSET; + break; case 'm': pmcstat_mergepmc = !pmcstat_mergepmc; /* From c4cd69901032954bb089de4d5cd751413bec655f Mon Sep 17 00:00:00 2001 From: Ruslan Bukin Date: Wed, 5 Aug 2020 19:11:31 +0000 Subject: [PATCH 118/141] o Add machine/iommu.h and include MD iommu headers from it, so we don't ifdef for every arch in busdma_iommu.c; o No need to include specialreg.h for x86, remove it. Requested by: andrew Reviewed by: kib Sponsored by: DARPA/AFRL Differential Revision: https://reviews.freebsd.org/D25957 --- sys/amd64/include/iommu.h | 6 ++++++ sys/dev/iommu/busdma_iommu.c | 9 ++------- sys/dev/iommu/iommu_gas.c | 4 +--- sys/i386/include/iommu.h | 6 ++++++ sys/x86/include/iommu.h | 13 +++++++++++++ 5 files changed, 28 insertions(+), 10 deletions(-) create mode 100644 sys/amd64/include/iommu.h create mode 100644 sys/i386/include/iommu.h create mode 100644 sys/x86/include/iommu.h diff --git a/sys/amd64/include/iommu.h b/sys/amd64/include/iommu.h new file mode 100644 index 000000000000..3737d51fdcef --- /dev/null +++ b/sys/amd64/include/iommu.h @@ -0,0 +1,6 @@ +/*- + * This file is in the public domain. + */ +/* $FreeBSD$ */ + +#include diff --git a/sys/dev/iommu/busdma_iommu.c b/sys/dev/iommu/busdma_iommu.c index 428880f85d01..908ed6933c68 100644 --- a/sys/dev/iommu/busdma_iommu.c +++ b/sys/dev/iommu/busdma_iommu.c @@ -59,17 +59,12 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include -#if defined(__amd64__) || defined(__i386__) -#include -#include -#include +#include #include -#include -#include -#endif /* * busdma_iommu.c, the implementation of the busdma(9) interface using diff --git a/sys/dev/iommu/iommu_gas.c b/sys/dev/iommu/iommu_gas.c index 0baf996bf416..d6a09d852bfb 100644 --- a/sys/dev/iommu/iommu_gas.c +++ b/sys/dev/iommu/iommu_gas.c @@ -65,9 +65,7 @@ __FBSDID("$FreeBSD$"); #include #include #include -#if defined(__amd64__) || defined(__i386__) -#include -#endif +#include #include /* diff --git a/sys/i386/include/iommu.h b/sys/i386/include/iommu.h new file mode 100644 index 000000000000..3737d51fdcef --- /dev/null +++ b/sys/i386/include/iommu.h @@ -0,0 +1,6 @@ +/*- + * This file is in the public domain. + */ +/* $FreeBSD$ */ + +#include diff --git a/sys/x86/include/iommu.h b/sys/x86/include/iommu.h new file mode 100644 index 000000000000..2757f1554258 --- /dev/null +++ b/sys/x86/include/iommu.h @@ -0,0 +1,13 @@ +/*- + * This file is in the public domain. + */ +/* $FreeBSD$ */ + +#ifndef _MACHINE_IOMMU_H_ +#define _MACHINE_IOMMU_H_ + +#include +#include +#include + +#endif /* !_MACHINE_IOMMU_H_ */ From 4f00177887ae00e8ddd97be786e17b63a2867084 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 19:15:59 +0000 Subject: [PATCH 119/141] pipe: reduce atime precision The routine is called on successful write and read, which on pipes happens a lot and for small sizes. Precision provided by default seems way bigger than necessary and it causes problems in vms on amd64 (it rdtscp's which vmexits). getnanotime seems to provide the level roughly in lines of Linux so we should be good here. Sample result from will-it-scale pipe1_processes -t 1 (ops/s): before: 426464 after: 3247421 Note the that atime handling for named pipes is broken with and without the patch. The filesystem code is never used for updating atime and never looks at the updated field. Consequently, while there are no provisions added to handle named pipes separately, the change is a nop for that case. Differential Revision: https://reviews.freebsd.org/D23964 --- sys/kern/sys_pipe.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/sys/kern/sys_pipe.c b/sys/kern/sys_pipe.c index 216d0f077778..a19b6efb0271 100644 --- a/sys/kern/sys_pipe.c +++ b/sys/kern/sys_pipe.c @@ -230,6 +230,7 @@ static int pipe_create(struct pipe *pipe, bool backing); static int pipe_paircreate(struct thread *td, struct pipepair **p_pp); static __inline int pipelock(struct pipe *cpipe, int catch); static __inline void pipeunlock(struct pipe *cpipe); +static void pipe_timestamp(struct timespec *tsp); #ifndef PIPE_NODIRECT static int pipe_build_write_buffer(struct pipe *wpipe, struct uio *uio); static void pipe_destroy_write_buffer(struct pipe *wpipe); @@ -279,7 +280,7 @@ pipe_zone_ctor(void *mem, int size, void *arg, int flags) */ rpipe = &pp->pp_rpipe; bzero(rpipe, sizeof(*rpipe)); - vfs_timestamp(&rpipe->pipe_ctime); + pipe_timestamp(&rpipe->pipe_ctime); rpipe->pipe_atime = rpipe->pipe_mtime = rpipe->pipe_ctime; wpipe = &pp->pp_wpipe; @@ -421,6 +422,20 @@ pipe_dtor(struct pipe *dpipe) } } +/* + * Get a timestamp. + * + * This used to be vfs_timestamp but the higher precision is unnecessary and + * can very negatively affect performance in virtualized environments (e.g., on + * vms running on amd64 when using the rdtscp instruction). + */ +static void +pipe_timestamp(struct timespec *tsp) +{ + + getnanotime(tsp); +} + /* * The pipe system call for the DTYPE_PIPE type of pipes. If we fail, let * the zone pick up the pieces via pipeclose(). @@ -804,7 +819,7 @@ pipe_read(struct file *fp, struct uio *uio, struct ucred *active_cred, /* XXX: should probably do this before getting any locks. */ if (error == 0) - vfs_timestamp(&rpipe->pipe_atime); + pipe_timestamp(&rpipe->pipe_atime); unlocked_error: --rpipe->pipe_busy; @@ -1290,7 +1305,7 @@ pipe_write(struct file *fp, struct uio *uio, struct ucred *active_cred, error = 0; if (error == 0) - vfs_timestamp(&wpipe->pipe_mtime); + pipe_timestamp(&wpipe->pipe_mtime); /* * We have something to offer, From bb62c418fd86676b52c5a4c7273f9992917c7056 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 19:34:13 +0000 Subject: [PATCH 120/141] vfs hash: annotate the lock with __exclusive_cache_line Note the code does not scale in the current form. --- sys/kern/vfs_hash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/kern/vfs_hash.c b/sys/kern/vfs_hash.c index 082d166cbf9a..652806b7b4db 100644 --- a/sys/kern/vfs_hash.c +++ b/sys/kern/vfs_hash.c @@ -43,7 +43,7 @@ static MALLOC_DEFINE(M_VFS_HASH, "vfs_hash", "VFS hash table"); static LIST_HEAD(vfs_hash_head, vnode) *vfs_hash_tbl; static LIST_HEAD(,vnode) vfs_hash_side; static u_long vfs_hash_mask; -static struct rwlock vfs_hash_lock; +static struct rwlock __exclusive_cache_line vfs_hash_lock; static void vfs_hashinit(void *dummy __unused) From ec3b2a79b5b5cae75c5c6925068fdd202ef644fe Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 20:42:08 +0000 Subject: [PATCH 121/141] pmcstat: fix build on non-64 bit platforms --- usr.sbin/pmcstat/pmcpl_callgraph.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/usr.sbin/pmcstat/pmcpl_callgraph.c b/usr.sbin/pmcstat/pmcpl_callgraph.c index 4cae6437486c..f6b662fdeb14 100644 --- a/usr.sbin/pmcstat/pmcpl_callgraph.c +++ b/usr.sbin/pmcstat/pmcpl_callgraph.c @@ -58,6 +58,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include #include @@ -501,7 +502,7 @@ pmcstat_cgnode_topprint(struct pmcstat_cgnode *cg, (void *)(cg->pcg_image->pi_vaddr + cg->pcg_func)); break; case FLAG_SHOW_OFFSET: - snprintf(ns, sizeof(ns), "%s+%#0lx", + snprintf(ns, sizeof(ns), "%s+%#0" PRIx64, pmcstat_string_unintern(sym->ps_name), cg->pcg_func - sym->ps_start); break; From 9ce4656a1ffff4f0b874d8eb8e242378ff906643 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 22:09:40 +0000 Subject: [PATCH 122/141] riscv: fix uintfptr_t Fixes compilation after r363932 --- sys/riscv/include/profile.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/riscv/include/profile.h b/sys/riscv/include/profile.h index 087af0504c75..edfcbd31b73a 100644 --- a/sys/riscv/include/profile.h +++ b/sys/riscv/include/profile.h @@ -70,7 +70,7 @@ void mcount(uintfptr_t frompc, uintfptr_t selfpc); #else /* !_KERNEL */ -typedef unsigned long long uintfptr_t; +typedef __uintfptr_t uintfptr_t; #define _MCOUNT_DECL void mcount #define MCOUNT From 0ef3c62577fc37389ea46c9fc5accfb7706b6c01 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Wed, 5 Aug 2020 22:09:57 +0000 Subject: [PATCH 123/141] arm64: fix uintfptr_t Fixes compilation after r363932 --- sys/arm64/include/profile.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/arm64/include/profile.h b/sys/arm64/include/profile.h index 087af0504c75..afbfbdb44c0b 100644 --- a/sys/arm64/include/profile.h +++ b/sys/arm64/include/profile.h @@ -70,7 +70,7 @@ void mcount(uintfptr_t frompc, uintfptr_t selfpc); #else /* !_KERNEL */ -typedef unsigned long long uintfptr_t; +typedef __uintfptr_t uintfptr_t; #define _MCOUNT_DECL void mcount #define MCOUNT From 4ec34a908bb2caf1967fd6e26e152e0bf2e4534e Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Thu, 6 Aug 2020 00:23:06 +0000 Subject: [PATCH 124/141] mac: even up all entry points to the same scheme - use a macro for checking whether the site is enabled - expand it to 0 if mac is not compiled in to begin with --- sys/security/mac/mac_framework.h | 45 +++++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 7 deletions(-) diff --git a/sys/security/mac/mac_framework.h b/sys/security/mac/mac_framework.h index 70a7aad44757..fed574d36135 100644 --- a/sys/security/mac/mac_framework.h +++ b/sys/security/mac/mac_framework.h @@ -264,11 +264,12 @@ extern bool mac_priv_check_fp_flag; #else #define mac_priv_check_fp_flag 0 #endif +#define mac_priv_check_enabled() __predict_false(mac_priv_check_fp_flag) static inline int mac_priv_check(struct ucred *cred, int priv) { - if (__predict_false(mac_priv_check_fp_flag)) + if (mac_priv_check_enabled()) return (mac_priv_check_impl(cred, priv)); return (0); } @@ -279,11 +280,12 @@ extern bool mac_priv_grant_fp_flag; #else #define mac_priv_grant_fp_flag 0 #endif +#define mac_priv_grant_enabled() __predict_false(mac_priv_grant_fp_flag) static inline int mac_priv_grant(struct ucred *cred, int priv) { - if (__predict_false(mac_priv_grant_fp_flag)) + if (mac_priv_grant_enabled()) return (mac_priv_grant_impl(cred, priv)); return (EPERM); } @@ -441,7 +443,11 @@ int mac_vnode_check_listextattr(struct ucred *cred, struct vnode *vp, int mac_vnode_check_lookup_impl(struct ucred *cred, struct vnode *dvp, struct componentname *cnp); +#ifdef MAC extern bool mac_vnode_check_lookup_fp_flag; +#else +#define mac_vnode_check_lookup_fp_flag 0 +#endif #define mac_vnode_check_lookup_enabled() __predict_false(mac_vnode_check_lookup_fp_flag) static inline int mac_vnode_check_lookup(struct ucred *cred, struct vnode *dvp, @@ -456,28 +462,38 @@ mac_vnode_check_lookup(struct ucred *cred, struct vnode *dvp, int mac_vnode_check_mmap_impl(struct ucred *cred, struct vnode *vp, int prot, int flags); +#ifdef MAC extern bool mac_vnode_check_mmap_fp_flag; +#else +#define mac_vnode_check_mmap_fp_flag 0 +#endif +#define mac_vnode_check_mmap_enabled() __predict_false(mac_vnode_check_mmap_fp_flag) static inline int mac_vnode_check_mmap(struct ucred *cred, struct vnode *vp, int prot, int flags) { mac_vnode_assert_locked(vp, "mac_vnode_check_mmap"); - if (__predict_false(mac_vnode_check_mmap_fp_flag)) + if (mac_vnode_check_mmap_enabled()) return (mac_vnode_check_mmap_impl(cred, vp, prot, flags)); return (0); } int mac_vnode_check_open_impl(struct ucred *cred, struct vnode *vp, accmode_t accmode); +#ifdef MAC extern bool mac_vnode_check_open_fp_flag; +#else +#define mac_vnode_check_open_fp_flag 0 +#endif +#define mac_vnode_check_open_enabled() __predict_false(mac_vnode_check_open_fp_flag) static inline int mac_vnode_check_open(struct ucred *cred, struct vnode *vp, accmode_t accmode) { mac_vnode_assert_locked(vp, "mac_vnode_check_open"); - if (__predict_false(mac_vnode_check_open_fp_flag)) + if (mac_vnode_check_open_enabled()) return (mac_vnode_check_open_impl(cred, vp, accmode)); return (0); } @@ -526,42 +542,57 @@ int mac_vnode_check_setutimes(struct ucred *cred, struct vnode *vp, int mac_vnode_check_stat_impl(struct ucred *active_cred, struct ucred *file_cred, struct vnode *vp); +#ifdef MAC extern bool mac_vnode_check_stat_fp_flag; +#else +#define mac_vnode_check_stat_fp_flag 0 +#endif +#define mac_vnode_check_stat_enabled() __predict_false(mac_vnode_check_stat_fp_flag) static inline int mac_vnode_check_stat(struct ucred *active_cred, struct ucred *file_cred, struct vnode *vp) { mac_vnode_assert_locked(vp, "mac_vnode_check_stat"); - if (__predict_false(mac_vnode_check_stat_fp_flag)) + if (mac_vnode_check_stat_enabled()) return (mac_vnode_check_stat_impl(active_cred, file_cred, vp)); return (0); } int mac_vnode_check_read_impl(struct ucred *active_cred, struct ucred *file_cred, struct vnode *vp); +#ifdef MAC extern bool mac_vnode_check_read_fp_flag; +#else +#define mac_vnode_check_read_fp_flag 0 +#endif +#define mac_vnode_check_read_enabled() __predict_false(mac_vnode_check_read_fp_flag) static inline int mac_vnode_check_read(struct ucred *active_cred, struct ucred *file_cred, struct vnode *vp) { mac_vnode_assert_locked(vp, "mac_vnode_check_read"); - if (__predict_false(mac_vnode_check_read_fp_flag)) + if (mac_vnode_check_read_enabled()) return (mac_vnode_check_read_impl(active_cred, file_cred, vp)); return (0); } int mac_vnode_check_write_impl(struct ucred *active_cred, struct ucred *file_cred, struct vnode *vp); +#ifdef MAC extern bool mac_vnode_check_write_fp_flag; +#else +#define mac_vnode_check_write_fp_flag 0 +#endif +#define mac_vnode_check_write_enabled() __predict_false(mac_vnode_check_write_fp_flag) static inline int mac_vnode_check_write(struct ucred *active_cred, struct ucred *file_cred, struct vnode *vp) { mac_vnode_assert_locked(vp, "mac_vnode_check_write"); - if (__predict_false(mac_vnode_check_write_fp_flag)) + if (mac_vnode_check_write_enabled()) return (mac_vnode_check_write_impl(active_cred, file_cred, vp)); return (0); } From 95888901f7489d3ca43398d3bc12ba1ddb5064c8 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Thu, 6 Aug 2020 04:19:47 +0000 Subject: [PATCH 125/141] cache: plug unititalized variable use CID: 1431128 --- sys/kern/vfs_cache.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 25d10c824ced..0107a4e062e8 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -3456,8 +3456,7 @@ cache_fplookup_final_withparent(struct cache_fpl *fpl) vput(dvp); else vrele(dvp); - cache_fpl_aborted(fpl); - return (error); + return (cache_fpl_aborted(fpl)); } error = cache_fplookup_final_child(fpl, tvs); From e910c93eeab0d59ae49c3321caa8697cec6d8b29 Mon Sep 17 00:00:00 2001 From: Mateusz Guzik Date: Thu, 6 Aug 2020 04:20:14 +0000 Subject: [PATCH 126/141] cache: add more predicts for failing conditions --- sys/kern/vfs_cache.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sys/kern/vfs_cache.c b/sys/kern/vfs_cache.c index 0107a4e062e8..670262ab1fed 100644 --- a/sys/kern/vfs_cache.c +++ b/sys/kern/vfs_cache.c @@ -3389,7 +3389,7 @@ cache_fplookup_final_child(struct cache_fpl *fpl, enum vgetstate tvs) if ((cnp->cn_flags & LOCKSHARED) == 0) lkflags = LK_EXCLUSIVE; error = vget_finish(tvp, lkflags, tvs); - if (error != 0) { + if (__predict_false(error != 0)) { return (cache_fpl_aborted(fpl)); } } else { @@ -3442,7 +3442,7 @@ cache_fplookup_final_withparent(struct cache_fpl *fpl) if ((cnp->cn_flags & LOCKPARENT) != 0) { error = vget_finish(dvp, LK_EXCLUSIVE, dvs); - if (error != 0) { + if (__predict_false(error != 0)) { vget_abort(tvp, tvs); return (cache_fpl_aborted(fpl)); } @@ -3460,7 +3460,7 @@ cache_fplookup_final_withparent(struct cache_fpl *fpl) } error = cache_fplookup_final_child(fpl, tvs); - if (error != 0) { + if (__predict_false(error != 0)) { MPASS(fpl->status == CACHE_FPL_STATUS_ABORTED); if ((cnp->cn_flags & LOCKPARENT) != 0) vput(dvp); From e70d59c0dd371fef666f959a26cda85fa7cd2bcc Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Thu, 6 Aug 2020 08:21:33 +0000 Subject: [PATCH 127/141] mmccam: Unhold the periph when we add the device Otherwise the device node aren't created. Pointy hat to: manu Reported by: bz --- sys/cam/mmc/mmc_da.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sys/cam/mmc/mmc_da.c b/sys/cam/mmc/mmc_da.c index b09c29387693..a603dabf9351 100644 --- a/sys/cam/mmc/mmc_da.c +++ b/sys/cam/mmc/mmc_da.c @@ -1505,6 +1505,7 @@ sdda_start_init(void *context, union ccb *start_ccb) softc->state = SDDA_STATE_NORMAL; + cam_periph_unhold(periph); /* MMC partitions support */ if (mmcp->card_features & CARD_FEATURE_MMC && mmc_get_spec_vers(periph) >= 4) { sdda_process_mmc_partitions(periph, start_ccb); @@ -1516,6 +1517,7 @@ sdda_start_init(void *context, union ccb *start_ccb) sdda_get_read_only(periph, start_ccb)); softc->part_curr = 0; } + cam_periph_hold(periph, PRIBIO|PCATCH); xpt_announce_periph(periph, softc->card_id_string); /* From 16696f6057eeef9c756837470f0c0fff3efe7697 Mon Sep 17 00:00:00 2001 From: Ruslan Bukin Date: Thu, 6 Aug 2020 08:48:23 +0000 Subject: [PATCH 128/141] Add iommu_domain constructor and destructor. Reviewed by: kib Sponsored by: DARPA/AFRL Differential Revision: https://reviews.freebsd.org/D25956 --- sys/dev/iommu/busdma_iommu.c | 20 ++++++++++++++++++++ sys/dev/iommu/iommu.h | 3 +++ sys/x86/iommu/intel_ctx.c | 16 +++++++++------- sys/x86/iommu/intel_dmar.h | 2 +- sys/x86/iommu/intel_idpgtbl.c | 11 +---------- 5 files changed, 34 insertions(+), 18 deletions(-) diff --git a/sys/dev/iommu/busdma_iommu.c b/sys/dev/iommu/busdma_iommu.c index 908ed6933c68..a9db66ecc387 100644 --- a/sys/dev/iommu/busdma_iommu.c +++ b/sys/dev/iommu/busdma_iommu.c @@ -1063,3 +1063,23 @@ bus_dma_iommu_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map1, free(ma, M_TEMP); return (error); } + +void +iommu_domain_init(struct iommu_unit *unit, struct iommu_domain *domain, + const struct iommu_domain_map_ops *ops) +{ + + domain->ops = ops; + domain->iommu = unit; + + RB_INIT(&domain->rb_root); + TAILQ_INIT(&domain->unload_entries); + mtx_init(&domain->lock, "iodom", NULL, MTX_DEF); +} + +void +iommu_domain_fini(struct iommu_domain *domain) +{ + + mtx_destroy(&domain->lock); +} diff --git a/sys/dev/iommu/iommu.h b/sys/dev/iommu/iommu.h index 31f9e5959698..7ff5420c9757 100644 --- a/sys/dev/iommu/iommu.h +++ b/sys/dev/iommu/iommu.h @@ -223,6 +223,9 @@ int iommu_gas_reserve_region(struct iommu_domain *domain, iommu_gaddr_t start, void iommu_set_buswide_ctx(struct iommu_unit *unit, u_int busno); bool iommu_is_buswide_ctx(struct iommu_unit *unit, u_int busno); +void iommu_domain_init(struct iommu_unit *unit, struct iommu_domain *domain, + const struct iommu_domain_map_ops *ops); +void iommu_domain_fini(struct iommu_domain *domain); bool bus_dma_iommu_set_buswide(device_t dev); int bus_dma_iommu_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map, diff --git a/sys/x86/iommu/intel_ctx.c b/sys/x86/iommu/intel_ctx.c index c905b1cbc1fd..338316c425ee 100644 --- a/sys/x86/iommu/intel_ctx.c +++ b/sys/x86/iommu/intel_ctx.c @@ -322,6 +322,7 @@ static struct dmar_domain * dmar_domain_alloc(struct dmar_unit *dmar, bool id_mapped) { struct iommu_domain *iodom; + struct iommu_unit *unit; struct dmar_domain *domain; int error, id, mgaw; @@ -330,16 +331,14 @@ dmar_domain_alloc(struct dmar_unit *dmar, bool id_mapped) return (NULL); domain = malloc(sizeof(*domain), M_DMAR_DOMAIN, M_WAITOK | M_ZERO); iodom = DOM2IODOM(domain); + unit = DMAR2IOMMU(dmar); domain->domain = id; LIST_INIT(&domain->contexts); - RB_INIT(&domain->iodom.rb_root); - TAILQ_INIT(&domain->iodom.unload_entries); TASK_INIT(&domain->iodom.unload_task, 0, dmar_domain_unload_task, domain); - mtx_init(&domain->iodom.lock, "dmardom", NULL, MTX_DEF); + iommu_domain_init(unit, iodom, &dmar_domain_map_ops); + domain->dmar = dmar; - domain->iodom.iommu = &dmar->iommu; - domain_pgtbl_init(domain); /* * For now, use the maximal usable physical address of the @@ -430,8 +429,11 @@ dmar_ctx_unlink(struct dmar_ctx *ctx) static void dmar_domain_destroy(struct dmar_domain *domain) { + struct iommu_domain *iodom; struct dmar_unit *dmar; + iodom = DOM2IODOM(domain); + KASSERT(TAILQ_EMPTY(&domain->iodom.unload_entries), ("unfinished unloads %p", domain)); KASSERT(LIST_EMPTY(&domain->contexts), @@ -442,7 +444,7 @@ dmar_domain_destroy(struct dmar_domain *domain) ("destroying dom %p with refs %d", domain, domain->refs)); if ((domain->iodom.flags & IOMMU_DOMAIN_GAS_INITED) != 0) { DMAR_DOMAIN_LOCK(domain); - iommu_gas_fini_domain(DOM2IODOM(domain)); + iommu_gas_fini_domain(iodom); DMAR_DOMAIN_UNLOCK(domain); } if ((domain->iodom.flags & IOMMU_DOMAIN_PGTBL_INITED) != 0) { @@ -450,7 +452,7 @@ dmar_domain_destroy(struct dmar_domain *domain) DMAR_DOMAIN_PGLOCK(domain); domain_free_pgtbl(domain); } - mtx_destroy(&domain->iodom.lock); + iommu_domain_fini(iodom); dmar = DOM2DMAR(domain); free_unr(dmar->domids, domain->domain); free(domain, M_DMAR_DOMAIN); diff --git a/sys/x86/iommu/intel_dmar.h b/sys/x86/iommu/intel_dmar.h index ae9dd282e567..e54f5f532688 100644 --- a/sys/x86/iommu/intel_dmar.h +++ b/sys/x86/iommu/intel_dmar.h @@ -264,7 +264,7 @@ void domain_flush_iotlb_sync(struct dmar_domain *domain, iommu_gaddr_t base, iommu_gaddr_t size); int domain_alloc_pgtbl(struct dmar_domain *domain); void domain_free_pgtbl(struct dmar_domain *domain); -void domain_pgtbl_init(struct dmar_domain *domain); +extern const struct iommu_domain_map_ops dmar_domain_map_ops; int dmar_dev_depth(device_t child); void dmar_dev_path(device_t child, int *busno, void *path1, int depth); diff --git a/sys/x86/iommu/intel_idpgtbl.c b/sys/x86/iommu/intel_idpgtbl.c index 910e135f30e5..76cda797a160 100644 --- a/sys/x86/iommu/intel_idpgtbl.c +++ b/sys/x86/iommu/intel_idpgtbl.c @@ -813,16 +813,7 @@ domain_flush_iotlb_sync(struct dmar_domain *domain, iommu_gaddr_t base, DMAR_UNLOCK(unit); } -static const struct iommu_domain_map_ops dmar_domain_map_ops = { +const struct iommu_domain_map_ops dmar_domain_map_ops = { .map = domain_map_buf, .unmap = domain_unmap_buf, }; - -void -domain_pgtbl_init(struct dmar_domain *domain) -{ - struct iommu_domain *iodom; - - iodom = DOM2IODOM(domain); - iodom->ops = &dmar_domain_map_ops; -} From a89b0586a35c53e4155973e8f528e0dbbaedd00c Mon Sep 17 00:00:00 2001 From: Andriy Gapon Date: Thu, 6 Aug 2020 11:18:06 +0000 Subject: [PATCH 129/141] ccu_sun8i_r: minor comment update MFC after: 1 week --- sys/arm/allwinner/clkng/ccu_sun8i_r.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sys/arm/allwinner/clkng/ccu_sun8i_r.c b/sys/arm/allwinner/clkng/ccu_sun8i_r.c index a0b7093ea8fd..cc3b5bff2cf7 100644 --- a/sys/arm/allwinner/clkng/ccu_sun8i_r.c +++ b/sys/arm/allwinner/clkng/ccu_sun8i_r.c @@ -119,7 +119,7 @@ NM_CLK(r_ccu_ir_clk, "ir", r_ccu_ir_parents, /* names, parents */ 0x54, /* offset */ 0, 4, 0, 0, /* N factor */ - 16, 2, 0, 0, /* M flags */ + 16, 2, 0, 0, /* M factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_REPARENT | AW_CLK_HAS_GATE);/* flags */ From 0424f19e9e85f280834b4879febea79b1115cc06 Mon Sep 17 00:00:00 2001 From: Ruslan Bukin Date: Thu, 6 Aug 2020 12:49:25 +0000 Subject: [PATCH 130/141] Move dmar_domain_unload_task to busdma_iommu.c. Reviewed by: kib Sponsored by: DARPA/AFRL Differential Revision: https://reviews.freebsd.org/D25972 --- sys/dev/iommu/busdma_iommu.c | 21 +++++++++++++++++++++ sys/x86/iommu/intel_ctx.c | 23 ----------------------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/sys/dev/iommu/busdma_iommu.c b/sys/dev/iommu/busdma_iommu.c index a9db66ecc387..8e266f9f3eb1 100644 --- a/sys/dev/iommu/busdma_iommu.c +++ b/sys/dev/iommu/busdma_iommu.c @@ -1064,6 +1064,26 @@ bus_dma_iommu_load_ident(bus_dma_tag_t dmat, bus_dmamap_t map1, return (error); } +static void +iommu_domain_unload_task(void *arg, int pending) +{ + struct iommu_domain *domain; + struct iommu_map_entries_tailq entries; + + domain = arg; + TAILQ_INIT(&entries); + + for (;;) { + IOMMU_DOMAIN_LOCK(domain); + TAILQ_SWAP(&domain->unload_entries, &entries, + iommu_map_entry, dmamap_link); + IOMMU_DOMAIN_UNLOCK(domain); + if (TAILQ_EMPTY(&entries)) + break; + iommu_domain_unload(domain, &entries, true); + } +} + void iommu_domain_init(struct iommu_unit *unit, struct iommu_domain *domain, const struct iommu_domain_map_ops *ops) @@ -1072,6 +1092,7 @@ iommu_domain_init(struct iommu_unit *unit, struct iommu_domain *domain, domain->ops = ops; domain->iommu = unit; + TASK_INIT(&domain->unload_task, 0, iommu_domain_unload_task, domain); RB_INIT(&domain->rb_root); TAILQ_INIT(&domain->unload_entries); mtx_init(&domain->lock, "iodom", NULL, MTX_DEF); diff --git a/sys/x86/iommu/intel_ctx.c b/sys/x86/iommu/intel_ctx.c index 338316c425ee..207988ce30ba 100644 --- a/sys/x86/iommu/intel_ctx.c +++ b/sys/x86/iommu/intel_ctx.c @@ -74,7 +74,6 @@ __FBSDID("$FreeBSD$"); static MALLOC_DEFINE(M_DMAR_CTX, "dmar_ctx", "Intel DMAR Context"); static MALLOC_DEFINE(M_DMAR_DOMAIN, "dmar_dom", "Intel DMAR Domain"); -static void dmar_domain_unload_task(void *arg, int pending); static void dmar_unref_domain_locked(struct dmar_unit *dmar, struct dmar_domain *domain); static void dmar_domain_destroy(struct dmar_domain *domain); @@ -334,8 +333,6 @@ dmar_domain_alloc(struct dmar_unit *dmar, bool id_mapped) unit = DMAR2IOMMU(dmar); domain->domain = id; LIST_INIT(&domain->contexts); - TASK_INIT(&domain->iodom.unload_task, 0, dmar_domain_unload_task, - domain); iommu_domain_init(unit, iodom, &dmar_domain_map_ops); domain->dmar = dmar; @@ -875,26 +872,6 @@ dmar_domain_unload(struct dmar_domain *domain, } TAILQ_CONCAT(&unit->tlb_flush_entries, entries, dmamap_link); DMAR_UNLOCK(unit); -} - -static void -dmar_domain_unload_task(void *arg, int pending) -{ - struct dmar_domain *domain; - struct iommu_map_entries_tailq entries; - - domain = arg; - TAILQ_INIT(&entries); - - for (;;) { - DMAR_DOMAIN_LOCK(domain); - TAILQ_SWAP(&domain->iodom.unload_entries, &entries, - iommu_map_entry, dmamap_link); - DMAR_DOMAIN_UNLOCK(domain); - if (TAILQ_EMPTY(&entries)) - break; - dmar_domain_unload(domain, &entries, true); - } } struct iommu_ctx * From 0736ad87b96e41e17f9598eb9c50c794bf035e67 Mon Sep 17 00:00:00 2001 From: Hans Petter Selasky Date: Thu, 6 Aug 2020 13:25:04 +0000 Subject: [PATCH 131/141] Add new USB ID. Submitted by: Dmitry Luhtionov MFC after: 1 week Sponsored by: Mellanox Technologies --- sys/dev/rtwn/usb/rtwn_usb_attach.h | 1 + sys/dev/usb/usbdevs | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/sys/dev/rtwn/usb/rtwn_usb_attach.h b/sys/dev/rtwn/usb/rtwn_usb_attach.h index ee9cf6b30019..a690b23f25be 100644 --- a/sys/dev/rtwn/usb/rtwn_usb_attach.h +++ b/sys/dev/rtwn/usb/rtwn_usb_attach.h @@ -123,6 +123,7 @@ static const STRUCT_USB_HOST_ID rtwn_devs[] = { RTWN_RTL8188EU_DEV(TPLINK, WN727NV5), RTWN_RTL8188EU_DEV(REALTEK, RTL8188ETV), RTWN_RTL8188EU_DEV(REALTEK, RTL8188EU), + RTWN_RTL8188EU_DEV(MERCUSYS, MW150US), #undef RTWN_RTL8188EU_DEV /* RTL8812AU */ diff --git a/sys/dev/usb/usbdevs b/sys/dev/usb/usbdevs index c9e366bfe242..7639c8259836 100644 --- a/sys/dev/usb/usbdevs +++ b/sys/dev/usb/usbdevs @@ -782,6 +782,7 @@ vendor NHJ 0x2770 NHJ vendor THINGM 0x27b8 ThingM vendor PERASO 0x2932 Peraso Technologies, Inc. vendor PLANEX 0x2c02 Planex Communications +vendor MERCUSYS 0x2c4e Mercusys, Inc. vendor QUECTEL 0x2c7c Quectel Wireless Solutions vendor VIDZMEDIA 0x3275 VidzMedia Pte Ltd vendor LINKINSTRUMENTS 0x3195 Link Instruments Inc. @@ -3192,6 +3193,9 @@ product MELCO WIU2433DM 0x0242 WI-U2-433DM product MELCO WIU3866D 0x025d WI-U3-866D product MELCO WIU2433DHP 0x029b WI-U2-433DHP +/* Mercusys, Inc. */ +product MERCUSYS MW150US 0x0102 Mercusys MW150US + /* Merlin products */ product MERLIN V620 0x1110 Merlin V620 From c178a7e73ccb042a30b8a3634e5d92e2ae83c41e Mon Sep 17 00:00:00 2001 From: Andriy Gapon Date: Thu, 6 Aug 2020 13:41:42 +0000 Subject: [PATCH 132/141] cp2112: driver for the namesake GPIO and I2C master gadget Documentation: - CP2112 Datasheet https://www.silabs.com/documents/public/data-sheets/cp2112-datasheet.pdf - AN495: CP2112 Interface Specification https://www.silabs.com/documents/public/application-notes/an495-cp2112-interface-specification.pdf - CP2112 Errata https://www.silabs.com/documents/public/errata/cp2112-errata.pdf The logic is implemented as three sub-drivers. The parent driver claims the USB device and creates two child devices. One acts as a GPIO controller and the other is an I2C controller. Tested with CP2112 revision F02. Both features seem to work. HTU21 sensor was used as an I2C slave. Reviewed by: adrian, hselasky MFC after: 2 weeks Relnotes: maybe Differential Revision: https://reviews.freebsd.org/D25359 --- sys/conf/files | 1 + sys/dev/usb/misc/cp2112.c | 1381 +++++++++++++++++++++++++++++++ sys/modules/usb/Makefile | 1 + sys/modules/usb/cp2112/Makefile | 37 + 4 files changed, 1420 insertions(+) create mode 100644 sys/dev/usb/misc/cp2112.c create mode 100644 sys/modules/usb/cp2112/Makefile diff --git a/sys/conf/files b/sys/conf/files index cbb29fa45663..04e224437f93 100644 --- a/sys/conf/files +++ b/sys/conf/files @@ -3331,6 +3331,7 @@ dev/usb/serial/usb_serial.c optional ucom | u3g | uark | ubsa | ubser | \ # # USB misc drivers # +dev/usb/misc/cp2112.c optional cp2112 dev/usb/misc/ufm.c optional ufm dev/usb/misc/udbp.c optional udbp dev/usb/misc/ugold.c optional ugold diff --git a/sys/dev/usb/misc/cp2112.c b/sys/dev/usb/misc/cp2112.c new file mode 100644 index 000000000000..0430fdbfe56f --- /dev/null +++ b/sys/dev/usb/misc/cp2112.c @@ -0,0 +1,1381 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) Andriy Gapon + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +/* + * Hardware information links: + * - CP2112 Datasheet + * https://www.silabs.com/documents/public/data-sheets/cp2112-datasheet.pdf + * - AN495: CP2112 Interface Specification + * https://www.silabs.com/documents/public/application-notes/an495-cp2112-interface-specification.pdf + * - CP2112 Errata + * https://www.silabs.com/documents/public/errata/cp2112-errata.pdf + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include "iicbus_if.h" + +#include +#include +#include +#include +#include "usbdevs.h" + +#define USB_DEBUG_VAR usb_debug +#include + +#define CP2112GPIO_LOCK(sc) sx_xlock(&sc->gpio_lock) +#define CP2112GPIO_UNLOCK(sc) sx_xunlock(&sc->gpio_lock) +#define CP2112GPIO_LOCKED(sc) sx_assert(&sc->gpio_lock, SX_XLOCKED) + +#define CP2112_PART_NUM 0x0c +#define CP2112_GPIO_COUNT 8 +#define CP2112_REPORT_SIZE 64 + +#define CP2112_REQ_RESET 0x1 +#define CP2112_REQ_GPIO_CFG 0x2 +#define CP2112_REQ_GPIO_GET 0x3 +#define CP2112_REQ_GPIO_SET 0x4 +#define CP2112_REQ_VERSION 0x5 +#define CP2112_REQ_SMB_CFG 0x6 + +#define CP2112_REQ_SMB_READ 0x10 +#define CP2112_REQ_SMB_WRITE_READ 0x11 +#define CP2112_REQ_SMB_READ_FORCE_SEND 0x12 +#define CP2112_REQ_SMB_READ_RESPONSE 0x13 +#define CP2112_REQ_SMB_WRITE 0x14 +#define CP2112_REQ_SMB_XFER_STATUS_REQ 0x15 +#define CP2112_REQ_SMB_XFER_STATUS_RESP 0x16 +#define CP2112_REQ_SMB_CANCEL 0x17 + +#define CP2112_REQ_LOCK 0x20 +#define CP2112_REQ_USB_CFG 0x21 + +#define CP2112_IIC_REPSTART_VER 2 /* Erratum CP2112_E10. */ + +#define CP2112_IIC_STATUS0_IDLE 0 +#define CP2112_IIC_STATUS0_BUSY 1 +#define CP2112_IIC_STATUS0_CMP 2 +#define CP2112_IIC_STATUS0_ERROR 3 + +#define CP2112_IIC_STATUS1_TIMEOUT_NACK 0 +#define CP2112_IIC_STATUS1_TIMEOUT_BUS 1 +#define CP2112_IIC_STATUS1_ARB_LOST 2 + + +struct cp2112_softc { + device_t sc_gpio_dev; + device_t sc_iic_dev; + struct usb_device *sc_udev; + uint8_t sc_iface_index; + uint8_t sc_version; +}; + +struct cp2112gpio_softc { + struct sx gpio_lock; + device_t busdev; + int gpio_caps; + struct gpio_pin pins[CP2112_GPIO_COUNT]; +}; + +static int cp2112_detach(device_t dev); +static int cp2112gpio_detach(device_t dev); +static int cp2112iic_detach(device_t dev); + +static int +cp2112_get_report(device_t dev, uint8_t id, void *data, uint16_t len) +{ + struct cp2112_softc *sc; + int err; + + sc = device_get_softc(dev); + err = usbd_req_get_report(sc->sc_udev, NULL, data, + len, sc->sc_iface_index, UHID_FEATURE_REPORT, id); + return (err); +} + +static int +cp2112_set_report(device_t dev, uint8_t id, void *data, uint16_t len) +{ + struct cp2112_softc *sc; + int err; + + sc = device_get_softc(dev); + err = usbd_req_set_report(sc->sc_udev, NULL, data, + len, sc->sc_iface_index, UHID_FEATURE_REPORT, id); + return (err); +} + +static int +cp2112_gpio_read_pin(device_t dev, uint32_t pin_num, bool *on) +{ + struct { + uint8_t id; + uint8_t state; + } __packed data; + struct cp2112gpio_softc *sc; + int err; + + sc = device_get_softc(dev); + CP2112GPIO_LOCKED(sc); + + data.id = CP2112_REQ_GPIO_GET; + err = cp2112_get_report(device_get_parent(dev), + CP2112_REQ_GPIO_GET, &data, sizeof(data)); + if (err != 0) + return (err); + *on = (data.state & ((uint8_t)1 << pin_num)) != 0; + return (0); + +} + +static int +cp2112_gpio_write_pin(device_t dev, uint32_t pin_num, bool on) +{ + struct { + uint8_t id; + uint8_t state; + uint8_t mask; + } __packed data; + struct cp2112gpio_softc *sc; + int err; + bool actual; + + sc = device_get_softc(dev); + CP2112GPIO_LOCKED(sc); + + data.id = CP2112_REQ_GPIO_SET; + data.state = (uint8_t)on << pin_num; + data.mask = (uint8_t)1 << pin_num; + + err = cp2112_set_report(device_get_parent(dev), + CP2112_REQ_GPIO_SET, &data, sizeof(data)); + if (err != 0) + return (err); + err = cp2112_gpio_read_pin(dev, pin_num, &actual); + if (err != 0) + return (err); + if (actual != on) + return (EIO); + return (0); +} + +static int +cp2112_gpio_configure_write_pin(device_t dev, uint32_t pin_num, + bool output, bool pushpull) +{ + struct { + uint8_t id; + uint8_t output; + uint8_t pushpull; + uint8_t special; + uint8_t divider; + } __packed data; + struct cp2112gpio_softc *sc; + int err; + uint8_t mask; + + sc = device_get_softc(dev); + CP2112GPIO_LOCKED(sc); + + mask = (uint8_t)1 << pin_num; + data.id = CP2112_REQ_GPIO_CFG; + err = cp2112_get_report(device_get_parent(dev), + CP2112_REQ_GPIO_CFG, &data, sizeof(data)); + if (err != 0) + return (err); + if (output) { + data.output |= mask; + if (pushpull) + data.pushpull |= mask; + else + data.pushpull &= ~mask; + } else { + data.output &= ~mask; + data.pushpull &= ~mask; + } + + err = cp2112_set_report(device_get_parent(dev), + CP2112_REQ_GPIO_CFG, &data, sizeof(data)); + if (err != 0) + return (err); + + /* Read back and verify. */ + err = cp2112_get_report(device_get_parent(dev), + CP2112_REQ_GPIO_CFG, &data, sizeof(data)); + if (err != 0) + return (err); + if (((data.output & mask) != 0) != output) + return (EIO); + if (((data.pushpull & mask) != 0) != pushpull) + return (EIO); + return (0); +} + +static device_t +cp2112_gpio_get_bus(device_t dev) +{ + struct cp2112gpio_softc *sc; + + sc = device_get_softc(dev); + return (sc->busdev); +} + +static int +cp2112_gpio_pin_max(device_t dev, int *maxpin) +{ + + *maxpin = CP2112_GPIO_COUNT - 1; + return (0); +} + +static int +cp2112_gpio_pin_set(device_t dev, uint32_t pin_num, uint32_t pin_value) +{ + struct cp2112gpio_softc *sc; + int err; + + if (pin_num >= CP2112_GPIO_COUNT) + return (EINVAL); + + sc = device_get_softc(dev); + CP2112GPIO_LOCK(sc); + err = cp2112_gpio_write_pin(dev, pin_num, pin_value != 0); + CP2112GPIO_UNLOCK(sc); + + return (err); +} + +static int +cp2112_gpio_pin_get(device_t dev, uint32_t pin_num, uint32_t *pin_value) +{ + struct cp2112gpio_softc *sc; + int err; + bool on; + + if (pin_num >= CP2112_GPIO_COUNT) + return (EINVAL); + + sc = device_get_softc(dev); + CP2112GPIO_LOCK(sc); + err = cp2112_gpio_read_pin(dev, pin_num, &on); + CP2112GPIO_UNLOCK(sc); + + if (err == 0) + *pin_value = on; + return (err); +} + +static int +cp2112_gpio_pin_toggle(device_t dev, uint32_t pin_num) +{ + struct cp2112gpio_softc *sc; + int err; + bool on; + + if (pin_num >= CP2112_GPIO_COUNT) + return (EINVAL); + + sc = device_get_softc(dev); + CP2112GPIO_LOCK(sc); + err = cp2112_gpio_read_pin(dev, pin_num, &on); + if (err == 0) + err = cp2112_gpio_write_pin(dev, pin_num, !on); + CP2112GPIO_UNLOCK(sc); + + return (err); +} + +static int +cp2112_gpio_pin_getcaps(device_t dev, uint32_t pin_num, uint32_t *caps) +{ + struct cp2112gpio_softc *sc; + + if (pin_num >= CP2112_GPIO_COUNT) + return (EINVAL); + + sc = device_get_softc(dev); + CP2112GPIO_LOCK(sc); + *caps = sc->gpio_caps; + CP2112GPIO_UNLOCK(sc); + + return (0); +} + +static int +cp2112_gpio_pin_getflags(device_t dev, uint32_t pin_num, uint32_t *flags) +{ + struct cp2112gpio_softc *sc; + + if (pin_num >= CP2112_GPIO_COUNT) + return (EINVAL); + + sc = device_get_softc(dev); + CP2112GPIO_LOCK(sc); + *flags = sc->pins[pin_num].gp_flags; + CP2112GPIO_UNLOCK(sc); + + return (0); +} + +static int +cp2112_gpio_pin_getname(device_t dev, uint32_t pin_num, char *name) +{ + struct cp2112gpio_softc *sc; + + if (pin_num >= CP2112_GPIO_COUNT) + return (EINVAL); + + sc = device_get_softc(dev); + CP2112GPIO_LOCK(sc); + memcpy(name, sc->pins[pin_num].gp_name, GPIOMAXNAME); + CP2112GPIO_UNLOCK(sc); + + return (0); +} + +static int +cp2112_gpio_pin_setflags(device_t dev, uint32_t pin_num, uint32_t flags) +{ + struct cp2112gpio_softc *sc; + struct gpio_pin *pin; + int err; + + if (pin_num >= CP2112_GPIO_COUNT) + return (EINVAL); + + sc = device_get_softc(dev); + if ((flags & sc->gpio_caps) != flags) + return (EINVAL); + + if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) == 0) + return (EINVAL); + if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) == + (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) { + return (EINVAL); + } + if ((flags & GPIO_PIN_INPUT) != 0) { + if ((flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) != 0) + return (EINVAL); + } else { + if ((flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) == + (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) + return (EINVAL); + } + + CP2112GPIO_LOCK(sc); + pin = &sc->pins[pin_num]; + + /* + * If neither push-pull or opendrain is explcitely requested, then + * preserve the current state. + */ + if ((flags & GPIO_PIN_OUTPUT) != 0 && + (flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) == 0) + flags |= pin->gp_flags & (GPIO_PIN_OPENDRAIN|GPIO_PIN_PUSHPULL); + err = cp2112_gpio_configure_write_pin(dev, pin_num, + (flags & GPIO_PIN_OUTPUT) != 0, + (flags & GPIO_PIN_PUSHPULL) != 0); + if (err == 0) + pin->gp_flags = flags; + CP2112GPIO_UNLOCK(sc); + + return (err); +} + +static const STRUCT_USB_HOST_ID cp2112_devs[] = { + { USB_VP(USB_VENDOR_SILABS, USB_PRODUCT_SILABS_CP2112) }, + { USB_VP(0x1009, USB_PRODUCT_SILABS_CP2112) }, /* XXX */ +}; + +static int +cp2112_probe(device_t dev) +{ + struct usb_attach_arg *uaa; + + uaa = device_get_ivars(dev); + if (uaa->usb_mode != USB_MODE_HOST) + return (ENXIO); + if (uaa->info.bInterfaceClass != UICLASS_HID) + return (ENXIO); + + if (usbd_lookup_id_by_uaa(cp2112_devs, sizeof(cp2112_devs), uaa) == 0) + return (BUS_PROBE_DEFAULT); + return (ENXIO); +} + +static int +cp2112_attach(device_t dev) +{ + struct { + uint8_t id; + uint8_t part_num; + uint8_t version; + } __packed vdata; + struct usb_attach_arg *uaa; + struct cp2112_softc *sc; + int err; + + uaa = device_get_ivars(dev); + sc = device_get_softc(dev); + + device_set_usb_desc(dev); + + sc->sc_udev = uaa->device; + sc->sc_iface_index = uaa->info.bIfaceIndex; + + vdata.id = CP2112_REQ_VERSION; + err = cp2112_get_report(dev, CP2112_REQ_VERSION, &vdata, sizeof(vdata)); + if (err != 0) + goto detach; + device_printf(dev, "part number 0x%02x, version 0x%02x\n", + vdata.part_num, vdata.version); + if (vdata.part_num != CP2112_PART_NUM) { + device_printf(dev, "unsupported part number\n"); + goto detach; + } + sc->sc_version = vdata.version; + sc->sc_gpio_dev = device_add_child(dev, "gpio", -1); + if (sc->sc_gpio_dev != NULL) { + err = device_probe_and_attach(sc->sc_gpio_dev); + if (err != 0) { + device_printf(dev, "failed to attach gpio child\n"); + } + } else { + device_printf(dev, "failed to create gpio child\n"); + } + + sc->sc_iic_dev = device_add_child(dev, "iichb", -1); + if (sc->sc_iic_dev != NULL) { + err = device_probe_and_attach(sc->sc_iic_dev); + if (err != 0) { + device_printf(dev, "failed to attach iic child\n"); + } + } else { + device_printf(dev, "failed to create iic child\n"); + } + + return (0); + +detach: + cp2112_detach(dev); + return (ENXIO); +} + +static int +cp2112_detach(device_t dev) +{ + int err; + + err = bus_generic_detach(dev); + if (err != 0) + return (err); + device_delete_children(dev); + return (0); +} + +static int +cp2112gpio_probe(device_t dev) +{ + device_set_desc(dev, "CP2112 GPIO interface"); + return (BUS_PROBE_SPECIFIC); +} + +static int +cp2112gpio_attach(device_t dev) +{ + struct { + uint8_t id; + uint8_t output; + uint8_t pushpull; + uint8_t special; + uint8_t divider; + } __packed data; + struct cp2112gpio_softc *sc; + device_t cp2112; + int err; + int i; + uint8_t mask; + + cp2112 = device_get_parent(dev); + sc = device_get_softc(dev); + sx_init(&sc->gpio_lock, "cp2112 lock"); + + sc->gpio_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | + GPIO_PIN_PUSHPULL; + + data.id = CP2112_REQ_GPIO_CFG; + err = cp2112_get_report(cp2112, CP2112_REQ_GPIO_CFG, + &data, sizeof(data)); + if (err != 0) + goto detach; + + for (i = 0; i < CP2112_GPIO_COUNT; i++) { + struct gpio_pin *pin; + + mask = (uint8_t)1 << i; + pin = &sc->pins[i]; + pin->gp_flags = 0; + + snprintf(pin->gp_name, GPIOMAXNAME, "GPIO%u", i); + pin->gp_name[GPIOMAXNAME - 1] = '\0'; + + if ((data.output & mask) != 0) { + pin->gp_flags |= GPIO_PIN_OUTPUT; + if ((data.pushpull & mask) != 0) + pin->gp_flags |= GPIO_PIN_PUSHPULL; + else + pin->gp_flags |= GPIO_PIN_OPENDRAIN; + } else { + pin->gp_flags |= GPIO_PIN_INPUT; + } + } + + sc->busdev = gpiobus_attach_bus(dev); + if (sc->busdev == NULL) { + device_printf(dev, "gpiobus_attach_bus failed\n"); + goto detach; + } + return (0); + +detach: + cp2112gpio_detach(dev); + return (ENXIO); +} + +static int +cp2112gpio_detach(device_t dev) +{ + struct cp2112gpio_softc *sc; + + sc = device_get_softc(dev); + if (sc->busdev != NULL) + gpiobus_detach_bus(dev); + sx_destroy(&sc->gpio_lock); + return (0); +} + +static device_method_t cp2112hid_methods[] = { + DEVMETHOD(device_probe, cp2112_probe), + DEVMETHOD(device_attach, cp2112_attach), + DEVMETHOD(device_detach, cp2112_detach), + + DEVMETHOD_END +}; + +static device_method_t cp2112gpio_methods[] = { + /* Device */ + DEVMETHOD(device_probe, cp2112gpio_probe), + DEVMETHOD(device_attach, cp2112gpio_attach), + DEVMETHOD(device_detach, cp2112gpio_detach), + + /* GPIO */ + DEVMETHOD(gpio_get_bus, cp2112_gpio_get_bus), + DEVMETHOD(gpio_pin_max, cp2112_gpio_pin_max), + DEVMETHOD(gpio_pin_get, cp2112_gpio_pin_get), + DEVMETHOD(gpio_pin_set, cp2112_gpio_pin_set), + DEVMETHOD(gpio_pin_toggle, cp2112_gpio_pin_toggle), + DEVMETHOD(gpio_pin_getname, cp2112_gpio_pin_getname), + DEVMETHOD(gpio_pin_getcaps, cp2112_gpio_pin_getcaps), + DEVMETHOD(gpio_pin_getflags, cp2112_gpio_pin_getflags), + DEVMETHOD(gpio_pin_setflags, cp2112_gpio_pin_setflags), + + DEVMETHOD_END +}; + +static driver_t cp2112hid_driver = { + .name = "cp2112hid", + .methods = cp2112hid_methods, + .size = sizeof(struct cp2112_softc), +}; + +static devclass_t cp2112hid_devclass; +DRIVER_MODULE(cp2112hid, uhub, cp2112hid_driver, cp2112hid_devclass, + NULL, NULL); +MODULE_DEPEND(cp2112hid, usb, 1, 1, 1); +MODULE_VERSION(cp2112hid, 1); +USB_PNP_HOST_INFO(cp2112_devs); + +static driver_t cp2112gpio_driver = { + .name = "gpio", + .methods = cp2112gpio_methods, + .size = sizeof(struct cp2112gpio_softc), +}; + +static devclass_t cp2112gpio_devclass; +DRIVER_MODULE(cp2112gpio, cp2112hid, cp2112gpio_driver, cp2112gpio_devclass, + NULL, NULL); +MODULE_DEPEND(cp2112gpio, cp2112hid, 1, 1, 1); +MODULE_DEPEND(cp2112gpio, gpiobus, 1, 1, 1); +MODULE_VERSION(cp2112gpio, 1); + + + +/* CP2112 I2C driver code. */ + + +enum { + CP2112_INTR_OUT = 0, + CP2112_INTR_IN, + CP2112_N_TRANSFER, +}; + +struct cp2112iic_softc { + device_t dev; + device_t iicbus_dev; + struct usb_xfer *xfers[CP2112_N_TRANSFER]; + u_char own_addr; + struct { + struct mtx lock; + struct cv cv; + struct { + uint8_t *data; + int len; + int done; + int error; + } in; + struct { + const uint8_t *data; + int len; + int done; + int error; + } out; + } io; +}; + +static void +cp2112iic_intr_write_callback(struct usb_xfer *xfer, usb_error_t error) +{ + struct cp2112iic_softc *sc; + struct cp2112_softc *psc; + struct usb_page_cache *pc; + + sc = usbd_xfer_softc(xfer); + psc = device_get_softc(device_get_parent(sc->dev)); + + mtx_assert(&sc->io.lock, MA_OWNED); + + switch (USB_GET_STATE(xfer)) { + case USB_ST_SETUP: + pc = usbd_xfer_get_frame(xfer, 0); + usbd_copy_in(pc, 0, sc->io.out.data, sc->io.out.len); + usbd_xfer_set_frame_len(xfer, 0, sc->io.out.len); + usbd_xfer_set_frames(xfer, 1); + usbd_transfer_submit(xfer); + break; + case USB_ST_TRANSFERRED: + sc->io.out.error = 0; + sc->io.out.done = 1; + cv_signal(&sc->io.cv); + break; + default: /* Error */ + device_printf(sc->dev, "write intr state %d error %d\n", + USB_GET_STATE(xfer), error); + sc->io.out.error = IIC_EBUSERR; + cv_signal(&sc->io.cv); + if (error != USB_ERR_CANCELLED) { + /* try to clear stall first */ + usbd_xfer_set_stall(xfer); + } + break; + } +} + +static void +cp2112iic_intr_read_callback(struct usb_xfer *xfer, usb_error_t error) +{ + struct cp2112iic_softc *sc = usbd_xfer_softc(xfer); + struct usb_page_cache *pc; + int act_len, len; + + mtx_assert(&sc->io.lock, MA_OWNED); + usbd_xfer_status(xfer, &act_len, NULL, NULL, NULL); + + switch (USB_GET_STATE(xfer)) { + case USB_ST_TRANSFERRED: + if (sc->io.in.done) { + device_printf(sc->dev, + "interrupt while previous is pending, ignored\n"); + } else if (sc->io.in.len == 0) { + uint8_t buf[8]; + + /* + * There is a spurious Transfer Status Response and + * zero-length Read Response during hardware + * configuration. Possibly they carry some information + * about the initial bus state. + */ + if (device_is_attached(sc->dev)) { + device_printf(sc->dev, + "unsolicited interrupt, ignored\n"); + if (bootverbose) { + pc = usbd_xfer_get_frame(xfer, 0); + len = MIN(sizeof(buf), act_len); + usbd_copy_out(pc, 0, buf, len); + device_printf(sc->dev, "data: %*D\n", + len, buf, " "); + } + } else { + pc = usbd_xfer_get_frame(xfer, 0); + len = MIN(sizeof(buf), act_len); + usbd_copy_out(pc, 0, buf, len); + if (buf[0] == CP2112_REQ_SMB_XFER_STATUS_RESP) { + device_printf(sc->dev, + "initial bus status0 = 0x%02x, " + "status1 = 0x%02x\n", + buf[1], buf[2]); + } + } + } else if (act_len == CP2112_REPORT_SIZE) { + pc = usbd_xfer_get_frame(xfer, 0); + usbd_copy_out(pc, 0, sc->io.in.data, sc->io.in.len); + sc->io.in.error = 0; + sc->io.in.done = 1; + } else { + device_printf(sc->dev, + "unexpected input report length %u\n", act_len); + sc->io.in.error = IIC_EBUSERR; + sc->io.in.done = 1; + } + cv_signal(&sc->io.cv); + case USB_ST_SETUP: +tr_setup: + usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); + usbd_transfer_submit(xfer); + break; + + default: /* Error */ + device_printf(sc->dev, "read intr state %d error %d\n", + USB_GET_STATE(xfer), error); + + sc->io.in.error = IIC_EBUSERR; + sc->io.in.done = 1; + cv_signal(&sc->io.cv); + if (error != USB_ERR_CANCELLED) { + /* try to clear stall first */ + usbd_xfer_set_stall(xfer); + goto tr_setup; + } + break; + } +} + +static const struct usb_config cp2112iic_config[CP2112_N_TRANSFER] = { + [CP2112_INTR_OUT] = { + .type = UE_INTERRUPT, + .endpoint = UE_ADDR_ANY, + .direction = UE_DIR_OUT, + .flags = { .pipe_bof = 1, .no_pipe_ok = 1, }, + .bufsize = 0, /* use wMaxPacketSize */ + .callback = &cp2112iic_intr_write_callback, + }, + [CP2112_INTR_IN] = { + .type = UE_INTERRUPT, + .endpoint = UE_ADDR_ANY, + .direction = UE_DIR_IN, + .flags = { .pipe_bof = 1, .short_xfer_ok = 1, }, + .bufsize = 0, /* use wMaxPacketSize */ + .callback = &cp2112iic_intr_read_callback, + }, +}; + +static int +cp2112iic_send_req(struct cp2112iic_softc *sc, const void *data, + uint16_t len) +{ + int err; + + mtx_assert(&sc->io.lock, MA_OWNED); + KASSERT(sc->io.out.done == 0, ("%s: conflicting request", __func__)); + + sc->io.out.data = data; + sc->io.out.len = len; + + DTRACE_PROBE1(send__req, uint8_t, *(const uint8_t *)data); + + usbd_transfer_start(sc->xfers[CP2112_INTR_OUT]); + + while (!sc->io.out.done) + cv_wait(&sc->io.cv, &sc->io.lock); + + usbd_transfer_stop(sc->xfers[CP2112_INTR_OUT]); + + sc->io.out.done = 0; + sc->io.out.data = NULL; + sc->io.out.len = 0; + err = sc->io.out.error; + if (err != 0) { + device_printf(sc->dev, "output report 0x%02x failed: %d\n", + *(const uint8_t*)data, err); + } + return (err); +} + +static int +cp2112iic_req_resp(struct cp2112iic_softc *sc, const void *req_data, + uint16_t req_len, void *resp_data, uint16_t resp_len) +{ + int err; + + mtx_assert(&sc->io.lock, MA_OWNED); + + /* + * Prepare to receive a response interrupt even before the + * request transfer is confirmed (USB_ST_TRANSFERED). + */ + KASSERT(sc->io.in.done == 0, ("%s: conflicting request", __func__)); + sc->io.in.len = resp_len; + sc->io.in.data = resp_data; + + err = cp2112iic_send_req(sc, req_data, req_len); + if (err != 0) { + sc->io.in.len = 0; + sc->io.in.data = NULL; + return (err); + } + + while (!sc->io.in.done) + cv_wait(&sc->io.cv, &sc->io.lock); + + err = sc->io.in.error; + sc->io.in.done = 0; + sc->io.in.error = 0; + sc->io.in.len = 0; + sc->io.in.data = NULL; + return (err); +} + +static int +cp2112iic_check_req_status(struct cp2112iic_softc *sc) +{ + struct { + uint8_t id; + uint8_t request; + } __packed xfer_status_req; + struct { + uint8_t id; + uint8_t status0; + uint8_t status1; + uint16_t status2; + uint16_t status3; + } __packed xfer_status_resp; + int err; + + mtx_assert(&sc->io.lock, MA_OWNED); + + do { + xfer_status_req.id = CP2112_REQ_SMB_XFER_STATUS_REQ; + xfer_status_req.request = 1; + err = cp2112iic_req_resp(sc, + &xfer_status_req, sizeof(xfer_status_req), + &xfer_status_resp, sizeof(xfer_status_resp)); + + if (xfer_status_resp.id != CP2112_REQ_SMB_XFER_STATUS_RESP) { + device_printf(sc->dev, + "unexpected response 0x%02x to status request\n", + xfer_status_resp.id); + err = IIC_EBUSERR; + goto out; + } + + DTRACE_PROBE4(xfer__status, uint8_t, xfer_status_resp.status0, + uint8_t, xfer_status_resp.status1, + uint16_t, be16toh(xfer_status_resp.status2), + uint16_t, be16toh(xfer_status_resp.status3)); + + switch (xfer_status_resp.status0) { + case CP2112_IIC_STATUS0_IDLE: + err = IIC_ESTATUS; + break; + case CP2112_IIC_STATUS0_BUSY: + err = ERESTART; /* non-I2C, special handling */ + break; + case CP2112_IIC_STATUS0_CMP: + err = IIC_NOERR; + break; + case CP2112_IIC_STATUS0_ERROR: + switch (xfer_status_resp.status1) { + case CP2112_IIC_STATUS1_TIMEOUT_NACK: + err = IIC_ENOACK; + break; + case CP2112_IIC_STATUS1_TIMEOUT_BUS: + err = IIC_ETIMEOUT; + break; + case CP2112_IIC_STATUS1_ARB_LOST: + err = IIC_EBUSBSY; + break; + default: + device_printf(sc->dev, + "i2c error, status = 0x%02x\n", + xfer_status_resp.status1); + err = IIC_ESTATUS; + break; + } + break; + default: + device_printf(sc->dev, + "unknown i2c xfer status0 0x%02x\n", + xfer_status_resp.status0); + err = IIC_EBUSERR; + break; + } + + } while (err == ERESTART); +out: + return (err); +} + +static int +cp2112iic_read_data(struct cp2112iic_softc *sc, void *data, uint16_t in_len, + uint16_t *out_len) +{ + struct { + uint8_t id; + uint16_t length; + } __packed data_read_force_send; + struct { + uint8_t id; + uint8_t status; + uint8_t length; + uint8_t data[61]; + } __packed data_read_resp; + int err; + + mtx_assert(&sc->io.lock, MA_OWNED); + + /* + * Prepare to receive a response interrupt even before the request + * transfer is confirmed (USB_ST_TRANSFERED). + */ + + if (in_len > sizeof(data_read_resp.data)) + in_len = sizeof(data_read_resp.data); + data_read_force_send.id = CP2112_REQ_SMB_READ_FORCE_SEND; + data_read_force_send.length = htobe16(in_len); + err = cp2112iic_req_resp(sc, + &data_read_force_send, sizeof(data_read_force_send), + &data_read_resp, sizeof(data_read_resp)); + if (err != 0) + goto out; + + if (data_read_resp.id != CP2112_REQ_SMB_READ_RESPONSE) { + device_printf(sc->dev, + "unexpected response 0x%02x to data read request\n", + data_read_resp.id); + err = IIC_EBUSERR; + goto out; + } + + DTRACE_PROBE2(read__response, uint8_t, data_read_resp.status, + uint8_t, data_read_resp.length); + + /* + * We expect either the request completed status or, more typical for + * this driver, the bus idle status because of the preceding + * Force Read Status command (which is not an I2C request). + */ + if (data_read_resp.status != CP2112_IIC_STATUS0_CMP && + data_read_resp.status != CP2112_IIC_STATUS0_IDLE) { + err = IIC_EBUSERR; + goto out; + } + if (data_read_resp.length > in_len) { + device_printf(sc->dev, "device returns more data than asked\n"); + err = IIC_EOVERFLOW; + goto out; + } + + *out_len = data_read_resp.length; + if (*out_len > 0) + memcpy(data, data_read_resp.data, *out_len); +out: + return (err); +} + + +static int +cp2112iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) +{ + struct cp2112iic_softc *sc = device_get_softc(dev); + struct cp2112_softc *psc = device_get_softc(device_get_parent(dev)); + const char *reason = NULL; + uint32_t i; + uint16_t read_off, to_read; + int err; + + /* + * The hardware interface imposes limits on allowed I2C messages. + * It is not possible to explicitly send a start or stop. + * It is not possible to do a zero length transfer. + * For this reason it's impossible to send a message with no data + * at all (like an SMBus quick message). + * Each read or write transfer beginning with the start condition + * and ends with the stop condition. The only exception is that + * it is possible to have a write transfer followed by a read + * transfer to the same slave with the repeated start condition + * between them. + */ + for (i = 0; i < nmsgs; i++) { + if (i == 0 && (msgs[i].flags & IIC_M_NOSTART) != 0) { + reason = "first message without start"; + break; + } + if (i == nmsgs - 1 && (msgs[i].flags & IIC_M_NOSTOP) != 0) { + reason = "last message without stop"; + break; + } + if (msgs[i].len == 0) { + reason = "message with no data"; + break; + } + if ((msgs[i].flags & IIC_M_RD) != 0 && msgs[i].len > 512) { + reason = "too long read"; + break; + } + if ((msgs[i].flags & IIC_M_RD) == 0 && msgs[i].len > 61) { + reason = "too long write"; + break; + } + if ((msgs[i].flags & IIC_M_NOSTART) != 0) { + reason = "message without start or repeated start"; + break; + } + if ((msgs[i].flags & IIC_M_NOSTOP) != 0 && + (msgs[i].flags & IIC_M_RD) != 0) { + reason = "read without stop"; + break; + } + if ((msgs[i].flags & IIC_M_NOSTOP) != 0 && + psc->sc_version < CP2112_IIC_REPSTART_VER) { + reason = "write without stop"; + break; + } + if ((msgs[i].flags & IIC_M_NOSTOP) != 0 && msgs[i].len > 16) { + reason = "too long write without stop"; + break; + } + if (i > 0) { + if ((msgs[i - 1].flags & IIC_M_NOSTOP) != 0 && + msgs[i].slave != msgs[i - 1].slave) { + reason = "change of slave without stop"; + break; + } + if ((msgs[i - 1].flags & IIC_M_NOSTOP) != 0 && + (msgs[i].flags & IIC_M_RD) == 0) { + reason = "write after repeated start"; + break; + } + } + } + if (reason != NULL) { + if (bootverbose) + device_printf(dev, "unsupported i2c message: %s\n", + reason); + return (IIC_ENOTSUPP); + } + + mtx_lock(&sc->io.lock); + + for (i = 0; i < nmsgs; i++) { + if (i + 1 < nmsgs && (msgs[i].flags & IIC_M_NOSTOP) != 0) { + KASSERT((msgs[i].flags & IIC_M_RD) == 0, + ("read without stop")); + KASSERT((msgs[i + 1].flags & IIC_M_RD) != 0, + ("write after write without stop")); + /* + * Combine into a single + * CP2112 operation. + */ + struct { + uint8_t id; + uint8_t slave; + uint16_t rlen; + uint8_t wlen; + uint8_t wdata[16]; + } __packed req; + + req.id = CP2112_REQ_SMB_WRITE_READ; + req.slave = msgs[i].slave & ~LSB; + to_read = msgs[i + 1].len; + req.rlen = htobe16(to_read); + req.wlen = msgs[i].len; + memcpy(req.wdata, msgs[i].buf, msgs[i].len); + err = cp2112iic_send_req(sc, &req, msgs[i].len + 5); + + /* + * The next message is already handled. + * Also needed for read data to go into the right msg. + */ + i++; + } else if ((msgs[i].flags & IIC_M_RD) != 0) { + struct { + uint8_t id; + uint8_t slave; + uint16_t len; + } __packed req; + + req.id = CP2112_REQ_SMB_READ; + req.slave = msgs[i].slave & ~LSB; + to_read = msgs[i].len; + req.len = htobe16(to_read); + err = cp2112iic_send_req(sc, &req, sizeof(req)); + } else { + struct { + uint8_t id; + uint8_t slave; + uint8_t len; + uint8_t data[61]; + } __packed req; + + req.id = CP2112_REQ_SMB_WRITE; + req.slave = msgs[i].slave & ~LSB; + req.len = msgs[i].len; + memcpy(req.data, msgs[i].buf, msgs[i].len); + to_read = 0; + err = cp2112iic_send_req(sc, &req, msgs[i].len + 3); + } + if (err != 0) + break; + + err = cp2112iic_check_req_status(sc); + if (err != 0) + break; + + read_off = 0; + while (to_read > 0) { + uint16_t act_read; + + err = cp2112iic_read_data(sc, msgs[i].buf + read_off, + to_read, &act_read); + if (err != 0) + break; + KASSERT(act_read <= to_read, ("cp2112iic_read_data " + "returned more data than asked")); + read_off += act_read; + to_read -= act_read; + } + if (err != 0) + break; + } + + mtx_unlock(&sc->io.lock); + return (err); +} + +static int +cp2112iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) +{ + struct { + uint8_t id; + uint32_t speed; /* Hz */ + uint8_t slave_addr; /* ACK only */ + uint8_t auto_send_read; /* boolean */ + uint16_t write_timeout; /* 0-1000 ms, 0 ~ no timeout */ + uint16_t read_timeout; /* 0-1000 ms, 0 ~ no timeout */ + uint8_t scl_low_timeout;/* boolean */ + uint16_t retry_count; /* 1-1000, 0 ~ forever */ + } __packed smb_cfg; + struct cp2112iic_softc *sc; + device_t cp2112; + u_int busfreq; + int err; + + sc = device_get_softc(dev); + cp2112 = device_get_parent(dev); + if (sc->iicbus_dev == NULL) + busfreq = 100000; + else + busfreq = IICBUS_GET_FREQUENCY(sc->iicbus_dev, speed); + + smb_cfg.id = CP2112_REQ_SMB_CFG; + err = cp2112_get_report(cp2112, CP2112_REQ_SMB_CFG, + &smb_cfg, sizeof(smb_cfg)); + if (err != 0) { + device_printf(dev, "failed to get CP2112_REQ_SMB_CFG report\n"); + return (err); + } + + if (oldaddr != NULL) + *oldaddr = smb_cfg.slave_addr; + /* + * For simplicity we do not enable Auto Send Read + * because of erratum CP2112_E101 (fixed in version 3). + * + * TODO: set I2C parameters based on configuration preferences: + * - read and write timeouts (no timeout by default), + * - SCL low timeout (disabled by default), + * etc. + * + * TODO: should the device reset request (0x01) be sent? + * If the device disconnects as a result, then no. + */ + smb_cfg.speed = htobe32(busfreq); + if (addr != 0) + smb_cfg.slave_addr = addr; + smb_cfg.auto_send_read = 0; + smb_cfg.retry_count = htobe16(1); + smb_cfg.scl_low_timeout = 0; + if (bootverbose) { + device_printf(dev, "speed %d Hz\n", be32toh(smb_cfg.speed)); + device_printf(dev, "slave addr 0x%02x\n", smb_cfg.slave_addr); + device_printf(dev, "auto send read %s\n", + smb_cfg.auto_send_read ? "on" : "off"); + device_printf(dev, "write timeout %d ms (0 - disabled)\n", + be16toh(smb_cfg.write_timeout)); + device_printf(dev, "read timeout %d ms (0 - disabled)\n", + be16toh(smb_cfg.read_timeout)); + device_printf(dev, "scl low timeout %s\n", + smb_cfg.scl_low_timeout ? "on" : "off"); + device_printf(dev, "retry count %d (0 - no limit)\n", + be16toh(smb_cfg.retry_count)); + } + err = cp2112_set_report(cp2112, CP2112_REQ_SMB_CFG, + &smb_cfg, sizeof(smb_cfg)); + if (err != 0) { + device_printf(dev, "failed to set CP2112_REQ_SMB_CFG report\n"); + return (err); + } + return (0); +} + +static int +cp2112iic_probe(device_t dev) +{ + device_set_desc(dev, "CP2112 I2C interface"); + return (BUS_PROBE_SPECIFIC); +} + +static int +cp2112iic_attach(device_t dev) +{ + struct cp2112iic_softc *sc; + struct cp2112_softc *psc; + device_t cp2112; + int err; + + sc = device_get_softc(dev); + sc->dev = dev; + cp2112 = device_get_parent(dev); + psc = device_get_softc(cp2112); + + mtx_init(&sc->io.lock, "cp2112iic lock", NULL, MTX_DEF | MTX_RECURSE); + cv_init(&sc->io.cv, "cp2112iic cv"); + + err = usbd_transfer_setup(psc->sc_udev, + &psc->sc_iface_index, sc->xfers, cp2112iic_config, + nitems(cp2112iic_config), sc, &sc->io.lock); + if (err != 0) { + device_printf(dev, "usbd_transfer_setup failed %d\n", err); + goto detach; + } + + /* Prepare to receive interrupts. */ + mtx_lock(&sc->io.lock); + usbd_transfer_start(sc->xfers[CP2112_INTR_IN]); + mtx_unlock(&sc->io.lock); + + sc->iicbus_dev = device_add_child(dev, "iicbus", -1); + if (sc->iicbus_dev == NULL) { + device_printf(dev, "iicbus creation failed\n"); + err = ENXIO; + goto detach; + } + bus_generic_attach(dev); + return (0); + +detach: + cp2112iic_detach(dev); + return (err); +} + +static int +cp2112iic_detach(device_t dev) +{ + struct cp2112iic_softc *sc; + int err; + + sc = device_get_softc(dev); + err = bus_generic_detach(dev); + if (err != 0) + return (err); + device_delete_children(dev); + + mtx_lock(&sc->io.lock); + usbd_transfer_stop(sc->xfers[CP2112_INTR_IN]); + mtx_unlock(&sc->io.lock); + usbd_transfer_unsetup(sc->xfers, nitems(cp2112iic_config)); + + cv_destroy(&sc->io.cv); + mtx_destroy(&sc->io.lock); + + return (0); +} + +static device_method_t cp2112iic_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, cp2112iic_probe), + DEVMETHOD(device_attach, cp2112iic_attach), + DEVMETHOD(device_detach, cp2112iic_detach), + + /* I2C methods */ + DEVMETHOD(iicbus_transfer, cp2112iic_transfer), + DEVMETHOD(iicbus_reset, cp2112iic_reset), + DEVMETHOD(iicbus_callback, iicbus_null_callback), + + DEVMETHOD_END +}; + +static driver_t cp2112iic_driver = { + "iichb", + cp2112iic_methods, + sizeof(struct cp2112iic_softc) +}; + +static devclass_t cp2112iic_devclass; +DRIVER_MODULE(cp2112iic, cp2112hid, cp2112iic_driver, cp2112iic_devclass, + NULL, NULL); +MODULE_DEPEND(cp2112iic, cp2112hid, 1, 1, 1); +MODULE_DEPEND(cp2112iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); +MODULE_VERSION(cp2112iic, 1); diff --git a/sys/modules/usb/Makefile b/sys/modules/usb/Makefile index 59ee709edd3f..bb6de370e667 100644 --- a/sys/modules/usb/Makefile +++ b/sys/modules/usb/Makefile @@ -50,6 +50,7 @@ SUBDIR += ${_rum} ${_run} ${_runfw} ${_uath} upgt usie ural ${_zyd} ${_urtw} SUBDIR += atp cfumass uhid uhid_snes ukbd ums udbp ufm uep wmt wsp ugold uled SUBDIR += ucom u3g uark ubsa ubser uchcom ucycom ufoma uftdi ugensa uipaq ulpt \ umct umcs umodem umoscom uplcom uslcom uvisor uvscom +SUBDIR += cp2112 SUBDIR += udl SUBDIR += uether aue axe axge cdce cdceem cue ${_kue} mos rue smsc udav uhso \ ipheth diff --git a/sys/modules/usb/cp2112/Makefile b/sys/modules/usb/cp2112/Makefile new file mode 100644 index 000000000000..dd0213842ecf --- /dev/null +++ b/sys/modules/usb/cp2112/Makefile @@ -0,0 +1,37 @@ +# +# $FreeBSD$ +# +# Copyright (c) Andriy Gapon +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGE. +# + +S= ${SRCTOP}/sys + +.PATH: $S/dev/usb/misc + +KMOD= cp2112 +SRCS= cp2112.c +SRCS+= opt_bus.h opt_usb.h +SRCS+= device_if.h bus_if.h gpio_if.h iicbus_if.h usb_if.h usbdevs.h + +.include From 32e50ae4647aca43192e9d3147327be3c8c14825 Mon Sep 17 00:00:00 2001 From: Alexander Motin Date: Thu, 6 Aug 2020 15:17:44 +0000 Subject: [PATCH 133/141] Add Intel Apollo Lake AHCI ID. Submitted by: Dmitry Luhtionov MFC after: 1 week --- sys/dev/ahci/ahci_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sys/dev/ahci/ahci_pci.c b/sys/dev/ahci/ahci_pci.c index 6f87efb6bb9c..1ff0d5a873a1 100644 --- a/sys/dev/ahci/ahci_pci.c +++ b/sys/dev/ahci/ahci_pci.c @@ -180,6 +180,7 @@ static const struct { {0x1f3e8086, 0x00, "Intel Avoton (RAID)", 0}, {0x1f3f8086, 0x00, "Intel Avoton (RAID)", 0}, {0x23a38086, 0x00, "Intel Coleto Creek", 0}, + {0x5ae38086, 0x00, "Intel Apollo Lake", 0}, {0x8c028086, 0x00, "Intel Lynx Point", 0}, {0x8c038086, 0x00, "Intel Lynx Point", 0}, {0x8c048086, 0x00, "Intel Lynx Point (RAID)", 0}, From 7013797e34b0fe507476f7aa20e24e89b75080d4 Mon Sep 17 00:00:00 2001 From: Mark Johnston Date: Thu, 6 Aug 2020 15:42:59 +0000 Subject: [PATCH 134/141] Remove the vfs.reassignbufcalls counter and sysctl. As the 20-year old comment above it suggests, the counter is of dubious value. Moreover, the (global) counter was not updated precisely and hurts scalability. Reviewed by: cem, kib, mjg MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D25965 --- sys/kern/vfs_subr.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/sys/kern/vfs_subr.c b/sys/kern/vfs_subr.c index 8b1e6553452f..233dc86321f9 100644 --- a/sys/kern/vfs_subr.c +++ b/sys/kern/vfs_subr.c @@ -206,15 +206,6 @@ static counter_u64_t recycles_free_count; SYSCTL_COUNTER_U64(_vfs, OID_AUTO, recycles_free, CTLFLAG_RD, &recycles_free_count, "Number of free vnodes recycled to meet vnode cache targets"); -/* - * Various variables used for debugging the new implementation of - * reassignbuf(). - * XXX these are probably of (very) limited utility now. - */ -static int reassignbufcalls; -SYSCTL_INT(_vfs, OID_AUTO, reassignbufcalls, CTLFLAG_RW | CTLFLAG_STATS, - &reassignbufcalls, 0, "Number of calls to reassignbuf"); - static counter_u64_t deferred_inact; SYSCTL_COUNTER_U64(_vfs, OID_AUTO, deferred_inact, CTLFLAG_RD, &deferred_inact, "Number of times inactive processing was deferred"); @@ -2732,7 +2723,6 @@ reassignbuf(struct buf *bp) vp = bp->b_vp; bo = bp->b_bufobj; - ++reassignbufcalls; CTR3(KTR_BUF, "reassignbuf(%p) vp %p flags %X", bp, bp->b_vp, bp->b_flags); From 0ffec1b03dc2b2dd048c4eeecedf75a028acb3c9 Mon Sep 17 00:00:00 2001 From: Mark Johnston Date: Thu, 6 Aug 2020 15:43:15 +0000 Subject: [PATCH 135/141] Clean up reassignbuf() and buf_vlist_remove() a bit. - Convert panic() calls to INVARIANTS-only assertions. The PCTRIE code provides some of the same protection since it will panic upon an attempt to remove a non-resident buffer. - Update the comment above reassignbuf() to reflect reality. Reviewed by: cem, kib, mjg MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D25965 --- sys/kern/vfs_subr.c | 39 +++++++++++++++------------------------ 1 file changed, 15 insertions(+), 24 deletions(-) diff --git a/sys/kern/vfs_subr.c b/sys/kern/vfs_subr.c index 233dc86321f9..5c25ab86cf9d 100644 --- a/sys/kern/vfs_subr.c +++ b/sys/kern/vfs_subr.c @@ -2256,13 +2256,17 @@ static void buf_vlist_remove(struct buf *bp) { struct bufv *bv; + b_xflags_t flags; + + flags = bp->b_xflags; KASSERT(bp->b_bufobj != NULL, ("No b_bufobj %p", bp)); ASSERT_BO_WLOCKED(bp->b_bufobj); - KASSERT((bp->b_xflags & (BX_VNDIRTY|BX_VNCLEAN)) != - (BX_VNDIRTY|BX_VNCLEAN), - ("buf_vlist_remove: Buf %p is on two lists", bp)); - if (bp->b_xflags & BX_VNDIRTY) + KASSERT((flags & (BX_VNDIRTY | BX_VNCLEAN)) != 0 && + (flags & (BX_VNDIRTY | BX_VNCLEAN)) != (BX_VNDIRTY | BX_VNCLEAN), + ("%s: buffer %p has invalid queue state", __func__, bp)); + + if ((flags & BX_VNDIRTY) != 0) bv = &bp->b_bufobj->bo_dirty; else bv = &bp->b_bufobj->bo_clean; @@ -2391,10 +2395,7 @@ brelvp(struct buf *bp) vp = bp->b_vp; /* XXX */ bo = bp->b_bufobj; BO_LOCK(bo); - if (bp->b_xflags & (BX_VNDIRTY | BX_VNCLEAN)) - buf_vlist_remove(bp); - else - panic("brelvp: Buffer %p not on queue.", bp); + buf_vlist_remove(bp); if ((bo->bo_flag & BO_ONWORKLST) && bo->bo_dirty.bv_cnt == 0) { bo->bo_flag &= ~BO_ONWORKLST; mtx_lock(&sync_mtx); @@ -2707,9 +2708,7 @@ syncer_resume(void) } /* - * Reassign a buffer from one vnode to another. - * Used to assign file specific control information - * (indirect blocks) to the vnode to which they belong. + * Move the buffer between the clean and dirty lists of its vnode. */ void reassignbuf(struct buf *bp) @@ -2724,23 +2723,15 @@ reassignbuf(struct buf *bp) vp = bp->b_vp; bo = bp->b_bufobj; + KASSERT((bp->b_flags & B_PAGING) == 0, + ("%s: cannot reassign paging buffer %p", __func__, bp)); + CTR3(KTR_BUF, "reassignbuf(%p) vp %p flags %X", bp, bp->b_vp, bp->b_flags); - /* - * B_PAGING flagged buffers cannot be reassigned because their vp - * is not fully linked in. - */ - if (bp->b_flags & B_PAGING) - panic("cannot reassign paging buffer"); - /* - * Delete from old vnode list, if on one. - */ BO_LOCK(bo); - if (bp->b_xflags & (BX_VNDIRTY | BX_VNCLEAN)) - buf_vlist_remove(bp); - else - panic("reassignbuf: Buffer %p not on queue.", bp); + buf_vlist_remove(bp); + /* * If dirty, put on list of dirty buffers; otherwise insert onto list * of clean buffers. From 1931aa942f90a34dbb4518f9f97f0a17ab880735 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Thu, 6 Aug 2020 16:11:30 +0000 Subject: [PATCH 136/141] pkgbase: Remove vcs revision from kernel and runtime comment This is not needed and we don't do that for other packages. --- release/packages/kernel.ucl | 2 +- release/packages/runtime.ucl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/release/packages/kernel.ucl b/release/packages/kernel.ucl index f9ee3643e1d1..d7684a6d889d 100644 --- a/release/packages/kernel.ucl +++ b/release/packages/kernel.ucl @@ -5,7 +5,7 @@ name = "FreeBSD-%PKGNAME%" origin = "base" version = "%VERSION%" -comment = "%COMMENT% %VCS_REVISION%" +comment = "%COMMENT%" categories = [ base ] maintainer = "re@FreeBSD.org" www = "https://www.FreeBSD.org" diff --git a/release/packages/runtime.ucl b/release/packages/runtime.ucl index 1d6f6c3ded29..b17971acb2eb 100644 --- a/release/packages/runtime.ucl +++ b/release/packages/runtime.ucl @@ -5,7 +5,7 @@ name = "FreeBSD-%PKGNAME%" origin = "base" version = "%VERSION%" -comment = "%COMMENT% %VCS_REVISION%" +comment = "%COMMENT%" categories = [ base ] maintainer = "re@FreeBSD.org" www = "https://www.FreeBSD.org" From d0327929abfbf1d42ab522d969d23ebb9845d179 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Thu, 6 Aug 2020 16:13:54 +0000 Subject: [PATCH 137/141] pkgbase: Add a new variable PKG_TIMESTAMP libarchive uses the SOURCE_DATE_EPOCH env variable to set the date of file in an archive, this is useful for reproducibility. Add a variable name PKG_TIMESTAMP that take a epoch time and set SOURCE_DATE_EPOCH to this. By default it is the current time so no changes here. --- Makefile.inc1 | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Makefile.inc1 b/Makefile.inc1 index 94fd5ef5c515..e0992e2acb4f 100644 --- a/Makefile.inc1 +++ b/Makefile.inc1 @@ -545,6 +545,13 @@ PKG_VERSION= ${_REVISION}${EXTRA_REVISION} .endif .endif # !defined(PKG_VERSION) +.if !defined(PKG_TIMESTAMP) +TIMEEPOCHNOW= %s +SOURCE_DATE_EPOCH= ${TIMEEPOCHNOW:gmtime} +.else +SOURCE_DATE_EPOCH= ${PKG_TIMESTAMP} +.endif + .if !defined(_MKSHOWCONFIG) _CPUTYPE!= MAKEFLAGS= CPUTYPE=${_TARGET_CPUTYPE} ${MAKE} -f /dev/null \ -m ${.CURDIR}/share/mk MK_AUTO_OBJ=no -V CPUTYPE @@ -1831,6 +1838,7 @@ create-packages-kernel: _pkgbootstrap _repodir .PHONY ${MAKE} -f Makefile.inc1 \ DESTDIR=${KSTAGEDIR} \ PKG_VERSION=${PKG_VERSION} DISTDIR=kernel \ + SOURCE_DATE_EPOCH=${SOURCE_DATE_EPOCH} \ create-kernel-packages create-packages: .PHONY create-packages-world create-packages-kernel @@ -1847,6 +1855,7 @@ create-world-packages: _pkgbootstrap .PHONY done > ${WSTAGEDIR}/packages.mk ${_+_}@cd ${.CURDIR}; \ ${MAKE} -f Makefile.inc1 create-world-packages-jobs \ + SOURCE_DATE_EPOCH=${SOURCE_DATE_EPOCH} \ .MAKE.JOB.PREFIX= .if make(create-world-packages-jobs) From 70fc0cc3874ff24f0c3fb4c0b0f505fb7dbb6723 Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Thu, 6 Aug 2020 16:14:43 +0000 Subject: [PATCH 138/141] pkgbase: Add the possibility to choose the output dir The output dir is set to ${REPODIR}/${PKG_ABI}/${PKG_VERSION} now. Add the possibility to specify the last componant and set it by default to ${PKG_VERSION} as before. This is useful for tests and also for building packages with the same PKG_VERSION provided to check differences. --- Makefile.inc1 | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/Makefile.inc1 b/Makefile.inc1 index e0992e2acb4f..9dc0be374a81 100644 --- a/Makefile.inc1 +++ b/Makefile.inc1 @@ -1789,6 +1789,7 @@ KSTAGEDIR?= ${OBJTOP}/kernelstage REPODIR?= ${OBJROOT}repo PKG_FORMAT?= txz PKGSIGNKEY?= # empty +PKG_OUTPUT_DIR?= ${PKG_VERSION} .ORDER: stage-packages create-packages .ORDER: create-packages create-world-packages @@ -1883,7 +1884,7 @@ create-world-package-${pkgname}: .PHONY create -f ${PKG_FORMAT} -M ${WSTAGEDIR}/${pkgname}.ucl \ -p ${WSTAGEDIR}/${pkgname}.plist \ -r ${WSTAGEDIR} \ - -o ${REPODIR}/${PKG_ABI}/${PKG_VERSION} + -o ${REPODIR}/${PKG_ABI}/${PKG_OUTPUT_DIR} .endfor _default_flavor= -default @@ -1916,7 +1917,7 @@ create-kernel-packages-flavor${flavor:C,^""$,${_default_flavor},}: _pkgbootstrap -M ${KSTAGEDIR}/${DISTDIR}/kernel.${INSTALLKERNEL}${flavor}.ucl \ -p ${KSTAGEDIR}/${DISTDIR}/kernel.${INSTALLKERNEL}${flavor}.plist \ -r ${KSTAGEDIR}/${DISTDIR} \ - -o ${REPODIR}/${PKG_ABI}/${PKG_VERSION} + -o ${REPODIR}/${PKG_ABI}/${PKG_OUTPUT_DIR} . endfor .endif .if ${BUILDKERNELS:[#]} > 1 && ${NO_INSTALLEXTRAKERNELS} != "yes" @@ -1949,7 +1950,7 @@ create-kernel-packages-extra-flavor${flavor:C,^""$,${_default_flavor},}-${_kerne -M ${KSTAGEDIR}/kernel.${_kernel}/kernel.${_kernel}${flavor}.ucl \ -p ${KSTAGEDIR}/kernel.${_kernel}/kernel.${_kernel}${flavor}.plist \ -r ${KSTAGEDIR}/kernel.${_kernel} \ - -o ${REPODIR}/${PKG_ABI}/${PKG_VERSION} + -o ${REPODIR}/${PKG_ABI}/${PKG_OUTPUT_DIR} . endfor . endif . endfor @@ -1965,7 +1966,7 @@ sign-packages: _pkgbootstrap .PHONY ${REPODIR}/$$(${PKG_CMD} -o ABI_FILE=${WSTAGEDIR}/usr/bin/uname config ABI)/${PKG_VERSION} \ ${PKGSIGNKEY} ; \ cd ${REPODIR}/$$(${PKG_CMD} -o ABI_FILE=${WSTAGEDIR}/usr/bin/uname config ABI); \ - ln -s ${PKG_VERSION} latest + ln -s ${PKG_OUTPUT_DIR} latest # # From 9f9cc3f989bbdf66323a4df2fee08473ea8d9071 Mon Sep 17 00:00:00 2001 From: Brooks Davis Date: Thu, 6 Aug 2020 16:20:20 +0000 Subject: [PATCH 139/141] Preserve ASLR vm_map flags across fork In the most common case (fork+execve) this doesn't matter, but further attempts to apply entropy would fail in (e.g.) a pre-fork server. Reported by: Alfredo Mazzinghi Reviewed by: kib, markj Obtained from: CheriBSD MFC after: 3 days Differential Revision: https://reviews.freebsd.org/D25966 --- sys/vm/vm_map.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sys/vm/vm_map.c b/sys/vm/vm_map.c index 998a34222e94..0d334e38d31d 100644 --- a/sys/vm/vm_map.c +++ b/sys/vm/vm_map.c @@ -4109,6 +4109,7 @@ vmspace_fork(struct vmspace *vm1, vm_ooffset_t *fork_charge) } new_map->anon_loc = old_map->anon_loc; + new_map->flags |= old_map->flags & (MAP_ASLR | MAP_ASLR_IGNSTART); VM_MAP_ENTRY_FOREACH(old_entry, old_map) { if ((old_entry->eflags & MAP_ENTRY_IS_SUB_MAP) != 0) From e039e3d1d2075c7f5ad596e6c7a3453775b691d0 Mon Sep 17 00:00:00 2001 From: Brandon Bergren Date: Thu, 6 Aug 2020 17:49:19 +0000 Subject: [PATCH 140/141] [POWERPC] Fix ppc64 makecontext() parameter overflow handling. On ELFv2, the overflow parameters in the stack frame are at a different offset from sp than ELFv1. Adjust code to use the correct offset in all cases. This had resulted in argv[8] and up being copied to the incorrect address in the new context's initial stack frame. This is not necessarily the only bug in this function, I need to do a full review still and ensure the rest of the math is sane for ELFv2 stack frames. Reported by: pherde (Probably. My notes are a bit unclear.) Reviewed by: jhibbits (in irc) Sponsored by: Tag1 Consulting, Inc. --- lib/libc/powerpc64/gen/makecontext.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/libc/powerpc64/gen/makecontext.c b/lib/libc/powerpc64/gen/makecontext.c index c21e9140d38f..7663b6f82e7d 100644 --- a/lib/libc/powerpc64/gen/makecontext.c +++ b/lib/libc/powerpc64/gen/makecontext.c @@ -102,7 +102,11 @@ __makecontext(ucontext_t *ucp, void (*start)(void), int argc, ...) uint64_t *argp; /* Skip past frame pointer and saved LR */ +#if !defined(_CALL_ELF) || _CALL_ELF == 1 argp = (uint64_t *)sp + 6; +#else + argp = (uint64_t *)sp + 4; +#endif for (i = 0; i < stackargs; i++) *argp++ = va_arg(ap, uint64_t); From 8bdf81e4d14d9b31cd0a7931de59510c3a6761c2 Mon Sep 17 00:00:00 2001 From: Alexander Motin Date: Thu, 6 Aug 2020 19:16:11 +0000 Subject: [PATCH 141/141] Add CTL support for REPORT IDENTIFYING INFORMATION command. It allows to report to initiator LU identifying information, preset via "ident_info" and "text_ident_info" options. Unfortunately it is impossible to implement SET IDENTIFYING INFORMATION, since we have no persistent storage it requires, so the information is read-only for initiator and has to be set out-of-band. MFC after: 1 week Sponsored by: iXsystems, Inc. --- sys/cam/ctl/ctl.c | 82 +++++++++++++++++++++++++++++++++++++ sys/cam/ctl/ctl_cmd_table.c | 20 ++++++--- sys/cam/ctl/ctl_private.h | 1 + sys/cam/scsi/scsi_all.h | 26 ++++++++++++ usr.sbin/ctladm/ctladm.8 | 8 +++- 5 files changed, 130 insertions(+), 7 deletions(-) diff --git a/sys/cam/ctl/ctl.c b/sys/cam/ctl/ctl.c index 3c325a8242a8..0a09cc0b2c80 100644 --- a/sys/cam/ctl/ctl.c +++ b/sys/cam/ctl/ctl.c @@ -7129,6 +7129,88 @@ ctl_read_defect(struct ctl_scsiio *ctsio) return (CTL_RETVAL_COMPLETE); } +int +ctl_report_ident_info(struct ctl_scsiio *ctsio) +{ + struct ctl_lun *lun = CTL_LUN(ctsio); + struct scsi_report_ident_info *cdb; + struct scsi_report_ident_info_data *rii_ptr; + struct scsi_report_ident_info_descr *riid_ptr; + const char *oii, *otii; + int retval, alloc_len, total_len = 0, len = 0; + + CTL_DEBUG_PRINT(("ctl_report_ident_info\n")); + + cdb = (struct scsi_report_ident_info *)ctsio->cdb; + retval = CTL_RETVAL_COMPLETE; + + total_len = sizeof(struct scsi_report_ident_info_data); + switch (cdb->type) { + case RII_LUII: + oii = dnvlist_get_string(lun->be_lun->options, + "ident_info", NULL); + if (oii) + len = strlen(oii); /* Approximately */ + break; + case RII_LUTII: + otii = dnvlist_get_string(lun->be_lun->options, + "text_ident_info", NULL); + if (otii) + len = strlen(otii) + 1; /* NULL-terminated */ + break; + case RII_IIS: + len = 2 * sizeof(struct scsi_report_ident_info_descr); + break; + default: + ctl_set_invalid_field(/*ctsio*/ ctsio, + /*sks_valid*/ 1, + /*command*/ 1, + /*field*/ 11, + /*bit_valid*/ 1, + /*bit*/ 2); + ctl_done((union ctl_io *)ctsio); + return(retval); + } + total_len += len; + alloc_len = scsi_4btoul(cdb->length); + + ctsio->kern_data_ptr = malloc(total_len, M_CTL, M_WAITOK | M_ZERO); + ctsio->kern_sg_entries = 0; + ctsio->kern_rel_offset = 0; + ctsio->kern_data_len = min(total_len, alloc_len); + ctsio->kern_total_len = ctsio->kern_data_len; + + rii_ptr = (struct scsi_report_ident_info_data *)ctsio->kern_data_ptr; + switch (cdb->type) { + case RII_LUII: + if (oii) { + if (oii[0] == '0' && oii[1] == 'x') + len = hex2bin(oii, (uint8_t *)(rii_ptr + 1), len); + else + strncpy((uint8_t *)(rii_ptr + 1), oii, len); + } + break; + case RII_LUTII: + if (otii) + strlcpy((uint8_t *)(rii_ptr + 1), otii, len); + break; + case RII_IIS: + riid_ptr = (struct scsi_report_ident_info_descr *)(rii_ptr + 1); + riid_ptr->type = RII_LUII; + scsi_ulto2b(0xffff, riid_ptr->length); + riid_ptr++; + riid_ptr->type = RII_LUTII; + scsi_ulto2b(0xffff, riid_ptr->length); + } + scsi_ulto2b(len, rii_ptr->length); + + ctl_set_success(ctsio); + ctsio->io_hdr.flags |= CTL_FLAG_ALLOCATED; + ctsio->be_move_done = ctl_config_move_done; + ctl_datamove((union ctl_io *)ctsio); + return(retval); +} + int ctl_report_tagret_port_groups(struct ctl_scsiio *ctsio) { diff --git a/sys/cam/ctl/ctl_cmd_table.c b/sys/cam/ctl/ctl_cmd_table.c index ffe02824975b..b3780dcf8c67 100644 --- a/sys/cam/ctl/ctl_cmd_table.c +++ b/sys/cam/ctl/ctl_cmd_table.c @@ -829,8 +829,15 @@ const struct ctl_cmd_entry ctl_cmd_table_a3[32] = /* 04 */ {NULL, CTL_SERIDX_INVLD, CTL_CMD_FLAG_NONE, CTL_LUN_PAT_NONE}, -/* 05 */ -{NULL, CTL_SERIDX_INVLD, CTL_CMD_FLAG_NONE, CTL_LUN_PAT_NONE}, +/* 05 REPORT IDENTIFYING INFORMATION */ +{ctl_report_ident_info, CTL_SERIDX_INQ, CTL_CMD_FLAG_OK_ON_BOTH | + CTL_CMD_FLAG_OK_ON_NO_MEDIA | + CTL_CMD_FLAG_OK_ON_STANDBY | + CTL_CMD_FLAG_OK_ON_UNAVAIL | + CTL_FLAG_DATA_IN | + CTL_CMD_FLAG_ALLOW_ON_PR_RESV, + CTL_LUN_PAT_NONE, + 12, {0x0f, 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x07}}, /* 06 */ {NULL, CTL_SERIDX_INVLD, CTL_CMD_FLAG_NONE, CTL_LUN_PAT_NONE}, @@ -854,7 +861,7 @@ const struct ctl_cmd_entry ctl_cmd_table_a3[32] = CTL_LUN_PAT_NONE, 12, {0xea, 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff, 0, 0x07}}, -/* 0B */ +/* 0B REPORT ALIASES */ {NULL, CTL_SERIDX_INVLD, CTL_CMD_FLAG_NONE, CTL_LUN_PAT_NONE}, /* 0C REPORT SUPPORTED_OPCODES */ @@ -877,7 +884,7 @@ const struct ctl_cmd_entry ctl_cmd_table_a3[32] = CTL_LUN_PAT_NONE, 12, {0x0d, 0x80, 0, 0, 0, 0xff, 0xff, 0xff, 0xff, 0, 0x07}}, -/* 0E */ +/* 0E REPORT PRIORITY */ {NULL, CTL_SERIDX_INVLD, CTL_CMD_FLAG_NONE, CTL_LUN_PAT_NONE}, /* 0F REPORT TIMESTAMP */ @@ -890,7 +897,10 @@ const struct ctl_cmd_entry ctl_cmd_table_a3[32] = CTL_LUN_PAT_NONE, 12, {0x0f, 0, 0, 0, 0, 0xff, 0xff, 0xff, 0xff, 0, 0x07}}, -/* 10-1f */ +/* 10 MANAGEMENT PROTOCOL IN */ +{NULL, CTL_SERIDX_INVLD, CTL_CMD_FLAG_NONE, CTL_LUN_PAT_NONE}, + +/* 11-1f */ }; const struct ctl_cmd_entry ctl_cmd_table[256] = diff --git a/sys/cam/ctl/ctl_private.h b/sys/cam/ctl/ctl_private.h index 5dd82d3032ac..cf67deb13ef7 100644 --- a/sys/cam/ctl/ctl_private.h +++ b/sys/cam/ctl/ctl_private.h @@ -517,6 +517,7 @@ int ctl_get_event_status(struct ctl_scsiio *ctsio); int ctl_mechanism_status(struct ctl_scsiio *ctsio); int ctl_persistent_reserve_in(struct ctl_scsiio *ctsio); int ctl_persistent_reserve_out(struct ctl_scsiio *ctsio); +int ctl_report_ident_info(struct ctl_scsiio *ctsio); int ctl_report_tagret_port_groups(struct ctl_scsiio *ctsio); int ctl_report_supported_opcodes(struct ctl_scsiio *ctsio); int ctl_report_supported_tmf(struct ctl_scsiio *ctsio); diff --git a/sys/cam/scsi/scsi_all.h b/sys/cam/scsi/scsi_all.h index c95ff1e12928..b9ee683f5990 100644 --- a/sys/cam/scsi/scsi_all.h +++ b/sys/cam/scsi/scsi_all.h @@ -1484,6 +1484,32 @@ struct scsi_maintenance_in uint8_t control; }; +struct scsi_report_ident_info +{ + uint8_t opcode; + uint8_t service_action; + uint8_t reserved[4]; + uint8_t length[4]; + uint8_t type; +#define RII_LUII 0x00 +#define RII_LUTII 0x04 +#define RII_IIS 0xfc + uint8_t control; +}; + +struct scsi_report_ident_info_data +{ + uint8_t reserved[2]; + uint8_t length[2]; +}; + +struct scsi_report_ident_info_descr +{ + uint8_t type; + uint8_t reserved; + uint8_t length[2]; +}; + struct scsi_report_supported_opcodes { uint8_t opcode; diff --git a/usr.sbin/ctladm/ctladm.8 b/usr.sbin/ctladm/ctladm.8 index d120fa8cf03b..7bb353c60522 100644 --- a/usr.sbin/ctladm/ctladm.8 +++ b/usr.sbin/ctladm/ctladm.8 @@ -1,6 +1,6 @@ .\" .\" Copyright (c) 2003 Silicon Graphics International Corp. -.\" Copyright (c) 2015 Alexander Motin +.\" Copyright (c) 2015-2020 Alexander Motin .\" Copyright (c) 2018 Marcelo Araujo .\" All rights reserved. .\" @@ -36,7 +36,7 @@ .\" $Id: //depot/users/kenm/FreeBSD-test2/usr.sbin/ctladm/ctladm.8#3 $ .\" $FreeBSD$ .\" -.Dd July 25, 2019 +.Dd August 6, 2020 .Dt CTLADM 8 .Os .Sh NAME @@ -877,6 +877,10 @@ EUI, NAA or UUID identifier should be set to UNIQUE value to allow EXTENDED COPY command access the LUN. Non-unique LUN identifiers may lead to data corruption. Some initiators may not support later introduced UUID identifiers. +.It Va ident_info +Specified LUN identification information (string or 0x + hex). +.It Va text_ident_info +Specified LUN text identification information (UTF-8 string). .It Va ha_role Setting to "primary" or "secondary" overrides default role of the node in HA cluster, set by kern.cam.ctl.ha_role sysctl.