Prepare DB# handler for deferred trigger of watchpoints.
Since pop %ss/mov %ss instructions defer all interrupts and exceptions for the next instruction, it is possible that the userspace watchpoint trap executes on the first instruction of the kernel entry for syscall/bpt. In this case, DB# should be treated similarly to NMI: on amd64 we must always load GSBASE even if the trap comes from kernel mode, and load the kernel page table root into %cr3. Moreover, the trap must use the dedicated stack, because we are still on the user stack when trapped on syscall entry. For i386, we must reload %cr3. The syscall instruction is not configured, so there is no issue with executing on user stack when trapping. Due to some CPU erratas it is not always possible to detect that the userspace watchpoint triggered by inspecting %dr6. In trap(), compare the trap %rip with the known unsafe entry points and if matched pretend that the watchpoint did not fire at all. Thank you to the MSRC Incident Response Team, and in particular Greg Lenti and Nate Warfield, for coordinating the response to this issue across multiple vendors. Thanks to Computer Recycling at The Working Center of Kitchener for making hardware available to allow us to test the patch on additional CPU families. Reviewed by: jhb Discussed with: Matthew Dillon Tested by: emaste Sponsored by: The FreeBSD Foundation Security: CVE-2018-8897 Security: FreeBSD-SA-18:06.debugreg
This commit is contained in:
kib
parent
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commit
e393d204ee
@ -115,7 +115,6 @@ X\l: subq $TF_RIP,%rsp
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jmp alltraps_noen
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.endm
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TRAP_NOEN dbg, T_TRCTRAP
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TRAP_NOEN bpt, T_BPTFLT
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#ifdef KDTRACE_HOOKS
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TRAP_NOEN dtrace_ret, T_DTRACE_RET
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@ -537,6 +536,121 @@ fast_syscall_common:
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IDTVEC(fast_syscall32)
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sysret
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/*
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* DB# handler is very similar to NM#, because 'mov/pop %ss' delay
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* generation of exception until the next instruction is executed,
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* which might be a kernel entry. So we must execute the handler
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* on IST stack and be ready for non-kernel GSBASE.
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*/
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IDTVEC(dbg)
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subq $TF_RIP,%rsp
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movl $(T_TRCTRAP),TF_TRAPNO(%rsp)
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movq $0,TF_ADDR(%rsp)
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movq $0,TF_ERR(%rsp)
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movq %rdi,TF_RDI(%rsp)
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movq %rsi,TF_RSI(%rsp)
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movq %rdx,TF_RDX(%rsp)
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movq %rcx,TF_RCX(%rsp)
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movq %r8,TF_R8(%rsp)
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movq %r9,TF_R9(%rsp)
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movq %rax,TF_RAX(%rsp)
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movq %rbx,TF_RBX(%rsp)
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movq %rbp,TF_RBP(%rsp)
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movq %r10,TF_R10(%rsp)
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movq %r11,TF_R11(%rsp)
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movq %r12,TF_R12(%rsp)
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movq %r13,TF_R13(%rsp)
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movq %r14,TF_R14(%rsp)
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movq %r15,TF_R15(%rsp)
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SAVE_SEGS
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movl $TF_HASSEGS,TF_FLAGS(%rsp)
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cld
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testb $SEL_RPL_MASK,TF_CS(%rsp)
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jnz dbg_fromuserspace
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/*
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* We've interrupted the kernel. Preserve GS.base in %r12,
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* %cr3 in %r13, and possibly lower half of MSR_IA32_SPEC_CTL in %r14d.
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*/
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movl $MSR_GSBASE,%ecx
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rdmsr
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movq %rax,%r12
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shlq $32,%rdx
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orq %rdx,%r12
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/* Retrieve and load the canonical value for GS.base. */
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movq TF_SIZE(%rsp),%rdx
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movl %edx,%eax
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shrq $32,%rdx
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wrmsr
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movq %cr3,%r13
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movq PCPU(KCR3),%rax
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cmpq $~0,%rax
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je 1f
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movq %rax,%cr3
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1: testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
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je 2f
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movl $MSR_IA32_SPEC_CTRL,%ecx
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rdmsr
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movl %eax,%r14d
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call handle_ibrs_entry
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2: FAKE_MCOUNT(TF_RIP(%rsp))
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movq %rsp,%rdi
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call trap
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MEXITCOUNT
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testl $CPUID_STDEXT3_IBPB,cpu_stdext_feature3(%rip)
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je 3f
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movl %r14d,%eax
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xorl %edx,%edx
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movl $MSR_IA32_SPEC_CTRL,%ecx
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wrmsr
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/*
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* Put back the preserved MSR_GSBASE value.
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*/
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3: movl $MSR_GSBASE,%ecx
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movq %r12,%rdx
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movl %edx,%eax
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shrq $32,%rdx
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wrmsr
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movq %r13,%cr3
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RESTORE_REGS
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addq $TF_RIP,%rsp
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jmp doreti_iret
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dbg_fromuserspace:
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/*
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* Switch to kernel GSBASE and kernel page table, and copy frame
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* from the IST stack to the normal kernel stack, since trap()
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* re-enables interrupts, and since we might trap on DB# while
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* in trap().
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*/
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swapgs
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movq PCPU(KCR3),%rax
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cmpq $~0,%rax
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je 1f
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movq %rax,%cr3
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1: movq PCPU(RSP0),%rax
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movl $TF_SIZE,%ecx
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subq %rcx,%rax
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movq %rax,%rdi
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movq %rsp,%rsi
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rep;movsb
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movq %rax,%rsp
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call handle_ibrs_entry
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movq PCPU(CURPCB),%rdi
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orl $PCB_FULL_IRET,PCB_FLAGS(%rdi)
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testb $CPUID_STDEXT_FSGSBASE,cpu_stdext_feature(%rip)
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jz 3f
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cmpw $KUF32SEL,TF_FS(%rsp)
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jne 2f
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rdfsbase %rax
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movq %rax,PCB_FSBASE(%rdi)
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2: cmpw $KUG32SEL,TF_GS(%rsp)
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jne 3f
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movl $MSR_KGSBASE,%ecx
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rdmsr
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shlq $32,%rdx
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orq %rdx,%rax
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movq %rax,PCB_GSBASE(%rdi)
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3: jmp calltrap
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/*
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* NMI handling is special.
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*
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@ -669,6 +669,7 @@ struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
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static char dblfault_stack[PAGE_SIZE] __aligned(16);
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static char mce0_stack[PAGE_SIZE] __aligned(16);
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static char nmi0_stack[PAGE_SIZE] __aligned(16);
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static char dbg0_stack[PAGE_SIZE] __aligned(16);
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CTASSERT(sizeof(struct nmi_pcpu) == 16);
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struct amd64tss common_tss[MAXCPU];
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@ -821,7 +822,7 @@ extern inthand_t
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IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
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IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
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IDTVEC(xmm), IDTVEC(dblfault),
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IDTVEC(div_pti), IDTVEC(dbg_pti), IDTVEC(bpt_pti),
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IDTVEC(div_pti), IDTVEC(bpt_pti),
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IDTVEC(ofl_pti), IDTVEC(bnd_pti), IDTVEC(ill_pti), IDTVEC(dna_pti),
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IDTVEC(fpusegm_pti), IDTVEC(tss_pti), IDTVEC(missing_pti),
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IDTVEC(stk_pti), IDTVEC(prot_pti), IDTVEC(page_pti),
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@ -1632,8 +1633,7 @@ hammer_time(u_int64_t modulep, u_int64_t physfree)
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SEL_KPL, 0);
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setidt(IDT_DE, pti ? &IDTVEC(div_pti) : &IDTVEC(div), SDT_SYSIGT,
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SEL_KPL, 0);
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setidt(IDT_DB, pti ? &IDTVEC(dbg_pti) : &IDTVEC(dbg), SDT_SYSIGT,
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SEL_KPL, 0);
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setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 4);
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setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2);
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setidt(IDT_BP, pti ? &IDTVEC(bpt_pti) : &IDTVEC(bpt), SDT_SYSIGT,
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SEL_UPL, 0);
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@ -1715,6 +1715,13 @@ hammer_time(u_int64_t modulep, u_int64_t physfree)
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np = ((struct nmi_pcpu *) &mce0_stack[sizeof(mce0_stack)]) - 1;
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np->np_pcpu = (register_t) pc;
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common_tss[0].tss_ist3 = (long) np;
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/*
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* DB# stack, runs on ist4.
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*/
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np = ((struct nmi_pcpu *) &dbg0_stack[sizeof(dbg0_stack)]) - 1;
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np->np_pcpu = (register_t) pc;
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common_tss[0].tss_ist4 = (long) np;
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/* Set the IO permission bitmap (empty due to tss seg limit) */
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common_tss[0].tss_iobase = sizeof(struct amd64tss) + IOPERM_BITMAP_SIZE;
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@ -91,6 +91,7 @@ extern struct pcpu __pcpu[];
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char *doublefault_stack;
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char *mce_stack;
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char *nmi_stack;
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char *dbg_stack;
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/*
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* Local data and functions.
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@ -251,6 +252,10 @@ init_secondary(void)
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np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
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common_tss[cpu].tss_ist3 = (long) np;
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/* The DB# stack runs on IST4. */
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np = ((struct nmi_pcpu *) &dbg_stack[PAGE_SIZE]) - 1;
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common_tss[cpu].tss_ist4 = (long) np;
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/* Prepare private GDT */
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gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
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for (x = 0; x < NGDT; x++) {
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@ -297,6 +302,10 @@ init_secondary(void)
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np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
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np->np_pcpu = (register_t) pc;
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/* Save the per-cpu pointer for use by the DB# handler. */
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np = ((struct nmi_pcpu *) &dbg_stack[PAGE_SIZE]) - 1;
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np->np_pcpu = (register_t) pc;
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wrmsr(MSR_FSBASE, 0); /* User value */
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wrmsr(MSR_GSBASE, (u_int64_t)pc);
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wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
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@ -392,6 +401,8 @@ native_start_all_aps(void)
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M_WAITOK | M_ZERO);
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nmi_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
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M_WAITOK | M_ZERO);
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dbg_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
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M_WAITOK | M_ZERO);
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dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
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M_WAITOK | M_ZERO);
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@ -7843,6 +7843,9 @@ pmap_pti_init(void)
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/* MC# stack IST 3 */
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va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
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pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
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/* DB# stack IST 4 */
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va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
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pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
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}
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pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
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(vm_offset_t)etext, true);
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@ -47,6 +47,7 @@ __FBSDID("$FreeBSD$");
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*/
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#include "opt_clock.h"
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#include "opt_compat.h"
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#include "opt_cpu.h"
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#include "opt_hwpmc_hooks.h"
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#include "opt_isa.h"
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@ -102,6 +103,10 @@ PMC_SOFT_DEFINE( , , page_fault, write);
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#include <sys/dtrace_bsd.h>
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#endif
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extern inthand_t IDTVEC(bpt), IDTVEC(bpt_pti), IDTVEC(dbg),
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IDTVEC(fast_syscall), IDTVEC(fast_syscall_pti), IDTVEC(fast_syscall32),
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IDTVEC(int0x80_syscall_pti), IDTVEC(int0x80_syscall);
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void __noinline trap(struct trapframe *frame);
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void trap_check(struct trapframe *frame);
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void dblfault_handler(struct trapframe *frame);
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@ -535,6 +540,52 @@ trap(struct trapframe *frame)
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load_dr6(rdr6() & ~0xf);
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return;
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}
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/*
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* Malicious user code can configure a debug
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* register watchpoint to trap on data access
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* to the top of stack and then execute 'pop
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* %ss; int 3'. Due to exception deferral for
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* 'pop %ss', the CPU will not interrupt 'int
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* 3' to raise the DB# exception for the debug
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* register but will postpone the DB# until
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* execution of the first instruction of the
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* BP# handler (in kernel mode). Normally the
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* previous check would ignore DB# exceptions
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* for watchpoints on user addresses raised in
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* kernel mode. However, some CPU errata
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* include cases where DB# exceptions do not
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* properly set bits in %dr6, e.g. Haswell
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* HSD23 and Skylake-X SKZ24.
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*
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* A deferred DB# can also be raised on the
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* first instructions of system call entry
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* points or single-step traps via similar use
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* of 'pop %ss' or 'mov xxx, %ss'.
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*/
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if (pti) {
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if (frame->tf_rip ==
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(uintptr_t)IDTVEC(fast_syscall_pti) ||
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#ifdef COMPAT_FREEBSD32
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frame->tf_rip ==
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(uintptr_t)IDTVEC(int0x80_syscall_pti) ||
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#endif
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frame->tf_rip == (uintptr_t)IDTVEC(bpt_pti))
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return;
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} else {
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if (frame->tf_rip ==
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(uintptr_t)IDTVEC(fast_syscall) ||
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#ifdef COMPAT_FREEBSD32
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frame->tf_rip ==
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(uintptr_t)IDTVEC(int0x80_syscall) ||
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#endif
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frame->tf_rip == (uintptr_t)IDTVEC(bpt))
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return;
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}
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if (frame->tf_rip == (uintptr_t)IDTVEC(dbg) ||
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/* Needed for AMD. */
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frame->tf_rip == (uintptr_t)IDTVEC(fast_syscall32))
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return;
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/*
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* FALLTHROUGH (TRCTRAP kernel mode, kernel address)
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*/
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@ -103,8 +103,6 @@ MCOUNT_LABEL(btrap)
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IDTVEC(div)
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pushl $0; TRAP(T_DIVIDE)
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IDTVEC(dbg)
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pushl $0; TRAP(T_TRCTRAP)
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IDTVEC(bpt)
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pushl $0; TRAP(T_BPTFLT)
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IDTVEC(dtrace_ret)
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@ -287,6 +285,39 @@ norm_ill:
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jmp alltraps
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#endif
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/*
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* See comment in the handler for the kernel case T_TRCTRAP in trap.c.
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* The exception handler must be ready to execute with wrong %cr3.
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* We save original %cr3 in frame->tf_err, similarly to NMI and MCE
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* handlers.
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*/
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IDTVEC(dbg)
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pushl $0
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pushl $T_TRCTRAP
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PUSH_FRAME2
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SET_KERNEL_SREGS
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cld
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movl %cr3, %eax
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movl %eax, TF_ERR(%esp)
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call 1f
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1: popl %eax
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movl (tramp_idleptd - 1b)(%eax), %eax
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movl %eax, %cr3
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FAKE_MCOUNT(TF_EIP(%esp))
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testl $PSL_VM, TF_EFLAGS(%esp)
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jnz dbg_user
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testb $SEL_RPL_MASK,TF_CS(%esp)
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jz calltrap
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dbg_user:
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NMOVE_STACKS
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pushl %esp
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movl $trap,%eax
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call *%eax
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add $4, %esp
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movl $T_RESERVED, TF_TRAPNO(%esp)
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MEXITCOUNT
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jmp doreti
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IDTVEC(mchk)
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pushl $0
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pushl $T_MCHK
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@ -469,6 +500,8 @@ doreti_exit:
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je doreti_iret_nmi
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cmpl $T_MCHK, TF_TRAPNO(%esp)
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je doreti_iret_nmi
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cmpl $T_TRCTRAP, TF_TRAPNO(%esp)
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je doreti_iret_nmi
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testl $SEL_RPL_MASK, TF_CS(%esp)
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jz doreti_popl_fs
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movl %esp, %esi
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@ -118,6 +118,8 @@ static int trap_pfault(struct trapframe *, int, vm_offset_t);
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static void trap_fatal(struct trapframe *, vm_offset_t);
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void dblfault_handler(void);
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extern inthand_t IDTVEC(bpt), IDTVEC(dbg), IDTVEC(int0x80_syscall);
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#define MAX_TRAP_MSG 32
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struct trap_data {
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@ -662,6 +664,36 @@ kernel_trctrap:
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load_dr6(rdr6() & ~0xf);
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return;
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}
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/*
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* Malicious user code can configure a debug
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* register watchpoint to trap on data access
|
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* to the top of stack and then execute 'pop
|
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* %ss; int 3'. Due to exception deferral for
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* 'pop %ss', the CPU will not interrupt 'int
|
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* 3' to raise the DB# exception for the debug
|
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* register but will postpone the DB# until
|
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* execution of the first instruction of the
|
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* BP# handler (in kernel mode). Normally the
|
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* previous check would ignore DB# exceptions
|
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* for watchpoints on user addresses raised in
|
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* kernel mode. However, some CPU errata
|
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* include cases where DB# exceptions do not
|
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* properly set bits in %dr6, e.g. Haswell
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* HSD23 and Skylake-X SKZ24.
|
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*
|
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* A deferred DB# can also be raised on the
|
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* first instructions of system call entry
|
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* points or single-step traps via similar use
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* of 'pop %ss' or 'mov xxx, %ss'.
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*/
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if (frame->tf_eip ==
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(uintptr_t)IDTVEC(int0x80_syscall) + setidt_disp ||
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||||
frame->tf_eip == (uintptr_t)IDTVEC(bpt) +
|
||||
setidt_disp ||
|
||||
frame->tf_eip == (uintptr_t)IDTVEC(dbg) +
|
||||
setidt_disp)
|
||||
return;
|
||||
/*
|
||||
* FALLTHROUGH (TRCTRAP kernel mode, kernel address)
|
||||
*/
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user