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Cater for ich4 quirks.

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Reported by: Jacob Rhoden
Tested by: Jacob Rhoden, mp
This commit is contained in:
orion 2002-08-19 16:03:56 +00:00
parent c601d7b784
commit e3be6c4141
2 changed files with 29 additions and 9 deletions
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35
sys/dev/sound/pci/ich.c
View File

@ -42,6 +42,7 @@ SND_DECLARE_FILE("$FreeBSD$");
#define ICH_MAX_BUFSZ 65536
#define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */
#define ICH4ID 0x24c58086 /* ICH4 needs special handling too */
/* buffer descriptor */
struct ich_desc {
@ -565,8 +566,12 @@ ich_init(struct sc_info *sc)
DELAY(600000);
stat = ich_rd(sc, ICH_REG_GLOB_STA, 4);
if ((stat & ICH_GLOB_STA_PCR) == 0)
return ENXIO;
if ((stat & ICH_GLOB_STA_PCR) == 0) {
/* ICH4 may fail when busmastering is enabled. Continue */
if (pci_get_devid(sc->dev) != ICH4ID) {
return ENXIO;
}
}
ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4);
@ -611,8 +616,8 @@ ich_pci_probe(device_t dev)
device_set_desc(dev, "Intel 82801CA (ICH3)");
return 0;
case 0x24c58086:
device_set_desc(dev, "Intel 82801DC (ICH4)");
case ICH4ID:
device_set_desc(dev, "Intel 82801DB (ICH4)");
return 0;
case SIS7012ID:
@ -631,7 +636,6 @@ ich_pci_probe(device_t dev)
static int
ich_pci_attach(device_t dev)
{
u_int32_t data;
u_int16_t extcaps;
struct sc_info *sc;
char status[SND_STATUSLEN];
@ -656,10 +660,23 @@ ich_pci_attach(device_t dev)
sc->sample_size = 2;
}
data = pci_read_config(dev, PCIR_COMMAND, 2);
data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
pci_write_config(dev, PCIR_COMMAND, data, 2);
data = pci_read_config(dev, PCIR_COMMAND, 2);
/*
* By default, ich4 has NAMBAR and NABMBAR i/o spaces as
* read-only. Need to enable "legacy support", by poking into
* pci config space. The driver should use MMBAR and MBBAR,
* but doing so will mess things up here. ich4 has enough new
* features it warrants it's own driver.
*/
if (pci_get_devid(dev) == ICH4ID) {
pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1);
}
pci_enable_io(dev, SYS_RES_IOPORT);
/*
* Enable bus master. On ich4 this may prevent the detection of
* the primary codec becoming ready in ich_init().
*/
pci_enable_busmaster(dev);
sc->nambarid = PCIR_NAMBAR;
sc->nabmbarid = PCIR_NABMBAR;

3
sys/dev/sound/pci/ich.h
View File

@ -30,6 +30,9 @@
#define PCIR_NAMBAR 0x10
#define PCIR_NABMBAR 0x14
#define PCIR_ICH_LEGACY 0x41
#define ICH_LEGACY_ENABLE 0x01
/* Native Audio Bus Master Control Registers */
#define ICH_REG_X_BDBAR 0x00
#define ICH_REG_X_CIV 0x04