Fix some strange errors of shutting transmitter up when start
transmition after software reset with no link estabilished yet. Fix TX DMA stop method (queue last packet to stop). PR: i386/6578
This commit is contained in:
Semen Ustimenko
parent
cec496ec2d
commit
e3e1bee33a
1181
sys/dev/tx/if_tx.c
1181
sys/dev/tx/if_tx.c
File diff suppressed because it is too large
Load Diff
1181
sys/pci/if_tx.c
1181
sys/pci/if_tx.c
File diff suppressed because it is too large
Load Diff
@ -23,25 +23,19 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: smc83c170.h,v 1.7 1998/04/15 17:47:08 bde Exp $
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* $Id: smc83c170.h,v 1.14 1998/07/03 23:59:09 galv Exp $
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*
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*/
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/*
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* Configuration
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*/
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#define EPIC_MAX_DEVICES 4
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#define TX_RING_SIZE 16
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#define RX_RING_SIZE 16
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#define TX_RING_SIZE 8
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#define RX_RING_SIZE 8
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#define EPIC_FULL_DUPLEX 1
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#define EPIC_HALF_DUPLEX 0
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#define ETHER_MAX_FRAME_LEN (ETHER_MAX_LEN + ETHER_CRC_LEN)
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/* Shall be moved to ../net/if_mib.h */
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#define dot3VendorSMC 8
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#define dot3ChipSetSMC83c170 1
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#define EPIC_LINK_DOWN 0x00000001
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/* PCI identification */
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#define SMC_VENDORID 0x10B8
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@ -180,11 +174,21 @@
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#define TXCON_LOOPBACK_DISABLE 0x00000000
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#define TXCON_LOOPBACK_MODE_INT 0x00000002
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#define TXCON_LOOPBACK_MODE_PHY 0x00000004
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#define TXCON_LOOPBACK_MODE_FULL_DUPLEX 0x00000006
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#define TXCON_LOOPBACK_MODE 0x00000006
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#define TXCON_FULL_DUPLEX 0x00000006
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#define TXCON_SLOT_TIME 0x00000078
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#define TXCON_DEFAULT (TXCON_SLOT_TIME|TXCON_EARLY_TRANSMIT_ENABLE)
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#if defined(EARLY_TX)
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#define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE)
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#define TRANSMIT_THRESHOLD 0x40
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#else
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#define TXCON_DEFAULT (TXCON_SLOT_TIME)
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#endif
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#if defined(EARLY_RX)
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#define RXCON_DEFAULT (RXCON_EARLY_RECEIVE_ENABLE | RXCON_SAVE_ERRORED_PACKETS)
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#else
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#define RXCON_DEFAULT (0)
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#endif
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/*
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* National Semiconductor's DP83840A Registers and bits
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*/
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@ -228,9 +232,15 @@
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* Quality Semiconductor's QS6612 registers and bits
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*/
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#define QS6612_OUI 0x006051
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#define QS6612_MCTL 17
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#define QS6612_INTSTAT 29
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#define QS6612_INTMASK 30
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#define MCTL_T4_PRESENT 0x1000 /* External T4 Enabled, ignored */
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/* if AutoNeg is enabled */
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#define MCTL_BTEXT 0x0800 /* Reduces 10baset squelch level */
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/* for extended cable length */
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#define INTSTAT_AN_COMPLETE 0x40 /* Autonegotiation complete */
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#define INTSTAT_RF_DETECTED 0x20 /* Remote Fault detected */
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#define INTSTAT_LINK_STATUS 0x10 /* Link status changed */
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@ -278,19 +288,11 @@ struct epic_frag_list {
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/* This is driver's structure to define EPIC descriptors */
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struct epic_rx_buffer {
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#if defined(RX_TO_MBUF)
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struct mbuf * mbuf; /* mbuf receiving packet */
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#else
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caddr_t data; /* or static address */
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#endif
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};
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struct epic_tx_buffer {
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#if defined(TX_FRAG_LIST)
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struct mbuf * mbuf; /* mbuf contained packet */
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#else
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caddr_t data; /* Tx buffer address */
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#endif
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};
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/*
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@ -308,13 +310,12 @@ typedef struct {
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/* and bounded on PAGE_SIZE */
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struct epic_rx_desc *rx_desc;
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struct epic_tx_desc *tx_desc;
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#if defined(TX_FRAG_LIST)
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struct epic_frag_list *tx_flist;
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#endif
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#if defined(_NET_IF_MEDIA_H_)
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struct ifmedia ifmedia;
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#endif
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struct arpcom epic_ac;
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u_int32_t flags;
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u_int32_t phyid;
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u_int32_t cur_tx;
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u_int32_t cur_rx;
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@ -325,7 +326,6 @@ typedef struct {
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#else
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caddr_t csr;
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#endif
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struct ifmib_iso_8802_3 dot3stats;
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} epic_softc_t;
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#define epic_if epic_ac.ac_if
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@ -345,6 +345,8 @@ typedef struct {
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#define CSR_READ_2(sc,reg) (*(u_int16_t*)((sc)->csr + (u_int32_t)(reg)))
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#define CSR_READ_4(sc,reg) (*(u_int32_t*)((sc)->csr + (u_int32_t)(reg)))
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#endif
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#define PHY_READ_2(sc,reg) epic_read_phy_register(sc,reg)
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#define PHY_WRITE_2(sc,reg,val) epic_write_phy_register(sc,reg,val)
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static char* epic_pci_probe __P((pcici_t, pcidi_t));
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@ -367,10 +369,13 @@ static void epic_shutdown __P((int, void *));
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static int epic_init_rings __P((epic_softc_t *));
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static void epic_free_rings __P((epic_softc_t *));
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static void epic_stop_activity __P((epic_softc_t *));
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static void epic_start_activity __P((epic_softc_t *));
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static void epic_set_rx_mode __P((epic_softc_t *));
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static void epic_set_mc_table __P((epic_softc_t *));
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static void epic_set_media_speed __P((epic_softc_t *));
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static void epic_init_phy __P((epic_softc_t *));
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static void epic_dump_state __P((epic_softc_t *));
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static int epic_autoneg __P((epic_softc_t *));
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static int epic_read_eeprom __P((epic_softc_t *,u_int16_t));
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@ -380,5 +385,5 @@ static u_int8_t epic_eeprom_clock __P((epic_softc_t *,u_int8_t));
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static void epic_write_eepromreg __P((epic_softc_t *,u_int8_t));
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static u_int8_t epic_read_eepromreg __P((epic_softc_t *));
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static int epic_read_phy_register __P((epic_softc_t *, u_int16_t));
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static void epic_write_phy_register __P((epic_softc_t *, u_int16_t,u_int16_t));
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static u_int16_t epic_read_phy_register __P((epic_softc_t *, u_int16_t));
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static void epic_write_phy_register __P((epic_softc_t *, u_int16_t, u_int16_t));
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