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dts: Import DTS from Linux 5.6

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This commit is contained in:
manu 2020-04-14 18:57:00 +00:00
commit e3f3d28ae8
576 changed files with 33072 additions and 10757 deletions
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40
sys/gnu/dts/arm/am335x-evm.dts
View File

@ -113,7 +113,7 @@
};
};
backlight {
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 0>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
@ -121,35 +121,15 @@
};
panel {
compatible = "ti,tilcdc,panel";
status = "okay";
compatible = "tfc,s9700rtwv43tr-01b";
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins_s0>;
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
backlight = <&backlight>;
display-timings {
800x480p62 {
clock-frequency = <30000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <39>;
hback-porch = <39>;
hsync-len = <47>;
vback-porch = <29>;
vfront-porch = <13>;
vsync-len = <2>;
hsync-active = <1>;
vsync-active = <1>;
port {
panel_0: endpoint@0 {
remote-endpoint = <&lcdc_0>;
};
};
};
@ -500,6 +480,12 @@
status = "okay";
blue-and-red-wiring = "crossed";
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&panel_0>;
};
};
};
&elm {

38
sys/gnu/dts/arm/am335x-evmsk.dts
View File

@ -183,36 +183,16 @@
};
panel {
compatible = "ti,tilcdc,panel";
compatible = "newhaven,nhd-4.3-480272ef-atxl";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&lcd_pins_default>;
pinctrl-1 = <&lcd_pins_sleep>;
backlight = <&lcd_bl>;
status = "okay";
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <32>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
480x272 {
hactive = <480>;
vactive = <272>;
hback-porch = <43>;
hfront-porch = <8>;
hsync-len = <4>;
vback-porch = <12>;
vfront-porch = <4>;
vsync-len = <10>;
clock-frequency = <9000000>;
hsync-active = <0>;
vsync-active = <0>;
port {
panel_0: endpoint@0 {
remote-endpoint = <&lcdc_0>;
};
};
};
@ -725,6 +705,12 @@
status = "okay";
blue-and-red-wiring = "crossed";
port {
lcdc_0: endpoint@0 {
remote-endpoint = <&panel_0>;
};
};
};
&rtc {

13
sys/gnu/dts/arm/am335x-icev2.dts
View File

@ -287,6 +287,19 @@
gpio-controller;
#gpio-cells = <2>;
};
/* osd9616p0899-10 */
display@3c {
compatible = "solomon,ssd1306fb-i2c";
reg = <0x3c>;
solomon,height = <16>;
solomon,width = <96>;
solomon,com-seq;
solomon,com-invdir;
solomon,page-offset = <0>;
solomon,prechargep1 = <2>;
solomon,prechargep2 = <13>;
};
};
&spi0 {

16
sys/gnu/dts/arm/am33xx-l4.dtsi
View File

@ -225,7 +225,6 @@
target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "adc_tsc";
reg = <0xd000 0x4>,
<0xd010 0x4>;
reg-names = "rev", "sysc";
@ -1009,7 +1008,6 @@
target-module@30000 { /* 0x48030000, ap 77 08.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi0";
reg = <0x30000 0x4>,
<0x30110 0x4>,
<0x30114 0x4>;
@ -1134,7 +1132,6 @@
target-module@42000 { /* 0x48042000, ap 24 1c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer3";
reg = <0x42000 0x4>,
<0x42010 0x4>,
<0x42014 0x4>;
@ -1160,7 +1157,6 @@
target-module@44000 { /* 0x48044000, ap 26 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer4";
reg = <0x44000 0x4>,
<0x44010 0x4>,
<0x44014 0x4>;
@ -1187,7 +1183,6 @@
target-module@46000 { /* 0x48046000, ap 28 28.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer5";
reg = <0x46000 0x4>,
<0x46010 0x4>,
<0x46014 0x4>;
@ -1214,7 +1209,6 @@
target-module@48000 { /* 0x48048000, ap 30 22.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer6";
reg = <0x48000 0x4>,
<0x48010 0x4>,
<0x48014 0x4>;
@ -1241,7 +1235,6 @@
target-module@4a000 { /* 0x4804a000, ap 85 60.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer7";
reg = <0x4a000 0x4>,
<0x4a010 0x4>,
<0x4a014 0x4>;
@ -1344,7 +1337,6 @@
target-module@80000 { /* 0x48080000, ap 38 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "elm";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
@ -1412,7 +1404,6 @@
target-module@ca000 { /* 0x480ca000, ap 91 40.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spinlock";
reg = <0xca000 0x4>,
<0xca010 0x4>,
<0xca014 0x4>;
@ -1533,7 +1524,6 @@
target-module@a0000 { /* 0x481a0000, ap 79 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi1";
reg = <0xa0000 0x4>,
<0xa0110 0x4>,
<0xa0114 0x4>;
@ -1749,7 +1739,6 @@
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xcc020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can0";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
<&dcan0_fck>;
@ -1773,7 +1762,6 @@
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xd0020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can1";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
<&dcan1_fck>;
@ -1863,7 +1851,6 @@
target-module@0 { /* 0x48300000, ap 66 48.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss0";
reg = <0x0 0x4>,
<0x4 0x4>;
reg-names = "rev", "sysc";
@ -1916,7 +1903,6 @@
target-module@2000 { /* 0x48302000, ap 68 52.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss1";
reg = <0x2000 0x4>,
<0x2004 0x4>;
reg-names = "rev", "sysc";
@ -1969,7 +1955,6 @@
target-module@4000 { /* 0x48304000, ap 70 44.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss2";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
@ -2022,7 +2007,6 @@
target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "lcdc";
reg = <0xe000 0x4>,
<0xe054 0x4>;
reg-names = "rev", "sysc";

94
sys/gnu/dts/arm/am33xx.dtsi
View File

@ -440,23 +440,87 @@
status = "disabled";
};
sham: sham@53100000 {
compatible = "ti,omap4-sham";
ti,hwmods = "sham";
reg = <0x53100000 0x200>;
interrupts = <109>;
dmas = <&edma 36 0>;
dma-names = "rx";
sham_target: target-module@53100000 {
compatible = "ti,sysc-omap3-sham", "ti,sysc";
reg = <0x53100100 0x4>,
<0x53100110 0x4>,
<0x53100114 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53100000 0x1000>;
sham: sham@0 {
compatible = "ti,omap4-sham";
reg = <0 0x200>;
interrupts = <109>;
dmas = <&edma 36 0>;
dma-names = "rx";
};
};
aes: aes@53500000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes";
reg = <0x53500000 0xa0>;
interrupts = <103>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
aes_target: target-module@53500000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x53500080 0x4>,
<0x53500084 0x4>,
<0x53500088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53500000 0x1000>;
aes: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <103>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
};
};
target-module@56000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_gfx 0>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x56000000 0x1000000>;
/*
* Closed source PowerVR driver, no child device
* binding or driver in mainline
*/
};
};
};

2
sys/gnu/dts/arm/am3517.dtsi
View File

@ -74,7 +74,7 @@
clock-names = "ick";
};
davinci_mdio: ethernet@5c030000 {
davinci_mdio: mdio@5c030000 {
compatible = "ti,davinci_mdio";
ti,hwmods = "davinci_mdio";
status = "disabled";

14
sys/gnu/dts/arm/am3703.dtsi Normal file
View File

@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
*/
#include "omap36xx.dtsi"
&iva {
status = "disabled";
};
&sgx_module {
status = "disabled";
};

10
sys/gnu/dts/arm/am3715.dtsi Normal file
View File

@ -0,0 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
*/
#include "omap36xx.dtsi"
&iva {
status = "disabled";
};

162
sys/gnu/dts/arm/am4372.dtsi
View File

@ -256,33 +256,92 @@
};
};
sham: sham@53100000 {
compatible = "ti,omap5-sham";
ti,hwmods = "sham";
reg = <0x53100000 0x300>;
dmas = <&edma 36 0>;
dma-names = "rx";
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
sham_target: target-module@53100000 {
compatible = "ti,sysc-omap3-sham", "ti,sysc";
reg = <0x53100100 0x4>,
<0x53100110 0x4>,
<0x53100114 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53100000 0x1000>;
sham: sham@0 {
compatible = "ti,omap5-sham";
reg = <0 0x300>;
dmas = <&edma 36 0>;
dma-names = "rx";
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
};
};
aes: aes@53501000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes";
reg = <0x53501000 0xa0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
aes_target: target-module@53501000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x53501080 0x4>,
<0x53501084 0x4>,
<0x53501088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x53501000 0x1000>;
aes: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
};
};
des: des@53701000 {
compatible = "ti,omap4-des";
ti,hwmods = "des";
reg = <0x53701000 0xa0>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 34 0>,
<&edma 33 0>;
dma-names = "tx", "rx";
des_target: target-module@53701000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x53701030 0x4>,
<0x53701034 0x4>,
<0x53701038 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l3_clkdm */
clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x53701000 0x1000>;
des: des@0 {
compatible = "ti,omap4-des";
reg = <0 0xa0>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma 34 0>,
<&edma 33 0>;
dma-names = "tx", "rx";
};
};
gpmc: gpmc@50000000 {
@ -305,17 +364,34 @@
status = "disabled";
};
qspi: spi@47900000 {
compatible = "ti,am4372-qspi";
reg = <0x47900000 0x100>,
<0x30000000 0x4000000>;
reg-names = "qspi_base", "qspi_mmap";
target-module@47900000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x47900000 0x4>,
<0x47900010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
interrupts = <0 138 0x4>;
num-cs = <4>;
status = "disabled";
#size-cells = <1>;
ranges = <0x0 0x47900000 0x1000>,
<0x30000000 0x30000000 0x4000000>;
qspi: spi@0 {
compatible = "ti,am4372-qspi";
reg = <0 0x100>,
<0x30000000 0x4000000>;
reg-names = "qspi_base", "qspi_mmap";
clocks = <&dpll_per_m2_div4_ck>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 138 0x4>;
num-cs = <4>;
};
};
dss: dss@4832a000 {
@ -369,6 +445,26 @@
pool;
};
};
target-module@56000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_gfx 0>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x56000000 0x1000000>;
};
};
};

4
sys/gnu/dts/arm/am437x-idk-evm.dts
View File

@ -526,11 +526,11 @@
* Supply voltage supervisor on board will not allow opp50 so
* disable it and set opp100 as suspend OPP.
*/
opp50@300000000 {
opp50-300000000 {
status = "disabled";
};
opp100@600000000 {
opp100-600000000 {
opp-suspend;
};
};

29
sys/gnu/dts/arm/am437x-l4.dtsi
View File

@ -225,7 +225,6 @@
target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "adc_tsc";
reg = <0xd000 0x4>,
<0xd010 0x4>;
reg-names = "rev", "sysc";
@ -763,7 +762,6 @@
target-module@30000 { /* 0x48030000, ap 65 08.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi0";
reg = <0x30000 0x4>,
<0x30110 0x4>,
<0x30114 0x4>;
@ -900,7 +898,6 @@
target-module@42000 { /* 0x48042000, ap 20 24.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer3";
reg = <0x42000 0x4>,
<0x42010 0x4>,
<0x42014 0x4>;
@ -927,7 +924,6 @@
target-module@44000 { /* 0x48044000, ap 22 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer4";
reg = <0x44000 0x4>,
<0x44010 0x4>,
<0x44014 0x4>;
@ -955,7 +951,6 @@
target-module@46000 { /* 0x48046000, ap 24 28.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer5";
reg = <0x46000 0x4>,
<0x46010 0x4>,
<0x46014 0x4>;
@ -983,7 +978,6 @@
target-module@48000 { /* 0x48048000, ap 26 1a.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer6";
reg = <0x48000 0x4>,
<0x48010 0x4>,
<0x48014 0x4>;
@ -1011,7 +1005,6 @@
target-module@4a000 { /* 0x4804a000, ap 71 48.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer7";
reg = <0x4a000 0x4>,
<0x4a010 0x4>,
<0x4a014 0x4>;
@ -1107,7 +1100,6 @@
target-module@80000 { /* 0x48080000, ap 32 18.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "elm";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
@ -1169,7 +1161,6 @@
target-module@ca000 { /* 0x480ca000, ap 77 38.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spinlock";
reg = <0xca000 0x4>,
<0xca010 0x4>,
<0xca014 0x4>;
@ -1282,7 +1273,6 @@
target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi1";
reg = <0xa0000 0x4>,
<0xa0110 0x4>,
<0xa0114 0x4>;
@ -1313,7 +1303,6 @@
target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi2";
reg = <0xa2000 0x4>,
<0xa2110 0x4>,
<0xa2114 0x4>;
@ -1344,7 +1333,6 @@
target-module@a4000 { /* 0x481a4000, ap 92 62.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi3";
reg = <0xa4000 0x4>,
<0xa4110 0x4>,
<0xa4114 0x4>;
@ -1527,7 +1515,6 @@
target-module@c1000 { /* 0x481c1000, ap 94 68.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer8";
reg = <0xc1000 0x4>,
<0xc1010 0x4>,
<0xc1014 0x4>;
@ -1556,7 +1543,6 @@
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xcc020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can0";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>;
clock-names = "fck";
@ -1577,7 +1563,6 @@
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xd0020 0x4>;
reg-names = "rev";
ti,hwmods = "d_can1";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>;
clock-names = "fck";
@ -1695,7 +1680,6 @@
target-module@0 { /* 0x48300000, ap 56 40.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss0";
reg = <0x0 0x4>,
<0x4 0x4>;
reg-names = "rev", "sysc";
@ -1748,7 +1732,6 @@
target-module@2000 { /* 0x48302000, ap 58 4a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss1";
reg = <0x2000 0x4>,
<0x2004 0x4>;
reg-names = "rev", "sysc";
@ -1801,7 +1784,6 @@
target-module@4000 { /* 0x48304000, ap 60 44.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss2";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
@ -1854,7 +1836,6 @@
target-module@6000 { /* 0x48306000, ap 96 58.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss3";
reg = <0x6000 0x4>,
<0x6004 0x4>;
reg-names = "rev", "sysc";
@ -1896,7 +1877,6 @@
target-module@8000 { /* 0x48308000, ap 98 54.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss4";
reg = <0x8000 0x4>,
<0x8004 0x4>;
reg-names = "rev", "sysc";
@ -1938,7 +1918,6 @@
target-module@a000 { /* 0x4830a000, ap 100 60.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss5";
reg = <0xa000 0x4>,
<0xa004 0x4>;
reg-names = "rev", "sysc";
@ -2086,7 +2065,6 @@
target-module@26000 { /* 0x48326000, ap 86 66.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "vpfe0";
reg = <0x26000 0x4>,
<0x26104 0x4>;
reg-names = "rev", "sysc";
@ -2113,7 +2091,6 @@
target-module@28000 { /* 0x48328000, ap 75 0e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "vpfe1";
reg = <0x28000 0x4>,
<0x28104 0x4>;
reg-names = "rev", "sysc";
@ -2162,7 +2139,6 @@
target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer9";
reg = <0x3d000 0x4>,
<0x3d010 0x4>,
<0x3d014 0x4>;
@ -2189,7 +2165,6 @@
target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer10";
reg = <0x3f000 0x4>,
<0x3f010 0x4>,
<0x3f014 0x4>;
@ -2216,7 +2191,6 @@
target-module@41000 { /* 0x48341000, ap 106 76.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer11";
reg = <0x41000 0x4>,
<0x41010 0x4>,
<0x41014 0x4>;
@ -2243,7 +2217,6 @@
target-module@45000 { /* 0x48345000, ap 108 6a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spi4";
reg = <0x45000 0x4>,
<0x45110 0x4>,
<0x45114 0x4>;
@ -2358,7 +2331,6 @@
target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "ocp2scp0";
reg = <0xa8000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */
@ -2440,7 +2412,6 @@
target-module@e8000 { /* 0x483e8000, ap 129 78.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "ocp2scp1";
reg = <0xe8000 0x4>;
reg-names = "rev";
/* Domains (P, C): per_pwrdm, l4ls_clkdm */

27
sys/gnu/dts/arm/am437x-sk-evm.dts
View File

@ -272,6 +272,12 @@
>;
};
clkout1_pin: pinmux_clkout1_pin {
pinctrl-single,pins = <
0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */
>;
};
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
@ -593,6 +599,25 @@
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
ov2659@30 {
compatible = "ovti,ov2659";
reg = <0x30>;
pinctrl-names = "default";
pinctrl-0 = <&clkout1_pin>;
clocks = <&clkout1_mux_ck>;
clock-names = "xvclk";
assigned-clocks = <&clkout1_mux_ck>;
assigned-clock-parents = <&clkout1_osc_div_ck>;
port {
ov2659_1: endpoint {
remote-endpoint = <&vpfe0_ep>;
link-frequencies = /bits/ 64 <70000000>;
};
};
};
edt-ft5306@38 {
status = "okay";
compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
@ -877,7 +902,7 @@
/* Camera port */
port {
vpfe0_ep: endpoint {
/* remote-endpoint = <&sensor>; add once we have it */
remote-endpoint = <&ov2659_1>;
ti,am437x-vpfe-interface = <0>;
bus-width = <8>;
hsync-active = <0>;

23
sys/gnu/dts/arm/am43x-epos-evm.dts
View File

@ -145,6 +145,12 @@
system-clock-frequency = <12000000>;
};
};
audio_mstrclk: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
};
};
&am43xx_pinmux {
@ -696,6 +702,21 @@
IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
};
ov2659@30 {
compatible = "ovti,ov2659";
reg = <0x30>;
clocks = <&audio_mstrclk>;
clock-names = "xvclk";
port {
ov2659_1: endpoint {
remote-endpoint = <&vpfe1_ep>;
link-frequencies = /bits/ 64 <70000000>;
};
};
};
};
&i2c2 {
@ -964,7 +985,7 @@
port {
vpfe1_ep: endpoint {
/* remote-endpoint = <&sensor>; add once we have it */
remote-endpoint = <&ov2659_1>;
ti,am437x-vpfe-interface = <0>;
bus-width = <8>;
hsync-active = <0>;

54
sys/gnu/dts/arm/am43xx-clocks.dtsi
View File

@ -704,6 +704,60 @@
ti,bit-shift = <8>;
reg = <0x2a48>;
};
clkout1_osc_div_ck: clkout1-osc-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <20>;
ti,max-div = <4>;
reg = <0x4100>;
};
clkout1_src2_mux_ck: clkout1-src2-mux-ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
<&dpll_mpu_m2_ck>;
reg = <0x4100>;
};
clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_mux_ck>;
ti,bit-shift = <4>;
ti,max-div = <8>;
reg = <0x4100>;
};
clkout1_src2_post_div_ck: clkout1-src2-post-div-ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&clkout1_src2_pre_div_ck>;
ti,bit-shift = <8>;
ti,max-div = <32>;
ti,index-power-of-two;
reg = <0x4100>;
};
clkout1_mux_ck: clkout1-mux-ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
ti,bit-shift = <16>;
reg = <0x4100>;
};
clkout1_ck: clkout1-ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout1_mux_ck>;
ti,bit-shift = <23>;
reg = <0x4100>;
};
};
&prcm {

59
sys/gnu/dts/arm/am57xx-idk-common.dtsi
View File

@ -9,6 +9,7 @@
aliases {
rtc0 = &tps659038_rtc;
rtc1 = &rtc;
display0 = &hdmi0;
};
chosen {
@ -96,6 +97,48 @@
default-state = "off";
};
};
hdmi0: connector@0 {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
tpd12s015: encoder@0 {
compatible = "ti,tpd12s016", "ti,tpd12s015";
gpios = <0>, /* optional CT_CP_HPD */
<0>, /* optional LS_OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint@0 {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint@0 {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&dra7_pmx_core {
@ -485,3 +528,19 @@
&cpu0 {
vdd-supply = <&smps12_reg>;
};
&hdmi {
status = "okay";
vdda-supply = <&ldo4_reg>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};
&dss {
status = "okay";
};

115
sys/gnu/dts/arm/armada-385-clearfog-gtr-l8.dts Normal file
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@ -0,0 +1,115 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include "armada-385-clearfog-gtr.dtsi"
/ {
model = "SolidRun Clearfog GTR L8";
};
&mdio {
switch0: switch0@4 {
compatible = "marvell,mv88e6190";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
label = "lan8";
phy-handle = <&switch0phy0>;
};
port@2 {
reg = <2>;
label = "lan7";
phy-handle = <&switch0phy1>;
};
port@3 {
reg = <3>;
label = "lan6";
phy-handle = <&switch0phy2>;
};
port@4 {
reg = <4>;
label = "lan5";
phy-handle = <&switch0phy3>;
};
port@5 {
reg = <5>;
label = "lan4";
phy-handle = <&switch0phy4>;
};
port@6 {
reg = <6>;
label = "lan3";
phy-handle = <&switch0phy5>;
};
port@7 {
reg = <7>;
label = "lan2";
phy-handle = <&switch0phy6>;
};
port@8 {
reg = <8>;
label = "lan1";
phy-handle = <&switch0phy7>;
};
port@10 {
reg = <10>;
label = "cpu";
ethernet = <&eth1>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: switch0phy0@1 {
reg = <0x1>;
};
switch0phy1: switch0phy1@2 {
reg = <0x2>;
};
switch0phy2: switch0phy2@3 {
reg = <0x3>;
};
switch0phy3: switch0phy3@4 {
reg = <0x4>;
};
switch0phy4: switch0phy4@5 {
reg = <0x5>;
};
switch0phy5: switch0phy5@6 {
reg = <0x6>;
};
switch0phy6: switch0phy6@7 {
reg = <0x7>;
};
switch0phy7: switch0phy7@8 {
reg = <0x8>;
};
};
};
};

79
sys/gnu/dts/arm/armada-385-clearfog-gtr-s4.dts Normal file
View File

@ -0,0 +1,79 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#include "armada-385-clearfog-gtr.dtsi"
/ {
model = "SolidRun Clearfog GTR S4";
};
&sfp0 {
tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
};
&mdio {
switch0: switch0@4 {
compatible = "marvell,mv88e6085";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
label = "lan2";
phy-handle = <&switch0phy0>;
};
port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
port@3 {
reg = <3>;
label = "lan4";
phy-handle = <&switch0phy2>;
};
port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&eth1>;
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
switch0phy3: switch0phy3@14 {
reg = <0x14>;
};
};
};
};

450
sys/gnu/dts/arm/armada-385-clearfog-gtr.dtsi Normal file
View File

@ -0,0 +1,450 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Clearfog GTR machines rev 1.0 (88F6825)
*
* Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
*/
/*
SERDES mapping -
0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
1. 6141 switch (2.5Gbps capable)
2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
3. USB 3.0 Host
4. mini PCIe CON2 - PCIe2
5. SFP connector, or optionally SGMII Ethernet 1512 PHY
USB 2.0 mapping -
0. USB 2.0 - 0 USB pins header CON12
1. USB 2.0 - 1 mini PCIe CON2
2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
Pin mapping -
0,1 - console UART
2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors,
front panel and PSE controller
4,5 - MDC/MDIO
6..17 - RGMII
18 - Topaz switch reset (active low)
19 - 1512 phy reset
20 - 1512 phy reset (eth2, optional)
21,28,37,38,39,40 - SD0
22 - USB 3.0 current limiter enable (active high)
24 - SFP TX fault (input active high)
25 - SFP present (input active low)
26,27 - I2C1 - connected to SFP
29 - Fan PWM
30 - CON4 mini PCIe wifi disable
31 - CON3 mini PCIe wifi disable
32 - Fuse programming power toggle (1.8v)
33 - CON4 mini PCIe reset
34 - CON2 mini PCIe wifi disable
35 - CON3 mini PCIe reset
36 - Rear button (GPIO active low)
41 - CON1 front panel connector
42 - Front LED1, or front panel CON1
43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS
44 - CON2 mini PCIe reset
45 - TPM PIRQ signal, or front panel CON1
46 - SFP TX disable
47 - Control isolation of boot sensitive SAR signals
48 - PSE reset
49 - PSE OSS signal
50 - PSE interrupt
52 - Front LED2, or front panel
53 - Front button
54 - SFP LOS (input active high)
55 - Fan sense
56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM
59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable)
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "armada-385.dtsi"
/ {
compatible = "marvell,armada385", "marvell,armada380";
aliases {
/* So that mvebu u-boot can update the MAC addresses */
ethernet1 = &eth0;
ethernet2 = &eth1;
ethernet3 = &eth2;
i2c0 = &i2c0;
i2c1 = &i2c1;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; /* 256 MB */
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
v_usb3_con: regulator-v-usb3-con {
compatible = "regulator-fixed";
gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_usb3_con_vbus>;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "v_usb3_con";
vin-supply = <&reg_5p0v>;
regulator-boot-on;
regulator-always-on;
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
internal-regs {
rtc@a3800 {
status = "okay";
};
i2c@11000 { /* ROM, temp sensor and front panel */
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
};
i2c@11100 { /* SFP (CON5/CON6) */
pinctrl-0 = <&cf_gtr_i2c1_pins>;
pinctrl-names = "default";
status = "okay";
};
pinctrl@18000 {
cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
marvell,pins = "mpp18";
marvell,function = "gpio";
};
cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
marvell,pins = "mpp22";
marvell,function = "gpio";
};
cf_gtr_fan_pwm: cf-gtr-fan-pwm {
marvell,pins = "mpp23";
marvell,function = "gpio";
};
cf_gtr_i2c1_pins: i2c1-pins {
/* SFP */
marvell,pins = "mpp26", "mpp27";
marvell,function = "i2c1";
};
cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
marvell,pins = "mpp21", "mpp28",
"mpp37", "mpp38",
"mpp39", "mpp40";
marvell,function = "sd0";
};
cf_gtr_isolation_pins: cf-gtr-isolation-pins {
marvell,pins = "mpp47";
marvell,function = "gpio";
};
cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
marvell,pins = "mpp48";
marvell,function = "gpio";
};
cf_gtr_spi1_cs_pins: spi1-cs-pins {
marvell,pins = "mpp59";
marvell,function = "spi1";
};
cf_gtr_front_button_pins: cf-gtr-front-button-pins {
marvell,pins = "mpp53";
marvell,function = "gpio";
};
cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
marvell,pins = "mpp36";
marvell,function = "gpio";
};
};
sdhci@d8000 {
bus-width = <4>;
no-1-8-v;
non-removable;
pinctrl-0 = <&cf_gtr_sdhci_pins>;
pinctrl-names = "default";
status = "okay";
vmmc = <&reg_3p3v>;
wp-inverted;
};
usb@58000 {
status = "okay";
};
usb3@f0000 {
status = "okay";
};
usb3@f8000 {
vbus-supply = <&v_usb3_con>;
status = "okay";
};
};
pcie {
status = "okay";
/*
* The PCIe units are accessible through
* the mini-PCIe connectors on the board.
*/
pcie@1,0 {
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
pcie@2,0 {
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
pcie@3,0 {
reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
};
sfp0: sfp {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
pinctrl-names = "default";
button_0 {
label = "Rear Button";
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
linux,can-disable;
linux,code = <BTN_0>;
};
button_1 {
label = "Front Button";
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
linux,can-disable;
linux,code = <BTN_1>;
};
};
gpio-leds {
compatible = "gpio-leds";
led1 {
function = LED_FUNCTION_CPU;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
led2 {
function = LED_FUNCTION_HEARTBEAT;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
};
};
};
&bm {
status = "okay";
};
&bm_bppi {
status = "okay";
};
&eth0 {
/* ethernet@70000 */
pinctrl-0 = <&ge0_rgmii_pins>;
pinctrl-names = "default";
phy = <&phy_dedicated>;
phy-mode = "rgmii-id";
buffer-manager = <&bm>;
bm,pool-long = <0>;
bm,pool-short = <1>;
status = "okay";
};
&eth1 {
/* ethernet@30000 */
bm,pool-long = <2>;
bm,pool-short = <1>;
buffer-manager = <&bm>;
phys = <&comphy1 1>;
phy-mode = "2500base-x";
status = "okay";
fixed-link {
speed = <2500>;
full-duplex;
};
};
&eth2 {
/* ethernet@34000 */
bm,pool-long = <3>;
bm,pool-short = <1>;
buffer-manager = <&bm>;
managed = "in-band-status";
phys = <&comphy5 1>;
phy-mode = "sgmii";
sfp = <&sfp0>;
status = "okay";
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
status = "okay";
phy_dedicated: ethernet-phy@0 {
/*
* Annoyingly, the marvell phy driver configures the LED
* register, rather than preserving reset-loaded setting.
* We undo that rubbish here.
*/
marvell,reg-init = <3 16 0 0x1017>;
reg = <0>;
};
};
&uart0 {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
status = "okay";
};
&spi1 {
/*
* CS0: W25Q32 flash
*/
pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>;
pinctrl-names = "default";
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "w25q32", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <3000000>;
status = "okay";
};
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
/* U26 temperature sensor placed near SoC */
temp1: nct75@4c {
compatible = "lm75";
reg = <0x4c>;
};
/* U27 temperature sensor placed near RTC battery */
temp2: nct75@4d {
compatible = "lm75";
reg = <0x4d>;
};
/* 2Kb eeprom */
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
};
};
&ahci0 {
status = "okay";
};
&ahci1 {
status = "okay";
};
&gpio0 {
pinctrl-0 = <&cf_gtr_fan_pwm>;
pinctrl-names = "default";
wifi-disable {
gpio-hog;
gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>;
output-low;
line-name = "wifi-disable";
};
};
&gpio1 {
pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
pinctrl-names = "default";
lte-disable {
gpio-hog;
gpios = <2 GPIO_ACTIVE_LOW>;
output-low;
line-name = "lte-disable";
};
/*
* This signal, when asserted, isolates Armada 38x sample at reset pins
* from control of external devices. Should be de-asserted after reset.
*/
sar-isolation {
gpio-hog;
gpios = <15 GPIO_ACTIVE_LOW>;
output-low;
line-name = "sar-isolation";
};
poe-reset {
gpio-hog;
gpios = <16 GPIO_ACTIVE_LOW>;
output-low;
line-name = "poe-reset";
};
};

11
sys/gnu/dts/arm/armada-388-clearfog.dtsi
View File

@ -111,11 +111,6 @@
};
&i2c0 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-CON3 CLKREQ#
@ -183,6 +178,12 @@
compatible = "microchip,mcp3021";
reg = <0x4c>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
};
&i2c1 {

5
sys/gnu/dts/arm/armada-388-helios4.dts
View File

@ -140,11 +140,6 @@
soc {
internal-regs {
i2c@11000 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
/*
* PCA9655 GPIO expander, up to 1MHz clock.
* 0-Board Revision bit 0 #

13
sys/gnu/dts/arm/armada-38x-solidrun-microsom.dtsi
View File

@ -71,6 +71,19 @@
};
};
&i2c0 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
};
&pinctrl {
microsom_phy_clk_pins: microsom-phy-clk-pins {
marvell,pins = "mpp45";

1
sys/gnu/dts/arm/aspeed-bmc-facebook-wedge100.dts
View File

@ -76,7 +76,6 @@
&mac1 {
status = "okay";
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};

1
sys/gnu/dts/arm/aspeed-bmc-facebook-wedge40.dts
View File

@ -75,7 +75,6 @@
&mac1 {
status = "okay";
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};

1
sys/gnu/dts/arm/aspeed-bmc-facebook-yamp.dts
View File

@ -35,7 +35,6 @@
&mac0 {
status = "okay";
use-ncsi;
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,

20
sys/gnu/dts/arm/aspeed-bmc-ibm-rainier.dts
View File

@ -97,22 +97,22 @@
status = "okay";
power-supply@68 {
compatible = "ibm,cffps2";
compatible = "ibm,cffps";
reg = <0x68>;
};
power-supply@69 {
compatible = "ibm,cffps2";
compatible = "ibm,cffps";
reg = <0x69>;
};
power-supply@6a {
compatible = "ibm,cffps2";
compatible = "ibm,cffps";
reg = <0x6a>;
};
power-supply@6b {
compatible = "ibm,cffps2";
compatible = "ibm,cffps";
reg = <0x6b>;
};
};
@ -352,18 +352,8 @@
&i2c8 {
status = "okay";
ucd90320@b {
compatible = "ti,ucd90160";
reg = <0x0b>;
};
ucd90320@c {
compatible = "ti,ucd90160";
reg = <0x0c>;
};
ucd90320@11 {
compatible = "ti,ucd90160";
compatible = "ti,ucd90320";
reg = <0x11>;
};

2
sys/gnu/dts/arm/aspeed-bmc-inspur-fp5280g2.dts
View File

@ -94,8 +94,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <1000>;
fan0-presence {

2
sys/gnu/dts/arm/aspeed-bmc-opp-swift.dts
View File

@ -82,8 +82,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <1000>;
scm0-presence {

18
sys/gnu/dts/arm/aspeed-bmc-opp-vesnin.dts
View File

@ -14,7 +14,7 @@
bootargs = "console=ttyS4,115200 earlyprintk";
};
memory {
memory@40000000 {
reg = <0x40000000 0x20000000>;
};
@ -107,10 +107,7 @@
&mac0 {
status = "okay";
use-ncsi;
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rmii1_default>;
};
@ -236,3 +233,16 @@
&wdt2 {
aspeed,alt-boot;
};
&sdmmc {
status = "okay";
};
&sdhci1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2_default>;
cd-inverted;
disable-wp;
};

2
sys/gnu/dts/arm/aspeed-bmc-opp-witherspoon.dts
View File

@ -77,8 +77,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <1000>;
fan0-presence {

21
sys/gnu/dts/arm/aspeed-g4.dtsi
View File

@ -179,18 +179,21 @@
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0 0x1e6e2000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,ast2400-pinctrl";
};
p2a: p2a-control {
p2a: p2a-control@2c {
reg = <0x2c 0x4>;
compatible = "aspeed,ast2400-p2a-ctrl";
status = "disabled";
};
pinctrl: pinctrl@80 {
reg = <0x80 0x18>, <0xa0 0x10>;
compatible = "aspeed,ast2400-pinctrl";
};
};
rng: hwrng@1e6e2078 {
@ -346,14 +349,14 @@
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2400-lpc-ctrl";
reg = <0x0 0x80>;
reg = <0x0 0x10>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
lpc_snoop: lpc-snoop@0 {
lpc_snoop: lpc-snoop@10 {
compatible = "aspeed,ast2400-lpc-snoop";
reg = <0x0 0x80>;
reg = <0x10 0x8>;
interrupts = <8>;
status = "disabled";
};

49
sys/gnu/dts/arm/aspeed-g5.dtsi
View File

@ -47,13 +47,6 @@
reg = <0x80000000 0>;
};
edac: sdram@1e6e0000 {
compatible = "aspeed,ast2500-sdram-edac";
reg = <0x1e6e0000 0x174>;
interrupts = <0>;
status = "disabled";
};
ahb {
compatible = "simple-bus";
#address-cells = <1>;
@ -213,23 +206,32 @@
#size-cells = <1>;
ranges;
edac: memory-controller@1e6e0000 {
compatible = "aspeed,ast2500-sdram-edac";
reg = <0x1e6e0000 0x174>;
interrupts = <0>;
status = "disabled";
};
syscon: syscon@1e6e2000 {
compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0 0x1e6e2000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
pinctrl: pinctrl {
compatible = "aspeed,ast2500-pinctrl";
aspeed,external-nodes = <&gfx &lhc>;
p2a: p2a-control@2c {
compatible = "aspeed,ast2500-p2a-ctrl";
reg = <0x2c 0x4>;
status = "disabled";
};
p2a: p2a-control {
compatible = "aspeed,ast2500-p2a-ctrl";
status = "disabled";
pinctrl: pinctrl@80 {
compatible = "aspeed,ast2500-pinctrl";
reg = <0x80 0x18>, <0xa0 0x10>;
aspeed,external-nodes = <&gfx>, <&lhc>;
};
};
@ -460,29 +462,30 @@
lpc_ctrl: lpc-ctrl@0 {
compatible = "aspeed,ast2500-lpc-ctrl";
reg = <0x0 0x80>;
reg = <0x0 0x10>;
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
status = "disabled";
};
lpc_snoop: lpc-snoop@0 {
lpc_snoop: lpc-snoop@10 {
compatible = "aspeed,ast2500-lpc-snoop";
reg = <0x0 0x80>;
reg = <0x10 0x8>;
interrupts = <8>;
status = "disabled";
};
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
lpc_reset: reset-controller@18 {
compatible = "aspeed,ast2500-lpc-reset";
reg = <0x18 0x4>;
#reset-cells = <1>;
};
lhc: lhc@20 {
compatible = "aspeed,ast2500-lhc";
reg = <0x20 0x24 0x48 0x8>;
};
ibt: ibt@c0 {
compatible = "aspeed,ast2500-ibt-bmc";
reg = <0xc0 0x18>;

2
sys/gnu/dts/arm/aspeed-g6.dtsi
View File

@ -365,7 +365,7 @@
status = "disabled";
};
wdt4: watchdog@1e7850C0 {
wdt4: watchdog@1e7850c0 {
compatible = "aspeed,ast2600-wdt";
reg = <0x1e7850C0 0x40>;
status = "disabled";

1
sys/gnu/dts/arm/ast2500-facebook-netbmc-common.dtsi
View File

@ -71,7 +71,6 @@
&mac1 {
status = "okay";
no-hw-checksum;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
};

172
sys/gnu/dts/arm/at91-kizbox.dts
View File

@ -28,85 +28,6 @@
};
};
ahb {
apb {
tcb0: timer@fffa0000 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
macb0: ethernet@fffc4000 {
phy-mode = "mii";
pinctrl-0 = <&pinctrl_macb_rmii
&pinctrl_macb_rmii_mii_alt>;
status = "okay";
};
usart3: serial@fffd0000 {
status = "okay";
};
dbgu: serial@fffff200 {
status = "okay";
};
watchdog@fffffd40 {
timeout-sec = <15>;
atmel,max-heartbeat-sec = <16>;
atmel,min-heartbeat-sec = <0>;
status = "okay";
};
};
usb0: ohci@500000 {
num-ports = <1>;
status = "okay";
};
ebi: ebi@10000000 {
status = "okay";
nand_controller: nand-controller {
status = "okay";
pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
pinctrl-names = "default";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
@ -127,15 +48,6 @@
};
};
i2c-gpio-0 {
status = "okay";
rtc: pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
pwm_leds {
compatible = "pwm-leds";
@ -179,3 +91,87 @@
&pinctrl_tcb1_tiob0>;
};
};
&tcb0 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>, <1>;
};
timer@2 {
compatible = "atmel,tcb-timer";
reg = <2>;
};
};
&ebi {
status = "okay";
};
&nand_controller {
status = "okay";
pinctrl-0 = <&pinctrl_nand_cs &pinctrl_nand_rb>;
pinctrl-names = "default";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
&macb0 {
phy-mode = "mii";
pinctrl-0 = <&pinctrl_macb_rmii
&pinctrl_macb_rmii_mii_alt>;
status = "okay";
};
&usart3 {
status = "okay";
};
&dbgu {
status = "okay";
};
&watchdog {
timeout-sec = <15>;
atmel,max-heartbeat-sec = <16>;
atmel,min-heartbeat-sec = <0>;
status = "okay";
};
&usb0 {
num-ports = <1>;
status = "okay";
};
&i2c_gpio0 {
status = "okay";
rtc: pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};

24
sys/gnu/dts/arm/at91-kizboxmini-base.dts Normal file
View File

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* at91-kizboxmini-base.dts - Device Tree file for Overkiz Kizbox mini
* base board
*
* Copyright (C) 2015 Overkiz SAS
* Author: Antoine Aubert <a.aubert@overkiz.com>
* Kévin Raymond <k.raymond@overkiz.com>
*/
/dts-v1/;
#include "at91-kizboxmini-common.dtsi"
/ {
model = "Overkiz Kizbox Mini";
compatible = "overkiz,kizboxmini-base", "atmel,at91sam9g25",
"atmel,at91sam9x5", "atmel,at91sam9";
};
&pinctrl_usart0 {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 2 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
};

165
sys/gnu/dts/arm/at91-kizboxmini.dts → sys/gnu/dts/arm/at91-kizboxmini-common.dtsi
View File

@ -1,17 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later
// SPDX-License-Identifier: GPL-2.0
/*
* at91-kizboxmini.dts - Device Tree file for Overkiz Kizbox mini board
*
* Copyright (C) 2014 Gaël PORTAY <g.portay@overkiz.com>
* Copyright (C) 2014-2018 Overkiz SAS
* Author: Antoine Aubert <a.aubert@overkiz.com>
* Gaël Portay <g.portay@overkiz.com>
* Kévin Raymond <k.raymond@overkiz.com>
* Dorian Rocipon <d.rocipon@overkiz.com>
*/
/dts-v1/;
#include "at91sam9g25.dtsi"
#include <dt-bindings/pwm/pwm.h>
/ {
model = "Overkiz Kizbox mini";
compatible = "overkiz,kizboxmini", "atmel,at91sam9g25", "atmel,at91sam9x5", "atmel,at91sam9";
chosen {
bootargs = "ubi.mtd=ubi";
stdout-path = &dbgu;
@ -22,24 +21,16 @@
};
clocks {
main_xtal {
clock-frequency = <12000000>;
};
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
};
ahb {
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
atmel,has-pmecc;
atmel,pmecc-cap = <4>;
atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
adc_op_clk {
status = "disabled";
};
};
@ -63,17 +54,25 @@
};
};
pwm_leds {
leds: pwm_leds {
compatible = "pwm-leds";
green {
led_blue: pwm_blue {
label = "pwm:blue:user";
pwms = <&pwm0 2 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "none";
status = "disabled";
};
led_green: pwm_green {
label = "pwm:green:user";
pwms = <&pwm0 0 10000000 0>;
max-brightness = <255>;
linux,default-trigger = "default-on";
};
red {
led_red: pwm_red {
label = "pwm:red:user";
pwms = <&pwm0 1 10000000 0>;
max-brightness = <255>;
@ -82,53 +81,12 @@
};
};
&dbgu {
&usart0 {
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
&ebi {
pinctrl-0 = <&pinctrl_ebi_addr_nand
&pinctrl_ebi_data_0_7>;
pinctrl-names = "default";
status = "okay";
nand-controller {
pinctrl-0 = <&pinctrl_nand_oe_we
&pinctrl_nand_cs
&pinctrl_nand_rb>;
pinctrl-names = "default";
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
};
&macb0 {
phy-mode = "rmii";
status = "okay";
@ -137,26 +95,70 @@
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_pwm0_1
&pinctrl_pwm0_pwm1_1>;
&pinctrl_pwm0_pwm1_1
&pinctrl_pwm0_pwm2_1>;
status = "okay";
};
&tcb0 {
timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
&dbgu {
status = "okay";
};
&usart0 {
&watchdog {
status = "okay";
};
&adc0 {
status = "disabled";
};
&rtc {
status = "disabled";
};
&ebi {
pinctrl-0 = <&pinctrl_ebi_addr_nand
&pinctrl_ebi_data_0_7>;
pinctrl-names = "default";
status = "okay";
};
&nand_controller {
status = "okay";
pinctrl-0 = <&pinctrl_nand_oe_we
&pinctrl_nand_cs
&pinctrl_nand_rb>;
pinctrl-names = "default";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootstrap@0 {
label = "bootstrap";
reg = <0x0 0x20000>;
};
ubi@20000 {
label = "ubi";
reg = <0x20000 0x7fe0000>;
};
};
};
};
&usb0 {
num-ports = <1>;
status = "okay";
@ -166,6 +168,3 @@
status = "okay";
};
&watchdog {
status = "okay";
};

26
sys/gnu/dts/arm/at91-kizboxmini-mb.dts Normal file
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@ -0,0 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015-2018 Overkiz SAS
* Author: Mickael Gardet <m.gardet@overkiz.com>
* Kévin Raymond <k.raymond@overkiz.com>
*/
/dts-v1/;
#include "at91-kizboxmini-common.dtsi"
/ {
model = "Overkiz Kizbox Mini Mother Board";
compatible = "overkiz,kizboxmini-mb", "atmel,at91sam9g25",
"atmel,at91sam9x5", "atmel,at91sam9";
};
&usb0 {
num-ports = <2>;
};
&rtc {
status = "okay";
};
&led_blue {
status = "okay";
};

49
sys/gnu/dts/arm/at91-kizboxmini-rd.dts Normal file
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@ -0,0 +1,49 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2015-2018 Overkiz SAS
* Author: Mickael Gardet <m.gardet@overkiz.com>
* Kévin Raymond <k.raymond@overkiz.com>
*/
/dts-v1/;
#include "at91-kizboxmini-common.dtsi"
/ {
model = "Overkiz Kizbox Mini RailDIN";
compatible = "overkiz,kizboxmini-rd", "atmel,at91sam9g25",
"atmel,at91sam9x5", "atmel,at91sam9";
clocks {
adc_op_clk {
status = "okay";
};
};
};
&pinctrl {
adc0 {
pinctrl_adc0_ad5: adc0_ad5-0 {
/* pull-up disable */
atmel,pins = <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
};
&usart0 {
status = "disabled";
};
&rtc {
status = "okay";
};
&led_blue {
status = "okay";
};
&adc0 {
atmel,adc-vref = <2500>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0_ad5>;
atmel,adc-channels-used = <0x0020>;
status = "okay";
};

1
sys/gnu/dts/arm/at91-nattis-2-natte-2.dts
View File

@ -8,7 +8,6 @@
*/
/dts-v1/;
#include "at91-linea.dtsi"
#include "sama5d3_lcd.dtsi"
#include "at91-natte.dtsi"
/ {

647
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@ -0,0 +1,647 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sam9x60ek.dts - Device Tree file for Microchip SAM9X60-EK board
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com>
*/
/dts-v1/;
#include "sam9x60.dtsi"
/ {
model = "Microchip SAM9X60-EK";
compatible = "microchip,sam9x60ek", "microchip,sam9x60", "atmel,at91sam9";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <24000000>;
};
};
regulators: regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vdd_1v8: fixed-regulator-vdd_1v8@0 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
status = "okay";
};
vdd_1v5: fixed-regulator-vdd_1v5@1 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
status = "okay";
};
vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
compatible = "regulator-fixed";
regulator-name = "VDD1_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
status = "okay";
};
vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
compatible = "regulator-fixed";
regulator-name = "VDD2_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
status = "okay";
};
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
status = "okay";
sw1 {
label = "SW1";
gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
linux,code=<0x104>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
status = "okay"; /* Conflict with pwm0. */
red {
label = "red";
gpios = <&pioB 11 GPIO_ACTIVE_HIGH>;
};
green {
label = "green";
gpios = <&pioB 12 GPIO_ACTIVE_HIGH>;
};
blue {
label = "blue";
gpios = <&pioB 13 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&adc {
vddana-supply = <&vdd1_3v3>;
vref-supply = <&vdd1_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
status = "okay";
};
&can0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_rx_tx>;
status = "disabled"; /* Conflict with dbgu. */
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_rx_tx>;
status = "okay";
};
&classd {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_classd_default>;
atmel,pwm-type = "diff";
atmel,non-overlap-time = <10>;
status = "okay";
};
&dbgu {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
status = "okay"; /* Conflict with can0. */
};
&ebi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
status = "okay";
nand_controller: nand-controller {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
status = "okay";
nand@3 {
reg = <0x3 0x0 0x800000>;
rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
uboot@40000 {
label = "u-boot";
reg = <0x40000 0xc0000>;
};
ubootenvred@100000 {
label = "U-Boot Env Redundant";
reg = <0x100000 0x40000>;
};
ubootenv@140000 {
label = "U-Boot Env";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x1f800000>;
};
};
};
};
};
&flx0 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c0: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
atmel,fifo-size = <16>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
eeprom@53 {
compatible = "atmel,24c32";
reg = <0x53>;
pagesize = <16>;
size = <128>;
status = "okay";
};
};
};
&flx4 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
status = "disabled";
spi0: spi@400 {
compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
clock-names = "spi_clk";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx4_default>;
atmel,fifo-size = <16>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
&flx5 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
uart1: serial@200 {
compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(10))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(11))>;
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
clock-names = "usart";
pinctrl-0 = <&pinctrl_flx5_default>;
pinctrl-names = "default";
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
};
&flx6 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
i2c1: i2c@600 {
compatible = "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx6_default>;
atmel,fifo-size = <16>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
gpio_exp: mcp23008@20 {
compatible = "microchip,mcp23008";
reg = <0x20>;
};
};
};
&i2s {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2s_default>;
#sound-dai-cells = <0>;
status = "disabled"; /* Conflict with QSPI. */
};
&macb0 {
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii>;
status = "okay";
ethernet-phy@0 {
reg = <0x0>;
};
};
&pinctrl {
atmel,mux-mask = <
/* A B C */
0xFFFFFE7F 0xC0E0397F 0xEF00019D /* pioA */
0x03FFFFFF 0x02FC7E68 0x00780000 /* pioB */
0xffffffff 0xF83FFFFF 0xB800F3FC /* pioC */
0x003FFFFF 0x003F8000 0x00000000 /* pioD */
>;
adc {
pinctrl_adc_default: adc_default {
atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_adtrg_default: adtrg_default {
atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
};
};
dbgu {
pinctrl_dbgu: dbgu-0 {
atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
};
i2s {
pinctrl_i2s_default: i2s {
atmel,pins =
<AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SCK */
AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SWS */
AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SDIN */
AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* I2SDOUT */
AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* I2SMCK */
};
};
qspi {
pinctrl_qspi: qspi {
atmel,pins =
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_SLEWRATE_DIS
AT91_PIOB 21 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOB 22 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOB 23 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOB 24 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_SLEWRATE_DIS)>;
};
};
nand {
pinctrl_nand_oe_we: nand-oe-we-0 {
atmel,pins =
<AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
pinctrl_nand_rb: nand-rb-0 {
atmel,pins =
<AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
pinctrl_nand_cs: nand-cs-0 {
atmel,pins =
<AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
ebi {
pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
atmel,pins =
<AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
pinctrl_ebi_data_0_15: ebi-data-msb-0 {
atmel,pins =
<AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_ebi_addr_nand: ebi-addr-0 {
atmel,pins =
<AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
};
};
flexcom {
pinctrl_flx0_default: flx0_twi {
atmel,pins =
<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_flx4_default: flx4_spi {
atmel,pins =
<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE
AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
};
pinctrl_flx5_default: flx_uart {
atmel,pins =
<AT91_PIOA 7 AT91_PERIPH_C AT91_PINCTRL_NONE
AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE
AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE
AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_flx6_default: flx6_twi {
atmel,pins =
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
};
classd {
pinctrl_classd_default: classd {
atmel,pins =
<AT91_PIOA 24 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
AT91_PIOA 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
AT91_PIOA 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
AT91_PIOA 27 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
};
};
can0 {
pinctrl_can0_rx_tx: can0_rx_tx {
atmel,pins =
<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0 */
AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX0 */
AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN /* Enable CAN0 mux */
AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
};
};
can1 {
pinctrl_can1_rx_tx: can1_rx_tx {
atmel,pins =
<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1 RXD1 */
AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANTX1 TXD1 */
AT91_PIOD 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN /* Enable CAN1 mux */
AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_DOWN>; /* Enable CAN Transceivers */
};
};
macb0 {
pinctrl_macb0_rmii: macb0_rmii-0 {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
};
};
pwm0 {
pinctrl_pwm0_0: pwm0_0 {
atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_1: pwm0_1 {
atmel,pins = <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_2: pwm0_2 {
atmel,pins = <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
pinctrl_pwm0_3: pwm0_3 {
atmel,pins = <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
};
};
sdmmc0 {
pinctrl_sdmmc0_default: sdmmc0 {
atmel,pins =
<AT91_PIOA 17 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA17 CK periph A with pullup */
AT91_PIOA 16 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA16 CMD periph A with pullup */
AT91_PIOA 15 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA15 DAT0 periph A */
AT91_PIOA 18 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA18 DAT1 periph A with pullup */
AT91_PIOA 19 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA19 DAT2 periph A with pullup */
AT91_PIOA 20 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA20 DAT3 periph A with pullup */
};
};
gpio_keys {
pinctrl_key_gpio_default: pinctrl_key_gpio {
atmel,pins = <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
}; /* pinctrl */
&pmc {
atmel,osc-bypass;
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2 &pinctrl_pwm0_3>;
status = "disabled"; /* Conflict with leds. */
};
&sdmmc0 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
disable-wp;
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay"; /* Conflict with i2s. */
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
m25p,fast-read;
at91bootstrap@0 {
label = "qspi: at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "qspi: bootloader";
reg = <0x40000 0xc0000>;
};
bootloaderenvred@100000 {
label = "qspi: bootloader env redundant";
reg = <0x100000 0x40000>;
};
bootloaderenv@140000 {
label = "qspi: bootloader env";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "qspi: device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "qspi: kernel";
reg = <0x200000 0x600000>;
};
};
};
&shutdown_controller {
atmel,shdwc-debouncer = <976>;
status = "okay";
input@0 {
reg = <0>;
};
};
&tcb0 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioD 15 GPIO_ACTIVE_HIGH
&pioD 16 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usb2 {
status = "okay";
};

4
sys/gnu/dts/arm/at91-sama5d27_som1.dtsi
View File

@ -24,6 +24,10 @@
};
ahb {
sdmmc0: sdio-host@a0000000 {
microchip,sdcal-inverted;
};
apb {
qspi1: spi@f0024000 {
pinctrl-names = "default";

6
sys/gnu/dts/arm/at91-sama5d27_som1_ek.dts
View File

@ -131,6 +131,9 @@
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <0>, <0>;
dma-names = "tx", "rx";
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
@ -246,6 +249,9 @@
i2c1: i2c@fc028000 {
dmas = <0>, <0>;
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";

304
sys/gnu/dts/arm/at91-sama5d27_wlsom1.dtsi Normal file
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@ -0,0 +1,304 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
* Author: Eugen Hristev <eugen.hristev@microcihp.com>
*/
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/atmel-flexcom.h>
#include <dt-bindings/pinctrl/at91.h>
/ {
model = "Microchip SAMA5D27 WLSOM1";
compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <24000000>;
};
};
};
&flx1 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
uart6: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(13))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(14))>;
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
clock-names = "usart";
pinctrl-0 = <&pinctrl_flx1_default>;
pinctrl-names = "default";
};
};
&i2c0 {
pinctrl-0 = <&pinctrl_i2c0_default>;
pinctrl-names = "default";
status = "okay";
};
&i2c1 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";
mcp16502@5b {
compatible = "microchip,mcp16502";
reg = <0x5b>;
status = "okay";
lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>;
regulators {
vdd_3v3: VDD_IO {
regulator-name = "VDD_IO";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3700000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-off-in-suspend;
regulator-mode = <4>;
};
};
vddio_ddr: VDD_DDR {
regulator-name = "VDD_DDR";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1850000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1200000>;
regulator-changeable-in-suspend;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1200000>;
regulator-changeable-in-suspend;
regulator-mode = <4>;
};
};
vdd_core: VDD_CORE {
regulator-name = "VDD_CORE";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1850000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-off-in-suspend;
regulator-mode = <4>;
};
};
vdd_ddr: VDD_OTHER {
regulator-name = "VDD_OTHER";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
regulator-changeable-in-suspend;
regulator-mode = <4>;
};
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
regulator-changeable-in-suspend;
regulator-mode = <4>;
};
};
LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
};
LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-state-standby {
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
};
};
&macb0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_default>;
phy-mode = "rmii";
ethernet-phy@0 {
reg = <0x0>;
interrupt-parent = <&pioA>;
interrupts = <PIN_PB24 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_phy_irq>;
};
};
&pmc {
atmel,osc-bypass;
};
&qspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi1_default>;
status = "disabled";
qspi1_flash: spi_flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
m25p,fast-read;
status = "disabled";
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0xc0000>;
};
bootloaderenvred@100000 {
label = "bootloader env redundant";
reg = <0x100000 0x40000>;
};
bootloaderenv@140000 {
label = "bootloader env";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
};
};
&pioA {
pinctrl_flx1_default: flx1_usart_default {
pinmux = <PIN_PA24__FLEXCOM1_IO0>,
<PIN_PA23__FLEXCOM1_IO1>,
<PIN_PA25__FLEXCOM1_IO3>,
<PIN_PA26__FLEXCOM1_IO4>;
bias-disable;
};
pinctrl_i2c0_default: i2c0_default {
pinmux = <PIN_PD21__TWD0>,
<PIN_PD22__TWCK0>;
bias-disable;
};
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD19__TWD1>,
<PIN_PD20__TWCK1>;
bias-disable;
};
pinctrl_macb0_default: macb0_default {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PB24__GPIO>;
bias-disable;
};
pinctrl_qspi1_default: qspi1_default {
pinmux = <PIN_PB5__QSPI1_SCK>,
<PIN_PB6__QSPI1_CS>,
<PIN_PB7__QSPI1_IO0>,
<PIN_PB8__QSPI1_IO1>,
<PIN_PB9__QSPI1_IO2>,
<PIN_PB10__QSPI1_IO3>;
bias-pull-up;
};
};

270
sys/gnu/dts/arm/at91-sama5d27_wlsom1_ek.dts Normal file
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@ -0,0 +1,270 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
*/
/dts-v1/;
#include "at91-sama5d27_wlsom1.dtsi"
/ {
model = "Microchip SAMA5D27 WLSOM1 EK";
compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
aliases {
serial0 = &uart0; /* DBGU */
serial1 = &uart6; /* BT */
serial2 = &uart5; /* mikro BUS 2 */
serial3 = &uart3; /* mikro BUS 1 */
i2c1 = &i2c1;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
status = "okay";
sw4 {
label = "USER BUTTON";
gpios = <&pioA PIN_PB2 GPIO_ACTIVE_LOW>;
linux,code = <0x104>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led_gpio_default>;
status = "okay";
red {
label = "red";
gpios = <&pioA PIN_PA6 GPIO_ACTIVE_HIGH>;
};
green {
label = "green";
gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>;
};
blue {
label = "blue";
gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&adc {
vddana-supply = <&vdd_3v3>;
vref-supply = <&vdd_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc_default>;
status = "okay";
};
&flx0 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
uart5: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(11))>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
AT91_XDMAC_DT_PERID(12))>;
dma-names = "tx", "rx";
clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
clock-names = "usart";
pinctrl-0 = <&pinctrl_flx0_default>;
pinctrl-names = "default";
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
};
&flx1 {
status = "okay";
uart6: serial@200 {
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
};
&macb0 {
status = "okay";
};
&pioA {
/*
* There is no real pinmux for ADC, if the pin
* is not requested by another peripheral then
* the muxing is done when channel is enabled.
* Requesting pins for ADC is GPIO is
* encouraged to prevent conflicts and to
* disable bias in order to be in the same
* state when the pin is not muxed to the adc.
*/
pinctrl_adc_default: adc_default {
pinmux = <PIN_PD25__GPIO>,
<PIN_PD26__GPIO>;
bias-disable;
};
pinctrl_flx0_default: flx0_usart_default {
pinmux = <PIN_PB28__FLEXCOM0_IO0>,
<PIN_PB29__FLEXCOM0_IO1>;
bias-disable;
};
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PB2__GPIO>;
bias-pull-up;
};
pinctrl_led_gpio_default: led_gpio_default {
pinmux = <PIN_PA6__GPIO>,
<PIN_PA7__GPIO>,
<PIN_PA8__GPIO>;
bias-pull-down;
};
pinctrl_sdmmc0_default: sdmmc0_default {
cmd_data {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
<PIN_PA4__SDMMC0_DAT2>,
<PIN_PA5__SDMMC0_DAT3>;
bias-disable;
};
ck_cd_vddsel {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA11__SDMMC0_VDDSEL>,
<PIN_PA12__SDMMC0_WP>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
};
pinctrl_uart0_default: uart0_default {
pinmux = <PIN_PB26__URXD0>,
<PIN_PB27__UTXD0>;
bias-disable;
};
pinctrl_uart3_default: uart3_default {
pinmux = <PIN_PB11__URXD3>,
<PIN_PB12__UTXD3>;
bias-disable;
};
pinctrl_pwm0_default: pwm0_default {
pinmux = <PIN_PA31__PWML0>,
<PIN_PA30__PWMH0>;
bias-disable;
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PA10__GPIO>;
bias-disable;
};
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default>;
status = "okay";
};
&qspi1 {
status = "okay";
qspi1_flash: spi_flash@0 {
status = "okay";
};
};
&sdmmc0 {
bus-width = <4>;
mmc-ddr-3_3v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
};
&shutdown_controller {
atmel,shdwc-debouncer = <976>;
atmel,wakeup-rtc-timer;
input@0 {
reg = <0>;
atmel,wakeup-type = "low";
};
};
&tcb0 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0_default>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_default>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "okay";
};
&usb1 {
num-ports = <3>;
atmel,vbus-gpio = <0
&pioA PIN_PA10 GPIO_ACTIVE_HIGH
0
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
&usb2 {
phy_type = "hsic";
status = "okay";
};
&watchdog {
status = "okay";
};

109
sys/gnu/dts/arm/at91-smartkiz.dts Normal file
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@ -0,0 +1,109 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017-2018 Overkiz SAS
* Author: Mickael Gardet <m.gardet@overkiz.com>
* Kévin Raymond <k.raymond@overkiz.com>
* Dorian Rocipon <d.rocipon@overkiz.com>
*/
/dts-v1/;
#include "at91-kizboxmini-common.dtsi"
/ {
model = "Overkiz SmartKiz";
compatible = "overkiz,smartkiz", "atmel,at91sam9g25",
"atmel,at91sam9x5", "atmel,at91sam9";
clocks {
adc_op_clk {
status = "okay";
};
};
aliases {
serial5 = &uart0;
};
pio_keys {
hk_reset {
label = "HK_RESET";
gpios = <&pioC 13 GPIO_ACTIVE_HIGH>;
};
power_rf {
label = "POWER_RF";
gpios = <&pioA 20 GPIO_ACTIVE_HIGH>;
};
power_wifi {
label = "POWER_WIFI";
gpios = <&pioA 21 GPIO_ACTIVE_HIGH>;
};
};
};
&pinctrl {
i2c1 {
pinctrl_i2c1: i2c1-0 {
atmel,pins =
<AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_PULL_UP
AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;
};
};
adc0 {
pinctrl_adc0_ad0: adc0_ad0-0 {
/* pull-up disable */
atmel,pins = <AT91_PIOB 11 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad5: adc0_ad5-0 {
/* pull-up disable */
atmel,pins = <AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad6: adc0_ad6-0 {
/* pull-up disable */
atmel,pins = <AT91_PIOB 17 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_adc0_ad11: adc0_ad11-0 {
/* pull-up disable */
atmel,pins = <AT91_PIOB 10 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
};
};
&i2c1 {
dmas = <0>, <0>;
pinctrl-0 = <&pinctrl_i2c1>;
status = "disabled";
};
&macb0 {
status = "disabled";
};
&rtc {
status = "okay";
};
&leds {
blue {
status = "okay";
};
};
&adc0 {
atmel,adc-vref = <2500>;
pinctrl-names = "default";
pinctrl-0 = <
&pinctrl_adc0_ad0
&pinctrl_adc0_ad5
&pinctrl_adc0_ad6
&pinctrl_adc0_ad11
>;
atmel,adc-channels-used = <0x0861>;
status = "okay";
};
&uart0 {
status = "okay";
};

16
sys/gnu/dts/arm/at91sam9260.dtsi
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@ -187,7 +187,7 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE
<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -221,7 +221,7 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE
<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -239,7 +239,7 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -257,7 +257,7 @@
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
<AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE
<AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -275,7 +275,7 @@
uart0 {
pinctrl_uart0: uart0-0 {
atmel,pins =
<AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE
<AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP
AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
};
};
@ -283,7 +283,7 @@
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE
<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
};
@ -738,7 +738,7 @@
status = "disabled";
};
watchdog@fffffd40 {
watchdog: watchdog@fffffd40 {
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
@ -793,7 +793,7 @@
};
};
i2c-gpio-0 {
i2c_gpio0: i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
&pioA 24 GPIO_ACTIVE_HIGH /* scl */

6
sys/gnu/dts/arm/at91sam9261.dtsi
View File

@ -329,7 +329,7 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
<AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -347,7 +347,7 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
<AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -365,7 +365,7 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
<AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};

6
sys/gnu/dts/arm/at91sam9263.dtsi
View File

@ -183,7 +183,7 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
<AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE
<AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -201,7 +201,7 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE
<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -219,7 +219,7 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
<AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE
<AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};

8
sys/gnu/dts/arm/at91sam9g45.dtsi
View File

@ -556,7 +556,7 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -574,7 +574,7 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE
<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -592,7 +592,7 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE
<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -610,7 +610,7 @@
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE
<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};

8
sys/gnu/dts/arm/at91sam9rl.dtsi
View File

@ -682,7 +682,7 @@
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
<AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -721,7 +721,7 @@
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -744,7 +744,7 @@
usart2 {
pinctrl_usart2: usart2-0 {
atmel,pins =
<AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
@ -767,7 +767,7 @@
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};

3
sys/gnu/dts/arm/bcm2711-rpi-4-b.dts
View File

@ -21,6 +21,7 @@
aliases {
ethernet0 = &genet;
pcie0 = &pcie0;
};
leds {
@ -31,6 +32,8 @@
pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
linux,default-trigger = "default-on";
};
};

82
sys/gnu/dts/arm/bcm2711.dtsi
View File

@ -12,26 +12,6 @@
interrupt-parent = <&gicv2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <1>;
ranges;
/*
* arm64 reserves the CMA by default somewhere in ZONE_DMA32,
* that's not good enough for the BCM2711 as some devices can
* only address the lower 1G of memory (ZONE_DMA).
*/
linux,cma {
compatible = "shared-dma-pool";
size = <0x2000000>; /* 32MB */
alloc-ranges = <0x0 0x00000000 0x40000000>;
reusable;
linux,cma-default;
};
};
soc {
/*
* Defined ranges:
@ -66,6 +46,17 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
avs_monitor: avs-monitor@7d5d2000 {
compatible = "brcm,bcm2711-avs-monitor",
"syscon", "simple-mfd";
reg = <0x7d5d2000 0xf00>;
thermal: thermal {
compatible = "brcm,bcm2711-thermal";
#thermal-sensor-cells = <0>;
};
};
dma: dma@7e007000 {
compatible = "brcm,bcm2835-dma";
reg = <0x7e007000 0xb00>;
@ -112,10 +103,8 @@
};
rng@7e104000 {
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
/* RNG is incompatible with brcm,bcm2835-rng */
status = "disabled";
compatible = "brcm,bcm2711-rng200";
reg = <0x7e104000 0x28>;
};
uart2: serial@7e201400 {
@ -331,7 +320,36 @@
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>;
ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
<0x6 0x00000000 0x6 0x00000000 0x40000000>;
pcie0: pcie@7d500000 {
compatible = "brcm,bcm2711-pcie";
reg = <0x0 0x7d500000 0x9310>;
device_type = "pci";
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "msi";
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
IRQ_TYPE_LEVEL_HIGH>;
msi-controller;
msi-parent = <&pcie0>;
ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
0x0 0x04000000>;
/*
* The wrapper around the PCIe block has a bug
* preventing it from accessing beyond the first 3GB of
* memory.
*/
dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
0x0 0xc0000000>;
brcm,enable-ssc;
};
genet: ethernet@7d580000 {
compatible = "brcm,bcm2711-genet-v5";
@ -363,6 +381,7 @@
&cpu_thermal {
coefficients = <(-487) 410040>;
thermal-sensors = <&thermal>;
};
&dsi0 {
@ -828,6 +847,19 @@
};
};
&rmem {
#address-cells = <2>;
};
&cma {
/*
* arm64 reserves the CMA by default somewhere in ZONE_DMA32,
* that's not good enough for the BCM2711 as some devices can
* only address the lower 1G of memory (ZONE_DMA).
*/
alloc-ranges = <0x0 0x00000000 0x40000000>;
};
&i2c0 {
compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

6
sys/gnu/dts/arm/bcm2835-common.dtsi
View File

@ -70,6 +70,12 @@
system-power-controller;
};
rng@7e104000 {
compatible = "brcm,bcm2835-rng";
reg = <0x7e104000 0x10>;
interrupts = <2 29>;
};
pixelvalve@7e206000 {
compatible = "brcm,bcm2835-pixelvalve0";
reg = <0x7e206000 0x100>;

1
sys/gnu/dts/arm/bcm2835-rpi-zero-w.dts
View File

@ -112,6 +112,7 @@
&sdhci {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>;
bus-width = <4>;
mmc-pwrseq = <&wifi_pwrseq>;

1
sys/gnu/dts/arm/bcm2835-rpi.dtsi
View File

@ -15,6 +15,7 @@
firmware: firmware {
compatible = "raspberrypi,bcm2835-firmware", "simple-bus";
mboxes = <&mailbox>;
dma-ranges;
};
power: power {

2
sys/gnu/dts/arm/bcm2837-rpi-3-a-plus.dts
View File

@ -26,6 +26,8 @@
pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
linux,default-trigger = "default-on";
};
};
};

2
sys/gnu/dts/arm/bcm2837-rpi-3-b-plus.dts
View File

@ -27,6 +27,8 @@
pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
linux,default-trigger = "default-on";
};
};

19
sys/gnu/dts/arm/bcm283x.dtsi
View File

@ -30,6 +30,19 @@
stdout-path = "serial0:115200n8";
};
rmem: reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
cma: linux,cma {
compatible = "shared-dma-pool";
size = <0x4000000>; /* 64MB */
reusable;
linux,cma-default;
};
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
@ -84,12 +97,6 @@
<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
};
rng@7e104000 {
compatible = "brcm,bcm2835-rng";
reg = <0x7e104000 0x10>;
interrupts = <2 29>;
};
mailbox: mailbox@7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;

15
sys/gnu/dts/arm/bcm958625hr.dts
View File

@ -55,18 +55,9 @@
priority = <200>;
};
/* Hardware I2C block cannot do more than 63 bytes per transfer,
* which would prevent reading from a SFP's EEPROM (256 byte).
*/
i2c1: i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpioa 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpioa 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
sfp: sfp {
compatible = "sff,sfp";
i2c-bus = <&i2c1>;
i2c-bus = <&i2c0>;
mod-def0-gpios = <&gpioa 28 GPIO_ACTIVE_LOW>;
los-gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>;
tx-fault-gpios = <&gpioa 30 GPIO_ACTIVE_HIGH>;
@ -74,6 +65,10 @@
};
};
&i2c0 {
status = "okay";
};
&amac0 {
status = "okay";
};

10
sys/gnu/dts/arm/dm3725.dtsi Normal file
View File

@ -0,0 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2020 André Hentschel <nerv@dawncrow.de>
*/
#include "omap36xx.dtsi"
&sgx_module {
status = "disabled";
};

4
sys/gnu/dts/arm/dm8148-evm.dts
View File

@ -24,12 +24,12 @@
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
};
&cpsw_emac1 {
phy-handle = <&ethphy1>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
};
&davinci_mdio {

4
sys/gnu/dts/arm/dm8148-t410.dts
View File

@ -33,12 +33,12 @@
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
};
&cpsw_emac1 {
phy-handle = <&ethphy1>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
};
&davinci_mdio {

4
sys/gnu/dts/arm/dra62x-j5eco-evm.dts
View File

@ -24,12 +24,12 @@
&cpsw_emac0 {
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
};
&cpsw_emac1 {
phy-handle = <&ethphy1>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
};
&davinci_mdio {

2
sys/gnu/dts/arm/dra7-evm-common.dtsi
View File

@ -4,7 +4,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/clock/ti-dra7-atl.h>
#include <dt-bindings/input/input.h>
/ {

4
sys/gnu/dts/arm/dra7-evm.dts
View File

@ -61,10 +61,10 @@
regulator-max-microvolt = <1800000>;
};
evm_3v3: fixedregulator-evm3v3 {
vsys_3v3: fixedregulator-vsys3v3 {
/* Output of Cntlr A of TPS43351-Q1 on dra7-evm */
compatible = "regulator-fixed";
regulator-name = "evm_3v3";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;

130
sys/gnu/dts/arm/dra7-l4.dtsi
View File

@ -186,7 +186,6 @@
target-module@56000 { /* 0x4a056000, ap 9 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "dma_system";
reg = <0x56000 0x4>,
<0x5602c 0x4>,
<0x56028 0x4>;
@ -212,7 +211,7 @@
ranges = <0x0 0x56000 0x1000>;
sdma: dma-controller@0 {
compatible = "ti,omap4430-sdma";
compatible = "ti,omap4430-sdma", "ti,omap-sdma";
reg = <0x0 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
@ -234,7 +233,6 @@
target-module@80000 { /* 0x4a080000, ap 13 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "ocp2scp1";
reg = <0x80000 0x4>,
<0x80010 0x4>,
<0x80014 0x4>;
@ -302,7 +300,6 @@
target-module@90000 { /* 0x4a090000, ap 59 42.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "ocp2scp3";
reg = <0x90000 0x4>,
<0x90010 0x4>,
<0x90014 0x4>;
@ -394,7 +391,6 @@
target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_mpu";
reg = <0xd9038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
@ -414,7 +410,6 @@
target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
ti,hwmods = "smartreflex_core";
reg = <0xdd038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
@ -471,7 +466,6 @@
target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "spinlock";
reg = <0xf6000 0x4>,
<0xf6010 0x4>,
<0xf6014 0x4>;
@ -1233,7 +1227,6 @@
target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer9";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
@ -1748,7 +1741,6 @@
target-module@78000 { /* 0x48078000, ap 39 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "elm";
reg = <0x78000 0x4>,
<0x78010 0x4>,
<0x78014 0x4>;
@ -1842,7 +1834,6 @@
target-module@86000 { /* 0x48086000, ap 41 5e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer10";
reg = <0x86000 0x4>,
<0x86010 0x4>;
reg-names = "rev", "sysc";
@ -1870,7 +1861,6 @@
target-module@88000 { /* 0x48088000, ap 43 66.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer11";
reg = <0x88000 0x4>,
<0x88010 0x4>;
reg-names = "rev", "sysc";
@ -2044,6 +2034,37 @@
<0x00001000 0x000a5000 0x00001000>;
};
des_target: target-module@a5000 { /* 0x480a5000 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0xa5030 0x4>,
<0xa5034 0x4>,
<0xa5038 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa5000 0x00001000>;
des: des@0 {
compatible = "ti,omap4-des";
reg = <0 0xa0>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
};
target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
compatible = "ti,sysc";
status = "disabled";
@ -2490,7 +2511,6 @@
target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss0";
reg = <0x3e000 0x4>,
<0x3e004 0x4>;
reg-names = "rev", "sysc";
@ -2537,7 +2557,6 @@
target-module@40000 { /* 0x48440000, ap 27 38.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss1";
reg = <0x40000 0x4>,
<0x40004 0x4>;
reg-names = "rev", "sysc";
@ -2584,7 +2603,6 @@
target-module@42000 { /* 0x48442000, ap 29 20.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "epwmss2";
reg = <0x42000 0x4>,
<0x42004 0x4>;
reg-names = "rev", "sysc";
@ -3326,7 +3344,6 @@
target-module@20000 { /* 0x48820000, ap 5 08.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer5";
reg = <0x20000 0x4>,
<0x20010 0x4>;
reg-names = "rev", "sysc";
@ -3354,7 +3371,6 @@
target-module@22000 { /* 0x48822000, ap 7 24.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer6";
reg = <0x22000 0x4>,
<0x22010 0x4>;
reg-names = "rev", "sysc";
@ -3382,7 +3398,6 @@
target-module@24000 { /* 0x48824000, ap 9 26.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer7";
reg = <0x24000 0x4>,
<0x24010 0x4>;
reg-names = "rev", "sysc";
@ -3410,7 +3425,6 @@
target-module@26000 { /* 0x48826000, ap 11 0c.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer8";
reg = <0x26000 0x4>,
<0x26010 0x4>;
reg-names = "rev", "sysc";
@ -3438,7 +3452,6 @@
target-module@28000 { /* 0x48828000, ap 13 16.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer13";
reg = <0x28000 0x4>,
<0x28010 0x4>;
reg-names = "rev", "sysc";
@ -3461,12 +3474,12 @@
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
};
target-module@2a000 { /* 0x4882a000, ap 15 10.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer14";
reg = <0x2a000 0x4>,
<0x2a010 0x4>;
reg-names = "rev", "sysc";
@ -3489,12 +3502,12 @@
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
};
target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer15";
reg = <0x2c000 0x4>,
<0x2c010 0x4>;
reg-names = "rev", "sysc";
@ -3517,12 +3530,12 @@
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
};
target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer16";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
@ -3545,6 +3558,7 @@
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
};
};
@ -4166,35 +4180,88 @@
};
target-module@170000 { /* 0x48970000, ap 21 0a.0 */
compatible = "ti,sysc";
status = "disabled";
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x170010 0x4>;
reg-names = "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x170000 0x10000>;
status = "disabled";
};
target-module@190000 { /* 0x48990000, ap 23 2e.0 */
compatible = "ti,sysc";
status = "disabled";
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x190010 0x4>;
reg-names = "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x190000 0x10000>;
status = "disabled";
};
target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
compatible = "ti,sysc";
status = "disabled";
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x1b0000 0x4>,
<0x1b0010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1b0000 0x10000>;
status = "disabled";
};
target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */
compatible = "ti,sysc";
status = "disabled";
target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x1d0010 0x4>;
reg-names = "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1d0000 0x10000>;
vpe: vpe@0 {
compatible = "ti,dra7-vpe";
reg = <0x0000 0x120>,
<0x0700 0x80>,
<0x5700 0x18>,
<0xd000 0x400>;
reg-names = "vpe_top",
"sc",
"csc",
"vpdma";
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};
@ -4422,7 +4489,6 @@
target-module@0 { /* 0x4ae20000, ap 19 08.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
ti,hwmods = "timer12";
reg = <0x0 0x4>,
<0x10 0x4>;
reg-names = "rev", "sysc";

277
sys/gnu/dts/arm/dra7.dtsi
View File

@ -148,6 +148,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0xc0000000>;
dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
ti,hwmods = "l3_main_1", "l3_main_2";
reg = <0x0 0x44000000 0x0 0x1000000>,
<0x0 0x45000000 0x0 0x1000>;
@ -184,6 +185,7 @@
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
num-lanes = <1>;
@ -238,6 +240,7 @@
device_type = "pci";
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x30013000 0x13000 0 0xffed000>;
dma-ranges = <0x02000000 0x0 0x00000000 0x00000000 0x1 0x00000000>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
num-lanes = <1>;
@ -377,44 +380,120 @@
ti,hwmods = "dmm";
};
mmu0_dsp1: mmu@40d01000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x40d01000 0x100>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu0_dsp1";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x0>;
status = "disabled";
target-module@40d01000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x40d01000 0x4>,
<0x40d01010 0x4>,
<0x40d01014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_dsp1 1>;
reset-names = "rstctrl";
ranges = <0x0 0x40d01000 0x1000>;
#size-cells = <1>;
#address-cells = <1>;
mmu0_dsp1: mmu@0 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x0>;
};
};
mmu1_dsp1: mmu@40d02000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x40d02000 0x100>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu1_dsp1";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x1>;
status = "disabled";
target-module@40d02000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x40d02000 0x4>,
<0x40d02010 0x4>,
<0x40d02014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_dsp1 1>;
reset-names = "rstctrl";
ranges = <0x0 0x40d02000 0x1000>;
#size-cells = <1>;
#address-cells = <1>;
mmu1_dsp1: mmu@0 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp1_system 0x1>;
};
};
mmu_ipu1: mmu@58882000 {
compatible = "ti,dra7-iommu";
reg = <0x58882000 0x100>;
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_ipu1";
#iommu-cells = <0>;
ti,iommu-bus-err-back;
status = "disabled";
target-module@58882000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x58882000 0x4>,
<0x58882010 0x4>,
<0x58882014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_ipu 2>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x58882000 0x100>;
mmu_ipu1: mmu@0 {
compatible = "ti,dra7-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,iommu-bus-err-back;
};
};
mmu_ipu2: mmu@55082000 {
compatible = "ti,dra7-iommu";
reg = <0x55082000 0x100>;
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu_ipu2";
#iommu-cells = <0>;
ti,iommu-bus-err-back;
status = "disabled";
target-module@55082000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x55082000 0x4>,
<0x55082010 0x4>,
<0x55082014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_core 2>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x55082000 0x100>;
mmu_ipu2: mmu@0 {
compatible = "ti,dra7-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,iommu-bus-err-back;
};
};
abb_mpu: regulator-abb-mpu {
@ -597,6 +676,24 @@
status = "disabled";
};
target-module@56000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x56000000 0x2000000>;
};
crossbar_mpu: crossbar@4a002a48 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
@ -652,48 +749,96 @@
};
};
aes1: aes@4b500000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes1";
reg = <0x4b500000 0xa0>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
aes1_target: target-module@4b500000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4b500080 0x4>,
<0x4b500084 0x4>,
<0x4b500088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l4sec_clkdm */
clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b500000 0x1000>;
aes1: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
};
aes2: aes@4b700000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes2";
reg = <0x4b700000 0xa0>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
aes2_target: target-module@4b700000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4b700080 0x4>,
<0x4b700084 0x4>,
<0x4b700088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): per_pwrdm, l4sec_clkdm */
clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b700000 0x1000>;
aes2: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
};
des: des@480a5000 {
compatible = "ti,omap4-des";
ti,hwmods = "des";
reg = <0x480a5000 0xa0>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
sham_target: target-module@4b101000 {
compatible = "ti,sysc-omap3-sham", "ti,sysc";
reg = <0x4b101100 0x4>,
<0x4b101110 0x4>,
<0x4b101114 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
clock-names = "fck";
};
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b101000 0x1000>;
sham: sham@53100000 {
compatible = "ti,omap5-sham";
ti,hwmods = "sham";
reg = <0x4b101000 0x300>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 119 0>;
dma-names = "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
sham: sham@0 {
compatible = "ti,omap5-sham";
reg = <0 0x300>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 119 0>;
dma-names = "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
};
opp_supply_mpu: opp-supply@4a003b20 {

33
sys/gnu/dts/arm/dra72-evm-common.dtsi
View File

@ -6,7 +6,7 @@
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clk/ti-dra7-atl.h>
#include <dt-bindings/clock/ti-dra7-atl.h>
/ {
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
@ -187,6 +187,12 @@
gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
clk_ov5640_fixed: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&dra7_pmx_core {
@ -269,6 +275,23 @@
line-name = "vin6_sel_s0";
};
};
ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&clk_ov5640_fixed>;
clock-names = "xclk";
port {
csi2_cam0: endpoint {
remote-endpoint = <&csi2_phy0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&uart1 {
@ -580,3 +603,11 @@
&pcie1_rc {
status = "okay";
};
&csi2_0 {
csi2_phy0: endpoint {
remote-endpoint = <&csi2_cam0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};

42
sys/gnu/dts/arm/dra72x.dtsi
View File

@ -17,6 +17,48 @@
};
};
&l4_per2 {
target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5b000 0x4>,
<0x5b010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x5b000 0x1000>;
cal: cal@0 {
compatible = "ti,dra72-cal";
reg = <0x0000 0x400>,
<0x0800 0x40>,
<0x0900 0x40>;
reg-names = "cal_top",
"cal_rx_core0",
"cal_rx_core1";
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
ti,camerrx-control = <&scm_conf 0xE94>;
ports {
#address-cells = <1>;
#size-cells = <0>;
csi2_0: port@0 {
reg = <0>;
};
csi2_1: port@1 {
reg = <1>;
};
};
};
};
};
&dss {
reg = <0x58000000 0x80>,
<0x58004054 0x4>,

71
sys/gnu/dts/arm/dra74x.dtsi
View File

@ -66,24 +66,63 @@
};
};
mmu0_dsp2: mmu@41501000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x41501000 0x100>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu0_dsp2";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x0>;
status = "disabled";
target-module@41501000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x41501000 0x4>,
<0x41501010 0x4>,
<0x41501014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_dsp2 1>;
reset-names = "rstctrl";
ranges = <0x0 0x41501000 0x1000>;
#size-cells = <1>;
#address-cells = <1>;
mmu0_dsp2: mmu@0 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x0>;
};
};
mmu1_dsp2: mmu@41502000 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x41502000 0x100>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmu1_dsp2";
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x1>;
status = "disabled";
target-module@41502000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x41502000 0x4>,
<0x41502010 0x4>,
<0x41502014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_dsp2 1>;
reset-names = "rstctrl";
ranges = <0x0 0x41502000 0x1000>;
#size-cells = <1>;
#address-cells = <1>;
mmu1_dsp2: mmu@0 {
compatible = "ti,dra7-dsp-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,syscon-mmuconfig = <&dsp2_system 0x1>;
};
};
};
};

101
sys/gnu/dts/arm/dra76-evm.dts
View File

@ -13,6 +13,13 @@
model = "TI DRA762 EVM";
compatible = "ti,dra76-evm", "ti,dra762", "ti,dra7";
aliases {
display0 = &hdmi0;
sound0 = &sound0;
sound1 = &hdmi;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
@ -116,6 +123,54 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
clk_ov5640_fixed: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
hdmi0: connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
tpd12s015: encoder {
compatible = "ti,tpd12s015";
gpios = <&gpio7 30 GPIO_ACTIVE_HIGH>, /* gpio7_30, CT CP HPD */
<&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&i2c1 {
@ -317,6 +372,27 @@
};
};
&i2c5 {
status = "okay";
clock-frequency = <400000>;
ov5640@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
clocks = <&clk_ov5640_fixed>;
clock-names = "xclk";
port {
csi2_cam0: endpoint {
remote-endpoint = <&csi2_phy0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&cpu0 {
vdd-supply = <&buck10_reg>;
};
@ -411,6 +487,23 @@
phy-supply = <&ldo3_reg>;
};
&dss {
status = "ok";
vdda_video-supply = <&ldo5_reg>;
};
&hdmi {
status = "ok";
vdda-supply = <&ldo1_reg>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};
&qspi {
spi-max-frequency = <96000000>;
m25p80@0 {
@ -447,3 +540,11 @@
max-bitrate = <5000000>;
};
};
&csi2_0 {
csi2_phy0: endpoint {
remote-endpoint = <&csi2_cam0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};

47
sys/gnu/dts/arm/dra76x.dtsi
View File

@ -41,6 +41,48 @@
};
&l4_per3 {
target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x1b0000 0x4>,
<0x1b0010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1b0000 0x10000>;
cal: cal@0 {
compatible = "ti,dra76-cal";
reg = <0x0000 0x400>,
<0x0800 0x40>,
<0x0900 0x40>;
reg-names = "cal_top",
"cal_rx_core0",
"cal_rx_core1";
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
ti,camerrx-control = <&scm_conf 0x6dc>;
ports {
#address-cells = <1>;
#size-cells = <0>;
csi2_0: port@0 {
reg = <0>;
};
csi2_1: port@1 {
reg = <1>;
};
};
};
};
};
/* MCAN interrupts are hard-wired to irqs 67, 68 */
&crossbar_mpu {
ti,irqs-skip = <10 67 68 133 139 140>;
@ -86,3 +128,8 @@
&usb4_tm {
status = "disabled";
};
&mmc3 {
/* dra76x is not affected by i887 */
max-frequency = <96000000>;
};

58
sys/gnu/dts/arm/dra7xx-clocks.dtsi
View File

@ -796,16 +796,6 @@
clock-div = <1>;
};
ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
ti,bit-shift = <24>;
reg = <0x0520>;
assigned-clocks = <&ipu1_gfclk_mux>;
assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
@ -1564,6 +1554,8 @@
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
ipu_clkctrl: ipu-clkctrl@50 {
@ -1591,10 +1583,10 @@
rtc_cm: rtc-cm@700 {
compatible = "ti,omap4-cm";
reg = <0x700 0x100>;
reg = <0x700 0x60>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x700 0x100>;
ranges = <0 0x700 0x60>;
rtc_clkctrl: rtc-clkctrl@20 {
compatible = "ti,clkctrl";
@ -1603,6 +1595,20 @@
};
};
vpe_cm: vpe-cm@760 {
compatible = "ti,omap4-cm";
reg = <0x760 0xc>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x760 0xc>;
vpe_clkctrl: vpe-clkctrl@0 {
compatible = "ti,clkctrl";
reg = <0x0 0xc>;
#clock-cells = <2>;
};
};
};
&cm_core {
@ -1720,6 +1726,20 @@
};
};
cam_cm: cam-cm@1000 {
compatible = "ti,omap4-cm";
reg = <0x1000 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000 0x100>;
cam_clkctrl: cam-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x2c>;
#clock-cells = <2>;
};
};
dss_cm: dss-cm@1100 {
compatible = "ti,omap4-cm";
reg = <0x1100 0x100>;
@ -1734,6 +1754,20 @@
};
};
gpu_cm: gpu-cm@1200 {
compatible = "ti,omap4-cm";
reg = <0x1200 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1200 0x100>;
gpu_clkctrl: gpu-clkctrl@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
l3init_cm: l3init-cm@1300 {
compatible = "ti,omap4-cm";
reg = <0x1300 0x100>;

3
sys/gnu/dts/arm/e60k02.dtsi
View File

@ -48,7 +48,8 @@
};
};
memory {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};

4
sys/gnu/dts/arm/exynos3250.dtsi
View File

@ -145,12 +145,12 @@
#size-cells = <1>;
ranges = <0 0x02020000 0x40000>;
smp-sysram@0 {
smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
smp-sysram@3f000 {
smp-sram@3f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x3f000 0x1000>;
};

6
sys/gnu/dts/arm/exynos4210-universal_c210.dts
View File

@ -590,16 +590,16 @@
};
&sysram {
smp-sysram@0 {
smp-sram@0 {
status = "disabled";
};
smp-sysram@5000 {
smp-sram@5000 {
compatible = "samsung,exynos4210-sysram";
reg = <0x5000 0x1000>;
};
smp-sysram@1f000 {
smp-sram@1f000 {
status = "disabled";
};
};

4
sys/gnu/dts/arm/exynos4210.dtsi
View File

@ -79,12 +79,12 @@
#size-cells = <1>;
ranges = <0 0x02020000 0x20000>;
smp-sysram@0 {
smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
smp-sysram@1f000 {
smp-sram@1f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x1f000 0x1000>;
};

9
sys/gnu/dts/arm/exynos4412-galaxy-s3.dtsi
View File

@ -33,7 +33,7 @@
};
};
lcd_vdd3_reg: voltage-regulator-6 {
lcd_vdd3_reg: voltage-regulator-7 {
compatible = "regulator-fixed";
regulator-name = "LCD_VDD_2.2V";
regulator-min-microvolt = <2200000>;
@ -42,7 +42,7 @@
enable-active-high;
};
ps_als_reg: voltage-regulator-7 {
ps_als_reg: voltage-regulator-8 {
compatible = "regulator-fixed";
regulator-name = "LED_A_3.0V";
regulator-min-microvolt = <3000000>;
@ -168,3 +168,8 @@
vdda-supply = <&ldo17_reg>;
status = "okay";
};
&touchkey_reg {
gpio = <&gpm0 0 GPIO_ACTIVE_HIGH>;
status = "okay";
};

29
sys/gnu/dts/arm/exynos4412-midas.dtsi
View File

@ -13,6 +13,7 @@
#include "exynos4412.dtsi"
#include "exynos4412-ppmu-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/maxim,max77686.h>
#include <dt-bindings/pinctrl/samsung.h>
@ -92,6 +93,15 @@
enable-active-high;
};
touchkey_reg: voltage-regulator-6 {
compatible = "regulator-fixed";
regulator-name = "LED_VDD_3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
status = "disabled";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@ -197,6 +207,25 @@
};
};
i2c-gpio-4 {
compatible = "i2c-gpio";
sda-gpios = <&gpl0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpl0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <2>;
#address-cells = <1>;
#size-cells = <0>;
touchkey@20 {
compatible = "cypress,midas-touchkey";
reg = <0x20>;
vdd-supply = <&touchkey_reg>;
vcc-supply = <&ldo5_reg>;
interrupt-parent = <&gpj0>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
linux,keycodes = <KEY_BACK KEY_MENU>;
};
};
i2c-mhl {
compatible = "i2c-gpio";
gpios = <&gpf0 4 GPIO_ACTIVE_HIGH>, <&gpf0 6 GPIO_ACTIVE_HIGH>;

7
sys/gnu/dts/arm/exynos4412-n710x.dts
View File

@ -13,7 +13,7 @@
/* bootargs are passed in by bootloader */
cam_vdda_reg: voltage-regulator-6 {
cam_vdda_reg: voltage-regulator-7 {
compatible = "regulator-fixed";
regulator-name = "CAM_SENSOR_CORE_1.2V";
regulator-min-microvolt = <1200000>;
@ -73,3 +73,8 @@
vdda-supply = <&cam_vdda_reg>;
status = "okay";
};
&touchkey_reg {
gpio = <&gpm0 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};

2
sys/gnu/dts/arm/exynos4412-odroid-common.dtsi
View File

@ -267,7 +267,7 @@
intn-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
connect-gpios = <&gpx3 4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
initial-mode = <1>;
};

25
sys/gnu/dts/arm/exynos4412-tiny4412.dts
View File

@ -66,6 +66,31 @@
clock-frequency = <24000000>;
};
};
panel {
compatible = "innolux,at070tn92";
port {
panel_input: endpoint {
remote-endpoint = <&lcdc_output>;
};
};
};
};
&fimd {
pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port@3 {
reg = <3>;
lcdc_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};
&rtc {

4
sys/gnu/dts/arm/exynos4412.dtsi
View File

@ -195,12 +195,12 @@
#size-cells = <1>;
ranges = <0 0x02020000 0x40000>;
smp-sysram@0 {
smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
smp-sysram@2f000 {
smp-sram@2f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x2f000 0x1000>;
};

2
sys/gnu/dts/arm/exynos5.dtsi
View File

@ -36,7 +36,7 @@
ranges;
chipid: chipid@10000000 {
compatible = "samsung,exynos4210-chipid", "syscon";
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};

4
sys/gnu/dts/arm/exynos5250-arndale.dts
View File

@ -15,7 +15,7 @@
#include "exynos5250.dtsi"
/ {
model = "Insignal Arndale evaluation board based on EXYNOS5250";
model = "Insignal Arndale evaluation board based on Exynos5250";
compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5";
memory@40000000 {
@ -154,7 +154,7 @@
compatible = "smsc,usb3503a";
reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
connect-gpios = <&gpd1 7 GPIO_ACTIVE_LOW>;
connect-gpios = <&gpd1 7 GPIO_ACTIVE_HIGH>;
};
};

4
sys/gnu/dts/arm/exynos5250-smdk5250.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG SMDK5250 board device tree source
* Samsung SMDK5250 board device tree source
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@ -12,7 +12,7 @@
#include "exynos5250.dtsi"
/ {
model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
model = "Samsung SMDK5250 board based on Exynos5250";
compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5";
aliases {

12
sys/gnu/dts/arm/exynos5250.dtsi
View File

@ -1,16 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5250 SoC device tree source
* Samsung Exynos5250 SoC device tree source
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
* EXYNOS5250 based board files can include this file and provide
* Samsung Exynos5250 SoC device nodes are listed in this file.
* Exynos5250 based board files can include this file and provide
* values for board specfic bindings.
*
* Note: This file does not include device nodes for all the controllers in
* EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
* Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
* additional nodes can be added to this file.
*/
@ -171,12 +171,12 @@
#size-cells = <1>;
ranges = <0 0x02020000 0x30000>;
smp-sysram@0 {
smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
smp-sysram@2f000 {
smp-sram@2f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x2f000 0x1000>;
};

4
sys/gnu/dts/arm/exynos5260-xyref5260.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG XYREF5260 board device tree source
* Samsung XYREF5260 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@ -10,7 +10,7 @@
#include "exynos5260.dtsi"
/ {
model = "SAMSUNG XYREF5260 board based on EXYNOS5260";
model = "Samsung XYREF5260 board based on Exynos5260";
compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5";
memory@20000000 {

2
sys/gnu/dts/arm/exynos5260.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5260 SoC device tree source
* Samsung Exynos5260 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com

2
sys/gnu/dts/arm/exynos5410-odroidxu.dts
View File

@ -170,7 +170,7 @@
intn-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
connect-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpx1 4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpx1 4 GPIO_ACTIVE_LOW>;
initial-mode = <1>;
clock-names = "refclk";

4
sys/gnu/dts/arm/exynos5410-smdk5410.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG SMDK5410 board device tree source
* Samsung SMDK5410 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@ -10,7 +10,7 @@
#include "exynos5410.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Samsung SMDK5410 board based on EXYNOS5410";
model = "Samsung SMDK5410 board based on Exynos5410";
compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
memory@40000000 {

6
sys/gnu/dts/arm/exynos5410.dtsi
View File

@ -1,12 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5410 SoC device tree source
* Samsung Exynos5410 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
* EXYNOS5410 based board files can include this file and provide
* Samsung Exynos5410 SoC device nodes are listed in this file.
* Exynos5410 based board files can include this file and provide
* values for board specfic bindings.
*/

2
sys/gnu/dts/arm/exynos5420-arndale-octa.dts
View File

@ -15,7 +15,7 @@
#include <dt-bindings/clock/samsung,s2mps11.h>
/ {
model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
model = "Insignal Arndale Octa evaluation board based on Exynos5420";
compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5";
memory@20000000 {

2
sys/gnu/dts/arm/exynos5420-cpus.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5420 SoC cpu device tree source
* Samsung Exynos5420 SoC cpu device tree source
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com

4
sys/gnu/dts/arm/exynos5420-smdk5420.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG SMDK5420 board device tree source
* Samsung SMDK5420 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
@ -12,7 +12,7 @@
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Samsung SMDK5420 board based on EXYNOS5420";
model = "Samsung SMDK5420 board based on Exynos5420";
compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5";
memory@20000000 {

339
sys/gnu/dts/arm/exynos5420.dtsi
View File

@ -1,12 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5420 SoC device tree source
* Samsung Exynos5420 SoC device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS5420 SoC device nodes are listed in this file.
* EXYNOS5420 based board files can include this file and provide
* Samsung Exynos5420 SoC device nodes are listed in this file.
* Exynos5420 based board files can include this file and provide
* values for board specfic bindings.
*/
@ -48,62 +48,62 @@
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1250000>;
opp-microvolt = <1250000 1250000 1500000>;
clock-latency-ns = <140000>;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <1212500>;
opp-microvolt = <1212500 1212500 1500000>;
clock-latency-ns = <140000>;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <1175000>;
opp-microvolt = <1175000 1175000 1500000>;
clock-latency-ns = <140000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1137500>;
opp-microvolt = <1137500 1137500 1500000>;
clock-latency-ns = <140000>;
};
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1112500>;
opp-microvolt = <1112500 1112500 1500000>;
clock-latency-ns = <140000>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1062500>;
opp-microvolt = <1062500 1062500 1500000>;
clock-latency-ns = <140000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1037500>;
opp-microvolt = <1037500 1037500 1500000>;
clock-latency-ns = <140000>;
};
opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1012500>;
opp-microvolt = <1012500 1012500 1500000>;
clock-latency-ns = <140000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = < 987500>;
opp-microvolt = < 987500 987500 1500000>;
clock-latency-ns = <140000>;
};
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = < 962500>;
opp-microvolt = < 962500 962500 1500000>;
clock-latency-ns = <140000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = < 937500>;
opp-microvolt = < 937500 937500 1500000>;
clock-latency-ns = <140000>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = < 912500>;
opp-microvolt = < 912500 912500 1500000>;
clock-latency-ns = <140000>;
};
};
@ -744,6 +744,56 @@
iommus = <&sysmmu_gscl1>;
};
gpu: gpu@11800000 {
compatible = "samsung,exynos5420-mali", "arm,mali-t628";
reg = <0x11800000 0x5000>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
clocks = <&clock CLK_G3D>;
clock-names = "core";
power-domains = <&g3d_pd>;
operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
#cooling-cells = <2>;
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-177000000 {
opp-hz = /bits/ 64 <177000000>;
opp-microvolt = <812500>;
};
opp-266000000 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <862500>;
};
opp-350000000 {
opp-hz = /bits/ 64 <350000000>;
opp-microvolt = <912500>;
};
opp-420000000 {
opp-hz = /bits/ 64 <420000000>;
opp-microvolt = <962500>;
};
opp-480000000 {
opp-hz = /bits/ 64 <480000000>;
opp-microvolt = <1000000>;
};
opp-543000000 {
opp-hz = /bits/ 64 <543000000>;
opp-microvolt = <1037500>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1150000>;
};
};
};
scaler_0: scaler@12800000 {
compatible = "samsung,exynos5420-scaler";
reg = <0x12800000 0x1294>;
@ -1042,7 +1092,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
clock-names = "bus";
operating-points-v2 = <&bus_wcore_opp_table>;
status = "disabled";
};
@ -1050,7 +1099,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK100_NOC>;
clock-names = "bus";
operating-points-v2 = <&bus_noc_opp_table>;
status = "disabled";
};
@ -1058,7 +1106,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
clock-names = "bus";
operating-points-v2 = <&bus_fsys_apb_opp_table>;
status = "disabled";
};
@ -1066,7 +1113,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
clock-names = "bus";
operating-points-v2 = <&bus_fsys_apb_opp_table>;
status = "disabled";
};
@ -1074,7 +1120,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
clock-names = "bus";
operating-points-v2 = <&bus_fsys2_opp_table>;
status = "disabled";
};
@ -1082,7 +1127,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333>;
clock-names = "bus";
operating-points-v2 = <&bus_mfc_opp_table>;
status = "disabled";
};
@ -1090,7 +1134,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266>;
clock-names = "bus";
operating-points-v2 = <&bus_gen_opp_table>;
status = "disabled";
};
@ -1098,7 +1141,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK66>;
clock-names = "bus";
operating-points-v2 = <&bus_peri_opp_table>;
status = "disabled";
};
@ -1106,7 +1148,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK333_G2D>;
clock-names = "bus";
operating-points-v2 = <&bus_g2d_opp_table>;
status = "disabled";
};
@ -1114,7 +1155,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK266_G2D>;
clock-names = "bus";
operating-points-v2 = <&bus_g2d_acp_opp_table>;
status = "disabled";
};
@ -1122,7 +1162,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
clock-names = "bus";
operating-points-v2 = <&bus_jpeg_opp_table>;
status = "disabled";
};
@ -1130,7 +1169,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK166>;
clock-names = "bus";
operating-points-v2 = <&bus_jpeg_apb_opp_table>;
status = "disabled";
};
@ -1138,7 +1176,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
clock-names = "bus";
operating-points-v2 = <&bus_disp1_fimd_opp_table>;
status = "disabled";
};
@ -1146,7 +1183,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
clock-names = "bus";
operating-points-v2 = <&bus_disp1_opp_table>;
status = "disabled";
};
@ -1154,7 +1190,6 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
clock-names = "bus";
operating-points-v2 = <&bus_gscl_opp_table>;
status = "disabled";
};
@ -1162,252 +1197,8 @@
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
clock-names = "bus";
operating-points-v2 = <&bus_mscl_opp_table>;
status = "disabled";
};
bus_wcore_opp_table: opp_table2 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <84000000>;
opp-microvolt = <925000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
opp-microvolt = <950000>;
};
opp02 {
opp-hz = /bits/ 64 <222000000>;
opp-microvolt = <950000>;
};
opp03 {
opp-hz = /bits/ 64 <333000000>;
opp-microvolt = <950000>;
};
opp04 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <987500>;
};
};
bus_noc_opp_table: opp_table3 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <67000000>;
};
opp01 {
opp-hz = /bits/ 64 <75000000>;
};
opp02 {
opp-hz = /bits/ 64 <86000000>;
};
opp03 {
opp-hz = /bits/ 64 <100000000>;
};
};
bus_fsys_apb_opp_table: opp_table4 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <100000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
};
bus_fsys2_opp_table: opp_table5 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <75000000>;
};
opp01 {
opp-hz = /bits/ 64 <100000000>;
};
opp02 {
opp-hz = /bits/ 64 <150000000>;
};
};
bus_mfc_opp_table: opp_table6 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <96000000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
};
opp02 {
opp-hz = /bits/ 64 <167000000>;
};
opp03 {
opp-hz = /bits/ 64 <222000000>;
};
opp04 {
opp-hz = /bits/ 64 <333000000>;
};
};
bus_gen_opp_table: opp_table7 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <89000000>;
};
opp01 {
opp-hz = /bits/ 64 <133000000>;
};
opp02 {
opp-hz = /bits/ 64 <178000000>;
};
opp03 {
opp-hz = /bits/ 64 <267000000>;
};
};
bus_peri_opp_table: opp_table8 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <67000000>;
};
};
bus_g2d_opp_table: opp_table9 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <84000000>;
};
opp01 {
opp-hz = /bits/ 64 <167000000>;
};
opp02 {
opp-hz = /bits/ 64 <222000000>;
};
opp03 {
opp-hz = /bits/ 64 <300000000>;
};
opp04 {
opp-hz = /bits/ 64 <333000000>;
};
};
bus_g2d_acp_opp_table: opp_table10 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <67000000>;
};
opp01 {
opp-hz = /bits/ 64 <133000000>;
};
opp02 {
opp-hz = /bits/ 64 <178000000>;
};
opp03 {
opp-hz = /bits/ 64 <267000000>;
};
};
bus_jpeg_opp_table: opp_table11 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <75000000>;
};
opp01 {
opp-hz = /bits/ 64 <150000000>;
};
opp02 {
opp-hz = /bits/ 64 <200000000>;
};
opp03 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_jpeg_apb_opp_table: opp_table12 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <84000000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
};
opp02 {
opp-hz = /bits/ 64 <134000000>;
};
opp03 {
opp-hz = /bits/ 64 <167000000>;
};
};
bus_disp1_fimd_opp_table: opp_table13 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <120000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
};
bus_disp1_opp_table: opp_table14 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <120000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
opp02 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_gscl_opp_table: opp_table15 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <150000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
opp02 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_mscl_opp_table: opp_table16 {
compatible = "operating-points-v2";
opp00 {
opp-hz = /bits/ 64 <84000000>;
};
opp01 {
opp-hz = /bits/ 64 <167000000>;
};
opp02 {
opp-hz = /bits/ 64 <222000000>;
};
opp03 {
opp-hz = /bits/ 64 <333000000>;
};
opp04 {
opp-hz = /bits/ 64 <400000000>;
};
};
};
thermal-zones {

2
sys/gnu/dts/arm/exynos5422-cpus.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* SAMSUNG EXYNOS5422 SoC cpu device tree source
* Samsung Exynos5422 SoC cpu device tree source
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com

285
sys/gnu/dts/arm/exynos5422-odroid-core.dtsi
View File

@ -35,7 +35,264 @@
};
};
dmc_opp_table: opp_table2 {
bus_wcore_opp_table: opp_table2 {
compatible = "operating-points-v2";
/* derived from 532MHz MPLL */
opp00 {
opp-hz = /bits/ 64 <88700000>;
opp-microvolt = <925000 925000 1400000>;
};
opp01 {
opp-hz = /bits/ 64 <133000000>;
opp-microvolt = <950000 950000 1400000>;
};
opp02 {
opp-hz = /bits/ 64 <177400000>;
opp-microvolt = <950000 950000 1400000>;
};
opp03 {
opp-hz = /bits/ 64 <266000000>;
opp-microvolt = <950000 950000 1400000>;
};
opp04 {
opp-hz = /bits/ 64 <532000000>;
opp-microvolt = <1000000 1000000 1400000>;
};
};
bus_noc_opp_table: opp_table3 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <66600000>;
};
opp01 {
opp-hz = /bits/ 64 <74000000>;
};
opp02 {
opp-hz = /bits/ 64 <83250000>;
};
opp03 {
opp-hz = /bits/ 64 <111000000>;
};
};
bus_fsys_apb_opp_table: opp_table4 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <111000000>;
};
opp01 {
opp-hz = /bits/ 64 <222000000>;
};
};
bus_fsys2_opp_table: opp_table5 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
opp00 {
opp-hz = /bits/ 64 <75000000>;
};
opp01 {
opp-hz = /bits/ 64 <120000000>;
};
opp02 {
opp-hz = /bits/ 64 <200000000>;
};
};
bus_mfc_opp_table: opp_table6 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <83250000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
};
opp02 {
opp-hz = /bits/ 64 <166500000>;
};
opp03 {
opp-hz = /bits/ 64 <222000000>;
};
opp04 {
opp-hz = /bits/ 64 <333000000>;
};
};
bus_gen_opp_table: opp_table7 {
compatible = "operating-points-v2";
/* derived from 532MHz MPLL */
opp00 {
opp-hz = /bits/ 64 <88700000>;
};
opp01 {
opp-hz = /bits/ 64 <133000000>;
};
opp02 {
opp-hz = /bits/ 64 <178000000>;
};
opp03 {
opp-hz = /bits/ 64 <266000000>;
};
};
bus_peri_opp_table: opp_table8 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <66600000>;
};
};
bus_g2d_opp_table: opp_table9 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <83250000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
};
opp02 {
opp-hz = /bits/ 64 <166500000>;
};
opp03 {
opp-hz = /bits/ 64 <222000000>;
};
opp04 {
opp-hz = /bits/ 64 <333000000>;
};
};
bus_g2d_acp_opp_table: opp_table10 {
compatible = "operating-points-v2";
/* derived from 532MHz MPLL */
opp00 {
opp-hz = /bits/ 64 <66500000>;
};
opp01 {
opp-hz = /bits/ 64 <133000000>;
};
opp02 {
opp-hz = /bits/ 64 <178000000>;
};
opp03 {
opp-hz = /bits/ 64 <266000000>;
};
};
bus_jpeg_opp_table: opp_table11 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
opp00 {
opp-hz = /bits/ 64 <75000000>;
};
opp01 {
opp-hz = /bits/ 64 <150000000>;
};
opp02 {
opp-hz = /bits/ 64 <200000000>;
};
opp03 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_jpeg_apb_opp_table: opp_table12 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <83250000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
};
opp02 {
opp-hz = /bits/ 64 <133000000>;
};
opp03 {
opp-hz = /bits/ 64 <166500000>;
};
};
bus_disp1_fimd_opp_table: opp_table13 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
opp00 {
opp-hz = /bits/ 64 <120000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
};
bus_disp1_opp_table: opp_table14 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
opp00 {
opp-hz = /bits/ 64 <120000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
opp02 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_gscl_opp_table: opp_table15 {
compatible = "operating-points-v2";
/* derived from 600MHz DPLL */
opp00 {
opp-hz = /bits/ 64 <150000000>;
};
opp01 {
opp-hz = /bits/ 64 <200000000>;
};
opp02 {
opp-hz = /bits/ 64 <300000000>;
};
};
bus_mscl_opp_table: opp_table16 {
compatible = "operating-points-v2";
/* derived from 666MHz CPLL */
opp00 {
opp-hz = /bits/ 64 <84000000>;
};
opp01 {
opp-hz = /bits/ 64 <167000000>;
};
opp02 {
opp-hz = /bits/ 64 <222000000>;
};
opp03 {
opp-hz = /bits/ 64 <333000000>;
};
opp04 {
opp-hz = /bits/ 64 <666000000>;
};
};
dmc_opp_table: opp_table17 {
compatible = "operating-points-v2";
opp00 {
@ -134,6 +391,7 @@
};
&bus_wcore {
operating-points-v2 = <&bus_wcore_opp_table>;
devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
<&nocp_mem1_0>, <&nocp_mem1_1>;
vdd-supply = <&buck3_reg>;
@ -142,76 +400,91 @@
};
&bus_noc {
operating-points-v2 = <&bus_noc_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_fsys_apb {
operating-points-v2 = <&bus_fsys_apb_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_fsys {
operating-points-v2 = <&bus_fsys2_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_fsys2 {
operating-points-v2 = <&bus_fsys2_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_mfc {
operating-points-v2 = <&bus_mfc_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_gen {
operating-points-v2 = <&bus_gen_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_peri {
operating-points-v2 = <&bus_peri_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_g2d {
operating-points-v2 = <&bus_g2d_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_g2d_acp {
operating-points-v2 = <&bus_g2d_acp_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_jpeg {
operating-points-v2 = <&bus_jpeg_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_jpeg_apb {
operating-points-v2 = <&bus_jpeg_apb_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_disp1_fimd {
operating-points-v2 = <&bus_disp1_fimd_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_disp1 {
operating-points-v2 = <&bus_disp1_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_gscl_scaler {
operating-points-v2 = <&bus_gscl_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
&bus_mscl {
operating-points-v2 = <&bus_mscl_opp_table>;
devfreq = <&bus_wcore>;
status = "okay";
};
@ -601,6 +874,8 @@
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-coupled-with = <&buck3_reg>;
regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
@ -613,6 +888,8 @@
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
regulator-coupled-with = <&buck2_reg>;
regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
@ -623,7 +900,6 @@
regulator-name = "vdd_g3d";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
@ -771,6 +1047,11 @@
vtmu-supply = <&ldo7_reg>;
};
&gpu {
mali-supply = <&buck4_reg>;
status = "okay";
};
&rtc {
status = "okay";
clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;

64
sys/gnu/dts/arm/exynos5422-odroidhc1.dts
View File

@ -72,14 +72,14 @@
*/
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
@ -116,14 +116,14 @@
};
map1 {
trip = <&cpu1_alert1>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
@ -160,14 +160,14 @@
};
map1 {
trip = <&cpu2_alert1>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
@ -204,14 +204,14 @@
};
map1 {
trip = <&cpu3_alert1>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};

78
sys/gnu/dts/arm/exynos5422-odroidxu3-common.dtsi
View File

@ -107,7 +107,7 @@
/*
* When reaching cpu0_alert3, reduce CPU
* by 2 steps. On Exynos5422/5800 that would
* be: 1600 MHz and 1100 MHz.
* (usually) be: 1800 MHz and 1200 MHz.
*/
map3 {
trip = <&cpu0_alert3>;
@ -122,19 +122,19 @@
};
/*
* When reaching cpu0_alert4, reduce CPU
* further, down to 600 MHz (12 steps for big,
* 7 steps for LITTLE).
* further, down to 600 MHz (14 steps for big,
* 8 steps for LITTLE).
*/
map4 {
cpu0_cooling_map4: map4 {
trip = <&cpu0_alert4>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
@ -198,16 +198,16 @@
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map4 {
cpu1_cooling_map4: map4 {
trip = <&cpu1_alert4>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
@ -271,16 +271,16 @@
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map4 {
cpu2_cooling_map4: map4 {
trip = <&cpu2_alert4>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};
@ -344,16 +344,16 @@
<&cpu6 0 2>,
<&cpu7 0 2>;
};
map4 {
cpu3_cooling_map4: map4 {
trip = <&cpu3_alert4>;
cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
cooling-device = <&cpu0 3 8>,
<&cpu1 3 8>,
<&cpu2 3 8>,
<&cpu3 3 8>,
<&cpu4 3 14>,
<&cpu5 3 14>,
<&cpu6 3 14>,
<&cpu7 3 14>;
};
};
};

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