Use the stock file for now (but leave a note behind about our OBE changes).
This commit is contained in:
obrien
parent
3519dd389b
commit
e40513279f
@ -404,6 +404,7 @@ const int x86_accumulate_outgoing_args = m_ATHLON | m_PENT4 | m_PPRO;
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const int x86_prologue_using_move = m_ATHLON | m_PENT4 | m_PPRO;
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const int x86_epilogue_using_move = m_ATHLON | m_PENT4 | m_PPRO;
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const int x86_decompose_lea = m_PENT4;
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const int x86_arch_always_fancy_math_387 = m_PENT|m_PPRO|m_ATHLON|m_PENT4;
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/* In case the avreage insn count for single function invocation is
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lower than this constant, emit fast (but longer) prologue and
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@ -1097,14 +1098,14 @@ override_options ()
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don't want additional code to keep the stack aligned when
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optimizing for code size. */
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ix86_preferred_stack_boundary = (optimize_size
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? TARGET_64BIT ? 64 : 32
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? TARGET_64BIT ? 128 : 32
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: 128);
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if (ix86_preferred_stack_boundary_string)
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{
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i = atoi (ix86_preferred_stack_boundary_string);
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if (i < (TARGET_64BIT ? 3 : 2) || i > 12)
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if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
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error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
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TARGET_64BIT ? 3 : 2);
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TARGET_64BIT ? 4 : 2);
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else
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ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
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}
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@ -1129,6 +1130,11 @@ override_options ()
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if (flag_unsafe_math_optimizations)
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target_flags &= ~MASK_IEEE_FP;
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/* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
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since the insns won't need emulation. */
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if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
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target_flags &= ~MASK_NO_FANCY_MATH_387;
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if (TARGET_64BIT)
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{
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if (TARGET_ALIGN_DOUBLE)
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@ -1340,7 +1346,7 @@ ix86_osf_output_function_prologue (file, size)
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{
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const char *prefix = "";
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const char *const lprefix = LPREFIX;
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int labelno = profile_label_no;
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int labelno = current_function_profile_label_no;
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#ifdef OSF_OS
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@ -1478,12 +1484,25 @@ ix86_return_pops_args (fundecl, funtype, size)
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return size;
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}
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/* Lose any fake structure return argument. */
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/* Lose any fake structure return argument if it is passed on the stack. */
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if (aggregate_value_p (TREE_TYPE (funtype))
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&& !TARGET_64BIT)
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return GET_MODE_SIZE (Pmode);
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{
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int nregs = ix86_regparm;
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return 0;
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if (funtype)
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{
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tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (funtype));
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if (attr)
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nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
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}
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if (!nregs)
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return GET_MODE_SIZE (Pmode);
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}
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return 0;
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}
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/* Argument support functions. */
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@ -1725,7 +1744,8 @@ classify_argument (mode, type, classes, bit_offset)
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classes[i] = subclasses[i % num];
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}
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/* Unions are similar to RECORD_TYPE but offset is always 0. */
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else if (TREE_CODE (type) == UNION_TYPE)
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else if (TREE_CODE (type) == UNION_TYPE
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|| TREE_CODE (type) == QUAL_UNION_TYPE)
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{
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for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
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{
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@ -1831,7 +1851,19 @@ classify_argument (mode, type, classes, bit_offset)
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case SCmode:
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classes[0] = X86_64_SSE_CLASS;
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return 1;
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case V4SFmode:
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case V4SImode:
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classes[0] = X86_64_SSE_CLASS;
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classes[1] = X86_64_SSEUP_CLASS;
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return 2;
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case V2SFmode:
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case V2SImode:
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case V4HImode:
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case V8QImode:
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classes[0] = X86_64_SSE_CLASS;
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return 1;
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case BLKmode:
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case VOIDmode:
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return 0;
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default:
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abort ();
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@ -1944,7 +1976,7 @@ construct_container (mode, type, in_return, nintregs, nsseregs, intreg, sse_regn
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abort ();
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}
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if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS)
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return gen_rtx_REG (TImode, SSE_REGNO (sse_regno));
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return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
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if (n == 2
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&& class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
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return gen_rtx_REG (TFmode, FIRST_STACK_REG);
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@ -1997,7 +2029,7 @@ construct_container (mode, type, in_return, nintregs, nsseregs, intreg, sse_regn
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sse_regno++;
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break;
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case X86_64_SSE_CLASS:
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if (i < n && class[i + 1] == X86_64_SSEUP_CLASS)
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if (i < n - 1 && class[i + 1] == X86_64_SSEUP_CLASS)
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tmpmode = TImode, i++;
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else
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tmpmode = DImode;
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@ -2489,6 +2521,7 @@ ix86_va_start (stdarg_p, valist, nextarg)
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t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
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TREE_SIDE_EFFECTS (t) = 1;
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expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
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cfun->preferred_stack_boundary = 128;
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}
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/* Implement va_arg. */
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@ -3867,9 +3900,7 @@ ix86_save_reg (regno, maybe_eh_return)
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int regno;
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int maybe_eh_return;
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{
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if (flag_pic
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&& ! TARGET_64BIT
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&& regno == PIC_OFFSET_TABLE_REGNUM
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if (regno == PIC_OFFSET_TABLE_REGNUM
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&& (current_function_uses_pic_offset_table
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|| current_function_uses_const_pool
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|| current_function_calls_eh_return))
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@ -4986,11 +5017,15 @@ legitimize_pic_address (orig, reg)
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if (GET_CODE (addr) == CONST)
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{
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addr = XEXP (addr, 0);
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if (GET_CODE (addr) == UNSPEC)
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{
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/* Check that the unspec is one of the ones we generate? */
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}
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else if (GET_CODE (addr) != PLUS)
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/* We must match stuff we generate before. Assume the only
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unspecs that can get here are ours. Not that we could do
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anything with them anyway... */
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if (GET_CODE (addr) == UNSPEC
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|| (GET_CODE (addr) == PLUS
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&& GET_CODE (XEXP (addr, 0)) == UNSPEC))
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return orig;
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if (GET_CODE (addr) != PLUS)
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abort ();
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}
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if (GET_CODE (addr) == PLUS)
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@ -5377,34 +5412,70 @@ rtx
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i386_simplify_dwarf_addr (orig_x)
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rtx orig_x;
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{
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rtx x = orig_x;
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rtx x = orig_x, y;
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if (GET_CODE (x) == MEM)
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x = XEXP (x, 0);
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if (TARGET_64BIT)
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{
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if (GET_CODE (x) != CONST
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|| GET_CODE (XEXP (x, 0)) != UNSPEC
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|| XINT (XEXP (x, 0), 1) != 15)
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|| XINT (XEXP (x, 0), 1) != 15
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|| GET_CODE (orig_x) != MEM)
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return orig_x;
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return XVECEXP (XEXP (x, 0), 0, 0);
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}
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if (GET_CODE (x) != PLUS
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|| GET_CODE (XEXP (x, 0)) != REG
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|| GET_CODE (XEXP (x, 1)) != CONST)
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return orig_x;
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if (GET_CODE (XEXP (x, 0)) == REG
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&& REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
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/* %ebx + GOT/GOTOFF */
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y = NULL;
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else if (GET_CODE (XEXP (x, 0)) == PLUS)
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{
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/* %ebx + %reg * scale + GOT/GOTOFF */
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y = XEXP (x, 0);
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if (GET_CODE (XEXP (y, 0)) == REG
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&& REGNO (XEXP (y, 0)) == PIC_OFFSET_TABLE_REGNUM)
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y = XEXP (y, 1);
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else if (GET_CODE (XEXP (y, 1)) == REG
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&& REGNO (XEXP (y, 1)) == PIC_OFFSET_TABLE_REGNUM)
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y = XEXP (y, 0);
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else
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return orig_x;
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if (GET_CODE (y) != REG
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&& GET_CODE (y) != MULT
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&& GET_CODE (y) != ASHIFT)
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return orig_x;
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}
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else
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return orig_x;
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x = XEXP (XEXP (x, 1), 0);
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if (GET_CODE (x) == UNSPEC
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&& (XINT (x, 1) == 6
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|| XINT (x, 1) == 7))
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return XVECEXP (x, 0, 0);
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&& ((XINT (x, 1) == 6 && GET_CODE (orig_x) == MEM)
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|| (XINT (x, 1) == 7 && GET_CODE (orig_x) != MEM)))
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{
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if (y)
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return gen_rtx_PLUS (Pmode, y, XVECEXP (x, 0, 0));
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return XVECEXP (x, 0, 0);
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}
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if (GET_CODE (x) == PLUS
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&& GET_CODE (XEXP (x, 0)) == UNSPEC
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&& GET_CODE (XEXP (x, 1)) == CONST_INT
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&& (XINT (XEXP (x, 0), 1) == 6
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|| XINT (XEXP (x, 0), 1) == 7))
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return gen_rtx_PLUS (VOIDmode, XVECEXP (XEXP (x, 0), 0, 0), XEXP (x, 1));
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&& ((XINT (XEXP (x, 0), 1) == 6 && GET_CODE (orig_x) == MEM)
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|| (XINT (XEXP (x, 0), 1) == 7 && GET_CODE (orig_x) != MEM)))
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{
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x = gen_rtx_PLUS (VOIDmode, XVECEXP (XEXP (x, 0), 0, 0), XEXP (x, 1));
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if (y)
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return gen_rtx_PLUS (Pmode, y, x);
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return x;
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}
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return orig_x;
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}
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@ -5593,6 +5664,8 @@ print_reg (x, code, file)
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C -- print opcode suffix for set/cmov insn.
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c -- like C, but print reversed condition
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F,f -- likewise, but for floating-point.
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O -- if CMOV_SUN_AS_SYNTAX, expand to "w.", "l." or "q.", otherwise
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nothing
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R -- print the prefix for register names.
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z -- print the opcode suffix for the size of the current operand.
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* -- print a star (in certain assembler syntax)
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@ -5682,11 +5755,14 @@ print_operand (file, x, code)
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case 'z':
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/* 387 opcodes don't get size suffixes if the operands are
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registers. */
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if (STACK_REG_P (x))
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return;
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/* this is the size of op from size of operand */
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/* Likewise if using Intel opcodes. */
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if (ASSEMBLER_DIALECT == ASM_INTEL)
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return;
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/* This is the size of op from size of operand. */
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switch (GET_MODE_SIZE (GET_MODE (x)))
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{
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case 2:
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@ -5787,10 +5863,31 @@ print_operand (file, x, code)
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break;
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}
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return;
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case 'O':
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#ifdef CMOV_SUN_AS_SYNTAX
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if (ASSEMBLER_DIALECT == ASM_ATT)
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{
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switch (GET_MODE (x))
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{
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case HImode: putc ('w', file); break;
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case SImode:
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case SFmode: putc ('l', file); break;
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case DImode:
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case DFmode: putc ('q', file); break;
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default: abort ();
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}
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putc ('.', file);
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}
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#endif
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return;
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case 'C':
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put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
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return;
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case 'F':
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#ifdef CMOV_SUN_AS_SYNTAX
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if (ASSEMBLER_DIALECT == ASM_ATT)
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putc ('.', file);
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#endif
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put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
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return;
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@ -5806,6 +5903,10 @@ print_operand (file, x, code)
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put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
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return;
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case 'f':
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#ifdef CMOV_SUN_AS_SYNTAX
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if (ASSEMBLER_DIALECT == ASM_ATT)
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putc ('.', file);
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#endif
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put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
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return;
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case '+':
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@ -5842,11 +5943,7 @@ print_operand (file, x, code)
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return;
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}
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default:
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{
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char str[50];
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sprintf (str, "invalid operand code `%c'", code);
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output_operand_lossage (str);
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}
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output_operand_lossage ("invalid operand code `%c'", code);
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}
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}
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@ -6577,7 +6674,7 @@ ix86_output_addr_diff_elt (file, value, rel)
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int value, rel;
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{
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if (TARGET_64BIT)
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fprintf (file, "%s%s%d-.+4+(.-%s%d)\n",
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fprintf (file, "%s%s%d-.+(.-%s%d)\n",
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ASM_LONG, LPREFIX, value, LPREFIX, rel);
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else if (HAVE_AS_GOTOFF_IN_DATA)
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fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
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@ -6704,7 +6801,7 @@ ix86_expand_vector_move (mode, operands)
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&& !register_operand (operands[1], mode)
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&& operands[1] != CONST0_RTX (mode))
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{
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rtx temp = force_reg (TImode, operands[1]);
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rtx temp = force_reg (GET_MODE (operands[1]), operands[1]);
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emit_move_insn (operands[0], temp);
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return;
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}
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@ -7117,7 +7214,7 @@ ix86_prepare_fp_compare_args (code, pop0, pop1)
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/* Try to rearrange the comparison to make it cheaper. */
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if (ix86_fp_comparison_cost (code)
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> ix86_fp_comparison_cost (swap_condition (code))
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&& (GET_CODE (op0) == REG || !reload_completed))
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&& (GET_CODE (op1) == REG || !no_new_pseudos))
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{
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rtx tmp;
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tmp = op0, op0 = op1, op1 = tmp;
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@ -11335,6 +11432,12 @@ ix86_expand_binop_builtin (icode, arglist, target)
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if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
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op1 = copy_to_mode_reg (mode1, op1);
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/* In the commutative cases, both op0 and op1 are nonimmediate_operand,
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yet one of the two must not be a memory. This is normally enforced
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by expanders, but we didn't bother to create one here. */
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if (GET_CODE (op0) == MEM && GET_CODE (op1) == MEM)
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op0 = copy_to_mode_reg (mode0, op0);
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pat = GEN_FCN (icode) (target, op0, op1);
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if (! pat)
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return 0;
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@ -11367,6 +11470,12 @@ ix86_expand_timode_binop_builtin (icode, arglist, target)
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if (! (*insn_data[icode].operand[2].predicate) (op1, TImode))
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op1 = copy_to_mode_reg (TImode, op1);
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/* In the commutative cases, both op0 and op1 are nonimmediate_operand,
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yet one of the two must not be a memory. This is normally enforced
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by expanders, but we didn't bother to create one here. */
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if (GET_CODE (op0) == MEM && GET_CODE (op1) == MEM)
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op0 = copy_to_mode_reg (TImode, op0);
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pat = GEN_FCN (icode) (target, op0, op1);
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if (! pat)
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return 0;
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@ -11394,6 +11503,10 @@ ix86_expand_store_builtin (icode, arglist)
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op1 = safe_vector_operand (op1, mode1);
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op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
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if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
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op1 = copy_to_mode_reg (mode1, op1);
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pat = GEN_FCN (icode) (op0, op1);
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if (pat)
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emit_insn (pat);
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@ -11448,7 +11561,7 @@ ix86_expand_unop1_builtin (icode, arglist, target)
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{
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rtx pat;
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tree arg0 = TREE_VALUE (arglist);
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rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
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rtx op1, op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
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enum machine_mode tmode = insn_data[icode].operand[0].mode;
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enum machine_mode mode0 = insn_data[icode].operand[1].mode;
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@ -11462,8 +11575,12 @@ ix86_expand_unop1_builtin (icode, arglist, target)
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if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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pat = GEN_FCN (icode) (target, op0, op0);
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op1 = op0;
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if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
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||||
op1 = copy_to_mode_reg (mode0, op1);
|
||||
|
||||
pat = GEN_FCN (icode) (target, op0, op1);
|
||||
if (! pat)
|
||||
return 0;
|
||||
emit_insn (pat);
|
||||
@ -11673,7 +11790,7 @@ ix86_expand_builtin (exp, target, subtarget, mode, ignore)
|
||||
return target;
|
||||
|
||||
case IX86_BUILTIN_MASKMOVQ:
|
||||
icode = CODE_FOR_mmx_maskmovq;
|
||||
icode = TARGET_64BIT ? CODE_FOR_mmx_maskmovq_rex : CODE_FOR_mmx_maskmovq;
|
||||
/* Note the arg order is different from the operand order. */
|
||||
arg1 = TREE_VALUE (arglist);
|
||||
arg2 = TREE_VALUE (TREE_CHAIN (arglist));
|
||||
@ -11685,7 +11802,7 @@ ix86_expand_builtin (exp, target, subtarget, mode, ignore)
|
||||
mode1 = insn_data[icode].operand[1].mode;
|
||||
mode2 = insn_data[icode].operand[2].mode;
|
||||
|
||||
if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
|
||||
if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
|
||||
op0 = copy_to_mode_reg (mode0, op0);
|
||||
if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
|
||||
op1 = copy_to_mode_reg (mode1, op1);
|
||||
@ -12324,3 +12441,47 @@ ix86_svr3_asm_out_constructor (symbol, priority)
|
||||
fputc ('\n', asm_out_file);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Order the registers for register allocator. */
|
||||
|
||||
void
|
||||
x86_order_regs_for_local_alloc ()
|
||||
{
|
||||
int pos = 0;
|
||||
int i;
|
||||
|
||||
/* First allocate the local general purpose registers. */
|
||||
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
|
||||
if (GENERAL_REGNO_P (i) && call_used_regs[i])
|
||||
reg_alloc_order [pos++] = i;
|
||||
|
||||
/* Global general purpose registers. */
|
||||
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
|
||||
if (GENERAL_REGNO_P (i) && !call_used_regs[i])
|
||||
reg_alloc_order [pos++] = i;
|
||||
|
||||
/* x87 registers come first in case we are doing FP math
|
||||
using them. */
|
||||
if (!TARGET_SSE_MATH)
|
||||
for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
|
||||
reg_alloc_order [pos++] = i;
|
||||
|
||||
/* SSE registers. */
|
||||
for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
|
||||
reg_alloc_order [pos++] = i;
|
||||
for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
|
||||
reg_alloc_order [pos++] = i;
|
||||
|
||||
/* x87 registerts. */
|
||||
if (TARGET_SSE_MATH)
|
||||
for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
|
||||
reg_alloc_order [pos++] = i;
|
||||
|
||||
for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
|
||||
reg_alloc_order [pos++] = i;
|
||||
|
||||
/* Initialize the rest of array as we do not allocate some registers
|
||||
at all. */
|
||||
while (pos < FIRST_PSEUDO_REGISTER)
|
||||
reg_alloc_order [pos++] = 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user