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179
Bindings/arm/arm,scmi.txt Normal file
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@ -0,0 +1,179 @@
System Control and Management Interface (SCMI) Message Protocol
----------------------------------------------------------
The SCMI is intended to allow agents such as OSPM to manage various functions
that are provided by the hardware platform it is running on, including power
and performance functions.
This binding is intended to define the interface the firmware implementing
the SCMI as described in ARM document number ARM DUI 0922B ("ARM System Control
and Management Interface Platform Design Document")[0] provide for OSPM in
the device tree.
Required properties:
The scmi node with the following properties shall be under the /firmware/ node.
- compatible : shall be "arm,scmi"
- mboxes: List of phandle and mailbox channel specifiers. It should contain
exactly one or two mailboxes, one for transmitting messages("tx")
and another optional for receiving the notifications("rx") if
supported.
- shmem : List of phandle pointing to the shared memory(SHM) area as per
generic mailbox client binding.
- #address-cells : should be '1' if the device has sub-nodes, maps to
protocol identifier for a given sub-node.
- #size-cells : should be '0' as 'reg' property doesn't have any size
associated with it.
Optional properties:
- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
about the generic mailbox controller and client driver bindings.
The mailbox is the only permitted method of calling the SCMI firmware.
Mailbox doorbell is used as a mechanism to alert the presence of a
messages and/or notification.
Each protocol supported shall have a sub-node with corresponding compatible
as described in the following sections. If the platform supports dedicated
communication channel for a particular protocol, the 3 properties namely:
mboxes, mbox-names and shmem shall be present in the sub-node corresponding
to that protocol.
Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
------------------------------------------------------------
This binding uses the common clock binding[1].
Required properties:
- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands.
Power domain bindings for the power domains based on SCMI Message Protocol
------------------------------------------------------------
This binding for the SCMI power domain providers uses the generic power
domain binding[2].
Required properties:
- #power-domain-cells : Should be 1. Contains the device or the power
domain ID value used by SCMI commands.
Sensor bindings for the sensors based on SCMI Message Protocol
--------------------------------------------------------------
SCMI provides an API to access the various sensors on the SoC.
Required properties:
- #thermal-sensor-cells: should be set to 1. This property follows the
thermal device tree bindings[3].
Valid cell values are raw identifiers (Sensor ID)
as used by the firmware. Refer to platform details
for your implementation for the IDs to use.
SRAM and Shared Memory for SCMI
-------------------------------
A small area of SRAM is reserved for SCMI communication between application
processors and SCP.
The properties should follow the generic mmio-sram description found in [4]
Each sub-node represents the reserved area for SCMI.
Required sub-node properties:
- reg : The base offset and size of the reserved area with the SRAM
- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
shared memory
[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/power/power_domain.txt
[3] Documentation/devicetree/bindings/thermal/thermal.txt
[4] Documentation/devicetree/bindings/sram/sram.txt
Example:
sram@50000000 {
compatible = "mmio-sram";
reg = <0x0 0x50000000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x50000000 0x10000>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x200>;
};
cpu_scp_hpri: scp-shmem@200 {
compatible = "arm,scmi-shmem";
reg = <0x200 0x200>;
};
};
mailbox@40000000 {
....
#mbox-cells = <1>;
reg = <0x0 0x40000000 0x0 0x10000>;
};
firmware {
...
scmi {
compatible = "arm,scmi";
mboxes = <&mailbox 0 &mailbox 1>;
mbox-names = "tx", "rx";
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
#address-cells = <1>;
#size-cells = <0>;
scmi_devpd: protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
};
scmi_dvfs: protocol@13 {
reg = <0x13>;
#clock-cells = <1>;
};
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
scmi_sensors0: protocol@15 {
reg = <0x15>;
#thermal-sensor-cells = <1>;
};
};
};
cpu@0 {
...
reg = <0 0>;
clocks = <&scmi_dvfs 0>;
};
hdlcd@7ff60000 {
...
reg = <0 0x7ff60000 0 0x1000>;
clocks = <&scmi_clk 4>;
power-domains = <&scmi_devpd 1>;
};
thermal-zones {
soc_thermal {
polling-delay-passive = <100>;
polling-delay = <1000>;
/* sensor ID */
thermal-sensors = <&scmi_sensors0 3>;
...
};
};

42
Bindings/arm/cpu-enable-method/nuvoton,npcm750-smp Normal file
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@ -0,0 +1,42 @@
=========================================================
Secondary CPU enable-method "nuvoton,npcm750-smp" binding
=========================================================
To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
defined in the "cpus" node.
Enable method name: "nuvoton,npcm750-smp"
Compatible machines: "nuvoton,npcm750"
Compatible CPUs: "arm,cortex-a9"
Related properties: (none)
Note:
This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
"nuvoton,npcm750-gcr".
Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "nuvoton,npcm750-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
clocks = <&clk NPCM7XX_CLK_CPU>;
clock-names = "clk_cpu";
reg = <0>;
next-level-cache = <&L2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
clocks = <&clk NPCM7XX_CLK_CPU>;
clock-names = "clk_cpu";
reg = <1>;
next-level-cache = <&L2>;
};
};

2
Bindings/arm/cpus.txt
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@ -185,6 +185,7 @@ described below.
"nvidia,tegra186-denver"
"qcom,krait"
"qcom,kryo"
"qcom,kryo385"
"qcom,scorpion"
- enable-method
Value type: <stringlist>
@ -198,6 +199,7 @@ described below.
"actions,s500-smp"
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"allwinner,sun9i-a80-smp"
"amlogic,meson8-smp"
"amlogic,meson8b-smp"
"arm,realview-smp"

33
Bindings/arm/hisilicon/hisilicon-low-pin-count.txt Normal file
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@ -0,0 +1,33 @@
Hisilicon Hip06 Low Pin Count device
Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
provides I/O access to some legacy ISA devices.
Hip06 is based on arm64 architecture where there is no I/O space. So, the
I/O ports here are not CPU addresses, and there is no 'ranges' property in
LPC device node.
Required properties:
- compatible: value should be as follows:
(a) "hisilicon,hip06-lpc"
(b) "hisilicon,hip07-lpc"
- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
- reg: base memory range where the LPC register set is mapped.
Note:
The node name before '@' must be "isa" to represent the binding stick to the
ISA/EISA binding specification.
Example:
isa@a01b0000 {
compatible = "hisilicon,hip06-lpc";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0xa01b0000 0x0 0x1000>;
ipmi0: bt@e4 {
compatible = "ipmi-bt";
device_type = "ipmi";
reg = <0x01 0xe4 0x04>;
};
};

23
Bindings/arm/hisilicon/hisilicon.txt
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@ -74,6 +74,29 @@ Example:
reboot-offset = <0x4>;
};
-----------------------------------------------------------------------
Hisilicon Hi3798CV200 Peripheral Controller
The Hi3798CV200 Peripheral Controller controls peripherals, queries
their status, and configures some functions of peripherals.
Required properties:
- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
and "simple-mfd".
- reg: Register address and size of Peripheral Controller.
- #address-cells: Should be 1.
- #size-cells: Should be 1.
Examples:
perictrl: peripheral-controller@8a20000 {
compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
"simple-mfd";
reg = <0x8a20000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
-----------------------------------------------------------------------
Hisilicon Hi6220 system controller

9
Bindings/arm/mediatek.txt
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@ -50,6 +50,15 @@ Supported boards:
- Reference board variant 1 for MT7622:
Required root node properties:
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
- Reference board for MT7623a with eMMC:
Required root node properties:
- compatible = "mediatek,mt7623a-rfb-emmc", "mediatek,mt7623";
- Reference board for MT7623a with NAND:
Required root node properties:
- compatible = "mediatek,mt7623a-rfb-nand", "mediatek,mt7623";
- Reference board for MT7623n with eMMC:
Required root node properties:
- compatible = "mediatek,mt7623n-rfb-emmc", "mediatek,mt7623";
- Reference board for MT7623n with NAND:
Required root node properties:
- compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";

20
Bindings/arm/mediatek/mediatek,audsys.txt
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@ -6,6 +6,7 @@ The MediaTek AUDSYS controller provides various clocks to the system.
Required Properties:
- compatible: Should be one of:
- "mediatek,mt2701-audsys", "syscon"
- "mediatek,mt7622-audsys", "syscon"
- #clock-cells: Must be 1
@ -13,10 +14,19 @@ The AUDSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Required sub-nodes:
-------
For common binding part and usage, refer to
../sonud/mt2701-afe-pcm.txt.
Example:
audsys: audsys@11220000 {
compatible = "mediatek,mt7622-audsys", "syscon";
reg = <0 0x11220000 0 0x1000>;
#clock-cells = <1>;
};
audsys: clock-controller@11220000 {
compatible = "mediatek,mt7622-audsys", "syscon";
reg = <0 0x11220000 0 0x2000>;
#clock-cells = <1>;
afe: audio-controller {
...
};
};

1
Bindings/arm/mediatek/mediatek,ethsys.txt
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@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7622-ethsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt

2
Bindings/arm/mediatek/mediatek,pciesys.txt
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@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-pciesys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
The PCIESYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

2
Bindings/arm/mediatek/mediatek,ssusbsys.txt
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@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-ssusbsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
The SSUSBSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};

6
Bindings/arm/npcm/npcm.txt Normal file
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@ -0,0 +1,6 @@
NPCM Platforms Device Tree Bindings
-----------------------------------
NPCM750 SoC
Required root node properties:
- compatible = "nuvoton,npcm750";

1
Bindings/arm/omap/ctrl.txt
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@ -25,6 +25,7 @@ Required properties:
"ti,omap4-scm-padconf-wkup"
"ti,omap5-scm-core"
"ti,omap5-scm-padconf-core"
"ti,omap5-scm-wkup-pad-conf"
"ti,dra7-scm-core"
- reg: Contains Control Module register address range
(base address and length)

16
Bindings/arm/omap/mpu.txt
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@ -13,6 +13,13 @@ Required properties:
Optional properties:
- sram: Phandle to the ocmcram node
am335x and am437x only:
- pm-sram: Phandles to ocmcram nodes to be used for power management.
First should be type 'protect-exec' for the driver to use to copy
and run PM functions, second should be regular pool to be used for
data region for code. See Documentation/devicetree/bindings/sram/sram.txt
for more details.
Examples:
- For an OMAP5 SMP system:
@ -36,3 +43,12 @@ mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
};
- For an AM335x system:
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
pm-sram = <&pm_sram_code
&pm_sram_data>;
};

1
Bindings/arm/qcom.txt
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@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings:
msm8996
mdm9615
ipq8074
sdm845
The 'board' element must be one of the following strings:

12
Bindings/arm/rockchip.txt
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@ -50,6 +50,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "firefly,firefly-rk3399", "rockchip,rk3399";
- Firefly roc-rk3328-cc board:
Required root node properties:
- compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328";
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
@ -181,10 +185,18 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
- Rockchip RK3399 Sapphire board standalone:
Required root node properties:
- compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
- Rockchip RK3399 Sapphire Excavator board:
Required root node properties:
- compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
- Theobroma Systems RK3368-uQ7 Haikou Baseboard:
Required root node properties:
- compatible = "tsd,rk3368-uq7-haikou", "rockchip,rk3368";
- Theobroma Systems RK3399-Q7 Haikou Baseboard:
Required root node properties:
- compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";

6
Bindings/arm/samsung/pmu.txt
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@ -43,6 +43,12 @@ following properties:
- interrupt-parent: a phandle indicating which interrupt controller
this PMU signals interrupts to.
Optional nodes:
- nodes defining the restart and poweroff syscon children
Example :
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5250-pmu", "syscon";

4
Bindings/arm/samsung/samsung-boards.txt
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@ -9,7 +9,11 @@ Required root node properties:
- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
- "samsung,trats" - for Exynos4210-based Tizen Reference board.
- "samsung,universal_c210" - for Exynos4210-based Samsung board.
- "samsung,i9300" - for Exynos4412-based Samsung GT-I9300 board.
- "samsung,i9305" - for Exynos4412-based Samsung GT-I9305 board.
- "samsung,midas" - for Exynos4412-based Samsung Midas board.
- "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board.
- "samsung,n710x" - for Exynos4412-based Samsung GT-N7100/GT-N7105 board.
- "samsung,trats2" - for Exynos4412-based Tizen Reference board.
- "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board.
- "samsung,xyref5260" - for Exynos5260-based Samsung board.

18
Bindings/arm/shmobile.txt
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@ -39,8 +39,12 @@ SoCs:
compatible = "renesas,r8a7795"
- R-Car M3-W (R8A77960)
compatible = "renesas,r8a7796"
- R-Car M3-N (R8A77965)
compatible = "renesas,r8a77965"
- R-Car V3M (R8A77970)
compatible = "renesas,r8a77970"
- R-Car V3H (R8A77980)
compatible = "renesas,r8a77980"
- R-Car D3 (R8A77995)
compatible = "renesas,r8a77995"
@ -52,11 +56,13 @@ Boards:
- APE6-EVM
compatible = "renesas,ape6evm", "renesas,r8a73a4"
- Atmark Techno Armadillo-800 EVA
compatible = "renesas,armadillo800eva"
compatible = "renesas,armadillo800eva", "renesas,r8a7740"
- Blanche (RTP0RC7792SEB00010S)
compatible = "renesas,blanche", "renesas,r8a7792"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
- Condor (RTP0RC77980SEB0010SS/RTP0RC77980SEB0010SA01)
compatible = "renesas,condor", "renesas,r8a77980"
- Draak (RTP0RC77995SEB0010S)
compatible = "renesas,draak", "renesas,r8a77995"
- Eagle (RTP0RC77970SEB0010S)
@ -102,19 +108,25 @@ Boards:
compatible = "renesas,salvator-x", "renesas,r8a7795"
- Salvator-X (RTP0RC7796SIPB0011S)
compatible = "renesas,salvator-x", "renesas,r8a7796"
- Salvator-X (RTP0RC7796SIPB0011S (M3N))
compatible = "renesas,salvator-x", "renesas,r8a77965"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7795"
- Salvator-XS (Salvator-X 2nd version, RTP0RC7796SIPB0012S)
compatible = "renesas,salvator-xs", "renesas,r8a7796"
- Salvator-XS (Salvator-X 2nd version, RTP0RC77965SIPB012S)
compatible = "renesas,salvator-xs", "renesas,r8a77965"
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
- SK-RZG1E (YR8A77450S000BE)
compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
- SK-RZG1M (YR8A77430S000BE)
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
- V3MSK
- Stout (ADAS Starterkit, Y-R-CAR-ADAS-SKH2-BOARD)
compatible = "renesas,stout", "renesas,r8a7790"
- V3MSK (Y-ASK-RCAR-V3M-WS10)
compatible = "renesas,v3msk", "renesas,r8a77970"
- Wheat
- Wheat (RTP0RC7792ASKB0000JE)
compatible = "renesas,wheat", "renesas,r8a7792"

1
Bindings/arm/stm32.txt
View File

@ -7,3 +7,4 @@ using one of the following compatible strings:
st,stm32f469
st,stm32f746
st,stm32h743
st,stm32mp157

44
Bindings/arm/sunxi/smp-sram.txt Normal file
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@ -0,0 +1,44 @@
Allwinner SRAM for smp bringup:
------------------------------------------------
Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
primary core (cpu0). Once the core gets powered up it checks if a magic
value is set at a specific location. If it is then the BROM will jump
to the software entry address, instead of executing a standard boot.
Therefore a reserved section sub-node has to be added to the mmio-sram
declaration.
Note that this is separate from the Allwinner SRAM controller found in
../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to
any device.
Also there are no "secure-only" properties. The implementation should
check if this SRAM is usable first.
Required sub-node properties:
- compatible : depending on the SoC this should be one of:
"allwinner,sun9i-a80-smp-sram"
The rest of the properties should follow the generic mmio-sram discription
found in ../../misc/sram.txt
Example:
sram_b: sram@20000 {
/* 256 KiB secure SRAM at 0x20000 */
compatible = "mmio-sram";
reg = <0x00020000 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00020000 0x40000>;
smp-sram@1000 {
/*
* This is checked by BROM to determine if
* cpu0 should jump to SMP entry vector
*/
compatible = "allwinner,sun9i-a80-smp-sram";
reg = <0x1000 0x8>;
};
};

16
Bindings/arm/tegra.txt
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@ -9,6 +9,12 @@ following compatible values:
nvidia,tegra20
nvidia,tegra30
nvidia,tegra114
nvidia,tegra124
nvidia,tegra132
nvidia,tegra210
nvidia,tegra186
nvidia,tegra194
Boards
-------------------------------------------
@ -26,8 +32,18 @@ board-specific compatible values:
nvidia,cardhu
nvidia,cardhu-a02
nvidia,cardhu-a04
nvidia,dalmore
nvidia,harmony
nvidia,jetson-tk1
nvidia,norrin
nvidia,p2371-0000
nvidia,p2371-2180
nvidia,p2571
nvidia,p2771-0000
nvidia,p2972-0000
nvidia,roth
nvidia,seaboard
nvidia,tn7
nvidia,ventana
toradex,apalis_t30
toradex,apalis_t30-eval

2
Bindings/arm/tegra/nvidia,tegra186-pmc.txt
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@ -3,6 +3,7 @@ NVIDIA Tegra Power Management Controller (PMC)
Required properties:
- compatible: Should contain one of the following:
- "nvidia,tegra186-pmc": for Tegra186
- "nvidia,tegra194-pmc": for Tegra194
- reg: Must contain an (offset, length) pair of the register set for each
entry in reg-names.
- reg-names: Must include the following entries:
@ -10,6 +11,7 @@ Required properties:
- "wake"
- "aotag"
- "scratch"
- "misc" (Only for Tegra194)
Optional properties:
- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.

56
Bindings/arm/xilinx.txt
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@ -5,3 +5,59 @@ shall have the following properties.
Required root node properties:
- compatible = "xlnx,zynq-7000";
Additional compatible strings:
- Xilinx internal board cc108
"xlnx,zynq-cc108"
- Xilinx internal board zc770 with different FMC cards
"xlnx,zynq-zc770-xm010"
"xlnx,zynq-zc770-xm011"
"xlnx,zynq-zc770-xm012"
"xlnx,zynq-zc770-xm013"
- Digilent Zybo Z7 board
"digilent,zynq-zybo-z7"
---------------------------------------------------------------
Xilinx Zynq UltraScale+ MPSoC Platforms Device Tree Bindings
Boards with ZynqMP SOC based on an ARM Cortex A53 processor
shall have the following properties.
Required root node properties:
- compatible = "xlnx,zynqmp";
Additional compatible strings:
- Xilinx internal board zc1232
"xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232"
- Xilinx internal board zc1254
"xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254"
- Xilinx internal board zc1275
"xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275"
- Xilinx internal board zc1751
"xlnx,zynqmp-zc1751"
- Xilinx 96boards compatible board zcu100
"xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100"
- Xilinx evaluation board zcu102
"xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102"
"xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102"
"xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102"
- Xilinx evaluation board zcu104
"xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104"
- Xilinx evaluation board zcu106
"xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106"
- Xilinx evaluation board zcu111
"xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111"

1
Bindings/ata/imx-sata.txt
View File

@ -7,6 +7,7 @@ Required properties:
- compatible : should be one of the following:
- "fsl,imx53-ahci" for i.MX53 SATA controller
- "fsl,imx6q-ahci" for i.MX6Q SATA controller
- "fsl,imx6qp-ahci" for i.MX6QP SATA controller
- interrupts : interrupt mapping for SATA IRQ
- reg : registers mapping
- clocks : list of clock specifiers, must contain an entry for each

36
Bindings/ata/nvidia,tegra124-ahci.txt
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@ -1,9 +1,10 @@
Tegra124 SoC SATA AHCI controller
Tegra SoC SATA AHCI controller
Required properties :
- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise,
must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>
is tegra132.
- compatible : Must be one of:
- Tegra124 : "nvidia,tegra124-ahci"
- Tegra132 : "nvidia,tegra132-ahci", "nvidia,tegra124-ahci"
- Tegra210 : "nvidia,tegra210-ahci"
- reg : Should contain 2 entries:
- AHCI register set (SATA BAR5)
- SATA register set
@ -13,8 +14,6 @@ Required properties :
- clock-names : Must include the following entries:
- sata
- sata-oob
- cml1
- pll_e
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
- reset-names : Must include the following entries:
@ -24,9 +23,22 @@ Required properties :
- phys : Must contain an entry for each entry in phy-names.
See ../phy/phy-bindings.txt for details.
- phy-names : Must include the following entries:
- sata-phy : XUSB PADCTL SATA PHY
- hvdd-supply : Defines the SATA HVDD regulator
- vddio-supply : Defines the SATA VDDIO regulator
- avdd-supply : Defines the SATA AVDD regulator
- target-5v-supply : Defines the SATA 5V power regulator
- target-12v-supply : Defines the SATA 12V power regulator
- For Tegra124 and Tegra132:
- sata-phy : XUSB PADCTL SATA PHY
- For Tegra124 and Tegra132:
- hvdd-supply : Defines the SATA HVDD regulator
- vddio-supply : Defines the SATA VDDIO regulator
- avdd-supply : Defines the SATA AVDD regulator
- target-5v-supply : Defines the SATA 5V power regulator
- target-12v-supply : Defines the SATA 12V power regulator
Optional properties:
- reg :
- AUX register set
- clock-names :
- cml1 :
cml1 clock should be defined here if the PHY driver
doesn't manage them. If it does, they should not be.
- phy-names :
- For T210:
- sata-phy

6
Bindings/bus/nvidia,tegra20-gmi.txt
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@ -73,7 +73,7 @@ Example with two SJA1000 CAN controllers connected to the GMI bus. We wrap the
controllers with a simple-bus node since they are all connected to the same
chip-select (CS4), in this example external address decoding is provided:
gmi@70090000 {
gmi@70009000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
@ -84,7 +84,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
bus@4,0 {
compatible = "simple-bus";
#address-cells = <1>;
@ -109,7 +108,7 @@ gmi@70090000 {
Example with one SJA1000 CAN controller connected to the GMI bus
on CS4:
gmi@70090000 {
gmi@70009000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
@ -120,7 +119,6 @@ gmi@70090000 {
reset-names = "gmi";
ranges = <4 0 0xd0000000 0xfffffff>;
can@4,0 {
reg = <4 0 0x100>;
nvidia,snor-mux-mode;

36
Bindings/clock/imx6sll-clock.txt Normal file
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@ -0,0 +1,36 @@
* Clock bindings for Freescale i.MX6 SLL
Required properties:
- compatible: Should be "fsl,imx6sll-ccm"
- reg: Address and length of the register set
- #clock-cells: Should be <1>
- clocks: list of clock specifiers, must contain an entry for each required
entry in clock-names
- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sll-clock.h
for the full list of i.MX6 SLL clock IDs.
Examples:
#include <dt-bindings/clock/imx6sll-clock.h>
clks: clock-controller@20c4000 {
compatible = "fsl,imx6sll-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
#clock-cells = <1>;
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
};
uart1: serial@2020000 {
compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
<&clks IMX6SLL_CLK_UART1_SERIAL>;
clock-names = "ipg", "per";
};

20
Bindings/clock/intc_stratix10.txt Normal file
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@ -0,0 +1,20 @@
Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be
"intel,stratix10-clkmgr"
- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
- #clock-cells : from common clock binding, shall be set to 1.
Example:
clkmgr: clock-controller@ffd10000 {
compatible = "intel,stratix10-clkmgr";
reg = <0xffd10000 0x1000>;
#clock-cells = <1>;
};

6
Bindings/clock/renesas,cpg-mssr.txt
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@ -22,7 +22,9 @@ Required Properties:
- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
- reg: Base address and length of the memory resource used by the CPG/MSSR
@ -32,8 +34,8 @@ Required Properties:
clock-names
- clock-names: List of external parent clock names. Valid names are:
- "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
r8a7795, r8a7796, r8a77970, r8a77995)
- "extalr" (r8a7795, r8a7796, r8a77970)
r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)
- "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
- "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
- #clock-cells: Must be 2

1
Bindings/clock/rockchip,rk3328-cru.txt
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@ -32,6 +32,7 @@ clock-output-names:
- "clkin_i2s" - external I2S clock - optional,
- "gmac_clkin" - external GMAC clock - optional
- "phy_50m_out" - output clock of the pll in the mac phy
- "hdmi_phy" - output clock of the hdmi phy pll - optional
Example: Clock controller node:

25
Bindings/clock/silabs,si544.txt Normal file
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@ -0,0 +1,25 @@
Binding for Silicon Labs 544 programmable I2C clock generator.
Reference
This binding uses the common clock binding[1]. Details about the device can be
found in the datasheet[2].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Si544 datasheet
https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
Required properties:
- compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
to the speed grade of the chip.
- reg: I2C device address.
- #clock-cells: From common clock bindings: Shall be 0.
Optional properties:
- clock-output-names: From common clock bindings. Recommended to be "si544".
Example:
si544: clock-controller@55 {
reg = <0x55>;
#clock-cells = <0>;
compatible = "silabs,si544b";
};

60
Bindings/clock/st,stm32mp1-rcc.txt Normal file
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@ -0,0 +1,60 @@
STMicroelectronics STM32 Peripheral Reset Clock Controller
==========================================================
The RCC IP is both a reset and a clock controller.
RCC makes also power management (resume/supend and wakeup interrupt).
Please also refer to reset.txt for common reset controller binding usage.
Please also refer to clock-bindings.txt for common clock controller
binding usage.
Required properties:
- compatible: "st,stm32mp1-rcc", "syscon"
- reg: should be register base and length as documented in the datasheet
- #clock-cells: 1, device nodes should specify the clock in their
"clocks" property, containing a phandle to the clock device node,
an index specifying the clock to use.
- #reset-cells: Shall be 1
- interrupts: Should contain a general interrupt line and a interrupt line
to the wake-up of processor (CSTOP).
Example:
rcc: rcc@50000000 {
compatible = "st,stm32mp1-rcc", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>,
<GIC_SPI 145 IRQ_TYPE_NONE>;
};
Specifying clocks
=================
All available clocks are defined as preprocessor macros in
dt-bindings/clock/stm32mp1-clks.h header and can be used in device
tree sources.
Specifying softreset control of devices
=======================================
Device nodes should specify the reset channel required in their "resets"
property, containing a phandle to the reset device node and an index specifying
which channel to use.
The index is the bit number within the RCC registers bank, starting from RCC
base address.
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
Where bit_offset is the bit offset within the register.
For example on STM32MP1, for LTDC reset:
ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
= 0x180 / 4 * 32 + 0 = 3072
The list of valid indices for STM32MP1 is available in:
include/dt-bindings/reset-controller/stm32mp1-resets.h
This file implements defines like:
#define LTDC_R 3072

4
Bindings/clock/sunxi-ccu.txt
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@ -20,6 +20,7 @@ Required properties :
- "allwinner,sun50i-a64-ccu"
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
- "allwinner,sun50i-h6-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
@ -31,6 +32,9 @@ Required properties :
- #clock-cells : must contain 1
- #reset-cells : must contain 1
For the main CCU on H6, one more clock is needed:
- "iosc": the SoC's internal frequency oscillator
For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
- "pll-periph": the SoC's peripheral PLL from the main CCU
- "iosc": the SoC's internal frequency oscillator

93
Bindings/clock/ti/davinci/da8xx-cfgchip.txt Normal file
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@ -0,0 +1,93 @@
Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP clocks
TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
registers call CFGCHIPn. Some of these registers function as clock
gates. This document describes the bindings for those clocks.
All of the clock nodes described below must be child nodes of a CFGCHIP node
(compatible = "ti,da830-cfgchip").
USB PHY clocks
--------------
Required properties:
- compatible: shall be "ti,da830-usb-phy-clocks".
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: phandles to the parent clocks corresponding to clock-names
- clock-names: shall be "fck", "usb_refclkin", "auxclk"
This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
eHRPWM Time Base Clock (TBCLK)
------------------------------
Required properties:
- compatible: shall be "ti,da830-tbclksync".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandle to the parent clock
- clock-names: shall be "fck"
PLL DIV4.5 divider
------------------
Required properties:
- compatible: shall be "ti,da830-div4p5ena".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandle to the parent clock
- clock-names: shall be "pll0_pllout"
EMIFA clock source (ASYNC1)
---------------------------
Required properties:
- compatible: shall be "ti,da850-async1-clksrc".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandles to the parent clocks corresponding to clock-names
- clock-names: shall be "pll0_sysclk3", "div4.5"
ASYNC3 clock source
-------------------
Required properties:
- compatible: shall be "ti,da850-async3-clksrc".
- #clock-cells: from common clock binding; shall be set to 0.
- clocks: phandles to the parent clocks corresponding to clock-names
- clock-names: shall be "pll0_sysclk2", "pll1_sysclk2"
Examples:
cfgchip: syscon@1417c {
compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
reg = <0x1417c 0x14>;
usb_phy_clk: usb-phy-clocks {
compatible = "ti,da830-usb-phy-clocks";
#clock-cells = <1>;
clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;
clock-names = "fck", "usb_refclkin", "auxclk";
};
ehrpwm_tbclk: ehrpwm_tbclk {
compatible = "ti,da830-tbclksync";
#clock-cells = <0>;
clocks = <&psc1 17>;
clock-names = "fck";
};
div4p5_clk: div4.5 {
compatible = "ti,da830-div4p5ena";
#clock-cells = <0>;
clocks = <&pll0_pllout>;
clock-names = "pll0_pllout";
};
async1_clk: async1 {
compatible = "ti,da850-async1-clksrc";
#clock-cells = <0>;
clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
clock-names = "pll0_sysclk3", "div4.5";
};
async3_clk: async3 {
compatible = "ti,da850-async3-clksrc";
#clock-cells = <0>;
clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
clock-names = "pll0_sysclk2", "pll1_sysclk2";
};
};
Also see:
- Documentation/devicetree/bindings/clock/clock-bindings.txt

96
Bindings/clock/ti/davinci/pll.txt Normal file
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@ -0,0 +1,96 @@
Binding for TI DaVinci PLL Controllers
The PLL provides clocks to most of the components on the SoC. In addition
to the PLL itself, this controller also contains bypasses, gates, dividers,
an multiplexers for various clock signals.
Required properties:
- compatible: shall be one of:
- "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
- "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
- reg: physical base address and size of the controller's register area.
- clocks: phandles corresponding to the clock names
- clock-names: names of the clock sources - depends on compatible string
- for "ti,da850-pll0", shall be "clksrc", "extclksrc"
- for "ti,da850-pll1", shall be "clksrc"
Optional properties:
- ti,clkmode-square-wave: Indicates that the the board is supplying a square
wave input on the OSCIN pin instead of using a crystal oscillator.
This property is only valid when compatible = "ti,da850-pll0".
Optional child nodes:
pllout
Describes the main PLL clock output (before POSTDIV). The node name must
be "pllout".
Required properties:
- #clock-cells: shall be 0
sysclk
Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
domains. The node name must be "sysclk". Consumers of this node should
use "n" in "SYSCLKn" as the index parameter for the clock cell.
Required properties:
- #clock-cells: shall be 1
auxclk
Describes the AUXCLK output of the PLL. The node name must be "auxclk".
This child node is only valid when compatible = "ti,da850-pll0".
Required properties:
- #clock-cells: shall be 0
obsclk
Describes the OBSCLK output of the PLL. The node name must be "obsclk".
Required properties:
- #clock-cells: shall be 0
Examples:
pll0: clock-controller@11000 {
compatible = "ti,da850-pll0";
reg = <0x11000 0x1000>;
clocks = <&ref_clk>, <&pll1_sysclk 3>;
clock-names = "clksrc", "extclksrc";
ti,clkmode-square-wave;
pll0_pllout: pllout {
#clock-cells = <0>;
};
pll0_sysclk: sysclk {
#clock-cells = <1>;
};
pll0_auxclk: auxclk {
#clock-cells = <0>;
};
pll0_obsclk: obsclk {
#clock-cells = <0>;
};
};
pll1: clock-controller@21a000 {
compatible = "ti,da850-pll1";
reg = <0x21a000 0x1000>;
clocks = <&ref_clk>;
clock-names = "clksrc";
pll0_sysclk: sysclk {
#clock-cells = <1>;
};
pll0_obsclk: obsclk {
#clock-cells = <0>;
};
};
Also see:
- Documentation/devicetree/bindings/clock/clock-bindings.txt

71
Bindings/clock/ti/davinci/psc.txt Normal file
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@ -0,0 +1,71 @@
Binding for TI DaVinci Power Sleep Controller (PSC)
The PSC provides power management, clock gating and reset functionality. It is
primarily used for clocking.
Required properties:
- compatible: shall be one of:
- "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
- "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
- reg: physical base address and size of the controller's register area
- #clock-cells: from common clock binding; shall be set to 1
- #power-domain-cells: from generic power domain binding; shall be set to 1.
- clocks: phandles to clocks corresponding to the clock-names property
- clock-names: list of parent clock names - depends on compatible value
- for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
"pll0_sysclk4", "pll0_sysclk6", "async1"
- for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
Optional properties:
- #reset-cells: from reset binding; shall be set to 1 - only applicable when
at least one local domain provides a local reset.
Consumers:
Clock, power domain and reset consumers shall use the local power domain
module ID (LPSC) as the index corresponding to the clock cell. Refer to
the device-specific datasheet to find these numbers. NB: Most local
domains only provide a clock/power domain and not a reset.
Examples:
psc0: clock-controller@10000 {
compatible = "ti,da850-psc0";
reg = <0x10000 0x1000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
<&pll0_sysclk 4>, <&pll0_sysclk 6>, <&async1_clk>;
clock_names = "pll0_sysclk1", "pll0_sysclk2",
"pll0_sysclk4", "pll0_sysclk6", "async1";
};
psc1: clock-controller@227000 {
compatible = "ti,da850-psc1";
reg = <0x227000 0x1000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>, <&async3_clk>;
clock_names = "pll0_sysclk2", "pll0_sysclk4", "async3";
};
/* consumer */
dsp: dsp@11800000 {
compatible = "ti,da850-dsp";
reg = <0x11800000 0x40000>,
<0x11e00000 0x8000>,
<0x11f00000 0x8000>,
<0x01c14044 0x4>,
<0x01c14174 0x8>;
reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
interrupt-parent = <&intc>;
interrupts = <28>;
clocks = <&psc0 15>;
power-domains = <&psc0 15>;
resets = <&psc0 15>;
};
Also see:
- Documentation/devicetree/bindings/clock/clock-bindings.txt
- Documentation/devicetree/bindings/power/power_domain.txt
- Documentation/devicetree/bindings/reset/reset.txt

3
Bindings/clock/ti/divider.txt
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@ -75,6 +75,9 @@ Optional properties:
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
see [2]
- ti,set-rate-parent : clk_set_rate is propagated to parent
- ti,latch-bit : latch the divider value to HW, only needed if the register
access requires this. As an example dra76x DPLL_GMAC H14 divider implements
such behavior.
Examples:
dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {

3
Bindings/clock/ti/mux.txt
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@ -48,6 +48,9 @@ Optional properties:
zero
- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
not supported by the composite-mux-clock subtype
- ti,latch-bit : latch the mux value to HW, only needed if the register
access requires this. As an example, dra7x DPLL_GMAC H14 muxing
implements such behavior.
Examples:

49
Bindings/connector/samsung,usb-connector-11pin.txt Normal file
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@ -0,0 +1,49 @@
Samsung micro-USB 11-pin connector
==================================
Samsung micro-USB 11-pin connector is an extension of micro-USB connector.
It is present in multiple Samsung mobile devices.
It has additional pins to route MHL traffic simultanously with USB.
The bindings are superset of usb-connector bindings for micro-USB connector[1].
Required properties:
- compatible: must be: "samsung,usb-connector-11pin", "usb-b-connector",
- type: must be "micro".
Required nodes:
- any data bus to the connector should be modeled using the OF graph bindings
specified in bindings/graph.txt, unless the bus is between parent node and
the connector. Since single connector can have multpile data buses every bus
has assigned OF graph port number as follows:
0: High Speed (HS),
3: Mobile High-Definition Link (MHL), specific to 11-pin Samsung micro-USB.
[1]: bindings/connector/usb-connector.txt
Example
-------
Micro-USB connector with HS lines routed via controller (MUIC) and MHL lines
connected to HDMI-MHL bridge (sii8620):
muic-max77843@66 {
...
usb_con: connector {
compatible = "samsung,usb-connector-11pin", "usb-b-connector";
label = "micro-USB";
type = "micro";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@3 {
reg = <3>;
usb_con_mhl: endpoint {
remote-endpoint = <&sii8620_mhl>;
};
};
};
};
};

75
Bindings/connector/usb-connector.txt Normal file
View File

@ -0,0 +1,75 @@
USB Connector
=============
USB connector node represents physical USB connector. It should be
a child of USB interface controller.
Required properties:
- compatible: describes type of the connector, must be one of:
"usb-a-connector",
"usb-b-connector",
"usb-c-connector".
Optional properties:
- label: symbolic name for the connector,
- type: size of the connector, should be specified in case of USB-A, USB-B
non-fullsize connectors: "mini", "micro".
Required nodes:
- any data bus to the connector should be modeled using the OF graph bindings
specified in bindings/graph.txt, unless the bus is between parent node and
the connector. Since single connector can have multpile data buses every bus
has assigned OF graph port number as follows:
0: High Speed (HS), present in all connectors,
1: Super Speed (SS), present in SS capable connectors,
2: Sideband use (SBU), present in USB-C.
Examples
--------
1. Micro-USB connector with HS lines routed via controller (MUIC):
muic-max77843@66 {
...
usb_con: connector {
compatible = "usb-b-connector";
label = "micro-USB";
type = "micro";
};
};
2. USB-C connector attached to CC controller (s2mm005), HS lines routed
to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
ccic: s2mm005@33 {
...
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb_con_hs: endpoint {
remote-endpoint = <&max77865_usbc_hs>;
};
};
port@1 {
reg = <1>;
usb_con_ss: endpoint {
remote-endpoint = <&usbdrd_phy_ss>;
};
};
port@2 {
reg = <2>;
usb_con_sbu: endpoint {
remote-endpoint = <&dp_aux>;
};
};
};
};
};

4
Bindings/cpufreq/cpufreq-dt.txt
View File

@ -18,8 +18,6 @@ Optional properties:
in unit of nanoseconds.
- voltage-tolerance: Specify the CPU voltage tolerance in percentage.
- #cooling-cells:
- cooling-min-level:
- cooling-max-level:
Please refer to Documentation/devicetree/bindings/thermal/thermal.txt.
Examples:
@ -40,8 +38,6 @@ cpus {
>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
cooling-min-level = <0>;
cooling-max-level = <2>;
};
cpu@1 {

4
Bindings/cpufreq/cpufreq-mediatek.txt
View File

@ -21,8 +21,6 @@ Optional properties:
flow is handled by hardware, hence no software "voltage tracking" is
needed.
- #cooling-cells:
- cooling-min-level:
- cooling-max-level:
Please refer to Documentation/devicetree/bindings/thermal/thermal.txt
for detail.
@ -67,8 +65,6 @@ Example 1 (MT7623 SoC):
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
cooling-min-level = <0>;
cooling-max-level = <7>;
};
cpu@1 {
device_type = "cpu";

9
Bindings/cris/axis.txt
View File

@ -1,9 +0,0 @@
Axis Communications AB
ARTPEC series SoC Device Tree Bindings
CRISv32 based SoCs are ETRAX FS and ARTPEC-3:
- compatible = "axis,crisv32";

8
Bindings/cris/boards.txt
View File

@ -1,8 +0,0 @@
Boards based on the CRIS SoCs:
Required root node properties:
- compatible = should be one or more of the following:
- "axis,dev88" - for Axis devboard 88 with ETRAX FS
Optional:

3
Bindings/crypto/arm-cryptocell.txt
View File

@ -1,7 +1,8 @@
Arm TrustZone CryptoCell cryptographic engine
Required properties:
- compatible: Should be "arm,cryptocell-712-ree".
- compatible: Should be one of: "arm,cryptocell-712-ree",
"arm,cryptocell-710-ree" or "arm,cryptocell-630p-ree".
- reg: Base physical address of the engine and length of memory mapped region.
- interrupts: Interrupt number for the device.

17
Bindings/crypto/fsl-sec4.txt
View File

@ -415,12 +415,27 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
value type: <u32>
Definition: LP register offset. default it is 0x34.
- clocks
Usage: optional, required if SNVS LP RTC requires explicit
enablement of clocks
Value type: <prop_encoded-array>
Definition: a clock specifier describing the clock required for
enabling and disabling SNVS LP RTC.
- clock-names
Usage: optional, required if SNVS LP RTC requires explicit
enablement of clocks
Value type: <string>
Definition: clock name string should be "snvs-rtc".
EXAMPLE
sec_mon_rtc_lp@1 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
interrupts = <93 2>;
regmap = <&snvs>;
offset = <0x34>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-rtc";
};
=====================================================================
@ -543,6 +558,8 @@ FULL EXAMPLE
regmap = <&sec_mon>;
offset = <0x34>;
interrupts = <93 2>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-rtc";
};
snvs-pwrkey@020cc000 {

6
Bindings/crypto/inside-secure-safexcel.txt
View File

@ -8,7 +8,11 @@ Required properties:
- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".
Optional properties:
- clocks: Reference to the crypto engine clock.
- clocks: Reference to the crypto engine clocks, the second clock is
needed for the Armada 7K/8K SoCs.
- clock-names: mandatory if there is a second clock, in this case the
name must be "core" for the first clock and "reg" for
the second one.
Example:

58
Bindings/display/bridge/renesas,lvds.txt Normal file
View File

@ -0,0 +1,58 @@
Renesas R-Car LVDS Encoder
==========================
These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
Gen2, R-Car Gen3 and RZ/G SoCs.
Required properties:
- compatible : Shall contain one of
- "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
- "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
- "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
- "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
- "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
- "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
- "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders
- "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders
- reg: Base address and length for the memory-mapped registers
- clocks: A phandle + clock-specifier pair for the functional clock
- resets: A phandle + reset specifier for the module reset
Required nodes:
The LVDS encoder has two video ports. Their connections are modelled using the
OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
- Video port 0 corresponds to the parallel RGB input
- Video port 1 corresponds to the LVDS output
Each port shall have a single endpoint.
Example:
lvds0: lvds@feb90000 {
compatible = "renesas,r8a7790-lvds";
reg = <0 0xfeb90000 0 0x1c>;
clocks = <&cpg CPG_MOD 726>;
resets = <&cpg 726>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};

13
Bindings/display/bridge/ti,ths8135.txt → Bindings/display/bridge/ti,ths813x.txt
View File

@ -1,11 +1,16 @@
THS8135 Video DAC
-----------------
THS8134 and THS8135 Video DAC
-----------------------------
This is the binding for Texas Instruments THS8135 Video DAC bridge.
This is the binding for Texas Instruments THS8134, THS8134A, THS8134B and
THS8135 Video DAC bridges.
Required properties:
- compatible: Must be "ti,ths8135"
- compatible: Must be one of
"ti,ths8134"
"ti,ths8134a," "ti,ths8134"
"ti,ths8134b", "ti,ths8134"
"ti,ths8135"
Required nodes:

1
Bindings/display/connector/dvi-connector.txt
View File

@ -10,6 +10,7 @@ Optional properties:
- analog: the connector has DVI analog pins
- digital: the connector has DVI digital pins
- dual-link: the connector has pins for DVI dual-link
- hpd-gpios: HPD GPIO number
Required nodes:
- Video port for DVI input

24
Bindings/display/etnaviv/etnaviv-drm.txt
View File

@ -1,23 +1,3 @@
Etnaviv DRM master device
=========================
The Etnaviv DRM master device is a virtual device needed to list all
Vivante GPU cores that comprise the GPU subsystem.
Required properties:
- compatible: Should be one of
"fsl,imx-gpu-subsystem"
"marvell,dove-gpu-subsystem"
- cores: Should contain a list of phandles pointing to Vivante GPU devices
example:
gpu-subsystem {
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu_2d>, <&gpu_3d>;
};
Vivante GPU core devices
========================
@ -32,7 +12,9 @@ Required properties:
- clocks: should contain one clock for entry in clock-names
see Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names:
- "bus": AXI/register clock
- "bus": AXI/master interface clock
- "reg": AHB/slave interface clock
(only required if GPU can gate slave interface independently)
- "core": GPU core clock
- "shader": Shader clock (only required if GPU has feature PIPE_3D)

26
Bindings/display/msm/dsi.txt
View File

@ -7,8 +7,6 @@ Required properties:
- reg: Physical base address and length of the registers of controller
- reg-names: The names of register regions. The following regions are required:
* "dsi_ctrl"
- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
be 0 or 1, since we have 2 DSI controllers at most for now.
- interrupts: The interrupt signal from the DSI block.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks.
@ -22,6 +20,8 @@ Required properties:
* "core"
For DSIv2, we need an additional clock:
* "src"
For DSI6G v2.0 onwards, we need also need the clock:
* "byte_intf"
- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
by a DSI PHY block. See [1] for details on clock bindings.
@ -88,21 +88,35 @@ Required properties:
* "qcom,dsi-phy-28nm-lp"
* "qcom,dsi-phy-20nm"
* "qcom,dsi-phy-28nm-8960"
- reg: Physical base address and length of the registers of PLL, PHY and PHY
regulator
* "qcom,dsi-phy-14nm"
* "qcom,dsi-phy-10nm"
- reg: Physical base address and length of the registers of PLL, PHY. Some
revisions require the PHY regulator base address, whereas others require the
PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions are required:
For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
* "dsi_pll"
* "dsi_phy"
* "dsi_phy_regulator"
For DSI 14nm and 10nm PHYs:
* "dsi_pll"
* "dsi_phy"
* "dsi_phy_lane"
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
be 0 or 1, since we have 2 DSI PHYs at most for now.
- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: Phandles to device clocks. See [1] for details on clock bindings.
- clock-names: the following clocks are required:
* "iface"
For 28nm HPM/LP, 28nm 8960 PHYs:
- vddio-supply: phandle to vdd-io regulator device node
For 20nm PHY:
- vddio-supply: phandle to vdd-io regulator device node
- vcca-supply: phandle to vcca regulator device node
For 14nm PHY:
- vcca-supply: phandle to vcca regulator device node
For 10nm PHY:
- vdds-supply: phandle to vdds regulator device node
Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY

31
Bindings/display/panel/arm,versatile-tft-panel.txt Normal file
View File

@ -0,0 +1,31 @@
ARM Versatile TFT Panels
These panels are connected to the daughterboards found on the
ARM Versatile reference designs.
This device node must appear as a child to a "syscon"-compatible
node.
Required properties:
- compatible: should be "arm,versatile-tft-panel"
Required subnodes:
- port: see display/panel/panel-common.txt, graph.txt
Example:
sysreg@0 {
compatible = "arm,versatile-sysreg", "syscon", "simple-mfd";
reg = <0x00000 0x1000>;
panel: display@0 {
compatible = "arm,versatile-tft-panel";
port {
panel_in: endpoint {
remote-endpoint = <&foo>;
};
};
};
};

12
Bindings/display/panel/auo,g104sn02.txt Normal file
View File

@ -0,0 +1,12 @@
AU Optronics Corporation 10.4" (800x600) color TFT LCD panel
Required properties:
- compatible: should be "auo,g104sn02"
- power-supply: as specified in the base binding
Optional properties:
- backlight: as specified in the base binding
- enable-gpios: as specified in the base binding
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.

5
Bindings/display/panel/display-timing.txt
View File

@ -80,6 +80,11 @@ The parameters are defined as:
| | v | | |
+----------+-------------------------------------+----------+-------+
Note: In addition to being used as subnode(s) of display-timings, the timing
subnode may also be used on its own. This is appropriate if only one mode
need be conveyed. In this case, the node should be named 'panel-timing'.
Example:
display-timings {

25
Bindings/display/panel/koe,tx31d200vm0baa.txt Normal file
View File

@ -0,0 +1,25 @@
Kaohsiung Opto-Electronics. TX31D200VM0BAA 12.3" HSXGA LVDS panel
This binding is compatible with the simple-panel binding, which is specified
in simple-panel.txt in this directory.
Required properties:
- compatible: should be "koe,tx31d200vm0baa"
Optional properties:
- backlight: phandle of the backlight device attached to the panel
Optional nodes:
- Video port for LVDS panel input.
Example:
panel {
compatible = "koe,tx31d200vm0baa";
backlight = <&backlight_lvds>;
port {
panel_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
};

2
Bindings/display/panel/orisetech,otm8009a.txt
View File

@ -9,6 +9,7 @@ Required properties:
Optional properties:
- reset-gpios: a GPIO spec for the reset pin (active low).
- power-supply: phandle of the regulator that provides the supply voltage.
Example:
&dsi {
@ -17,5 +18,6 @@ Example:
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
power-supply = <&v1v8>;
};
};

2
Bindings/display/panel/panel-common.txt
View File

@ -38,7 +38,7 @@ Display Timings
require specific display timings. The panel-timing subnode expresses those
timings as specified in the timing subnode section of the display timing
bindings defined in
Documentation/devicetree/bindings/display/display-timing.txt.
Documentation/devicetree/bindings/display/panel/display-timing.txt.
Connectivity

25
Bindings/display/panel/raydium,rm68200.txt Normal file
View File

@ -0,0 +1,25 @@
Raydium Semiconductor Corporation RM68200 5.5" 720p MIPI-DSI TFT LCD panel
The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD
panel connected using a MIPI-DSI video interface.
Required properties:
- compatible: "raydium,rm68200"
- reg: the virtual channel number of a DSI peripheral
Optional properties:
- reset-gpios: a GPIO spec for the reset pin (active low).
- power-supply: phandle of the regulator that provides the supply voltage.
- backlight: phandle of the backlight device attached to the panel.
Example:
&dsi {
...
panel@0 {
compatible = "raydium,rm68200";
reg = <0>;
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
power-supply = <&v1v8>;
backlight = <&pwm_backlight>;
};
};

4
Bindings/display/panel/simple-panel.txt
View File

@ -1,4 +1,8 @@
Simple display panel
====================
panel node
----------
Required properties:
- power-supply: See panel-common.txt

35
Bindings/display/renesas,du.txt
View File

@ -13,13 +13,10 @@ Required Properties:
- "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
- "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
- "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
- "renesas,du-r8a77970" for R8A77970 (R-Car V3M) compatible DU
- "renesas,du-r8a77995" for R8A77995 (R-Car D3) compatible DU
- reg: A list of base address and length of each memory resource, one for
each entry in the reg-names property.
- reg-names: Name of the memory resources. The DU requires one memory
resource for the DU core (named "du") and one memory resource for each
LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical
index).
- reg: the memory-mapped I/O registers base address and length
- interrupt-parent: phandle of the parent interrupt controller.
- interrupts: Interrupt specifiers for the DU interrupts.
@ -29,14 +26,13 @@ Required Properties:
- clock-names: Name of the clocks. This property is model-dependent.
- R8A7779 uses a single functional clock. The clock doesn't need to be
named.
- All other DU instances use one functional clock per channel and one
clock per LVDS encoder (if available). The functional clocks must be
named "du.x" with "x" being the channel numerical index. The LVDS clocks
must be named "lvds.x" with "x" being the LVDS encoder numerical index.
- In addition to the functional and encoder clocks, all DU versions also
support externally supplied pixel clocks. Those clocks are optional.
When supplied they must be named "dclkin.x" with "x" being the input
clock numerical index.
- All other DU instances use one functional clock per channel The
functional clocks must be named "du.x" with "x" being the channel
numerical index.
- In addition to the functional clocks, all DU versions also support
externally supplied pixel clocks. Those clocks are optional. When
supplied they must be named "dclkin.x" with "x" being the input clock
numerical index.
- vsps: A list of phandle and channel index tuples to the VSPs that handle
the memory interfaces for the DU channels. The phandle identifies the VSP
@ -63,15 +59,15 @@ corresponding to each DU output.
R8A7794 (R-Car E2) DPAD 0 DPAD 1 - -
R8A7795 (R-Car H3) DPAD 0 HDMI 0 HDMI 1 LVDS 0
R8A7796 (R-Car M3-W) DPAD 0 HDMI 0 LVDS 0 -
R8A77970 (R-Car V3M) DPAD 0 LVDS 0 - -
R8A77995 (R-Car D3) DPAD 0 LVDS 0 LVDS 1 -
Example: R8A7795 (R-Car H3) ES2.0 DU
du: display@feb00000 {
compatible = "renesas,du-r8a7795";
reg = <0 0xfeb00000 0 0x80000>,
<0 0xfeb90000 0 0x14>;
reg-names = "du", "lvds.0";
reg = <0 0xfeb00000 0 0x80000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
@ -79,9 +75,8 @@ Example: R8A7795 (R-Car H3) ES2.0 DU
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>,
<&cpg CPG_MOD 722>,
<&cpg CPG_MOD 721>,
<&cpg CPG_MOD 727>;
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
<&cpg CPG_MOD 721>;
clock-names = "du.0", "du.1", "du.2", "du.3";
vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
ports {

74
Bindings/display/rockchip/cdn-dp-rockchip.txt Normal file
View File

@ -0,0 +1,74 @@
Rockchip RK3399 specific extensions to the cdn Display Port
================================
Required properties:
- compatible: must be "rockchip,rk3399-cdn-dp"
- reg: physical base address of the controller and length
- clocks: from common clock binding: handle to dp clock.
- clock-names: from common clock binding:
Required elements: "core-clk" "pclk" "spdif" "grf"
- resets : a list of phandle + reset specifier pairs
- reset-names : string of reset names
Required elements: "apb", "core", "dptx", "spdif"
- power-domains : power-domain property defined with a phandle
to respective power domain.
- assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
- assigned-clock-rates : the DP core clk frequency, shall be: 100000000
- rockchip,grf: this soc should set GRF regs, so need get grf here.
- ports: contain a port nodes with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
contained 2 endpoints, connecting to the output of vop.
- phys: from general PHY binding: the phandle for the PHY device.
- extcon: extcon specifier for the Power Delivery
- #sound-dai-cells = it must be 1 if your system is using 2 DAIs: I2S, SPDIF
-------------------------------------------------------------------------------
Example:
cdn_dp: dp@fec00000 {
compatible = "rockchip,rk3399-cdn-dp";
reg = <0x0 0xfec00000 0x0 0x100000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
<&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
clock-names = "core-clk", "pclk", "spdif", "grf";
assigned-clocks = <&cru SCLK_DP_CORE>;
assigned-clock-rates = <100000000>;
power-domains = <&power RK3399_PD_HDCP>;
phys = <&tcphy0_dp>, <&tcphy1_dp>;
resets = <&cru SRST_DPTX_SPDIF_REC>;
reset-names = "spdif";
extcon = <&fusb0>, <&fusb1>;
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
dp_in: port {
#address-cells = <1>;
#size-cells = <0>;
dp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_dp>;
};
dp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_dp>;
};
};
};
};

2
Bindings/display/st,stm32-ltdc.txt
View File

@ -98,7 +98,7 @@ Example 2: DSI panel
compatible = "st,stm32-dsi";
reg = <0x40016c00 0x800>;
clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
clock-names = "ref", "pclk";
clock-names = "pclk", "ref";
resets = <&rcc STM32F4_APB2_RESET(DSI)>;
reset-names = "apb";

104
Bindings/display/sunxi/sun4i-drm.txt
View File

@ -64,6 +64,56 @@ Required properties:
first port should be the input endpoint. The second should be the
output, usually to an HDMI connector.
DWC HDMI TX Encoder
-------------------
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
with Allwinner's own PHY IP. It supports audio and video outputs and CEC.
These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
following device-specific properties.
Required properties:
- compatible: value must be one of:
* "allwinner,sun8i-a83t-dw-hdmi"
- reg: base address and size of memory-mapped region
- reg-io-width: See dw_hdmi.txt. Shall be 1.
- interrupts: HDMI interrupt number
- clocks: phandles to the clocks feeding the HDMI encoder
* iahb: the HDMI bus clock
* isfr: the HDMI register clock
* tmds: TMDS clock
- clock-names: the clock names mentioned above
- resets: phandle to the reset controller
- reset-names: must be "ctrl"
- phys: phandle to the DWC HDMI PHY
- phy-names: must be "phy"
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoint. The second should be the
output, usually to an HDMI connector.
DWC HDMI PHY
------------
Required properties:
- compatible: value must be one of:
* allwinner,sun8i-a83t-hdmi-phy
* allwinner,sun8i-h3-hdmi-phy
- reg: base address and size of memory-mapped region
- clocks: phandles to the clocks feeding the HDMI PHY
* bus: the HDMI PHY interface clock
* mod: the HDMI PHY module clock
- clock-names: the clock names mentioned above
- resets: phandle to the reset controller driving the PHY
- reset-names: must be "phy"
H3 HDMI PHY requires additional clock:
- pll-0: parent of phy clock
TV Encoder
----------
@ -94,24 +144,29 @@ Required properties:
* allwinner,sun7i-a20-tcon
* allwinner,sun8i-a33-tcon
* allwinner,sun8i-a83t-tcon-lcd
* allwinner,sun8i-a83t-tcon-tv
* allwinner,sun8i-v3s-tcon
* allwinner,sun9i-a80-tcon-lcd
* allwinner,sun9i-a80-tcon-tv
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the TCON. Three are needed:
- clocks: phandles to the clocks feeding the TCON.
- 'ahb': the interface clocks
- 'tcon-ch0': The clock driving the TCON channel 0
- 'tcon-ch0': The clock driving the TCON channel 0, if supported
- resets: phandles to the reset controllers driving the encoder
- "lcd": the reset line for the TCON channel 0
- "lcd": the reset line for the TCON
- "edp": the reset line for the eDP block (A80 only)
- clock-names: the clock names mentioned above
- reset-names: the reset names mentioned above
- clock-output-names: Name of the pixel clock created
- clock-output-names: Name of the pixel clock created, if TCON supports
channel 0.
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoint, the second one the output
The output may have multiple endpoints. The TCON has two channels,
The output may have multiple endpoints. TCON can have 1 or 2 channels,
usually with the first channel being used for the panels interfaces
(RGB, LVDS, etc.), and the second being used for the outputs that
require another controller (TV Encoder, HDMI, etc.). The endpoints
@ -119,11 +174,13 @@ Required properties:
channel the endpoint is associated to. If that property is not
present, the endpoint number will be used as the channel number.
On SoCs other than the A33 and V3s, there is one more clock required:
For TCONs with channel 0, there is one more clock required:
- 'tcon-ch0': The clock driving the TCON channel 0
For TCONs with channel 1, there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
On SoCs that support LVDS (all SoCs but the A13, H3, H5 and V3s), you
need one more reset line:
When TCON support LVDS (all TCONs except TV TCON on A83T and those found
in A13, H3, H5 and V3s SoCs), you need one more reset line:
- 'lvds': The reset line driving the LVDS logic
And on the A23, A31, A31s and A33, you need one more clock line:
@ -134,7 +191,7 @@ DRC
---
The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
(A31, A23, A33), allows to dynamically adjust pixel
(A31, A23, A33, A80), allows to dynamically adjust pixel
brightness/contrast based on histogram measurements for LCD content
adaptive backlight control.
@ -144,6 +201,7 @@ Required properties:
* allwinner,sun6i-a31-drc
* allwinner,sun6i-a31s-drc
* allwinner,sun8i-a33-drc
* allwinner,sun9i-a80-drc
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the DRC
@ -170,6 +228,7 @@ Required properties:
* allwinner,sun6i-a31-display-backend
* allwinner,sun7i-a20-display-backend
* allwinner,sun8i-a33-display-backend
* allwinner,sun9i-a80-display-backend
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the frontend and backend
@ -191,6 +250,28 @@ On the A33, some additional properties are required:
- resets and reset-names need to have a phandle to the SAT bus
resets, whose name will be "sat"
DEU
---
The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC,
can sharpen the display content in both luma and chroma channels.
Required properties:
- compatible: value must be one of:
* allwinner,sun9i-a80-deu
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the DEU
* ahb: the DEU interface clock
* mod: the DEU module clock
* ram: the DEU DRAM clock
- clock-names: the clock names mentioned above
- resets: phandles to the reset line driving the DEU
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
first port should be the input endpoints, the second one the outputs
Display Engine Frontend
-----------------------
@ -204,6 +285,7 @@ Required properties:
* allwinner,sun6i-a31-display-frontend
* allwinner,sun7i-a20-display-frontend
* allwinner,sun8i-a33-display-frontend
* allwinner,sun9i-a80-display-frontend
- reg: base address and size of the memory-mapped region.
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the frontend and backend
@ -226,6 +308,8 @@ supported.
Required properties:
- compatible: value must be one of:
* allwinner,sun8i-a83t-de2-mixer-0
* allwinner,sun8i-a83t-de2-mixer-1
* allwinner,sun8i-h3-de2-mixer-0
* allwinner,sun8i-v3s-de2-mixer
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
@ -256,7 +340,9 @@ Required properties:
* allwinner,sun7i-a20-display-engine
* allwinner,sun8i-a33-display-engine
* allwinner,sun8i-a83t-display-engine
* allwinner,sun8i-h3-display-engine
* allwinner,sun8i-v3s-display-engine
* allwinner,sun9i-a80-display-engine
- allwinner,pipelines: list of phandle to the display engine
frontends (DE 1.0) or mixers (DE 2.0) available.

4
Bindings/dma/brcm,bcm2835-dma.txt
View File

@ -74,8 +74,8 @@ Example:
bcm2835_i2s: i2s@7e203000 {
compatible = "brcm,bcm2835-i2s";
reg = < 0x7e203000 0x20>,
< 0x7e101098 0x02>;
reg = < 0x7e203000 0x24>;
clocks = <&clocks BCM2835_CLOCK_PCM>;
dmas = <&dma 2>,
<&dma 3>;

33
Bindings/dma/mtk-hsdma.txt Normal file
View File

@ -0,0 +1,33 @@
MediaTek High-Speed DMA Controller
==================================
This device follows the generic DMA bindings defined in dma/dma.txt.
Required properties:
- compatible: Must be one of
"mediatek,mt7622-hsdma": for MT7622 SoC
"mediatek,mt7623-hsdma": for MT7623 SoC
- reg: Should contain the register's base address and length.
- interrupts: Should contain a reference to the interrupt used by this
device.
- clocks: Should be the clock specifiers corresponding to the entry in
clock-names property.
- clock-names: Should contain "hsdma" entries.
- power-domains: Phandle to the power domain that the device is part of
- #dma-cells: The length of the DMA specifier, must be <1>. This one cell
in dmas property of a client device represents the channel
number.
Example:
hsdma: dma-controller@1b007000 {
compatible = "mediatek,mt7623-hsdma";
reg = <0 0x1b007000 0 0x1000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
clocks = <&ethsys CLK_ETHSYS_HSDMA>;
clock-names = "hsdma";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
#dma-cells = <1>;
};
DMA clients must use the format described in dma/dma.txt file.

4
Bindings/dma/qcom_bam_dma.txt
View File

@ -15,6 +15,10 @@ Required properties:
the secure world.
- qcom,controlled-remotely : optional, indicates that the bam is controlled by
remote proccessor i.e. execution environment.
- num-channels : optional, indicates supported number of DMA channels in a
remotely controlled bam.
- qcom,num-ees : optional, indicates supported number of Execution Environments
in a remotely controlled bam.
Example:

3
Bindings/dma/renesas,rcar-dmac.txt
View File

@ -18,6 +18,7 @@ Required Properties:
Examples with soctypes are:
- "renesas,dmac-r8a7743" (RZ/G1M)
- "renesas,dmac-r8a7745" (RZ/G1E)
- "renesas,dmac-r8a77470" (RZ/G1C)
- "renesas,dmac-r8a7790" (R-Car H2)
- "renesas,dmac-r8a7791" (R-Car M2-W)
- "renesas,dmac-r8a7792" (R-Car V2H)
@ -25,7 +26,9 @@ Required Properties:
- "renesas,dmac-r8a7794" (R-Car E2)
- "renesas,dmac-r8a7795" (R-Car H3)
- "renesas,dmac-r8a7796" (R-Car M3-W)
- "renesas,dmac-r8a77965" (R-Car M3-N)
- "renesas,dmac-r8a77970" (R-Car V3M)
- "renesas,dmac-r8a77980" (R-Car V3H)
- reg: base address and length of the registers block for the DMAC

1
Bindings/dma/renesas,usb-dmac.txt
View File

@ -11,6 +11,7 @@ Required Properties:
- "renesas,r8a7794-usb-dmac" (R-Car E2)
- "renesas,r8a7795-usb-dmac" (R-Car H3)
- "renesas,r8a7796-usb-dmac" (R-Car M3-W)
- "renesas,r8a77965-usb-dmac" (R-Car M3-N)
- reg: base address and length of the registers block for the DMAC
- interrupts: interrupt specifiers for the DMAC, one for each entry in
interrupt-names.

41
Bindings/dma/snps,dw-axi-dmac.txt Normal file
View File

@ -0,0 +1,41 @@
Synopsys DesignWare AXI DMA Controller
Required properties:
- compatible: "snps,axi-dma-1.01a"
- reg: Address range of the DMAC registers. This should include
all of the per-channel registers.
- interrupt: Should contain the DMAC interrupt number.
- interrupt-parent: Should be the phandle for the interrupt controller
that services interrupts for this device.
- dma-channels: Number of channels supported by hardware.
- snps,dma-masters: Number of AXI masters supported by the hardware.
- snps,data-width: Maximum AXI data width supported by hardware.
(0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
- snps,priority: Priority of channel. Array size is equal to the number of
dma-channels. Priority value must be programmed within [0:dma-channels-1]
range. (0 - minimum priority)
- snps,block-size: Maximum block size supported by the controller channel.
Array size is equal to the number of dma-channels.
Optional properties:
- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
in this property. If this property is missing the maximum AXI burst length
supported by DMAC is used. [1:256]
Example:
dmac: dma-controller@80000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x80000 0x400>;
clocks = <&core_clk>, <&cfgr_clk>;
clock-names = "core-clk", "cfgr-clk";
interrupt-parent = <&intc>;
interrupts = <27>;
dma-channels = <4>;
snps,dma-masters = <2>;
snps,data-width = <3>;
snps,block-size = <4096 4096 4096 4096>;
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <16>;
};

6
Bindings/dma/stm32-dma.txt
View File

@ -62,14 +62,14 @@ channel: a phandle to the DMA controller plus the following four integer cells:
0x1: medium
0x2: high
0x3: very high
4. A 32bit mask specifying the DMA FIFO threshold configuration which are device
dependent:
-bit 0-1: Fifo threshold
4. A 32bit bitfield value specifying DMA features which are device dependent:
-bit 0-1: DMA FIFO threshold selection
0x0: 1/4 full FIFO
0x1: 1/2 full FIFO
0x2: 3/4 full FIFO
0x3: full FIFO
Example:
usart1: serial@40011000 {

4
Bindings/eeprom/at24.txt
View File

@ -41,12 +41,16 @@ Required properties:
"nxp",
"ramtron",
"renesas",
"rohm",
"st",
Some vendors use different model names for chips which are just
variants of the above. Known such exceptions are listed below:
"nxp,se97b" - the fallback is "atmel,24c02",
"renesas,r1ex24002" - the fallback is "atmel,24c02"
"renesas,r1ex24128" - the fallback is "atmel,24c128"
"rohm,br24t01" - the fallback is "atmel,24c01"
- reg: The I2C address of the EEPROM.

151
Bindings/fsi/fsi.txt Normal file
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@ -0,0 +1,151 @@
FSI bus & engine generic device tree bindings
=============================================
The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
engines within those slaves. However, we have a facility to match devicetree
nodes to probed engines. This allows for fsi engines to expose non-probeable
busses, which are then exposed by the device tree. For example, an FSI engine
that is an I2C master - the I2C bus can be described by the device tree under
the engine's device tree node.
FSI masters may require their own DT nodes (to describe the master HW itself);
that requirement is defined by the master's implementation, and is described by
the fsi-master-* binding specifications.
Under the masters' nodes, we can describe the bus topology using nodes to
represent the FSI slaves and their slave engines. As a basic outline:
fsi-master {
/* top-level of FSI bus topology, bound to an FSI master driver and
* exposes an FSI bus */
fsi-slave@<link,id> {
/* this node defines the FSI slave device, and is handled
* entirely with FSI core code */
fsi-slave-engine@<addr> {
/* this node defines the engine endpoint & address range, which
* is bound to the relevant fsi device driver */
...
};
fsi-slave-engine@<addr> {
...
};
};
};
Note that since the bus is probe-able, some (or all) of the topology may
not be described; this binding only provides an optional facility for
adding subordinate device tree nodes as children of FSI engines.
FSI masters
-----------
FSI master nodes declare themselves as such with the "fsi-master" compatible
value. It's likely that an implementation-specific compatible value will
be needed as well, for example:
compatible = "fsi-master-gpio", "fsi-master";
Since the master nodes describe the top-level of the FSI topology, they also
need to declare the FSI-standard addressing scheme. This requires two cells for
addresses (link index and slave ID), and no size:
#address-cells = <2>;
#size-cells = <0>;
An optional boolean property can be added to indicate that a particular master
should not scan for connected devices at initialization time. This is
necessary in cases where a scan could cause arbitration issues with other
masters that may be present on the bus.
no-scan-on-init;
FSI slaves
----------
Slaves are identified by a (link-index, slave-id) pair, so require two cells
for an address identifier. Since these are not a range, no size cells are
required. For an example, a slave on link 1, with ID 2, could be represented
as:
cfam@1,2 {
reg = <1 2>;
[...];
}
Each slave provides an address-space, under which the engines are accessible.
That address space has a maximum of 23 bits, so we use one cell to represent
addresses and sizes in the slave address space:
#address-cells = <1>;
#size-cells = <1>;
FSI engines (devices)
---------------------
Engines are identified by their address under the slaves' address spaces. We
use a single cell for address and size. Engine nodes represent the endpoint
FSI device, and are passed to those FSI device drivers' ->probe() functions.
For example, for a slave using a single 0x400-byte page starting at address
0xc00:
engine@c00 {
reg = <0xc00 0x400>;
};
Full example
------------
Here's an example that illustrates:
- an FSI master
- connected to an FSI slave
- that contains an engine that is an I2C master
- connected to an I2C EEPROM
The FSI master may be connected to additional slaves, and slaves may have
additional engines, but they don't necessarily need to be describe in the
device tree if no extra platform information is required.
/* The GPIO-based FSI master node, describing the top level of the
* FSI bus
*/
gpio-fsi {
compatible = "fsi-master-gpio", "fsi-master";
#address-cells = <2>;
#size-cells = <0>;
/* A FSI slave (aka. CFAM) at link 0, ID 0. */
cfam@0,0 {
reg = <0 0>;
#address-cells = <1>;
#size-cells = <1>;
/* FSI engine at 0xc00, using a single page. In this example,
* it's an I2C master controller, so subnodes describe the
* I2C bus.
*/
i2c-controller@c00 {
reg = <0xc00 0x400>;
/* Engine-specific data. In this case, we're describing an
* I2C bus, so we're conforming to the generic I2C binding
*/
compatible = "some-vendor,fsi-i2c-controller";
#address-cells = <1>;
#size-cells = <1>;
/* I2C endpoint device: an Atmel EEPROM */
eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
pagesize = <64>;
};
};
};
};

97
Bindings/gpio/gpio-eic-sprd.txt Normal file
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@ -0,0 +1,97 @@
Spreadtrum EIC controller bindings
The EIC is the abbreviation of external interrupt controller, which can
be used only in input mode. The Spreadtrum platform has 2 EIC controllers,
one is in digital chip, and another one is in PMIC. The digital chip EIC
controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and
EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
module.
The EIC-debounce sub-module provides up to 8 source input signal
connections. A debounce mechanism is used to capture the input signals'
stable status (millisecond resolution) and a single-trigger mechanism
is introduced into this sub-module to enhance the input event detection
reliability. In addition, this sub-module's clock can be shut off
automatically to reduce power dissipation. Moreover the debounce range
is from 1ms to 4s with a step size of 1ms. The input signal will be
ignored if it is asserted for less than 1 ms.
The EIC-latch sub-module is used to latch some special power down signals
and generate interrupts, since the EIC-latch does not depend on the APB
clock to capture signals.
The EIC-async sub-module uses a 32kHz clock to capture the short signals
(microsecond resolution) to generate interrupts by level or edge trigger.
The EIC-sync is similar with GPIO's input function, which is a synchronized
signal input register. It can generate interrupts by level or edge trigger
when detecting input signals.
Required properties:
- compatible: Should be one of the following:
"sprd,sc9860-eic-debounce",
"sprd,sc9860-eic-latch",
"sprd,sc9860-eic-async",
"sprd,sc9860-eic-sync",
"sprd,sc27xx-eic".
- reg: Define the base and range of the I/O address space containing
the GPIO controller registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be <2>. The first cell is the gpio number and
the second cell is used to specify optional parameters.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be <2>. Specifies the number of cells needed
to encode interrupt source.
- interrupts: Should be the port interrupt shared by all the gpios.
Example:
eic_debounce: gpio@40210000 {
compatible = "sprd,sc9860-eic-debounce";
reg = <0 0x40210000 0 0x80>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
eic_latch: gpio@40210080 {
compatible = "sprd,sc9860-eic-latch";
reg = <0 0x40210080 0 0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
eic_async: gpio@402100a0 {
compatible = "sprd,sc9860-eic-async";
reg = <0 0x402100a0 0 0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
eic_sync: gpio@402100c0 {
compatible = "sprd,sc9860-eic-sync";
reg = <0 0x402100c0 0 0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
};
pmic_eic: gpio@300 {
compatible = "sprd,sc27xx-eic";
reg = <0x300>;
interrupt-parent = <&sc2731_pmic>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

22
Bindings/gpio/gpio-etraxfs.txt
View File

@ -1,22 +0,0 @@
Axis ETRAX FS General I/O controller bindings
Required properties:
- compatible: one of:
- "axis,etraxfs-gio"
- "axis,artpec3-gio"
- reg: Physical base address and length of the controller's registers.
- #gpio-cells: Should be 3
- The first cell is the gpio offset number.
- The second cell is reserved and is currently unused.
- The third cell is the port number (hex).
- gpio-controller: Marks the device node as a GPIO controller.
Example:
gio: gpio@b001a000 {
compatible = "axis,etraxfs-gio";
reg = <0xb001a000 0x1000>;
gpio-controller;
#gpio-cells = <3>;
};

2
Bindings/gpio/gpio-pca953x.txt
View File

@ -16,6 +16,8 @@ Required properties:
nxp,pca9574
nxp,pca9575
nxp,pca9698
nxp,pcal6524
nxp,pcal9555a
maxim,max7310
maxim,max7312
maxim,max7313

28
Bindings/gpio/gpio-sprd.txt Normal file
View File

@ -0,0 +1,28 @@
Spreadtrum GPIO controller bindings
The controller's registers are organized as sets of sixteen 16-bit
registers with each set controlling a bank of up to 16 pins. A single
interrupt is shared for all of the banks handled by the controller.
Required properties:
- compatible: Should be "sprd,sc9860-gpio".
- reg: Define the base and range of the I/O address space containing
the GPIO controller registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be <2>. The first cell is the gpio number and
the second cell is used to specify optional parameters.
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be <2>. Specifies the number of cells needed
to encode interrupt source.
- interrupts: Should be the port interrupt shared by all the gpios.
Example:
ap_gpio: gpio@40280000 {
compatible = "sprd,sc9860-gpio";
reg = <0 0x40280000 0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
};

45
Bindings/gpio/gpio-tz1090-pdc.txt
View File

@ -1,45 +0,0 @@
ImgTec TZ1090 PDC GPIO Controller
Required properties:
- compatible: Compatible property value should be "img,tz1090-pdc-gpio".
- reg: Physical base address of the controller and length of memory mapped
region. This starts at and cover the SOC_GPIO_CONTROL registers.
- gpio-controller: Specifies that the node is a gpio controller.
- #gpio-cells: Should be 2. The syntax of the gpio specifier used by client
nodes should have the following values.
<[phandle of the gpio controller node]
[PDC gpio number]
[gpio flags]>
Values for gpio specifier:
- GPIO number: a value in the range 0 to 6.
- GPIO flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
Only the following flags are supported:
GPIO_ACTIVE_HIGH
GPIO_ACTIVE_LOW
Optional properties:
- gpio-ranges: Mapping to pin controller pins (as described in
Documentation/devicetree/bindings/gpio/gpio.txt)
- interrupts: Individual syswake interrupts (other GPIOs cannot interrupt)
Example:
pdc_gpios: gpio-controller@2006500 {
gpio-controller;
#gpio-cells = <2>;
compatible = "img,tz1090-pdc-gpio";
reg = <0x02006500 0x100>;
interrupt-parent = <&pdc>;
interrupts = <8 IRQ_TYPE_NONE>, /* Syswake 0 */
<9 IRQ_TYPE_NONE>, /* Syswake 1 */
<10 IRQ_TYPE_NONE>; /* Syswake 2 */
gpio-ranges = <&pdc_pinctrl 0 0 7>;
};

88
Bindings/gpio/gpio-tz1090.txt
View File

@ -1,88 +0,0 @@
ImgTec TZ1090 GPIO Controller
Required properties:
- compatible: Compatible property value should be "img,tz1090-gpio".
- reg: Physical base address of the controller and length of memory mapped
region.
- #address-cells: Should be 1 (for bank subnodes)
- #size-cells: Should be 0 (for bank subnodes)
- Each bank of GPIOs should have a subnode to represent it.
Bank subnode required properties:
- reg: Index of bank in the range 0 to 2.
- gpio-controller: Specifies that the node is a gpio controller.
- #gpio-cells: Should be 2. The syntax of the gpio specifier used by client
nodes should have the following values.
<[phandle of the gpio controller node]
[gpio number within the gpio bank]
[gpio flags]>
Values for gpio specifier:
- GPIO number: a value in the range 0 to 29.
- GPIO flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
Only the following flags are supported:
GPIO_ACTIVE_HIGH
GPIO_ACTIVE_LOW
Bank subnode optional properties:
- gpio-ranges: Mapping to pin controller pins (as described in
Documentation/devicetree/bindings/gpio/gpio.txt)
- interrupts: Interrupt for the entire bank
- interrupt-controller: Specifies that the node is an interrupt controller
- #interrupt-cells: Should be 2. The syntax of the interrupt specifier used by
client nodes should have the following values.
<[phandle of the interurupt controller]
[gpio number within the gpio bank]
[irq flags]>
Values for irq specifier:
- GPIO number: a value in the range 0 to 29
- IRQ flags: value to describe edge and level triggering, as defined in
<dt-bindings/interrupt-controller/irq.h>. Only the following flags are
supported:
IRQ_TYPE_EDGE_RISING
IRQ_TYPE_EDGE_FALLING
IRQ_TYPE_EDGE_BOTH
IRQ_TYPE_LEVEL_HIGH
IRQ_TYPE_LEVEL_LOW
Example:
gpios: gpio-controller@2005800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "img,tz1090-gpio";
reg = <0x02005800 0x90>;
/* bank 0 with an interrupt */
gpios0: bank@0 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
reg = <0>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 30>;
interrupt-controller;
};
/* bank 2 without interrupt */
gpios2: bank@2 {
#gpio-cells = <2>;
reg = <2>;
gpio-controller;
gpio-ranges = <&pinctrl 0 60 30>;
};
};

7
Bindings/gpio/gpio.txt
View File

@ -151,9 +151,9 @@ in a lot of designs, some using all 32 bits, some using 18 and some using
first 18 GPIOs, at local offset 0 .. 17, are in use.
If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an
additional bitmask is needed to specify which GPIOs are actually in use,
and which are dummies. The bindings for this case has not yet been
specified, but should be specified if/when such hardware appears.
additional set of tuples is needed to specify which GPIOs are unusable, with
the gpio-reserved-ranges binding. This property indicates the start and size
of the GPIOs that can't be used.
Optionally, a GPIO controller may have a "gpio-line-names" property. This is
an array of strings defining the names of the GPIO lines going out of the
@ -178,6 +178,7 @@ gpio-controller@00000000 {
gpio-controller;
#gpio-cells = <2>;
ngpios = <18>;
gpio-reserved-ranges = <0 4>, <12 2>;
gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",
"LED G", "LED B", "Col A", "Col B", "Col C", "Col D",
"Row A", "Row B", "Row C", "Row D", "NMI button",

27
Bindings/gpio/nintendo,hollywood-gpio.txt Normal file
View File

@ -0,0 +1,27 @@
Nintendo Wii (Hollywood) GPIO controller
Required properties:
- compatible: "nintendo,hollywood-gpio
- reg: Physical base address and length of the controller's registers.
- gpio-controller: Marks the device node as a GPIO controller.
- #gpio-cells: Should be <2>. The first cell is the pin number and the
second cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted).
Optional properties:
- ngpios: see Documentation/devicetree/bindings/gpio/gpio.txt
- interrupt-controller: Marks the device node as an interrupt controller.
- #interrupt-cells: Should be two.
- interrupts: Interrupt specifier for the controller's Broadway (PowerPC)
interrupt.
- interrupt-parent: phandle of the parent interrupt controller.
Example:
GPIO: gpio@d8000c0 {
#gpio-cells = <2>;
compatible = "nintendo,hollywood-gpio";
reg = <0x0d8000c0 0x40>;
gpio-controller;
ngpios = <24>;
}

30
Bindings/gpio/raspberrypi,firmware-gpio.txt Normal file
View File

@ -0,0 +1,30 @@
Raspberry Pi GPIO expander
The Raspberry Pi 3 GPIO expander is controlled by the VC4 firmware. The
firmware exposes a mailbox interface that allows the ARM core to control the
GPIO lines on the expander.
The Raspberry Pi GPIO expander node must be a child node of the Raspberry Pi
firmware node.
Required properties:
- compatible : Should be "raspberrypi,firmware-gpio"
- gpio-controller : Marks the device node as a gpio controller
- #gpio-cells : Should be two. The first cell is the pin number, and
the second cell is used to specify the gpio polarity:
0 = active high
1 = active low
Example:
firmware: firmware-rpi {
compatible = "raspberrypi,bcm2835-firmware";
mboxes = <&mailbox>;
expgpio: gpio {
compatible = "raspberrypi,firmware-gpio";
gpio-controller;
#gpio-cells = <2>;
};
};

1
Bindings/gpu/arm,mali-utgard.txt
View File

@ -10,6 +10,7 @@ Required properties:
* And, optionally, one of the vendor specific compatible:
+ allwinner,sun4i-a10-mali
+ allwinner,sun7i-a20-mali
+ allwinner,sun8i-h3-mali
+ allwinner,sun50i-h5-mali
+ amlogic,meson-gxbb-mali
+ amlogic,meson-gxl-mali

2
Bindings/i2c/i2c-rcar.txt
View File

@ -13,7 +13,9 @@ Required properties:
"renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC.
"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
"renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC.
"renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
"renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC.
"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
"renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
device.

1
Bindings/i2c/i2c-sh_mobile.txt
View File

@ -13,6 +13,7 @@ Required properties:
- "renesas,iic-r8a7794" (R-Car E2)
- "renesas,iic-r8a7795" (R-Car H3)
- "renesas,iic-r8a7796" (R-Car M3-W)
- "renesas,iic-r8a77965" (R-Car M3-N)
- "renesas,iic-sh73a0" (SH-Mobile AG5)
- "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1
compatible device)

29
Bindings/i2c/i2c-synquacer.txt Normal file
View File

@ -0,0 +1,29 @@
Socionext SynQuacer I2C
Required properties:
- compatible : Must be "socionext,synquacer-i2c"
- reg : Offset and length of the register set for the device
- interrupts : A single interrupt specifier
- #address-cells : Must be <1>;
- #size-cells : Must be <0>;
- clock-names : Must contain "pclk".
- clocks : Must contain an entry for each name in clock-names.
(See the common clock bindings.)
Optional properties:
- clock-frequency : Desired I2C bus clock frequency in Hz. As only Normal and
Fast modes are supported, possible values are 100000 and
400000.
Example :
i2c@51210000 {
compatible = "socionext,synquacer-i2c";
reg = <0x51210000 0x1000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "pclk";
clocks = <&clk_i2c>;
clock-frequency = <400000>;
};

48
Bindings/iio/adc/axp20x_adc.txt Normal file
View File

@ -0,0 +1,48 @@
* X-Powers AXP ADC bindings
Required properties:
- compatible: should be one of:
- "x-powers,axp209-adc",
- "x-powers,axp221-adc",
- "x-powers,axp813-adc",
- #io-channel-cells: should be 1,
Example:
&axp22x {
adc {
compatible = "x-powers,axp221-adc";
#io-channel-cells = <1>;
};
};
ADC channels and their indexes per variant:
AXP209
------
0 | acin_v
1 | acin_i
2 | vbus_v
3 | vbus_i
4 | pmic_temp
5 | gpio0_v
6 | gpio1_v
7 | ipsout_v
8 | batt_v
9 | batt_chrg_i
10 | batt_dischrg_i
AXP22x
------
0 | pmic_temp
1 | batt_v
2 | batt_chrg_i
3 | batt_dischrg_i
AXP813
------
0 | pmic_temp
1 | gpio0_v
2 | batt_v
3 | batt_chrg_i
4 | batt_dischrg_i

8
Bindings/iio/adc/st,stm32-dfsdm-adc.txt
View File

@ -32,6 +32,10 @@ Optional properties:
to "clock" property. Frequency must be a multiple of the rcc
clock frequency. If not, SPI CLKOUT frequency will not be
accurate.
- pinctrl-names: Set to "default".
- pinctrl-0: List of phandles pointing to pin configuration
nodes to set pins in mode of operation for dfsdm
on external pin.
Contents of a STM32 DFSDM child nodes:
--------------------------------------
@ -68,8 +72,8 @@ Optional properties:
- st,adc-channel-types: Single-ended channel input type.
- "SPI_R": SPI with data on rising edge (default)
- "SPI_F": SPI with data on falling edge
- "MANCH_R": manchester codec, rising edge = logic 0
- "MANCH_F": manchester codec, falling edge = logic 1
- "MANCH_R": manchester codec, rising edge = logic 0, falling edge = logic 1
- "MANCH_F": manchester codec, rising edge = logic 1, falling edge = logic 0
- st,adc-channel-clk-src: Conversion clock source.
- "CLKIN": external SPI clock (CLKIN x)
- "CLKOUT": internal SPI clock (CLKOUT) (default)

27
Bindings/iio/potentiometer/ad5272.txt Normal file
View File

@ -0,0 +1,27 @@
* Analog Devices AD5272 digital potentiometer
The node for this device must be a child node of a I2C controller, hence
all mandatory properties for your controller must be specified. See directory:
Documentation/devicetree/bindings/i2c
for more details.
Required properties:
- compatible: Must be one of the following, depending on the model:
adi,ad5272-020
adi,ad5272-050
adi,ad5272-100
adi,ad5274-020
adi,ad5274-100
Optional properties:
- reset-gpios: GPIO specification for the RESET input. This is an
active low signal to the AD5272.
Example:
ad5272: potentiometer@2f {
reg = <0x2F>;
compatible = "adi,ad5272-020";
reset-gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>;
};

28
Bindings/iio/temperature/mlx90632.txt Normal file
View File

@ -0,0 +1,28 @@
* Melexis MLX90632 contactless Infra Red temperature sensor
Link to datasheet: https://www.melexis.com/en/documents/documentation/datasheets/datasheet-mlx90632
There are various applications for the Infra Red contactless temperature sensor
and MLX90632 is most suitable for consumer applications where measured object
temperature is in range between -20 to 200 degrees Celsius with relative error
of measurement below 1 degree Celsius in object temperature range for
industrial applications. Since it can operate and measure ambient temperature
in range of -20 to 85 degrees Celsius it is suitable also for outdoor use.
Be aware that electronics surrounding the sensor can increase ambient
temperature. MLX90632 can be calibrated to reduce the housing effect via
already existing EEPROM parameters.
Since measured object emissivity effects Infra Red energy emitted, emissivity
should be set before requesting the object temperature.
Required properties:
- compatible: should be "melexis,mlx90632"
- reg: the I2C address of the sensor (default 0x3a)
Example:
mlx90632@3a {
compatible = "melexis,mlx90632";
reg = <0x3a>;
};

7
Bindings/input/atmel,maxtouch.txt
View File

@ -4,6 +4,13 @@ Required properties:
- compatible:
atmel,maxtouch
The following compatibles have been used in various products but are
deprecated:
atmel,qt602240_ts
atmel,atmel_mxt_ts
atmel,atmel_mxt_tp
atmel,mXT224
- reg: The I2C address of the device
- interrupts: The sink for the touchpad's IRQ output

8
Bindings/input/gpio-keys.txt
View File

@ -26,6 +26,14 @@ Optional subnode-properties:
If not specified defaults to 5.
- wakeup-source: Boolean, button can wake-up the system.
(Legacy property supported: "gpio-key,wakeup")
- wakeup-event-action: Specifies whether the key should wake the
system when asserted, when deasserted, or both. This property is
only valid for keys that wake up the system (e.g., when the
"wakeup-source" property is also provided).
Supported values are defined in linux-event-codes.h:
EV_ACT_ASSERTED - asserted
EV_ACT_DEASSERTED - deasserted
EV_ACT_ANY - both asserted and deasserted
- linux,can-disable: Boolean, indicates that button is connected
to dedicated (not shared) interrupt which can be disabled to
suppress events from the button.

22
Bindings/input/zii,rave-sp-pwrbutton.txt Normal file
View File

@ -0,0 +1,22 @@
Zodiac Inflight Innovations RAVE Supervisory Processor Power Button Bindings
RAVE SP input device is a "MFD cell" device corresponding to power
button functionality of RAVE Supervisory Processor. It is expected
that its Device Tree node is specified as a child of the node
corresponding to the parent RAVE SP device (as documented in
Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
Required properties:
- compatible: Should be "zii,rave-sp-pwrbutton"
Example:
rave-sp {
compatible = "zii,rave-sp-rdu1";
current-speed = <38400>;
pwrbutton {
compatible = "zii,rave-sp-pwrbutton";
};
}

19
Bindings/interrupt-controller/andestech,ativic32.txt Normal file
View File

@ -0,0 +1,19 @@
* Andestech Internal Vector Interrupt Controller
The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller
suitable for a simpler SoC platform not requiring a more sophisticated and
bigger External Vector Interrupt Controller.
Main node required properties:
- compatible : should at least contain "andestech,ativic32".
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts
Examples:
intc: interrupt-controller {
compatible = "andestech,ativic32";
#interrupt-cells = <1>;
interrupt-controller;
};

23
Bindings/interrupt-controller/axis,crisv32-intc.txt
View File

@ -1,23 +0,0 @@
* CRISv32 Interrupt Controller
Interrupt controller for the CRISv32 SoCs.
Main node required properties:
- compatible : should be:
"axis,crisv32-intc"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The type shall be a <u32> and the value shall be 1.
- reg: physical base address and size of the intc registers map.
Example:
intc: interrupt-controller {
compatible = "axis,crisv32-intc";
reg = <0xb001c000 0x1000>;
interrupt-controller;
#interrupt-cells = <1>;
};

22
Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt Normal file
View File

@ -0,0 +1,22 @@
Microsemi Ocelot SoC ICPU Interrupt Controller
Required properties:
- compatible : should be "mscc,ocelot-icpu-intr"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
- interrupt-parent : phandle of the CPU interrupt controller.
- interrupts : Specifies the CPU interrupt the controller is connected to.
Example:
intc: interrupt-controller@70000070 {
compatible = "mscc,ocelot-icpu-intr";
reg = <0x70000070 0x70>;
#interrupt-cells = <1>;
interrupt-controller;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
};

78
Bindings/interrupt-controller/qcom,pdc.txt Normal file
View File

@ -0,0 +1,78 @@
PDC interrupt controller
Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
Power Domain Controller (PDC) that is on always-on domain. In addition to
providing power control for the power domains, the hardware also has an
interrupt controller that can be used to help detect edge low interrupts as
well detect interrupts when the GIC is non-operational.
GIC is parent interrupt controller at the highest level. Platform interrupt
controller PDC is next in hierarchy, followed by others. Drivers requiring
wakeup capabilities of their device interrupts routed through the PDC, must
specify PDC as their interrupt controller and request the PDC port associated
with the GIC interrupt. See example below.
Properties:
- compatible:
Usage: required
Value type: <string>
Definition: Should contain "qcom,<soc>-pdc"
- "qcom,sdm845-pdc": For SDM845
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: Specifies the base physical address for PDC hardware.
- interrupt-cells:
Usage: required
Value type: <u32>
Definition: Specifies the number of cells needed to encode an interrupt
source.
Must be 2.
The first element of the tuple is the PDC pin for the
interrupt.
The second element is the trigger type.
- interrupt-parent:
Usage: required
Value type: <phandle>
Definition: Specifies the interrupt parent necessary for hierarchical
domain to operate.
- interrupt-controller:
Usage: required
Value type: <bool>
Definition: Identifies the node as an interrupt controller.
- qcom,pdc-ranges:
Usage: required
Value type: <u32 array>
Definition: Specifies the PDC pin offset and the number of PDC ports.
The tuples indicates the valid mapping of valid PDC ports
and their hwirq mapping.
The first element of the tuple is the starting PDC port.
The second element is the GIC hwirq number for the PDC port.
The third element is the number of interrupts in sequence.
Example:
pdc: interrupt-controller@b220000 {
compatible = "qcom,sdm845-pdc";
reg = <0xb220000 0x30000>;
qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
DT binding of a device that wants to use the GIC SPI 514 as a wakeup
interrupt, must do -
wake-device {
interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
};
In this case interrupt 514 would be mapped to port 2 on the PDC as defined by
the qcom,pdc-ranges property.

5
Bindings/iommu/renesas,ipmmu-vmsa.txt
View File

@ -11,6 +11,8 @@ Required Properties:
the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.
- "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.
- "renesas,ipmmu-r8a7743" for the R8A7743 (RZ/G1M) IPMMU.
- "renesas,ipmmu-r8a7745" for the R8A7745 (RZ/G1E) IPMMU.
- "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.
- "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.
- "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.
@ -19,7 +21,8 @@ Required Properties:
- "renesas,ipmmu-r8a7796" for the R8A7796 (R-Car M3-W) IPMMU.
- "renesas,ipmmu-r8a77970" for the R8A77970 (R-Car V3M) IPMMU.
- "renesas,ipmmu-r8a77995" for the R8A77995 (R-Car D3) IPMMU.
- "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU.
- "renesas,ipmmu-vmsa" for generic R-Car Gen2 or RZ/G1 VMSA-compatible
IPMMU.
- reg: Base address and size of the IPMMU registers.
- interrupts: Specifiers for the MMU fault interrupts. For instances that

7
Bindings/iommu/rockchip,iommu.txt
View File

@ -14,6 +14,11 @@ Required properties:
"single-master" device, and needs no additional information
to associate with its master device. See:
Documentation/devicetree/bindings/iommu/iommu.txt
- clocks : A list of clocks required for the IOMMU to be accessible by
the host CPU.
- clock-names : Should contain the following:
"iface" - Main peripheral bus clock (PCLK/HCL) (required)
"aclk" - AXI bus clock (required)
Optional properties:
- rockchip,disable-mmu-reset : Don't use the mmu reset operation.
@ -27,5 +32,7 @@ Example:
reg = <0xff940300 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
};

25
Bindings/ipmi/aspeed-kcs-bmc.txt Normal file
View File

@ -0,0 +1,25 @@
* Aspeed KCS (Keyboard Controller Style) IPMI interface
The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
(Baseboard Management Controllers) and the KCS interface can be
used to perform in-band IPMI communication with their host.
Required properties:
- compatible : should be one of
"aspeed,ast2400-kcs-bmc"
"aspeed,ast2500-kcs-bmc"
- interrupts : interrupt generated by the controller
- kcs_chan : The LPC channel number in the controller
- kcs_addr : The host CPU IO map address
Example:
kcs3: kcs3@0 {
compatible = "aspeed,ast2500-kcs-bmc";
reg = <0x0 0x80>;
interrupts = <8>;
kcs_chan = <3>;
kcs_addr = <0xCA2>;
status = "okay";
};

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