cxgbe(4): Update the firmware interface header.
This allows the driver to be updated for the next firmware without waiting for it to be released. MFC after: 2 weeks Sponsored by: Chelsio Communications
This commit is contained in:
Navdeep Parhar
parent
7511645efa
commit
e56d731b7d
@ -142,6 +142,7 @@ enum fw_wr_opcodes {
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FW_ISCSI_TX_DATA_WR = 0x45,
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FW_PTP_TX_PKT_WR = 0x46,
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FW_TLSTX_DATA_WR = 0x68,
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FW_TLS_TUNNEL_OFLD_WR = 0x69,
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FW_CRYPTO_LOOKASIDE_WR = 0x6d,
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FW_COISCSI_TGT_WR = 0x70,
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FW_COISCSI_TGT_CONN_WR = 0x71,
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@ -2200,6 +2201,11 @@ enum fw_chnet_ifconf_wr_subop {
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FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING4,
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FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING6,
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FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING4,
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FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING6,
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FW_CHNET_IFCONF_WR_SUBOP_PMTU6_CLEAR,
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FW_CHNET_IFCONF_WR_SUBOP_MAX,
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};
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@ -2228,7 +2234,8 @@ struct fw_chnet_ifconf_wr {
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} mac;
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} u;
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struct fw_chnet_ifconf_params {
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__be32 r0;
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__be16 ping_pldsize;
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__be16 r0;
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__be16 vlanid;
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__be16 mtu;
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union fw_chnet_ifconf_addr_type {
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@ -4080,6 +4087,13 @@ struct fw_crypto_lookaside_wr {
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(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \
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M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
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struct fw_tls_tunnel_ofld_wr {
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__be32 op_compl;
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__be32 flowid_len16;
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__be32 plen;
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__be32 r4;
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};
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/******************************************************************************
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* C O M M A N D s
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*********************/
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@ -4137,6 +4151,7 @@ enum fw_cmd_opcodes {
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FW_DEVLOG_CMD = 0x25,
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FW_WATCHDOG_CMD = 0x27,
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FW_CLIP_CMD = 0x28,
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FW_CLIP2_CMD = 0x29,
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FW_CHNET_IFACE_CMD = 0x26,
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FW_FCOE_RES_INFO_CMD = 0x31,
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FW_FCOE_LINK_CMD = 0x32,
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@ -4752,6 +4767,22 @@ enum fw_params_mnem {
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/*
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* device parameters
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*/
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#define S_FW_PARAMS_PARAM_FILTER_MODE 16
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#define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff
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#define V_FW_PARAMS_PARAM_FILTER_MODE(x) \
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((x) << S_FW_PARAMS_PARAM_FILTER_MODE)
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#define G_FW_PARAMS_PARAM_FILTER_MODE(x) \
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(((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \
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M_FW_PARAMS_PARAM_FILTER_MODE)
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#define S_FW_PARAMS_PARAM_FILTER_MASK 0
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#define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff
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#define V_FW_PARAMS_PARAM_FILTER_MASK(x) \
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((x) << S_FW_PARAMS_PARAM_FILTER_MASK)
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#define G_FW_PARAMS_PARAM_FILTER_MASK(x) \
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(((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \
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M_FW_PARAMS_PARAM_FILTER_MASK)
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enum fw_params_param_dev {
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FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
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FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
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@ -4799,6 +4830,14 @@ enum fw_params_param_dev {
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FW_PARAMS_PARAM_DEV_ADD_SMAC = 0x25,
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FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26,
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FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
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FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28,
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FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29,
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FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A,
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FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B,
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FW_PARAMS_PARAM_DEV_VF_TRVLAN = 0x2C,
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FW_PARAMS_PARAM_DEV_TCB_CACHE_FLUSH = 0x2D,
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FW_PARAMS_PARAM_DEV_FILTER = 0x2E,
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FW_PARAMS_PARAM_DEV_CLIP2_CMD = 0x2F,
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};
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/*
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@ -4827,6 +4866,12 @@ enum fw_params_param_dev_diag {
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FW_PARAM_DEV_DIAG_TMP = 0x00,
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FW_PARAM_DEV_DIAG_VDD = 0x01,
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FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02,
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FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR = 0x03,
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};
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enum fw_params_param_dev_filter{
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FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00,
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FW_PARAM_DEV_FILTER_MODE_MASK = 0x01,
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};
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enum fw_params_param_dev_fwcache {
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@ -4892,6 +4937,18 @@ enum fw_params_param_pfvf {
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FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B,
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FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C,
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FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,
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FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E,
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FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F,
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FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40,
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};
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/*
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* virtual link state as seen by the specified VF
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*/
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enum vf_link_states {
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VF_LINK_STATE_AUTO = 0x00,
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VF_LINK_STATE_ENABLE = 0x01,
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VF_LINK_STATE_DISABLE = 0x02,
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};
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/*
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@ -4907,6 +4964,7 @@ enum fw_params_param_dmaq {
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FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
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FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
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FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14,
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FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15,
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FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
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FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30
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};
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@ -4922,6 +4980,7 @@ enum fw_params_param_chnet_flags {
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FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1,
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FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2,
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FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4,
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FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6_SLAAC = 0x8,
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};
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#define S_FW_PARAMS_MNEM 24
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@ -5852,7 +5911,7 @@ struct fw_eq_eth_cmd {
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__be32 dcaen_to_eqsize;
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__be64 eqaddr;
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__be32 autoequiqe_to_viid;
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__be32 r8_lo;
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__be32 timeren_timerix;
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__be64 r9;
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};
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@ -6046,6 +6105,19 @@ struct fw_eq_eth_cmd {
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#define G_FW_EQ_ETH_CMD_VIID(x) \
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(((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
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#define S_FW_EQ_ETH_CMD_TIMEREN 3
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#define M_FW_EQ_ETH_CMD_TIMEREN 0x1
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#define V_FW_EQ_ETH_CMD_TIMEREN(x) ((x) << S_FW_EQ_ETH_CMD_TIMEREN)
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#define G_FW_EQ_ETH_CMD_TIMEREN(x) \
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(((x) >> S_FW_EQ_ETH_CMD_TIMEREN) & M_FW_EQ_ETH_CMD_TIMEREN)
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#define F_FW_EQ_ETH_CMD_TIMEREN V_FW_EQ_ETH_CMD_TIMEREN(1U)
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#define S_FW_EQ_ETH_CMD_TIMERIX 0
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#define M_FW_EQ_ETH_CMD_TIMERIX 0x7
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#define V_FW_EQ_ETH_CMD_TIMERIX(x) ((x) << S_FW_EQ_ETH_CMD_TIMERIX)
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#define G_FW_EQ_ETH_CMD_TIMERIX(x) \
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(((x) >> S_FW_EQ_ETH_CMD_TIMERIX) & M_FW_EQ_ETH_CMD_TIMERIX)
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struct fw_eq_ctrl_cmd {
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__be32 op_to_vfn;
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__be32 alloc_to_len16;
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@ -6414,6 +6486,8 @@ struct fw_eq_ofld_cmd {
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#define G_FW_EQ_OFLD_CMD_EQSIZE(x) \
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(((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)
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/* Following macros present here only to maintain backward
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* compatibiity. Driver must not use these anymore */
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/* Macros for VIID parsing:
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VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */
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#define S_FW_VIID_PFN 8
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@ -7125,11 +7199,12 @@ enum fw_port_mdi {
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#define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL
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#define FW_PORT_CAP32_FEC_RS 0x00800000UL
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#define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
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#define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL
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#define FW_PORT_CAP32_FEC_NO_FEC 0x02000000UL
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#define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL
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#define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL
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#define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL
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#define FW_PORT_CAP32_RESERVED2 0xe0000000UL
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#define FW_PORT_CAP32_FORCE_FEC 0x20000000UL
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#define FW_PORT_CAP32_RESERVED2 0xc0000000UL
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#define S_FW_PORT_CAP32_SPEED 0
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#define M_FW_PORT_CAP32_SPEED 0xfff
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@ -7190,6 +7265,14 @@ enum fw_port_mdi32 {
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#define CAP32_FC(__cap32) \
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(V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32)
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static inline bool
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fec_supported(uint32_t caps)
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{
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return ((caps & (FW_PORT_CAP32_SPEED_25G | FW_PORT_CAP32_SPEED_50G |
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FW_PORT_CAP32_SPEED_100G)) != 0);
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}
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enum fw_port_action {
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FW_PORT_ACTION_L1_CFG = 0x0001,
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FW_PORT_ACTION_L2_CFG = 0x0002,
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@ -7226,7 +7309,8 @@ enum fw_port_l2cfg_ctlbf {
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FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
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FW_PORT_L2_CTLBF_IVLAN = 0x10,
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FW_PORT_L2_CTLBF_TXIPG = 0x20,
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FW_PORT_L2_CTLBF_MTU = 0x40
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FW_PORT_L2_CTLBF_MTU = 0x40,
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FW_PORT_L2_CTLBF_OVLAN_FILT = 0x80,
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};
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enum fw_dcb_app_tlv_sf {
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@ -7435,6 +7519,13 @@ struct fw_port_cmd {
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(((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)
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#define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U)
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#define S_FW_PORT_CMD_OVLAN_FILT 2
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#define M_FW_PORT_CMD_OVLAN_FILT 0x1
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#define V_FW_PORT_CMD_OVLAN_FILT(x) ((x) << S_FW_PORT_CMD_OVLAN_FILT)
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#define G_FW_PORT_CMD_OVLAN_FILT(x) \
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(((x) >> S_FW_PORT_CMD_OVLAN_FILT) & M_FW_PORT_CMD_OVLAN_FILT)
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#define F_FW_PORT_CMD_OVLAN_FILT V_FW_PORT_CMD_OVLAN_FILT(1U)
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#define S_FW_PORT_CMD_TXIPG 3
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#define M_FW_PORT_CMD_TXIPG 0x1fff
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#define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG)
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@ -8145,7 +8236,7 @@ struct fw_ptp_cmd {
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__u8 txchan;
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__be16 absid;
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__be16 mode;
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__be16 r3;
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__be16 ptp_rx_ctrl_pkd;
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} init;
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struct fw_ptp_ts {
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__u8 sc;
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@ -8164,6 +8255,14 @@ struct fw_ptp_cmd {
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#define G_FW_PTP_CMD_PORTID(x) \
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(((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID)
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#define S_FW_PTP_CMD_PTP_RX_CTRL 15
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#define M_FW_PTP_CMD_PTP_RX_CTRL 0x1
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#define V_FW_PTP_CMD_PTP_RX_CTRL(x) ((x) << S_FW_PTP_CMD_PTP_RX_CTRL)
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#define G_FW_PTP_CMD_PTP_RX_CTRL(x) \
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(((x) >> S_FW_PTP_CMD_PTP_RX_CTRL) & M_FW_PTP_CMD_PTP_RX_CTRL)
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#define F_FW_PTP_CMD_PTP_RX_CTRL V_FW_PTP_CMD_PTP_RX_CTRL(1U)
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struct fw_rss_ind_tbl_cmd {
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__be32 op_to_viid;
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__be32 retval_len16;
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@ -8815,6 +8914,16 @@ struct fw_clip_cmd {
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#define G_FW_CLIP_CMD_INDEX(x) \
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(((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX)
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struct fw_clip2_cmd {
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__be32 op_to_write;
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__be32 alloc_to_len16;
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__be64 ip_hi;
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__be64 ip_lo;
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__be64 ipm_hi;
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__be64 ipm_lo;
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__be32 r4[2];
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};
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/******************************************************************************
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* F O i S C S I C O M M A N D s
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**************************************/
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@ -9880,6 +9989,10 @@ enum {
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T6FW_HDR_INTFVER_FCOE = 0x00,
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};
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#define FW_VERSION32(MAJOR, MINOR, MICRO, BUILD) ( \
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V_FW_HDR_FW_VER_MAJOR(MAJOR) | V_FW_HDR_FW_VER_MINOR(MINOR) | \
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V_FW_HDR_FW_VER_MICRO(MICRO) | V_FW_HDR_FW_VER_BUILD(BUILD))
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enum {
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FW_HDR_MAGIC_RUNTIME = 0x00000000,
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FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74,
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@ -9920,4 +10033,8 @@ struct fw_ifconf_dhcp_info {
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__u8 data[270];
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};
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struct fw_ifconf_ping_info {
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__be16 ping_pldsize;
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};
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#endif /* _T4FW_INTERFACE_H_ */
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