Initial import of Ralink/Mediatek MIPS SoC support #3
Interrupt controllers found in various Mediatek/Ralink SoCs. mtk_intr_v1 and mtk_intr_v2 are basically the same at the moment, with just different register mappings. However, v1 interrupt controller has a subset of the functionality of the v2 interrupt controller, so in the future the v2 interrupt controller driver may be enhanced, if needed, with things like level/edge interrupts and soft interrupts. So, for the moment I suggest we keep them as 2 separate files. mtk_intr_gic provides very basic (similar to v1 and v2) support for MIPS GIC controllers, which currently maps all interrupts to a single core and sets them to type level, active high. In the future this may be developed into a generic GIC controller to support any new MIPS SoCs that include it. The GIC is a standard MTI interrupt controller in their multi-core line-up (e.g., 1004K, 1074K, etc.), rather than a SoC-specific controller. Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D5839
This commit is contained in:
Stanislav Galabov
parent
b74b6b0a82
commit
e56e179d55
377
sys/mips/mediatek/mtk_intr_gic.c
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377
sys/mips/mediatek/mtk_intr_gic.c
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@ -0,0 +1,377 @@
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/*-
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* Copyright (c) 2016 Stanislav Galabov
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* Copyright (c) 2015 Alexander Kabaev
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/cpuset.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#include <sys/sched.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/smp.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "pic_if.h"
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#define MTK_NIRQS 64 /* We'll only use 64 for now */
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#define MTK_INTPOL 0x0100
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#define MTK_INTTRIG 0x0180
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#define MTK_INTDIS 0x0300
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#define MTK_INTENA 0x0380
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#define MTK_INTMASK 0x0400
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#define MTK_INTSTAT 0x0480
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#define MTK_MAPPIN(_i) (0x0500 + (4 * (_i)))
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#define MTK_MAPVPE(_i, _v) (0x2000 + (32 * (_i)) + (((_v) / 32) * 4))
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#define MTK_INTPOL_POS 1
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#define MTK_INTPOL_NEG 0
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#define MTK_INTTRIG_EDGE 1
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#define MTK_INTTRIG_LEVEL 0
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#define MTK_PIN_BITS(_i) ((1 << 31) | (_i))
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#define MTK_VPE_BITS(_v) (1 << ((_v) % 32))
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static int mtk_gic_intr(void *);
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struct mtk_gic_irqsrc {
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struct intr_irqsrc isrc;
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u_int irq;
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};
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struct mtk_gic_softc {
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device_t gic_dev;
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void * gic_intrhand;
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struct resource * gic_res[2];
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struct mtk_gic_irqsrc gic_irqs[MTK_NIRQS];
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struct mtx mutex;
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uint32_t nirqs;
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};
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#define GIC_INTR_ISRC(sc, irq) (&(sc)->gic_irqs[(irq)].isrc)
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static struct resource_spec mtk_gic_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Registers */
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{ SYS_RES_IRQ, 0, RF_ACTIVE }, /* Parent interrupt 1 */
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{ -1, 0 }
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};
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static struct ofw_compat_data compat_data[] = {
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{ "mti,gic", 1 },
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{ NULL, 0 }
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};
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#if 0
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#define READ4(_sc, _reg) \
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bus_space_read_4((_sc)->bst, (_sc)->bsh, _reg)
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#define WRITE4(_sc, _reg, _val) \
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bus_space_write_4((_sc)->bst, (_sc)->bsh, _reg, _val)
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#else
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#define READ4(_sc, _reg) bus_read_4((_sc)->gic_res[0], (_reg))
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#define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->gic_res[0], (_reg), (_val))
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#endif
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static int
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mtk_gic_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "MTK Interrupt Controller (GIC)");
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return (BUS_PROBE_DEFAULT);
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}
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static inline void
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gic_irq_unmask(struct mtk_gic_softc *sc, u_int irq)
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{
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WRITE4(sc, MTK_INTENA, (1u << (irq)));
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}
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static inline void
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gic_irq_mask(struct mtk_gic_softc *sc, u_int irq)
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{
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WRITE4(sc, MTK_INTDIS, (1u << (irq)));
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}
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static inline intptr_t
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gic_xref(device_t dev)
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{
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return (OF_xref_from_node(ofw_bus_get_node(dev)));
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}
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static int
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mtk_gic_register_isrcs(struct mtk_gic_softc *sc)
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{
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int error;
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uint32_t irq;
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struct intr_irqsrc *isrc;
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const char *name;
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name = device_get_nameunit(sc->gic_dev);
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for (irq = 0; irq < sc->nirqs; irq++) {
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sc->gic_irqs[irq].irq = irq;
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isrc = GIC_INTR_ISRC(sc, irq);
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error = intr_isrc_register(isrc, sc->gic_dev, 0, "%s", name);
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if (error != 0) {
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/* XXX call intr_isrc_deregister */
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device_printf(sc->gic_dev, "%s failed", __func__);
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return (error);
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}
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}
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return (0);
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}
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static int
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mtk_gic_attach(device_t dev)
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{
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struct mtk_gic_softc *sc;
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intptr_t xref = gic_xref(dev);
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int i;
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sc = device_get_softc(dev);
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if (bus_alloc_resources(dev, mtk_gic_spec, sc->gic_res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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sc->gic_dev = dev;
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/* Initialize mutex */
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mtx_init(&sc->mutex, "PIC lock", "", MTX_SPIN);
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/* Set the number of interrupts */
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sc->nirqs = nitems(sc->gic_irqs);
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/* Mask all interrupts */
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WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF);
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/* All interrupts are of type level */
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WRITE4(sc, MTK_INTTRIG, 0x00000000);
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/* All interrupts are of positive polarity */
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WRITE4(sc, MTK_INTPOL, 0xFFFFFFFF);
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/*
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* Route all interrupts to pin 0 on VPE 0;
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*/
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for (i = 0; i < 32; i++) {
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WRITE4(sc, MTK_MAPPIN(i), MTK_PIN_BITS(0));
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WRITE4(sc, MTK_MAPVPE(i, 0), MTK_VPE_BITS(0));
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}
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/* Register the interrupts */
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if (mtk_gic_register_isrcs(sc) != 0) {
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device_printf(dev, "could not register GIC ISRCs\n");
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goto cleanup;
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}
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/*
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* Now, when everything is initialized, it's right time to
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* register interrupt controller to interrupt framefork.
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*/
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if (intr_pic_register(dev, xref) != 0) {
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device_printf(dev, "could not register PIC\n");
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goto cleanup;
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}
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if (bus_setup_intr(dev, sc->gic_res[1], INTR_TYPE_CLK,
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mtk_gic_intr, NULL, sc, &sc->gic_intrhand)) {
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device_printf(dev, "could not setup irq handler\n");
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intr_pic_deregister(dev, xref);
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goto cleanup;
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}
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return (0);
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cleanup:
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bus_release_resources(dev, mtk_gic_spec, sc->gic_res);
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return(ENXIO);
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}
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static int
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mtk_gic_intr(void *arg)
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{
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struct mtk_gic_softc *sc = arg;
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struct thread *td;
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uint32_t i, intr;
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td = curthread;
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/* Workaround: do not inflate intr nesting level */
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td->td_intr_nesting_level--;
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intr = READ4(sc, MTK_INTSTAT) & READ4(sc, MTK_INTMASK);
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while ((i = fls(intr)) != 0) {
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i--;
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intr &= ~(1u << i);
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if (intr_isrc_dispatch(GIC_INTR_ISRC(sc, i),
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curthread->td_intr_frame) != 0) {
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device_printf(sc->gic_dev,
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"Stray interrupt %u detected\n", i);
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gic_irq_mask(sc, i);
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continue;
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}
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}
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KASSERT(i == 0, ("all interrupts handled"));
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td->td_intr_nesting_level++;
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return (FILTER_HANDLED);
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}
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static int
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mtk_gic_map_intr(device_t dev, struct intr_map_data *data,
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struct intr_irqsrc **isrcp)
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{
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#ifdef FDT
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struct mtk_gic_softc *sc;
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sc = device_get_softc(dev);
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if (data == NULL || data->type != INTR_MAP_DATA_FDT ||
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data->fdt.ncells != 1 || data->fdt.cells[0] >= sc->nirqs)
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return (EINVAL);
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*isrcp = GIC_INTR_ISRC(sc, data->fdt.cells[0]);
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return (0);
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#else
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return (EINVAL);
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#endif
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}
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static void
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mtk_gic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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u_int irq;
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irq = ((struct mtk_gic_irqsrc *)isrc)->irq;
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gic_irq_unmask(device_get_softc(dev), irq);
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}
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static void
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mtk_gic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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u_int irq;
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irq = ((struct mtk_gic_irqsrc *)isrc)->irq;
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gic_irq_mask(device_get_softc(dev), irq);
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}
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static void
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mtk_gic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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mtk_gic_disable_intr(dev, isrc);
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}
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static void
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mtk_gic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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mtk_gic_enable_intr(dev, isrc);
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}
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static void
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mtk_gic_post_filter(device_t dev, struct intr_irqsrc *isrc)
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{
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}
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#ifdef SMP
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static int
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mtk_gic_bind(device_t dev, struct intr_irqsrc *isrc)
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{
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return (EOPNOTSUPP);
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}
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static void
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mtk_gic_init_secondary(device_t dev)
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{
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}
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static void
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mtk_gic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus)
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{
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}
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#endif
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static device_method_t mtk_gic_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, mtk_gic_probe),
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DEVMETHOD(device_attach, mtk_gic_attach),
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/* Interrupt controller interface */
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DEVMETHOD(pic_disable_intr, mtk_gic_disable_intr),
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DEVMETHOD(pic_enable_intr, mtk_gic_enable_intr),
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DEVMETHOD(pic_map_intr, mtk_gic_map_intr),
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DEVMETHOD(pic_post_filter, mtk_gic_post_filter),
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DEVMETHOD(pic_post_ithread, mtk_gic_post_ithread),
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DEVMETHOD(pic_pre_ithread, mtk_gic_pre_ithread),
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#ifdef SMP
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DEVMETHOD(pic_bind, mtk_gic_bind),
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DEVMETHOD(pic_init_secondary, mtk_gic_init_secondary),
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DEVMETHOD(pic_ipi_send, mtk_gic_ipi_send),
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#endif
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{ 0, 0 }
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};
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static driver_t mtk_gic_driver = {
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"intc",
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mtk_gic_methods,
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sizeof(struct mtk_gic_softc),
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};
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static devclass_t mtk_gic_devclass;
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EARLY_DRIVER_MODULE(intc_gic, simplebus, mtk_gic_driver, mtk_gic_devclass, 0, 0,
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BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
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353
sys/mips/mediatek/mtk_intr_v1.c
Normal file
353
sys/mips/mediatek/mtk_intr_v1.c
Normal file
@ -0,0 +1,353 @@
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/*-
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* Copyright (c) 2015 Stanislav Galabov
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* Copyright (c) 2015 Alexander Kabaev
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* All rights reserved.
|
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*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions, and the following disclaimer,
|
||||
* without modification, immediately at the beginning of the file.
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
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*/
|
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|
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#include "opt_platform.h"
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|
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
|
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
|
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
|
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#include <sys/cpuset.h>
|
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#include <sys/sched.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/smp.h>
|
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|
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
|
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|
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#include "pic_if.h"
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#define MTK_NIRQS 32
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#define MTK_IRQ0STAT 0x0000
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#define MTK_IRQ1STAT 0x0004
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#define MTK_INTTYPE 0x0020
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#define MTK_INTRAW 0x0030
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#define MTK_INTENA 0x0034
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#define MTK_INTDIS 0x0038
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static int mtk_pic_intr(void *);
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|
||||
struct mtk_pic_irqsrc {
|
||||
struct intr_irqsrc isrc;
|
||||
u_int irq;
|
||||
};
|
||||
|
||||
struct mtk_pic_softc {
|
||||
device_t pic_dev;
|
||||
void * pic_intrhand;
|
||||
struct resource * pic_res[2];
|
||||
struct mtk_pic_irqsrc pic_irqs[MTK_NIRQS];
|
||||
struct mtx mutex;
|
||||
uint32_t nirqs;
|
||||
};
|
||||
|
||||
#define PIC_INTR_ISRC(sc, irq) (&(sc)->pic_irqs[(irq)].isrc)
|
||||
|
||||
static struct resource_spec mtk_pic_spec[] = {
|
||||
{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Registers */
|
||||
{ SYS_RES_IRQ, 0, RF_ACTIVE }, /* Parent interrupt 1 */
|
||||
// { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Parent interrupt 2 */
|
||||
{ -1, 0 }
|
||||
};
|
||||
|
||||
static struct ofw_compat_data compat_data[] = {
|
||||
{ "ralink,rt2880-intc", 1 },
|
||||
{ "ralink,rt3050-intc", 1 },
|
||||
{ "ralink,rt3352-intc", 1 },
|
||||
{ "ralink,rt3883-intc", 1 },
|
||||
{ "ralink,rt5350-intc", 1 },
|
||||
{ "ralink,mt7620a-intc", 1 },
|
||||
{ NULL, 0 }
|
||||
};
|
||||
|
||||
#define READ4(_sc, _reg) bus_read_4((_sc)->pic_res[0], _reg)
|
||||
#define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val)
|
||||
|
||||
static int
|
||||
mtk_pic_probe(device_t dev)
|
||||
{
|
||||
|
||||
if (!ofw_bus_status_okay(dev))
|
||||
return (ENXIO);
|
||||
|
||||
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
|
||||
return (ENXIO);
|
||||
|
||||
device_set_desc(dev, "MTK Interrupt Controller (v2)");
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
|
||||
static inline void
|
||||
pic_irq_unmask(struct mtk_pic_softc *sc, u_int irq)
|
||||
{
|
||||
|
||||
WRITE4(sc, MTK_INTENA, (1u << (irq)));
|
||||
}
|
||||
|
||||
static inline void
|
||||
pic_irq_mask(struct mtk_pic_softc *sc, u_int irq)
|
||||
{
|
||||
|
||||
WRITE4(sc, MTK_INTDIS, (1u << (irq)));
|
||||
}
|
||||
|
||||
static inline intptr_t
|
||||
pic_xref(device_t dev)
|
||||
{
|
||||
return (OF_xref_from_node(ofw_bus_get_node(dev)));
|
||||
}
|
||||
|
||||
static int
|
||||
mtk_pic_register_isrcs(struct mtk_pic_softc *sc)
|
||||
{
|
||||
int error;
|
||||
uint32_t irq;
|
||||
struct intr_irqsrc *isrc;
|
||||
const char *name;
|
||||
|
||||
name = device_get_nameunit(sc->pic_dev);
|
||||
for (irq = 0; irq < sc->nirqs; irq++) {
|
||||
sc->pic_irqs[irq].irq = irq;
|
||||
isrc = PIC_INTR_ISRC(sc, irq);
|
||||
error = intr_isrc_register(isrc, sc->pic_dev, 0, "%s", name);
|
||||
if (error != 0) {
|
||||
/* XXX call intr_isrc_deregister */
|
||||
device_printf(sc->pic_dev, "%s failed", __func__);
|
||||
return (error);
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
mtk_pic_attach(device_t dev)
|
||||
{
|
||||
struct mtk_pic_softc *sc;
|
||||
intptr_t xref = pic_xref(dev);
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
if (bus_alloc_resources(dev, mtk_pic_spec, sc->pic_res)) {
|
||||
device_printf(dev, "could not allocate resources\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
sc->pic_dev = dev;
|
||||
|
||||
/* Initialize mutex */
|
||||
mtx_init(&sc->mutex, "PIC lock", "", MTX_SPIN);
|
||||
|
||||
/* Set the number of interrupts */
|
||||
sc->nirqs = nitems(sc->pic_irqs);
|
||||
|
||||
/* Mask all interrupts */
|
||||
WRITE4(sc, MTK_INTDIS, 0x7FFFFFFF);
|
||||
|
||||
/* But enable interrupt generation/masking */
|
||||
WRITE4(sc, MTK_INTENA, 0x80000000);
|
||||
|
||||
/* Set all interrupts to type 0 */
|
||||
WRITE4(sc, MTK_INTTYPE, 0x00000000);
|
||||
|
||||
/* Register the interrupts */
|
||||
if (mtk_pic_register_isrcs(sc) != 0) {
|
||||
device_printf(dev, "could not register PIC ISRCs\n");
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
/*
|
||||
* Now, when everything is initialized, it's right time to
|
||||
* register interrupt controller to interrupt framefork.
|
||||
*/
|
||||
if (intr_pic_register(dev, xref) != 0) {
|
||||
device_printf(dev, "could not register PIC\n");
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
if (bus_setup_intr(dev, sc->pic_res[1], INTR_TYPE_CLK,
|
||||
mtk_pic_intr, NULL, sc, &sc->pic_intrhand)) {
|
||||
device_printf(dev, "could not setup irq handler\n");
|
||||
intr_pic_deregister(dev, xref);
|
||||
goto cleanup;
|
||||
}
|
||||
return (0);
|
||||
|
||||
cleanup:
|
||||
bus_release_resources(dev, mtk_pic_spec, sc->pic_res);
|
||||
return(ENXIO);
|
||||
}
|
||||
|
||||
static int
|
||||
mtk_pic_intr(void *arg)
|
||||
{
|
||||
struct mtk_pic_softc *sc = arg;
|
||||
struct thread *td;
|
||||
uint32_t i, intr;
|
||||
|
||||
td = curthread;
|
||||
/* Workaround: do not inflate intr nesting level */
|
||||
td->td_intr_nesting_level--;
|
||||
|
||||
#ifdef _notyet_
|
||||
intr = READ4(sc, MTK_IRQ1STAT);
|
||||
while ((i = fls(intr)) != 0) {
|
||||
i--;
|
||||
intr &= ~(1u << i);
|
||||
|
||||
if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i),
|
||||
curthread->td_intr_frame) != 0) {
|
||||
device_printf(sc->pic_dev,
|
||||
"Stray interrupt %u detected\n", i);
|
||||
pic_irq_mask(sc, i);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
KASSERT(i == 0, ("all interrupts handled"));
|
||||
#endif
|
||||
|
||||
intr = READ4(sc, MTK_IRQ0STAT);
|
||||
|
||||
while ((i = fls(intr)) != 0) {
|
||||
i--;
|
||||
intr &= ~(1u << i);
|
||||
|
||||
if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i),
|
||||
curthread->td_intr_frame) != 0) {
|
||||
device_printf(sc->pic_dev,
|
||||
"Stray interrupt %u detected\n", i);
|
||||
pic_irq_mask(sc, i);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
KASSERT(i == 0, ("all interrupts handled"));
|
||||
|
||||
td->td_intr_nesting_level++;
|
||||
|
||||
return (FILTER_HANDLED);
|
||||
}
|
||||
|
||||
static int
|
||||
mtk_pic_map_intr(device_t dev, struct intr_map_data *data,
|
||||
struct intr_irqsrc **isrcp)
|
||||
{
|
||||
#ifdef FDT
|
||||
struct mtk_pic_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
if (data == NULL || data->type != INTR_MAP_DATA_FDT ||
|
||||
data->fdt.ncells != 1 || data->fdt.cells[0] >= sc->nirqs)
|
||||
return (EINVAL);
|
||||
|
||||
*isrcp = PIC_INTR_ISRC(sc, data->fdt.cells[0]);
|
||||
return (0);
|
||||
#else
|
||||
return (EINVAL);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
mtk_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
u_int irq;
|
||||
|
||||
irq = ((struct mtk_pic_irqsrc *)isrc)->irq;
|
||||
pic_irq_unmask(device_get_softc(dev), irq);
|
||||
}
|
||||
|
||||
static void
|
||||
mtk_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
u_int irq;
|
||||
|
||||
irq = ((struct mtk_pic_irqsrc *)isrc)->irq;
|
||||
pic_irq_mask(device_get_softc(dev), irq);
|
||||
}
|
||||
|
||||
static void
|
||||
mtk_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
|
||||
mtk_pic_disable_intr(dev, isrc);
|
||||
}
|
||||
|
||||
static void
|
||||
mtk_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
|
||||
mtk_pic_enable_intr(dev, isrc);
|
||||
}
|
||||
|
||||
static void
|
||||
mtk_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
}
|
||||
|
||||
static device_method_t mtk_pic_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, mtk_pic_probe),
|
||||
DEVMETHOD(device_attach, mtk_pic_attach),
|
||||
/* Interrupt controller interface */
|
||||
DEVMETHOD(pic_disable_intr, mtk_pic_disable_intr),
|
||||
DEVMETHOD(pic_enable_intr, mtk_pic_enable_intr),
|
||||
DEVMETHOD(pic_map_intr, mtk_pic_map_intr),
|
||||
DEVMETHOD(pic_post_filter, mtk_pic_post_filter),
|
||||
DEVMETHOD(pic_post_ithread, mtk_pic_post_ithread),
|
||||
DEVMETHOD(pic_pre_ithread, mtk_pic_pre_ithread),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t mtk_pic_driver = {
|
||||
"intc",
|
||||
mtk_pic_methods,
|
||||
sizeof(struct mtk_pic_softc),
|
||||
};
|
||||
|
||||
static devclass_t mtk_pic_devclass;
|
||||
|
||||
EARLY_DRIVER_MODULE(intc_v1, simplebus, mtk_pic_driver, mtk_pic_devclass, 0, 0,
|
||||
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
|
||||
348
sys/mips/mediatek/mtk_intr_v2.c
Normal file
348
sys/mips/mediatek/mtk_intr_v2.c
Normal file
@ -0,0 +1,348 @@
|
||||
/*-
|
||||
* Copyright (c) 2015 Stanislav Galabov
|
||||
* Copyright (c) 2015 Alexander Kabaev
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions, and the following disclaimer,
|
||||
* without modification, immediately at the beginning of the file.
|
||||
* 2. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "opt_platform.h"
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/ktr.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/rman.h>
|
||||
#include <sys/pcpu.h>
|
||||
#include <sys/proc.h>
|
||||
#include <sys/cpuset.h>
|
||||
#include <sys/lock.h>
|
||||
#include <sys/mutex.h>
|
||||
#include <sys/smp.h>
|
||||
#include <sys/sched.h>
|
||||
#include <machine/bus.h>
|
||||
#include <machine/intr.h>
|
||||
#include <machine/smp.h>
|
||||
|
||||
#include <dev/fdt/fdt_common.h>
|
||||
#include <dev/ofw/openfirm.h>
|
||||
#include <dev/ofw/ofw_bus.h>
|
||||
#include <dev/ofw/ofw_bus_subr.h>
|
||||
|
||||
#include "pic_if.h"
|
||||
|
||||
#define MTK_NIRQS 32
|
||||
|
||||
#define MTK_IRQ0STAT 0x009c
|
||||
#define MTK_IRQ1STAT 0x00a0
|
||||
#define MTK_INTTYPE 0x0000
|
||||
#define MTK_INTRAW 0x00a4
|
||||
#define MTK_INTENA 0x0080
|
||||
#define MTK_INTDIS 0x0078
|
||||
|
||||
static int mtk_pic_intr(void *);
|
||||
|
||||
struct mtk_pic_irqsrc {
|
||||
struct intr_irqsrc isrc;
|
||||
u_int irq;
|
||||
};
|
||||
|
||||
struct mtk_pic_softc {
|
||||
device_t pic_dev;
|
||||
void * pic_intrhand;
|
||||
struct resource * pic_res[2];
|
||||
struct mtk_pic_irqsrc pic_irqs[MTK_NIRQS];
|
||||
struct mtx mutex;
|
||||
uint32_t nirqs;
|
||||
};
|
||||
|
||||
#define PIC_INTR_ISRC(sc, irq) (&(sc)->pic_irqs[(irq)].isrc)
|
||||
|
||||
static struct resource_spec mtk_pic_spec[] = {
|
||||
{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Registers */
|
||||
{ SYS_RES_IRQ, 0, RF_ACTIVE }, /* Parent interrupt 1 */
|
||||
// { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Parent interrupt 2 */
|
||||
{ -1, 0 }
|
||||
};
|
||||
|
||||
static struct ofw_compat_data compat_data[] = {
|
||||
{ "ralink,mt7628an-intc", 1 },
|
||||
{ NULL, 0 }
|
||||
};
|
||||
|
||||
#define READ4(_sc, _reg) bus_read_4((_sc)->pic_res[0], _reg)
|
||||
#define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val)
|
||||
|
||||
static int
|
||||
mtk_pic_probe(device_t dev)
|
||||
{
|
||||
|
||||
if (!ofw_bus_status_okay(dev))
|
||||
return (ENXIO);
|
||||
|
||||
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
|
||||
return (ENXIO);
|
||||
|
||||
device_set_desc(dev, "MTK Interrupt Controller (v2)");
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
|
||||
static inline void
|
||||
pic_irq_unmask(struct mtk_pic_softc *sc, u_int irq)
|
||||
{
|
||||
|
||||
WRITE4(sc, MTK_INTENA, (1u << (irq)));
|
||||
}
|
||||
|
||||
static inline void
|
||||
pic_irq_mask(struct mtk_pic_softc *sc, u_int irq)
|
||||
{
|
||||
|
||||
WRITE4(sc, MTK_INTDIS, (1u << (irq)));
|
||||
}
|
||||
|
||||
static inline intptr_t
|
||||
pic_xref(device_t dev)
|
||||
{
|
||||
return (OF_xref_from_node(ofw_bus_get_node(dev)));
|
||||
}
|
||||
|
||||
static int
|
||||
mtk_pic_register_isrcs(struct mtk_pic_softc *sc)
|
||||
{
|
||||
int error;
|
||||
uint32_t irq;
|
||||
struct intr_irqsrc *isrc;
|
||||
const char *name;
|
||||
|
||||
name = device_get_nameunit(sc->pic_dev);
|
||||
for (irq = 0; irq < sc->nirqs; irq++) {
|
||||
sc->pic_irqs[irq].irq = irq;
|
||||
isrc = PIC_INTR_ISRC(sc, irq);
|
||||
error = intr_isrc_register(isrc, sc->pic_dev, 0, "%s", name);
|
||||
if (error != 0) {
|
||||
/* XXX call intr_isrc_deregister */
|
||||
device_printf(sc->pic_dev, "%s failed", __func__);
|
||||
return (error);
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
mtk_pic_attach(device_t dev)
|
||||
{
|
||||
struct mtk_pic_softc *sc;
|
||||
intptr_t xref = pic_xref(dev);
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
if (bus_alloc_resources(dev, mtk_pic_spec, sc->pic_res)) {
|
||||
device_printf(dev, "could not allocate resources\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
sc->pic_dev = dev;
|
||||
|
||||
/* Initialize mutex */
|
||||
mtx_init(&sc->mutex, "PIC lock", "", MTX_SPIN);
|
||||
|
||||
/* Set the number of interrupts */
|
||||
sc->nirqs = nitems(sc->pic_irqs);
|
||||
|
||||
/* Mask all interrupts */
|
||||
WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF);
|
||||
|
||||
/* But enable interrupt generation/masking */
|
||||
WRITE4(sc, MTK_INTENA, 0x00000000);
|
||||
|
||||
/* Set all interrupts to type 0 */
|
||||
WRITE4(sc, MTK_INTTYPE, 0xFFFFFFFF);
|
||||
|
||||
/* Register the interrupts */
|
||||
if (mtk_pic_register_isrcs(sc) != 0) {
|
||||
device_printf(dev, "could not register PIC ISRCs\n");
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
/*
|
||||
* Now, when everything is initialized, it's right time to
|
||||
* register interrupt controller to interrupt framefork.
|
||||
*/
|
||||
if (intr_pic_register(dev, xref) != 0) {
|
||||
device_printf(dev, "could not register PIC\n");
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
if (bus_setup_intr(dev, sc->pic_res[1], INTR_TYPE_CLK,
|
||||
mtk_pic_intr, NULL, sc, &sc->pic_intrhand)) {
|
||||
device_printf(dev, "could not setup irq handler\n");
|
||||
intr_pic_deregister(dev, xref);
|
||||
goto cleanup;
|
||||
}
|
||||
return (0);
|
||||
|
||||
cleanup:
|
||||
bus_release_resources(dev, mtk_pic_spec, sc->pic_res);
|
||||
return(ENXIO);
|
||||
}
|
||||
|
||||
static int
|
||||
mtk_pic_intr(void *arg)
|
||||
{
|
||||
struct mtk_pic_softc *sc = arg;
|
||||
struct thread *td;
|
||||
uint32_t i, intr;
|
||||
|
||||
td = curthread;
|
||||
/* Workaround: do not inflate intr nesting level */
|
||||
td->td_intr_nesting_level--;
|
||||
|
||||
#ifdef _notyet_
|
||||
intr = READ4(sc, MTK_IRQ1STAT);
|
||||
while ((i = fls(intr)) != 0) {
|
||||
i--;
|
||||
intr &= ~(1u << i);
|
||||
|
||||
if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i),
|
||||
curthread->td_intr_frame) != 0) {
|
||||
device_printf(sc->pic_dev,
|
||||
"Stray interrupt %u detected\n", i);
|
||||
pic_irq_mask(sc, i);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
KASSERT(i == 0, ("all interrupts handled"));
|
||||
#endif
|
||||
|
||||
intr = READ4(sc, MTK_IRQ0STAT);
|
||||
|
||||
while ((i = fls(intr)) != 0) {
|
||||
i--;
|
||||
intr &= ~(1u << i);
|
||||
|
||||
if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i),
|
||||
curthread->td_intr_frame) != 0) {
|
||||
device_printf(sc->pic_dev,
|
||||
"Stray interrupt %u detected\n", i);
|
||||
pic_irq_mask(sc, i);
|
||||
continue;
|
||||
}
|
||||
}
|
||||
|
||||
KASSERT(i == 0, ("all interrupts handled"));
|
||||
|
||||
td->td_intr_nesting_level++;
|
||||
|
||||
return (FILTER_HANDLED);
|
||||
}
|
||||
|
||||
static int
|
||||
mtk_pic_map_intr(device_t dev, struct intr_map_data *data,
|
||||
struct intr_irqsrc **isrcp)
|
||||
{
|
||||
#ifdef FDT
|
||||
struct mtk_pic_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
if (data == NULL || data->type != INTR_MAP_DATA_FDT ||
|
||||
data->fdt.ncells != 1 || data->fdt.cells[0] >= sc->nirqs)
|
||||
return (EINVAL);
|
||||
|
||||
*isrcp = PIC_INTR_ISRC(sc, data->fdt.cells[0]);
|
||||
return (0);
|
||||
#else
|
||||
return (EINVAL);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
mtk_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
u_int irq;
|
||||
|
||||
irq = ((struct mtk_pic_irqsrc *)isrc)->irq;
|
||||
pic_irq_unmask(device_get_softc(dev), irq);
|
||||
}
|
||||
|
||||
static void
|
||||
mtk_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
u_int irq;
|
||||
|
||||
irq = ((struct mtk_pic_irqsrc *)isrc)->irq;
|
||||
pic_irq_mask(device_get_softc(dev), irq);
|
||||
}
|
||||
|
||||
static void
|
||||
mtk_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
|
||||
mtk_pic_disable_intr(dev, isrc);
|
||||
}
|
||||
|
||||
static void
|
||||
mtk_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
|
||||
mtk_pic_enable_intr(dev, isrc);
|
||||
}
|
||||
|
||||
static void
|
||||
mtk_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
}
|
||||
|
||||
static device_method_t mtk_pic_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, mtk_pic_probe),
|
||||
DEVMETHOD(device_attach, mtk_pic_attach),
|
||||
/* Interrupt controller interface */
|
||||
DEVMETHOD(pic_disable_intr, mtk_pic_disable_intr),
|
||||
DEVMETHOD(pic_enable_intr, mtk_pic_enable_intr),
|
||||
DEVMETHOD(pic_map_intr, mtk_pic_map_intr),
|
||||
DEVMETHOD(pic_post_filter, mtk_pic_post_filter),
|
||||
DEVMETHOD(pic_post_ithread, mtk_pic_post_ithread),
|
||||
DEVMETHOD(pic_pre_ithread, mtk_pic_pre_ithread),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t mtk_pic_driver = {
|
||||
"intc",
|
||||
mtk_pic_methods,
|
||||
sizeof(struct mtk_pic_softc),
|
||||
};
|
||||
|
||||
static devclass_t mtk_pic_devclass;
|
||||
|
||||
EARLY_DRIVER_MODULE(intc_v2, simplebus, mtk_pic_driver, mtk_pic_devclass, 0, 0,
|
||||
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
|
||||
Loading…
Reference in New Issue
Block a user