Tweak -mdoc usage.
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@ -930,7 +930,7 @@ The number of cycles micro-ops were dispatched for execution on port
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The number of cycles micro-ops were dispatched for execution on port
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4.
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.It Li RS_UOPS_DISPATCHED.PORT5
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.Pq Event A1H , Umask 20
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.Pq Event A1H , Umask 20H
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The number of cycles micro-ops were dispatched for execution on port
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5.
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.It Li SB_DRAIN_CYCLES
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@ -1116,7 +1116,7 @@ globally observed.
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The number of cycles while a store was blocked due to a conflict with
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an internal or external snoop.
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.It Li STORE_FORWARDS.GOOD
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.Pq Event 02, Umask 81H
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.Pq Event 02H , Umask 81H
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The number of times stored data was forwarded directly to a load.
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.It Li THERMAL_TRIP
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.Pq Event 3BH , Umask C0H
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@ -234,12 +234,12 @@ The number of branch instructions executed including speculative branches.
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.Pq Event E0H , Umask 00H
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The number of branch instructions decoded.
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.It Li Br_Instr_Ret
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.Pq Event C4H, Umask 00H
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.Pq Event C4H , Umask 00H
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.Pq Alias Qq "Branch Instruction Retired"
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The number of branch instructions retired.
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This is an architectural performance event.
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.It Li Br_MisPred_Ret
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.Pq Event C5H, Umask 00H
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.Pq Event C5H , Umask 00H
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.Pq Alias Qq "Branch Misses Retired"
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The number of mispredicted branch instructions retired.
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This is an architectural performance event.
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@ -553,7 +553,7 @@ The number of L2 cache writes including speculative writes.
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.Pq Event 03H , Umask 00H
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The number of load operations delayed due to store buffer blocks.
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.It Li LLC_Misses
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.Pq Event 2EH, Umask 41H
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.Pq Event 2EH , Umask 41H
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The number of cache misses for references to the last level cache,
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excluding misses due to hardware prefetches.
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This is an architectural performance event.
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@ -561,7 +561,7 @@ This is an architectural performance event.
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The number of references to the last level cache,
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excluding those due to hardware prefetches.
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This is an architectural performance event.
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.Pq Event 2EH, Umask 4FH
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.Pq Event 2EH , Umask 4FH
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This is an architectural performance event.
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.It Li MMX_Assist
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.Pq Event CDH , Umask 00H
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@ -275,7 +275,7 @@ The number of branches executed, but not necessarily retired.
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The number of branch instructions retired.
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This is an architectural performance event.
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.It Li BR_INST_RETIRED.MISPRED
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.Pq Event C5H, Umask 00H
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.Pq Event C5H , Umask 00H
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.Pq Alias Qq "Branch Misses Retired"
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The number of mispredicted branch instructions retired.
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This is an architectural performance event.
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