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* Handle the three other timer interrupts for now, from the AR724x

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later.  If the interrupts are ACKed even if they're not masked, we get
  the interrupts again later.  Grr.

* The AR724x and later chips want the interrupt bits cleared by writing the
  relevant bit to it, NOT by writing all but the current interrupt to it.

Tested:

* AR9344, DB120 reference board

TODO:

* Test ar724x and later chips to ensure no regressions have occured.
This commit is contained in:
Adrian Chadd 2014-03-16 08:38:31 +00:00
parent 3a92d97ff0
commit e581852dd5
1 changed files with 3 additions and 3 deletions
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6
sys/mips/atheros/apb.c
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@ -362,9 +362,9 @@ apb_filter(void *arg)
case AR71XX_SOC_AR9341:
case AR71XX_SOC_AR9342:
case AR71XX_SOC_AR9344:
/* Ack/clear the irq on status register for AR724x */
/* ACK/clear the given interrupt */
ATH_WRITE_REG(AR71XX_MISC_INTR_STATUS,
reg & ~(1 << irq));
(1 << irq));
break;
default:
/* fallthrough */
@ -385,7 +385,7 @@ apb_filter(void *arg)
continue;
}
/* Ignore timer interrupts */
if (irq != 0)
if (irq != 0 && irq != 8 && irq != 9 && irq != 10)
printf("Stray APB IRQ %d\n", irq);
continue;
}