Fix timer to support oneshot and periodic mode
Use 64 bit high and low counter for timecounter and delay Reviewed by: mav@, ian@ Approved by: gonzo@
This commit is contained in:
Ganbold Tsagaankhuu
parent
abd1548c8d
commit
e62a1d7908
@ -62,12 +62,18 @@ __FBSDID("$FreeBSD$");
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#define SW_TIMER0_INT_VALUE_REG 0x14
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#define SW_TIMER0_CUR_VALUE_REG 0x18
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#define SYS_TIMER_SCAL 16 /* timer clock source pre-divsion */
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#define SYS_TIMER_CLKSRC 24000000 /* timer clock source */
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#define TMR_INTER_VAL SYS_TIMER_CLKSRC/(SYS_TIMER_SCAL * 1000)
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#define SW_COUNTER64LO_REG 0xa4
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#define SW_COUNTER64HI_REG 0xa8
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#define CNT64_CTRL_REG 0xa0
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#define CLOCK_TICK_RATE TMR_INTER_VAL
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#define INITIAL_TIMECOUNTER (0xffffffff)
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#define CNT64_RL_EN 0x02 /* read latch enable */
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#define TIMER_ENABLE (1<<0)
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#define TIMER_AUTORELOAD (1<<1)
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#define TIMER_OSC24M (1<<2) /* oscillator = 24mhz */
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#define TIMER_PRESCALAR (4<<4) /* prescalar = 16 */
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#define SYS_TIMER_CLKSRC 24000000 /* clock source */
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struct a10_timer_softc {
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device_t sc_dev;
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@ -76,7 +82,7 @@ struct a10_timer_softc {
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bus_space_handle_t sc_bsh;
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void *sc_ih; /* interrupt handler */
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uint32_t sc_period;
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uint32_t clkfreq;
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uint32_t timer0_freq;
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struct eventtimer et;
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};
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@ -92,8 +98,10 @@ static int a10_timer_timer_start(struct eventtimer *,
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struct bintime *, struct bintime *);
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static int a10_timer_timer_stop(struct eventtimer *);
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static uint64_t timer_read_counter64(void);
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static int a10_timer_initialized = 0;
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static int a10_timer_intr(void *);
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static int a10_timer_hardclock(void *);
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static int a10_timer_probe(device_t);
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static int a10_timer_attach(device_t);
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@ -113,6 +121,22 @@ static struct resource_spec a10_timer_spec[] = {
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{ -1, 0 }
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};
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static uint64_t
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timer_read_counter64(void)
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{
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uint32_t lo, hi;
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/* Latch counter, wait for it to be ready to read. */
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timer_write_4(a10_timer_sc, CNT64_CTRL_REG, CNT64_RL_EN);
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while (timer_read_4(a10_timer_sc, CNT64_CTRL_REG) & CNT64_RL_EN)
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continue;
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hi = timer_read_4(a10_timer_sc, SW_COUNTER64HI_REG);
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lo = timer_read_4(a10_timer_sc, SW_COUNTER64LO_REG);
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return (((uint64_t)hi << 32) | lo);
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}
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static int
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a10_timer_probe(device_t dev)
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{
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@ -130,7 +154,6 @@ a10_timer_attach(device_t dev)
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struct a10_timer_softc *sc;
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int err;
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uint32_t val;
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uint32_t freq;
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sc = device_get_softc(dev);
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@ -143,28 +166,8 @@ a10_timer_attach(device_t dev)
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sc->sc_bst = rman_get_bustag(sc->res[0]);
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sc->sc_bsh = rman_get_bushandle(sc->res[0]);
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/* set interval */
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timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, TMR_INTER_VAL);
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/* set clock source to HOSC, 16 pre-division */
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val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
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val &= ~(0x07<<4);
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val &= ~(0x03<<2);
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val |= (4<<4) | (1<<2);
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timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
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/* set mode to auto reload */
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val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
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val |= (1<<1);
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timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
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/* Enable timer0 */
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val = timer_read_4(sc, SW_TIMER_IRQ_EN_REG);
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val |= (1<<0);
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timer_write_4(sc, SW_TIMER_IRQ_EN_REG, val);
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/* Setup and enable the timer interrupt */
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err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, a10_timer_intr,
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err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, a10_timer_hardclock,
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NULL, sc, &sc->sc_ih);
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if (err != 0) {
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bus_release_resources(dev, a10_timer_spec, sc->res);
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@ -172,17 +175,27 @@ a10_timer_attach(device_t dev)
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"err = %d\n", err);
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return (ENXIO);
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}
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freq = SYS_TIMER_CLKSRC;
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/* Set desired frequency in event timer and timecounter */
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sc->et.et_frequency = (uint64_t)freq;
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sc->clkfreq = (uint64_t)freq;
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/* Set clock source to OSC24M, 16 pre-division */
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val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
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val |= TIMER_PRESCALAR | TIMER_OSC24M;
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timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
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/* Enable timer0 */
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val = timer_read_4(sc, SW_TIMER_IRQ_EN_REG);
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val |= TIMER_ENABLE;
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timer_write_4(sc, SW_TIMER_IRQ_EN_REG, val);
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sc->timer0_freq = SYS_TIMER_CLKSRC;
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/* Set desired frequency in event timer and timecounter */
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sc->et.et_frequency = sc->timer0_freq;
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sc->et.et_name = "a10_timer Eventtimer";
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sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
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sc->et.et_quality = 1000;
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sc->et.et_min_period.sec = 0;
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sc->et.et_min_period.frac =
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((0x00000002LLU << 32) / sc->et.et_frequency) << 32;
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((0x00000005LLU << 32) / sc->et.et_frequency) << 32;
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sc->et.et_max_period.sec = 0xfffffff0U / sc->et.et_frequency;
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sc->et.et_max_period.frac =
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((0xfffffffeLLU << 32) / sc->et.et_frequency) << 32;
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@ -194,15 +207,20 @@ a10_timer_attach(device_t dev)
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if (device_get_unit(dev) == 0)
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a10_timer_sc = sc;
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a10_timer_timecounter.tc_frequency = (uint64_t)freq;
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a10_timer_timecounter.tc_frequency = sc->timer0_freq;
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tc_init(&a10_timer_timecounter);
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printf("clock: hz=%d stathz = %d\n", hz, stathz);
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if (bootverbose) {
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device_printf(sc->sc_dev, "clock: hz=%d stathz = %d\n", hz, stathz);
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device_printf(sc->sc_dev, "timer clock frequency %d\n", sc->clkfreq);
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device_printf(sc->sc_dev, "event timer clock frequency %u\n",
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sc->timer0_freq);
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device_printf(sc->sc_dev, "timecounter clock frequency %lld\n",
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a10_timer_timecounter.tc_frequency);
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}
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a10_timer_initialized = 1;
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return (0);
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}
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@ -211,25 +229,42 @@ a10_timer_timer_start(struct eventtimer *et, struct bintime *first,
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struct bintime *period)
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{
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struct a10_timer_softc *sc;
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uint32_t clo, count;
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uint32_t count;
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uint32_t val;
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sc = (struct a10_timer_softc *)et->et_priv;
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if (first != NULL) {
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sc->sc_period = 0;
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if (period != NULL) {
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sc->sc_period = (sc->et.et_frequency * (period->frac >> 32)) >> 32;
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sc->sc_period += sc->et.et_frequency * period->sec;
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}
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if (first == NULL)
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count = sc->sc_period;
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else {
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count = (sc->et.et_frequency * (first->frac >> 32)) >> 32;
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if (first->sec != 0)
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count += sc->et.et_frequency * first->sec;
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/* clear */
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timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, 0);
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clo = timer_read_4(sc, SW_TIMER0_CUR_VALUE_REG);
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clo += count;
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timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, clo);
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return (0);
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}
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return (EINVAL);
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/* Update timer values */
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timer_write_4(sc, SW_TIMER0_INT_VALUE_REG, sc->sc_period);
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timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, count);
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val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
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if (first == NULL) {
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/* periodic */
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val |= TIMER_AUTORELOAD;
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} else {
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/* oneshot */
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val &= ~TIMER_AUTORELOAD;
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}
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/* Enable timer0 */
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val |= TIMER_ENABLE;
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timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
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return (0);
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}
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static int
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@ -240,12 +275,9 @@ a10_timer_timer_stop(struct eventtimer *et)
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sc = (struct a10_timer_softc *)et->et_priv;
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/* clear */
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timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, 0);
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/* disable */
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/* Disable timer0 */
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val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
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val &= ~(1<<0); /* Disable timer0 */
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val &= ~TIMER_ENABLE;
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timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
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sc->sc_period = 0;
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@ -256,8 +288,7 @@ a10_timer_timer_stop(struct eventtimer *et)
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int
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a10_timer_get_timerfreq(struct a10_timer_softc *sc)
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{
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return (sc->clkfreq);
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return (sc->timer0_freq);
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}
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void
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@ -267,18 +298,35 @@ cpu_initclocks(void)
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}
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static int
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a10_timer_intr(void *arg)
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a10_timer_hardclock(void *arg)
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{
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struct a10_timer_softc *sc;
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uint32_t val;
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sc = (struct a10_timer_softc *)arg;
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/* Clear interrupt pending bit. */
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timer_write_4(sc, SW_TIMER_IRQ_STA_REG, 0x1);
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val = timer_read_4(sc, SW_TIMER0_CTRL_REG);
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/*
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* Disabled autoreload and sc_period > 0 means
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* timer_start was called with non NULL first value.
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* Now we will set periodic timer with the given period
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* value.
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*/
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if ((val & (1<<1)) == 0 && sc->sc_period > 0) {
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/* Update timer */
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timer_write_4(sc, SW_TIMER0_CUR_VALUE_REG, sc->sc_period);
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/* Make periodic and enable */
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val |= TIMER_AUTORELOAD | TIMER_ENABLE;
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timer_write_4(sc, SW_TIMER0_CTRL_REG, val);
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}
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if (sc->et.et_active)
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sc->et.et_event_cb(&sc->et, sc->et.et_arg);
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/* pending */
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timer_write_4(sc, SW_TIMER_IRQ_STA_REG, 0x1);
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return (FILTER_HANDLED);
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}
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@ -289,7 +337,7 @@ a10_timer_get_timecount(struct timecounter *tc)
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if (a10_timer_sc == NULL)
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return (0);
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return (timer_read_4(a10_timer_sc, SW_TIMER0_CUR_VALUE_REG));
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return ((u_int)timer_read_counter64());
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}
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static device_method_t a10_timer_methods[] = {
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@ -313,29 +361,19 @@ void
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DELAY(int usec)
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{
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uint32_t counter;
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uint32_t val, val_temp;
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int32_t nticks;
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uint64_t end, now;
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/* Timer is not initialized yet */
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if (!a10_timer_initialized) {
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for (; usec > 0; usec--)
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for (counter = 200; counter > 0; counter--)
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/* Prevent optimizing out the loop */
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for (counter = 50; counter > 0; counter--)
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cpufunc_nullop();
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return;
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}
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val = timer_read_4(a10_timer_sc, SW_TIMER0_CUR_VALUE_REG);
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nticks = ((a10_timer_sc->clkfreq / 1000000 + 1) * usec);
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now = timer_read_counter64();
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end = now + (a10_timer_sc->timer0_freq / 1000000) * (usec + 1);
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while (nticks > 0) {
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val_temp = timer_read_4(a10_timer_sc, SW_TIMER0_CUR_VALUE_REG);
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if (val > val_temp)
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nticks -= (val - val_temp);
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else
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nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));
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val = val_temp;
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}
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while (now < end)
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now = timer_read_counter64();
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}
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