This is a revised fe, Ethernet driver for MB8696x based adapters.
This commit is contained in:
jkh
parent
fb28135c8b
commit
e7242595bb
1193
sys/dev/fe/if_fe.c
1193
sys/dev/fe/if_fe.c
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,7 @@
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/*
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* Hardware specification of various 8696x based Ethernet cards.
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* Contributed by M. Sekiguchi <seki@sysrap.cs.fujitsu.co.jp>
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*
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* All Rights Reserved, Copyright (C) Fujitsu Limited 1995
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*
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* This software may be used, modified, copied, distributed, and sold,
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@ -21,12 +24,7 @@
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* SUCH DAMAGE.
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*/
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#define FE_REG_VERSION "if_fereg.h ver. 0.8"
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/*
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* Hardware specification of various 86960/86965 based Ethernet cards.
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* Contributed by M.S. <seki@sysrap.cs.fujitsu.co.jp>
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*/
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/* $Id:$ */
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/*
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* Registers on FMV-180 series' ISA bus interface ASIC.
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@ -34,61 +32,68 @@
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* Doesn't it look silly, eh? FIXME.
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*/
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#define FE_FMV0 16 /* Hardware status. */
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#define FE_FMV1 17 /* Hardware type? Always 0 */
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#define FE_FMV2 18 /* Hardware configuration. */
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#define FE_FMV3 19 /* Hardware enable. */
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#define FE_FMV0 16 /* Card status register #0 */
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#define FE_FMV1 17 /* Card status register #1 */
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#define FE_FMV2 18 /* Card config register #0 */
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#define FE_FMV3 19 /* Card config register #1 */
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#define FE_FMV4 20 /* Station address #1 */
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#define FE_FMV5 21 /* Station address #2 */
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#define FE_FMV6 22 /* Station address #3 */
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#define FE_FMV7 23 /* Station address #4 */
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#define FE_FMV8 24 /* Station address #5 */
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#define FE_FMV9 25 /* Station address #6 */
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#define FE_FMV10 26 /* Unknown; to be set to 0. */
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#define FE_FMV10 26 /* Buffer RAM control register */
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#define FE_FMV11 27 /* Buffer RAM data register */
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/*
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* FMV-180 series' ASIC register values.
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*/
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/* Magic value in FMV0 register. */
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#define FE_FMV0_MAGIC_MASK 0x78
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#define FE_FMV0_MAGIC_VALUE 0x50
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/* FMV0: Card status register #0: Misc info? */
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#define FE_FMV0_MEDIA 0x07 /* Supported physical media. */
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#define FE_FMV0_PRRDY 0x10 /* ??? */
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#define FE_FMV0_PRERR 0x20 /* ??? */
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#define FE_FMV0_ERRDY 0x40 /* ??? */
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#define FE_FMV0_IREQ 0x80 /* ??? */
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/* Model identification. */
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#define FE_FMV0_MODEL 0x07
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#define FE_FMV0_MODEL_FMV181 0x05
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#define FE_FMV0_MODEL_FMV182 0x03
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#define FE_FMV0_MEDIUM_5 0x01 /* 10base5/Dsub */
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#define FE_FMV0_MEDIUM_2 0x02 /* 10base2/BNC */
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#define FE_FMV0_MEDIUM_T 0x04 /* 10baseT/RJ45 */
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/* Card type ID? Always 0? */
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#define FE_FMV1_CARDID_MASK 0xFF
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#define FE_FMV1_CARDID_ID 0x00
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/* Card status register #1: Hardware revision. */
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#define FE_FMV1_REV 0x0F /* Card revision */
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#define FE_FMV1_UPPER 0xF0 /* Usage unknown */
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/* I/O port address assignment. */
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#define FE_FMV2_ADDR 0x07
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#define FE_FMV2_ADDR_SHIFT 0
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/* Card config register #0: I/O port address assignment. */
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#define FE_FMV2_IOS 0x07 /* I/O selection. */
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#define FE_FMV2_MES 0x38 /* ??? boot ROM? */
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#define FE_FMV2_IRS 0xC0 /* IRQ selection. */
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/* Boot ROM address assignment. */
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#define FE_FMV2_ROM 0x38
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#define FE_FMV2_ROM_SHIFT 3
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#define FE_FMV2_IOS_SHIFT 0
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#define FE_FMV2_MES_SHIFT 3
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#define FE_FMV2_IRS_SHIFT 6
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/* IRQ assignment. */
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#define FE_FMV2_IRQ 0xC0
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#define FE_FMV2_IRQ_SHIFT 6
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/* Hardware(?) enable flag. */
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#define FE_FMV3_ENABLE_FLAG 0x80
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/* Extra bits in FMV3 register. Always 0? */
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#define FE_FMV3_EXTRA_MASK 0x7F
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#define FE_FMV3_EXTRA_VALUE 0x00
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/* Card config register #1: IRQ enable */
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#define FE_FMV3_IRQENB 0x80 /* IRQ enable. */
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/*
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* EEPROM allocation of AT1700/RE2000.
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* Register(?) specific to AT1700/RE2000.
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*/
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#define FE_EEP_ATI_ADDR 8 /* Station address. (8-13) */
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#define FE_EEP_ATI_TYPE 25 /* Hardware type? FIXME. */
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#define FE_EEP_ATI_TYPE_HIGHIRQ 0x04 /* IRQ delivery? FIXME. */
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#define FE_ATI_RESET 0x1F /* Write to reset the 86965. */
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/* EEPROM allocation (offsets) of AT1700/RE2000. */
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#define FE_ATI_EEP_ADDR 0x08 /* Station address. (8-13) */
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#define FE_ATI_EEP_MEDIA 0x18 /* Media type. */
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#define FE_ATI_EEP_MAGIC 0x19 /* XXX Magic. */
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#define FE_ATI_EEP_MODEL 0x1e /* Hardware type. */
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#define FE_ATI_EEP_REVISION 0x1f /* Hardware revision. */
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/* Value for FE_ATI_EEP_MODEL. */
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#define FE_ATI_MODEL_AT1700T 0x00
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#define FE_ATI_MODEL_AT1700BT 0x01
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#define FE_ATI_MODEL_AT1700FT 0x02
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#define FE_ATI_MODEL_AT1700AT 0x03
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/*
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* Registers on MBH10302.
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@ -104,3 +109,24 @@
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#define FE_MBH0_INTR_ENABLE 0x10 /* Enable interrupts. */
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#define FE_MBH0_INTR_DISABLE 0x00 /* Disable interrupts. */
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/*
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* Registers on RE1000. (*NOT* on RE1000 Plus.)
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*/
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/* IRQ configuration. */
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#define FE_RE1000_IRQCONF 0x10
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#define FE_RE1000_IRQCONF_IRQ 0xf0
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#define FE_RE1000_IRQCONF_IRQSHIFT 4
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/* MAC (station) address. */
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#define FE_RE1000_MAC0 0x11
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#define FE_RE1000_MAC1 0x13
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#define FE_RE1000_MAC2 0x15
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#define FE_RE1000_MAC3 0x17
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#define FE_RE1000_MAC4 0x19
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#define FE_RE1000_MAC5 0x1B
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/* "Check sum" -- an xor of MAC0 through MAC5 */
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#define FE_RE1000_MACCHK 0x1D
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1193
sys/i386/isa/if_fe.c
1193
sys/i386/isa/if_fe.c
File diff suppressed because it is too large
Load Diff
@ -1,4 +1,7 @@
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/*
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* Hardware specification of various 8696x based Ethernet cards.
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* Contributed by M. Sekiguchi <seki@sysrap.cs.fujitsu.co.jp>
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*
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* All Rights Reserved, Copyright (C) Fujitsu Limited 1995
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*
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* This software may be used, modified, copied, distributed, and sold,
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@ -21,12 +24,7 @@
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* SUCH DAMAGE.
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*/
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#define FE_REG_VERSION "if_fereg.h ver. 0.8"
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/*
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* Hardware specification of various 86960/86965 based Ethernet cards.
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* Contributed by M.S. <seki@sysrap.cs.fujitsu.co.jp>
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*/
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/* $Id:$ */
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/*
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* Registers on FMV-180 series' ISA bus interface ASIC.
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@ -34,61 +32,68 @@
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* Doesn't it look silly, eh? FIXME.
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*/
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#define FE_FMV0 16 /* Hardware status. */
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#define FE_FMV1 17 /* Hardware type? Always 0 */
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#define FE_FMV2 18 /* Hardware configuration. */
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#define FE_FMV3 19 /* Hardware enable. */
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#define FE_FMV0 16 /* Card status register #0 */
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#define FE_FMV1 17 /* Card status register #1 */
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#define FE_FMV2 18 /* Card config register #0 */
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#define FE_FMV3 19 /* Card config register #1 */
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#define FE_FMV4 20 /* Station address #1 */
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#define FE_FMV5 21 /* Station address #2 */
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#define FE_FMV6 22 /* Station address #3 */
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#define FE_FMV7 23 /* Station address #4 */
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#define FE_FMV8 24 /* Station address #5 */
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#define FE_FMV9 25 /* Station address #6 */
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#define FE_FMV10 26 /* Unknown; to be set to 0. */
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#define FE_FMV10 26 /* Buffer RAM control register */
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#define FE_FMV11 27 /* Buffer RAM data register */
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/*
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* FMV-180 series' ASIC register values.
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*/
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/* Magic value in FMV0 register. */
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#define FE_FMV0_MAGIC_MASK 0x78
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#define FE_FMV0_MAGIC_VALUE 0x50
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/* FMV0: Card status register #0: Misc info? */
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#define FE_FMV0_MEDIA 0x07 /* Supported physical media. */
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#define FE_FMV0_PRRDY 0x10 /* ??? */
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#define FE_FMV0_PRERR 0x20 /* ??? */
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#define FE_FMV0_ERRDY 0x40 /* ??? */
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#define FE_FMV0_IREQ 0x80 /* ??? */
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/* Model identification. */
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#define FE_FMV0_MODEL 0x07
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#define FE_FMV0_MODEL_FMV181 0x05
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#define FE_FMV0_MODEL_FMV182 0x03
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#define FE_FMV0_MEDIUM_5 0x01 /* 10base5/Dsub */
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#define FE_FMV0_MEDIUM_2 0x02 /* 10base2/BNC */
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#define FE_FMV0_MEDIUM_T 0x04 /* 10baseT/RJ45 */
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/* Card type ID? Always 0? */
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#define FE_FMV1_CARDID_MASK 0xFF
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#define FE_FMV1_CARDID_ID 0x00
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/* Card status register #1: Hardware revision. */
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#define FE_FMV1_REV 0x0F /* Card revision */
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#define FE_FMV1_UPPER 0xF0 /* Usage unknown */
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/* I/O port address assignment. */
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#define FE_FMV2_ADDR 0x07
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#define FE_FMV2_ADDR_SHIFT 0
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/* Card config register #0: I/O port address assignment. */
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#define FE_FMV2_IOS 0x07 /* I/O selection. */
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#define FE_FMV2_MES 0x38 /* ??? boot ROM? */
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#define FE_FMV2_IRS 0xC0 /* IRQ selection. */
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/* Boot ROM address assignment. */
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#define FE_FMV2_ROM 0x38
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#define FE_FMV2_ROM_SHIFT 3
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#define FE_FMV2_IOS_SHIFT 0
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#define FE_FMV2_MES_SHIFT 3
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#define FE_FMV2_IRS_SHIFT 6
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/* IRQ assignment. */
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#define FE_FMV2_IRQ 0xC0
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#define FE_FMV2_IRQ_SHIFT 6
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/* Hardware(?) enable flag. */
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#define FE_FMV3_ENABLE_FLAG 0x80
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/* Extra bits in FMV3 register. Always 0? */
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#define FE_FMV3_EXTRA_MASK 0x7F
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#define FE_FMV3_EXTRA_VALUE 0x00
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/* Card config register #1: IRQ enable */
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#define FE_FMV3_IRQENB 0x80 /* IRQ enable. */
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/*
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* EEPROM allocation of AT1700/RE2000.
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* Register(?) specific to AT1700/RE2000.
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*/
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#define FE_EEP_ATI_ADDR 8 /* Station address. (8-13) */
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#define FE_EEP_ATI_TYPE 25 /* Hardware type? FIXME. */
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#define FE_EEP_ATI_TYPE_HIGHIRQ 0x04 /* IRQ delivery? FIXME. */
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#define FE_ATI_RESET 0x1F /* Write to reset the 86965. */
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/* EEPROM allocation (offsets) of AT1700/RE2000. */
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#define FE_ATI_EEP_ADDR 0x08 /* Station address. (8-13) */
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#define FE_ATI_EEP_MEDIA 0x18 /* Media type. */
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#define FE_ATI_EEP_MAGIC 0x19 /* XXX Magic. */
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#define FE_ATI_EEP_MODEL 0x1e /* Hardware type. */
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#define FE_ATI_EEP_REVISION 0x1f /* Hardware revision. */
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/* Value for FE_ATI_EEP_MODEL. */
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#define FE_ATI_MODEL_AT1700T 0x00
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#define FE_ATI_MODEL_AT1700BT 0x01
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#define FE_ATI_MODEL_AT1700FT 0x02
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#define FE_ATI_MODEL_AT1700AT 0x03
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/*
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* Registers on MBH10302.
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@ -104,3 +109,24 @@
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#define FE_MBH0_INTR_ENABLE 0x10 /* Enable interrupts. */
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#define FE_MBH0_INTR_DISABLE 0x00 /* Disable interrupts. */
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/*
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* Registers on RE1000. (*NOT* on RE1000 Plus.)
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*/
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/* IRQ configuration. */
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#define FE_RE1000_IRQCONF 0x10
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#define FE_RE1000_IRQCONF_IRQ 0xf0
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#define FE_RE1000_IRQCONF_IRQSHIFT 4
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/* MAC (station) address. */
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#define FE_RE1000_MAC0 0x11
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#define FE_RE1000_MAC1 0x13
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#define FE_RE1000_MAC2 0x15
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#define FE_RE1000_MAC3 0x17
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#define FE_RE1000_MAC4 0x19
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#define FE_RE1000_MAC5 0x1B
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/* "Check sum" -- an xor of MAC0 through MAC5 */
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#define FE_RE1000_MACCHK 0x1D
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