o Write the soft reset bit in the cavium core to reset. [1]
o panic if the board boot descriptor is too old... Obtained from: [1] looking at the cavium sdk's executive code
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@ -109,7 +109,7 @@ platform_cpu_init()
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void
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void
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platform_reset(void)
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platform_reset(void)
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{
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{
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mips_generic_reset();
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oct_write64(OCTEON_CIU_SOFT_RST, 1);
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}
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}
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@ -961,7 +961,9 @@ octeon_boot_params_init(register_t ptr)
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if (ptr != 0 && ptr < MAX_APP_DESC_ADDR) {
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if (ptr != 0 && ptr < MAX_APP_DESC_ADDR) {
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app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr;
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app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr;
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octeon_bd_ver = app_desc_ptr->desc_version;
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octeon_bd_ver = app_desc_ptr->desc_version;
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if (app_desc_ptr->desc_version == 6)
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if (app_desc_ptr->desc_version < 6)
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panic("Your boot code is too old to be supported.\n");
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if (app_desc_ptr->desc_version >= 6)
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bad_desc = octeon_process_app_desc_ver_6();
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bad_desc = octeon_process_app_desc_ver_6();
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}
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}
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if (bad_desc)
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if (bad_desc)
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@ -597,11 +597,9 @@ static inline mipsx_addr_size octeon_ptr_to_phys (void *ptr)
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#define OCTEON_CIU_PP_RST OCTEON_ADD_IO_SEG(0x0001070000000700ull)
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#define OCTEON_CIU_PP_RST OCTEON_ADD_IO_SEG(0x0001070000000700ull)
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#define OCTEON_CIU_SOFT_RST OCTEON_ADD_IO_SEG(0x0001070000000740ull)
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#define OCTEON_OCTEON_DID_TAG 12ULL
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#define OCTEON_OCTEON_DID_TAG 12ULL
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/*
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/*
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* octeon_addr_t
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* octeon_addr_t
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*/
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*/
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