d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

When reading PHY regs over the i2c bus, the turnaround ACK bit

Browse Source 
is read one clock edge too late. This bit is driven low by
slave (as any other input data bits from slave) when the clock
is LOW. The current code did read the bit after the clock was
driven high again.

Reviewed by:	luoqi
MFC after:	2 weeks
This commit is contained in:
Martin Blapp 2003-01-10 08:09:58 +00:00
parent c24891e9e2
commit e808cf6260
8 changed files with 8 additions and 8 deletions

2
sys/dev/nge/if_nge.c

@ -483,9 +483,9 @@ nge_mii_readreg(sc, frame)
/* Check for ack */
SIO_CLR(NGE_MEAR_MII_CLK);
DELAY(1);
ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
SIO_SET(NGE_MEAR_MII_CLK);
DELAY(1);
ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
/*
* Now try reading data bits. If the ack failed, we still

2
sys/dev/vr/if_vr.c

@ -329,9 +329,9 @@ vr_mii_readreg(sc, frame)
/* Check for ack */
SIO_CLR(VR_MIICMD_CLK);
DELAY(1);
ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
SIO_SET(VR_MIICMD_CLK);
DELAY(1);
ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
/*
* Now try reading data bits. If the ack failed, we still

2
sys/dev/xe/if_xe.c

@ -1659,9 +1659,9 @@ xe_mii_readreg(struct xe_softc *scp, struct xe_mii_frame *frame) {
/* Check for ack */
XE_MII_CLR(XE_MII_CLK);
DELAY(1);
ack = XE_INB(XE_GPR2) & XE_MII_RDD;
XE_MII_SET(XE_MII_CLK);
DELAY(1);
ack = XE_INB(XE_GPR2) & XE_MII_RDD;
/*
* Now try reading data bits. If the ack failed, we still

2
sys/pci/if_rl.c

@ -491,9 +491,9 @@ rl_mii_readreg(sc, frame)
/* Check for ack */
MII_CLR(RL_MII_CLK);
DELAY(1);
ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
MII_SET(RL_MII_CLK);
DELAY(1);
ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
/*
* Now try reading data bits. If the ack failed, we still

2
sys/pci/if_ste.c

@ -282,9 +282,9 @@ ste_mii_readreg(sc, frame)
/* Check for ack */
MII_CLR(STE_PHYCTL_MCLK);
DELAY(1);
ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
MII_SET(STE_PHYCTL_MCLK);
DELAY(1);
ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
/*
* Now try reading data bits. If the ack failed, we still

2
sys/pci/if_vr.c

@ -329,9 +329,9 @@ vr_mii_readreg(sc, frame)
/* Check for ack */
SIO_CLR(VR_MIICMD_CLK);
DELAY(1);
ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
SIO_SET(VR_MIICMD_CLK);
DELAY(1);
ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
/*
* Now try reading data bits. If the ack failed, we still

2
sys/pci/if_wb.c

@ -436,9 +436,9 @@ wb_mii_readreg(sc, frame)
/* Check for ack */
SIO_CLR(WB_SIO_MII_CLK);
DELAY(1);
ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
SIO_SET(WB_SIO_MII_CLK);
DELAY(1);
ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
SIO_CLR(WB_SIO_MII_CLK);
DELAY(1);
SIO_SET(WB_SIO_MII_CLK);

2
sys/pci/if_xl.c

@ -494,8 +494,8 @@ xl_mii_readreg(sc, frame)
/* Check for ack */
MII_CLR(XL_MII_CLK);
MII_SET(XL_MII_CLK);
ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
MII_SET(XL_MII_CLK);
/*
* Now try reading data bits. If the ack failed, we still