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Backport svn r124339 from gcc 4.3 and add opteron-sse3, athlon64-sse3

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and k8-sse3 cpu-types for -march=/-mtune= gcc options.
These new cpu-types include the SSE3 instruction set that is supported
by all newer AMD Athlon 64 and Opteron processors.
All three cpu-types are supported by clang and all gcc versions
starting with 4.3 SVN rev 124339 (at that time GPLv2 licensed).

PR:		gnu/154906
Discussed with:	kib, kan, dim
Obtained from:	gcc 4.3 (r124339, GPLv2 licensed)
MFC after:	2 weeks
This commit is contained in:
mm 2011-02-20 22:25:23 +00:00
parent 83135f45f4
commit e970f17028
3 changed files with 15 additions and 1 deletions
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9
contrib/gcc/config/i386/i386.c
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@ -1523,10 +1523,19 @@ override_options (void)
| PTA_SSE | PTA_SSE2 },
{"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
| PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
{"k8-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
| PTA_3DNOW_A | PTA_SSE | PTA_SSE2
| PTA_SSE3 },
{"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
| PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
{"opteron-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
| PTA_3DNOW_A | PTA_SSE | PTA_SSE2
| PTA_SSE3 },
{"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
| PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
{"athlon64-sse3", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
| PTA_3DNOW_A | PTA_SSE | PTA_SSE2
| PTA_SSE3 },
{"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
| PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
{"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ },

5
contrib/gcc/doc/gcc.1
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@ -129,7 +129,7 @@
.\" ========================================================================
.\"
.IX Title "GCC 1"
.TH GCC 1 "2007-07-19" "gcc-4.2.1" "GNU"
.TH GCC 1 "2011-02-20" "gcc-4.2.1" "GNU"
.SH "NAME"
gcc \- GNU project C and C++ compiler
.SH "SYNOPSIS"
@ -8751,6 +8751,9 @@ instruction set support.
.IX Item "k8, opteron, athlon64, athlon-fx"
\&\s-1AMD\s0 K8 core based CPUs with x86\-64 instruction set support. (This supersets
\&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3dNOW!, enhanced 3dNOW! and 64\-bit instruction set extensions.)
.IP "\fIk8-sse3, opteron-sse3, athlon64-sse3\fR" 4
.IX Item "k8-sse3, opteron-sse3, athlon64-sse3"
Improved versions of k8, opteron and athlon64 with \s-1SSE3\s0 instruction set support.
.IP "\fIwinchip\-c6\fR" 4
.IX Item "winchip-c6"
\&\s-1IDT\s0 Winchip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction

2
contrib/gcc/doc/invoke.texi
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@ -9382,6 +9382,8 @@ instruction set support.
@item k8, opteron, athlon64, athlon-fx
AMD K8 core based CPUs with x86-64 instruction set support. (This supersets
MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
@item k8-sse3, opteron-sse3, athlon64-sse3
Improved versions of k8, opteron and athlon64 with SSE3 instruction set support.
@item winchip-c6
IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
set support.