o go ahead and route the interupt, even if it is supposedly unique.
there are some strange machines that seem to need this. o delete bogus comment. o don't use the the bios for read/writing config space. They interact badly with SMP and being called from ISR. This brings -current in line with -stable. # make the latter #ifdef on USE_PCI_BIOS_FOR_READ_WRITE in case we # need to go back in a hurry.
This commit is contained in:
Warner Losh
parent
3d9841b4eb
commit
ea5420299c
@ -71,8 +71,10 @@ static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin);
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static void pci_print_irqmask(u_int16_t irqs);
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static void pci_print_route_table(struct PIR_table *prt, int size);
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#ifdef USE_PCI_BIOS_FOR_READ_WRITE
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static int pcibios_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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#endif
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static int pcibios_cfgopen(void);
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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@ -195,9 +197,13 @@ pci_cfgregopen(void)
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static u_int32_t
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pci_do_cfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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#ifdef USE_PCI_BIOS_FOR_READ_WRITE
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return(usebios ?
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pcibios_cfgread(bus, slot, func, reg, bytes) :
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pcireg_cfgread(bus, slot, func, reg, bytes));
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#else
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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#endif
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}
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u_int32_t
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@ -266,19 +272,18 @@ pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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void
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pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
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{
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#ifdef USE_PCI_BIOS_FOR_READ_WRITE
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if (usebios)
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pcibios_cfgwrite(bus, slot, func, reg, data, bytes);
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else
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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#else
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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#endif
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}
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/*
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* Route a PCI interrupt
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*
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* XXX we don't do anything "right" with the function number in the PIR table
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* (because the consumer isn't currently passing it in). We don't care
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* anyway, due to the way PCI interrupts are assigned.
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*/
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int
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pci_cfgintr(int bus, int device, int pin, int oldirq)
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@ -324,8 +329,6 @@ pci_cfgintr(int bus, int device, int pin, int oldirq)
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irq = pci_cfgintr_linked(pe, pin);
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if (irq == PCI_INVALID_IRQ)
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irq = pci_cfgintr_unique(pe, pin);
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if (irq != PCI_INVALID_IRQ)
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already = 1;
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if (irq == PCI_INVALID_IRQ)
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irq = pci_cfgintr_virgin(pe, pin);
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if (irq == PCI_INVALID_IRQ)
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@ -599,6 +602,7 @@ pci_probe_route_table(int bus)
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return (0);
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}
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#ifdef USE_PCI_BIOS_FOR_READ_WRITE
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/*
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* Config space access using BIOS functions
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*/
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@ -654,6 +658,7 @@ pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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args.edi = reg;
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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}
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#endif
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/*
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* Determine whether there is a PCI BIOS present
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@ -71,8 +71,10 @@ static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin);
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static void pci_print_irqmask(u_int16_t irqs);
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static void pci_print_route_table(struct PIR_table *prt, int size);
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#ifdef USE_PCI_BIOS_FOR_READ_WRITE
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static int pcibios_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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#endif
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static int pcibios_cfgopen(void);
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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@ -195,9 +197,13 @@ pci_cfgregopen(void)
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static u_int32_t
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pci_do_cfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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#ifdef USE_PCI_BIOS_FOR_READ_WRITE
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return(usebios ?
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pcibios_cfgread(bus, slot, func, reg, bytes) :
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pcireg_cfgread(bus, slot, func, reg, bytes));
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#else
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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#endif
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}
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u_int32_t
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@ -266,19 +272,18 @@ pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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void
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pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
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{
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#ifdef USE_PCI_BIOS_FOR_READ_WRITE
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if (usebios)
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pcibios_cfgwrite(bus, slot, func, reg, data, bytes);
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else
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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#else
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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#endif
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}
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/*
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* Route a PCI interrupt
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*
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* XXX we don't do anything "right" with the function number in the PIR table
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* (because the consumer isn't currently passing it in). We don't care
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* anyway, due to the way PCI interrupts are assigned.
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*/
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int
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pci_cfgintr(int bus, int device, int pin, int oldirq)
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@ -324,8 +329,6 @@ pci_cfgintr(int bus, int device, int pin, int oldirq)
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irq = pci_cfgintr_linked(pe, pin);
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if (irq == PCI_INVALID_IRQ)
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irq = pci_cfgintr_unique(pe, pin);
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if (irq != PCI_INVALID_IRQ)
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already = 1;
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if (irq == PCI_INVALID_IRQ)
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irq = pci_cfgintr_virgin(pe, pin);
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if (irq == PCI_INVALID_IRQ)
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@ -599,6 +602,7 @@ pci_probe_route_table(int bus)
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return (0);
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}
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#ifdef USE_PCI_BIOS_FOR_READ_WRITE
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/*
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* Config space access using BIOS functions
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*/
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@ -654,6 +658,7 @@ pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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args.edi = reg;
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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}
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#endif
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/*
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* Determine whether there is a PCI BIOS present
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@ -71,8 +71,10 @@ static int pci_cfgintr_virgin(struct PIR_entry *pe, int pin);
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static void pci_print_irqmask(u_int16_t irqs);
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static void pci_print_route_table(struct PIR_table *prt, int size);
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#ifdef USE_PCI_BIOS_FOR_READ_WRITE
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static int pcibios_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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#endif
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static int pcibios_cfgopen(void);
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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@ -195,9 +197,13 @@ pci_cfgregopen(void)
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static u_int32_t
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pci_do_cfgregread(int bus, int slot, int func, int reg, int bytes)
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{
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#ifdef USE_PCI_BIOS_FOR_READ_WRITE
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return(usebios ?
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pcibios_cfgread(bus, slot, func, reg, bytes) :
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pcireg_cfgread(bus, slot, func, reg, bytes));
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#else
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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#endif
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}
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u_int32_t
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@ -266,19 +272,18 @@ pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
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void
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pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
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{
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#ifdef USE_PCI_BIOS_FOR_READ_WRITE
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if (usebios)
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pcibios_cfgwrite(bus, slot, func, reg, data, bytes);
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else
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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#else
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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#endif
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}
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/*
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* Route a PCI interrupt
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*
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* XXX we don't do anything "right" with the function number in the PIR table
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* (because the consumer isn't currently passing it in). We don't care
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* anyway, due to the way PCI interrupts are assigned.
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*/
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int
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pci_cfgintr(int bus, int device, int pin, int oldirq)
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@ -324,8 +329,6 @@ pci_cfgintr(int bus, int device, int pin, int oldirq)
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irq = pci_cfgintr_linked(pe, pin);
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if (irq == PCI_INVALID_IRQ)
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irq = pci_cfgintr_unique(pe, pin);
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if (irq != PCI_INVALID_IRQ)
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already = 1;
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if (irq == PCI_INVALID_IRQ)
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irq = pci_cfgintr_virgin(pe, pin);
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if (irq == PCI_INVALID_IRQ)
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@ -599,6 +602,7 @@ pci_probe_route_table(int bus)
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return (0);
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}
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#ifdef USE_PCI_BIOS_FOR_READ_WRITE
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/*
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* Config space access using BIOS functions
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*/
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@ -654,6 +658,7 @@ pcibios_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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args.edi = reg;
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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}
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#endif
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/*
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* Determine whether there is a PCI BIOS present
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