From eaf00819bcfa90ab7ac8af324826eb985197d8c8 Mon Sep 17 00:00:00 2001 From: Konstantin Belousov Date: Sun, 23 May 2021 19:38:54 +0300 Subject: [PATCH] Add support for Gemini Lake LPSS UARTs. With this patch: % dmesg | grep -i uart uart2: mem 0xa1426000-0xa1426fff,0xa1425000-0xa1425fff irq 4 at device 24.0 on pci0 uart3: mem 0xa1424000-0xa1424fff,0xa1423000-0xa1423fff irq 5 at device 24.1 on pci0 uart4: mem 0xfea10000-0xfea10fff irq 6 at device 24.2 on pci0 uart5: mem 0xa1422000-0xa1422fff,0xa1421000-0xa1421fff irq 7 at device 24.3 on pci0 PR: 256101 Submitted by: Daniel Ponte MFC after: 1 week --- sys/dev/uart/uart_bus_pci.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/sys/dev/uart/uart_bus_pci.c b/sys/dev/uart/uart_bus_pci.c index 707b82dc078b..f7e9bd6ac401 100644 --- a/sys/dev/uart/uart_bus_pci.c +++ b/sys/dev/uart/uart_bus_pci.c @@ -145,6 +145,14 @@ static const struct pci_id pci_ns8250_ids[] = { { 0x8086, 0x2a07, 0xffff, 0, "Intel AMT - PM965/GM965 KT Controller", 0x10 }, { 0x8086, 0x2a47, 0xffff, 0, "Mobile 4 Series Chipset KT Controller", 0x10 }, { 0x8086, 0x2e17, 0xffff, 0, "4 Series Chipset Serial KT Controller", 0x10 }, +{ 0x8086, 0x31bc, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 0", 0x10, + 24 * DEFAULT_RCLK, 2 }, +{ 0x8086, 0x31be, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 1", 0x10, + 24 * DEFAULT_RCLK, 2 }, +{ 0x8086, 0x31c0, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 2", 0x10, + 24 * DEFAULT_RCLK, 2 }, +{ 0x8086, 0x31ee, 0xffff, 0, "Intel Gemini Lake SIO/LPSS UART 3", 0x10, + 24 * DEFAULT_RCLK, 2 }, { 0x8086, 0x3b67, 0xffff, 0, "5 Series/3400 Series Chipset KT Controller", 0x10 }, { 0x8086, 0x5abc, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 0", 0x10,