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Refactor timer management code with priority to one-shot operation mode.

Browse Source 
The main goal of this is to generate timer interrupts only when there is
some work to do. When CPU is busy interrupts are generating at full rate
of hz + stathz to fullfill scheduler and timekeeping requirements. But
when CPU is idle, only minimum set of interrupts (down to 8 interrupts per
second per CPU now), needed to handle scheduled callouts is executed.
This allows significantly increase idle CPU sleep time, increasing effect
of static power-saving technologies. Also it should reduce host CPU load
on virtualized systems, when guest system is idle.

There is set of tunables, also available as writable sysctls, allowing to
control wanted event timer subsystem behavior:
  kern.eventtimer.timer - allows to choose event timer hardware to use.
On x86 there is up to 4 different kinds of timers. Depending on whether
chosen timer is per-CPU, behavior of other options slightly differs.
  kern.eventtimer.periodic - allows to choose periodic and one-shot
operation mode. In periodic mode, current timer hardware taken as the only
source of time for time events. This mode is quite alike to previous kernel
behavior. One-shot mode instead uses currently selected time counter
hardware to schedule all needed events one by one and program timer to
generate interrupt exactly in specified time. Default value depends of
chosen timer capabilities, but one-shot mode is preferred, until other is
forced by user or hardware.
  kern.eventtimer.singlemul - in periodic mode specifies how much times
higher timer frequency should be, to not strictly alias hardclock() and
statclock() events. Default values are 2 and 4, but could be reduced to 1
if extra interrupts are unwanted.
  kern.eventtimer.idletick - makes each CPU to receive every timer interrupt
independently of whether they busy or not. By default this options is
disabled. If chosen timer is per-CPU and runs in periodic mode, this option
has no effect - all interrupts are generating.

As soon as this patch modifies cpu_idle() on some platforms, I have also
refactored one on x86. Now it makes use of MONITOR/MWAIT instrunctions
(if supported) under high sleep/wakeup rate, as fast alternative to other
methods. It allows SMP scheduler to wake up sleeping CPUs much faster
without using IPI, significantly increasing performance on some highly
task-switching loads.

Tested by:	many (on i386, amd64, sparc64 and powerc)
H/W donated by:	Gheorghe Ardelean
Sponsored by:	iXsystems, Inc.
This commit is contained in:
mav 2010-09-13 07:25:35 +00:00
parent 18db545520
commit eb4931dc6c
36 changed files with 1207 additions and 737 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

246
sys/amd64/amd64/machdep.c
View File

@ -585,59 +585,89 @@ cpu_halt(void)
}
void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */
static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */
static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
TUNABLE_INT("machdep.idle_mwait", &idle_mwait);
SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait,
0, "Use MONITOR/MWAIT for short idle");
static void
cpu_idle_hlt(int busy)
{
/*
* we must absolutely guarentee that hlt is the next instruction
* after sti or we introduce a timing window.
*/
disable_intr();
if (sched_runnable())
enable_intr();
else
__asm __volatile("sti; hlt");
}
#define STATE_RUNNING 0x0
#define STATE_MWAIT 0x1
#define STATE_SLEEPING 0x2
static void
cpu_idle_acpi(int busy)
{
int *state;
state = (int *)PCPU_PTR(monitorbuf);
*state = STATE_SLEEPING;
disable_intr();
if (sched_runnable())
if (sched_runnable())
enable_intr();
else if (cpu_idle_hook)
cpu_idle_hook();
else
__asm __volatile("sti; hlt");
*state = STATE_RUNNING;
}
static int cpu_ident_amdc1e = 0;
static int
cpu_probe_amdc1e(void)
static void
cpu_idle_hlt(int busy)
{
int *state;
state = (int *)PCPU_PTR(monitorbuf);
*state = STATE_SLEEPING;
/*
* We must absolutely guarentee that hlt is the next instruction
* after sti or we introduce a timing window.
*/
disable_intr();
if (sched_runnable())
enable_intr();
else
__asm __volatile("sti; hlt");
*state = STATE_RUNNING;
}
/*
* MWAIT cpu power states. Lower 4 bits are sub-states.
*/
#define MWAIT_C0 0xf0
#define MWAIT_C1 0x00
#define MWAIT_C2 0x10
#define MWAIT_C3 0x20
#define MWAIT_C4 0x30
static void
cpu_idle_mwait(int busy)
{
int *state;
state = (int *)PCPU_PTR(monitorbuf);
*state = STATE_MWAIT;
if (!sched_runnable()) {
cpu_monitor(state, 0, 0);
if (*state == STATE_MWAIT)
cpu_mwait(0, MWAIT_C1);
}
*state = STATE_RUNNING;
}
static void
cpu_idle_spin(int busy)
{
int *state;
int i;
/*
* Forget it, if we're not using local APIC timer.
*/
if (resource_disabled("apic", 0) ||
(resource_int_value("apic", 0, "clock", &i) == 0 && i == 0))
return (0);
/*
* Detect the presence of C1E capability mostly on latest
* dual-cores (or future) k8 family.
*/
if (cpu_vendor_id == CPU_VENDOR_AMD &&
(cpu_id & 0x00000f00) == 0x00000f00 &&
(cpu_id & 0x0fff0000) >= 0x00040000) {
cpu_ident_amdc1e = 1;
return (1);
state = (int *)PCPU_PTR(monitorbuf);
*state = STATE_RUNNING;
for (i = 0; i < 1000; i++) {
if (sched_runnable())
return;
cpu_spinwait();
}
return (0);
}
/*
@ -655,110 +685,83 @@ cpu_probe_amdc1e(void)
#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)
static void
cpu_idle_amdc1e(int busy)
cpu_probe_amdc1e(void)
{
disable_intr();
if (sched_runnable())
enable_intr();
else {
uint64_t msr;
msr = rdmsr(MSR_AMDK8_IPM);
if (msr & AMDK8_CMPHALT)
wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
if (cpu_idle_hook)
cpu_idle_hook();
else
__asm __volatile("sti; hlt");
/*
* Detect the presence of C1E capability mostly on latest
* dual-cores (or future) k8 family.
*/
if (cpu_vendor_id == CPU_VENDOR_AMD &&
(cpu_id & 0x00000f00) == 0x00000f00 &&
(cpu_id & 0x0fff0000) >= 0x00040000) {
cpu_ident_amdc1e = 1;
}
}
static void
cpu_idle_spin(int busy)
{
return;
}
void (*cpu_idle_fn)(int) = cpu_idle_acpi;
void
cpu_idle(int busy)
{
uint64_t msr;
CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
busy, curcpu);
#ifdef SMP
if (mp_grab_cpu_hlt())
return;
#endif
cpu_idle_fn(busy);
}
/*
* mwait cpu power states. Lower 4 bits are sub-states.
*/
#define MWAIT_C0 0xf0
#define MWAIT_C1 0x00
#define MWAIT_C2 0x10
#define MWAIT_C3 0x20
#define MWAIT_C4 0x30
#define MWAIT_DISABLED 0x0
#define MWAIT_WOKEN 0x1
#define MWAIT_WAITING 0x2
static void
cpu_idle_mwait(int busy)
{
int *mwait;
mwait = (int *)PCPU_PTR(monitorbuf);
*mwait = MWAIT_WAITING;
if (sched_runnable())
return;
cpu_monitor(mwait, 0, 0);
if (*mwait == MWAIT_WAITING)
cpu_mwait(0, MWAIT_C1);
}
static void
cpu_idle_mwait_hlt(int busy)
{
int *mwait;
mwait = (int *)PCPU_PTR(monitorbuf);
if (busy == 0) {
*mwait = MWAIT_DISABLED;
cpu_idle_hlt(busy);
return;
/* If we are busy - try to use fast methods. */
if (busy) {
if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
cpu_idle_mwait(busy);
goto out;
}
}
*mwait = MWAIT_WAITING;
if (sched_runnable())
return;
cpu_monitor(mwait, 0, 0);
if (*mwait == MWAIT_WAITING)
cpu_mwait(0, MWAIT_C1);
/* If we have time - switch timers into idle mode. */
if (!busy) {
critical_enter();
cpu_idleclock();
}
/* Apply AMD APIC timer C1E workaround. */
if (cpu_ident_amdc1e && cpu_disable_deep_sleep) {
msr = rdmsr(MSR_AMDK8_IPM);
if (msr & AMDK8_CMPHALT)
wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
}
/* Call main idle method. */
cpu_idle_fn(busy);
/* Switch timers mack into active mode. */
if (!busy) {
cpu_activeclock();
critical_exit();
}
out:
CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
busy, curcpu);
}
int
cpu_idle_wakeup(int cpu)
{
struct pcpu *pcpu;
int *mwait;
int *state;
if (cpu_idle_fn == cpu_idle_spin)
return (1);
if (cpu_idle_fn != cpu_idle_mwait && cpu_idle_fn != cpu_idle_mwait_hlt)
return (0);
pcpu = pcpu_find(cpu);
mwait = (int *)pcpu->pc_monitorbuf;
state = (int *)pcpu->pc_monitorbuf;
/*
* This doesn't need to be atomic since missing the race will
* simply result in unnecessary IPIs.
*/
if (cpu_idle_fn == cpu_idle_mwait_hlt && *mwait == MWAIT_DISABLED)
if (*state == STATE_SLEEPING)
return (0);
*mwait = MWAIT_WOKEN;
if (*state == STATE_MWAIT)
*state = STATE_RUNNING;
return (1);
}
@ -771,8 +774,6 @@ struct {
} idle_tbl[] = {
{ cpu_idle_spin, "spin" },
{ cpu_idle_mwait, "mwait" },
{ cpu_idle_mwait_hlt, "mwait_hlt" },
{ cpu_idle_amdc1e, "amdc1e" },
{ cpu_idle_hlt, "hlt" },
{ cpu_idle_acpi, "acpi" },
{ NULL, NULL }
@ -791,8 +792,8 @@ idle_sysctl_available(SYSCTL_HANDLER_ARGS)
if (strstr(idle_tbl[i].id_name, "mwait") &&
(cpu_feature2 & CPUID2_MON) == 0)
continue;
if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 &&
cpu_ident_amdc1e == 0)
if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
cpu_idle_hook == NULL)
continue;
p += sprintf(p, "%s, ", idle_tbl[i].id_name);
}
@ -801,6 +802,9 @@ idle_sysctl_available(SYSCTL_HANDLER_ARGS)
return (error);
}
SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
0, 0, idle_sysctl_available, "A", "list of available idle functions");
static int
idle_sysctl(SYSCTL_HANDLER_ARGS)
{
@ -824,8 +828,8 @@ idle_sysctl(SYSCTL_HANDLER_ARGS)
if (strstr(idle_tbl[i].id_name, "mwait") &&
(cpu_feature2 & CPUID2_MON) == 0)
continue;
if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 &&
cpu_ident_amdc1e == 0)
if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
cpu_idle_hook == NULL)
continue;
if (strcmp(idle_tbl[i].id_name, buf))
continue;
@ -835,9 +839,6 @@ idle_sysctl(SYSCTL_HANDLER_ARGS)
return (EINVAL);
}
SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
0, 0, idle_sysctl_available, "A", "list of available idle functions");
SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
idle_sysctl, "A", "currently selected idle function");
@ -1743,8 +1744,7 @@ hammer_time(u_int64_t modulep, u_int64_t physfree)
}
#endif
if (cpu_probe_amdc1e())
cpu_idle_fn = cpu_idle_amdc1e;
cpu_probe_amdc1e();
/* Location of kernel stack for locore */
return ((u_int64_t)thread0.td_pcb);

24
sys/amd64/amd64/mp_machdep.c
View File

@ -118,7 +118,6 @@ u_long *ipi_invlcache_counts[MAXCPU];
u_long *ipi_rendezvous_counts[MAXCPU];
u_long *ipi_lazypmap_counts[MAXCPU];
static u_long *ipi_hardclock_counts[MAXCPU];
static u_long *ipi_statclock_counts[MAXCPU];
#endif
extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
@ -1196,16 +1195,22 @@ smp_masked_invlpg_range(cpumask_t mask, vm_offset_t addr1, vm_offset_t addr2)
void
ipi_bitmap_handler(struct trapframe frame)
{
struct trapframe *oldframe;
struct thread *td;
int cpu = PCPU_GET(cpuid);
u_int ipi_bitmap;
critical_enter();
td = curthread;
td->td_intr_nesting_level++;
oldframe = td->td_intr_frame;
td->td_intr_frame = &frame;
ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
if (ipi_bitmap & (1 << IPI_PREEMPT)) {
#ifdef COUNT_IPIS
(*ipi_preempt_counts[cpu])++;
#endif
sched_preempt(curthread);
sched_preempt(td);
}
if (ipi_bitmap & (1 << IPI_AST)) {
#ifdef COUNT_IPIS
@ -1217,14 +1222,11 @@ ipi_bitmap_handler(struct trapframe frame)
#ifdef COUNT_IPIS
(*ipi_hardclock_counts[cpu])++;
#endif
hardclockintr(&frame);
}
if (ipi_bitmap & (1 << IPI_STATCLOCK)) {
#ifdef COUNT_IPIS
(*ipi_statclock_counts[cpu])++;
#endif
statclockintr(&frame);
hardclockintr();
}
td->td_intr_frame = oldframe;
td->td_intr_nesting_level--;
critical_exit();
}
/*
@ -1579,8 +1581,6 @@ mp_ipi_intrcnt(void *dummy)
intrcnt_add(buf, &ipi_lazypmap_counts[i]);
snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
intrcnt_add(buf, &ipi_hardclock_counts[i]);
snprintf(buf, sizeof(buf), "cpu%d:statclock", i);
intrcnt_add(buf, &ipi_statclock_counts[i]);
}
}
SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);

3
sys/amd64/include/apicvar.h
View File

@ -123,8 +123,7 @@
#define IPI_AST 0 /* Generate software trap. */
#define IPI_PREEMPT 1
#define IPI_HARDCLOCK 2
#define IPI_STATCLOCK 3
#define IPI_BITMAP_LAST IPI_STATCLOCK
#define IPI_BITMAP_LAST IPI_HARDCLOCK
#define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
#define IPI_STOP (APIC_IPI_INTS + 7) /* Stop CPU until restarted. */

18
sys/dev/acpica/acpi_cpu.c
View File

@ -900,7 +900,13 @@ acpi_cpu_idle()
/* Find the lowest state that has small enough latency. */
cx_next_idx = 0;
for (i = sc->cpu_cx_lowest; i >= 0; i--) {
#ifndef __ia64__
if (cpu_disable_deep_sleep)
i = sc->cpu_non_c3;
else
#endif
i = sc->cpu_cx_lowest;
for (; i >= 0; i--) {
if (sc->cpu_cx_states[i].trans_lat * 3 <= sc->cpu_prev_sleep) {
cx_next_idx = i;
break;
@ -929,15 +935,17 @@ acpi_cpu_idle()
/*
* Execute HLT (or equivalent) and wait for an interrupt. We can't
* precisely calculate the time spent in C1 since the place we wake up
* is an ISR. Assume we slept no more then half of quantum.
* is an ISR. Assume we slept no more then half of quantum, unless
* we are called inside critical section, delaying context switch.
*/
if (cx_next->type == ACPI_STATE_C1) {
AcpiHwRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock);
acpi_cpu_c1();
AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock);
end_time = acpi_TimerDelta(end_time, start_time);
sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 +
min(PM_USEC(end_time), 500000 / hz)) / 4;
end_time = PM_USEC(acpi_TimerDelta(end_time, start_time));
if (curthread->td_critnest == 0)
end_time = min(end_time, 500000 / hz);
sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4;
return;
}

6
sys/dev/acpica/acpi_hpet.c
View File

@ -683,15 +683,15 @@ hpet_detach(device_t dev)
static int
hpet_suspend(device_t dev)
{
struct hpet_softc *sc;
// struct hpet_softc *sc;
/*
* Disable the timer during suspend. The timer will not lose
* its state in S1 or S2, but we are required to disable
* it.
*/
sc = device_get_softc(dev);
hpet_disable(sc);
// sc = device_get_softc(dev);
// hpet_disable(sc);
return (0);
}

266
sys/i386/i386/machdep.c
View File

@ -1175,9 +1175,6 @@ cpu_est_clockrate(int cpu_id, uint64_t *rate)
return (0);
}
void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */
#ifdef XEN
void
@ -1208,60 +1205,94 @@ cpu_halt(void)
__asm__ ("hlt");
}
static void
cpu_idle_hlt(int busy)
{
/*
* we must absolutely guarentee that hlt is the next instruction
* after sti or we introduce a timing window.
*/
disable_intr();
if (sched_runnable())
enable_intr();
else
__asm __volatile("sti; hlt");
}
#endif
void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */
static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */
static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
TUNABLE_INT("machdep.idle_mwait", &idle_mwait);
SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait,
0, "Use MONITOR/MWAIT for short idle");
#define STATE_RUNNING 0x0
#define STATE_MWAIT 0x1
#define STATE_SLEEPING 0x2
static void
cpu_idle_acpi(int busy)
{
int *state;
state = (int *)PCPU_PTR(monitorbuf);
*state = STATE_SLEEPING;
disable_intr();
if (sched_runnable())
if (sched_runnable())
enable_intr();
else if (cpu_idle_hook)
cpu_idle_hook();
else
__asm __volatile("sti; hlt");
*state = STATE_RUNNING;
}
static int cpu_ident_amdc1e = 0;
#ifndef XEN
static void
cpu_idle_hlt(int busy)
{
int *state;
static int
cpu_probe_amdc1e(void)
{
#ifdef DEV_APIC
state = (int *)PCPU_PTR(monitorbuf);
*state = STATE_SLEEPING;
/*
* We must absolutely guarentee that hlt is the next instruction
* after sti or we introduce a timing window.
*/
disable_intr();
if (sched_runnable())
enable_intr();
else
__asm __volatile("sti; hlt");
*state = STATE_RUNNING;
}
#endif
/*
* MWAIT cpu power states. Lower 4 bits are sub-states.
*/
#define MWAIT_C0 0xf0
#define MWAIT_C1 0x00
#define MWAIT_C2 0x10
#define MWAIT_C3 0x20
#define MWAIT_C4 0x30
static void
cpu_idle_mwait(int busy)
{
int *state;
state = (int *)PCPU_PTR(monitorbuf);
*state = STATE_MWAIT;
if (!sched_runnable()) {
cpu_monitor(state, 0, 0);
if (*state == STATE_MWAIT)
cpu_mwait(0, MWAIT_C1);
}
*state = STATE_RUNNING;
}
static void
cpu_idle_spin(int busy)
{
int *state;
int i;
/*
* Forget it, if we're not using local APIC timer.
*/
if (resource_disabled("apic", 0) ||
(resource_int_value("apic", 0, "clock", &i) == 0 && i == 0))
return (0);
/*
* Detect the presence of C1E capability mostly on latest
* dual-cores (or future) k8 family.
*/
if (cpu_vendor_id == CPU_VENDOR_AMD &&
(cpu_id & 0x00000f00) == 0x00000f00 &&
(cpu_id & 0x0fff0000) >= 0x00040000) {
cpu_ident_amdc1e = 1;
return (1);
state = (int *)PCPU_PTR(monitorbuf);
*state = STATE_RUNNING;
for (i = 0; i < 1000; i++) {
if (sched_runnable())
return;
cpu_spinwait();
}
#endif
return (0);
}
/*
@ -1279,32 +1310,20 @@ cpu_probe_amdc1e(void)
#define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)
static void
cpu_idle_amdc1e(int busy)
cpu_probe_amdc1e(void)
{
disable_intr();
if (sched_runnable())
enable_intr();
else {
uint64_t msr;
msr = rdmsr(MSR_AMDK8_IPM);
if (msr & AMDK8_CMPHALT)
wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
if (cpu_idle_hook)
cpu_idle_hook();
else
__asm __volatile("sti; hlt");
/*
* Detect the presence of C1E capability mostly on latest
* dual-cores (or future) k8 family.
*/
if (cpu_vendor_id == CPU_VENDOR_AMD &&
(cpu_id & 0x00000f00) == 0x00000f00 &&
(cpu_id & 0x0fff0000) >= 0x00040000) {
cpu_ident_amdc1e = 1;
}
}
static void
cpu_idle_spin(int busy)
{
return;
}
#ifdef XEN
void (*cpu_idle_fn)(int) = cpu_idle_hlt;
#else
@ -1314,79 +1333,72 @@ void (*cpu_idle_fn)(int) = cpu_idle_acpi;
void
cpu_idle(int busy)
{
uint64_t msr;
CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
busy, curcpu);
#if defined(SMP) && !defined(XEN)
if (mp_grab_cpu_hlt())
return;
#endif
cpu_idle_fn(busy);
}
/*
* mwait cpu power states. Lower 4 bits are sub-states.
*/
#define MWAIT_C0 0xf0
#define MWAIT_C1 0x00
#define MWAIT_C2 0x10
#define MWAIT_C3 0x20
#define MWAIT_C4 0x30
#define MWAIT_DISABLED 0x0
#define MWAIT_WOKEN 0x1
#define MWAIT_WAITING 0x2
static void
cpu_idle_mwait(int busy)
{
int *mwait;
mwait = (int *)PCPU_PTR(monitorbuf);
*mwait = MWAIT_WAITING;
if (sched_runnable())
return;
cpu_monitor(mwait, 0, 0);
if (*mwait == MWAIT_WAITING)
cpu_mwait(0, MWAIT_C1);
}
static void
cpu_idle_mwait_hlt(int busy)
{
int *mwait;
mwait = (int *)PCPU_PTR(monitorbuf);
if (busy == 0) {
*mwait = MWAIT_DISABLED;
cpu_idle_hlt(busy);
return;
/* If we are busy - try to use fast methods. */
if (busy) {
if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
cpu_idle_mwait(busy);
goto out;
}
}
*mwait = MWAIT_WAITING;
if (sched_runnable())
return;
cpu_monitor(mwait, 0, 0);
if (*mwait == MWAIT_WAITING)
cpu_mwait(0, MWAIT_C1);
#ifndef XEN
/* If we have time - switch timers into idle mode. */
if (!busy) {
critical_enter();
cpu_idleclock();
}
#endif
/* Apply AMD APIC timer C1E workaround. */
if (cpu_ident_amdc1e
#ifndef XEN
&& cpu_disable_deep_sleep
#endif
) {
msr = rdmsr(MSR_AMDK8_IPM);
if (msr & AMDK8_CMPHALT)
wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
}
/* Call main idle method. */
cpu_idle_fn(busy);
#ifndef XEN
/* Switch timers mack into active mode. */
if (!busy) {
cpu_activeclock();
critical_exit();
}
#endif
out:
CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
busy, curcpu);
}
int
cpu_idle_wakeup(int cpu)
{
struct pcpu *pcpu;
int *mwait;
int *state;
if (cpu_idle_fn == cpu_idle_spin)
return (1);
if (cpu_idle_fn != cpu_idle_mwait && cpu_idle_fn != cpu_idle_mwait_hlt)
return (0);
pcpu = pcpu_find(cpu);
mwait = (int *)pcpu->pc_monitorbuf;
state = (int *)pcpu->pc_monitorbuf;
/*
* This doesn't need to be atomic since missing the race will
* simply result in unnecessary IPIs.
*/
if (cpu_idle_fn == cpu_idle_mwait_hlt && *mwait == MWAIT_DISABLED)
if (*state == STATE_SLEEPING)
return (0);
*mwait = MWAIT_WOKEN;
if (*state == STATE_MWAIT)
*state = STATE_RUNNING;
return (1);
}
@ -1399,8 +1411,6 @@ struct {
} idle_tbl[] = {
{ cpu_idle_spin, "spin" },
{ cpu_idle_mwait, "mwait" },
{ cpu_idle_mwait_hlt, "mwait_hlt" },
{ cpu_idle_amdc1e, "amdc1e" },
{ cpu_idle_hlt, "hlt" },
{ cpu_idle_acpi, "acpi" },
{ NULL, NULL }
@ -1419,8 +1429,8 @@ idle_sysctl_available(SYSCTL_HANDLER_ARGS)
if (strstr(idle_tbl[i].id_name, "mwait") &&
(cpu_feature2 & CPUID2_MON) == 0)
continue;
if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 &&
cpu_ident_amdc1e == 0)
if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
cpu_idle_hook == NULL)
continue;
p += sprintf(p, "%s, ", idle_tbl[i].id_name);
}
@ -1429,6 +1439,9 @@ idle_sysctl_available(SYSCTL_HANDLER_ARGS)
return (error);
}
SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
0, 0, idle_sysctl_available, "A", "list of available idle functions");
static int
idle_sysctl(SYSCTL_HANDLER_ARGS)
{
@ -1452,8 +1465,8 @@ idle_sysctl(SYSCTL_HANDLER_ARGS)
if (strstr(idle_tbl[i].id_name, "mwait") &&
(cpu_feature2 & CPUID2_MON) == 0)
continue;
if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 &&
cpu_ident_amdc1e == 0)
if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
cpu_idle_hook == NULL)
continue;
if (strcmp(idle_tbl[i].id_name, buf))
continue;
@ -1463,9 +1476,6 @@ idle_sysctl(SYSCTL_HANDLER_ARGS)
return (EINVAL);
}
SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
0, 0, idle_sysctl_available, "A", "list of available idle functions");
SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
idle_sysctl, "A", "currently selected idle function");
@ -2695,8 +2705,7 @@ init386(first)
thread0.td_pcb->pcb_fsd = PCPU_GET(fsgs_gdt)[0];
thread0.td_pcb->pcb_gsd = PCPU_GET(fsgs_gdt)[1];
if (cpu_probe_amdc1e())
cpu_idle_fn = cpu_idle_amdc1e;
cpu_probe_amdc1e();
}
#else
@ -2970,8 +2979,7 @@ init386(first)
thread0.td_pcb->pcb_ext = 0;
thread0.td_frame = &proc0_tf;
if (cpu_probe_amdc1e())
cpu_idle_fn = cpu_idle_amdc1e;
cpu_probe_amdc1e();
}
#endif

24
sys/i386/i386/mp_machdep.c
View File

@ -167,7 +167,6 @@ u_long *ipi_invlcache_counts[MAXCPU];
u_long *ipi_rendezvous_counts[MAXCPU];
u_long *ipi_lazypmap_counts[MAXCPU];
static u_long *ipi_hardclock_counts[MAXCPU];
static u_long *ipi_statclock_counts[MAXCPU];
#endif
/*
@ -1284,16 +1283,22 @@ smp_masked_invlpg_range(cpumask_t mask, vm_offset_t addr1, vm_offset_t addr2)
void
ipi_bitmap_handler(struct trapframe frame)
{
struct trapframe *oldframe;
struct thread *td;
int cpu = PCPU_GET(cpuid);
u_int ipi_bitmap;
critical_enter();
td = curthread;
td->td_intr_nesting_level++;
oldframe = td->td_intr_frame;
td->td_intr_frame = &frame;
ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
if (ipi_bitmap & (1 << IPI_PREEMPT)) {
#ifdef COUNT_IPIS
(*ipi_preempt_counts[cpu])++;
#endif
sched_preempt(curthread);
sched_preempt(td);
}
if (ipi_bitmap & (1 << IPI_AST)) {
#ifdef COUNT_IPIS
@ -1305,14 +1310,11 @@ ipi_bitmap_handler(struct trapframe frame)
#ifdef COUNT_IPIS
(*ipi_hardclock_counts[cpu])++;
#endif
hardclockintr(&frame);
}
if (ipi_bitmap & (1 << IPI_STATCLOCK)) {
#ifdef COUNT_IPIS
(*ipi_statclock_counts[cpu])++;
#endif
statclockintr(&frame);
hardclockintr();
}
td->td_intr_frame = oldframe;
td->td_intr_nesting_level--;
critical_exit();
}
/*
@ -1627,8 +1629,6 @@ mp_ipi_intrcnt(void *dummy)
intrcnt_add(buf, &ipi_lazypmap_counts[i]);
snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
intrcnt_add(buf, &ipi_hardclock_counts[i]);
snprintf(buf, sizeof(buf), "cpu%d:statclock", i);
intrcnt_add(buf, &ipi_statclock_counts[i]);
}
}
SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);

6
sys/i386/include/apicvar.h
View File

@ -124,8 +124,7 @@
#define IPI_AST 0 /* Generate software trap. */
#define IPI_PREEMPT 1
#define IPI_HARDCLOCK 2
#define IPI_STATCLOCK 3
#define IPI_BITMAP_LAST IPI_STATCLOCK
#define IPI_BITMAP_LAST IPI_HARDCLOCK
#define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
#define IPI_STOP (APIC_IPI_INTS + 7) /* Stop CPU until restarted. */
@ -152,8 +151,7 @@
#define IPI_AST 0 /* Generate software trap. */
#define IPI_PREEMPT 1
#define IPI_HARDCLOCK 2
#define IPI_STATCLOCK 3
#define IPI_BITMAP_LAST IPI_STATCLOCK
#define IPI_BITMAP_LAST IPI_HARDCLOCK
#define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
#define IPI_STOP (APIC_IPI_INTS + 7) /* Stop CPU until restarted. */

140
sys/kern/kern_clock.c
View File

@ -373,11 +373,9 @@ int profprocs;
int ticks;
int psratio;
int timer1hz;
int timer2hz;
static DPCPU_DEFINE(u_int, hard_cnt);
static DPCPU_DEFINE(u_int, stat_cnt);
static DPCPU_DEFINE(u_int, prof_cnt);
static DPCPU_DEFINE(int, pcputicks); /* Per-CPU version of ticks. */
static struct mtx global_hardclock_mtx;
MTX_SYSINIT(global_hardclock_mtx, &global_hardclock_mtx, "ghc_mtx", MTX_SPIN);
/*
* Initialize clock frequencies and start both clocks running.
@ -408,52 +406,6 @@ initclocks(dummy)
#endif
}
void
timer1clock(int usermode, uintfptr_t pc)
{
u_int *cnt;
cnt = DPCPU_PTR(hard_cnt);
*cnt += hz;
if (*cnt >= timer1hz) {
*cnt -= timer1hz;
if (*cnt >= timer1hz)
*cnt = 0;
if (PCPU_GET(cpuid) == 0)
hardclock(usermode, pc);
else
hardclock_cpu(usermode);
}
if (timer2hz == 0)
timer2clock(usermode, pc);
}
void
timer2clock(int usermode, uintfptr_t pc)
{
u_int *cnt;
int t2hz = timer2hz ? timer2hz : timer1hz;
cnt = DPCPU_PTR(stat_cnt);
*cnt += stathz;
if (*cnt >= t2hz) {
*cnt -= t2hz;
if (*cnt >= t2hz)
*cnt = 0;
statclock(usermode);
}
if (profprocs == 0)
return;
cnt = DPCPU_PTR(prof_cnt);
*cnt += profhz;
if (*cnt >= t2hz) {
*cnt -= t2hz;
if (*cnt >= t2hz)
*cnt = 0;
profclock(usermode, pc);
}
}
/*
* Each time the real-time timer fires, this function is called on all CPUs.
* Note that hardclock() calls hardclock_cpu() for the boot CPU, so only
@ -486,7 +438,7 @@ hardclock_cpu(int usermode)
PROC_SUNLOCK(p);
}
thread_lock(td);
sched_tick();
sched_tick(1);
td->td_flags |= flags;
thread_unlock(td);
@ -507,6 +459,7 @@ hardclock(int usermode, uintfptr_t pc)
atomic_add_int((volatile int *)&ticks, 1);
hardclock_cpu(usermode);
tc_ticktock();
cpu_tick_calibration();
/*
* If no separate statistics clock is available, run it from here.
*
@ -525,6 +478,89 @@ hardclock(int usermode, uintfptr_t pc)
#endif /* SW_WATCHDOG */
}
void
hardclock_anycpu(int cnt, int usermode)
{
struct pstats *pstats;
struct thread *td = curthread;
struct proc *p = td->td_proc;
int *t = DPCPU_PTR(pcputicks);
int flags;
int global, newticks;
/*
* Update per-CPU and possibly global ticks values.
*/
*t += cnt;
do {
global = ticks;
newticks = *t - global;
if (newticks <= 0) {
if (newticks < -1)
*t = global - 1;
newticks = 0;
break;
}
} while (!atomic_cmpset_int(&ticks, global, *t));
/*
* Run current process's virtual and profile time, as needed.
*/
pstats = p->p_stats;
flags = 0;
if (usermode &&
timevalisset(&pstats->p_timer[ITIMER_VIRTUAL].it_value)) {
PROC_SLOCK(p);
if (itimerdecr(&pstats->p_timer[ITIMER_VIRTUAL],
tick * cnt) == 0)
flags |= TDF_ALRMPEND | TDF_ASTPENDING;
PROC_SUNLOCK(p);
}
if (timevalisset(&pstats->p_timer[ITIMER_PROF].it_value)) {
PROC_SLOCK(p);
if (itimerdecr(&pstats->p_timer[ITIMER_PROF],
tick * cnt) == 0)
flags |= TDF_PROFPEND | TDF_ASTPENDING;
PROC_SUNLOCK(p);
}
thread_lock(td);
sched_tick(cnt);
td->td_flags |= flags;
thread_unlock(td);
#ifdef HWPMC_HOOKS
if (PMC_CPU_HAS_SAMPLES(PCPU_GET(cpuid)))
PMC_CALL_HOOK_UNLOCKED(curthread, PMC_FN_DO_SAMPLES, NULL);
#endif
callout_tick();
/* We are in charge to handle this tick duty. */
if (newticks > 0) {
mtx_lock_spin(&global_hardclock_mtx);
tc_ticktock();
#ifdef DEVICE_POLLING
hardclock_device_poll(); /* This is very short and quick. */
#endif /* DEVICE_POLLING */
#ifdef SW_WATCHDOG
if (watchdog_enabled > 0) {
watchdog_ticks -= newticks;
if (watchdog_ticks <= 0)
watchdog_fire();
}
#endif /* SW_WATCHDOG */
mtx_unlock_spin(&global_hardclock_mtx);
}
if (curcpu == CPU_FIRST())
cpu_tick_calibration();
}
void
hardclock_sync(int cpu)
{
int *t = DPCPU_ID_PTR(cpu, pcputicks);
*t = ticks;
}
/*
* Compute number of ticks in the specified amount of time.
*/

895
sys/kern/kern_clocksource.c
View File

File diff suppressed because it is too large Load Diff

2
sys/kern/kern_et.c
View File

@ -38,7 +38,7 @@ SLIST_HEAD(et_eventtimers_list, eventtimer);
static struct et_eventtimers_list eventtimers = SLIST_HEAD_INITIALIZER(et_eventtimers);
struct mtx et_eventtimers_mtx;
MTX_SYSINIT(et_eventtimers_init, &et_eventtimers_mtx, "et_mtx", MTX_SPIN);
MTX_SYSINIT(et_eventtimers_init, &et_eventtimers_mtx, "et_mtx", MTX_DEF);
SYSCTL_NODE(_kern, OID_AUTO, eventtimer, CTLFLAG_RW, 0, "Event timers");
SYSCTL_NODE(_kern_eventtimer, OID_AUTO, et, CTLFLAG_RW, 0, "");

18
sys/kern/kern_tc.c
View File

@ -770,16 +770,11 @@ void
tc_ticktock(void)
{
static int count;
static time_t last_calib;
if (++count < tc_tick)
return;
count = 0;
tc_windup();
if (time_uptime != last_calib && !(time_uptime & 0xf)) {
cpu_tick_calibrate(0);
last_calib = time_uptime;
}
}
static void
@ -830,9 +825,20 @@ tc_cpu_ticks(void)
return (u + base);
}
void
cpu_tick_calibration(void)
{
static time_t last_calib;
if (time_uptime != last_calib && !(time_uptime & 0xf)) {
cpu_tick_calibrate(0);
last_calib = time_uptime;
}
}
/*
* This function gets called every 16 seconds on only one designated
* CPU in the system from hardclock() via tc_ticktock().
* CPU in the system from hardclock() via cpu_tick_calibration()().
*
* Whenever the real time clock is stepped we get called with reset=1
* to make sure we handle suspend/resume and similar events correctly.

39
sys/kern/kern_timeout.c
View File

@ -111,6 +111,7 @@ struct callout_cpu {
int cc_softticks;
int cc_cancel;
int cc_waiting;
int cc_firsttick;
};
#ifdef SMP
@ -126,6 +127,7 @@ struct callout_cpu cc_cpu;
#define CC_UNLOCK(cc) mtx_unlock_spin(&(cc)->cc_lock)
static int timeout_cpu;
void (*callout_new_inserted)(int cpu, int ticks) = NULL;
MALLOC_DEFINE(M_CALLOUT, "callout", "Callout datastructures");
@ -260,7 +262,7 @@ callout_tick(void)
need_softclock = 0;
cc = CC_SELF();
mtx_lock_spin_flags(&cc->cc_lock, MTX_QUIET);
cc->cc_ticks++;
cc->cc_firsttick = cc->cc_ticks = ticks;
for (; (cc->cc_softticks - cc->cc_ticks) <= 0; cc->cc_softticks++) {
bucket = cc->cc_softticks & callwheelmask;
if (!TAILQ_EMPTY(&cc->cc_callwheel[bucket])) {
@ -277,6 +279,34 @@ callout_tick(void)
swi_sched(cc->cc_cookie, 0);
}
int
callout_tickstofirst(void)
{
struct callout_cpu *cc;
struct callout *c;
struct callout_tailq *sc;
int curticks;
int skip = 1;
cc = CC_SELF();
mtx_lock_spin_flags(&cc->cc_lock, MTX_QUIET);
curticks = cc->cc_ticks;
while( skip < ncallout && skip < hz/8 ) {
sc = &cc->cc_callwheel[ (curticks+skip) & callwheelmask ];
/* search scanning ticks */
TAILQ_FOREACH( c, sc, c_links.tqe ){
if (c && (c->c_time <= curticks + ncallout)
&& (c->c_time > 0))
goto out;
}
skip++;
}
out:
cc->cc_firsttick = curticks + skip;
mtx_unlock_spin_flags(&cc->cc_lock, MTX_QUIET);
return (skip);
}
static struct callout_cpu *
callout_lock(struct callout *c)
{
@ -639,9 +669,14 @@ retry:
c->c_arg = arg;
c->c_flags |= (CALLOUT_ACTIVE | CALLOUT_PENDING);
c->c_func = ftn;
c->c_time = cc->cc_ticks + to_ticks;
c->c_time = ticks + to_ticks;
TAILQ_INSERT_TAIL(&cc->cc_callwheel[c->c_time & callwheelmask],
c, c_links.tqe);
if ((c->c_time - cc->cc_firsttick) < 0) {
cc->cc_firsttick = c->c_time;
(*callout_new_inserted)(cpu,
to_ticks + (ticks - cc->cc_ticks));
}
CTR5(KTR_CALLOUT, "%sscheduled %p func %p arg %p in %d",
cancelled ? "re" : "", c, c->c_func, c->c_arg, to_ticks);
CC_UNLOCK(cc);

2
sys/kern/sched_4bsd.c
View File

@ -1547,7 +1547,7 @@ sched_pctcpu(struct thread *td)
}
void
sched_tick(void)
sched_tick(int cnt)
{
}

8
sys/kern/sched_ule.c
View File

@ -196,7 +196,7 @@ static int preempt_thresh = 0;
#endif
static int static_boost = PRI_MIN_TIMESHARE;
static int sched_idlespins = 10000;
static int sched_idlespinthresh = 64;
static int sched_idlespinthresh = 16;
/*
* tdq - per processor runqs and statistics. All fields are protected by the
@ -2163,7 +2163,7 @@ sched_clock(struct thread *td)
* is easier than trying to scale based on stathz.
*/
void
sched_tick(void)
sched_tick(int cnt)
{
struct td_sched *ts;
@ -2175,7 +2175,7 @@ sched_tick(void)
if (ts->ts_incrtick == ticks)
return;
/* Adjust ticks for pctcpu */
ts->ts_ticks += 1 << SCHED_TICK_SHIFT;
ts->ts_ticks += cnt << SCHED_TICK_SHIFT;
ts->ts_ltick = ticks;
ts->ts_incrtick = ticks;
/*
@ -2549,7 +2549,7 @@ sched_idletd(void *dummy)
if (tdq->tdq_load == 0) {
tdq->tdq_cpu_idle = 1;
if (tdq->tdq_load == 0) {
cpu_idle(switchcnt > sched_idlespinthresh);
cpu_idle(switchcnt > sched_idlespinthresh * 4);
tdq->tdq_switchcnt++;
}
tdq->tdq_cpu_idle = 0;

1
sys/mips/include/smp.h
View File

@ -28,7 +28,6 @@
#define IPI_STOP_HARD 0x0008
#define IPI_PREEMPT 0x0010
#define IPI_HARDCLOCK 0x0020
#define IPI_STATCLOCK 0x0040
#ifndef LOCORE

6
sys/mips/mips/mp_machdep.c
View File

@ -164,11 +164,7 @@ mips_ipi_handler(void *arg)
break;
case IPI_HARDCLOCK:
CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
hardclockintr(arg);;
break;
case IPI_STATCLOCK:
CTR1(KTR_SMP, "%s: IPI_STATCLOCK", __func__);
statclockintr(arg);;
hardclockintr();;
break;
default:
panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu);

139
sys/pc98/pc98/machdep.c
View File

@ -1120,40 +1120,36 @@ cpu_halt(void)
__asm__ ("hlt");
}
static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
TUNABLE_INT("machdep.idle_mwait", &idle_mwait);
SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait,
0, "Use MONITOR/MWAIT for short idle");
#define STATE_RUNNING 0x0
#define STATE_MWAIT 0x1
#define STATE_SLEEPING 0x2
static void
cpu_idle_hlt(int busy)
{
int *state;
state = (int *)PCPU_PTR(monitorbuf);
*state = STATE_SLEEPING;
/*
* we must absolutely guarentee that hlt is the next instruction
* We must absolutely guarentee that hlt is the next instruction
* after sti or we introduce a timing window.
*/
disable_intr();
if (sched_runnable())
if (sched_runnable())
enable_intr();
else
__asm __volatile("sti; hlt");
}
static void
cpu_idle_spin(int busy)
{
return;
}
void (*cpu_idle_fn)(int) = cpu_idle_hlt;
void
cpu_idle(int busy)
{
#if defined(SMP)
if (mp_grab_cpu_hlt())
return;
#endif
cpu_idle_fn(busy);
*state = STATE_RUNNING;
}
/*
* mwait cpu power states. Lower 4 bits are sub-states.
* MWAIT cpu power states. Lower 4 bits are sub-states.
*/
#define MWAIT_C0 0xf0
#define MWAIT_C1 0x00
@ -1161,63 +1157,91 @@ cpu_idle(int busy)
#define MWAIT_C3 0x20
#define MWAIT_C4 0x30
#define MWAIT_DISABLED 0x0
#define MWAIT_WOKEN 0x1
#define MWAIT_WAITING 0x2
static void
cpu_idle_mwait(int busy)
{
int *mwait;
int *state;
mwait = (int *)PCPU_PTR(monitorbuf);
*mwait = MWAIT_WAITING;
if (sched_runnable())
return;
cpu_monitor(mwait, 0, 0);
if (*mwait == MWAIT_WAITING)
cpu_mwait(0, MWAIT_C1);
state = (int *)PCPU_PTR(monitorbuf);
*state = STATE_MWAIT;
if (!sched_runnable()) {
cpu_monitor(state, 0, 0);
if (*state == STATE_MWAIT)
cpu_mwait(0, MWAIT_C1);
}
*state = STATE_RUNNING;
}
static void
cpu_idle_mwait_hlt(int busy)
cpu_idle_spin(int busy)
{
int *mwait;
int *state;
int i;
mwait = (int *)PCPU_PTR(monitorbuf);
if (busy == 0) {
*mwait = MWAIT_DISABLED;
cpu_idle_hlt(busy);
return;
state = (int *)PCPU_PTR(monitorbuf);
*state = STATE_RUNNING;
for (i = 0; i < 1000; i++) {
if (sched_runnable())
return;
cpu_spinwait();
}
*mwait = MWAIT_WAITING;
if (sched_runnable())
}
void (*cpu_idle_fn)(int) = cpu_idle_hlt;
void
cpu_idle(int busy)
{
CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
busy, curcpu);
#ifdef SMP
if (mp_grab_cpu_hlt())
return;
cpu_monitor(mwait, 0, 0);
if (*mwait == MWAIT_WAITING)
cpu_mwait(0, MWAIT_C1);
#endif
/* If we are busy - try to use fast methods. */
if (busy) {
if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
cpu_idle_mwait(busy);
goto out;
}
}
/* If we have time - switch timers into idle mode. */
if (!busy) {
critical_enter();
cpu_idleclock();
}
/* Call main idle method. */
cpu_idle_fn(busy);
/* Switch timers mack into active mode. */
if (!busy) {
cpu_activeclock();
critical_exit();
}
out:
CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
busy, curcpu);
}
int
cpu_idle_wakeup(int cpu)
{
struct pcpu *pcpu;
int *mwait;
int *state;
if (cpu_idle_fn == cpu_idle_spin)
return (1);
if (cpu_idle_fn != cpu_idle_mwait && cpu_idle_fn != cpu_idle_mwait_hlt)
return (0);
pcpu = pcpu_find(cpu);
mwait = (int *)pcpu->pc_monitorbuf;
state = (int *)pcpu->pc_monitorbuf;
/*
* This doesn't need to be atomic since missing the race will
* simply result in unnecessary IPIs.
*/
if (cpu_idle_fn == cpu_idle_mwait_hlt && *mwait == MWAIT_DISABLED)
if (*state == STATE_SLEEPING)
return (0);
*mwait = MWAIT_WOKEN;
if (*state == STATE_MWAIT)
*state = STATE_RUNNING;
return (1);
}
@ -1230,7 +1254,6 @@ struct {
} idle_tbl[] = {
{ cpu_idle_spin, "spin" },
{ cpu_idle_mwait, "mwait" },
{ cpu_idle_mwait_hlt, "mwait_hlt" },
{ cpu_idle_hlt, "hlt" },
{ NULL, NULL }
};
@ -1255,6 +1278,9 @@ idle_sysctl_available(SYSCTL_HANDLER_ARGS)
return (error);
}
SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
0, 0, idle_sysctl_available, "A", "list of available idle functions");
static int
idle_sysctl(SYSCTL_HANDLER_ARGS)
{
@ -1286,9 +1312,6 @@ idle_sysctl(SYSCTL_HANDLER_ARGS)
return (EINVAL);
}
SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
0, 0, idle_sysctl_available, "A", "list of available idle functions");
SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
idle_sysctl, "A", "currently selected idle function");

12
sys/powerpc/aim/machdep.c
View File

@ -638,7 +638,13 @@ cpu_idle(int busy)
panic("ints disabled in idleproc!");
}
#endif
CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
busy, curcpu);
if (powerpc_pow_enabled) {
if (!busy) {
critical_enter();
cpu_idleclock();
}
switch (vers) {
case IBM970:
case IBM970FX:
@ -658,7 +664,13 @@ cpu_idle(int busy)
isync();
break;
}
if (!busy) {
cpu_activeclock();
critical_exit();
}
}
CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
busy, curcpu);
}
int

12
sys/powerpc/booke/machdep.c
View File

@ -488,9 +488,21 @@ cpu_idle (int busy)
}
#endif
CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
busy, curcpu);
if (!busy) {
critical_enter();
cpu_idleclock();
}
/* Freescale E500 core RM section 6.4.1. */
msr = msr | PSL_WE;
__asm __volatile("msync; mtmsr %0; isync" :: "r" (msr));
if (!busy) {
cpu_activeclock();
critical_exit();
}
CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
busy, curcpu);
}
int

1
sys/powerpc/include/smp.h
View File

@ -37,7 +37,6 @@
#define IPI_STOP 3
#define IPI_STOP_HARD 3
#define IPI_HARDCLOCK 4
#define IPI_STATCLOCK 5
#ifndef LOCORE

2
sys/powerpc/powerpc/mp_machdep.c
View File

@ -315,7 +315,7 @@ powerpc_ipi_handler(void *arg)
break;
case IPI_HARDCLOCK:
CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
hardclockintr(curthread->td_intr_frame);
hardclockintr();
break;
}
}

1
sys/sparc64/include/intr_machdep.h
View File

@ -47,7 +47,6 @@
#define PIL_STOP 5 /* stop cpu ipi */
#define PIL_PREEMPT 6 /* preempt idle thread cpu ipi */
#define PIL_HARDCLOCK 7 /* hardclock broadcast */
#define PIL_STATCLOCK 8 /* statclock broadcast */
#define PIL_FILTER 12 /* filter interrupts */
#define PIL_FAST 13 /* fast interrupts */
#define PIL_TICK 14 /* tick interrupts */

1
sys/sparc64/include/smp.h
View File

@ -59,7 +59,6 @@
#define IPI_RENDEZVOUS PIL_RENDEZVOUS
#define IPI_PREEMPT PIL_PREEMPT
#define IPI_HARDCLOCK PIL_HARDCLOCK
#define IPI_STATCLOCK PIL_STATCLOCK
#define IPI_STOP PIL_STOP
#define IPI_STOP_HARD PIL_STOP

3
sys/sparc64/sparc64/intr_machdep.c
View File

@ -97,8 +97,7 @@ static const char *const pil_names[] = {
"stop", /* PIL_STOP */
"preempt", /* PIL_PREEMPT */
"hardclock", /* PIL_HARDCLOCK */
"statclock", /* PIL_STATCLOCK */
"stray", "stray", "stray",
"stray", "stray", "stray", "stray",
"filter", /* PIL_FILTER */
"fast", /* PIL_FAST */
"tick", /* PIL_TICK */

21
sys/sparc64/sparc64/mp_machdep.c
View File

@ -98,7 +98,6 @@ __FBSDID("$FreeBSD$");
static ih_func_t cpu_ipi_ast;
static ih_func_t cpu_ipi_hardclock;
static ih_func_t cpu_ipi_preempt;
static ih_func_t cpu_ipi_statclock;
static ih_func_t cpu_ipi_stop;
/*
@ -292,7 +291,6 @@ cpu_mp_start(void)
intr_setup(PIL_STOP, cpu_ipi_stop, -1, NULL, NULL);
intr_setup(PIL_PREEMPT, cpu_ipi_preempt, -1, NULL, NULL);
intr_setup(PIL_HARDCLOCK, cpu_ipi_hardclock, -1, NULL, NULL);
intr_setup(PIL_STATCLOCK, cpu_ipi_statclock, -1, NULL, NULL);
cpuid_to_mid[curcpu] = PCPU_GET(mid);
@ -524,15 +522,18 @@ cpu_ipi_preempt(struct trapframe *tf)
static void
cpu_ipi_hardclock(struct trapframe *tf)
{
struct trapframe *oldframe;
struct thread *td;
hardclockintr(tf);
}
static void
cpu_ipi_statclock(struct trapframe *tf)
{
statclockintr(tf);
critical_enter();
td = curthread;
td->td_intr_nesting_level++;
oldframe = td->td_intr_frame;
td->td_intr_frame = tf;
hardclockintr();
td->td_intr_frame = oldframe;
td->td_intr_nesting_level--;
critical_exit();
}
static void

1
sys/sun4v/include/intr_machdep.h
View File

@ -47,7 +47,6 @@
#define PIL_STOP 5 /* stop cpu ipi */
#define PIL_PREEMPT 6 /* preempt idle thread cpu ipi */
#define PIL_HARDCLOCK 7 /* hardclock broadcast */
#define PIL_STATCLOCK 8 /* statclock broadcast */
#define PIL_FAST 13 /* fast interrupts */
#define PIL_TICK 14

2
sys/sun4v/include/smp.h
View File

@ -47,7 +47,6 @@
#define IPI_STOP_HARD PIL_STOP
#define IPI_PREEMPT PIL_PREEMPT
#define IPI_HARDCLOCK PIL_HARDCLOCK
#define IPI_STATCLOCK PIL_STATCLOCK
#define IPI_RETRIES 5000
@ -83,7 +82,6 @@ void cpu_ipi_ast(struct trapframe *tf);
void cpu_ipi_stop(struct trapframe *tf);
void cpu_ipi_preempt(struct trapframe *tf);
void cpu_ipi_hardclock(struct trapframe *tf);
void cpu_ipi_statclock(struct trapframe *tf);
void ipi_all_but_self(u_int ipi);
void ipi_cpu(int cpu, u_int ipi);

4
sys/sun4v/sun4v/intr_machdep.c
View File

@ -110,8 +110,7 @@ static char *pil_names[] = {
"stop", /* PIL_STOP */
"preempt", /* PIL_PREEMPT */
"hardclock", /* PIL_HARDCLOCK */
"statclock", /* PIL_STATCLOCK */
"stray", "stray", "stray", "stray",
"stray", "stray", "stray", "stray", "stray",
"fast", /* PIL_FAST */
"tick", /* PIL_TICK */
};
@ -265,7 +264,6 @@ intr_init(void)
intr_handlers[PIL_STOP]= cpu_ipi_stop;
intr_handlers[PIL_PREEMPT]= cpu_ipi_preempt;
intr_handlers[PIL_HARDCLOCK]= cpu_ipi_hardclock;
intr_handlers[PIL_STATCLOCK]= cpu_ipi_statclock;
#endif
mtx_init(&intr_table_lock, "intr table", NULL, MTX_SPIN);
cpu_intrq_alloc();

19
sys/sun4v/sun4v/mp_machdep.c
View File

@ -472,15 +472,18 @@ cpu_ipi_preempt(struct trapframe *tf)
void
cpu_ipi_hardclock(struct trapframe *tf)
{
struct trapframe *oldframe;
struct thread *td;
hardclockintr(tf);
}
void
cpu_ipi_statclock(struct trapframe *tf)
{
statclockintr(tf);
critical_enter();
td = curthread;
td->td_intr_nesting_level++;
oldframe = td->td_intr_frame;
td->td_intr_frame = tf;
hardclockintr();
td->td_intr_frame = oldframe;
td->td_intr_nesting_level--;
critical_exit();
}
void

3
sys/sys/callout.h
View File

@ -96,7 +96,8 @@ int callout_schedule_on(struct callout *, int, int);
#define callout_stop(c) _callout_stop_safe(c, 0)
int _callout_stop_safe(struct callout *, int);
void callout_tick(void);
int callout_tickstofirst(void);
extern void (*callout_new_inserted)(int cpu, int ticks);
#endif

2
sys/sys/sched.h
View File

@ -111,7 +111,7 @@ void sched_preempt(struct thread *td);
void sched_add(struct thread *td, int flags);
void sched_clock(struct thread *td);
void sched_rem(struct thread *td);
void sched_tick(void);
void sched_tick(int cnt);
void sched_relinquish(struct thread *td);
struct thread *sched_choose(void);
void sched_idletd(void *);

10
sys/sys/systm.h
View File

@ -237,20 +237,22 @@ void realitexpire(void *);
int sysbeep(int hertz, int period);
void hardclock(int usermode, uintfptr_t pc);
void hardclock_anycpu(int cnt, int usermode);
void hardclock_cpu(int usermode);
void hardclock_sync(int cpu);
void softclock(void *);
void statclock(int usermode);
void profclock(int usermode, uintfptr_t pc);
void timer1clock(int usermode, uintfptr_t pc);
void timer2clock(int usermode, uintfptr_t pc);
int hardclockintr(struct trapframe *frame);
int statclockintr(struct trapframe *frame);
int hardclockintr(void);
void startprofclock(struct proc *);
void stopprofclock(struct proc *);
void cpu_startprofclock(void);
void cpu_stopprofclock(void);
void cpu_idleclock(void);
void cpu_activeclock(void);
extern int cpu_disable_deep_sleep;
int cr_cansee(struct ucred *u1, struct ucred *u2);
int cr_canseesocket(struct ucred *cred, struct socket *so);

4
sys/sys/timeet.h
View File

@ -83,8 +83,8 @@ struct eventtimer {
};
extern struct mtx et_eventtimers_mtx;
#define ET_LOCK() mtx_lock_spin(&et_eventtimers_mtx)
#define ET_UNLOCK() mtx_unlock_spin(&et_eventtimers_mtx)
#define ET_LOCK() mtx_lock(&et_eventtimers_mtx)
#define ET_UNLOCK() mtx_unlock(&et_eventtimers_mtx)
/* Driver API */
int et_register(struct eventtimer *et);

1
sys/sys/timetc.h
View File

@ -70,6 +70,7 @@ u_int64_t tc_getfrequency(void);
void tc_init(struct timecounter *tc);
void tc_setclock(struct timespec *ts);
void tc_ticktock(void);
void cpu_tick_calibration(void);
#ifdef SYSCTL_DECL
SYSCTL_DECL(_kern_timecounter);

2
sys/x86/x86/local_apic.c
View File

@ -261,7 +261,7 @@ lapic_init(vm_paddr_t addr)
lapic_et.et_quality = 600;
if (!arat) {
lapic_et.et_flags |= ET_FLAGS_C3STOP;
lapic_et.et_quality -= 100;
lapic_et.et_quality -= 200;
}
lapic_et.et_frequency = 0;
/* We don't know frequency yet, so trying to guess. */