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Import files needed to build mips binaries with binutils 2.9.1.

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imp 1999-02-28 23:08:24 +00:00
parent effee09f85
commit eb98fb7651
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2716
contrib/binutils/bfd/coff-mips.c Normal file
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contrib/binutils/bfd/cpu-mips.c Normal file
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/* bfd back-end for mips support
Copyright (C) 1990, 91-97, 1998 Free Software Foundation, Inc.
Written by Steve Chamberlain of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \
{ \
BITS_WORD, /* bits in a word */ \
BITS_ADDR, /* bits in an address */ \
8, /* 8 bits in a byte */ \
bfd_arch_mips, \
NUMBER, \
"mips", \
PRINT, \
3, \
DEFAULT, \
bfd_default_compatible, \
bfd_default_scan, \
NEXT, \
}
enum {
I_mips3000,
I_mips3900,
I_mips4000,
I_mips4010,
I_mips4100,
I_mips4300,
I_mips4400,
I_mips4600,
I_mips4650,
I_mips5000,
I_mips6000,
I_mips8000,
I_mips10000,
I_mips16
};
#define NN(index) (&arch_info_struct[(index)+1])
static const bfd_arch_info_type arch_info_struct[] =
{
N (32, 32, bfd_mach_mips3000, "mips:3000", false, NN(I_mips3000)),
N (32, 32, bfd_mach_mips3900, "mips:3900", false, NN(I_mips3900)),
N (64, 64, bfd_mach_mips4000, "mips:4000", false, NN(I_mips4000)),
N (64, 64, bfd_mach_mips4010, "mips:4010", false, NN(I_mips4010)),
N (64, 64, bfd_mach_mips4100, "mips:4100", false, NN(I_mips4100)),
N (64, 64, bfd_mach_mips4300, "mips:4300", false, NN(I_mips4300)),
N (64, 64, bfd_mach_mips4400, "mips:4400", false, NN(I_mips4400)),
N (64, 64, bfd_mach_mips4600, "mips:4600", false, NN(I_mips4600)),
N (64, 64, bfd_mach_mips4650, "mips:4650", false, NN(I_mips4650)),
N (64, 64, bfd_mach_mips5000, "mips:5000", false, NN(I_mips5000)),
N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
N (64, 64, bfd_mach_mips10000, "mips:10000", false, NN(I_mips10000)),
N (64, 64, bfd_mach_mips16, "mips:16", false, 0),
};
/* The default architecture is mips:3000, but with a machine number of
zero. This lets the linker distinguish between a default setting
of mips, and an explicit setting of mips:3000. */
const bfd_arch_info_type bfd_mips_arch =
N (32, 32, 0, "mips", true, &arch_info_struct[0]);

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contrib/binutils/bfd/elf32-mips.c Normal file
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/* Hopefully this should include either machine/param.h (Ultrix) or
machine/machparam.h (Mach), whichever is its name on this system. */
#include <sys/param.h>
#include <machine/vmparam.h>
#define HOST_PAGE_SIZE NBPG
/* #define HOST_SEGMENT_SIZE NBPG -- we use HOST_DATA_START_ADDR */
#define HOST_MACHINE_ARCH bfd_arch_mips
/* #define HOST_MACHINE_MACHINE */
#define HOST_TEXT_START_ADDR USRTEXT
#define HOST_DATA_START_ADDR USRDATA
#define HOST_STACK_END_ADDR USRSTACK
#define TRAD_UNIX_CORE_FILE_FAILING_SIGNAL(core_bfd) \
((core_bfd)->tdata.trad_core_data->u.u_arg[0])

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/* BFD backend for MIPS BSD (a.out) binaries.
Copyright (C) 1993, 94, 95, 97, 1998 Free Software Foundation, Inc.
Written by Ralph Campbell.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define BYTES_IN_WORD 4
/* #define ENTRY_CAN_BE_ZERO */
#define N_HEADER_IN_TEXT(x) 1
#define N_SHARED_LIB(x) 0
#define N_TXTADDR(x) \
(N_MAGIC(x) != ZMAGIC ? (x).a_entry : /* object file or NMAGIC */\
TEXT_START_ADDR + EXEC_BYTES_SIZE /* no padding */\
)
#define N_DATADDR(x) (N_TXTADDR(x)+N_TXTSIZE(x))
#define TEXT_START_ADDR 4096
#define TARGET_PAGE_SIZE 4096
#define SEGMENT_SIZE TARGET_PAGE_SIZE
#define DEFAULT_ARCH bfd_arch_mips
#define MACHTYPE_OK(mtype) ((mtype) == M_UNKNOWN \
|| (mtype) == M_MIPS1 || (mtype) == M_MIPS2)
#define MY_symbol_leading_char '\0'
#define MY(OP) CAT(mipsbsd_,OP)
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
#include "libaout.h"
#define SET_ARCH_MACH(ABFD, EXEC) \
MY(set_arch_mach)(ABFD, N_MACHTYPE (EXEC)); \
MY(choose_reloc_size)(ABFD);
void MY(set_arch_mach) PARAMS ((bfd *abfd, int machtype));
static void MY(choose_reloc_size) PARAMS ((bfd *abfd));
#define MY_write_object_contents MY(write_object_contents)
static boolean MY(write_object_contents) PARAMS ((bfd *abfd));
/* We can't use MY(x) here because it leads to a recursive call to CAT
when expanded inside JUMP_TABLE. */
#define MY_bfd_reloc_type_lookup mipsbsd_reloc_howto_type_lookup
#define MY_canonicalize_reloc mipsbsd_canonicalize_reloc
#define MY_bfd_link_hash_table_create _bfd_generic_link_hash_table_create
#define MY_bfd_link_add_symbols _bfd_generic_link_add_symbols
#define MY_final_link_callback unused
#define MY_bfd_final_link _bfd_generic_final_link
#define MY_backend_data &MY(backend_data)
#define MY_BFD_TARGET
#include "aout-target.h"
void
MY(set_arch_mach) (abfd, machtype)
bfd *abfd;
int machtype;
{
enum bfd_architecture arch;
long machine;
/* Determine the architecture and machine type of the object file. */
switch (machtype) {
case M_MIPS1:
arch = bfd_arch_mips;
machine = 3000;
break;
case M_MIPS2:
arch = bfd_arch_mips;
machine = 4000;
break;
default:
arch = bfd_arch_obscure;
machine = 0;
break;
}
bfd_set_arch_mach(abfd, arch, machine);
}
/* Determine the size of a relocation entry, based on the architecture */
static void
MY(choose_reloc_size) (abfd)
bfd *abfd;
{
switch (bfd_get_arch(abfd)) {
case bfd_arch_sparc:
case bfd_arch_a29k:
case bfd_arch_mips:
obj_reloc_entry_size (abfd) = RELOC_EXT_SIZE;
break;
default:
obj_reloc_entry_size (abfd) = RELOC_STD_SIZE;
break;
}
}
/* Write an object file in BSD a.out format.
Section contents have already been written. We write the
file header, symbols, and relocation. */
static boolean
MY(write_object_contents) (abfd)
bfd *abfd;
{
struct external_exec exec_bytes;
struct internal_exec *execp = exec_hdr (abfd);
/* Magic number, maestro, please! */
switch (bfd_get_arch(abfd)) {
case bfd_arch_m68k:
switch (bfd_get_mach(abfd)) {
case bfd_mach_m68010:
N_SET_MACHTYPE(*execp, M_68010);
break;
default:
case bfd_mach_m68020:
N_SET_MACHTYPE(*execp, M_68020);
break;
}
break;
case bfd_arch_sparc:
N_SET_MACHTYPE(*execp, M_SPARC);
break;
case bfd_arch_i386:
N_SET_MACHTYPE(*execp, M_386);
break;
case bfd_arch_a29k:
N_SET_MACHTYPE(*execp, M_29K);
break;
case bfd_arch_mips:
switch (bfd_get_mach(abfd)) {
case 4000:
case 6000:
N_SET_MACHTYPE(*execp, M_MIPS2);
break;
default:
N_SET_MACHTYPE(*execp, M_MIPS1);
break;
}
break;
default:
N_SET_MACHTYPE(*execp, M_UNKNOWN);
}
MY(choose_reloc_size)(abfd);
WRITE_HEADERS(abfd, execp);
return true;
}
/*
* MIPS relocation types.
*/
#define MIPS_RELOC_32 0
#define MIPS_RELOC_JMP 1
#define MIPS_RELOC_WDISP16 2
#define MIPS_RELOC_HI16 3
#define MIPS_RELOC_HI16_S 4
#define MIPS_RELOC_LO16 5
/*
* This is only called when performing a BFD_RELOC_MIPS_JMP relocation.
* The jump destination address is formed from the upper 4 bits of the
* "current" program counter concatenated with the jump instruction's
* 26 bit field and two trailing zeros.
* If the destination address is not in the same segment as the "current"
* program counter, then we need to signal an error.
*/
static bfd_reloc_status_type
mips_fix_jmp_addr (abfd,reloc_entry,symbol,data,input_section,output_bfd)
bfd *abfd;
arelent *reloc_entry;
struct symbol_cache_entry *symbol;
PTR data;
asection *input_section;
bfd *output_bfd;
{
bfd_vma relocation, pc;
/* If this is a partial relocation, just continue. */
if (output_bfd != (bfd *)NULL)
return bfd_reloc_continue;
/* If this is an undefined symbol, return error */
if (bfd_is_und_section (symbol->section)
&& (symbol->flags & BSF_WEAK) == 0)
return bfd_reloc_undefined;
/*
* Work out which section the relocation is targetted at and the
* initial relocation command value.
*/
if (bfd_is_com_section (symbol->section))
relocation = 0;
else
relocation = symbol->value;
relocation += symbol->section->output_section->vma;
relocation += symbol->section->output_offset;
relocation += reloc_entry->addend;
pc = input_section->output_section->vma + input_section->output_offset +
reloc_entry->address + 4;
if ((relocation & 0xF0000000) != (pc & 0xF0000000))
return bfd_reloc_overflow;
return bfd_reloc_continue;
}
/*
* This is only called when performing a BFD_RELOC_HI16_S relocation.
* We need to see if bit 15 is set in the result. If it is, we add
* 0x10000 and continue normally. This will compensate for the sign extension
* when the low bits are added at run time.
*/
static bfd_reloc_status_type
mips_fix_hi16_s PARAMS ((bfd *, arelent *, asymbol *, PTR,
asection *, bfd *, char **));
static bfd_reloc_status_type
mips_fix_hi16_s (abfd, reloc_entry, symbol, data, input_section,
output_bfd, error_message)
bfd *abfd;
arelent *reloc_entry;
asymbol *symbol;
PTR data;
asection *input_section;
bfd *output_bfd;
char **error_message;
{
bfd_vma relocation;
/* If this is a partial relocation, just continue. */
if (output_bfd != (bfd *)NULL)
return bfd_reloc_continue;
/* If this is an undefined symbol, return error */
if (bfd_is_und_section (symbol->section)
&& (symbol->flags & BSF_WEAK) == 0)
return bfd_reloc_undefined;
/*
* Work out which section the relocation is targetted at and the
* initial relocation command value.
*/
if (bfd_is_com_section (symbol->section))
relocation = 0;
else
relocation = symbol->value;
relocation += symbol->section->output_section->vma;
relocation += symbol->section->output_offset;
relocation += reloc_entry->addend;
if (relocation & 0x8000)
reloc_entry->addend += 0x10000;
return bfd_reloc_continue;
}
static reloc_howto_type mips_howto_table_ext[] = {
{MIPS_RELOC_32, 0, 2, 32, false, 0, complain_overflow_bitfield, 0,
"32", false, 0, 0xffffffff, false},
{MIPS_RELOC_JMP, 2, 2, 26, false, 0, complain_overflow_dont,
mips_fix_jmp_addr,
"MIPS_JMP", false, 0, 0x03ffffff, false},
{MIPS_RELOC_WDISP16, 2, 2, 16, true, 0, complain_overflow_signed, 0,
"WDISP16", false, 0, 0x0000ffff, false},
{MIPS_RELOC_HI16, 16, 2, 16, false, 0, complain_overflow_bitfield, 0,
"HI16", false, 0, 0x0000ffff, false},
{MIPS_RELOC_HI16_S, 16, 2, 16, false, 0, complain_overflow_bitfield,
mips_fix_hi16_s,
"HI16_S", false, 0, 0x0000ffff, false},
{MIPS_RELOC_LO16, 0, 2, 16, false, 0, complain_overflow_dont, 0,
"LO16", false, 0, 0x0000ffff, false},
};
static reloc_howto_type *
MY(reloc_howto_type_lookup) (abfd, code)
bfd *abfd;
bfd_reloc_code_real_type code;
{
if (bfd_get_arch (abfd) != bfd_arch_mips)
return 0;
switch (code)
{
case BFD_RELOC_CTOR:
case BFD_RELOC_32:
return (&mips_howto_table_ext[MIPS_RELOC_32]);
case BFD_RELOC_MIPS_JMP:
return (&mips_howto_table_ext[MIPS_RELOC_JMP]);
case BFD_RELOC_16_PCREL_S2:
return (&mips_howto_table_ext[MIPS_RELOC_WDISP16]);
case BFD_RELOC_HI16:
return (&mips_howto_table_ext[MIPS_RELOC_HI16]);
case BFD_RELOC_HI16_S:
return (&mips_howto_table_ext[MIPS_RELOC_HI16_S]);
case BFD_RELOC_LO16:
return (&mips_howto_table_ext[MIPS_RELOC_LO16]);
default:
return 0;
}
}
/*
* This is just like the standard aoutx.h version but we need to do our
* own mapping of external reloc type values to howto entries.
*/
long
MY(canonicalize_reloc)(abfd, section, relptr, symbols)
bfd *abfd;
sec_ptr section;
arelent **relptr;
asymbol **symbols;
{
arelent *tblptr = section->relocation;
unsigned int count, c;
extern reloc_howto_type NAME(aout,ext_howto_table)[];
/* If we have already read in the relocation table, return the values. */
if (section->flags & SEC_CONSTRUCTOR) {
arelent_chain *chain = section->constructor_chain;
for (count = 0; count < section->reloc_count; count++) {
*relptr++ = &chain->relent;
chain = chain->next;
}
*relptr = 0;
return section->reloc_count;
}
if (tblptr && section->reloc_count) {
for (count = 0; count++ < section->reloc_count;)
*relptr++ = tblptr++;
*relptr = 0;
return section->reloc_count;
}
if (!NAME(aout,slurp_reloc_table)(abfd, section, symbols))
return -1;
tblptr = section->relocation;
/* fix up howto entries */
for (count = 0; count++ < section->reloc_count;)
{
c = tblptr->howto - NAME(aout,ext_howto_table);
tblptr->howto = &mips_howto_table_ext[c];
*relptr++ = tblptr++;
}
*relptr = 0;
return section->reloc_count;
}
static CONST struct aout_backend_data MY(backend_data) = {
0, /* zmagic contiguous */
1, /* text incl header */
0, /* entry is text address */
0, /* exec_hdr_flags */
TARGET_PAGE_SIZE, /* text vma */
MY_set_sizes,
0, /* text size includes exec header */
0, /* add_dynamic_symbols */
0, /* add_one_symbol */
0, /* link_dynamic_object */
0, /* write_dynamic_symbol */
0, /* check_dynamic_reloc */
0 /* finish_dynamic_link */
};
const bfd_target aout_mips_little_vec =
{
"a.out-mips-little", /* name */
bfd_target_aout_flavour,
BFD_ENDIAN_LITTLE, /* target byte order (little) */
BFD_ENDIAN_LITTLE, /* target headers byte order (little) */
(HAS_RELOC | EXEC_P | /* object flags */
HAS_LINENO | HAS_DEBUG |
HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
(SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_CODE | SEC_DATA),
MY_symbol_leading_char,
' ', /* ar_pad_char */
15, /* ar_max_namelen */
bfd_getl64, bfd_getl_signed_64, bfd_putl64,
bfd_getl32, bfd_getl_signed_32, bfd_putl32,
bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
bfd_getl64, bfd_getl_signed_64, bfd_putl64,
bfd_getl32, bfd_getl_signed_32, bfd_putl32,
bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
{_bfd_dummy_target, MY_object_p, /* bfd_check_format */
bfd_generic_archive_p, MY_core_file_p},
{bfd_false, MY_mkobject, /* bfd_set_format */
_bfd_generic_mkarchive, bfd_false},
{bfd_false, MY_write_object_contents, /* bfd_write_contents */
_bfd_write_archive_contents, bfd_false},
BFD_JUMP_TABLE_GENERIC (MY),
BFD_JUMP_TABLE_COPY (MY),
BFD_JUMP_TABLE_CORE (MY),
BFD_JUMP_TABLE_ARCHIVE (MY),
BFD_JUMP_TABLE_SYMBOLS (MY),
BFD_JUMP_TABLE_RELOCS (MY),
BFD_JUMP_TABLE_WRITE (MY),
BFD_JUMP_TABLE_LINK (MY),
BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
(PTR) MY_backend_data,
};
const bfd_target aout_mips_big_vec =
{
"a.out-mips-big", /* name */
bfd_target_aout_flavour,
BFD_ENDIAN_BIG, /* target byte order (big) */
BFD_ENDIAN_BIG, /* target headers byte order (big) */
(HAS_RELOC | EXEC_P | /* object flags */
HAS_LINENO | HAS_DEBUG |
HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
(SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_CODE | SEC_DATA),
MY_symbol_leading_char,
' ', /* ar_pad_char */
15, /* ar_max_namelen */
bfd_getb64, bfd_getb_signed_64, bfd_putb64,
bfd_getb32, bfd_getb_signed_32, bfd_putb32,
bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
bfd_getb64, bfd_getb_signed_64, bfd_putb64,
bfd_getb32, bfd_getb_signed_32, bfd_putb32,
bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
{_bfd_dummy_target, MY_object_p, /* bfd_check_format */
bfd_generic_archive_p, MY_core_file_p},
{bfd_false, MY_mkobject, /* bfd_set_format */
_bfd_generic_mkarchive, bfd_false},
{bfd_false, MY_write_object_contents, /* bfd_write_contents */
_bfd_write_archive_contents, bfd_false},
BFD_JUMP_TABLE_GENERIC (MY),
BFD_JUMP_TABLE_COPY (MY),
BFD_JUMP_TABLE_CORE (MY),
BFD_JUMP_TABLE_ARCHIVE (MY),
BFD_JUMP_TABLE_SYMBOLS (MY),
BFD_JUMP_TABLE_RELOCS (MY),
BFD_JUMP_TABLE_WRITE (MY),
BFD_JUMP_TABLE_LINK (MY),
BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
(PTR) MY_backend_data,
};

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CC = cc -Wf,-XNg1000
# for X11, since the native DECwindows include files are really broken when
# it comes to function prototypes.
X11_EXTRA_CFLAGS = "-DNeedFunctionPrototypes=0"

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/* MIPS ELF support for BFD.
Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
By Ian Lance Taylor, Cygnus Support, <ian@cygnus.com>, from
information in the System V Application Binary Interface, MIPS
Processor Supplement.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* This file holds definitions specific to the MIPS ELF ABI. Note
that most of this is not actually implemented by BFD. */
#ifndef _ELF_MIPS_H
#define _ELF_MIPS_H
/* Processor specific flags for the ELF header e_flags field. */
/* At least one .noreorder directive appears in the source. */
#define EF_MIPS_NOREORDER 0x00000001
/* File contains position independent code. */
#define EF_MIPS_PIC 0x00000002
/* Code in file uses the standard calling sequence for calling
position independent code. */
#define EF_MIPS_CPIC 0x00000004
/* Code in file uses new ABI (-n32 on Irix 6). */
#define EF_MIPS_ABI2 0x00000020
/* Four bit MIPS architecture field. */
#define EF_MIPS_ARCH 0xf0000000
/* -mips1 code. */
#define E_MIPS_ARCH_1 0x00000000
/* -mips2 code. */
#define E_MIPS_ARCH_2 0x10000000
/* -mips3 code. */
#define E_MIPS_ARCH_3 0x20000000
/* -mips4 code. */
#define E_MIPS_ARCH_4 0x30000000
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
values have a special meaning. */
/* Defined and allocated common symbol. Value is virtual address. If
relocated, alignment must be preserved. */
#define SHN_MIPS_ACOMMON 0xff00
/* Defined and allocated text symbol. Value is virtual address.
Occur in the dynamic symbol table of Alpha OSF/1 and Irix 5 executables. */
#define SHN_MIPS_TEXT 0xff01
/* Defined and allocated data symbol. Value is virtual address.
Occur in the dynamic symbol table of Alpha OSF/1 and Irix 5 executables. */
#define SHN_MIPS_DATA 0xff02
/* Small common symbol. */
#define SHN_MIPS_SCOMMON 0xff03
/* Small undefined symbol. */
#define SHN_MIPS_SUNDEFINED 0xff04
/* Processor specific section types. */
/* Section contains the set of dynamic shared objects used when
statically linking. */
#define SHT_MIPS_LIBLIST 0x70000000
/* I'm not sure what this is, but it's used on Irix 5. */
#define SHT_MIPS_MSYM 0x70000001
/* Section contains list of symbols whose definitions conflict with
symbols defined in shared objects. */
#define SHT_MIPS_CONFLICT 0x70000002
/* Section contains the global pointer table. */
#define SHT_MIPS_GPTAB 0x70000003
/* Section contains microcode information. The exact format is
unspecified. */
#define SHT_MIPS_UCODE 0x70000004
/* Section contains some sort of debugging information. The exact
format is unspecified. It's probably ECOFF symbols. */
#define SHT_MIPS_DEBUG 0x70000005
/* Section contains register usage information. */
#define SHT_MIPS_REGINFO 0x70000006
/* Section contains interface information. */
#define SHT_MIPS_IFACE 0x7000000b
/* Section contains description of contents of another section. */
#define SHT_MIPS_CONTENT 0x7000000c
/* Section contains miscellaneous options. */
#define SHT_MIPS_OPTIONS 0x7000000d
/* DWARF debugging section. */
#define SHT_MIPS_DWARF 0x7000001e
/* I'm not sure what this is, but it appears on Irix 6. */
#define SHT_MIPS_SYMBOL_LIB 0x70000020
/* Events section. */
#define SHT_MIPS_EVENTS 0x70000021
/* A section of type SHT_MIPS_LIBLIST contains an array of the
following structure. The sh_link field is the section index of the
string table. The sh_info field is the number of entries in the
section. */
typedef struct
{
/* String table index for name of shared object. */
unsigned long l_name;
/* Time stamp. */
unsigned long l_time_stamp;
/* Checksum of symbol names and common sizes. */
unsigned long l_checksum;
/* String table index for version. */
unsigned long l_version;
/* Flags. */
unsigned long l_flags;
} Elf32_Lib;
/* The l_flags field of an Elf32_Lib structure may contain the
following flags. */
/* Require an exact match at runtime. */
#define LL_EXACT_MATCH 0x00000001
/* Ignore version incompatibilities at runtime. */
#define LL_IGNORE_INT_VER 0x00000002
/* A section of type SHT_MIPS_CONFLICT is an array of indices into the
.dynsym section. Each element has the following type. */
typedef unsigned long Elf32_Conflict;
/* A section of type SHT_MIPS_GPTAB contains information about how
much GP space would be required for different -G arguments. This
information is only used so that the linker can provide informative
suggestions as to the best -G value to use. The sh_info field is
the index of the section for which this information applies. The
contents of the section are an array of the following union. The
first element uses the gt_header field. The remaining elements use
the gt_entry field. */
typedef union
{
struct
{
/* -G value actually used for this object file. */
unsigned long gt_current_g_value;
/* Unused. */
unsigned long gt_unused;
} gt_header;
struct
{
/* If this -G argument has been used... */
unsigned long gt_g_value;
/* ...this many GP section bytes would be required. */
unsigned long gt_bytes;
} gt_entry;
} Elf32_gptab;
/* The external version of Elf32_gptab. */
typedef union
{
struct
{
unsigned char gt_current_g_value[4];
unsigned char gt_unused[4];
} gt_header;
struct
{
unsigned char gt_g_value[4];
unsigned char gt_bytes[4];
} gt_entry;
} Elf32_External_gptab;
/* A section of type SHT_MIPS_REGINFO contains the following
structure. */
typedef struct
{
/* Mask of general purpose registers used. */
unsigned long ri_gprmask;
/* Mask of co-processor registers used. */
unsigned long ri_cprmask[4];
/* GP register value for this object file. */
long ri_gp_value;
} Elf32_RegInfo;
/* The external version of the Elf_RegInfo structure. */
typedef struct
{
unsigned char ri_gprmask[4];
unsigned char ri_cprmask[4][4];
unsigned char ri_gp_value[4];
} Elf32_External_RegInfo;
/* MIPS ELF .reginfo swapping routines. */
extern void bfd_mips_elf32_swap_reginfo_in
PARAMS ((bfd *, const Elf32_External_RegInfo *, Elf32_RegInfo *));
extern void bfd_mips_elf32_swap_reginfo_out
PARAMS ((bfd *, const Elf32_RegInfo *, Elf32_External_RegInfo *));
/* Processor specific section flags. */
/* This section must be in the global data area. */
#define SHF_MIPS_GPREL 0x10000000
/* This section should be merged. */
#define SHF_MIPS_MERGE 0x20000000
/* This section contains 32 bit addresses. */
#define SHF_MIPS_ADDR32 0x40000000
/* This section contains 64 bit addresses. */
#define SHF_MIPS_ADDR64 0x80000000
/* This section may not be stripped. */
#define SHF_MIPS_NOSTRIP 0x08000000
/* This section is local to threads. */
#define SHF_MIPS_LOCAL 0x04000000
/* Linker should generate implicit weak names for this section. */
#define SHF_MIPS_NAMES 0x02000000
/* Processor specific program header types. */
/* Register usage information. Identifies one .reginfo section. */
#define PT_MIPS_REGINFO 0x70000000
/* Runtime procedure table. */
#define PT_MIPS_RTPROC 0x70000001
/* Processor specific dynamic array tags. */
/* 32 bit version number for runtime linker interface. */
#define DT_MIPS_RLD_VERSION 0x70000001
/* Time stamp. */
#define DT_MIPS_TIME_STAMP 0x70000002
/* Checksum of external strings and common sizes. */
#define DT_MIPS_ICHECKSUM 0x70000003
/* Index of version string in string table. */
#define DT_MIPS_IVERSION 0x70000004
/* 32 bits of flags. */
#define DT_MIPS_FLAGS 0x70000005
/* Base address of the segment. */
#define DT_MIPS_BASE_ADDRESS 0x70000006
/* Address of .conflict section. */
#define DT_MIPS_CONFLICT 0x70000008
/* Address of .liblist section. */
#define DT_MIPS_LIBLIST 0x70000009
/* Number of local global offset table entries. */
#define DT_MIPS_LOCAL_GOTNO 0x7000000a
/* Number of entries in the .conflict section. */
#define DT_MIPS_CONFLICTNO 0x7000000b
/* Number of entries in the .liblist section. */
#define DT_MIPS_LIBLISTNO 0x70000010
/* Number of entries in the .dynsym section. */
#define DT_MIPS_SYMTABNO 0x70000011
/* Index of first external dynamic symbol not referenced locally. */
#define DT_MIPS_UNREFEXTNO 0x70000012
/* Index of first dynamic symbol in global offset table. */
#define DT_MIPS_GOTSYM 0x70000013
/* Number of page table entries in global offset table. */
#define DT_MIPS_HIPAGENO 0x70000014
/* Address of run time loader map, used for debugging. */
#define DT_MIPS_RLD_MAP 0x70000016
/* Flags which may appear in a DT_MIPS_FLAGS entry. */
/* No flags. */
#define RHF_NONE 0x00000000
/* Uses shortcut pointers. */
#define RHF_QUICKSTART 0x00000001
/* Hash size is not a power of two. */
#define RHF_NOTPOT 0x00000002
/* Ignore LD_LIBRARY_PATH. */
#define RHS_NO_LIBRARY_REPLACEMENT \
0x00000004
/* Special values for the st_other field in the symbol table. These
are used in an Irix 5 dynamic symbol table. */
#define STO_DEFAULT 0x00
#define STO_INTERNAL 0x01
#define STO_HIDDEN 0x02
#define STO_PROTECTED 0x03
/* This value is used for a mips16 .text symbol. */
#define STO_MIPS16 0xf0
/* The 64-bit MIPS ELF ABI uses an unusual reloc format. Each
relocation entry specifies up to three actual relocations, all at
the same address. The first relocation which required a symbol
uses the symbol in the r_sym field. The second relocation which
requires a symbol uses the symbol in the r_ssym field. If all
three relocations require a symbol, the third one uses a zero
value. */
/* An entry in a 64 bit SHT_REL section. */
typedef struct
{
/* Address of relocation. */
unsigned char r_offset[8];
/* Symbol index. */
unsigned char r_sym[4];
/* Special symbol. */
unsigned char r_ssym[1];
/* Third relocation. */
unsigned char r_type3[1];
/* Second relocation. */
unsigned char r_type2[1];
/* First relocation. */
unsigned char r_type[1];
} Elf64_Mips_External_Rel;
typedef struct
{
/* Address of relocation. */
bfd_vma r_offset;
/* Symbol index. */
unsigned long r_sym;
/* Special symbol. */
unsigned char r_ssym;
/* Third relocation. */
unsigned char r_type3;
/* Second relocation. */
unsigned char r_type2;
/* First relocation. */
unsigned char r_type;
} Elf64_Mips_Internal_Rel;
/* An entry in a 64 bit SHT_RELA section. */
typedef struct
{
/* Address of relocation. */
unsigned char r_offset[8];
/* Symbol index. */
unsigned char r_sym[4];
/* Special symbol. */
unsigned char r_ssym[1];
/* Third relocation. */
unsigned char r_type3[1];
/* Second relocation. */
unsigned char r_type2[1];
/* First relocation. */
unsigned char r_type[1];
/* Addend. */
unsigned char r_addend[8];
} Elf64_Mips_External_Rela;
typedef struct
{
/* Address of relocation. */
bfd_vma r_offset;
/* Symbol index. */
unsigned long r_sym;
/* Special symbol. */
unsigned char r_ssym;
/* Third relocation. */
unsigned char r_type3;
/* Second relocation. */
unsigned char r_type2;
/* First relocation. */
unsigned char r_type;
/* Addend. */
bfd_signed_vma r_addend;
} Elf64_Mips_Internal_Rela;
/* Values found in the r_ssym field of a relocation entry. */
/* No relocation. */
#define RSS_UNDEF 0
/* Value of GP. */
#define RSS_GP 1
/* Value of GP in object being relocated. */
#define RSS_GP0 2
/* Address of location being relocated. */
#define RSS_LOC 3
/* A SHT_MIPS_OPTIONS section contains a series of options, each of
which starts with this header. */
typedef struct
{
/* Type of option. */
unsigned char kind[1];
/* Size of option descriptor, including header. */
unsigned char size[1];
/* Section index of affected section, or 0 for global option. */
unsigned char section[2];
/* Information specific to this kind of option. */
unsigned char info[4];
} Elf_External_Options;
typedef struct
{
/* Type of option. */
unsigned char kind;
/* Size of option descriptor, including header. */
unsigned char size;
/* Section index of affected section, or 0 for global option. */
unsigned short section;
/* Information specific to this kind of option. */
unsigned long info;
} Elf_Internal_Options;
/* MIPS ELF option header swapping routines. */
extern void bfd_mips_elf_swap_options_in
PARAMS ((bfd *, const Elf_External_Options *, Elf_Internal_Options *));
extern void bfd_mips_elf_swap_options_out
PARAMS ((bfd *, const Elf_Internal_Options *, Elf_External_Options *));
/* Values which may appear in the kind field of an Elf_Options
structure. */
/* Undefined. */
#define ODK_NULL 0
/* Register usage and GP value. */
#define ODK_REGINFO 1
/* Exception processing information. */
#define ODK_EXCEPTIONS 2
/* Section padding information. */
#define ODK_PAD 3
/* In the 32 bit ABI, an ODK_REGINFO option is just a Elf32_Reginfo
structure. In the 64 bit ABI, it is the following structure. The
info field of the options header is not used. */
typedef struct
{
/* Mask of general purpose registers used. */
unsigned char ri_gprmask[4];
/* Padding. */
unsigned char ri_pad[4];
/* Mask of co-processor registers used. */
unsigned char ri_cprmask[4][4];
/* GP register value for this object file. */
unsigned char ri_gp_value[8];
} Elf64_External_RegInfo;
typedef struct
{
/* Mask of general purpose registers used. */
unsigned long ri_gprmask;
/* Padding. */
unsigned long ri_pad;
/* Mask of co-processor registers used. */
unsigned long ri_cprmask[4];
/* GP register value for this object file. */
bfd_vma ri_gp_value;
} Elf64_Internal_RegInfo;
/* MIPS ELF reginfo swapping routines. */
extern void bfd_mips_elf64_swap_reginfo_in
PARAMS ((bfd *, const Elf64_External_RegInfo *, Elf64_Internal_RegInfo *));
extern void bfd_mips_elf64_swap_reginfo_out
PARAMS ((bfd *, const Elf64_Internal_RegInfo *, Elf64_External_RegInfo *));
#endif /* _ELF_MIPS_H */

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/* mips.h. Mips opcode list for GDB, the GNU debugger.
Copyright 1993, 94, 95, 96, 1997 Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef _MIPS_H_
#define _MIPS_H_
/* These are bit masks and shift counts to use to access the various
fields of an instruction. To retrieve the X field of an
instruction, use the expression
(i >> OP_SH_X) & OP_MASK_X
To set the same field (to j), use
i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
Make sure you use fields that are appropriate for the instruction,
of course.
The 'i' format uses OP, RS, RT and IMMEDIATE.
The 'j' format uses OP and TARGET.
The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
The 'b' format uses OP, RS, RT and DELTA.
The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
breakpoint instruction are not defined; Kane says the breakpoint
code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
only use ten bits).
The syscall instruction uses SYSCALL.
The general coprocessor instructions use COPZ. */
#define OP_MASK_OP 0x3f
#define OP_SH_OP 26
#define OP_MASK_RS 0x1f
#define OP_SH_RS 21
#define OP_MASK_FR 0x1f
#define OP_SH_FR 21
#define OP_MASK_FMT 0x1f
#define OP_SH_FMT 21
#define OP_MASK_BCC 0x7
#define OP_SH_BCC 18
#define OP_MASK_CODE 0x3ff
#define OP_SH_CODE 16
#define OP_MASK_RT 0x1f
#define OP_SH_RT 16
#define OP_MASK_FT 0x1f
#define OP_SH_FT 16
#define OP_MASK_CACHE 0x1f
#define OP_SH_CACHE 16
#define OP_MASK_RD 0x1f
#define OP_SH_RD 11
#define OP_MASK_FS 0x1f
#define OP_SH_FS 11
#define OP_MASK_PREFX 0x1f
#define OP_SH_PREFX 11
#define OP_MASK_CCC 0x7
#define OP_SH_CCC 8
#define OP_MASK_SYSCALL 0xfffff
#define OP_SH_SYSCALL 6
#define OP_MASK_SHAMT 0x1f
#define OP_SH_SHAMT 6
#define OP_MASK_FD 0x1f
#define OP_SH_FD 6
#define OP_MASK_TARGET 0x3ffffff
#define OP_SH_TARGET 0
#define OP_MASK_COPZ 0x1ffffff
#define OP_SH_COPZ 0
#define OP_MASK_IMMEDIATE 0xffff
#define OP_SH_IMMEDIATE 0
#define OP_MASK_DELTA 0xffff
#define OP_SH_DELTA 0
#define OP_MASK_FUNCT 0x3f
#define OP_SH_FUNCT 0
#define OP_MASK_SPEC 0x3f
#define OP_SH_SPEC 0
#define OP_SH_LOCC 8 /* FP condition code */
#define OP_SH_HICC 18 /* FP condition code */
#define OP_MASK_CC 0x7
#define OP_SH_COP1NORM 25 /* Normal COP1 encoding */
#define OP_MASK_COP1NORM 0x1 /* a single bit */
#define OP_SH_COP1SPEC 21 /* COP1 encodings */
#define OP_MASK_COP1SPEC 0xf
#define OP_MASK_COP1SCLR 0x4
#define OP_MASK_COP1CMP 0x3
#define OP_SH_COP1CMP 4
#define OP_SH_FORMAT 21 /* FP short format field */
#define OP_MASK_FORMAT 0x7
#define OP_SH_TRUE 16
#define OP_MASK_TRUE 0x1
#define OP_SH_GE 17
#define OP_MASK_GE 0x01
#define OP_SH_UNSIGNED 16
#define OP_MASK_UNSIGNED 0x1
#define OP_SH_HINT 16
#define OP_MASK_HINT 0x1f
#define OP_SH_MMI 0 /* Multimedia (parallel) op */
#define OP_MASK_MMI 0x3f
#define OP_SH_MMISUB 6
#define OP_MASK_MMISUB 0x1f
#define OP_MASK_PERFREG 0x1f /* Performance monitoring */
#define OP_SH_PERFREG 1
/* This structure holds information for a particular instruction. */
struct mips_opcode
{
/* The name of the instruction. */
const char *name;
/* A string describing the arguments for this instruction. */
const char *args;
/* The basic opcode for the instruction. When assembling, this
opcode is modified by the arguments to produce the actual opcode
that is used. If pinfo is INSN_MACRO, then this is 0. */
unsigned long match;
/* If pinfo is not INSN_MACRO, then this is a bit mask for the
relevant portions of the opcode when disassembling. If the
actual opcode anded with the match field equals the opcode field,
then we have found the correct instruction. If pinfo is
INSN_MACRO, then this field is the macro identifier. */
unsigned long mask;
/* For a macro, this is INSN_MACRO. Otherwise, it is a collection
of bits describing the instruction, notably any relevant hazard
information. */
unsigned long pinfo;
/* A collection of bits describing the instruction sets of which this
instruction or macro is a member. */
unsigned long membership;
};
/* These are the characters which may appears in the args field of an
instruction. They appear in the order in which the fields appear
when the instruction is used. Commas and parentheses in the args
string are ignored when assembling, and written into the output
when disassembling.
Each of these characters corresponds to a mask field defined above.
"<" 5 bit shift amount (OP_*_SHAMT)
">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
"a" 26 bit target address (OP_*_TARGET)
"b" 5 bit base register (OP_*_RS)
"c" 10 bit breakpoint code (OP_*_CODE)
"d" 5 bit destination register specifier (OP_*_RD)
"h" 5 bit prefx hint (OP_*_PREFX)
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
"j" 16 bit signed immediate (OP_*_DELTA)
"k" 5 bit cache opcode in target register position (OP_*_CACHE)
"o" 16 bit signed offset (OP_*_DELTA)
"p" 16 bit PC relative branch target address (OP_*_DELTA)
"r" 5 bit same register used as both source and target (OP_*_RS)
"s" 5 bit source register specifier (OP_*_RS)
"t" 5 bit target register (OP_*_RT)
"u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
"v" 5 bit same register used as both source and destination (OP_*_RS)
"w" 5 bit same register used as both target and destination (OP_*_RT)
"C" 25 bit coprocessor function code (OP_*_COPZ)
"B" 20 bit syscall function code (OP_*_SYSCALL)
"x" accept and ignore register name
"z" must be zero register
Floating point instructions:
"D" 5 bit destination register (OP_*_FD)
"M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
"N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
"S" 5 bit fs source 1 register (OP_*_FS)
"T" 5 bit ft source 2 register (OP_*_FT)
"R" 5 bit fr source 3 register (OP_*_FR)
"V" 5 bit same register used as floating source and destination (OP_*_FS)
"W" 5 bit same register used as floating target and destination (OP_*_FT)
Coprocessor instructions:
"E" 5 bit target register (OP_*_RT)
"G" 5 bit destination register (OP_*_RD)
"P" 5 bit performance-monitor register (OP_*_PERFREG)
Macro instructions:
"A" General 32 bit expression
"I" 32 bit immediate
"F" 64 bit floating point constant in .rdata
"L" 64 bit floating point constant in .lit8
"f" 32 bit floating point constant
"l" 32 bit floating point constant in .lit4
Other:
"()" parens surrounding optional value
"," separates operands
Characters used so far, for quick reference when adding more:
"<>(),"
"ABCDEFGILMNSTRVW"
"abcdfhijkloprstuvwxz"
*/
/* These are the bits which may be set in the pinfo field of an
instructions, if it is not equal to INSN_MACRO. */
/* Modifies the general purpose register in OP_*_RD. */
#define INSN_WRITE_GPR_D 0x00000001
/* Modifies the general purpose register in OP_*_RT. */
#define INSN_WRITE_GPR_T 0x00000002
/* Modifies general purpose register 31. */
#define INSN_WRITE_GPR_31 0x00000004
/* Modifies the floating point register in OP_*_FD. */
#define INSN_WRITE_FPR_D 0x00000008
/* Modifies the floating point register in OP_*_FS. */
#define INSN_WRITE_FPR_S 0x00000010
/* Modifies the floating point register in OP_*_FT. */
#define INSN_WRITE_FPR_T 0x00000020
/* Reads the general purpose register in OP_*_RS. */
#define INSN_READ_GPR_S 0x00000040
/* Reads the general purpose register in OP_*_RT. */
#define INSN_READ_GPR_T 0x00000080
/* Reads the floating point register in OP_*_FS. */
#define INSN_READ_FPR_S 0x00000100
/* Reads the floating point register in OP_*_FT. */
#define INSN_READ_FPR_T 0x00000200
/* Reads the floating point register in OP_*_FR. */
#define INSN_READ_FPR_R 0x00000400
/* Modifies coprocessor condition code. */
#define INSN_WRITE_COND_CODE 0x00000800
/* Reads coprocessor condition code. */
#define INSN_READ_COND_CODE 0x00001000
/* TLB operation. */
#define INSN_TLB 0x00002000
/* Reads coprocessor register other than floating point register. */
#define INSN_COP 0x00004000
/* Instruction loads value from memory, requiring delay. */
#define INSN_LOAD_MEMORY_DELAY 0x00008000
/* Instruction loads value from coprocessor, requiring delay. */
#define INSN_LOAD_COPROC_DELAY 0x00010000
/* Instruction has unconditional branch delay slot. */
#define INSN_UNCOND_BRANCH_DELAY 0x00020000
/* Instruction has conditional branch delay slot. */
#define INSN_COND_BRANCH_DELAY 0x00040000
/* Conditional branch likely: if branch not taken, insn nullified. */
#define INSN_COND_BRANCH_LIKELY 0x00080000
/* Moves to coprocessor register, requiring delay. */
#define INSN_COPROC_MOVE_DELAY 0x00100000
/* Loads coprocessor register from memory, requiring delay. */
#define INSN_COPROC_MEMORY_DELAY 0x00200000
/* Reads the HI register. */
#define INSN_READ_HI 0x00400000
/* Reads the LO register. */
#define INSN_READ_LO 0x00800000
/* Modifies the HI register. */
#define INSN_WRITE_HI 0x01000000
/* Modifies the LO register. */
#define INSN_WRITE_LO 0x02000000
/* Takes a trap (easier to keep out of delay slot). */
#define INSN_TRAP 0x04000000
/* Instruction stores value into memory. */
#define INSN_STORE_MEMORY 0x08000000
/* Instruction uses single precision floating point. */
#define FP_S 0x10000000
/* Instruction uses double precision floating point. */
#define FP_D 0x20000000
/* As yet unused bits: 0x40000000 */
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
#define INSN_MACRO 0xffffffff
/* MIPS ISA field--CPU level at which insn is supported. */
#define INSN_ISA 0x0000000F
/* An instruction which is not part of any basic MIPS ISA.
(ie it is a chip specific instruction) */
#define INSN_NO_ISA 0x00000000
/* MIPS ISA 1 instruction. */
#define INSN_ISA1 0x00000001
/* MIPS ISA 2 instruction (R6000 or R4000). */
#define INSN_ISA2 0x00000002
/* MIPS ISA 3 instruction (R4000). */
#define INSN_ISA3 0x00000003
/* MIPS ISA 4 instruction (R8000). */
#define INSN_ISA4 0x00000004
/* Chip specific instructions. These are bitmasks. */
/* MIPS R4650 instruction. */
#define INSN_4650 0x00000010
/* LSI R4010 instruction. */
#define INSN_4010 0x00000020
/* NEC VR4100 instruction. */
#define INSN_4100 0x00000040
/* Toshiba R3900 instruction. */
#define INSN_3900 0x00000080
/* This is a list of macro expanded instructions.
*
* _I appended means immediate
* _A appended means address
* _AB appended means address with base register
* _D appended means 64 bit floating point constant
* _S appended means 32 bit floating point constant
*/
enum {
M_ABS,
M_ADD_I,
M_ADDU_I,
M_AND_I,
M_BEQ,
M_BEQ_I,
M_BEQL_I,
M_BGE,
M_BGEL,
M_BGE_I,
M_BGEL_I,
M_BGEU,
M_BGEUL,
M_BGEU_I,
M_BGEUL_I,
M_BGT,
M_BGTL,
M_BGT_I,
M_BGTL_I,
M_BGTU,
M_BGTUL,
M_BGTU_I,
M_BGTUL_I,
M_BLE,
M_BLEL,
M_BLE_I,
M_BLEL_I,
M_BLEU,
M_BLEUL,
M_BLEU_I,
M_BLEUL_I,
M_BLT,
M_BLTL,
M_BLT_I,
M_BLTL_I,
M_BLTU,
M_BLTUL,
M_BLTU_I,
M_BLTUL_I,
M_BNE,
M_BNE_I,
M_BNEL_I,
M_DABS,
M_DADD_I,
M_DADDU_I,
M_DDIV_3,
M_DDIV_3I,
M_DDIVU_3,
M_DDIVU_3I,
M_DIV_3,
M_DIV_3I,
M_DIVU_3,
M_DIVU_3I,
M_DLA_AB,
M_DLI,
M_DMUL,
M_DMUL_I,
M_DMULO,
M_DMULO_I,
M_DMULOU,
M_DMULOU_I,
M_DREM_3,
M_DREM_3I,
M_DREMU_3,
M_DREMU_3I,
M_DSUB_I,
M_DSUBU_I,
M_DSUBU_I_2,
M_J_A,
M_JAL_1,
M_JAL_2,
M_JAL_A,
M_L_DOB,
M_L_DAB,
M_LA_AB,
M_LB_A,
M_LB_AB,
M_LBU_A,
M_LBU_AB,
M_LD_A,
M_LD_OB,
M_LD_AB,
M_LDC1_AB,
M_LDC2_AB,
M_LDC3_AB,
M_LDL_AB,
M_LDR_AB,
M_LH_A,
M_LH_AB,
M_LHU_A,
M_LHU_AB,
M_LI,
M_LI_D,
M_LI_DD,
M_LI_S,
M_LI_SS,
M_LL_AB,
M_LLD_AB,
M_LS_A,
M_LW_A,
M_LW_AB,
M_LWC0_A,
M_LWC0_AB,
M_LWC1_A,
M_LWC1_AB,
M_LWC2_A,
M_LWC2_AB,
M_LWC3_A,
M_LWC3_AB,
M_LWL_A,
M_LWL_AB,
M_LWR_A,
M_LWR_AB,
M_LWU_AB,
M_MUL,
M_MUL_I,
M_MULO,
M_MULO_I,
M_MULOU,
M_MULOU_I,
M_NOR_I,
M_OR_I,
M_REM_3,
M_REM_3I,
M_REMU_3,
M_REMU_3I,
M_ROL,
M_ROL_I,
M_ROR,
M_ROR_I,
M_S_DA,
M_S_DOB,
M_S_DAB,
M_S_S,
M_SC_AB,
M_SCD_AB,
M_SD_A,
M_SD_OB,
M_SD_AB,
M_SDC1_AB,
M_SDC2_AB,
M_SDC3_AB,
M_SDL_AB,
M_SDR_AB,
M_SEQ,
M_SEQ_I,
M_SGE,
M_SGE_I,
M_SGEU,
M_SGEU_I,
M_SGT,
M_SGT_I,
M_SGTU,
M_SGTU_I,
M_SLE,
M_SLE_I,
M_SLEU,
M_SLEU_I,
M_SLT_I,
M_SLTU_I,
M_SNE,
M_SNE_I,
M_SB_A,
M_SB_AB,
M_SH_A,
M_SH_AB,
M_SW_A,
M_SW_AB,
M_SWC0_A,
M_SWC0_AB,
M_SWC1_A,
M_SWC1_AB,
M_SWC2_A,
M_SWC2_AB,
M_SWC3_A,
M_SWC3_AB,
M_SWL_A,
M_SWL_AB,
M_SWR_A,
M_SWR_AB,
M_SUB_I,
M_SUBU_I,
M_SUBU_I_2,
M_TEQ_I,
M_TGE_I,
M_TGEU_I,
M_TLT_I,
M_TLTU_I,
M_TNE_I,
M_TRUNCWD,
M_TRUNCWS,
M_ULD,
M_ULD_A,
M_ULH,
M_ULH_A,
M_ULHU,
M_ULHU_A,
M_ULW,
M_ULW_A,
M_USH,
M_USH_A,
M_USW,
M_USW_A,
M_USD,
M_USD_A,
M_XOR_I,
M_COP0,
M_COP1,
M_COP2,
M_COP3,
M_NUM_MACROS
};
/* The order of overloaded instructions matters. Label arguments and
register arguments look the same. Instructions that can have either
for arguments must apear in the correct order in this table for the
assembler to pick the right one. In other words, entries with
immediate operands must apear after the same instruction with
registers.
Many instructions are short hand for other instructions (i.e., The
jal <register> instruction is short for jalr <register>). */
extern const struct mips_opcode mips_builtin_opcodes[];
extern const int bfd_mips_num_builtin_opcodes;
extern struct mips_opcode *mips_opcodes;
extern int bfd_mips_num_opcodes;
#define NUMOPCODES bfd_mips_num_opcodes
/* The rest of this file adds definitions for the mips16 TinyRISC
processor. */
/* These are the bitmasks and shift counts used for the different
fields in the instruction formats. Other than OP, no masks are
provided for the fixed portions of an instruction, since they are
not needed.
The I format uses IMM11.
The RI format uses RX and IMM8.
The RR format uses RX, and RY.
The RRI format uses RX, RY, and IMM5.
The RRR format uses RX, RY, and RZ.
The RRI_A format uses RX, RY, and IMM4.
The SHIFT format uses RX, RY, and SHAMT.
The I8 format uses IMM8.
The I8_MOVR32 format uses RY and REGR32.
The IR_MOV32R format uses REG32R and MOV32Z.
The I64 format uses IMM8.
The RI64 format uses RY and IMM5.
*/
#define MIPS16OP_MASK_OP 0x1f
#define MIPS16OP_SH_OP 11
#define MIPS16OP_MASK_IMM11 0x7ff
#define MIPS16OP_SH_IMM11 0
#define MIPS16OP_MASK_RX 0x7
#define MIPS16OP_SH_RX 8
#define MIPS16OP_MASK_IMM8 0xff
#define MIPS16OP_SH_IMM8 0
#define MIPS16OP_MASK_RY 0x7
#define MIPS16OP_SH_RY 5
#define MIPS16OP_MASK_IMM5 0x1f
#define MIPS16OP_SH_IMM5 0
#define MIPS16OP_MASK_RZ 0x7
#define MIPS16OP_SH_RZ 2
#define MIPS16OP_MASK_IMM4 0xf
#define MIPS16OP_SH_IMM4 0
#define MIPS16OP_MASK_REGR32 0x1f
#define MIPS16OP_SH_REGR32 0
#define MIPS16OP_MASK_REG32R 0x1f
#define MIPS16OP_SH_REG32R 3
#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
#define MIPS16OP_MASK_MOVE32Z 0x7
#define MIPS16OP_SH_MOVE32Z 0
#define MIPS16OP_MASK_IMM6 0x3f
#define MIPS16OP_SH_IMM6 5
/* These are the characters which may appears in the args field of an
instruction. They appear in the order in which the fields appear
when the instruction is used. Commas and parentheses in the args
string are ignored when assembling, and written into the output
when disassembling.
"y" 3 bit register (MIPS16OP_*_RY)
"x" 3 bit register (MIPS16OP_*_RX)
"z" 3 bit register (MIPS16OP_*_RZ)
"Z" 3 bit register (MIPS16OP_*_MOVE32Z)
"v" 3 bit same register as source and destination (MIPS16OP_*_RX)
"w" 3 bit same register as source and destination (MIPS16OP_*_RY)
"0" zero register ($0)
"S" stack pointer ($sp or $29)
"P" program counter
"R" return address register ($ra or $31)
"X" 5 bit MIPS register (MIPS16OP_*_REGR32)
"Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
"6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
"a" 26 bit jump address
"e" 11 bit extension value
"l" register list for entry instruction
"L" register list for exit instruction
The remaining codes may be extended. Except as otherwise noted,
the full extended operand is a 16 bit signed value.
"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
"[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
"]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
"4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
"5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
"H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
"W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
"D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
"j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
"8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
"V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
"C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
"U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
"k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
"K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
"p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
"q" 11 bit branch address (MIPS16OP_*_IMM11)
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
*/
/* For the mips16, we use the same opcode table format and a few of
the same flags. However, most of the flags are different. */
/* Modifies the register in MIPS16OP_*_RX. */
#define MIPS16_INSN_WRITE_X 0x00000001
/* Modifies the register in MIPS16OP_*_RY. */
#define MIPS16_INSN_WRITE_Y 0x00000002
/* Modifies the register in MIPS16OP_*_RZ. */
#define MIPS16_INSN_WRITE_Z 0x00000004
/* Modifies the T ($24) register. */
#define MIPS16_INSN_WRITE_T 0x00000008
/* Modifies the SP ($29) register. */
#define MIPS16_INSN_WRITE_SP 0x00000010
/* Modifies the RA ($31) register. */
#define MIPS16_INSN_WRITE_31 0x00000020
/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
/* Reads the register in MIPS16OP_*_RX. */
#define MIPS16_INSN_READ_X 0x00000080
/* Reads the register in MIPS16OP_*_RY. */
#define MIPS16_INSN_READ_Y 0x00000100
/* Reads the register in MIPS16OP_*_MOVE32Z. */
#define MIPS16_INSN_READ_Z 0x00000200
/* Reads the T ($24) register. */
#define MIPS16_INSN_READ_T 0x00000400
/* Reads the SP ($29) register. */
#define MIPS16_INSN_READ_SP 0x00000800
/* Reads the RA ($31) register. */
#define MIPS16_INSN_READ_31 0x00001000
/* Reads the program counter. */
#define MIPS16_INSN_READ_PC 0x00002000
/* Reads the general purpose register in MIPS16OP_*_REGR32. */
#define MIPS16_INSN_READ_GPR_X 0x00004000
/* The following flags have the same value for the mips16 opcode
table:
INSN_UNCOND_BRANCH_DELAY
INSN_COND_BRANCH_DELAY
INSN_COND_BRANCH_LIKELY (never used)
INSN_READ_HI
INSN_READ_LO
INSN_WRITE_HI
INSN_WRITE_LO
INSN_TRAP
INSN_ISA3
*/
extern const struct mips_opcode mips16_opcodes[];
extern const int bfd_mips16_num_opcodes;
#endif /* _MIPS_H_ */

30
contrib/binutils/ld/emulparams/elf32bmip.sh Normal file
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@ -0,0 +1,30 @@
SCRIPT_NAME=elf
OUTPUT_FORMAT="elf32-bigmips"
BIG_OUTPUT_FORMAT="elf32-bigmips"
LITTLE_OUTPUT_FORMAT="elf32-littlemips"
TEXT_START_ADDR=0x0400000
DATA_ADDR=0x10000000
MAXPAGESIZE=0x40000
NONPAGED_TEXT_START_ADDR=0x0400000
SHLIB_TEXT_START_ADDR=0x5ffe0000
TEXT_DYNAMIC=
INITIAL_READONLY_SECTIONS='.reginfo : { *(.reginfo) }'
OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)'
OTHER_GOT_SYMBOLS='
_gp = ALIGN(16) + 0x7ff0;
'
OTHER_GOT_SECTIONS='
.lit8 : { *(.lit8) }
.lit4 : { *(.lit4) }
'
TEXT_START_SYMBOLS='_ftext = . ;'
DATA_START_SYMBOLS='_fdata = . ;'
OTHER_BSS_SYMBOLS='_fbss = .;'
OTHER_SECTIONS='
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
'
ARCH=mips
MACHINE=
TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes

31
contrib/binutils/ld/emulparams/elf32bsmip.sh Executable file
View File

@ -0,0 +1,31 @@
SCRIPT_NAME=elf
OUTPUT_FORMAT="elf32-bigmips"
BIG_OUTPUT_FORMAT="elf32-bigmips"
LITTLE_OUTPUT_FORMAT="elf32-littlemips"
TEXT_START_ADDR=0x0400000
DATA_ADDR=0x10000000
MAXPAGESIZE=0x40000
NONPAGED_TEXT_START_ADDR=0x0400000
SHLIB_TEXT_START_ADDR=0x5ffe0000
TEXT_DYNAMIC=
INITIAL_READONLY_SECTIONS='.reginfo : { *(.reginfo) }'
OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)'
OTHER_GOT_SYMBOLS='
_gp = ALIGN(16) + 0x7ff0;
'
OTHER_GOT_SECTIONS='
.lit8 : { *(.lit8) }
.lit4 : { *(.lit4) }
'
TEXT_START_SYMBOLS='_ftext = . ;'
DATA_START_SYMBOLS='_fdata = . ;'
OTHER_BSS_SYMBOLS='_fbss = .;'
OTHER_SECTIONS='
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
'
ARCH=mips
MACHINE=
TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes
ENTRY=__start

29
contrib/binutils/ld/emulparams/elf32ebmip.sh Normal file
View File

@ -0,0 +1,29 @@
SCRIPT_NAME=elf
OUTPUT_FORMAT="elf32-bigmips"
BIG_OUTPUT_FORMAT="elf32-bigmips"
LITTLE_OUTPUT_FORMAT="elf32-littlemips"
TEXT_START_ADDR=0x0400000
MAXPAGESIZE=0x40000
NONPAGED_TEXT_START_ADDR=0x0400000
SHLIB_TEXT_START_ADDR=0x5ffe0000
INITIAL_READONLY_SECTIONS='.reginfo : { *(.reginfo) }'
OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)'
OTHER_GOT_SYMBOLS='
_gp = ALIGN(16) + 0x7ff0;
'
OTHER_GOT_SECTIONS='
.lit8 : { *(.lit8) }
.lit4 : { *(.lit4) }
'
TEXT_START_SYMBOLS='_ftext = . ;'
DATA_START_SYMBOLS='_fdata = . ;'
OTHER_BSS_SYMBOLS='_fbss = .;'
OTHER_SECTIONS='
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
'
ARCH=mips
MACHINE=
TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes
EMBEDDED=yes

29
contrib/binutils/ld/emulparams/elf32elmip.sh Normal file
View File

@ -0,0 +1,29 @@
SCRIPT_NAME=elf
OUTPUT_FORMAT="elf32-littlemips"
BIG_OUTPUT_FORMAT="elf32-bigmips"
LITTLE_OUTPUT_FORMAT="elf32-littlemips"
TEXT_START_ADDR=0x0400000
MAXPAGESIZE=0x40000
NONPAGED_TEXT_START_ADDR=0x0400000
SHLIB_TEXT_START_ADDR=0x5ffe0000
INITIAL_READONLY_SECTIONS='.reginfo : { *(.reginfo) }'
OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)'
OTHER_GOT_SYMBOLS='
_gp = ALIGN(16) + 0x7ff0;
'
OTHER_GOT_SECTIONS='
.lit8 : { *(.lit8) }
.lit4 : { *(.lit4) }
'
TEXT_START_SYMBOLS='_ftext = . ;'
DATA_START_SYMBOLS='_fdata = . ;'
OTHER_BSS_SYMBOLS='_fbss = .;'
OTHER_SECTIONS='
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
'
ARCH=mips
MACHINE=
TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes
EMBEDDED=yes

30
contrib/binutils/ld/emulparams/elf32lmip.sh Normal file
View File

@ -0,0 +1,30 @@
SCRIPT_NAME=elf
OUTPUT_FORMAT="elf32-littlemips"
BIG_OUTPUT_FORMAT="elf32-bigmips"
LITTLE_OUTPUT_FORMAT="elf32-littlemips"
TEXT_START_ADDR=0x0400000
DATA_ADDR=0x10000000
MAXPAGESIZE=0x40000
NONPAGED_TEXT_START_ADDR=0x0400000
SHLIB_TEXT_START_ADDR=0x5ffe0000
TEXT_DYNAMIC=
INITIAL_READONLY_SECTIONS='.reginfo : { *(.reginfo) }'
OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)'
OTHER_GOT_SYMBOLS='
_gp = ALIGN(16) + 0x7ff0;
'
OTHER_GOT_SECTIONS='
.lit8 : { *(.lit8) }
.lit4 : { *(.lit4) }
'
TEXT_START_SYMBOLS='_ftext = . ;'
DATA_START_SYMBOLS='_fdata = . ;'
OTHER_BSS_SYMBOLS='_fbss = .;'
OTHER_SECTIONS='
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
'
ARCH=mips
MACHINE=
TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes

31
contrib/binutils/ld/emulparams/elf32lsmip.sh Executable file
View File

@ -0,0 +1,31 @@
SCRIPT_NAME=elf
OUTPUT_FORMAT="elf32-littlemips"
BIG_OUTPUT_FORMAT="elf32-bigmips"
LITTLE_OUTPUT_FORMAT="elf32-littlemips"
TEXT_START_ADDR=0x0400000
DATA_ADDR=0x10000000
MAXPAGESIZE=0x40000
NONPAGED_TEXT_START_ADDR=0x0400000
SHLIB_TEXT_START_ADDR=0x5ffe0000
TEXT_DYNAMIC=
INITIAL_READONLY_SECTIONS='.reginfo : { *(.reginfo) }'
OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)'
OTHER_GOT_SYMBOLS='
_gp = ALIGN(16) + 0x7ff0;
'
OTHER_GOT_SECTIONS='
.lit8 : { *(.lit8) }
.lit4 : { *(.lit4) }
'
TEXT_START_SYMBOLS='_ftext = . ;'
DATA_START_SYMBOLS='_fdata = . ;'
OTHER_BSS_SYMBOLS='_fbss = .;'
OTHER_SECTIONS='
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
'
ARCH=mips
MACHINE=
TEMPLATE_NAME=elf32
GENERATE_SHLIB_SCRIPT=yes
ENTRY=__start