From ebb670b334996e0d7c30cdbb483ae7a36ab13337 Mon Sep 17 00:00:00 2001 From: orion Date: Wed, 21 Mar 2001 12:51:37 +0000 Subject: [PATCH] Change ordering of SPDIF register pokes. SPDIF enable needs to be the last poke in sequence. Enabling SPDIF was coercing output rate to 48K, not good for 44.1K tracks. --- sys/dev/sound/pci/cmi.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/sys/dev/sound/pci/cmi.c b/sys/dev/sound/pci/cmi.c index d4ef7a1662d4..27489a2f262a 100644 --- a/sys/dev/sound/pci/cmi.c +++ b/sys/dev/sound/pci/cmi.c @@ -307,8 +307,6 @@ static void cmi_spdif_speed(struct cmi_info *cmi, int speed) { u_int32_t fcr1, lcr, mcr; - mcr = 0; - if (speed >= 44100) { fcr1 = CMPCI_REG_SPDIF0_ENABLE; lcr = CMPCI_REG_XSPDIF_ENABLE; @@ -318,12 +316,12 @@ cmi_spdif_speed(struct cmi_info *cmi, int speed) { fcr1 = mcr = lcr = 0; } - cmi_partial_wr4(cmi, CMPCI_REG_FUNC_1, 0, - CMPCI_REG_SPDIF0_ENABLE, fcr1); cmi_partial_wr4(cmi, CMPCI_REG_MISC, 0, CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr); cmi_partial_wr4(cmi, CMPCI_REG_LEGACY_CTRL, 0, CMPCI_REG_XSPDIF_ENABLE, lcr); + cmi_partial_wr4(cmi, CMPCI_REG_FUNC_1, 0, + CMPCI_REG_SPDIF0_ENABLE, fcr1); } /* ------------------------------------------------------------------------- */