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Correct the polarity of the PPS assert and clear events with respect to the

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electrical signals on the serial port.  Virtually all devices which output a
PPS signal generate a brief higher-voltage pulse, the leading edge of which
is the on-time point.

Both DCD and CTS are active-low signals on the wire, meaning the assertion
of their status bits in the modem status register corresponds to the lower
voltage level on the wire.  So when the status bit transitions to not-set,
create a PPS assert event; when the status bit transitions to set, create a
PPS clear event.
This commit is contained in:
ian 2015-08-10 20:54:03 +00:00
parent ba06112c24
commit ebeb87c84e
1 changed files with 7 additions and 1 deletions
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8
sys/dev/uart/uart_core.c
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@ -320,12 +320,18 @@ uart_intr_sigchg(void *arg)
sig = UART_GETSIG(sc);
/*
* Time pulse counting support. Note that both CTS and DCD are
* active-low signals. The status bit is high to indicate that
* the signal on the line is low, which corresponds to a PPS
* clear event.
*/
if (sc->sc_pps.ppsparam.mode & PPS_CAPTUREBOTH) {
pps_sig = uart_pps_signal(sc->sc_pps_mode);
if (sig & SER_DELTA(pps_sig)) {
pps_capture(&sc->sc_pps);
pps_event(&sc->sc_pps, (sig & pps_sig) ?
PPS_CAPTUREASSERT : PPS_CAPTURECLEAR);
PPS_CAPTURECLEAR : PPS_CAPTUREASSERT);
}
}