typo: suppported.
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d9a48fc632
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@ -282,7 +282,7 @@ inet6_rth_space(int type, int segments)
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return (((segments * 2) + 1) << 3);
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/* FALLTHROUGH */
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default:
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return (0); /* type not suppported */
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return (0); /* type not supported */
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}
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}
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@ -848,7 +848,7 @@ enable_K6_wt_alloc(void)
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*/
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/*
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* The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
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* but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
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* but only the Cache Inhibit(CI) (bit 3 of TR12) is supported.
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* All other bits in TR12 have no effect on the processer's operation.
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* The I/O Trap Restart function (bit 9 of TR12) is always enabled
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* on the AMD-K6.
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@ -898,7 +898,7 @@ enable_K6_2_wt_alloc(void)
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*/
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/*
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* The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
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* but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
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* but only the Cache Inhibit(CI) (bit 3 of TR12) is supported.
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* All other bits in TR12 have no effect on the processer's operation.
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* The I/O Trap Restart function (bit 9 of TR12) is always enabled
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* on the AMD-K6.
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