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Merge ^/head r274961 through r276342.

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This commit is contained in:
Dimitry Andric 2014-12-28 20:02:06 +00:00
commit eca4d50aaa
32 changed files with 974 additions and 16171 deletions
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39
cddl/contrib/opensolaris/lib/libdtrace/common/dt_link.c
View File

@ -685,8 +685,8 @@ dump_elf64(dtrace_hdl_t *dtp, const dof_hdr_t *dof, int fd)
elf_file.ehdr.e_machine = EM_ARM;
#elif defined(__mips__)
elf_file.ehdr.e_machine = EM_MIPS;
#elif defined(__powerpc__)
elf_file.ehdr.e_machine = EM_PPC;
#elif defined(__powerpc64__)
elf_file.ehdr.e_machine = EM_PPC64;
#elif defined(__sparc)
elf_file.ehdr.e_machine = EM_SPARCV9;
#elif defined(__i386) || defined(__amd64)
@ -784,21 +784,32 @@ dump_elf64(dtrace_hdl_t *dtp, const dof_hdr_t *dof, int fd)
static int
dt_symtab_lookup(Elf_Data *data_sym, int nsym, uintptr_t addr, uint_t shn,
GElf_Sym *sym)
GElf_Sym *sym, int uses_funcdesc, Elf *elf)
{
int i, ret = -1;
Elf64_Addr symval;
Elf_Scn *opd_scn;
Elf_Data *opd_desc;
GElf_Sym s;
for (i = 0; i < nsym && gelf_getsym(data_sym, i, sym) != NULL; i++) {
if (GELF_ST_TYPE(sym->st_info) == STT_FUNC &&
shn == sym->st_shndx &&
sym->st_value <= addr &&
addr < sym->st_value + sym->st_size) {
if (GELF_ST_BIND(sym->st_info) == STB_GLOBAL)
return (0);
if (GELF_ST_TYPE(sym->st_info) == STT_FUNC) {
symval = sym->st_value;
if (uses_funcdesc) {
opd_scn = elf_getscn(elf, sym->st_shndx);
opd_desc = elf_rawdata(opd_scn, NULL);
symval =
*(uint64_t*)((char *)opd_desc->d_buf + symval);
}
if ((uses_funcdesc || shn == sym->st_shndx) &&
symval <= addr &&
addr < symval + sym->st_size) {
if (GELF_ST_BIND(sym->st_info) == STB_GLOBAL)
return (0);
ret = 0;
s = *sym;
ret = 0;
s = *sym;
}
}
}
@ -1375,7 +1386,8 @@ process_obj(dtrace_hdl_t *dtp, const char *obj, int *eprobesp)
continue;
if (dt_symtab_lookup(data_sym, isym, rela.r_offset,
shdr_rel.sh_info, &fsym) != 0) {
shdr_rel.sh_info, &fsym,
(emachine1 == EM_PPC64), elf) != 0) {
dt_strtab_destroy(strtab);
goto err;
}
@ -1536,7 +1548,8 @@ process_obj(dtrace_hdl_t *dtp, const char *obj, int *eprobesp)
p = strhyphenate(p + 3); /* strlen("___") */
if (dt_symtab_lookup(data_sym, isym, rela.r_offset,
shdr_rel.sh_info, &fsym) != 0)
shdr_rel.sh_info, &fsym,
(emachine1 == EM_PPC64), elf) != 0)
goto err;
if (fsym.st_name > data_str->d_size)

4
contrib/bsnmp/lib/snmpcrypto.c
View File

@ -366,7 +366,7 @@ snmp_pdu_decrypt(const struct snmp_pdu *pdu)
return (SNMP_CODE_OK);
}
int
enum snmp_code
snmp_passwd_to_keys(struct snmp_user *user, char *passwd __unused)
{
if (user->auth_proto == SNMP_AUTH_NOAUTH &&
@ -378,7 +378,7 @@ snmp_passwd_to_keys(struct snmp_user *user, char *passwd __unused)
return (SNMP_CODE_FAILED);
}
int
enum snmp_code
snmp_get_local_keys(struct snmp_user *user, uint8_t *eid __unused,
uint32_t elen __unused)
{

8
lib/libc/tests/hash/Makefile
View File

@ -1,8 +1,14 @@
# $FreeBSD$
.include <src.opts.mk>
TESTSDIR= ${TESTSBASE}/lib/libc/hash
NETBSD_ATF_TESTS_C= sha2_test
NETBSD_ATF_TESTS_C=
.if ${MK_OPENSSL} != "no"
NETBSD_ATF_TESTS_C+= sha2_test
.endif
NETBSD_ATF_TESTS_SH= hash_test

7
lib/ncurses/Makefile
View File

@ -3,4 +3,11 @@
SUBDIR= ncurses form menu panel \
ncursesw formw menuw panelw
SUBDIR_PARALLEL=
.for subdir in ${SUBDIR:Nncurses*:N*w}
SUBDIR_DEPEND_${subdir}= ncurses
SUBDIR_DEPEND_${subdir}w= ncursesw
.endfor
.include <bsd.subdir.mk>

2
libexec/rtld-elf/powerpc/reloc.c
View File

@ -483,7 +483,7 @@ reloc_jmpslot(Elf_Addr *wherep, Elf_Addr target, const Obj_Entry *defobj,
*/
offset = target - (Elf_Addr)wherep;
if (abs(offset) < 32*1024*1024) { /* inside 32MB? */
if (abs((int)offset) < 32*1024*1024) { /* inside 32MB? */
/* b value # branch directly */
*wherep = 0x48000000 | (offset & 0x03fffffc);
__syncicache(wherep, 4);

2
share/man/man7/build.7
View File

@ -24,7 +24,7 @@
.\"
.\" $FreeBSD$
.\"
.Dd June 25, 2014
.Dd December 18, 2014
.Dt BUILD 7
.Os
.Sh NAME

2
share/mk/bsd.progs.mk
View File

@ -43,7 +43,7 @@ PROG ?= $t
.if defined(PROG)
# just one of many
PROG_OVERRIDE_VARS += BINDIR DPSRCS MAN SRCS
PROG_VARS += CFLAGS CPPFLAGS CXXFLAGS DPADD DPLIBS LDADD LDFLAGS ${PROG_OVERRIDE_VARS}
PROG_VARS += CFLAGS CPPFLAGS CXXFLAGS DPADD DPLIBS LDADD LIBADD LDFLAGS ${PROG_OVERRIDE_VARS}
.for v in ${PROG_VARS:O:u}
.if empty(${PROG_OVERRIDE_VARS:M$v})
.if defined(${v}.${PROG})

1
share/mk/src.libnames.mk
View File

@ -110,6 +110,7 @@ _LIBRARIES= \
memstat \
mp \
nandfs \
ncurses \
ncursesw \
netgraph \
ngatm \

43
sys/amd64/ia32/ia32_sigtramp.S
View File

@ -86,34 +86,14 @@ ia32_osigcode:
* executed, we would have a window where the ring 0 code is
* executed with the wrong gsbase.
*
* Instead, reflect the lcall $7,$0 back to ring 3 trampoline
* which sets up the frame for int $0x80.
* Instead, set LDT descriptor 0 as code segment, which reflects
* the lcall $7,$0 back to ring 3 trampoline. The trampoline sets up
* the frame for int $0x80.
*/
ALIGN_TEXT
lcall_tramp:
.code64
/*
* There, we are in 64bit mode and need to return to 32bit.
* First, convert call frame from 64 to 32 bit format.
*/
pushq %rax
movl 16(%rsp),%eax
movl %eax,20(%rsp) /* ret %cs */
movl 8(%rsp),%eax
movl %eax,16(%rsp) /* ret %rip -> %eip */
popq %rax
addq $8,%rsp
/* Now return to 32bit */
pushq $0x33 /* _ucode32sel UPL */
callq 1f
1:
addq $2f-1b,(%rsp)
lretq
2:
/* Back in 32bit mode */
.code32
cmpl $SYS_vfork,%eax
je 4f
je 1f
pushl %ebp
movl %esp,%ebp
pushl 0x24(%ebp) /* arg 6 */
@ -122,21 +102,20 @@ lcall_tramp:
pushl 0x18(%ebp)
pushl 0x14(%ebp)
pushl 0x10(%ebp) /* arg 1 */
pushl 0xc(%ebp) /* gap */
subl $4,%esp /* gap */
int $0x80
leavel
3:
lretl
4:
1:
/*
* vfork handling is special and relies on the libc stub saving
* the return ip in %ecx. If vfork failed, then there is no
* child which can corrupt the frame created by call gate.
* the return ip in %ecx. Also, we assume that the call was done
* with ucode32 selector in %cs.
*/
int $0x80
jb 3b
addl $8,%esp
jmpl *%ecx
movl $0x33,4(%esp) /* GUCODE32_SEL | SEL_UPL */
movl %ecx,(%esp)
lretl
#endif
ALIGN_TEXT

39
sys/amd64/ia32/ia32_syscall.c
View File

@ -223,39 +223,28 @@ int
setup_lcall_gate(void)
{
struct i386_ldt_args uap;
struct user_segment_descriptor descs[2];
struct gate_descriptor *ssd;
struct user_segment_descriptor desc;
uint32_t lcall_addr;
int error;
bzero(&uap, sizeof(uap));
uap.start = 0;
uap.num = 2;
/*
* This is the easiest way to cut the space for system
* descriptor in ldt. Manually adjust the descriptor type to
* the call gate later.
*/
bzero(&descs[0], sizeof(descs));
descs[0].sd_type = SDT_SYSNULL;
descs[1].sd_type = SDT_SYSNULL;
error = amd64_set_ldt(curthread, &uap, descs);
uap.num = 1;
lcall_addr = curproc->p_sysent->sv_psstrings - sz_lcall_tramp;
bzero(&desc, sizeof(desc));
desc.sd_type = SDT_MEMERA;
desc.sd_dpl = SEL_UPL;
desc.sd_p = 1;
desc.sd_def32 = 1;
desc.sd_gran = 1;
desc.sd_lolimit = 0xffff;
desc.sd_hilimit = 0xf;
desc.sd_lobase = lcall_addr;
desc.sd_hibase = lcall_addr >> 24;
error = amd64_set_ldt(curthread, &uap, &desc);
if (error != 0)
return (error);
lcall_addr = curproc->p_sysent->sv_psstrings - sz_lcall_tramp;
mtx_lock(&dt_lock);
ssd = (struct gate_descriptor *)(curproc->p_md.md_ldt->ldt_base);
bzero(ssd, sizeof(*ssd));
ssd->gd_looffset = lcall_addr;
ssd->gd_hioffset = lcall_addr >> 16;
ssd->gd_selector = _ucodesel;
ssd->gd_type = SDT_SYSCGT;
ssd->gd_dpl = SEL_UPL;
ssd->gd_p = 1;
mtx_unlock(&dt_lock);
return (0);
}
#endif

29
sys/amd64/vmm/io/vatpic.c
View File

@ -73,6 +73,7 @@ struct atpic {
uint8_t request; /* Interrupt Request Register (IIR) */
uint8_t service; /* Interrupt Service (ISR) */
uint8_t mask; /* Interrupt Mask Register (IMR) */
uint8_t smm; /* special mask mode */
int acnt[8]; /* sum of pin asserts and deasserts */
int lowprio; /* lowest priority irq */
@ -131,8 +132,16 @@ vatpic_get_highest_isrpin(struct atpic *atpic)
ATPIC_PIN_FOREACH(pin, atpic, i) {
bit = (1 << pin);
if (atpic->service & bit)
return (pin);
if (atpic->service & bit) {
/*
* An IS bit that is masked by an IMR bit will not be
* cleared by a non-specific EOI in Special Mask Mode.
*/
if (atpic->smm && (atpic->mask & bit) != 0)
continue;
else
return (pin);
}
}
return (-1);
@ -153,6 +162,15 @@ vatpic_get_highest_irrpin(struct atpic *atpic)
if (atpic->sfn)
serviced &= ~(1 << 2);
/*
* In 'Special Mask Mode', when a mask bit is set in OCW1 it inhibits
* further interrupts at that level and enables interrupts from all
* other levels that are not masked. In other words the ISR has no
* bearing on the levels that can generate interrupts.
*/
if (atpic->smm)
serviced = 0;
ATPIC_PIN_FOREACH(pin, atpic, tmp) {
bit = 1 << pin;
@ -261,6 +279,7 @@ vatpic_icw1(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
atpic->lowprio = 7;
atpic->rd_cmd_reg = 0;
atpic->poll = 0;
atpic->smm = 0;
if ((val & ICW1_SNGL) != 0) {
VATPIC_CTR0(vatpic, "vatpic cascade mode required");
@ -375,8 +394,10 @@ vatpic_ocw3(struct vatpic *vatpic, struct atpic *atpic, uint8_t val)
VATPIC_CTR1(vatpic, "atpic ocw3 0x%x", val);
if (val & OCW3_ESMM) {
VATPIC_CTR0(vatpic, "atpic special mask mode not implemented");
return (-1);
atpic->smm = val & OCW3_SMM ? 1 : 0;
VATPIC_CTR2(vatpic, "%s atpic special mask mode %s",
master_atpic(vatpic, atpic) ? "master" : "slave",
atpic->smm ? "enabled" : "disabled");
}
if (val & OCW3_RR) {

200
sys/arm/arm/cpu_asm-v6.S Normal file
View File

@ -0,0 +1,200 @@
/*-
* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
* Copyright 2014 Michal Meloun <meloun@miracle.cz>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <machine/acle-compat.h>
#include <machine/asm.h>
#include <machine/asmacros.h>
#include <machine/armreg.h>
#include <machine/sysreg.h>
#if __ARM_ARCH >= 7
/*
* Define cache functions used by startup code, which counts on the fact that
* only r0-r4,r12 (ip) are modified and no stack space is used. This set
* of function must be called with interrupts disabled and don't follow
* ARM ABI (cannot be called form C code.
* Moreover, it works only with caches integrated to CPU (accessible via CP15).
*/
/* Invalidate D cache to PoC. (aka all cache levels)*/
ASENTRY(dcache_inv_poc_all)
mrc CP15_CLIDR(r0)
ands r0, r0, #0x07000000
mov r0, r0, lsr #23 /* Get LoC (naturally aligned) */
beq 4f
1: mcr CP15_CSSELR(r0) /* set cache level */
isb
mrc CP15_CCSIDR(r0) /* read CCSIDR */
ubfx r2, r0, #13, #15 /* get num sets - 1 from CCSIDR */
ubfx r3, r0, #3, #10 /* get num ways - 1 from CCSIDR */
clz r1, r3 /* number of bits to MSB of way */
lsl r3, r3, r1 /* shift into position */
mov ip, #1
lsl ip, ip, r1 /* ip now contains the way decr */
ubfx r0, r0, #0, #3 /* get linesize from CCSIDR */
add r0, r0, #4 /* apply bias */
lsl r2, r2, r0 /* shift sets by log2(linesize) */
add r3, r3, r2 /* merge numsets - 1 with numways - 1 */
sub ip, ip, r2 /* subtract numsets - 1 from way decr */
mov r1, #1
lsl r1, r1, r0 /* r1 now contains the set decr */
mov r2, ip /* r2 now contains set way decr */
/* r3 = ways/sets, r2 = way decr, r1 = set decr, r0 and ip are free */
2: mcr CP15_DCISW(r3) /* invalidate line */
movs r0, r3 /* get current way/set */
beq 3f /* at 0 means we are done */
movs r0, r0, lsl #10 /* clear way bits leaving only set bits*/
subne r3, r3, r1 /* non-zero?, decrement set */
subeq r3, r3, r2 /* zero?, decrement way and restore set count */
b 2b
3:
mrc CP15_CSSELR(r0) /* get cache level */
add r0, r0, #2 /* next level */
mrc CP15_CLIDR(r1)
ands r1, r1, #0x07000000
mov r1, r1, lsr #23 /* Get LoC (naturally aligned) */
cmp r1, r0
bgt 1b
4: dsb /* wait for stores to finish */
mov r0, #0
mcr CP15_CSSELR(r0)
isb
bx lr
END(dcache_inv_poc_all)
/* Invalidate D cache to PoU. (aka L1 cache only)*/
ASENTRY(dcache_inv_pou_all)
mrc CP15_CLIDR(r0)
ands r0, r0, #0x07000000
mov r0, r0, lsr #26 /* Get LoUU (naturally aligned) */
beq 4f
1: mcr CP15_CSSELR(r0) /* set cache level */
isb
mrc CP15_CCSIDR(r0) /* read CCSIDR */
ubfx r2, r0, #13, #15 /* get num sets - 1 from CCSIDR */
ubfx r3, r0, #3, #10 /* get num ways - 1 from CCSIDR */
clz r1, r3 /* number of bits to MSB of way */
lsl r3, r3, r1 /* shift into position */
mov ip, #1
lsl ip, ip, r1 /* ip now contains the way decr */
ubfx r0, r0, #0, #3 /* get linesize from CCSIDR */
add r0, r0, #4 /* apply bias */
lsl r2, r2, r0 /* shift sets by log2(linesize) */
add r3, r3, r2 /* merge numsets - 1 with numways - 1 */
sub ip, ip, r2 /* subtract numsets - 1 from way decr */
mov r1, #1
lsl r1, r1, r0 /* r1 now contains the set decr */
mov r2, ip /* r2 now contains set way decr */
/* r3 = ways/sets, r2 = way decr, r1 = set decr, r0 and ip are free */
2: mcr CP15_DCISW(r3) /* clean & invalidate line */
movs r0, r3 /* get current way/set */
beq 3f /* at 0 means we are done */
movs r0, r0, lsl #10 /* clear way bits leaving only set bits*/
subne r3, r3, r1 /* non-zero?, decrement set */
subeq r3, r3, r2 /* zero?, decrement way and restore set count */
b 2b
3:
mrc CP15_CSSELR(r0) /* get cache level */
add r0, r0, #2 /* next level */
mrc CP15_CLIDR(r1)
ands r1, r1, #0x07000000
mov r1, r1, lsr #26 /* Get LoUU (naturally aligned) */
cmp r1, r0
bgt 1b
4: dsb /* wait for stores to finish */
mov r0, #0
mcr CP15_CSSELR(r0)
bx lr
END(dcache_inv_pou_all)
/* Write back and Invalidate D cache to PoC. */
ASENTRY(dcache_wbinv_poc_all)
mrc CP15_CLIDR(r0)
ands r0, r0, #0x07000000
mov r0, r0, lsr #23 /* Get LoC (naturally aligned) */
beq 4f
1: mcr CP15_CSSELR(r0) /* set cache level */
isb
mrc CP15_CCSIDR(r0) /* read CCSIDR */
ubfx r2, r0, #13, #15 /* get num sets - 1 from CCSIDR */
ubfx r3, r0, #3, #10 /* get num ways - 1 from CCSIDR */
clz r1, r3 /* number of bits to MSB of way */
lsl r3, r3, r1 /* shift into position */
mov ip, #1
lsl ip, ip, r1 /* ip now contains the way decr */
ubfx r0, r0, #0, #3 /* get linesize from CCSIDR */
add r0, r0, #4 /* apply bias */
lsl r2, r2, r0 /* shift sets by log2(linesize) */
add r3, r3, r2 /* merge numsets - 1 with numways - 1 */
sub ip, ip, r2 /* subtract numsets - 1 from way decr */
mov r1, #1
lsl r1, r1, r0 /* r1 now contains the set decr */
mov r2, ip /* r2 now contains set way decr */
/* r3 = ways/sets, r2 = way decr, r1 = set decr, r0 and ip are free */
2: mcr CP15_DCCISW(r3) /* clean & invalidate line */
movs r0, r3 /* get current way/set */
beq 3f /* at 0 means we are done */
movs r0, r0, lsl #10 /* clear way bits leaving only set bits*/
subne r3, r3, r1 /* non-zero?, decrement set */
subeq r3, r3, r2 /* zero?, decrement way and restore set count */
b 2b
3:
mrc CP15_CSSELR(r0) /* get cache level */
add r0, r0, #2 /* next level */
mrc CP15_CLIDR(r1)
ands r1, r1, #0x07000000
mov r1, r1, lsr #23 /* Get LoC (naturally aligned) */
cmp r1, r0
bgt 1b
4: dsb /* wait for stores to finish */
mov r0, #0
mcr CP15_CSSELR(r0)
bx lr
END(dcache_wbinv_poc_all)
#endif /* __ARM_ARCH >= 7 */

121
sys/arm/arm/cpuinfo.c Normal file
View File

@ -0,0 +1,121 @@
/*-
* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
* Copyright 2014 Michal Meloun <meloun@miracle.cz>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <machine/cpuinfo.h>
#include <machine/cpu-v6.h>
struct cpuinfo cpuinfo;
/* Read and parse CPU id scheme */
void
cpuinfo_init(void)
{
cpuinfo.midr = cp15_midr_get();
/* Test old version id schemes first */
if ((cpuinfo.midr & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) {
if (CPU_ID_ISOLD(cpuinfo.midr)) {
/* obsolete ARMv2 or ARMv3 CPU */
cpuinfo.midr = 0;
return;
}
if (CPU_ID_IS7(cpuinfo.midr)) {
if ((cpuinfo.midr & (1 << 23)) == 0) {
/* obsolete ARMv3 CPU */
cpuinfo.midr = 0;
return;
}
/* ARMv4T CPU */
cpuinfo.architecture = 1;
cpuinfo.revision = (cpuinfo.midr >> 16) & 0x7F;
}
} else {
/* must be new id scheme */
cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F;
cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F;
}
/* Parse rest of MIDR */
cpuinfo.implementer = (cpuinfo.midr >> 24) & 0xFF;
cpuinfo.part_number = (cpuinfo.midr >> 4) & 0xFFF;
cpuinfo.patch = cpuinfo.midr & 0x0F;
/* CP15 c0,c0 regs 0-7 exist on all CPUs (although aliased with MIDR) */
cpuinfo.ctr = cp15_ctr_get();
cpuinfo.tcmtr = cp15_tcmtr_get();
cpuinfo.tlbtr = cp15_tlbtr_get();
cpuinfo.mpidr = cp15_mpidr_get();
cpuinfo.revidr = cp15_revidr_get();
/* if CPU is not v7 cpu id scheme */
if (cpuinfo.architecture != 0xF)
return;
cpuinfo.id_pfr0 = cp15_id_pfr0_get();
cpuinfo.id_pfr1 = cp15_id_pfr1_get();
cpuinfo.id_dfr0 = cp15_id_dfr0_get();
cpuinfo.id_afr0 = cp15_id_afr0_get();
cpuinfo.id_mmfr0 = cp15_id_mmfr0_get();
cpuinfo.id_mmfr1 = cp15_id_mmfr1_get();
cpuinfo.id_mmfr2 = cp15_id_mmfr2_get();
cpuinfo.id_mmfr3 = cp15_id_mmfr3_get();
cpuinfo.id_isar0 = cp15_id_isar0_get();
cpuinfo.id_isar1 = cp15_id_isar1_get();
cpuinfo.id_isar2 = cp15_id_isar2_get();
cpuinfo.id_isar3 = cp15_id_isar3_get();
cpuinfo.id_isar4 = cp15_id_isar4_get();
cpuinfo.id_isar5 = cp15_id_isar5_get();
/* Not yet - CBAR only exist on ARM SMP Cortex A CPUs
cpuinfo.cbar = cp15_cbar_get();
*/
/* Test if revidr is implemented */
if (cpuinfo.revidr == cpuinfo.midr)
cpuinfo.revidr = 0;
/* parsed bits of above registers */
/* id_mmfr0 */
cpuinfo.outermost_shareability = (cpuinfo.id_mmfr0 >> 8) & 0xF;
cpuinfo.shareability_levels = (cpuinfo.id_mmfr0 >> 12) & 0xF;
cpuinfo.auxiliary_registers = (cpuinfo.id_mmfr0 >> 20) & 0xF;
cpuinfo.innermost_shareability = (cpuinfo.id_mmfr0 >> 28) & 0xF;
/* id_mmfr2 */
cpuinfo.mem_barrier = (cpuinfo.id_mmfr2 >> 20) & 0xF;
/* id_mmfr3 */
cpuinfo.coherent_walk = (cpuinfo.id_mmfr3 >> 20) & 0xF;
cpuinfo.maintenance_broadcast =(cpuinfo.id_mmfr3 >> 12) & 0xF;
/* id_pfr1 */
cpuinfo.generic_timer_ext = (cpuinfo.id_pfr1 >> 16) & 0xF;
cpuinfo.virtualization_ext = (cpuinfo.id_pfr1 >> 12) & 0xF;
cpuinfo.security_ext = (cpuinfo.id_pfr1 >> 4) & 0xF;
}

3
sys/arm/arm/machdep.c
View File

@ -90,6 +90,7 @@ __FBSDID("$FreeBSD$");
#include <machine/armreg.h>
#include <machine/atags.h>
#include <machine/cpu.h>
#include <machine/cpuinfo.h>
#include <machine/devmap.h>
#include <machine/frame.h>
#include <machine/intr.h>
@ -1064,6 +1065,8 @@ initarm(struct arm_boot_params *abp)
arm_physmem_kernaddr = abp->abp_physaddr;
memsize = 0;
cpuinfo_init();
set_cpufuncs();
/*

52
sys/arm/broadcom/bcm2835/bcm2835_bsc.c
View File

@ -53,6 +53,7 @@ __FBSDID("$FreeBSD$");
#include "iicbus_if.h"
static void bcm_bsc_intr(void *);
static int bcm_bsc_detach(device_t);
static void
bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask,
@ -72,10 +73,8 @@ bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS)
{
struct bcm_bsc_softc *sc;
uint32_t clk;
int error;
sc = (struct bcm_bsc_softc *)arg1;
BCM_BSC_LOCK(sc);
clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
BCM_BSC_UNLOCK(sc);
@ -83,20 +82,8 @@ bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS)
if (clk == 0)
clk = 32768;
clk = BCM_BSC_CORE_CLK / clk;
error = sysctl_handle_int(oidp, &clk, sizeof(clk), req);
if (error != 0 || req->newptr == NULL)
return (error);
clk = BCM_BSC_CORE_CLK / clk;
if (clk % 2)
clk--;
if (clk > 0xffff)
clk = 0xffff;
BCM_BSC_LOCK(sc);
BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, clk);
BCM_BSC_UNLOCK(sc);
return (0);
return (sysctl_handle_int(oidp, &clk, 0, req));
}
static int
@ -192,7 +179,7 @@ bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc)
ctx = device_get_sysctl_ctx(sc->sc_dev);
tree_node = device_get_sysctl_tree(sc->sc_dev);
tree = SYSCTL_CHILDREN(tree_node);
SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock",
SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency",
CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency");
SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch",
@ -307,7 +294,11 @@ bcm_bsc_attach(device_t dev)
bcm_bsc_reset(sc);
BCM_BSC_UNLOCK(sc);
device_add_child(dev, "iicbus", -1);
sc->sc_iicbus = device_add_child(dev, "iicbus", -1);
if (sc->sc_iicbus == NULL) {
bcm_bsc_detach(dev);
return (ENXIO);
}
return (bus_generic_attach(dev));
}
@ -462,29 +453,16 @@ static int
bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
{
struct bcm_bsc_softc *sc;
uint32_t freq;
uint32_t busfreq;
sc = device_get_softc(dev);
BCM_BSC_LOCK(sc);
bcm_bsc_reset(sc);
freq = 0;
switch (speed) {
case IIC_SLOW:
freq = BCM_BSC_SLOW;
break;
case IIC_FAST:
freq = BCM_BSC_FAST;
break;
case IIC_FASTEST:
freq = BCM_BSC_FASTEST;
break;
case IIC_UNKNOWN:
default:
/* Reuse last frequency. */
break;
}
if (freq != 0)
BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / freq);
if (sc->sc_iicbus == NULL)
busfreq = 100000;
else
busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq);
BCM_BSC_UNLOCK(sc);
return (IIC_ENOADDR);

5
sys/arm/broadcom/bcm2835/bcm2835_bscvar.h
View File

@ -41,6 +41,7 @@ struct {
struct bcm_bsc_softc {
device_t sc_dev;
device_t sc_iicbus;
struct mtx sc_mtx;
struct resource * sc_mem_res;
struct resource * sc_irq_res;
@ -56,10 +57,6 @@ struct bcm_bsc_softc {
#define BCM_I2C_READ 0x02
#define BCM_I2C_ERROR 0x04
#define BCM_BSC_SLOW 10000 /* 10 kHz. */
#define BCM_BSC_FAST 50000 /* 50 kHz. */
#define BCM_BSC_FASTEST 100000 /* 100 kHz. */
#define BCM_BSC_WRITE(_sc, _off, _val) \
bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
#define BCM_BSC_READ(_sc, _off) \

26
sys/arm/broadcom/bcm2835/bcm2835_mbox.c
View File

@ -31,25 +31,16 @@ __FBSDID("$FreeBSD$");
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/module.h>
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/rman.h>
#include <sys/sema.h>
#include <sys/timeet.h>
#include <sys/timetc.h>
#include <sys/watchdog.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/intr.h>
#include <dev/fdt/fdt_common.h>
#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include <machine/bus.h>
#include <machine/fdt.h>
#include <arm/broadcom/bcm2835/bcm2835_mbox.h>
#include "mbox_if.h"
@ -188,25 +179,21 @@ bcm_mbox_attach(device_t dev)
static int
bcm_mbox_write(device_t dev, int chan, uint32_t data)
{
int limit = 20000;
int limit = 1000;
struct bcm_mbox_softc *sc = device_get_softc(dev);
dprintf("bcm_mbox_write: chan %d, data %08x\n", chan, data);
MBOX_LOCK(sc);
while ((mbox_read_4(sc, REG_STATUS) & STATUS_FULL) && limit--) {
DELAY(2);
}
while ((mbox_read_4(sc, REG_STATUS) & STATUS_FULL) && --limit)
DELAY(5);
if (limit == 0) {
printf("bcm_mbox_write: STATUS_FULL stuck");
MBOX_UNLOCK(sc);
return (EAGAIN);
}
mbox_write_4(sc, REG_WRITE, MBOX_MSG(chan, data));
MBOX_UNLOCK(sc);
return (0);
}
@ -254,4 +241,3 @@ static driver_t bcm_mbox_driver = {
static devclass_t bcm_mbox_devclass;
DRIVER_MODULE(mbox, simplebus, bcm_mbox_driver, bcm_mbox_devclass, 0, 0);

396
sys/arm/include/cpu-v6.h Normal file
View File

@ -0,0 +1,396 @@
/*-
* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
* Copyright 2014 Michal Meloun <meloun@miracle.cz>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef MACHINE_CPU_V6_H
#define MACHINE_CPU_V6_H
#include "machine/atomic.h"
#include "machine/cpufunc.h"
#include "machine/cpuinfo.h"
#include "machine/sysreg.h"
#define CPU_ASID_KERNEL 0
/*
* Macros to generate CP15 (system control processor) read/write functions.
*/
#define _FX(s...) #s
#define _RF0(fname, aname...) \
static __inline register_t \
fname(void) \
{ \
register_t reg; \
__asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \
return(reg); \
}
#define _WF0(fname, aname...) \
static __inline void \
fname(void) \
{ \
__asm __volatile("mcr\t" _FX(aname)); \
}
#define _WF1(fname, aname...) \
static __inline void \
fname(register_t reg) \
{ \
__asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \
}
/*
* Raw CP15 maintenance operations
* !!! not for external use !!!
*/
/* TLB */
_WF0(_CP15_TLBIALL, CP15_TLBIALL) /* Invalidate entire unified TLB */
#if __ARM_ARCH >= 7 && defined SMP
_WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS) /* Invalidate entire unified TLB IS */
#endif
_WF1(_CP15_TLBIASID, CP15_TLBIASID(%0)) /* Invalidate unified TLB by ASID */
#if __ARM_ARCH >= 7 && defined SMP
_WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0)) /* Invalidate unified TLB by ASID IS */
#endif
_WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0)) /* Invalidate unified TLB by MVA, all ASID */
#if __ARM_ARCH >= 7 && defined SMP
_WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0)) /* Invalidate unified TLB by MVA, all ASID IS */
#endif
_WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0)) /* Invalidate unified TLB by MVA */
_WF1(_CP15_TTB_SET, CP15_TTBR0(%0))
/* Cache and Branch predictor */
_WF0(_CP15_BPIALL, CP15_BPIALL) /* Branch predictor invalidate all */
#if __ARM_ARCH >= 7 && defined SMP
_WF0(_CP15_BPIALLIS, CP15_BPIALLIS) /* Branch predictor invalidate all IS */
#endif
_WF1(_CP15_BPIMVA, CP15_BPIMVA(%0)) /* Branch predictor invalidate by MVA */
_WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0)) /* Data cache clean and invalidate by MVA PoC */
_WF1(_CP15_DCCISW, CP15_DCCISW(%0)) /* Data cache clean and invalidate by set/way */
_WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0)) /* Data cache clean by MVA PoC */
#if __ARM_ARCH >= 7
_WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0)) /* Data cache clean by MVA PoU */
#endif
_WF1(_CP15_DCCSW, CP15_DCCSW(%0)) /* Data cache clean by set/way */
_WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0)) /* Data cache invalidate by MVA PoC */
_WF1(_CP15_DCISW, CP15_DCISW(%0)) /* Data cache invalidate by set/way */
_WF0(_CP15_ICIALLU, CP15_ICIALLU) /* Instruction cache invalidate all PoU */
#if __ARM_ARCH >= 7 && defined SMP
_WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS) /* Instruction cache invalidate all PoU IS */
#endif
_WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0)) /* Instruction cache invalidate */
/*
* Publicly accessible functions
*/
/* Various control registers */
_RF0(cp15_dfsr_get, CP15_DFSR(%0))
_RF0(cp15_ifsr_get, CP15_IFSR(%0))
_WF1(cp15_prrr_set, CP15_PRRR(%0))
_WF1(cp15_nmrr_set, CP15_NMRR(%0))
_RF0(cp15_ttbr_get, CP15_TTBR0(%0))
_RF0(cp15_dfar_get, CP15_DFAR(%0))
#if __ARM_ARCH >= 7
_RF0(cp15_ifar_get, CP15_IFAR(%0))
#endif
/*CPU id registers */
_RF0(cp15_midr_get, CP15_MIDR(%0))
_RF0(cp15_ctr_get, CP15_CTR(%0))
_RF0(cp15_tcmtr_get, CP15_TCMTR(%0))
_RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
_RF0(cp15_mpidr_get, CP15_MPIDR(%0))
_RF0(cp15_revidr_get, CP15_REVIDR(%0))
_RF0(cp15_aidr_get, CP15_AIDR(%0))
_RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0))
_RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0))
_RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0))
_RF0(cp15_id_afr0_get, CP15_ID_AFR0(%0))
_RF0(cp15_id_mmfr0_get, CP15_ID_MMFR0(%0))
_RF0(cp15_id_mmfr1_get, CP15_ID_MMFR1(%0))
_RF0(cp15_id_mmfr2_get, CP15_ID_MMFR2(%0))
_RF0(cp15_id_mmfr3_get, CP15_ID_MMFR3(%0))
_RF0(cp15_id_isar0_get, CP15_ID_ISAR0(%0))
_RF0(cp15_id_isar1_get, CP15_ID_ISAR1(%0))
_RF0(cp15_id_isar2_get, CP15_ID_ISAR2(%0))
_RF0(cp15_id_isar3_get, CP15_ID_ISAR3(%0))
_RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0))
_RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0))
_RF0(cp15_cbar_get, CP15_CBAR(%0))
#undef _FX
#undef _RF0
#undef _WF0
#undef _WF1
/*
* TLB maintenance operations.
*/
/* Local (i.e. not broadcasting ) operations. */
/* Flush all TLB entries (even global). */
static __inline void
tlb_flush_all_local(void)
{
dsb();
_CP15_TLBIALL();
dsb();
}
/* Flush all not global TLB entries. */
static __inline void
tlb_flush_all_ng_local(void)
{
dsb();
_CP15_TLBIASID(CPU_ASID_KERNEL);
dsb();
}
/* Flush single TLB entry (even global). */
static __inline void
tlb_flush_local(vm_offset_t sva)
{
dsb();
_CP15_TLBIMVA((sva & ~PAGE_MASK ) | CPU_ASID_KERNEL);
dsb();
}
/* Flush range of TLB entries (even global). */
static __inline void
tlb_flush_range_local(vm_offset_t sva, vm_size_t size)
{
vm_offset_t va;
vm_offset_t eva = sva + size;
dsb();
for (va = sva; va < eva; va += PAGE_SIZE)
_CP15_TLBIMVA((va & ~PAGE_MASK ) | CPU_ASID_KERNEL);
dsb();
}
/* Broadcasting operations. */
#ifndef SMP
#define tlb_flush_all() tlb_flush_all_local()
#define tlb_flush_all_ng() tlb_flush_all_ng_local()
#define tlb_flush(sva) tlb_flush_local(sva)
#define tlb_flush_range(sva, size) tlb_flush_range_local(sva, size)
#else /* SMP */
static __inline void
tlb_flush_all(void)
{
dsb();
_CP15_TLBIALLIS();
dsb();
}
static __inline void
tlb_flush_all_ng(void)
{
dsb();
_CP15_TLBIASIDIS(CPU_ASID_KERNEL);
dsb();
}
static __inline void
tlb_flush(vm_offset_t sva)
{
dsb();
_CP15_TLBIMVAAIS(sva);
dsb();
}
static __inline void
tlb_flush_range(vm_offset_t sva, vm_size_t size)
{
vm_offset_t va;
vm_offset_t eva = sva + size;
dsb();
for (va = sva; va < eva; va += PAGE_SIZE)
_CP15_TLBIMVAAIS(va);
dsb();
}
#endif /* SMP */
/*
* Cache maintenance operations.
*/
/* Sync I and D caches to PoU */
static __inline void
icache_sync(vm_offset_t sva, vm_size_t size)
{
vm_offset_t va;
vm_offset_t eva = sva + size;
dsb();
for (va = sva; va < eva; va += arm_dcache_align) {
#ifdef SMP
_CP15_DCCMVAU(va);
#else
_CP15_DCCMVAC(va);
#endif
}
dsb();
#ifdef SMP
_CP15_ICIALLUIS();
#else
_CP15_ICIALLU();
#endif
dsb();
isb();
}
/* Invalidate I cache */
static __inline void
icache_inv_all(void)
{
#ifdef SMP
_CP15_ICIALLUIS();
#else
_CP15_ICIALLU();
#endif
dsb();
isb();
}
/* Write back D-cache to PoU */
static __inline void
dcache_wb_pou(vm_offset_t sva, vm_size_t size)
{
vm_offset_t va;
vm_offset_t eva = sva + size;
dsb();
for (va = sva; va < eva; va += arm_dcache_align) {
#ifdef SMP
_CP15_DCCMVAU(va);
#else
_CP15_DCCMVAC(va);
#endif
}
dsb();
}
/* Invalidate D-cache to PoC */
static __inline void
dcache_inv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
{
vm_offset_t va;
vm_offset_t eva = sva + size;
/* invalidate L1 first */
for (va = sva; va < eva; va += arm_dcache_align) {
_CP15_DCIMVAC(va);
}
dsb();
/* then L2 */
cpu_l2cache_inv_range(pa, size);
dsb();
/* then L1 again */
for (va = sva; va < eva; va += arm_dcache_align) {
_CP15_DCIMVAC(va);
}
dsb();
}
/* Write back D-cache to PoC */
static __inline void
dcache_wb_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
{
vm_offset_t va;
vm_offset_t eva = sva + size;
dsb();
for (va = sva; va < eva; va += arm_dcache_align) {
_CP15_DCCMVAC(va);
}
dsb();
cpu_l2cache_wb_range(pa, size);
}
/* Write back and invalidate D-cache to PoC */
static __inline void
dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
{
vm_offset_t va;
vm_offset_t eva = sva + size;
dsb();
/* write back L1 first */
for (va = sva; va < eva; va += arm_dcache_align) {
_CP15_DCCMVAC(va);
}
dsb();
/* then write back and invalidate L2 */
cpu_l2cache_wbinv_range(pa, size);
/* then invalidate L1 */
for (va = sva; va < eva; va += arm_dcache_align) {
_CP15_DCIMVAC(va);
}
dsb();
}
/* Set TTB0 register */
static __inline void
cp15_ttbr_set(uint32_t reg)
{
dsb();
_CP15_TTB_SET(reg);
dsb();
_CP15_BPIALL();
dsb();
isb();
tlb_flush_all_ng_local();
}
#endif /* !MACHINE_CPU_V6_H */

1
sys/arm/include/cpufunc.h
View File

@ -563,7 +563,6 @@ void xscalec3_context_switch (void);
#endif /* CPU_XSCALE_81342 */
#define tlb_flush cpu_tlb_flushID
#define setttb cpu_setttb
#define drain_writebuf cpu_drain_writebuf

91
sys/arm/include/cpuinfo.h Normal file
View File

@ -0,0 +1,91 @@
/*-
* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
* Copyright 2014 Michal Meloun <meloun@miracle.cz>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_CPUINFO_H_
#define _MACHINE_CPUINFO_H_
#include <sys/types.h>
struct cpuinfo {
/* raw id registers */
uint32_t midr;
uint32_t ctr;
uint32_t tcmtr;
uint32_t tlbtr;
uint32_t mpidr;
uint32_t revidr;
uint32_t id_pfr0;
uint32_t id_pfr1;
uint32_t id_dfr0;
uint32_t id_afr0;
uint32_t id_mmfr0;
uint32_t id_mmfr1;
uint32_t id_mmfr2;
uint32_t id_mmfr3;
uint32_t id_isar0;
uint32_t id_isar1;
uint32_t id_isar2;
uint32_t id_isar3;
uint32_t id_isar4;
uint32_t id_isar5;
uint32_t cbar;
/* Parsed bits of above registers... */
/* midr */
int implementer;
int revision;
int architecture;
int part_number;
int patch;
/* id_mmfr0 */
int outermost_shareability;
int shareability_levels;
int auxiliary_registers;
int innermost_shareability;
/* id_mmfr1 */
int mem_barrier;
/* id_mmfr3 */
int coherent_walk;
int maintenance_broadcast;
/* id_pfr1 */
int generic_timer_ext;
int virtualization_ext;
int security_ext;
};
extern struct cpuinfo cpuinfo;
void cpuinfo_init(void);
#endif /* _MACHINE_CPUINFO_H_ */

3
sys/arm/ti/ti_gpio.c
View File

@ -334,7 +334,7 @@ static int
ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin)
{
if (pin > sc->sc_maxpin ||
if (pin >= sc->sc_maxpin ||
TI_GPIO_BANK(pin) >= ti_max_gpio_banks() ||
sc->sc_mem_res[TI_GPIO_BANK(pin)] == NULL) {
return (EINVAL);
@ -755,6 +755,7 @@ ti_gpio_attach(device_t dev)
sc->sc_dev = dev;
TI_GPIO_LOCK_INIT(sc);
ti_gpio_pin_max(dev, &sc->sc_maxpin);
sc->sc_maxpin++;
/* There are up to 6 different GPIO register sets located in different
* memory areas on the chip. The memory range should have been set for

34
sys/arm/ti/ti_i2c.c
View File

@ -473,38 +473,6 @@ out:
return (err);
}
/**
* ti_i2c_callback - as we only provide iicbus_transfer() interface
* we don't need to implement the serialization here.
* @dev: i2c device handle
*
*
*
* LOCKING:
* Called from timer context
*
* RETURNS:
* EH_HANDLED or EH_NOT_HANDLED
*/
static int
ti_i2c_callback(device_t dev, int index, caddr_t data)
{
int error = 0;
switch (index) {
case IIC_REQUEST_BUS:
break;
case IIC_RELEASE_BUS:
break;
default:
error = EINVAL;
}
return (error);
}
static int
ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed)
{
@ -955,7 +923,7 @@ static device_method_t ti_i2c_methods[] = {
DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node),
/* iicbus interface */
DEVMETHOD(iicbus_callback, ti_i2c_callback),
DEVMETHOD(iicbus_callback, iicbus_null_callback),
DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset),
DEVMETHOD(iicbus_transfer, ti_i2c_transfer),

5
sys/boot/common/loader.8
View File

@ -671,8 +671,9 @@ Overrides the compile-time set value of
or the preset default of 512.
Must be a power of 2.
.It Va twiddle_divisor
Throttles the output of the `twiddle' I/O progress indicator displayed
while loading the kernel and modules.
Throttles the output of the
.Sq twiddle
I/O progress indicator displayed while loading the kernel and modules.
This is useful on slow serial consoles where the time spent waiting for
these characters to be written can add up to many seconds.
The default is 1 (full speed); a value of 2 spins half as fast, and so on.

4
sys/conf/files
View File

@ -1731,7 +1731,7 @@ iwn6000g2afw.fwo optional iwn6000g2afw | iwnfw \
no-implicit-rule \
clean "iwn6000g2afw.fwo"
iwn6000g2a.fw optional iwn6000g2afw | iwnfw \
dependency "$S/contrib/dev/iwn/iwlwifi-6000g2a-17.168.5.2.fw.uu" \
dependency "$S/contrib/dev/iwn/iwlwifi-6000g2a-18.168.6.1.fw.uu" \
compile-with "${NORMAL_FW}" \
no-obj no-implicit-rule \
clean "iwn6000g2a.fw"
@ -1745,7 +1745,7 @@ iwn6000g2bfw.fwo optional iwn6000g2bfw | iwnfw \
no-implicit-rule \
clean "iwn6000g2bfw.fwo"
iwn6000g2b.fw optional iwn6000g2bfw | iwnfw \
dependency "$S/contrib/dev/iwn/iwlwifi-6000g2b-17.168.5.2.fw.uu" \
dependency "$S/contrib/dev/iwn/iwlwifi-6000g2b-18.168.6.1.fw.uu" \
compile-with "${NORMAL_FW}" \
no-obj no-implicit-rule \
clean "iwn6000g2b.fw"

2
sys/conf/files.arm
View File

@ -11,6 +11,8 @@ arm/arm/copystr.S standard
arm/arm/cpufunc.c standard
arm/arm/cpufunc_asm.S standard
arm/arm/cpufunc_asm_armv4.S standard
arm/arm/cpuinfo.c standard
arm/arm/cpu_asm-v6.S optional armv6
arm/arm/db_disasm.c optional ddb
arm/arm/db_interface.c optional ddb
arm/arm/db_trace.c optional ddb

7833
sys/contrib/dev/iwn/iwlwifi-6000g2a-17.168.5.2.fw.uu
View File

File diff suppressed because it is too large Load Diff

8128
sys/contrib/dev/iwn/iwlwifi-6000g2b-17.168.5.2.fw.uu
View File

File diff suppressed because it is too large Load Diff

6
sys/dev/bce/if_bcefw.h
View File

@ -7997,7 +7997,7 @@ const u32 bce_TPAT_b09FwBss[(0x12b4/4) + 1] = { 0x0 };
const u32 bce_TPAT_b09FwSbss[(0x3c/4) + 1] = { 0x0 };
const u32 bce_TPAT_b09FwSdata[(0x0/4) + 1] = { 0x0 };
int bce_COM_b09FwReleaseMajor = 0x6;
int bce_COM_b09FwReleaseMinor = 0x0;
int bce_COM_b09FwReleaseFix = 0x11;
@ -11727,8 +11727,8 @@ const u32 bce_RXP_b09FwText[(0x9090/4) + 1] = {
0x90cf0009, 0x240d0004, 0x31ee00ff, 0x11cdfd85,
0x24020001, 0x3c010801, 0xa022950d, 0xa002154,
0x0, 0x0 };
u32 bce_RXP_b09FwData[(0x0/4) + 1] = { 0x0 };
u32 bce_RXP_b09FwRodata[(0x33c/4) + 1] = {
const u32 bce_RXP_b09FwData[(0x0/4) + 1] = { 0x0 };
const u32 bce_RXP_b09FwRodata[(0x33c/4) + 1] = {
0x8003344,
0x8003344, 0x8003420, 0x80033f4, 0x80033d8,
0x8003328, 0x8003328, 0x8003328, 0x800334c,

1
sys/dev/usb/controller/xhci.h
View File

@ -452,7 +452,6 @@ struct xhci_softc {
struct usb_device *sc_devices[XHCI_MAX_DEVICES];
struct resource *sc_io_res;
int sc_irq_rid;
struct resource *sc_irq_res;
void *sc_intr_hdl;

45
sys/dev/usb/controller/xhci_pci.c
View File

@ -203,21 +203,19 @@ xhci_pci_attach(device_t self)
usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0);
sc->sc_irq_rid = 0;
rid = 0;
if (xhci_use_msi) {
count = pci_msi_count(self);
if (count >= 1) {
count = 1;
if (pci_alloc_msi(self, &count) == 0) {
if (bootverbose)
device_printf(self, "MSI enabled\n");
sc->sc_irq_rid = 1;
}
count = 1;
if (pci_alloc_msi(self, &count) == 0) {
if (bootverbose)
device_printf(self, "MSI enabled\n");
rid = 1;
}
}
sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ,
&sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE);
sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
if (sc->sc_irq_res == NULL) {
pci_release_msi(self);
device_printf(self, "Could not allocate IRQ\n");
/* goto error; FALLTHROUGH - use polling */
}
@ -234,16 +232,22 @@ xhci_pci_attach(device_t self)
err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl);
if (err != 0) {
bus_release_resource(self, SYS_RES_IRQ,
rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
sc->sc_irq_res = NULL;
pci_release_msi(self);
device_printf(self, "Could not setup IRQ, err=%d\n", err);
sc->sc_intr_hdl = NULL;
}
}
if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL ||
xhci_use_polling() != 0) {
device_printf(self, "Interrupt polling at %dHz\n", hz);
USB_BUS_LOCK(&sc->sc_bus);
xhci_interrupt_poll(sc);
USB_BUS_UNLOCK(&sc->sc_bus);
if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) {
if (xhci_use_polling() != 0) {
device_printf(self, "Interrupt polling at %dHz\n", hz);
USB_BUS_LOCK(&sc->sc_bus);
xhci_interrupt_poll(sc);
USB_BUS_UNLOCK(&sc->sc_bus);
} else
goto error;
}
/* On Intel chipsets reroute ports from EHCI to XHCI controller. */
@ -307,11 +311,10 @@ xhci_pci_detach(device_t self)
sc->sc_intr_hdl = NULL;
}
if (sc->sc_irq_res) {
if (sc->sc_irq_rid == 1)
pci_release_msi(self);
bus_release_resource(self, SYS_RES_IRQ, sc->sc_irq_rid,
sc->sc_irq_res);
bus_release_resource(self, SYS_RES_IRQ,
rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
sc->sc_irq_res = NULL;
pci_release_msi(self);
}
if (sc->sc_io_res) {
bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,

11
sys/kern/kern_sysctl.c
View File

@ -174,7 +174,8 @@ sysctl_root_handler_locked(struct sysctl_oid *oid, void *arg1, intptr_t arg2,
int error;
bool xlocked;
atomic_add_int(&oid->oid_running, 1);
if (oid->oid_kind & CTLFLAG_DYN)
atomic_add_int(&oid->oid_running, 1);
xlocked = sysctl_unlock();
if (!(oid->oid_kind & CTLFLAG_MPSAFE))
@ -184,9 +185,11 @@ sysctl_root_handler_locked(struct sysctl_oid *oid, void *arg1, intptr_t arg2,
mtx_unlock(&Giant);
sysctl_lock(xlocked);
if (atomic_fetchadd_int(&oid->oid_running, -1) == 1 &&
(oid->oid_kind & CTLFLAG_DYING) != 0)
wakeup(&oid->oid_running);
if (oid->oid_kind & CTLFLAG_DYN) {
if (atomic_fetchadd_int(&oid->oid_running, -1) == 1 &&
(oid->oid_kind & CTLFLAG_DYING) != 0)
wakeup(&oid->oid_running);
}
return (error);
}

2
sys/modules/dtrace/dtraceall/dtraceall.c
View File

@ -66,7 +66,7 @@ MODULE_VERSION(dtraceall, 1);
MODULE_DEPEND(dtraceall, opensolaris, 1, 1, 1);
MODULE_DEPEND(dtraceall, dtrace, 1, 1, 1);
MODULE_DEPEND(dtraceall, dtmalloc, 1, 1, 1);
#if defined(NFSCLIENT)
#if defined(NFSCL)
MODULE_DEPEND(dtraceall, dtnfscl, 1, 1, 1);
#endif
#if defined(__amd64__) || defined(__i386__) || defined(__powerpc__)