d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Change the way DMA is handled during the command phase. Only test on

Browse Source 
SDONE, not HDONE.

In the data phase dma handler, mask off just the enable bits instead of
clearing the whole register.  Clearing the direction bit could be bad.
Also don't stop a DMA until MREQPEND goes false.  Doing this may cause
an ABORT on the PCI bus although I have yet to see this happen.

Add definitions for MREQPEND and the BRDCTL register.  The BRDCTL register
is used to handle high byte termination and automatic termination testing.
This commit is contained in:
Justin T. Gibbs 1997-01-24 21:57:47 +00:00
parent f42cf36fa8
commit ed69a71305
2 changed files with 30 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
sys/dev/aic7xxx/aic7xxx.seq
View File

@ -505,8 +505,19 @@ p_command:
call set_stcnt_from_hcnt
mvi 0x3d call dma # SCSIEN|SDMAEN|HDMAEN|
# DIRECTION|FIFORESET
mvi DFCNTRL, 0x3d /* SCSIEN|SDMAEN|HDMAEN
* |DIRECTION|FIFORESET
*/
p_command_dma:
test SSTAT0, SDONE jnz p_command_dma_done
test SSTAT1, PHASEMIS jz p_command_dma
test SSTAT0, SDONE jnz p_command_dma_done
clr DFCNTRL
jmp ITloop
p_command_dma_done:
and DFCNTRL, 0xc7 /* ~(SCSIEN|SDMAEN|HDMAEN) */
p_command_dma_clear:
test DFCNTRL, 0x38 jnz p_command_dma_clear
jmp ITloop
/*
@ -929,10 +940,12 @@ dma4:
* actually off first lest we get an ILLSADDR.
*/
dma5:
/* disable DMA, but maintain WIDEODD */
and DFCNTRL,WIDEODD
/* Don't clobber an inprogress host data transfer */
test DFSTATUS, MREQPEND jnz dma5
/* disable DMA */
and DFCNTRL, 0xc7 /* ~(SCSIEN|SDMAEN|HDMAEN|DIRECTION) */
dma6:
test DFCNTRL,0x38 jnz dma6 /* SCSIENACK|SDMAENACK|HDMAENACK */
test DFCNTRL, HDMAENACK jnz dma6
return:
ret

14
sys/dev/aic7xxx/aic7xxx_reg.h
View File

@ -475,6 +475,7 @@
#define FIFORESET 0x01
#define DFSTATUS 0x094
#define MREQPEND 0x10
#define HDONE 0x08
#define FIFOEMP 0x01
@ -527,7 +528,7 @@
#define MK_MESSAGE 0x80
#define DISCENB 0x40
#define TAG_ENB 0x20
#define TRACE_SCB 0x10
#define SPLIT_SG 0x10
#define ABORT_SCB 0x08
#define DISCONNECTED 0x04
#define SCB_TAG_TYPE 0x03
@ -588,6 +589,16 @@
#define DSPCISTATUS 0x086
#define BRDCTL 0x01d
#define BRDDAT7 0x80
#define BRDDAT6 0x40
#define BRDDAT5 0x20
#define BRDSTB 0x10
#define BRDCS 0x08
#define BRDRW 0x04
#define BRDCTL1 0x02
#define BRDCTL0 0x01
/*
* Serial EEPROM Control (p. 4-92 in 7870 Databook)
* Controls the reading and writing of an external serial 1-bit
@ -621,7 +632,6 @@
#define SEECK 0x04
#define SEEDO 0x02
#define SEEDI 0x01
/* ---------------------- Scratch RAM Offsets ------------------------- */
/* These offsets are either to values that are initialized by the board's
* BIOS or are specified by the sequencer code.