MFp4:
- Try hard to calculate a safe sp, so that the stack doesn't get smashed while uncompressing or relocating the kernel. - Bring in code needed to calculate the cacheline size etc, needed for arm9_idcache_wbinv_all.
This commit is contained in:
Olivier Houchard
parent
9464ffd0a4
commit
ee8ecea34b
@ -32,6 +32,7 @@ __FBSDID("$FreeBSD$");
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#include <machine/elf.h>
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#include <machine/pte.h>
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#include <machine/cpufunc.h>
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#include <machine/armreg.h>
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#include <stdlib.h>
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@ -41,6 +42,8 @@ __FBSDID("$FreeBSD$");
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extern char kernel_start[];
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extern char kernel_end[];
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extern void *_end;
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void __start(void);
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#define GZ_HEAD 0xa
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@ -50,7 +53,7 @@ void __start(void);
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#elif defined(CPU_ARM8)
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#define cpu_idcache_wbinv_all arm8_cache_purgeID
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#elif defined(CPU_ARM9)
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#define cpu_idcache_wbinv_all arm9_dcache_wbinv_all
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#define cpu_idcache_wbinv_all arm9_idcache_wbinv_all
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#elif defined(CPU_ARM10)
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#define cpu_idcache_wbinv_all arm10_idcache_wbinv_all
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#elif defined(CPU_SA110) || defined(CPU_SA1110) || defined(CPU_SA1100) || \
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@ -60,8 +63,35 @@ void __start(void);
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defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
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#define cpu_idcache_wbinv_all xscale_cache_purgeID
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#endif
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int arm_pdcache_line_size = 32;
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#ifdef KZIP
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int arm_picache_size;
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int arm_picache_line_size;
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int arm_picache_ways;
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int arm_pdcache_size; /* and unified */
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int arm_pdcache_line_size = 32;
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int arm_pdcache_ways;
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int arm_pcache_type;
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int arm_pcache_unified;
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int arm_dcache_align;
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int arm_dcache_align_mask;
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/* Additional cache information local to this file. Log2 of some of the
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above numbers. */
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static int arm_dcache_l2_nsets;
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static int arm_dcache_l2_assoc;
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static int arm_dcache_l2_linesize;
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int block_userspace_access = 0;
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extern int arm9_dcache_sets_inc;
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extern int arm9_dcache_sets_max;
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extern int arm9_dcache_index_max;
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extern int arm9_dcache_index_inc;
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#endif
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static __inline void *
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memcpy(void *dst, const void *src, int len)
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@ -107,13 +137,18 @@ _start(void)
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{
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int physaddr = KERNPHYSADDR;
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int tmp1;
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unsigned int sp = (unsigned int)&_end;
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#ifdef KZIP
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sp += KERNSIZE + 0x100;
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sp &= ~(L1_TABLE_SIZE - 1);
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sp += 2 * L1_TABLE_SIZE;
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#endif
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sp += 1024 * 1024; /* Should be enough for a stack */
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__asm __volatile("adr %0, 2f\n"
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"bic %0, %0, #0xff000000\n"
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"bic sp, sp, #0xff000000\n"
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"and %1, %1, #0xff000000\n"
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"orr %0, %0, %1\n"
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"orr sp, sp, %1\n"
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"mrc p15, 0, %1, c1, c0, 0\n"
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"bic %1, %1, #1\n" /* Disable MMU */
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"orr %1, %1, #(4 | 8)\n" /* Add DC enable,
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@ -127,11 +162,92 @@ _start(void)
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"nop\n"
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"mov pc, %0\n"
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"2: nop\n"
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: "=r" (tmp1), "+r" (physaddr));
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"mov sp, %2\n"
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: "=r" (tmp1), "+r" (physaddr), "+r" (sp));
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__start();
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}
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#ifdef KZIP
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static void
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get_cachetype_cp15()
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{
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u_int ctype, isize, dsize;
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u_int multiplier;
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__asm __volatile("mrc p15, 0, %0, c0, c0, 1"
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: "=r" (ctype));
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/*
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* ...and thus spake the ARM ARM:
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*
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* If an <opcode2> value corresponding to an unimplemented or
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* reserved ID register is encountered, the System Control
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* processor returns the value of the main ID register.
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*/
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if (ctype == cpufunc_id())
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goto out;
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if ((ctype & CPU_CT_S) == 0)
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arm_pcache_unified = 1;
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/*
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* If you want to know how this code works, go read the ARM ARM.
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*/
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arm_pcache_type = CPU_CT_CTYPE(ctype);
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if (arm_pcache_unified == 0) {
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isize = CPU_CT_ISIZE(ctype);
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multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2;
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arm_picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3);
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if (CPU_CT_xSIZE_ASSOC(isize) == 0) {
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if (isize & CPU_CT_xSIZE_M)
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arm_picache_line_size = 0; /* not present */
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else
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arm_picache_ways = 1;
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} else {
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arm_picache_ways = multiplier <<
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(CPU_CT_xSIZE_ASSOC(isize) - 1);
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}
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arm_picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8);
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}
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dsize = CPU_CT_DSIZE(ctype);
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multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2;
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arm_pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3);
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if (CPU_CT_xSIZE_ASSOC(dsize) == 0) {
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if (dsize & CPU_CT_xSIZE_M)
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arm_pdcache_line_size = 0; /* not present */
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else
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arm_pdcache_ways = 1;
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} else {
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arm_pdcache_ways = multiplier <<
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(CPU_CT_xSIZE_ASSOC(dsize) - 1);
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}
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arm_pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8);
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arm_dcache_align = arm_pdcache_line_size;
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arm_dcache_l2_assoc = CPU_CT_xSIZE_ASSOC(dsize) + multiplier - 2;
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arm_dcache_l2_linesize = CPU_CT_xSIZE_LEN(dsize) + 3;
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arm_dcache_l2_nsets = 6 + CPU_CT_xSIZE_SIZE(dsize) -
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CPU_CT_xSIZE_ASSOC(dsize) - CPU_CT_xSIZE_LEN(dsize);
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out:
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arm_dcache_align_mask = arm_dcache_align - 1;
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}
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static void
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arm9_setup(void)
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{
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get_cachetype_cp15();
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arm9_dcache_sets_inc = 1U << arm_dcache_l2_linesize;
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arm9_dcache_sets_max = (1U << (arm_dcache_l2_linesize +
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arm_dcache_l2_nsets)) - arm9_dcache_sets_inc;
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arm9_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc);
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arm9_dcache_index_max = 0U - arm9_dcache_index_inc;
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}
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static unsigned char *orig_input, *i_input, *i_output;
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@ -354,7 +470,6 @@ load_kernel(unsigned int kstart, unsigned int curaddr,unsigned int func_end,
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extern char func_end[];
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extern void *_end;
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#define PMAP_DOMAIN_KERNEL 15 /*
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* Just define it instead of including the
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@ -404,6 +519,7 @@ __start(void)
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void *curaddr;
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void *dst, *altdst;
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char *kernel = (char *)&kernel_start;
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int sp;
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__asm __volatile("mov %0, pc" :
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"=r" (curaddr));
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@ -413,6 +529,11 @@ __start(void)
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int pt_addr = (((int)&_end + KERNSIZE + 0x100) &
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~(L1_TABLE_SIZE - 1)) + L1_TABLE_SIZE;
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#ifdef CPU_ARM9
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/* So that idcache_wbinv works; */
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if ((cpufunc_id() & 0x0000f000) == 0x00009000)
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arm9_setup();
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#endif
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setup_pagetables(pt_addr, (vm_paddr_t)curaddr,
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(vm_paddr_t)curaddr + 0x10000000);
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/* Gzipped kernel */
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@ -433,10 +554,10 @@ __start(void)
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dst = 4 + load_kernel((unsigned int)&kernel_start,
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(unsigned int)curaddr,
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(unsigned int)&func_end, 0);
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sp = (vm_offset_t)dst + 4096;
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dst = (void *)sp;
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memcpy((void *)dst, (void *)&load_kernel, (unsigned int)&func_end -
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(unsigned int)&load_kernel);
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((void (*)())dst)((unsigned int)kernel,
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(unsigned int)curaddr,
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dst + (unsigned int)(&func_end) -
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(unsigned int)(&load_kernel), 1);
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do_call(dst, kernel, dst + (unsigned int)(&func_end) -
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(unsigned int)(&load_kernel), sp);
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}
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@ -26,6 +26,14 @@
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$")
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ENTRY(do_call)
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mov r6, r0
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mov r0, r1
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ldr r1, =0xfff00000
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and r1, pc, r1
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mov sp, r3
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mov r3, #1
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mov pc, r6
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.section ".real_kernel","aw"
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.globl kernel_start;
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kernel_start:
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@ -62,7 +62,7 @@ SYSTEM_LD_TAIL +=;sed s/" + SIZEOF_HEADERS"// ldscript.$M\
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FILES_CPU_FUNC = $S/$M/$M/cpufunc_asm_arm7tdmi.S \
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$S/$M/$M/cpufunc_asm_arm8.S $S/$M/$M/cpufunc_asm_arm9.S \
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$S/$M/$M/cpufunc_asm_sa1.S $S/$M/$M/cpufunc_asm_arm10.S \
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$S/$M/$M/cpufunc_asm_xscale.S
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$S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S
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trampoline: ${KERNEL_KO}.tramp
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${KERNEL_KO}.tramp: ${KERNEL_KO}
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echo "#define KERNNAME \"${KERNEL_KO}.tmp\"" >opt_kernname.h
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@ -71,6 +71,8 @@ ${KERNEL_KO}.tramp: ${KERNEL_KO}
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ldscript.$M.tramp.noheader
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${OBJCOPY} --strip-symbol '$$d' --strip-symbol '$$a' \
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-g --strip-symbol '$$t' ${FULLKERNEL} ${KERNEL_KO}.tmp
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eval $$(stat -s ${KERNEL_KO}.tmp) && \
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echo "#define KERNSIZE $$st_size" >>opt_kernname.h
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${CC} -O -nostdlib -I. -Xlinker -T -Xlinker ldscript.$M.tramp \
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$S/$M/$M/elf_trampoline.c $S/$M/$M/inckern.S -o ${KERNEL_KO}.tramp
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${CC} -O -nostdlib -I. -Xlinker -T -Xlinker ldscript.$M.tramp.noheader \
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