bce: clean up empty lines in .c and .h files
This commit is contained in:
Mateusz Guzik
parent
a62d779028
commit
eef5873fc1
File diff suppressed because it is too large
Load Diff
@ -1256,7 +1256,6 @@ const u32 bce_COM_b06FwBss[(0xc4/4) + 1] = { 0x0 };
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const u32 bce_COM_b06FwSbss[(0x38/4) + 1] = { 0x0 };
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const u32 bce_COM_b06FwSdata[(0x0/4) + 1] = { 0x0 };
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int bce_RXP_b06FwReleaseMajor = 0x6;
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int bce_RXP_b06FwReleaseMinor = 0x0;
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int bce_RXP_b06FwReleaseFix = 0xf;
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@ -3122,7 +3121,6 @@ const u32 bce_RXP_b06FwBss[(0x440/4) + 1] = { 0x0 };
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const u32 bce_RXP_b06FwSbss[(0x4c/4) + 1] = { 0x0 };
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const u32 bce_RXP_b06FwSdata[(0x0/4) + 1] = { 0x0 };
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int bce_TPAT_b06FwReleaseMajor = 0x6;
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int bce_TPAT_b06FwReleaseMinor = 0x0;
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int bce_TPAT_b06FwReleaseFix = 0xf;
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@ -3528,7 +3526,6 @@ const u32 bce_TPAT_b06FwBss[(0x450/4) + 1] = { 0x0 };
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const u32 bce_TPAT_b06FwSbss[(0x44/4) + 1] = { 0x0 };
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const u32 bce_TPAT_b06FwSdata[(0x0/4) + 1] = { 0x0 };
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int bce_TXP_b06FwReleaseMajor = 0x6;
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int bce_TXP_b06FwReleaseMinor = 0x0;
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int bce_TXP_b06FwReleaseFix = 0xf;
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@ -4513,7 +4510,6 @@ const u32 bce_TXP_b06FwBss[(0x14c/4) + 1] = { 0x0 };
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const u32 bce_TXP_b06FwSbss[(0x68/4) + 1] = { 0x0 };
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const u32 bce_TXP_b06FwSdata[(0x0/4) + 1] = { 0x0 };
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int bce_CP_b06FwReleaseMajor = 0x6;
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int bce_CP_b06FwReleaseMinor = 0x0;
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int bce_CP_b06FwReleaseFix = 0xf;
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@ -5953,7 +5949,6 @@ const u32 bce_CP_b06FwBss[(0x5d8/4) + 1] = { 0x0 };
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const u32 bce_CP_b06FwSbss[(0xf1/4) + 1] = { 0x0 };
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const u32 bce_CP_b06FwSdata[(0x0/4) + 1] = { 0x0 };
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const u32 bce_rv2p_proc1[] = {
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0x00000010, 0xb1800006,
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0x0000001f, 0x0106000f,
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@ -6244,7 +6239,6 @@ const u32 bce_rv2p_proc1[] = {
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0x00000018, 0x8000feed,
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};
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u32 bce_rv2p_proc2[] = {
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0x00000010, 0xb1800004,
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0x0000001f, 0x0106000f,
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@ -6662,7 +6656,6 @@ u32 bce_rv2p_proc2[] = {
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0x00000018, 0x8000fe68,
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};
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int bce_TXP_b09FwReleaseMajor = 0x6;
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int bce_TXP_b09FwReleaseMinor = 0x0;
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int bce_TXP_b09FwReleaseFix = 0x11;
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@ -7669,7 +7662,6 @@ const u32 bce_TXP_b09FwBss[(0x24c/4) + 1] = { 0x0 };
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const u32 bce_TXP_b09FwSbss[(0x64/4) + 1] = { 0x0 };
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const u32 bce_TXP_b09FwSdata[(0x0/4) + 1] = { 0x0 };
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int bce_TPAT_b09FwReleaseMajor = 0x6;
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int bce_TPAT_b09FwReleaseMinor = 0x0;
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int bce_TPAT_b09FwReleaseFix = 0x11;
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@ -7999,7 +7991,6 @@ const u32 bce_TPAT_b09FwBss[(0x12b4/4) + 1] = { 0x0 };
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const u32 bce_TPAT_b09FwSbss[(0x3c/4) + 1] = { 0x0 };
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const u32 bce_TPAT_b09FwSdata[(0x0/4) + 1] = { 0x0 };
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int bce_COM_b09FwReleaseMajor = 0x6;
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int bce_COM_b09FwReleaseMinor = 0x0;
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int bce_COM_b09FwReleaseFix = 0x11;
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@ -9397,7 +9388,6 @@ const u32 bce_COM_b09FwBss[(0x11c/4) + 1] = { 0x0 };
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const u32 bce_COM_b09FwSbss[(0x30/4) + 1] = { 0x0 };
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const u32 bce_COM_b09FwSdata[(0x0/4) + 1] = { 0x0 };
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int bce_RXP_b09FwReleaseMajor = 0x6;
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int bce_RXP_b09FwReleaseMinor = 0x0;
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int bce_RXP_b09FwReleaseFix = 0x11;
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@ -11788,7 +11778,6 @@ const u32 bce_RXP_b09FwBss[(0x1bc/4) + 1] = { 0x0 };
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const u32 bce_RXP_b09FwSbss[(0x78/4) + 1] = { 0x0 };
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const u32 bce_RXP_b09FwSdata[(0x0/4) + 1] = { 0x0 };
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int bce_CP_b09FwReleaseMajor = 0x6;
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int bce_CP_b09FwReleaseMinor = 0x0;
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int bce_CP_b09FwReleaseFix = 0x11;
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@ -13247,7 +13236,6 @@ const u32 bce_CP_b09FwBss[(0x19c/4) + 1] = { 0x0 };
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const u32 bce_CP_b09FwSbss[(0xa8/4) + 1] = { 0x0 };
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const u32 bce_CP_b09FwSdata[(0x0/4) + 1] = { 0x0 };
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const u32 bce_xi_rv2p_proc1[] = {
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0x00000010, 0xb1800006,
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0x0000001f, 0x05060011,
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@ -13538,7 +13526,6 @@ const u32 bce_xi_rv2p_proc1[] = {
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0x00000018, 0x8000feed,
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};
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const u32 bce_xi_rv2p_proc2[] = {
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0x00000010, 0xb1800004,
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0x0000001f, 0x05060011,
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@ -14007,7 +13994,6 @@ const u32 bce_xi_rv2p_proc2[] = {
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0x00000018, 0x8000fe35,
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};
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const u32 bce_xi90_rv2p_proc1[] = {
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0x00000010, 0xb1800006,
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0x0000001f, 0x03060011,
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@ -14313,7 +14299,6 @@ const u32 bce_xi90_rv2p_proc1[] = {
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0x00000018, 0x8000fede,
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};
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const u32 bce_xi90_rv2p_proc2[] = {
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0x00000010, 0xb1800004,
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0x0000001f, 0x03060011,
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@ -14831,7 +14816,6 @@ const u32 bce_xi90_rv2p_proc2[] = {
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0x00000018, 0x8000fe04,
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};
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/*
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* The RV2P block must be configured for the system
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* page size, or more specifically, the number of
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@ -489,7 +489,6 @@ default: DBPRINT(sc, BCE_INSANE_PHY, \
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#endif /* BCE_DEBUG */
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/****************************************************************************/
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/* Device identification definitions. */
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/****************************************************************************/
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@ -542,7 +541,6 @@ default: DBPRINT(sc, BCE_INSANE_PHY, \
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/* A serdes chip will have the first bit of the bond id set. */
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#define BCE_CHIP_BOND_ID_SERDES_BIT 0x01
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/* shorthand one */
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#define BCE_ASICREV(x) ((x) >> 28)
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#define BCE_ASICREV_BCM5700 0x06
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@ -639,7 +637,6 @@ struct flash_spec {
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const u8 *name;
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};
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/****************************************************************************/
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/* Shared Memory layout */
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/* The BCE bootcode will initialize this data area with port configurtion */
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@ -662,7 +659,6 @@ struct flash_spec {
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*/
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#define FW_ACK_TIME_OUT_MS 1000
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#define BCE_DRV_RESET_SIGNATURE 0x00000000
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#define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
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@ -1042,7 +1038,6 @@ struct flash_spec {
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*/
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#define BCE_PCI_PCIX_CMD 0x42
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/****************************************************************************/
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/* Convenience definitions. */
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/****************************************************************************/
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@ -1093,7 +1088,6 @@ struct flash_spec {
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#define BCE_ADDR_HI(y) (0)
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#endif
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/****************************************************************************/
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/* Do not modify any of the following data structures, they are generated */
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/* from RTL code. */
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@ -1124,7 +1118,6 @@ struct tx_bd {
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u16 tx_bd_vlan_tag;
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};
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/*
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* rx_bd definition
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*/
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@ -1139,7 +1132,6 @@ struct rx_bd {
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#define RX_BD_FLAGS_START (1<<3)
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};
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/*
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* status_block definition
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*/
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@ -1229,7 +1221,6 @@ struct status_block {
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#endif
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};
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/*
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* statistics_block definition
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*/
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@ -1316,7 +1307,6 @@ struct statistics_block {
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u32 stat_GenStat15;
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};
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/*
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* l2_fhdr definition
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*/
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@ -1392,7 +1382,6 @@ struct l2_fhdr {
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"\02RULE_b1" \
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"\01RULE_b0"
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/*
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* l2_tx_context definition (5706 and 5708)
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*/
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@ -1439,7 +1428,6 @@ struct l2_fhdr {
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#define BCE_L2CTX_TX_TBDR_BHADDR_HI_XI 0x00000258
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#define BCE_L2CTX_TX_TBDR_BHADDR_LO_XI 0x0000025c
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/*
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* l2_rx_context definition (5706, 5708, 5709, and 5716)
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*/
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@ -1482,7 +1470,6 @@ struct l2_fhdr {
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#define BCE_L2CTX_RX_NX_PG_BDHADDR_LO 0x00000054
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#define BCE_L2CTX_RX_NX_PG_BDIDX 0x00000058
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/*
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* l2_mq definitions (5706, 5708, 5709, and 5716)
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*/
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@ -1566,7 +1553,6 @@ struct l2_fhdr {
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#define BCE_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
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#define BCE_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
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/*
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* pci_reg definition
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* offset: 0x400
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@ -1748,7 +1734,6 @@ struct l2_fhdr {
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#define BCE_PCI_MSI_ADDR_H 0x00000454
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#define BCE_PCI_MSI_ADDR_L 0x00000458
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/*
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* misc_reg definition
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* offset: 0x800
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@ -2784,7 +2769,6 @@ struct l2_fhdr {
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#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2L<<10)
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#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3L<<10)
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/*
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* dma_reg definition
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* offset: 0xc00
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@ -2993,7 +2977,6 @@ struct l2_fhdr {
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#define BCE_DMA_FUSE_CTRL2_DATA 0x00000f14
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/*
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* context_reg definition
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* offset: 0x1000
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@ -3178,7 +3161,6 @@ struct l2_fhdr {
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#define BCE_CTX_CAM_CTRL_WRITE_REQ (1L<<30)
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#define BCE_CTX_CAM_CTRL_READ_REQ (1L<<31)
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/*
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* emac_reg definition
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* offset: 0x1400
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@ -3673,7 +3655,6 @@ struct l2_fhdr {
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#define BCE_EMAC_TX_STAT_AC21 0x000016d4
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#define BCE_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
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/*
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* rpm_reg definition
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* offset: 0x1800
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@ -4041,7 +4022,6 @@ struct l2_fhdr {
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#define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8
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#define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc
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/*
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* rlup_reg definition
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* offset: 0x2000
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@ -4051,7 +4031,6 @@ struct l2_fhdr {
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#define BCE_RLUP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
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#define BCE_RLUP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
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/*
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* rv2pcsr_reg definition
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* offset: 0x2400
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@ -4061,7 +4040,6 @@ struct l2_fhdr {
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#define BCE_RV2PCSR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
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#define BCE_RV2PCSR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
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/*
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* rdma_reg definition
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* offset: 0x2c00
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@ -4071,8 +4049,6 @@ struct l2_fhdr {
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#define BCE_RDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
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#define BCE_RDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
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/*
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* timer_reg definition
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* offset: 0x4400
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@ -4092,7 +4068,6 @@ struct l2_fhdr {
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#define BCE_TIMER_25MHZ_FREE_RUN 0x00004448
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/*
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* tsch_reg definition
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* offset: 0x4c00
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@ -4103,8 +4078,6 @@ struct l2_fhdr {
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#define BCE_TSCH_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
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#define BCE_TSCH_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
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/*
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* rbuf_reg definition
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* offset: 0x200000
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@ -4152,7 +4125,6 @@ struct l2_fhdr {
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#define BCE_RBUF_CLIST_DATA 0x00210000
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#define BCE_RBUF_BUF_DATA 0x00220000
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/*
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* rv2p_reg definition
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* offset: 0x2800
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@ -4308,7 +4280,6 @@ struct l2_fhdr {
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#define BCE_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
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#define BCE_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
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/*
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* mq_reg definition
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* offset: 0x3c00
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@ -4427,7 +4398,6 @@ struct l2_fhdr {
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#define BCE_MQ_MAP_L2_5_ENA (0x1L<<31)
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#define BCE_MQ_MAP_L2_5_DEFAULT 0x83000b08
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/*
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* csch_reg definition
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* offset: 0x4000
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@ -4438,7 +4408,6 @@ struct l2_fhdr {
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#define BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
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#define BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
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/*
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* tbdr_reg definition
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* offset: 0x5000
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@ -4506,7 +4475,6 @@ struct l2_fhdr {
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#define BCE_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
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#define BCE_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
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/*
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* tdma_reg definition
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* offset: 0x5c00
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@ -4596,7 +4564,6 @@ struct l2_fhdr {
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#define BCE_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
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#define BCE_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
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/*
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* nvm_reg definition
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* offset: 0x6400
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@ -4701,7 +4668,6 @@ struct l2_fhdr {
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#define BCE_NVM_WRITE1_WRDI_CMD (0xffL<<8)
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#define BCE_NVM_WRITE1_SR_DATA (0xffL<<16)
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/*
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* hc_reg definition
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* offset: 0x6800
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@ -5485,7 +5451,6 @@ struct l2_fhdr {
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#define BCE_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffL<<0)
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#define BCE_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffL<<16)
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/*
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* txp_reg definition
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* offset: 0x40000
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@ -5566,7 +5531,6 @@ struct l2_fhdr {
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#define BCE_TXP_SCRATCH 0x00060000
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/*
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* tpat_reg definition
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* offset: 0x80000
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@ -5646,7 +5610,6 @@ struct l2_fhdr {
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#define BCE_TPAT_SCRATCH 0x000a0000
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/*
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* rxp_reg definition
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* offset: 0xc0000
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@ -5748,7 +5711,6 @@ struct l2_fhdr {
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#define BCE_RXP_SCRATCH 0x000e0000
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/*
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* com_reg definition
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* offset: 0x100000
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@ -5871,7 +5833,6 @@ struct l2_fhdr {
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#define BCE_COM_SCRATCH 0x00120000
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/*
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* cp_reg definition
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* offset: 0x180000
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@ -5952,7 +5913,6 @@ struct l2_fhdr {
|
||||
|
||||
#define BCE_CP_SCRATCH 0x001a0000
|
||||
|
||||
|
||||
/*
|
||||
* tas_reg definition
|
||||
* offset: 0x1c0000
|
||||
@ -5962,7 +5922,6 @@ struct l2_fhdr {
|
||||
#define BCE_TAS_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
|
||||
#define BCE_TAS_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
|
||||
|
||||
|
||||
/*
|
||||
* mcp_reg definition
|
||||
* offset: 0x140000
|
||||
|
||||
Loading…
Reference in New Issue
Block a user