Implement enough of an uart driver to get serial console working.
This commit is contained in:
cognet
parent
a2d6663b8d
commit
f041eed5b0
@ -6,6 +6,6 @@ arm/sa11x0/sa11x0_io.c optional saip
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arm/sa11x0/sa11x0_io_asm.S optional saip
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arm/sa11x0/sa11x0_irq.S optional saip
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arm/sa11x0/sa11x0_irqhandler.c optional saip
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dev/uart/uart_cpu_sa1110.c optional uart saip
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dev/uart/uart_dev_sa1110.c optional uart saip
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dev/uart/uart_bus_sa1110.c optional uart saip
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arm/sa11x0/uart_cpu_sa1110.c optional uart saip
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arm/sa11x0/uart_dev_sa1110.c optional uart saip
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arm/sa11x0/uart_bus_sa1110.c optional uart saip
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78
sys/arm/sa11x0/uart_bus_sa1110.c
Normal file
78
sys/arm/sa11x0/uart_bus_sa1110.c
Normal file
@ -0,0 +1,78 @@
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/*
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* Copyright (c) 2004 Olivier Houchard. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#include <dev/pci/pcivar.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_bus.h>
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#include <dev/uart/uart_cpu.h>
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#include <arm/sa11x0/uart_dev_sa1110.h>
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#include "uart_if.h"
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static int uart_sa1110_probe(device_t dev);
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static device_method_t uart_sa1110_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, uart_sa1110_probe),
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DEVMETHOD(device_attach, uart_bus_attach),
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DEVMETHOD(device_detach, uart_bus_detach),
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{ 0, 0 }
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};
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static driver_t uart_sa1110_driver = {
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uart_driver_name,
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uart_sa1110_methods,
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sizeof(struct uart_softc),
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};
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extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
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static int
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uart_sa1110_probe(device_t dev)
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{
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struct uart_softc *sc;
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sc = device_get_softc(dev);
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sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
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sc->sc_class = &uart_sa1110_class;
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bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
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return(uart_bus_probe(dev, 0, 0, 0, 0));
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return (0);
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}
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DRIVER_MODULE(uart, saip, uart_sa1110_driver, uart_devclass, 0, 0);
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68
sys/arm/sa11x0/uart_cpu_sa1110.c
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68
sys/arm/sa11x0/uart_cpu_sa1110.c
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@ -0,0 +1,68 @@
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/*
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* Copyright (c) 2003 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cons.h>
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#include <machine/bus.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <arm/sa11x0/sa11x0_var.h>
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bus_space_tag_t uart_bus_space_io;
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bus_space_tag_t uart_bus_space_mem;
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int
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uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
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{
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return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
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}
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extern int got_mmu;
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int
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uart_cpu_getdev(int devtype, struct uart_devinfo *di)
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{
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di->ops = uart_sa1110_ops;
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di->bas.chan = 0;
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di->bas.bst = &sa11x0_bs_tag;
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di->bas.bsh = 0x80010000;
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di->bas.regshft = 0;
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di->bas.rclk = 0;
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di->baudrate = 9600;
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di->databits = 8;
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di->stopbits = 1;
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di->parity = UART_PARITY_NONE;
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uart_bus_space_io = &sa11x0_bs_tag;
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uart_bus_space_mem = NULL;
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return (0);
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}
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307
sys/arm/sa11x0/uart_dev_sa1110.c
Normal file
307
sys/arm/sa11x0/uart_dev_sa1110.c
Normal file
@ -0,0 +1,307 @@
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/*
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* Copyright (c) 2003 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/cons.h>
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#include <sys/tty.h>
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#include <machine/bus.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include <arm/sa11x0/uart_dev_sa1110.h>
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#include "uart_if.h"
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#define DEFAULT_RCLK 3686400
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extern int got_mmu;
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/*
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* Low-level UART interface.
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*/
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static int sa1110_probe(struct uart_bas *bas);
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static void sa1110_init(struct uart_bas *bas, int, int, int, int);
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static void sa1110_term(struct uart_bas *bas);
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static void sa1110_putc(struct uart_bas *bas, int);
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static int sa1110_poll(struct uart_bas *bas);
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static int sa1110_getc(struct uart_bas *bas);
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int did_mmu = 0;
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extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
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struct uart_ops uart_sa1110_ops = {
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.probe = sa1110_probe,
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.init = sa1110_init,
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.term = sa1110_term,
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.putc = sa1110_putc,
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.poll = sa1110_poll,
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.getc = sa1110_getc,
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};
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static int
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sa1110_probe(struct uart_bas *bas)
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{
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return (0);
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}
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static void
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sa1110_addr_change(struct uart_bas *bas)
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{
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bas->bsh = 0xd000d000;
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did_mmu = 1;
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}
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static void
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sa1110_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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int brd;
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/* XXX: sigh. */
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if (!did_mmu && got_mmu)
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sa1110_addr_change(bas);
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if (bas->rclk == 0)
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bas->rclk = DEFAULT_RCLK;
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while (uart_getreg(bas, SACOM_SR1) & SR1_TBY);
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uart_setreg(bas, SACOM_CR3, 0);
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brd = SACOMSPEED(baudrate);
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uart_setreg(bas, SACOM_CR1, brd >> 8);
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uart_setreg(bas, SACOM_CR2, brd & 0xff);
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uart_setreg(bas, SACOM_CR3, CR3_RXE | CR3_TXE);
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}
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static void
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sa1110_term(struct uart_bas *bas)
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{
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/* XXX */
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}
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static void
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sa1110_putc(struct uart_bas *bas, int c)
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{
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/* XXX: sigh. */
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if (!did_mmu && got_mmu)
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sa1110_addr_change(bas);
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while (!uart_getreg(bas, SACOM_SR1) & SR1_TNF);
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uart_setreg(bas, SACOM_DR, c);
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}
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static int
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sa1110_poll(struct uart_bas *bas)
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{
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/* XXX: sigh. */
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if (!did_mmu && got_mmu)
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sa1110_addr_change(bas);
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if (!(uart_getreg(bas, SACOM_SR1) & SR1_RNE))
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return (-1);
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return (uart_getreg(bas, SACOM_DR) & 0xff);
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}
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static int
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sa1110_getc(struct uart_bas *bas)
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{
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int c;
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/* XXX: sigh. */
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if (!did_mmu && got_mmu)
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sa1110_addr_change(bas);
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while (!(uart_getreg(bas, SACOM_SR1) & SR1_RNE)) {
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u_int32_t sr0;
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sr0 = uart_getreg(bas, SACOM_SR0);
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if (ISSET(sr0, SR0_RBB))
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uart_setreg(bas, SACOM_SR0, SR0_RBB);
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if (ISSET(sr0, SR0_REB))
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uart_setreg(bas, SACOM_SR0, SR0_REB);
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}
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c = uart_getreg(bas, SACOM_DR);
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c &= 0xff;
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return (c);
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}
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static int sa1110_bus_probe(struct uart_softc *sc);
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static int sa1110_bus_attach(struct uart_softc *sc);
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static int sa1110_bus_flush(struct uart_softc *, int);
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static int sa1110_bus_getsig(struct uart_softc *);
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static int sa1110_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int sa1110_bus_ipend(struct uart_softc *);
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static int sa1110_bus_param(struct uart_softc *, int, int, int, int);
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static int sa1110_bus_receive(struct uart_softc *);
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static int sa1110_bus_setsig(struct uart_softc *, int);
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static int sa1110_bus_transmit(struct uart_softc *);
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static kobj_method_t sa1110_methods[] = {
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KOBJMETHOD(uart_probe, sa1110_bus_probe),
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KOBJMETHOD(uart_attach, sa1110_bus_attach),
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KOBJMETHOD(uart_flush, sa1110_bus_flush),
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KOBJMETHOD(uart_getsig, sa1110_bus_getsig),
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KOBJMETHOD(uart_ioctl, sa1110_bus_ioctl),
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KOBJMETHOD(uart_ipend, sa1110_bus_ipend),
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KOBJMETHOD(uart_param, sa1110_bus_param),
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KOBJMETHOD(uart_receive, sa1110_bus_receive),
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KOBJMETHOD(uart_setsig, sa1110_bus_setsig),
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KOBJMETHOD(uart_transmit, sa1110_bus_transmit),
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{0, 0 }
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};
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int
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sa1110_bus_probe(struct uart_softc *sc)
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{
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return (0);
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}
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static int
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sa1110_bus_attach(struct uart_softc *sc)
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{
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bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
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sc->sc_txfifosz = 3;
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sc->sc_rxfifosz = 1;
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sc->sc_hwiflow = 0;
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uart_setreg(&sc->sc_bas, SACOM_CR3, CR3_RXE | CR3_TXE | CR3_RIE | CR3_TIE);
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return (0);
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}
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static int
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sa1110_bus_transmit(struct uart_softc *sc)
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{
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int i;
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#if 0
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int sr = uart_getreg(&sc->sc_bas, SACOM_SR0);
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while (!(uart_getreg(&sc->sc_bas, SACOM_CR3) & CR3_TIE))
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uart_setreg(&sc->sc_bas, SACOM_CR3,
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uart_getreg(&sc->sc_bas, SACOM_CR3) | CR3_TIE);
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#endif
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sc->sc_txbusy = 1;
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uart_setreg(&sc->sc_bas, SACOM_CR3, uart_getreg(&sc->sc_bas, SACOM_CR3)
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| CR3_TIE);
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for (i = 0; i < sc->sc_txdatasz; i++) {
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while (!uart_getreg(&sc->sc_bas, SACOM_SR1) & SR1_TNF);
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uart_setreg(&sc->sc_bas, SACOM_DR, sc->sc_txbuf[i]);
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uart_barrier(&sc->sc_bas);
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}
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#if 0
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sr = uart_getreg(&sc->sc_bas, SACOM_SR0);
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#endif
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return (0);
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}
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static int
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sa1110_bus_setsig(struct uart_softc *sc, int sig)
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{
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return (0);
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}
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static int
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sa1110_bus_receive(struct uart_softc *sc)
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{
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#if 0
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while (!(uart_getreg(&sc->sc_bas, SACOM_SR1) & SR1_RNE)) {
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u_int32_t sr0;
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sr0 = uart_getreg(&sc->sc_bas, SACOM_SR0);
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if (ISSET(sr0, SR0_RBB))
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uart_setreg(&sc->sc_bas, SACOM_SR0, SR0_RBB);
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if (ISSET(sr0, SR0_REB))
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uart_setreg(&sc->sc_bas, SACOM_SR0, SR0_REB);
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}
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#endif
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uart_setreg(&sc->sc_bas, SACOM_CR3, uart_getreg(&sc->sc_bas, SACOM_CR3)
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| CR3_RIE);
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uart_rx_put(sc, uart_getreg(&sc->sc_bas, SACOM_DR));
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return (0);
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}
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static int
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sa1110_bus_param(struct uart_softc *sc, int baudrate, int databits,
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int stopbits, int parity)
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{
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int brd;
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if (baudrate > 0) {
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brd = SACOMSPEED(baudrate);
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uart_setreg(&sc->sc_bas, SACOM_CR1, brd >> 8);
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uart_setreg(&sc->sc_bas, SACOM_CR2, brd & 0xff);
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}
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return (0);
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}
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static int
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sa1110_bus_ipend(struct uart_softc *sc)
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{
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int sr = uart_getreg(&sc->sc_bas, SACOM_SR0);
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int ipend = 0;
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int mask = CR3_RIE | CR3_TIE;
|
||||
if (sr & 1) {
|
||||
if (uart_getreg(&sc->sc_bas, SACOM_CR3) & CR3_TIE)
|
||||
ipend |= UART_IPEND_TXIDLE;
|
||||
mask &= ~CR3_TIE;
|
||||
}
|
||||
if (sr & 4) {
|
||||
if (uart_getreg(&sc->sc_bas, SACOM_CR3) & CR3_RIE)
|
||||
ipend |= UART_IPEND_RXREADY;
|
||||
mask &= ~CR3_RIE;
|
||||
}
|
||||
uart_setreg(&sc->sc_bas, SACOM_CR3, CR3_RXE | mask);
|
||||
return (ipend);
|
||||
}
|
||||
static int
|
||||
sa1110_bus_flush(struct uart_softc *sc, int what)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
sa1110_bus_getsig(struct uart_softc *sc)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
sa1110_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
|
||||
{
|
||||
return (EINVAL);
|
||||
}
|
||||
struct uart_class uart_sa1110_class = {
|
||||
"sa1110 class",
|
||||
sa1110_methods,
|
||||
1,
|
||||
.uc_range = 8,
|
||||
.uc_rclk = 3686400
|
||||
};
|
||||
83
sys/arm/sa11x0/uart_dev_sa1110.h
Normal file
83
sys/arm/sa11x0/uart_dev_sa1110.h
Normal file
@ -0,0 +1,83 @@
|
||||
/*
|
||||
* Copyright (c) 2003 Marcel Moolenaar
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _DEV_UART_DEV_SA1110_H_
|
||||
#define _DEV_UART_DEV_SA1110_H_
|
||||
|
||||
#define SACOM_FREQ (3686400 / 16)
|
||||
#define SACOMSPEED(b) (SACOM_FREQ / (b) - 1)
|
||||
|
||||
/* UART control register 0 */
|
||||
#define SACOM_CR0 0x00
|
||||
#define CR0_PE 0x01 /* Parity enable */
|
||||
#define CR0_OES 0x02 /* Odd/even parity select */
|
||||
#define CR0_SBS 0x04 /* Stop bit select */
|
||||
#define CR0_DSS 0x08 /* Data size select */
|
||||
#define CR0_SCE 0x10 /* Sample clock enable */
|
||||
#define CR0_RCE 0x20 /* Receive clock edge enable */
|
||||
#define CR0_TCE 0x40 /* Transmit clock edge enable */
|
||||
|
||||
/* UART control register 1 and 2 - baud rate divisor */
|
||||
#define SACOM_CR1 0x04
|
||||
#define SACOM_CR2 0x08
|
||||
|
||||
/* UART control register 3 */
|
||||
#define SACOM_CR3 0x0C
|
||||
#define CR3_RXE 0x01 /* Receiver enable */
|
||||
#define CR3_TXE 0x02 /* Transmitter enable */
|
||||
#define CR3_BRK 0x04 /* Break */
|
||||
#define CR3_RIE 0x08 /* Receive FIFO interrupt enable */
|
||||
#define CR3_TIE 0x10 /* Transmit FIFO interrupt enable */
|
||||
#define CR3_LBM 0x20 /* Loopback mode */
|
||||
|
||||
/* UART data register */
|
||||
#define SACOM_DR 0x14
|
||||
#define DR_PRE 0x100 /* Parity error */
|
||||
#define DR_FRE 0x200 /* Framing error */
|
||||
#define DR_ROR 0x400 /* Receiver overrun */
|
||||
|
||||
/* UART status register 0 */
|
||||
#define SACOM_SR0 0x1C
|
||||
#define SR0_TFS 0x01 /* Transmit FIFO service request */
|
||||
#define SR0_RFS 0x02 /* Receive FIFO service request */
|
||||
#define SR0_RID 0x04 /* Receiver idle */
|
||||
#define SR0_RBB 0x08 /* Receiver begin of break */
|
||||
#define SR0_REB 0x10 /* Receiver end of break */
|
||||
#define SR0_EIF 0x20 /* Error in FIFO */
|
||||
|
||||
/* UART status register 1 */
|
||||
#define SACOM_SR1 0x20
|
||||
#define SR1_TBY 0x01 /* Transmitter busy */
|
||||
#define SR1_RNE 0x02 /* Receive FIFO not empty */
|
||||
#define SR1_TNF 0x04 /* Transmit FIFO not full */
|
||||
#define SR1_PRE 0x08 /* Parity error */
|
||||
#define SR1_FRE 0x10 /* Framing error */
|
||||
#define SR1_ROR 0x20 /* Receive FIFO overrun */
|
||||
|
||||
#define ISSET(a, b) ((a) & (b))
|
||||
#endif
|
||||
Loading…
x
Reference in New Issue
Block a user